1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, u16 vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 393 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 394 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 395 } 396 397 /* reg_sfd_uc_lag_sub_port 398 * LAG sub port. 399 * Must be 0 if multichannel VEPA is not enabled. 400 * Access: RW 401 */ 402 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 403 MLXSW_REG_SFD_REC_LEN, 0x08, false); 404 405 /* reg_sfd_uc_lag_set_vid 406 * Set VID. 407 * 0 - Do not update VID. 408 * 1 - Set VID. 409 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 410 * Access: RW 411 * 412 * Note: Reserved when legacy bridge model is used. 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_lag_fid_vid 418 * Filtering ID or VLAN ID 419 * For SwitchX and SwitchX-2: 420 * - Dynamic entries (policy 2,3) use FID 421 * - Static entries (policy 0) use VID 422 * - When independent learning is configured, VID=FID 423 * For Spectrum: use FID for both Dynamic and Static entries. 424 * VID should not be used. 425 * Access: Index 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x08, false); 429 430 /* reg_sfd_uc_lag_lag_vid 431 * New vlan ID. 432 * Access: RW 433 * 434 * Note: Reserved when legacy bridge model is used and set_vid=0. 435 */ 436 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 437 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 438 439 /* reg_sfd_uc_lag_lag_id 440 * LAG Identifier - pointer into the LAG descriptor table. 441 * Access: RW 442 */ 443 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 444 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 445 446 static inline void 447 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 448 enum mlxsw_reg_sfd_rec_policy policy, 449 const char *mac, u16 fid_vid, 450 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 451 u16 lag_id) 452 { 453 mlxsw_reg_sfd_rec_pack(payload, rec_index, 454 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 455 mac, action); 456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 457 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 458 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 459 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 460 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 461 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 462 } 463 464 /* reg_sfd_mc_pgi 465 * 466 * Multicast port group index - index into the port group table. 467 * Value 0x1FFF indicates the pgi should point to the MID entry. 468 * For Spectrum this value must be set to 0x1FFF 469 * Access: RW 470 */ 471 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 472 MLXSW_REG_SFD_REC_LEN, 0x08, false); 473 474 /* reg_sfd_mc_fid_vid 475 * 476 * Filtering ID or VLAN ID 477 * Access: Index 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x08, false); 481 482 /* reg_sfd_mc_mid 483 * 484 * Multicast identifier - global identifier that represents the multicast 485 * group across all devices. 486 * Access: RW 487 */ 488 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 489 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 490 491 static inline void 492 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 493 const char *mac, u16 fid_vid, 494 enum mlxsw_reg_sfd_rec_action action, u16 mid) 495 { 496 mlxsw_reg_sfd_rec_pack(payload, rec_index, 497 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 498 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 499 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 500 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 501 } 502 503 /* reg_sfd_uc_tunnel_uip_msb 504 * When protocol is IPv4, the most significant byte of the underlay IPv4 505 * destination IP. 506 * When protocol is IPv6, reserved. 507 * Access: RW 508 */ 509 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 510 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 511 512 /* reg_sfd_uc_tunnel_fid 513 * Filtering ID. 514 * Access: Index 515 */ 516 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 517 MLXSW_REG_SFD_REC_LEN, 0x08, false); 518 519 enum mlxsw_reg_sfd_uc_tunnel_protocol { 520 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 521 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 522 }; 523 524 /* reg_sfd_uc_tunnel_protocol 525 * IP protocol. 526 * Access: RW 527 */ 528 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 529 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 530 531 /* reg_sfd_uc_tunnel_uip_lsb 532 * When protocol is IPv4, the least significant bytes of the underlay 533 * IPv4 destination IP. 534 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 535 * which is configured by RIPS. 536 * Access: RW 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 539 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 540 541 static inline void 542 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 543 enum mlxsw_reg_sfd_rec_policy policy, 544 const char *mac, u16 fid, 545 enum mlxsw_reg_sfd_rec_action action, 546 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 547 { 548 mlxsw_reg_sfd_rec_pack(payload, rec_index, 549 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 550 action); 551 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 552 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 553 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 554 } 555 556 static inline void 557 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 558 enum mlxsw_reg_sfd_rec_policy policy, 559 const char *mac, u16 fid, 560 enum mlxsw_reg_sfd_rec_action action, u32 uip) 561 { 562 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 563 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 564 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 565 action, 566 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 567 } 568 569 static inline void 570 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 571 u16 fid, enum mlxsw_reg_sfd_rec_action action, 572 u32 uip_ptr) 573 { 574 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 575 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 576 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 577 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 578 mac, fid, action, 579 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 580 } 581 582 enum mlxsw_reg_tunnel_port { 583 MLXSW_REG_TUNNEL_PORT_NVE, 584 MLXSW_REG_TUNNEL_PORT_VPLS, 585 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 586 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 587 }; 588 589 /* SFN - Switch FDB Notification Register 590 * ------------------------------------------- 591 * The switch provides notifications on newly learned FDB entries and 592 * aged out entries. The notifications can be polled by software. 593 */ 594 #define MLXSW_REG_SFN_ID 0x200B 595 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 596 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 597 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 598 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 599 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 600 601 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 602 603 /* reg_sfn_swid 604 * Switch partition ID. 605 * Access: Index 606 */ 607 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 608 609 /* reg_sfn_end 610 * Forces the current session to end. 611 * Access: OP 612 */ 613 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 614 615 /* reg_sfn_num_rec 616 * Request: Number of learned notifications and aged-out notification 617 * records requested. 618 * Response: Number of notification records returned (must be smaller 619 * than or equal to the value requested) 620 * Ranges 0..64 621 * Access: OP 622 */ 623 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 624 625 static inline void mlxsw_reg_sfn_pack(char *payload) 626 { 627 MLXSW_REG_ZERO(sfn, payload); 628 mlxsw_reg_sfn_swid_set(payload, 0); 629 mlxsw_reg_sfn_end_set(payload, 0); 630 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 631 } 632 633 /* reg_sfn_rec_swid 634 * Switch partition ID. 635 * Access: RO 636 */ 637 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 638 MLXSW_REG_SFN_REC_LEN, 0x00, false); 639 640 enum mlxsw_reg_sfn_rec_type { 641 /* MAC addresses learned on a regular port. */ 642 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 643 /* MAC addresses learned on a LAG port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 645 /* Aged-out MAC address on a regular port. */ 646 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 647 /* Aged-out MAC address on a LAG port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 649 /* Learned unicast tunnel record. */ 650 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 651 /* Aged-out unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 653 }; 654 655 /* reg_sfn_rec_type 656 * Notification record type. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 660 MLXSW_REG_SFN_REC_LEN, 0x00, false); 661 662 /* reg_sfn_rec_mac 663 * MAC address. 664 * Access: RO 665 */ 666 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 667 MLXSW_REG_SFN_REC_LEN, 0x02); 668 669 /* reg_sfn_mac_sub_port 670 * VEPA channel on the local port. 671 * 0 if multichannel VEPA is not enabled. 672 * Access: RO 673 */ 674 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 675 MLXSW_REG_SFN_REC_LEN, 0x08, false); 676 677 /* reg_sfn_mac_fid 678 * Filtering identifier. 679 * Access: RO 680 */ 681 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 682 MLXSW_REG_SFN_REC_LEN, 0x08, false); 683 684 /* reg_sfn_mac_system_port 685 * Unique port identifier for the final destination of the packet. 686 * Access: RO 687 */ 688 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 689 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 690 691 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 692 char *mac, u16 *p_vid, 693 u16 *p_local_port) 694 { 695 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 696 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 697 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 698 } 699 700 /* reg_sfn_mac_lag_lag_id 701 * LAG ID (pointer into the LAG descriptor table). 702 * Access: RO 703 */ 704 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 705 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 706 707 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 708 char *mac, u16 *p_vid, 709 u16 *p_lag_id) 710 { 711 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 712 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 713 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 714 } 715 716 /* reg_sfn_uc_tunnel_uip_msb 717 * When protocol is IPv4, the most significant byte of the underlay IPv4 718 * address of the remote VTEP. 719 * When protocol is IPv6, reserved. 720 * Access: RO 721 */ 722 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 723 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 724 725 enum mlxsw_reg_sfn_uc_tunnel_protocol { 726 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 727 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 728 }; 729 730 /* reg_sfn_uc_tunnel_protocol 731 * IP protocol. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 735 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_uip_lsb 738 * When protocol is IPv4, the least significant bytes of the underlay 739 * IPv4 address of the remote VTEP. 740 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 741 * Access: RO 742 */ 743 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 744 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 745 746 /* reg_sfn_uc_tunnel_port 747 * Tunnel port. 748 * Reserved on Spectrum. 749 * Access: RO 750 */ 751 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 752 MLXSW_REG_SFN_REC_LEN, 0x10, false); 753 754 static inline void 755 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 756 u16 *p_fid, u32 *p_uip, 757 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 758 { 759 u32 uip_msb, uip_lsb; 760 761 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 762 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 763 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 764 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 765 *p_uip = uip_msb << 24 | uip_lsb; 766 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 767 } 768 769 /* SPMS - Switch Port MSTP/RSTP State Register 770 * ------------------------------------------- 771 * Configures the spanning tree state of a physical port. 772 */ 773 #define MLXSW_REG_SPMS_ID 0x200D 774 #define MLXSW_REG_SPMS_LEN 0x404 775 776 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 777 778 /* reg_spms_local_port 779 * Local port number. 780 * Access: Index 781 */ 782 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 783 784 enum mlxsw_reg_spms_state { 785 MLXSW_REG_SPMS_STATE_NO_CHANGE, 786 MLXSW_REG_SPMS_STATE_DISCARDING, 787 MLXSW_REG_SPMS_STATE_LEARNING, 788 MLXSW_REG_SPMS_STATE_FORWARDING, 789 }; 790 791 /* reg_spms_state 792 * Spanning tree state of each VLAN ID (VID) of the local port. 793 * 0 - Do not change spanning tree state (used only when writing). 794 * 1 - Discarding. No learning or forwarding to/from this port (default). 795 * 2 - Learning. Port is learning, but not forwarding. 796 * 3 - Forwarding. Port is learning and forwarding. 797 * Access: RW 798 */ 799 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 800 801 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 802 { 803 MLXSW_REG_ZERO(spms, payload); 804 mlxsw_reg_spms_local_port_set(payload, local_port); 805 } 806 807 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 808 enum mlxsw_reg_spms_state state) 809 { 810 mlxsw_reg_spms_state_set(payload, vid, state); 811 } 812 813 /* SPVID - Switch Port VID 814 * ----------------------- 815 * The switch port VID configures the default VID for a port. 816 */ 817 #define MLXSW_REG_SPVID_ID 0x200E 818 #define MLXSW_REG_SPVID_LEN 0x08 819 820 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 821 822 /* reg_spvid_tport 823 * Port is tunnel port. 824 * Reserved when SwitchX/-2 or Spectrum-1. 825 * Access: Index 826 */ 827 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 828 829 /* reg_spvid_local_port 830 * When tport = 0: Local port number. Not supported for CPU port. 831 * When tport = 1: Tunnel port. 832 * Access: Index 833 */ 834 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 835 836 /* reg_spvid_sub_port 837 * Virtual port within the physical port. 838 * Should be set to 0 when virtual ports are not enabled on the port. 839 * Access: Index 840 */ 841 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 842 843 /* reg_spvid_egr_et_set 844 * When VLAN is pushed at ingress (for untagged packets or for 845 * QinQ push mode) then the EtherType is decided at the egress port. 846 * Reserved when Spectrum-1. 847 * Access: RW 848 */ 849 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 850 851 /* reg_spvid_et_vlan 852 * EtherType used for when VLAN is pushed at ingress (for untagged 853 * packets or for QinQ push mode). 854 * 0: ether_type0 - (default) 855 * 1: ether_type1 856 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 857 * Ethertype IDs are configured by SVER. 858 * Reserved when egr_et_set = 1. 859 * Access: RW 860 */ 861 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 862 863 /* reg_spvid_pvid 864 * Port default VID 865 * Access: RW 866 */ 867 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 868 869 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 870 u8 et_vlan) 871 { 872 MLXSW_REG_ZERO(spvid, payload); 873 mlxsw_reg_spvid_local_port_set(payload, local_port); 874 mlxsw_reg_spvid_pvid_set(payload, pvid); 875 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 876 } 877 878 /* SPVM - Switch Port VLAN Membership 879 * ---------------------------------- 880 * The Switch Port VLAN Membership register configures the VLAN membership 881 * of a port in a VLAN denoted by VID. VLAN membership is managed per 882 * virtual port. The register can be used to add and remove VID(s) from a port. 883 */ 884 #define MLXSW_REG_SPVM_ID 0x200F 885 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 886 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 887 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 888 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 889 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 890 891 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 892 893 /* reg_spvm_pt 894 * Priority tagged. If this bit is set, packets forwarded to the port with 895 * untagged VLAN membership (u bit is set) will be tagged with priority tag 896 * (VID=0) 897 * Access: RW 898 */ 899 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 900 901 /* reg_spvm_pte 902 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 903 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 904 * Access: WO 905 */ 906 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 907 908 /* reg_spvm_local_port 909 * Local port number. 910 * Access: Index 911 */ 912 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 913 914 /* reg_spvm_sub_port 915 * Virtual port within the physical port. 916 * Should be set to 0 when virtual ports are not enabled on the port. 917 * Access: Index 918 */ 919 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 920 921 /* reg_spvm_num_rec 922 * Number of records to update. Each record contains: i, e, u, vid. 923 * Access: OP 924 */ 925 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 926 927 /* reg_spvm_rec_i 928 * Ingress membership in VLAN ID. 929 * Access: Index 930 */ 931 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 932 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 933 MLXSW_REG_SPVM_REC_LEN, 0, false); 934 935 /* reg_spvm_rec_e 936 * Egress membership in VLAN ID. 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 940 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_u 944 * Untagged - port is an untagged member - egress transmission uses untagged 945 * frames on VID<n> 946 * Access: Index 947 */ 948 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 949 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 950 MLXSW_REG_SPVM_REC_LEN, 0, false); 951 952 /* reg_spvm_rec_vid 953 * Egress membership in VLAN ID. 954 * Access: Index 955 */ 956 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 957 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 958 MLXSW_REG_SPVM_REC_LEN, 0, false); 959 960 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 961 u16 vid_begin, u16 vid_end, 962 bool is_member, bool untagged) 963 { 964 int size = vid_end - vid_begin + 1; 965 int i; 966 967 MLXSW_REG_ZERO(spvm, payload); 968 mlxsw_reg_spvm_local_port_set(payload, local_port); 969 mlxsw_reg_spvm_num_rec_set(payload, size); 970 971 for (i = 0; i < size; i++) { 972 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 973 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 974 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 975 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 976 } 977 } 978 979 /* SPAFT - Switch Port Acceptable Frame Types 980 * ------------------------------------------ 981 * The Switch Port Acceptable Frame Types register configures the frame 982 * admittance of the port. 983 */ 984 #define MLXSW_REG_SPAFT_ID 0x2010 985 #define MLXSW_REG_SPAFT_LEN 0x08 986 987 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 988 989 /* reg_spaft_local_port 990 * Local port number. 991 * Access: Index 992 * 993 * Note: CPU port is not supported (all tag types are allowed). 994 */ 995 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 996 997 /* reg_spaft_sub_port 998 * Virtual port within the physical port. 999 * Should be set to 0 when virtual ports are not enabled on the port. 1000 * Access: RW 1001 */ 1002 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1003 1004 /* reg_spaft_allow_untagged 1005 * When set, untagged frames on the ingress are allowed (default). 1006 * Access: RW 1007 */ 1008 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1009 1010 /* reg_spaft_allow_prio_tagged 1011 * When set, priority tagged frames on the ingress are allowed (default). 1012 * Access: RW 1013 */ 1014 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1015 1016 /* reg_spaft_allow_tagged 1017 * When set, tagged frames on the ingress are allowed (default). 1018 * Access: RW 1019 */ 1020 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1021 1022 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1023 bool allow_untagged) 1024 { 1025 MLXSW_REG_ZERO(spaft, payload); 1026 mlxsw_reg_spaft_local_port_set(payload, local_port); 1027 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1028 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1029 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1030 } 1031 1032 /* SFGC - Switch Flooding Group Configuration 1033 * ------------------------------------------ 1034 * The following register controls the association of flooding tables and MIDs 1035 * to packet types used for flooding. 1036 */ 1037 #define MLXSW_REG_SFGC_ID 0x2011 1038 #define MLXSW_REG_SFGC_LEN 0x14 1039 1040 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1041 1042 enum mlxsw_reg_sfgc_type { 1043 MLXSW_REG_SFGC_TYPE_BROADCAST, 1044 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1046 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1047 MLXSW_REG_SFGC_TYPE_RESERVED, 1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1049 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1050 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1051 MLXSW_REG_SFGC_TYPE_MAX, 1052 }; 1053 1054 /* reg_sfgc_type 1055 * The traffic type to reach the flooding table. 1056 * Access: Index 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1059 1060 /* bridge_type is used in SFGC and SFMR. */ 1061 enum mlxsw_reg_bridge_type { 1062 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1063 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1064 }; 1065 1066 /* reg_sfgc_bridge_type 1067 * Access: Index 1068 * 1069 * Note: SwitchX-2 only supports 802.1Q mode. 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1072 1073 enum mlxsw_flood_table_type { 1074 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1075 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1076 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1077 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1078 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1079 }; 1080 1081 /* reg_sfgc_table_type 1082 * See mlxsw_flood_table_type 1083 * Access: RW 1084 * 1085 * Note: FID offset and FID types are not supported in SwitchX-2. 1086 */ 1087 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1088 1089 /* reg_sfgc_flood_table 1090 * Flooding table index to associate with the specific type on the specific 1091 * switch partition. 1092 * Access: RW 1093 */ 1094 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1095 1096 /* reg_sfgc_counter_set_type 1097 * Counter Set Type for flow counters. 1098 * Access: RW 1099 */ 1100 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1101 1102 /* reg_sfgc_counter_index 1103 * Counter Index for flow counters. 1104 * Access: RW 1105 */ 1106 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1107 1108 /* reg_sfgc_mid_base 1109 * MID Base. 1110 * Access: RW 1111 * 1112 * Note: Reserved when legacy bridge model is used. 1113 */ 1114 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1115 1116 static inline void 1117 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1118 enum mlxsw_reg_bridge_type bridge_type, 1119 enum mlxsw_flood_table_type table_type, 1120 unsigned int flood_table, u16 mid_base) 1121 { 1122 MLXSW_REG_ZERO(sfgc, payload); 1123 mlxsw_reg_sfgc_type_set(payload, type); 1124 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1125 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1126 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1127 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1128 } 1129 1130 /* SFDF - Switch Filtering DB Flush 1131 * -------------------------------- 1132 * The switch filtering DB flush register is used to flush the FDB. 1133 * Note that FDB notifications are flushed as well. 1134 */ 1135 #define MLXSW_REG_SFDF_ID 0x2013 1136 #define MLXSW_REG_SFDF_LEN 0x14 1137 1138 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1139 1140 /* reg_sfdf_swid 1141 * Switch partition ID. 1142 * Access: Index 1143 */ 1144 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1145 1146 enum mlxsw_reg_sfdf_flush_type { 1147 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1148 MLXSW_REG_SFDF_FLUSH_PER_FID, 1149 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1150 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1151 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1152 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1153 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1154 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1155 }; 1156 1157 /* reg_sfdf_flush_type 1158 * Flush type. 1159 * 0 - All SWID dynamic entries are flushed. 1160 * 1 - All FID dynamic entries are flushed. 1161 * 2 - All dynamic entries pointing to port are flushed. 1162 * 3 - All FID dynamic entries pointing to port are flushed. 1163 * 4 - All dynamic entries pointing to LAG are flushed. 1164 * 5 - All FID dynamic entries pointing to LAG are flushed. 1165 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1166 * flushed. 1167 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1168 * flushed, per FID. 1169 * Access: RW 1170 */ 1171 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1172 1173 /* reg_sfdf_flush_static 1174 * Static. 1175 * 0 - Flush only dynamic entries. 1176 * 1 - Flush both dynamic and static entries. 1177 * Access: RW 1178 */ 1179 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1180 1181 static inline void mlxsw_reg_sfdf_pack(char *payload, 1182 enum mlxsw_reg_sfdf_flush_type type) 1183 { 1184 MLXSW_REG_ZERO(sfdf, payload); 1185 mlxsw_reg_sfdf_flush_type_set(payload, type); 1186 mlxsw_reg_sfdf_flush_static_set(payload, true); 1187 } 1188 1189 /* reg_sfdf_fid 1190 * FID to flush. 1191 * Access: RW 1192 */ 1193 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1194 1195 /* reg_sfdf_system_port 1196 * Port to flush. 1197 * Access: RW 1198 */ 1199 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1200 1201 /* reg_sfdf_port_fid_system_port 1202 * Port to flush, pointed to by FID. 1203 * Access: RW 1204 */ 1205 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1206 1207 /* reg_sfdf_lag_id 1208 * LAG ID to flush. 1209 * Access: RW 1210 */ 1211 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1212 1213 /* reg_sfdf_lag_fid_lag_id 1214 * LAG ID to flush, pointed to by FID. 1215 * Access: RW 1216 */ 1217 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1218 1219 /* SLDR - Switch LAG Descriptor Register 1220 * ----------------------------------------- 1221 * The switch LAG descriptor register is populated by LAG descriptors. 1222 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1223 * max_lag-1. 1224 */ 1225 #define MLXSW_REG_SLDR_ID 0x2014 1226 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1227 1228 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1229 1230 enum mlxsw_reg_sldr_op { 1231 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1232 MLXSW_REG_SLDR_OP_LAG_CREATE, 1233 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1234 /* Ports that appear in the list have the Distributor enabled */ 1235 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1236 /* Removes ports from the disributor list */ 1237 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1238 }; 1239 1240 /* reg_sldr_op 1241 * Operation. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1245 1246 /* reg_sldr_lag_id 1247 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1248 * Access: Index 1249 */ 1250 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1251 1252 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1253 { 1254 MLXSW_REG_ZERO(sldr, payload); 1255 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1256 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1257 } 1258 1259 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1260 { 1261 MLXSW_REG_ZERO(sldr, payload); 1262 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1263 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1264 } 1265 1266 /* reg_sldr_num_ports 1267 * The number of member ports of the LAG. 1268 * Reserved for Create / Destroy operations 1269 * For Add / Remove operations - indicates the number of ports in the list. 1270 * Access: RW 1271 */ 1272 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1273 1274 /* reg_sldr_system_port 1275 * System port. 1276 * Access: RW 1277 */ 1278 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1279 1280 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1281 u16 local_port) 1282 { 1283 MLXSW_REG_ZERO(sldr, payload); 1284 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1285 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1286 mlxsw_reg_sldr_num_ports_set(payload, 1); 1287 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1288 } 1289 1290 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1291 u16 local_port) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 mlxsw_reg_sldr_num_ports_set(payload, 1); 1297 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1298 } 1299 1300 /* SLCR - Switch LAG Configuration 2 Register 1301 * ------------------------------------------- 1302 * The Switch LAG Configuration register is used for configuring the 1303 * LAG properties of the switch. 1304 */ 1305 #define MLXSW_REG_SLCR_ID 0x2015 1306 #define MLXSW_REG_SLCR_LEN 0x10 1307 1308 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1309 1310 enum mlxsw_reg_slcr_pp { 1311 /* Global Configuration (for all ports) */ 1312 MLXSW_REG_SLCR_PP_GLOBAL, 1313 /* Per port configuration, based on local_port field */ 1314 MLXSW_REG_SLCR_PP_PER_PORT, 1315 }; 1316 1317 /* reg_slcr_pp 1318 * Per Port Configuration 1319 * Note: Reading at Global mode results in reading port 1 configuration. 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1323 1324 /* reg_slcr_local_port 1325 * Local port number 1326 * Supported from CPU port 1327 * Not supported from router port 1328 * Reserved when pp = Global Configuration 1329 * Access: Index 1330 */ 1331 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1332 1333 enum mlxsw_reg_slcr_type { 1334 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1335 MLXSW_REG_SLCR_TYPE_XOR, 1336 MLXSW_REG_SLCR_TYPE_RANDOM, 1337 }; 1338 1339 /* reg_slcr_type 1340 * Hash type 1341 * Access: RW 1342 */ 1343 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1344 1345 /* Ingress port */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1347 /* SMAC - for IPv4 and IPv6 packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1349 /* SMAC - for non-IP packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1351 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1352 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1353 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1354 /* DMAC - for IPv4 and IPv6 packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1356 /* DMAC - for non-IP packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1358 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1359 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1360 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1361 /* Ethertype - for IPv4 and IPv6 packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1363 /* Ethertype - for non-IP packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1365 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1366 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1367 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1368 /* VLAN ID - for IPv4 and IPv6 packets */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1370 /* VLAN ID - for non-IP packets */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1372 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1373 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1374 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1375 /* Source IP address (can be IPv4 or IPv6) */ 1376 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1377 /* Destination IP address (can be IPv4 or IPv6) */ 1378 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1379 /* TCP/UDP source port */ 1380 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1381 /* TCP/UDP destination port*/ 1382 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1383 /* IPv4 Protocol/IPv6 Next Header */ 1384 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1385 /* IPv6 Flow label */ 1386 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1387 /* SID - FCoE source ID */ 1388 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1389 /* DID - FCoE destination ID */ 1390 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1391 /* OXID - FCoE originator exchange ID */ 1392 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1393 /* Destination QP number - for RoCE packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1395 1396 /* reg_slcr_lag_hash 1397 * LAG hashing configuration. This is a bitmask, in which each set 1398 * bit includes the corresponding item in the LAG hash calculation. 1399 * The default lag_hash contains SMAC, DMAC, VLANID and 1400 * Ethertype (for all packet types). 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1404 1405 /* reg_slcr_seed 1406 * LAG seed value. The seed is the same for all ports. 1407 * Access: RW 1408 */ 1409 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1410 1411 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1412 { 1413 MLXSW_REG_ZERO(slcr, payload); 1414 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1415 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1416 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1417 mlxsw_reg_slcr_seed_set(payload, seed); 1418 } 1419 1420 /* SLCOR - Switch LAG Collector Register 1421 * ------------------------------------- 1422 * The Switch LAG Collector register controls the Local Port membership 1423 * in a LAG and enablement of the collector. 1424 */ 1425 #define MLXSW_REG_SLCOR_ID 0x2016 1426 #define MLXSW_REG_SLCOR_LEN 0x10 1427 1428 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1429 1430 enum mlxsw_reg_slcor_col { 1431 /* Port is added with collector disabled */ 1432 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1433 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1435 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1436 }; 1437 1438 /* reg_slcor_col 1439 * Collector configuration 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1443 1444 /* reg_slcor_local_port 1445 * Local port number 1446 * Not supported for CPU port 1447 * Access: Index 1448 */ 1449 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1450 1451 /* reg_slcor_lag_id 1452 * LAG Identifier. Index into the LAG descriptor table. 1453 * Access: Index 1454 */ 1455 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1456 1457 /* reg_slcor_port_index 1458 * Port index in the LAG list. Only valid on Add Port to LAG col. 1459 * Valid range is from 0 to cap_max_lag_members-1 1460 * Access: RW 1461 */ 1462 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1463 1464 static inline void mlxsw_reg_slcor_pack(char *payload, 1465 u16 local_port, u16 lag_id, 1466 enum mlxsw_reg_slcor_col col) 1467 { 1468 MLXSW_REG_ZERO(slcor, payload); 1469 mlxsw_reg_slcor_col_set(payload, col); 1470 mlxsw_reg_slcor_local_port_set(payload, local_port); 1471 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1475 u16 local_port, u16 lag_id, 1476 u8 port_index) 1477 { 1478 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1479 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1480 mlxsw_reg_slcor_port_index_set(payload, port_index); 1481 } 1482 1483 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1484 u16 local_port, u16 lag_id) 1485 { 1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1487 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1488 } 1489 1490 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1491 u16 local_port, u16 lag_id) 1492 { 1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1495 } 1496 1497 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1498 u16 local_port, u16 lag_id) 1499 { 1500 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1501 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1502 } 1503 1504 /* SPMLR - Switch Port MAC Learning Register 1505 * ----------------------------------------- 1506 * Controls the Switch MAC learning policy per port. 1507 */ 1508 #define MLXSW_REG_SPMLR_ID 0x2018 1509 #define MLXSW_REG_SPMLR_LEN 0x8 1510 1511 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1512 1513 /* reg_spmlr_local_port 1514 * Local port number. 1515 * Access: Index 1516 */ 1517 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1518 1519 /* reg_spmlr_sub_port 1520 * Virtual port within the physical port. 1521 * Should be set to 0 when virtual ports are not enabled on the port. 1522 * Access: Index 1523 */ 1524 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1525 1526 enum mlxsw_reg_spmlr_learn_mode { 1527 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1528 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1529 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1530 }; 1531 1532 /* reg_spmlr_learn_mode 1533 * Learning mode on the port. 1534 * 0 - Learning disabled. 1535 * 2 - Learning enabled. 1536 * 3 - Security mode. 1537 * 1538 * In security mode the switch does not learn MACs on the port, but uses the 1539 * SMAC to see if it exists on another ingress port. If so, the packet is 1540 * classified as a bad packet and is discarded unless the software registers 1541 * to receive port security error packets usign HPKT. 1542 */ 1543 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1544 1545 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1546 enum mlxsw_reg_spmlr_learn_mode mode) 1547 { 1548 MLXSW_REG_ZERO(spmlr, payload); 1549 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1550 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1551 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1552 } 1553 1554 /* SVFA - Switch VID to FID Allocation Register 1555 * -------------------------------------------- 1556 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1557 * virtualized ports. 1558 */ 1559 #define MLXSW_REG_SVFA_ID 0x201C 1560 #define MLXSW_REG_SVFA_LEN 0x18 1561 1562 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1563 1564 /* reg_svfa_swid 1565 * Switch partition ID. 1566 * Access: Index 1567 */ 1568 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1569 1570 /* reg_svfa_local_port 1571 * Local port number. 1572 * Access: Index 1573 * 1574 * Note: Reserved for 802.1Q FIDs. 1575 */ 1576 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1577 1578 enum mlxsw_reg_svfa_mt { 1579 MLXSW_REG_SVFA_MT_VID_TO_FID, 1580 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1581 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1582 }; 1583 1584 /* reg_svfa_mapping_table 1585 * Mapping table: 1586 * 0 - VID to FID 1587 * 1 - {Port, VID} to FID 1588 * Access: Index 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1593 1594 /* reg_svfa_v 1595 * Valid. 1596 * Valid if set. 1597 * Access: RW 1598 * 1599 * Note: Reserved for SwitchX-2. 1600 */ 1601 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1602 1603 /* reg_svfa_fid 1604 * Filtering ID. 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1608 1609 /* reg_svfa_vid 1610 * VLAN ID. 1611 * Access: Index 1612 */ 1613 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1614 1615 /* reg_svfa_counter_set_type 1616 * Counter set type for flow counters. 1617 * Access: RW 1618 * 1619 * Note: Reserved for SwitchX-2. 1620 */ 1621 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1622 1623 /* reg_svfa_counter_index 1624 * Counter index for flow counters. 1625 * Access: RW 1626 * 1627 * Note: Reserved for SwitchX-2. 1628 */ 1629 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1630 1631 /* reg_svfa_vni 1632 * Virtual Network Identifier. 1633 * Access: Index 1634 * 1635 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1636 */ 1637 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1638 1639 /* reg_svfa_irif_v 1640 * Ingress RIF valid. 1641 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1642 * 1 - Ingress RIF valid. 1643 * Must not be set for a non enabled RIF. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1649 1650 /* reg_svfa_irif 1651 * Ingress RIF (Router Interface). 1652 * Range is 0..cap_max_router_interfaces-1. 1653 * Access: RW 1654 * 1655 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1656 */ 1657 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1658 1659 static inline void __mlxsw_reg_svfa_pack(char *payload, 1660 enum mlxsw_reg_svfa_mt mt, bool valid, 1661 u16 fid, bool irif_v, u16 irif) 1662 { 1663 MLXSW_REG_ZERO(svfa, payload); 1664 mlxsw_reg_svfa_swid_set(payload, 0); 1665 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1666 mlxsw_reg_svfa_v_set(payload, valid); 1667 mlxsw_reg_svfa_fid_set(payload, fid); 1668 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1669 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1670 } 1671 1672 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1673 bool valid, u16 fid, u16 vid, 1674 bool irif_v, u16 irif) 1675 { 1676 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1677 1678 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1679 mlxsw_reg_svfa_local_port_set(payload, local_port); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1684 u16 vid, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vid_set(payload, vid); 1690 } 1691 1692 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1693 u32 vni, bool irif_v, u16 irif) 1694 { 1695 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1696 1697 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1698 mlxsw_reg_svfa_vni_set(payload, vni); 1699 } 1700 1701 /* SPVTR - Switch Port VLAN Stacking Register 1702 * ------------------------------------------ 1703 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1704 * to enable VLAN stacking. 1705 */ 1706 #define MLXSW_REG_SPVTR_ID 0x201D 1707 #define MLXSW_REG_SPVTR_LEN 0x10 1708 1709 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1710 1711 /* reg_spvtr_tport 1712 * Port is tunnel port. 1713 * Access: Index 1714 * 1715 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1716 */ 1717 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1718 1719 /* reg_spvtr_local_port 1720 * When tport = 0: local port number (Not supported from/to CPU). 1721 * When tport = 1: tunnel port. 1722 * Access: Index 1723 */ 1724 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1725 1726 /* reg_spvtr_ippe 1727 * Ingress Port Prio Mode Update Enable. 1728 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1733 1734 /* reg_spvtr_ipve 1735 * Ingress Port VID Mode Update Enable. 1736 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1737 * field. 1738 * Reserved on Get operations. 1739 * Access: OP 1740 */ 1741 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1742 1743 /* reg_spvtr_epve 1744 * Egress Port VID Mode Update Enable. 1745 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1746 * field. 1747 * Access: OP 1748 */ 1749 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1750 1751 /* reg_spvtr_ipprio_mode 1752 * Ingress Port Priority Mode. 1753 * This controls the PCP and DEI of the new outer VLAN 1754 * Note: for SwitchX/-2 the DEI is not affected. 1755 * 0: use port default PCP and DEI (configured by QPDPC). 1756 * 1: use C-VLAN PCP and DEI. 1757 * Has no effect when ipvid_mode = 0. 1758 * Reserved when tport = 1. 1759 * Access: RW 1760 */ 1761 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1762 1763 enum mlxsw_reg_spvtr_ipvid_mode { 1764 /* IEEE Compliant PVID (default) */ 1765 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1766 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1767 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1768 /* Always push VLAN (also for prio tagged packets) */ 1769 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1770 }; 1771 1772 /* reg_spvtr_ipvid_mode 1773 * Ingress Port VLAN-ID Mode. 1774 * For Spectrum family, this affects the values of SPVM.i 1775 * Access: RW 1776 */ 1777 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1778 1779 enum mlxsw_reg_spvtr_epvid_mode { 1780 /* IEEE Compliant VLAN membership */ 1781 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1782 /* Pop VLAN (for VLAN stacking) */ 1783 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1784 }; 1785 1786 /* reg_spvtr_epvid_mode 1787 * Egress Port VLAN-ID Mode. 1788 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1789 * Access: WO 1790 */ 1791 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1792 1793 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1794 u16 local_port, 1795 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1796 { 1797 MLXSW_REG_ZERO(spvtr, payload); 1798 mlxsw_reg_spvtr_tport_set(payload, tport); 1799 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1800 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1801 mlxsw_reg_spvtr_ipve_set(payload, true); 1802 } 1803 1804 /* SVPE - Switch Virtual-Port Enabling Register 1805 * -------------------------------------------- 1806 * Enables port virtualization. 1807 */ 1808 #define MLXSW_REG_SVPE_ID 0x201E 1809 #define MLXSW_REG_SVPE_LEN 0x4 1810 1811 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1812 1813 /* reg_svpe_local_port 1814 * Local port number 1815 * Access: Index 1816 * 1817 * Note: CPU port is not supported (uses VLAN mode only). 1818 */ 1819 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1820 1821 /* reg_svpe_vp_en 1822 * Virtual port enable. 1823 * 0 - Disable, VLAN mode (VID to FID). 1824 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1825 * Access: RW 1826 */ 1827 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1828 1829 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1830 bool enable) 1831 { 1832 MLXSW_REG_ZERO(svpe, payload); 1833 mlxsw_reg_svpe_local_port_set(payload, local_port); 1834 mlxsw_reg_svpe_vp_en_set(payload, enable); 1835 } 1836 1837 /* SFMR - Switch FID Management Register 1838 * ------------------------------------- 1839 * Creates and configures FIDs. 1840 */ 1841 #define MLXSW_REG_SFMR_ID 0x201F 1842 #define MLXSW_REG_SFMR_LEN 0x30 1843 1844 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1845 1846 enum mlxsw_reg_sfmr_op { 1847 MLXSW_REG_SFMR_OP_CREATE_FID, 1848 MLXSW_REG_SFMR_OP_DESTROY_FID, 1849 }; 1850 1851 /* reg_sfmr_op 1852 * Operation. 1853 * 0 - Create or edit FID. 1854 * 1 - Destroy FID. 1855 * Access: WO 1856 */ 1857 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1858 1859 /* reg_sfmr_fid 1860 * Filtering ID. 1861 * Access: Index 1862 */ 1863 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1864 1865 /* reg_sfmr_flood_rsp 1866 * Router sub-port flooding table. 1867 * 0 - Regular flooding table. 1868 * 1 - Router sub-port flooding table. For this FID the flooding is per 1869 * router-sub-port local_port. Must not be set for a FID which is not a 1870 * router-sub-port and must be set prior to enabling the relevant RIF. 1871 * Access: RW 1872 * 1873 * Note: Reserved when legacy bridge model is used. 1874 */ 1875 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1876 1877 /* reg_sfmr_flood_bridge_type 1878 * Flood bridge type (see SFGC.bridge_type). 1879 * 0 - type_0. 1880 * 1 - type_1. 1881 * Access: RW 1882 * 1883 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1884 */ 1885 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1886 1887 /* reg_sfmr_fid_offset 1888 * FID offset. 1889 * Used to point into the flooding table selected by SFGC register if 1890 * the table is of type FID-Offset. Otherwise, this field is reserved. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1894 1895 /* reg_sfmr_vtfp 1896 * Valid Tunnel Flood Pointer. 1897 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1898 * Access: RW 1899 * 1900 * Note: Reserved for 802.1Q FIDs. 1901 */ 1902 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1903 1904 /* reg_sfmr_nve_tunnel_flood_ptr 1905 * Underlay Flooding and BC Pointer. 1906 * Used as a pointer to the first entry of the group based link lists of 1907 * flooding or BC entries (for NVE tunnels). 1908 * Access: RW 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1911 1912 /* reg_sfmr_vv 1913 * VNI Valid. 1914 * If not set, then vni is reserved. 1915 * Access: RW 1916 * 1917 * Note: Reserved for 802.1Q FIDs. 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1920 1921 /* reg_sfmr_vni 1922 * Virtual Network Identifier. 1923 * When legacy bridge model is used, a given VNI can only be assigned to one 1924 * FID. When unified bridge model is used, it configures only the FID->VNI, 1925 * the VNI->FID is done by SVFA. 1926 * Access: RW 1927 */ 1928 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1929 1930 /* reg_sfmr_irif_v 1931 * Ingress RIF valid. 1932 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1933 * 1 - Ingress RIF valid. 1934 * Must not be set for a non valid RIF. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1940 1941 /* reg_sfmr_irif 1942 * Ingress RIF (Router Interface). 1943 * Range is 0..cap_max_router_interfaces-1. 1944 * Access: RW 1945 * 1946 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1949 1950 /* reg_sfmr_smpe_valid 1951 * SMPE is valid. 1952 * Access: RW 1953 * 1954 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1955 * Spectrum-1. 1956 */ 1957 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1958 1959 /* reg_sfmr_smpe 1960 * Switch multicast port to egress VID. 1961 * Range is 0..cap_max_rmpe-1 1962 * Access: RW 1963 * 1964 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1965 * Spectrum-1. 1966 */ 1967 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1968 1969 static inline void mlxsw_reg_sfmr_pack(char *payload, 1970 enum mlxsw_reg_sfmr_op op, u16 fid, 1971 u16 fid_offset, bool flood_rsp, 1972 enum mlxsw_reg_bridge_type bridge_type, 1973 bool smpe_valid, u16 smpe) 1974 { 1975 MLXSW_REG_ZERO(sfmr, payload); 1976 mlxsw_reg_sfmr_op_set(payload, op); 1977 mlxsw_reg_sfmr_fid_set(payload, fid); 1978 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1979 mlxsw_reg_sfmr_vtfp_set(payload, false); 1980 mlxsw_reg_sfmr_vv_set(payload, false); 1981 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1982 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1983 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1984 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1985 } 1986 1987 /* SPVMLR - Switch Port VLAN MAC Learning Register 1988 * ----------------------------------------------- 1989 * Controls the switch MAC learning policy per {Port, VID}. 1990 */ 1991 #define MLXSW_REG_SPVMLR_ID 0x2020 1992 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1993 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1994 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1995 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1996 MLXSW_REG_SPVMLR_REC_LEN * \ 1997 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1998 1999 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 2000 2001 /* reg_spvmlr_local_port 2002 * Local ingress port. 2003 * Access: Index 2004 * 2005 * Note: CPU port is not supported. 2006 */ 2007 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 2008 2009 /* reg_spvmlr_num_rec 2010 * Number of records to update. 2011 * Access: OP 2012 */ 2013 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2014 2015 /* reg_spvmlr_rec_learn_enable 2016 * 0 - Disable learning for {Port, VID}. 2017 * 1 - Enable learning for {Port, VID}. 2018 * Access: RW 2019 */ 2020 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2021 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2022 2023 /* reg_spvmlr_rec_vid 2024 * VLAN ID to be added/removed from port or for querying. 2025 * Access: Index 2026 */ 2027 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2028 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2029 2030 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2031 u16 vid_begin, u16 vid_end, 2032 bool learn_enable) 2033 { 2034 int num_rec = vid_end - vid_begin + 1; 2035 int i; 2036 2037 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2038 2039 MLXSW_REG_ZERO(spvmlr, payload); 2040 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2041 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2042 2043 for (i = 0; i < num_rec; i++) { 2044 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2045 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2046 } 2047 } 2048 2049 /* SPVC - Switch Port VLAN Classification Register 2050 * ----------------------------------------------- 2051 * Configures the port to identify packets as untagged / single tagged / 2052 * double packets based on the packet EtherTypes. 2053 * Ethertype IDs are configured by SVER. 2054 */ 2055 #define MLXSW_REG_SPVC_ID 0x2026 2056 #define MLXSW_REG_SPVC_LEN 0x0C 2057 2058 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2059 2060 /* reg_spvc_local_port 2061 * Local port. 2062 * Access: Index 2063 * 2064 * Note: applies both to Rx port and Tx port, so if a packet traverses 2065 * through Rx port i and a Tx port j then port i and port j must have the 2066 * same configuration. 2067 */ 2068 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2069 2070 /* reg_spvc_inner_et2 2071 * Vlan Tag1 EtherType2 enable. 2072 * Packet is initially classified as double VLAN Tag if in addition to 2073 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2074 * equal to ether_type2. 2075 * 0: disable (default) 2076 * 1: enable 2077 * Access: RW 2078 */ 2079 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2080 2081 /* reg_spvc_et2 2082 * Vlan Tag0 EtherType2 enable. 2083 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2084 * equal to ether_type2. 2085 * 0: disable (default) 2086 * 1: enable 2087 * Access: RW 2088 */ 2089 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2090 2091 /* reg_spvc_inner_et1 2092 * Vlan Tag1 EtherType1 enable. 2093 * Packet is initially classified as double VLAN Tag if in addition to 2094 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2095 * equal to ether_type1. 2096 * 0: disable 2097 * 1: enable (default) 2098 * Access: RW 2099 */ 2100 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2101 2102 /* reg_spvc_et1 2103 * Vlan Tag0 EtherType1 enable. 2104 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2105 * equal to ether_type1. 2106 * 0: disable 2107 * 1: enable (default) 2108 * Access: RW 2109 */ 2110 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2111 2112 /* reg_inner_et0 2113 * Vlan Tag1 EtherType0 enable. 2114 * Packet is initially classified as double VLAN Tag if in addition to 2115 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2116 * equal to ether_type0. 2117 * 0: disable 2118 * 1: enable (default) 2119 * Access: RW 2120 */ 2121 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2122 2123 /* reg_et0 2124 * Vlan Tag0 EtherType0 enable. 2125 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2126 * equal to ether_type0. 2127 * 0: disable 2128 * 1: enable (default) 2129 * Access: RW 2130 */ 2131 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2132 2133 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2134 bool et0) 2135 { 2136 MLXSW_REG_ZERO(spvc, payload); 2137 mlxsw_reg_spvc_local_port_set(payload, local_port); 2138 /* Enable inner_et1 and inner_et0 to enable identification of double 2139 * tagged packets. 2140 */ 2141 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2142 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2143 mlxsw_reg_spvc_et1_set(payload, et1); 2144 mlxsw_reg_spvc_et0_set(payload, et0); 2145 } 2146 2147 /* SPEVET - Switch Port Egress VLAN EtherType 2148 * ------------------------------------------ 2149 * The switch port egress VLAN EtherType configures which EtherType to push at 2150 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2151 * is set. 2152 */ 2153 #define MLXSW_REG_SPEVET_ID 0x202A 2154 #define MLXSW_REG_SPEVET_LEN 0x08 2155 2156 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2157 2158 /* reg_spevet_local_port 2159 * Egress Local port number. 2160 * Not supported to CPU port. 2161 * Access: Index 2162 */ 2163 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2164 2165 /* reg_spevet_et_vlan 2166 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2167 * 0: ether_type0 - (default) 2168 * 1: ether_type1 2169 * 2: ether_type2 2170 * Access: RW 2171 */ 2172 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2173 2174 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2175 u8 et_vlan) 2176 { 2177 MLXSW_REG_ZERO(spevet, payload); 2178 mlxsw_reg_spevet_local_port_set(payload, local_port); 2179 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2180 } 2181 2182 /* SMPE - Switch Multicast Port to Egress VID 2183 * ------------------------------------------ 2184 * The switch multicast port to egress VID maps 2185 * {egress_port, SMPE index} -> {VID}. 2186 */ 2187 #define MLXSW_REG_SMPE_ID 0x202B 2188 #define MLXSW_REG_SMPE_LEN 0x0C 2189 2190 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2191 2192 /* reg_smpe_local_port 2193 * Local port number. 2194 * CPU port is not supported. 2195 * Access: Index 2196 */ 2197 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2198 2199 /* reg_smpe_smpe_index 2200 * Switch multicast port to egress VID. 2201 * Range is 0..cap_max_rmpe-1. 2202 * Access: Index 2203 */ 2204 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2205 2206 /* reg_smpe_evid 2207 * Egress VID. 2208 * Access: RW 2209 */ 2210 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2211 2212 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2213 u16 smpe_index, u16 evid) 2214 { 2215 MLXSW_REG_ZERO(smpe, payload); 2216 mlxsw_reg_smpe_local_port_set(payload, local_port); 2217 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2218 mlxsw_reg_smpe_evid_set(payload, evid); 2219 } 2220 2221 /* SMID-V2 - Switch Multicast ID Version 2 Register 2222 * ------------------------------------------------ 2223 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2224 * of the multicast group within the stacking domain, into a list of local 2225 * ports into which the packet is replicated. 2226 */ 2227 #define MLXSW_REG_SMID2_ID 0x2034 2228 #define MLXSW_REG_SMID2_LEN 0x120 2229 2230 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2231 2232 /* reg_smid2_swid 2233 * Switch partition ID. 2234 * Access: Index 2235 */ 2236 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2237 2238 /* reg_smid2_mid 2239 * Multicast identifier - global identifier that represents the multicast group 2240 * across all devices. 2241 * Access: Index 2242 */ 2243 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2244 2245 /* reg_smid2_smpe_valid 2246 * SMPE is valid. 2247 * When not valid, the egress VID will not be modified by the SMPE table. 2248 * Access: RW 2249 * 2250 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2251 */ 2252 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2253 2254 /* reg_smid2_smpe 2255 * Switch multicast port to egress VID. 2256 * Access: RW 2257 * 2258 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2259 */ 2260 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2261 2262 /* reg_smid2_port 2263 * Local port memebership (1 bit per port). 2264 * Access: RW 2265 */ 2266 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2267 2268 /* reg_smid2_port_mask 2269 * Local port mask (1 bit per port). 2270 * Access: WO 2271 */ 2272 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2273 2274 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2275 bool set, bool smpe_valid, u16 smpe) 2276 { 2277 MLXSW_REG_ZERO(smid2, payload); 2278 mlxsw_reg_smid2_swid_set(payload, 0); 2279 mlxsw_reg_smid2_mid_set(payload, mid); 2280 mlxsw_reg_smid2_port_set(payload, port, set); 2281 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2282 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2283 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2284 } 2285 2286 /* CWTP - Congetion WRED ECN TClass Profile 2287 * ---------------------------------------- 2288 * Configures the profiles for queues of egress port and traffic class 2289 */ 2290 #define MLXSW_REG_CWTP_ID 0x2802 2291 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2292 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2293 #define MLXSW_REG_CWTP_LEN 0x40 2294 2295 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2296 2297 /* reg_cwtp_local_port 2298 * Local port number 2299 * Not supported for CPU port 2300 * Access: Index 2301 */ 2302 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2303 2304 /* reg_cwtp_traffic_class 2305 * Traffic Class to configure 2306 * Access: Index 2307 */ 2308 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2309 2310 /* reg_cwtp_profile_min 2311 * Minimum Average Queue Size of the profile in cells. 2312 * Access: RW 2313 */ 2314 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2315 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2316 2317 /* reg_cwtp_profile_percent 2318 * Percentage of WRED and ECN marking for maximum Average Queue size 2319 * Range is 0 to 100, units of integer percentage 2320 * Access: RW 2321 */ 2322 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2323 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2324 2325 /* reg_cwtp_profile_max 2326 * Maximum Average Queue size of the profile in cells 2327 * Access: RW 2328 */ 2329 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2330 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2331 2332 #define MLXSW_REG_CWTP_MIN_VALUE 64 2333 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2334 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2335 2336 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2337 u8 traffic_class) 2338 { 2339 int i; 2340 2341 MLXSW_REG_ZERO(cwtp, payload); 2342 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2343 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2344 2345 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2346 mlxsw_reg_cwtp_profile_min_set(payload, i, 2347 MLXSW_REG_CWTP_MIN_VALUE); 2348 mlxsw_reg_cwtp_profile_max_set(payload, i, 2349 MLXSW_REG_CWTP_MIN_VALUE); 2350 } 2351 } 2352 2353 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2354 2355 static inline void 2356 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2357 u32 probability) 2358 { 2359 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2360 2361 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2362 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2363 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2364 } 2365 2366 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2367 * --------------------------------------------------- 2368 * The CWTPM register maps each egress port and traffic class to profile num. 2369 */ 2370 #define MLXSW_REG_CWTPM_ID 0x2803 2371 #define MLXSW_REG_CWTPM_LEN 0x44 2372 2373 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2374 2375 /* reg_cwtpm_local_port 2376 * Local port number 2377 * Not supported for CPU port 2378 * Access: Index 2379 */ 2380 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2381 2382 /* reg_cwtpm_traffic_class 2383 * Traffic Class to configure 2384 * Access: Index 2385 */ 2386 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2387 2388 /* reg_cwtpm_ew 2389 * Control enablement of WRED for traffic class: 2390 * 0 - Disable 2391 * 1 - Enable 2392 * Access: RW 2393 */ 2394 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2395 2396 /* reg_cwtpm_ee 2397 * Control enablement of ECN for traffic class: 2398 * 0 - Disable 2399 * 1 - Enable 2400 * Access: RW 2401 */ 2402 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2403 2404 /* reg_cwtpm_tcp_g 2405 * TCP Green Profile. 2406 * Index of the profile within {port, traffic class} to use. 2407 * 0 for disabling both WRED and ECN for this type of traffic. 2408 * Access: RW 2409 */ 2410 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2411 2412 /* reg_cwtpm_tcp_y 2413 * TCP Yellow Profile. 2414 * Index of the profile within {port, traffic class} to use. 2415 * 0 for disabling both WRED and ECN for this type of traffic. 2416 * Access: RW 2417 */ 2418 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2419 2420 /* reg_cwtpm_tcp_r 2421 * TCP Red Profile. 2422 * Index of the profile within {port, traffic class} to use. 2423 * 0 for disabling both WRED and ECN for this type of traffic. 2424 * Access: RW 2425 */ 2426 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2427 2428 /* reg_cwtpm_ntcp_g 2429 * Non-TCP Green Profile. 2430 * Index of the profile within {port, traffic class} to use. 2431 * 0 for disabling both WRED and ECN for this type of traffic. 2432 * Access: RW 2433 */ 2434 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2435 2436 /* reg_cwtpm_ntcp_y 2437 * Non-TCP Yellow Profile. 2438 * Index of the profile within {port, traffic class} to use. 2439 * 0 for disabling both WRED and ECN for this type of traffic. 2440 * Access: RW 2441 */ 2442 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2443 2444 /* reg_cwtpm_ntcp_r 2445 * Non-TCP Red Profile. 2446 * Index of the profile within {port, traffic class} to use. 2447 * 0 for disabling both WRED and ECN for this type of traffic. 2448 * Access: RW 2449 */ 2450 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2451 2452 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2453 2454 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2455 u8 traffic_class, u8 profile, 2456 bool wred, bool ecn) 2457 { 2458 MLXSW_REG_ZERO(cwtpm, payload); 2459 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2460 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2461 mlxsw_reg_cwtpm_ew_set(payload, wred); 2462 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2463 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2464 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2465 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2466 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2467 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2468 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2469 } 2470 2471 /* PGCR - Policy-Engine General Configuration Register 2472 * --------------------------------------------------- 2473 * This register configures general Policy-Engine settings. 2474 */ 2475 #define MLXSW_REG_PGCR_ID 0x3001 2476 #define MLXSW_REG_PGCR_LEN 0x20 2477 2478 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2479 2480 /* reg_pgcr_default_action_pointer_base 2481 * Default action pointer base. Each region has a default action pointer 2482 * which is equal to default_action_pointer_base + region_id. 2483 * Access: RW 2484 */ 2485 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2486 2487 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2488 { 2489 MLXSW_REG_ZERO(pgcr, payload); 2490 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2491 } 2492 2493 /* PPBT - Policy-Engine Port Binding Table 2494 * --------------------------------------- 2495 * This register is used for configuration of the Port Binding Table. 2496 */ 2497 #define MLXSW_REG_PPBT_ID 0x3002 2498 #define MLXSW_REG_PPBT_LEN 0x14 2499 2500 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2501 2502 enum mlxsw_reg_pxbt_e { 2503 MLXSW_REG_PXBT_E_IACL, 2504 MLXSW_REG_PXBT_E_EACL, 2505 }; 2506 2507 /* reg_ppbt_e 2508 * Access: Index 2509 */ 2510 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2511 2512 enum mlxsw_reg_pxbt_op { 2513 MLXSW_REG_PXBT_OP_BIND, 2514 MLXSW_REG_PXBT_OP_UNBIND, 2515 }; 2516 2517 /* reg_ppbt_op 2518 * Access: RW 2519 */ 2520 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2521 2522 /* reg_ppbt_local_port 2523 * Local port. Not including CPU port. 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2527 2528 /* reg_ppbt_g 2529 * group - When set, the binding is of an ACL group. When cleared, 2530 * the binding is of an ACL. 2531 * Must be set to 1 for Spectrum. 2532 * Access: RW 2533 */ 2534 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2535 2536 /* reg_ppbt_acl_info 2537 * ACL/ACL group identifier. If the g bit is set, this field should hold 2538 * the acl_group_id, else it should hold the acl_id. 2539 * Access: RW 2540 */ 2541 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2542 2543 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2544 enum mlxsw_reg_pxbt_op op, 2545 u16 local_port, u16 acl_info) 2546 { 2547 MLXSW_REG_ZERO(ppbt, payload); 2548 mlxsw_reg_ppbt_e_set(payload, e); 2549 mlxsw_reg_ppbt_op_set(payload, op); 2550 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2551 mlxsw_reg_ppbt_g_set(payload, true); 2552 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2553 } 2554 2555 /* PACL - Policy-Engine ACL Register 2556 * --------------------------------- 2557 * This register is used for configuration of the ACL. 2558 */ 2559 #define MLXSW_REG_PACL_ID 0x3004 2560 #define MLXSW_REG_PACL_LEN 0x70 2561 2562 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2563 2564 /* reg_pacl_v 2565 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2566 * while the ACL is bounded to either a port, VLAN or ACL rule. 2567 * Access: RW 2568 */ 2569 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2570 2571 /* reg_pacl_acl_id 2572 * An identifier representing the ACL (managed by software) 2573 * Range 0 .. cap_max_acl_regions - 1 2574 * Access: Index 2575 */ 2576 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2577 2578 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2579 2580 /* reg_pacl_tcam_region_info 2581 * Opaque object that represents a TCAM region. 2582 * Obtained through PTAR register. 2583 * Access: RW 2584 */ 2585 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2586 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2587 2588 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2589 bool valid, const char *tcam_region_info) 2590 { 2591 MLXSW_REG_ZERO(pacl, payload); 2592 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2593 mlxsw_reg_pacl_v_set(payload, valid); 2594 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2595 } 2596 2597 /* PAGT - Policy-Engine ACL Group Table 2598 * ------------------------------------ 2599 * This register is used for configuration of the ACL Group Table. 2600 */ 2601 #define MLXSW_REG_PAGT_ID 0x3005 2602 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2603 #define MLXSW_REG_PAGT_ACL_LEN 4 2604 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2605 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2606 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2607 2608 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2609 2610 /* reg_pagt_size 2611 * Number of ACLs in the group. 2612 * Size 0 invalidates a group. 2613 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2614 * Total number of ACLs in all groups must be lower or equal 2615 * to cap_max_acl_tot_groups 2616 * Note: a group which is binded must not be invalidated 2617 * Access: Index 2618 */ 2619 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2620 2621 /* reg_pagt_acl_group_id 2622 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2623 * the ACL Group identifier (managed by software). 2624 * Access: Index 2625 */ 2626 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2627 2628 /* reg_pagt_multi 2629 * Multi-ACL 2630 * 0 - This ACL is the last ACL in the multi-ACL 2631 * 1 - This ACL is part of a multi-ACL 2632 * Access: RW 2633 */ 2634 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2635 2636 /* reg_pagt_acl_id 2637 * ACL identifier 2638 * Access: RW 2639 */ 2640 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2641 2642 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2643 { 2644 MLXSW_REG_ZERO(pagt, payload); 2645 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2646 } 2647 2648 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2649 u16 acl_id, bool multi) 2650 { 2651 u8 size = mlxsw_reg_pagt_size_get(payload); 2652 2653 if (index >= size) 2654 mlxsw_reg_pagt_size_set(payload, index + 1); 2655 mlxsw_reg_pagt_multi_set(payload, index, multi); 2656 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2657 } 2658 2659 /* PTAR - Policy-Engine TCAM Allocation Register 2660 * --------------------------------------------- 2661 * This register is used for allocation of regions in the TCAM. 2662 * Note: Query method is not supported on this register. 2663 */ 2664 #define MLXSW_REG_PTAR_ID 0x3006 2665 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2666 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2667 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2668 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2669 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2670 2671 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2672 2673 enum mlxsw_reg_ptar_op { 2674 /* allocate a TCAM region */ 2675 MLXSW_REG_PTAR_OP_ALLOC, 2676 /* resize a TCAM region */ 2677 MLXSW_REG_PTAR_OP_RESIZE, 2678 /* deallocate TCAM region */ 2679 MLXSW_REG_PTAR_OP_FREE, 2680 /* test allocation */ 2681 MLXSW_REG_PTAR_OP_TEST, 2682 }; 2683 2684 /* reg_ptar_op 2685 * Access: OP 2686 */ 2687 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2688 2689 /* reg_ptar_action_set_type 2690 * Type of action set to be used on this region. 2691 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2692 * Access: WO 2693 */ 2694 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2695 2696 enum mlxsw_reg_ptar_key_type { 2697 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2698 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2699 }; 2700 2701 /* reg_ptar_key_type 2702 * TCAM key type for the region. 2703 * Access: WO 2704 */ 2705 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2706 2707 /* reg_ptar_region_size 2708 * TCAM region size. When allocating/resizing this is the requested size, 2709 * the response is the actual size. Note that actual size may be 2710 * larger than requested. 2711 * Allowed range 1 .. cap_max_rules-1 2712 * Reserved during op deallocate. 2713 * Access: WO 2714 */ 2715 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2716 2717 /* reg_ptar_region_id 2718 * Region identifier 2719 * Range 0 .. cap_max_regions-1 2720 * Access: Index 2721 */ 2722 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2723 2724 /* reg_ptar_tcam_region_info 2725 * Opaque object that represents the TCAM region. 2726 * Returned when allocating a region. 2727 * Provided by software for ACL generation and region deallocation and resize. 2728 * Access: RW 2729 */ 2730 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2731 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2732 2733 /* reg_ptar_flexible_key_id 2734 * Identifier of the Flexible Key. 2735 * Only valid if key_type == "FLEX_KEY" 2736 * The key size will be rounded up to one of the following values: 2737 * 9B, 18B, 36B, 54B. 2738 * This field is reserved for in resize operation. 2739 * Access: WO 2740 */ 2741 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2742 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2743 2744 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2745 enum mlxsw_reg_ptar_key_type key_type, 2746 u16 region_size, u16 region_id, 2747 const char *tcam_region_info) 2748 { 2749 MLXSW_REG_ZERO(ptar, payload); 2750 mlxsw_reg_ptar_op_set(payload, op); 2751 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2752 mlxsw_reg_ptar_key_type_set(payload, key_type); 2753 mlxsw_reg_ptar_region_size_set(payload, region_size); 2754 mlxsw_reg_ptar_region_id_set(payload, region_id); 2755 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2756 } 2757 2758 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2759 u16 key_id) 2760 { 2761 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2762 } 2763 2764 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2765 { 2766 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2767 } 2768 2769 /* PPBS - Policy-Engine Policy Based Switching Register 2770 * ---------------------------------------------------- 2771 * This register retrieves and sets Policy Based Switching Table entries. 2772 */ 2773 #define MLXSW_REG_PPBS_ID 0x300C 2774 #define MLXSW_REG_PPBS_LEN 0x14 2775 2776 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2777 2778 /* reg_ppbs_pbs_ptr 2779 * Index into the PBS table. 2780 * For Spectrum, the index points to the KVD Linear. 2781 * Access: Index 2782 */ 2783 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2784 2785 /* reg_ppbs_system_port 2786 * Unique port identifier for the final destination of the packet. 2787 * Access: RW 2788 */ 2789 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2790 2791 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2792 u16 system_port) 2793 { 2794 MLXSW_REG_ZERO(ppbs, payload); 2795 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2796 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2797 } 2798 2799 /* PRCR - Policy-Engine Rules Copy Register 2800 * ---------------------------------------- 2801 * This register is used for accessing rules within a TCAM region. 2802 */ 2803 #define MLXSW_REG_PRCR_ID 0x300D 2804 #define MLXSW_REG_PRCR_LEN 0x40 2805 2806 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2807 2808 enum mlxsw_reg_prcr_op { 2809 /* Move rules. Moves the rules from "tcam_region_info" starting 2810 * at offset "offset" to "dest_tcam_region_info" 2811 * at offset "dest_offset." 2812 */ 2813 MLXSW_REG_PRCR_OP_MOVE, 2814 /* Copy rules. Copies the rules from "tcam_region_info" starting 2815 * at offset "offset" to "dest_tcam_region_info" 2816 * at offset "dest_offset." 2817 */ 2818 MLXSW_REG_PRCR_OP_COPY, 2819 }; 2820 2821 /* reg_prcr_op 2822 * Access: OP 2823 */ 2824 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2825 2826 /* reg_prcr_offset 2827 * Offset within the source region to copy/move from. 2828 * Access: Index 2829 */ 2830 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2831 2832 /* reg_prcr_size 2833 * The number of rules to copy/move. 2834 * Access: WO 2835 */ 2836 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2837 2838 /* reg_prcr_tcam_region_info 2839 * Opaque object that represents the source TCAM region. 2840 * Access: Index 2841 */ 2842 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2843 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2844 2845 /* reg_prcr_dest_offset 2846 * Offset within the source region to copy/move to. 2847 * Access: Index 2848 */ 2849 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2850 2851 /* reg_prcr_dest_tcam_region_info 2852 * Opaque object that represents the destination TCAM region. 2853 * Access: Index 2854 */ 2855 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2856 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2857 2858 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2859 const char *src_tcam_region_info, 2860 u16 src_offset, 2861 const char *dest_tcam_region_info, 2862 u16 dest_offset, u16 size) 2863 { 2864 MLXSW_REG_ZERO(prcr, payload); 2865 mlxsw_reg_prcr_op_set(payload, op); 2866 mlxsw_reg_prcr_offset_set(payload, src_offset); 2867 mlxsw_reg_prcr_size_set(payload, size); 2868 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2869 src_tcam_region_info); 2870 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2871 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2872 dest_tcam_region_info); 2873 } 2874 2875 /* PEFA - Policy-Engine Extended Flexible Action Register 2876 * ------------------------------------------------------ 2877 * This register is used for accessing an extended flexible action entry 2878 * in the central KVD Linear Database. 2879 */ 2880 #define MLXSW_REG_PEFA_ID 0x300F 2881 #define MLXSW_REG_PEFA_LEN 0xB0 2882 2883 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2884 2885 /* reg_pefa_index 2886 * Index in the KVD Linear Centralized Database. 2887 * Access: Index 2888 */ 2889 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2890 2891 /* reg_pefa_a 2892 * Index in the KVD Linear Centralized Database. 2893 * Activity 2894 * For a new entry: set if ca=0, clear if ca=1 2895 * Set if a packet lookup has hit on the specific entry 2896 * Access: RO 2897 */ 2898 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2899 2900 /* reg_pefa_ca 2901 * Clear activity 2902 * When write: activity is according to this field 2903 * When read: after reading the activity is cleared according to ca 2904 * Access: OP 2905 */ 2906 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2907 2908 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2909 2910 /* reg_pefa_flex_action_set 2911 * Action-set to perform when rule is matched. 2912 * Must be zero padded if action set is shorter. 2913 * Access: RW 2914 */ 2915 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2916 2917 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2918 const char *flex_action_set) 2919 { 2920 MLXSW_REG_ZERO(pefa, payload); 2921 mlxsw_reg_pefa_index_set(payload, index); 2922 mlxsw_reg_pefa_ca_set(payload, ca); 2923 if (flex_action_set) 2924 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2925 flex_action_set); 2926 } 2927 2928 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2929 { 2930 *p_a = mlxsw_reg_pefa_a_get(payload); 2931 } 2932 2933 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2934 * -------------------------------------------------------------- 2935 * This register is used for binding Multicast router to an ACL group 2936 * that serves the MC router. 2937 * This register is not supported by SwitchX/-2 and Spectrum. 2938 */ 2939 #define MLXSW_REG_PEMRBT_ID 0x3014 2940 #define MLXSW_REG_PEMRBT_LEN 0x14 2941 2942 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2943 2944 enum mlxsw_reg_pemrbt_protocol { 2945 MLXSW_REG_PEMRBT_PROTO_IPV4, 2946 MLXSW_REG_PEMRBT_PROTO_IPV6, 2947 }; 2948 2949 /* reg_pemrbt_protocol 2950 * Access: Index 2951 */ 2952 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2953 2954 /* reg_pemrbt_group_id 2955 * ACL group identifier. 2956 * Range 0..cap_max_acl_groups-1 2957 * Access: RW 2958 */ 2959 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2960 2961 static inline void 2962 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2963 u16 group_id) 2964 { 2965 MLXSW_REG_ZERO(pemrbt, payload); 2966 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2967 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2968 } 2969 2970 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2971 * ----------------------------------------------------- 2972 * This register is used for accessing rules within a TCAM region. 2973 * It is a new version of PTCE in order to support wider key, 2974 * mask and action within a TCAM region. This register is not supported 2975 * by SwitchX and SwitchX-2. 2976 */ 2977 #define MLXSW_REG_PTCE2_ID 0x3017 2978 #define MLXSW_REG_PTCE2_LEN 0x1D8 2979 2980 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2981 2982 /* reg_ptce2_v 2983 * Valid. 2984 * Access: RW 2985 */ 2986 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2987 2988 /* reg_ptce2_a 2989 * Activity. Set if a packet lookup has hit on the specific entry. 2990 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2991 * Access: RO 2992 */ 2993 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2994 2995 enum mlxsw_reg_ptce2_op { 2996 /* Read operation. */ 2997 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2998 /* clear on read operation. Used to read entry 2999 * and clear Activity bit. 3000 */ 3001 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3002 /* Write operation. Used to write a new entry to the table. 3003 * All R/W fields are relevant for new entry. Activity bit is set 3004 * for new entries - Note write with v = 0 will delete the entry. 3005 */ 3006 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3007 /* Update action. Only action set will be updated. */ 3008 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3009 /* Clear activity. A bit is cleared for the entry. */ 3010 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3011 }; 3012 3013 /* reg_ptce2_op 3014 * Access: OP 3015 */ 3016 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3017 3018 /* reg_ptce2_offset 3019 * Access: Index 3020 */ 3021 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3022 3023 /* reg_ptce2_priority 3024 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3025 * Note: priority does not have to be unique per rule. 3026 * Within a region, higher priority should have lower offset (no limitation 3027 * between regions in a multi-region). 3028 * Access: RW 3029 */ 3030 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3031 3032 /* reg_ptce2_tcam_region_info 3033 * Opaque object that represents the TCAM region. 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3037 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3038 3039 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3040 3041 /* reg_ptce2_flex_key_blocks 3042 * ACL Key. 3043 * Access: RW 3044 */ 3045 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3046 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3047 3048 /* reg_ptce2_mask 3049 * mask- in the same size as key. A bit that is set directs the TCAM 3050 * to compare the corresponding bit in key. A bit that is clear directs 3051 * the TCAM to ignore the corresponding bit in key. 3052 * Access: RW 3053 */ 3054 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3055 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3056 3057 /* reg_ptce2_flex_action_set 3058 * ACL action set. 3059 * Access: RW 3060 */ 3061 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3062 MLXSW_REG_FLEX_ACTION_SET_LEN); 3063 3064 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3065 enum mlxsw_reg_ptce2_op op, 3066 const char *tcam_region_info, 3067 u16 offset, u32 priority) 3068 { 3069 MLXSW_REG_ZERO(ptce2, payload); 3070 mlxsw_reg_ptce2_v_set(payload, valid); 3071 mlxsw_reg_ptce2_op_set(payload, op); 3072 mlxsw_reg_ptce2_offset_set(payload, offset); 3073 mlxsw_reg_ptce2_priority_set(payload, priority); 3074 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3075 } 3076 3077 /* PERPT - Policy-Engine ERP Table Register 3078 * ---------------------------------------- 3079 * This register adds and removes eRPs from the eRP table. 3080 */ 3081 #define MLXSW_REG_PERPT_ID 0x3021 3082 #define MLXSW_REG_PERPT_LEN 0x80 3083 3084 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3085 3086 /* reg_perpt_erpt_bank 3087 * eRP table bank. 3088 * Range 0 .. cap_max_erp_table_banks - 1 3089 * Access: Index 3090 */ 3091 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3092 3093 /* reg_perpt_erpt_index 3094 * Index to eRP table within the eRP bank. 3095 * Range is 0 .. cap_max_erp_table_bank_size - 1 3096 * Access: Index 3097 */ 3098 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3099 3100 enum mlxsw_reg_perpt_key_size { 3101 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3102 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3103 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3104 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3105 }; 3106 3107 /* reg_perpt_key_size 3108 * Access: OP 3109 */ 3110 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3111 3112 /* reg_perpt_bf_bypass 3113 * 0 - The eRP is used only if bloom filter state is set for the given 3114 * rule. 3115 * 1 - The eRP is used regardless of bloom filter state. 3116 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3117 * Access: RW 3118 */ 3119 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3120 3121 /* reg_perpt_erp_id 3122 * eRP ID for use by the rules. 3123 * Access: RW 3124 */ 3125 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3126 3127 /* reg_perpt_erpt_base_bank 3128 * Base eRP table bank, points to head of erp_vector 3129 * Range is 0 .. cap_max_erp_table_banks - 1 3130 * Access: OP 3131 */ 3132 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3133 3134 /* reg_perpt_erpt_base_index 3135 * Base index to eRP table within the eRP bank 3136 * Range is 0 .. cap_max_erp_table_bank_size - 1 3137 * Access: OP 3138 */ 3139 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3140 3141 /* reg_perpt_erp_index_in_vector 3142 * eRP index in the vector. 3143 * Access: OP 3144 */ 3145 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3146 3147 /* reg_perpt_erp_vector 3148 * eRP vector. 3149 * Access: OP 3150 */ 3151 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3152 3153 /* reg_perpt_mask 3154 * Mask 3155 * 0 - A-TCAM will ignore the bit in key 3156 * 1 - A-TCAM will compare the bit in key 3157 * Access: RW 3158 */ 3159 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3160 3161 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3162 unsigned long *erp_vector, 3163 unsigned long size) 3164 { 3165 unsigned long bit; 3166 3167 for_each_set_bit(bit, erp_vector, size) 3168 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3169 } 3170 3171 static inline void 3172 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3173 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3174 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3175 char *mask) 3176 { 3177 MLXSW_REG_ZERO(perpt, payload); 3178 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3179 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3180 mlxsw_reg_perpt_key_size_set(payload, key_size); 3181 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3182 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3183 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3184 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3185 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3186 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3187 } 3188 3189 /* PERAR - Policy-Engine Region Association Register 3190 * ------------------------------------------------- 3191 * This register associates a hw region for region_id's. Changing on the fly 3192 * is supported by the device. 3193 */ 3194 #define MLXSW_REG_PERAR_ID 0x3026 3195 #define MLXSW_REG_PERAR_LEN 0x08 3196 3197 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3198 3199 /* reg_perar_region_id 3200 * Region identifier 3201 * Range 0 .. cap_max_regions-1 3202 * Access: Index 3203 */ 3204 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3205 3206 static inline unsigned int 3207 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3208 { 3209 return DIV_ROUND_UP(block_num, 4); 3210 } 3211 3212 /* reg_perar_hw_region 3213 * HW Region 3214 * Range 0 .. cap_max_regions-1 3215 * Default: hw_region = region_id 3216 * For a 8 key block region, 2 consecutive regions are used 3217 * For a 12 key block region, 3 consecutive regions are used 3218 * Access: RW 3219 */ 3220 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3221 3222 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3223 u16 hw_region) 3224 { 3225 MLXSW_REG_ZERO(perar, payload); 3226 mlxsw_reg_perar_region_id_set(payload, region_id); 3227 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3228 } 3229 3230 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3231 * ----------------------------------------------------- 3232 * This register is a new version of PTCE-V2 in order to support the 3233 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3234 */ 3235 #define MLXSW_REG_PTCE3_ID 0x3027 3236 #define MLXSW_REG_PTCE3_LEN 0xF0 3237 3238 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3239 3240 /* reg_ptce3_v 3241 * Valid. 3242 * Access: RW 3243 */ 3244 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3245 3246 enum mlxsw_reg_ptce3_op { 3247 /* Write operation. Used to write a new entry to the table. 3248 * All R/W fields are relevant for new entry. Activity bit is set 3249 * for new entries. Write with v = 0 will delete the entry. Must 3250 * not be used if an entry exists. 3251 */ 3252 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3253 /* Update operation */ 3254 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3255 /* Read operation */ 3256 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3257 }; 3258 3259 /* reg_ptce3_op 3260 * Access: OP 3261 */ 3262 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3263 3264 /* reg_ptce3_priority 3265 * Priority of the rule. Higher values win. 3266 * For Spectrum-2 range is 1..cap_kvd_size - 1 3267 * Note: Priority does not have to be unique per rule. 3268 * Access: RW 3269 */ 3270 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3271 3272 /* reg_ptce3_tcam_region_info 3273 * Opaque object that represents the TCAM region. 3274 * Access: Index 3275 */ 3276 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3277 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3278 3279 /* reg_ptce3_flex2_key_blocks 3280 * ACL key. The key must be masked according to eRP (if exists) or 3281 * according to master mask. 3282 * Access: Index 3283 */ 3284 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3285 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3286 3287 /* reg_ptce3_erp_id 3288 * eRP ID. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3292 3293 /* reg_ptce3_delta_start 3294 * Start point of delta_value and delta_mask, in bits. Must not exceed 3295 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3296 * Access: Index 3297 */ 3298 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3299 3300 /* reg_ptce3_delta_mask 3301 * Delta mask. 3302 * 0 - Ignore relevant bit in delta_value 3303 * 1 - Compare relevant bit in delta_value 3304 * Delta mask must not be set for reserved fields in the key blocks. 3305 * Note: No delta when no eRPs. Thus, for regions with 3306 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3307 * Access: Index 3308 */ 3309 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3310 3311 /* reg_ptce3_delta_value 3312 * Delta value. 3313 * Bits which are masked by delta_mask must be 0. 3314 * Access: Index 3315 */ 3316 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3317 3318 /* reg_ptce3_prune_vector 3319 * Pruning vector relative to the PERPT.erp_id. 3320 * Used for reducing lookups. 3321 * 0 - NEED: Do a lookup using the eRP. 3322 * 1 - PRUNE: Do not perform a lookup using the eRP. 3323 * Maybe be modified by PEAPBL and PEAPBM. 3324 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3325 * all 1's or all 0's. 3326 * Access: RW 3327 */ 3328 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3329 3330 /* reg_ptce3_prune_ctcam 3331 * Pruning on C-TCAM. Used for reducing lookups. 3332 * 0 - NEED: Do a lookup in the C-TCAM. 3333 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3334 * Access: RW 3335 */ 3336 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3337 3338 /* reg_ptce3_large_exists 3339 * Large entry key ID exists. 3340 * Within the region: 3341 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3342 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3343 * For rule delete: The MSB of the key will be removed. 3344 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3345 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3346 * For rule delete: The MSB of the key will not be removed. 3347 * Access: WO 3348 */ 3349 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3350 3351 /* reg_ptce3_large_entry_key_id 3352 * Large entry key ID. 3353 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3354 * blocks. Must be different for different keys which have the same common 3355 * 6 key blocks (MSB, blocks 6..11) key within a region. 3356 * Range is 0..cap_max_pe_large_key_id - 1 3357 * Access: RW 3358 */ 3359 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3360 3361 /* reg_ptce3_action_pointer 3362 * Pointer to action. 3363 * Range is 0..cap_max_kvd_action_sets - 1 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3367 3368 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3369 enum mlxsw_reg_ptce3_op op, 3370 u32 priority, 3371 const char *tcam_region_info, 3372 const char *key, u8 erp_id, 3373 u16 delta_start, u8 delta_mask, 3374 u8 delta_value, bool large_exists, 3375 u32 lkey_id, u32 action_pointer) 3376 { 3377 MLXSW_REG_ZERO(ptce3, payload); 3378 mlxsw_reg_ptce3_v_set(payload, valid); 3379 mlxsw_reg_ptce3_op_set(payload, op); 3380 mlxsw_reg_ptce3_priority_set(payload, priority); 3381 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3382 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3383 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3384 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3385 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3386 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3387 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3388 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3389 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3390 } 3391 3392 /* PERCR - Policy-Engine Region Configuration Register 3393 * --------------------------------------------------- 3394 * This register configures the region parameters. The region_id must be 3395 * allocated. 3396 */ 3397 #define MLXSW_REG_PERCR_ID 0x302A 3398 #define MLXSW_REG_PERCR_LEN 0x80 3399 3400 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3401 3402 /* reg_percr_region_id 3403 * Region identifier. 3404 * Range 0..cap_max_regions-1 3405 * Access: Index 3406 */ 3407 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3408 3409 /* reg_percr_atcam_ignore_prune 3410 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3411 * Access: RW 3412 */ 3413 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3414 3415 /* reg_percr_ctcam_ignore_prune 3416 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3417 * Access: RW 3418 */ 3419 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3420 3421 /* reg_percr_bf_bypass 3422 * Bloom filter bypass. 3423 * 0 - Bloom filter is used (default) 3424 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3425 * region_id or eRP. See PERPT.bf_bypass 3426 * Access: RW 3427 */ 3428 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3429 3430 /* reg_percr_master_mask 3431 * Master mask. Logical OR mask of all masks of all rules of a region 3432 * (both A-TCAM and C-TCAM). When there are no eRPs 3433 * (erpt_pointer_valid = 0), then this provides the mask. 3434 * Access: RW 3435 */ 3436 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3437 3438 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3439 { 3440 MLXSW_REG_ZERO(percr, payload); 3441 mlxsw_reg_percr_region_id_set(payload, region_id); 3442 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3443 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3444 mlxsw_reg_percr_bf_bypass_set(payload, false); 3445 } 3446 3447 /* PERERP - Policy-Engine Region eRP Register 3448 * ------------------------------------------ 3449 * This register configures the region eRP. The region_id must be 3450 * allocated. 3451 */ 3452 #define MLXSW_REG_PERERP_ID 0x302B 3453 #define MLXSW_REG_PERERP_LEN 0x1C 3454 3455 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3456 3457 /* reg_pererp_region_id 3458 * Region identifier. 3459 * Range 0..cap_max_regions-1 3460 * Access: Index 3461 */ 3462 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3463 3464 /* reg_pererp_ctcam_le 3465 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3469 3470 /* reg_pererp_erpt_pointer_valid 3471 * erpt_pointer is valid. 3472 * Access: RW 3473 */ 3474 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3475 3476 /* reg_pererp_erpt_bank_pointer 3477 * Pointer to eRP table bank. May be modified at any time. 3478 * Range 0..cap_max_erp_table_banks-1 3479 * Reserved when erpt_pointer_valid = 0 3480 */ 3481 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3482 3483 /* reg_pererp_erpt_pointer 3484 * Pointer to eRP table within the eRP bank. Can be changed for an 3485 * existing region. 3486 * Range 0..cap_max_erp_table_size-1 3487 * Reserved when erpt_pointer_valid = 0 3488 * Access: RW 3489 */ 3490 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3491 3492 /* reg_pererp_erpt_vector 3493 * Vector of allowed eRP indexes starting from erpt_pointer within the 3494 * erpt_bank_pointer. Next entries will be in next bank. 3495 * Note that eRP index is used and not eRP ID. 3496 * Reserved when erpt_pointer_valid = 0 3497 * Access: RW 3498 */ 3499 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3500 3501 /* reg_pererp_master_rp_id 3502 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3503 * for the lookup. Can be changed for an existing region. 3504 * Reserved when erpt_pointer_valid = 1 3505 * Access: RW 3506 */ 3507 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3508 3509 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3510 unsigned long *erp_vector, 3511 unsigned long size) 3512 { 3513 unsigned long bit; 3514 3515 for_each_set_bit(bit, erp_vector, size) 3516 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3517 } 3518 3519 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3520 bool ctcam_le, bool erpt_pointer_valid, 3521 u8 erpt_bank_pointer, u8 erpt_pointer, 3522 u8 master_rp_id) 3523 { 3524 MLXSW_REG_ZERO(pererp, payload); 3525 mlxsw_reg_pererp_region_id_set(payload, region_id); 3526 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3527 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3528 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3529 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3530 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3531 } 3532 3533 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3534 * ---------------------------------------------------------------- 3535 * This register configures the Bloom filter entries. 3536 */ 3537 #define MLXSW_REG_PEABFE_ID 0x3022 3538 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3539 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3540 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3541 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3542 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3543 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3544 3545 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3546 3547 /* reg_peabfe_size 3548 * Number of BF entries to be updated. 3549 * Range 1..256 3550 * Access: Op 3551 */ 3552 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3553 3554 /* reg_peabfe_bf_entry_state 3555 * Bloom filter state 3556 * 0 - Clear 3557 * 1 - Set 3558 * Access: RW 3559 */ 3560 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3561 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3562 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3563 3564 /* reg_peabfe_bf_entry_bank 3565 * Bloom filter bank ID 3566 * Range 0..cap_max_erp_table_banks-1 3567 * Access: Index 3568 */ 3569 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3570 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3571 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3572 3573 /* reg_peabfe_bf_entry_index 3574 * Bloom filter entry index 3575 * Range 0..2^cap_max_bf_log-1 3576 * Access: Index 3577 */ 3578 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3579 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3580 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3581 3582 static inline void mlxsw_reg_peabfe_pack(char *payload) 3583 { 3584 MLXSW_REG_ZERO(peabfe, payload); 3585 } 3586 3587 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3588 u8 state, u8 bank, u32 bf_index) 3589 { 3590 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3591 3592 if (rec_index >= num_rec) 3593 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3594 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3595 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3596 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3597 } 3598 3599 /* IEDR - Infrastructure Entry Delete Register 3600 * ---------------------------------------------------- 3601 * This register is used for deleting entries from the entry tables. 3602 * It is legitimate to attempt to delete a nonexisting entry (the device will 3603 * respond as a good flow). 3604 */ 3605 #define MLXSW_REG_IEDR_ID 0x3804 3606 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3607 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3608 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3609 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3610 MLXSW_REG_IEDR_REC_LEN * \ 3611 MLXSW_REG_IEDR_REC_MAX_COUNT) 3612 3613 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3614 3615 /* reg_iedr_num_rec 3616 * Number of records. 3617 * Access: OP 3618 */ 3619 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3620 3621 /* reg_iedr_rec_type 3622 * Resource type. 3623 * Access: OP 3624 */ 3625 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3626 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3627 3628 /* reg_iedr_rec_size 3629 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3630 * Access: OP 3631 */ 3632 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3633 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3634 3635 /* reg_iedr_rec_index_start 3636 * Resource index start. 3637 * Access: OP 3638 */ 3639 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3640 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3641 3642 static inline void mlxsw_reg_iedr_pack(char *payload) 3643 { 3644 MLXSW_REG_ZERO(iedr, payload); 3645 } 3646 3647 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3648 u8 rec_type, u16 rec_size, 3649 u32 rec_index_start) 3650 { 3651 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3652 3653 if (rec_index >= num_rec) 3654 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3655 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3656 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3657 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3658 } 3659 3660 /* QPTS - QoS Priority Trust State Register 3661 * ---------------------------------------- 3662 * This register controls the port policy to calculate the switch priority and 3663 * packet color based on incoming packet fields. 3664 */ 3665 #define MLXSW_REG_QPTS_ID 0x4002 3666 #define MLXSW_REG_QPTS_LEN 0x8 3667 3668 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3669 3670 /* reg_qpts_local_port 3671 * Local port number. 3672 * Access: Index 3673 * 3674 * Note: CPU port is supported. 3675 */ 3676 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3677 3678 enum mlxsw_reg_qpts_trust_state { 3679 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3680 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3681 }; 3682 3683 /* reg_qpts_trust_state 3684 * Trust state for a given port. 3685 * Access: RW 3686 */ 3687 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3688 3689 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3690 enum mlxsw_reg_qpts_trust_state ts) 3691 { 3692 MLXSW_REG_ZERO(qpts, payload); 3693 3694 mlxsw_reg_qpts_local_port_set(payload, local_port); 3695 mlxsw_reg_qpts_trust_state_set(payload, ts); 3696 } 3697 3698 /* QPCR - QoS Policer Configuration Register 3699 * ----------------------------------------- 3700 * The QPCR register is used to create policers - that limit 3701 * the rate of bytes or packets via some trap group. 3702 */ 3703 #define MLXSW_REG_QPCR_ID 0x4004 3704 #define MLXSW_REG_QPCR_LEN 0x28 3705 3706 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3707 3708 enum mlxsw_reg_qpcr_g { 3709 MLXSW_REG_QPCR_G_GLOBAL = 2, 3710 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3711 }; 3712 3713 /* reg_qpcr_g 3714 * The policer type. 3715 * Access: Index 3716 */ 3717 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3718 3719 /* reg_qpcr_pid 3720 * Policer ID. 3721 * Access: Index 3722 */ 3723 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3724 3725 /* reg_qpcr_clear_counter 3726 * Clear counters. 3727 * Access: OP 3728 */ 3729 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3730 3731 /* reg_qpcr_color_aware 3732 * Is the policer aware of colors. 3733 * Must be 0 (unaware) for cpu port. 3734 * Access: RW for unbounded policer. RO for bounded policer. 3735 */ 3736 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3737 3738 /* reg_qpcr_bytes 3739 * Is policer limit is for bytes per sec or packets per sec. 3740 * 0 - packets 3741 * 1 - bytes 3742 * Access: RW for unbounded policer. RO for bounded policer. 3743 */ 3744 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3745 3746 enum mlxsw_reg_qpcr_ir_units { 3747 MLXSW_REG_QPCR_IR_UNITS_M, 3748 MLXSW_REG_QPCR_IR_UNITS_K, 3749 }; 3750 3751 /* reg_qpcr_ir_units 3752 * Policer's units for cir and eir fields (for bytes limits only) 3753 * 1 - 10^3 3754 * 0 - 10^6 3755 * Access: OP 3756 */ 3757 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3758 3759 enum mlxsw_reg_qpcr_rate_type { 3760 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3761 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3762 }; 3763 3764 /* reg_qpcr_rate_type 3765 * Policer can have one limit (single rate) or 2 limits with specific operation 3766 * for packets that exceed the lower rate but not the upper one. 3767 * (For cpu port must be single rate) 3768 * Access: RW for unbounded policer. RO for bounded policer. 3769 */ 3770 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3771 3772 /* reg_qpc_cbs 3773 * Policer's committed burst size. 3774 * The policer is working with time slices of 50 nano sec. By default every 3775 * slice is granted the proportionate share of the committed rate. If we want to 3776 * allow a slice to exceed that share (while still keeping the rate per sec) we 3777 * can allow burst. The burst size is between the default proportionate share 3778 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3779 * committed rate will result in exceeding the rate). The burst size must be a 3780 * log of 2 and will be determined by 2^cbs. 3781 * Access: RW 3782 */ 3783 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3784 3785 /* reg_qpcr_cir 3786 * Policer's committed rate. 3787 * The rate used for sungle rate, the lower rate for double rate. 3788 * For bytes limits, the rate will be this value * the unit from ir_units. 3789 * (Resolution error is up to 1%). 3790 * Access: RW 3791 */ 3792 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3793 3794 /* reg_qpcr_eir 3795 * Policer's exceed rate. 3796 * The higher rate for double rate, reserved for single rate. 3797 * Lower rate for double rate policer. 3798 * For bytes limits, the rate will be this value * the unit from ir_units. 3799 * (Resolution error is up to 1%). 3800 * Access: RW 3801 */ 3802 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3803 3804 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3805 3806 /* reg_qpcr_exceed_action. 3807 * What to do with packets between the 2 limits for double rate. 3808 * Access: RW for unbounded policer. RO for bounded policer. 3809 */ 3810 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3811 3812 enum mlxsw_reg_qpcr_action { 3813 /* Discard */ 3814 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3815 /* Forward and set color to red. 3816 * If the packet is intended to cpu port, it will be dropped. 3817 */ 3818 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3819 }; 3820 3821 /* reg_qpcr_violate_action 3822 * What to do with packets that cross the cir limit (for single rate) or the eir 3823 * limit (for double rate). 3824 * Access: RW for unbounded policer. RO for bounded policer. 3825 */ 3826 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3827 3828 /* reg_qpcr_violate_count 3829 * Counts the number of times violate_action happened on this PID. 3830 * Access: RW 3831 */ 3832 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3833 3834 /* Packets */ 3835 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3836 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3837 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3838 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3839 3840 /* Bandwidth */ 3841 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3842 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3843 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3844 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3845 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3846 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3847 3848 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3849 enum mlxsw_reg_qpcr_ir_units ir_units, 3850 bool bytes, u32 cir, u16 cbs) 3851 { 3852 MLXSW_REG_ZERO(qpcr, payload); 3853 mlxsw_reg_qpcr_pid_set(payload, pid); 3854 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3855 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3856 mlxsw_reg_qpcr_violate_action_set(payload, 3857 MLXSW_REG_QPCR_ACTION_DISCARD); 3858 mlxsw_reg_qpcr_cir_set(payload, cir); 3859 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3860 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3861 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3862 } 3863 3864 /* QTCT - QoS Switch Traffic Class Table 3865 * ------------------------------------- 3866 * Configures the mapping between the packet switch priority and the 3867 * traffic class on the transmit port. 3868 */ 3869 #define MLXSW_REG_QTCT_ID 0x400A 3870 #define MLXSW_REG_QTCT_LEN 0x08 3871 3872 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3873 3874 /* reg_qtct_local_port 3875 * Local port number. 3876 * Access: Index 3877 * 3878 * Note: CPU port is not supported. 3879 */ 3880 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3881 3882 /* reg_qtct_sub_port 3883 * Virtual port within the physical port. 3884 * Should be set to 0 when virtual ports are not enabled on the port. 3885 * Access: Index 3886 */ 3887 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3888 3889 /* reg_qtct_switch_prio 3890 * Switch priority. 3891 * Access: Index 3892 */ 3893 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3894 3895 /* reg_qtct_tclass 3896 * Traffic class. 3897 * Default values: 3898 * switch_prio 0 : tclass 1 3899 * switch_prio 1 : tclass 0 3900 * switch_prio i : tclass i, for i > 1 3901 * Access: RW 3902 */ 3903 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3904 3905 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3906 u8 switch_prio, u8 tclass) 3907 { 3908 MLXSW_REG_ZERO(qtct, payload); 3909 mlxsw_reg_qtct_local_port_set(payload, local_port); 3910 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3911 mlxsw_reg_qtct_tclass_set(payload, tclass); 3912 } 3913 3914 /* QEEC - QoS ETS Element Configuration Register 3915 * --------------------------------------------- 3916 * Configures the ETS elements. 3917 */ 3918 #define MLXSW_REG_QEEC_ID 0x400D 3919 #define MLXSW_REG_QEEC_LEN 0x20 3920 3921 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3922 3923 /* reg_qeec_local_port 3924 * Local port number. 3925 * Access: Index 3926 * 3927 * Note: CPU port is supported. 3928 */ 3929 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3930 3931 enum mlxsw_reg_qeec_hr { 3932 MLXSW_REG_QEEC_HR_PORT, 3933 MLXSW_REG_QEEC_HR_GROUP, 3934 MLXSW_REG_QEEC_HR_SUBGROUP, 3935 MLXSW_REG_QEEC_HR_TC, 3936 }; 3937 3938 /* reg_qeec_element_hierarchy 3939 * 0 - Port 3940 * 1 - Group 3941 * 2 - Subgroup 3942 * 3 - Traffic Class 3943 * Access: Index 3944 */ 3945 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3946 3947 /* reg_qeec_element_index 3948 * The index of the element in the hierarchy. 3949 * Access: Index 3950 */ 3951 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3952 3953 /* reg_qeec_next_element_index 3954 * The index of the next (lower) element in the hierarchy. 3955 * Access: RW 3956 * 3957 * Note: Reserved for element_hierarchy 0. 3958 */ 3959 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3960 3961 /* reg_qeec_mise 3962 * Min shaper configuration enable. Enables configuration of the min 3963 * shaper on this ETS element 3964 * 0 - Disable 3965 * 1 - Enable 3966 * Access: RW 3967 */ 3968 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3969 3970 /* reg_qeec_ptps 3971 * PTP shaper 3972 * 0: regular shaper mode 3973 * 1: PTP oriented shaper 3974 * Allowed only for hierarchy 0 3975 * Not supported for CPU port 3976 * Note that ptps mode may affect the shaper rates of all hierarchies 3977 * Supported only on Spectrum-1 3978 * Access: RW 3979 */ 3980 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3981 3982 enum { 3983 MLXSW_REG_QEEC_BYTES_MODE, 3984 MLXSW_REG_QEEC_PACKETS_MODE, 3985 }; 3986 3987 /* reg_qeec_pb 3988 * Packets or bytes mode. 3989 * 0 - Bytes mode 3990 * 1 - Packets mode 3991 * Access: RW 3992 * 3993 * Note: Used for max shaper configuration. For Spectrum, packets mode 3994 * is supported only for traffic classes of CPU port. 3995 */ 3996 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3997 3998 /* The smallest permitted min shaper rate. */ 3999 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4000 4001 /* reg_qeec_min_shaper_rate 4002 * Min shaper information rate. 4003 * For CPU port, can only be configured for port hierarchy. 4004 * When in bytes mode, value is specified in units of 1000bps. 4005 * Access: RW 4006 */ 4007 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4008 4009 /* reg_qeec_mase 4010 * Max shaper configuration enable. Enables configuration of the max 4011 * shaper on this ETS element. 4012 * 0 - Disable 4013 * 1 - Enable 4014 * Access: RW 4015 */ 4016 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4017 4018 /* The largest max shaper value possible to disable the shaper. */ 4019 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4020 4021 /* reg_qeec_max_shaper_rate 4022 * Max shaper information rate. 4023 * For CPU port, can only be configured for port hierarchy. 4024 * When in bytes mode, value is specified in units of 1000bps. 4025 * Access: RW 4026 */ 4027 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4028 4029 /* reg_qeec_de 4030 * DWRR configuration enable. Enables configuration of the dwrr and 4031 * dwrr_weight. 4032 * 0 - Disable 4033 * 1 - Enable 4034 * Access: RW 4035 */ 4036 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4037 4038 /* reg_qeec_dwrr 4039 * Transmission selection algorithm to use on the link going down from 4040 * the ETS element. 4041 * 0 - Strict priority 4042 * 1 - DWRR 4043 * Access: RW 4044 */ 4045 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4046 4047 /* reg_qeec_dwrr_weight 4048 * DWRR weight on the link going down from the ETS element. The 4049 * percentage of bandwidth guaranteed to an ETS element within 4050 * its hierarchy. The sum of all weights across all ETS elements 4051 * within one hierarchy should be equal to 100. Reserved when 4052 * transmission selection algorithm is strict priority. 4053 * Access: RW 4054 */ 4055 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4056 4057 /* reg_qeec_max_shaper_bs 4058 * Max shaper burst size 4059 * Burst size is 2^max_shaper_bs * 512 bits 4060 * For Spectrum-1: Range is: 5..25 4061 * For Spectrum-2: Range is: 11..25 4062 * Reserved when ptps = 1 4063 * Access: RW 4064 */ 4065 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4066 4067 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4068 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4069 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4070 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4071 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4072 4073 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4074 enum mlxsw_reg_qeec_hr hr, u8 index, 4075 u8 next_index) 4076 { 4077 MLXSW_REG_ZERO(qeec, payload); 4078 mlxsw_reg_qeec_local_port_set(payload, local_port); 4079 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4080 mlxsw_reg_qeec_element_index_set(payload, index); 4081 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4082 } 4083 4084 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4085 bool ptps) 4086 { 4087 MLXSW_REG_ZERO(qeec, payload); 4088 mlxsw_reg_qeec_local_port_set(payload, local_port); 4089 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4090 mlxsw_reg_qeec_ptps_set(payload, ptps); 4091 } 4092 4093 /* QRWE - QoS ReWrite Enable 4094 * ------------------------- 4095 * This register configures the rewrite enable per receive port. 4096 */ 4097 #define MLXSW_REG_QRWE_ID 0x400F 4098 #define MLXSW_REG_QRWE_LEN 0x08 4099 4100 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4101 4102 /* reg_qrwe_local_port 4103 * Local port number. 4104 * Access: Index 4105 * 4106 * Note: CPU port is supported. No support for router port. 4107 */ 4108 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4109 4110 /* reg_qrwe_dscp 4111 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4112 * Access: RW 4113 */ 4114 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4115 4116 /* reg_qrwe_pcp 4117 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4118 * Access: RW 4119 */ 4120 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4121 4122 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4123 bool rewrite_pcp, bool rewrite_dscp) 4124 { 4125 MLXSW_REG_ZERO(qrwe, payload); 4126 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4127 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4128 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4129 } 4130 4131 /* QPDSM - QoS Priority to DSCP Mapping 4132 * ------------------------------------ 4133 * QoS Priority to DSCP Mapping Register 4134 */ 4135 #define MLXSW_REG_QPDSM_ID 0x4011 4136 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4137 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4138 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4139 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4140 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4141 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4142 4143 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4144 4145 /* reg_qpdsm_local_port 4146 * Local Port. Supported for data packets from CPU port. 4147 * Access: Index 4148 */ 4149 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4150 4151 /* reg_qpdsm_prio_entry_color0_e 4152 * Enable update of the entry for color 0 and a given port. 4153 * Access: WO 4154 */ 4155 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4156 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4157 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4158 4159 /* reg_qpdsm_prio_entry_color0_dscp 4160 * DSCP field in the outer label of the packet for color 0 and a given port. 4161 * Reserved when e=0. 4162 * Access: RW 4163 */ 4164 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4165 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4166 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4167 4168 /* reg_qpdsm_prio_entry_color1_e 4169 * Enable update of the entry for color 1 and a given port. 4170 * Access: WO 4171 */ 4172 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4173 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4174 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4175 4176 /* reg_qpdsm_prio_entry_color1_dscp 4177 * DSCP field in the outer label of the packet for color 1 and a given port. 4178 * Reserved when e=0. 4179 * Access: RW 4180 */ 4181 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4182 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4183 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4184 4185 /* reg_qpdsm_prio_entry_color2_e 4186 * Enable update of the entry for color 2 and a given port. 4187 * Access: WO 4188 */ 4189 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4190 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4191 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4192 4193 /* reg_qpdsm_prio_entry_color2_dscp 4194 * DSCP field in the outer label of the packet for color 2 and a given port. 4195 * Reserved when e=0. 4196 * Access: RW 4197 */ 4198 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4199 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4200 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4201 4202 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4203 { 4204 MLXSW_REG_ZERO(qpdsm, payload); 4205 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4206 } 4207 4208 static inline void 4209 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4210 { 4211 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4212 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4213 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4214 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4215 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4216 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4217 } 4218 4219 /* QPDP - QoS Port DSCP to Priority Mapping Register 4220 * ------------------------------------------------- 4221 * This register controls the port default Switch Priority and Color. The 4222 * default Switch Priority and Color are used for frames where the trust state 4223 * uses default values. All member ports of a LAG should be configured with the 4224 * same default values. 4225 */ 4226 #define MLXSW_REG_QPDP_ID 0x4007 4227 #define MLXSW_REG_QPDP_LEN 0x8 4228 4229 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4230 4231 /* reg_qpdp_local_port 4232 * Local Port. Supported for data packets from CPU port. 4233 * Access: Index 4234 */ 4235 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4236 4237 /* reg_qpdp_switch_prio 4238 * Default port Switch Priority (default 0) 4239 * Access: RW 4240 */ 4241 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4242 4243 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4244 u8 switch_prio) 4245 { 4246 MLXSW_REG_ZERO(qpdp, payload); 4247 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4248 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4249 } 4250 4251 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4252 * -------------------------------------------------- 4253 * This register controls the mapping from DSCP field to 4254 * Switch Priority for IP packets. 4255 */ 4256 #define MLXSW_REG_QPDPM_ID 0x4013 4257 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4258 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4259 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4260 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4261 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4262 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4263 4264 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4265 4266 /* reg_qpdpm_local_port 4267 * Local Port. Supported for data packets from CPU port. 4268 * Access: Index 4269 */ 4270 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4271 4272 /* reg_qpdpm_dscp_e 4273 * Enable update of the specific entry. When cleared, the switch_prio and color 4274 * fields are ignored and the previous switch_prio and color values are 4275 * preserved. 4276 * Access: WO 4277 */ 4278 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4279 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4280 4281 /* reg_qpdpm_dscp_prio 4282 * The new Switch Priority value for the relevant DSCP value. 4283 * Access: RW 4284 */ 4285 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4286 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4287 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4288 4289 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4290 { 4291 MLXSW_REG_ZERO(qpdpm, payload); 4292 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4293 } 4294 4295 static inline void 4296 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4297 { 4298 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4299 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4300 } 4301 4302 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4303 * ------------------------------------------------------------------ 4304 * This register configures if the Switch Priority to Traffic Class mapping is 4305 * based on Multicast packet indication. If so, then multicast packets will get 4306 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4307 * QTCT. 4308 * By default, Switch Priority to Traffic Class mapping is not based on 4309 * Multicast packet indication. 4310 */ 4311 #define MLXSW_REG_QTCTM_ID 0x401A 4312 #define MLXSW_REG_QTCTM_LEN 0x08 4313 4314 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4315 4316 /* reg_qtctm_local_port 4317 * Local port number. 4318 * No support for CPU port. 4319 * Access: Index 4320 */ 4321 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4322 4323 /* reg_qtctm_mc 4324 * Multicast Mode 4325 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4326 * indication (default is 0, not based on Multicast packet indication). 4327 */ 4328 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4329 4330 static inline void 4331 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4332 { 4333 MLXSW_REG_ZERO(qtctm, payload); 4334 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4335 mlxsw_reg_qtctm_mc_set(payload, mc); 4336 } 4337 4338 /* QPSC - QoS PTP Shaper Configuration Register 4339 * -------------------------------------------- 4340 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4341 * Supported only on Spectrum-1. 4342 */ 4343 #define MLXSW_REG_QPSC_ID 0x401B 4344 #define MLXSW_REG_QPSC_LEN 0x28 4345 4346 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4347 4348 enum mlxsw_reg_qpsc_port_speed { 4349 MLXSW_REG_QPSC_PORT_SPEED_100M, 4350 MLXSW_REG_QPSC_PORT_SPEED_1G, 4351 MLXSW_REG_QPSC_PORT_SPEED_10G, 4352 MLXSW_REG_QPSC_PORT_SPEED_25G, 4353 }; 4354 4355 /* reg_qpsc_port_speed 4356 * Port speed. 4357 * Access: Index 4358 */ 4359 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4360 4361 /* reg_qpsc_shaper_time_exp 4362 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4363 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4364 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4365 * Access: RW 4366 */ 4367 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4368 4369 /* reg_qpsc_shaper_time_mantissa 4370 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4371 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4372 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4373 * Access: RW 4374 */ 4375 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4376 4377 /* reg_qpsc_shaper_inc 4378 * Number of tokens added to shaper on each update. 4379 * Units of 8B. 4380 * Access: RW 4381 */ 4382 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4383 4384 /* reg_qpsc_shaper_bs 4385 * Max shaper Burst size. 4386 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4387 * Range is: 5..25 (from 2KB..2GB) 4388 * Access: RW 4389 */ 4390 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4391 4392 /* reg_qpsc_ptsc_we 4393 * Write enable to port_to_shaper_credits. 4394 * Access: WO 4395 */ 4396 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4397 4398 /* reg_qpsc_port_to_shaper_credits 4399 * For split ports: range 1..57 4400 * For non-split ports: range 1..112 4401 * Written only when ptsc_we is set. 4402 * Access: RW 4403 */ 4404 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4405 4406 /* reg_qpsc_ing_timestamp_inc 4407 * Ingress timestamp increment. 4408 * 2's complement. 4409 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4410 * value for all ports. 4411 * Same units as used by MTPPTR. 4412 * Access: RW 4413 */ 4414 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4415 4416 /* reg_qpsc_egr_timestamp_inc 4417 * Egress timestamp increment. 4418 * 2's complement. 4419 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4420 * value for all ports. 4421 * Same units as used by MTPPTR. 4422 * Access: RW 4423 */ 4424 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4425 4426 static inline void 4427 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4428 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4429 u8 shaper_bs, u8 port_to_shaper_credits, 4430 int ing_timestamp_inc, int egr_timestamp_inc) 4431 { 4432 MLXSW_REG_ZERO(qpsc, payload); 4433 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4434 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4435 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4436 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4437 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4438 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4439 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4440 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4441 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4442 } 4443 4444 /* PMLP - Ports Module to Local Port Register 4445 * ------------------------------------------ 4446 * Configures the assignment of modules to local ports. 4447 */ 4448 #define MLXSW_REG_PMLP_ID 0x5002 4449 #define MLXSW_REG_PMLP_LEN 0x40 4450 4451 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4452 4453 /* reg_pmlp_rxtx 4454 * 0 - Tx value is used for both Tx and Rx. 4455 * 1 - Rx value is taken from a separte field. 4456 * Access: RW 4457 */ 4458 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4459 4460 /* reg_pmlp_local_port 4461 * Local port number. 4462 * Access: Index 4463 */ 4464 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4465 4466 /* reg_pmlp_width 4467 * 0 - Unmap local port. 4468 * 1 - Lane 0 is used. 4469 * 2 - Lanes 0 and 1 are used. 4470 * 4 - Lanes 0, 1, 2 and 3 are used. 4471 * 8 - Lanes 0-7 are used. 4472 * Access: RW 4473 */ 4474 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4475 4476 /* reg_pmlp_module 4477 * Module number. 4478 * Access: RW 4479 */ 4480 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4481 4482 /* reg_pmlp_slot_index 4483 * Module number. 4484 * Slot_index 4485 * Slot_index = 0 represent the onboard (motherboard). 4486 * In case of non-modular system only slot_index = 0 is available. 4487 * Access: RW 4488 */ 4489 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4490 4491 /* reg_pmlp_tx_lane 4492 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4493 * Access: RW 4494 */ 4495 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4496 4497 /* reg_pmlp_rx_lane 4498 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4499 * equal to Tx lane. 4500 * Access: RW 4501 */ 4502 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4503 4504 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4505 { 4506 MLXSW_REG_ZERO(pmlp, payload); 4507 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4508 } 4509 4510 /* PMTU - Port MTU Register 4511 * ------------------------ 4512 * Configures and reports the port MTU. 4513 */ 4514 #define MLXSW_REG_PMTU_ID 0x5003 4515 #define MLXSW_REG_PMTU_LEN 0x10 4516 4517 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4518 4519 /* reg_pmtu_local_port 4520 * Local port number. 4521 * Access: Index 4522 */ 4523 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4524 4525 /* reg_pmtu_max_mtu 4526 * Maximum MTU. 4527 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4528 * reported, otherwise the minimum between the max_mtu of the different 4529 * types is reported. 4530 * Access: RO 4531 */ 4532 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4533 4534 /* reg_pmtu_admin_mtu 4535 * MTU value to set port to. Must be smaller or equal to max_mtu. 4536 * Note: If port type is Infiniband, then port must be disabled, when its 4537 * MTU is set. 4538 * Access: RW 4539 */ 4540 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4541 4542 /* reg_pmtu_oper_mtu 4543 * The actual MTU configured on the port. Packets exceeding this size 4544 * will be dropped. 4545 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4546 * oper_mtu might be smaller than admin_mtu. 4547 * Access: RO 4548 */ 4549 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4550 4551 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4552 u16 new_mtu) 4553 { 4554 MLXSW_REG_ZERO(pmtu, payload); 4555 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4556 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4557 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4558 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4559 } 4560 4561 /* PTYS - Port Type and Speed Register 4562 * ----------------------------------- 4563 * Configures and reports the port speed type. 4564 * 4565 * Note: When set while the link is up, the changes will not take effect 4566 * until the port transitions from down to up state. 4567 */ 4568 #define MLXSW_REG_PTYS_ID 0x5004 4569 #define MLXSW_REG_PTYS_LEN 0x40 4570 4571 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4572 4573 /* an_disable_admin 4574 * Auto negotiation disable administrative configuration 4575 * 0 - Device doesn't support AN disable. 4576 * 1 - Device supports AN disable. 4577 * Access: RW 4578 */ 4579 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4580 4581 /* reg_ptys_local_port 4582 * Local port number. 4583 * Access: Index 4584 */ 4585 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4586 4587 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4588 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4589 4590 /* reg_ptys_proto_mask 4591 * Protocol mask. Indicates which protocol is used. 4592 * 0 - Infiniband. 4593 * 1 - Fibre Channel. 4594 * 2 - Ethernet. 4595 * Access: Index 4596 */ 4597 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4598 4599 enum { 4600 MLXSW_REG_PTYS_AN_STATUS_NA, 4601 MLXSW_REG_PTYS_AN_STATUS_OK, 4602 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4603 }; 4604 4605 /* reg_ptys_an_status 4606 * Autonegotiation status. 4607 * Access: RO 4608 */ 4609 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4610 4611 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4612 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4613 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4614 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4615 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4616 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4617 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4618 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4619 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4620 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4621 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4622 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4623 4624 /* reg_ptys_ext_eth_proto_cap 4625 * Extended Ethernet port supported speeds and protocols. 4626 * Access: RO 4627 */ 4628 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4629 4630 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4631 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4632 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4633 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4634 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4635 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4636 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4637 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4638 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4639 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4640 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4641 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4642 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4643 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4644 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4645 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4646 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4647 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4648 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4649 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4650 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4651 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4652 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4653 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4654 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4655 4656 /* reg_ptys_eth_proto_cap 4657 * Ethernet port supported speeds and protocols. 4658 * Access: RO 4659 */ 4660 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4661 4662 /* reg_ptys_ext_eth_proto_admin 4663 * Extended speed and protocol to set port to. 4664 * Access: RW 4665 */ 4666 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4667 4668 /* reg_ptys_eth_proto_admin 4669 * Speed and protocol to set port to. 4670 * Access: RW 4671 */ 4672 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4673 4674 /* reg_ptys_ext_eth_proto_oper 4675 * The extended current speed and protocol configured for the port. 4676 * Access: RO 4677 */ 4678 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4679 4680 /* reg_ptys_eth_proto_oper 4681 * The current speed and protocol configured for the port. 4682 * Access: RO 4683 */ 4684 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4685 4686 enum mlxsw_reg_ptys_connector_type { 4687 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4688 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4689 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4690 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4691 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4692 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4693 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4694 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4695 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4696 }; 4697 4698 /* reg_ptys_connector_type 4699 * Connector type indication. 4700 * Access: RO 4701 */ 4702 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4703 4704 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4705 u32 proto_admin, bool autoneg) 4706 { 4707 MLXSW_REG_ZERO(ptys, payload); 4708 mlxsw_reg_ptys_local_port_set(payload, local_port); 4709 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4710 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4711 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4712 } 4713 4714 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4715 u32 proto_admin, bool autoneg) 4716 { 4717 MLXSW_REG_ZERO(ptys, payload); 4718 mlxsw_reg_ptys_local_port_set(payload, local_port); 4719 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4720 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4721 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4722 } 4723 4724 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4725 u32 *p_eth_proto_cap, 4726 u32 *p_eth_proto_admin, 4727 u32 *p_eth_proto_oper) 4728 { 4729 if (p_eth_proto_cap) 4730 *p_eth_proto_cap = 4731 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4732 if (p_eth_proto_admin) 4733 *p_eth_proto_admin = 4734 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4735 if (p_eth_proto_oper) 4736 *p_eth_proto_oper = 4737 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4738 } 4739 4740 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4741 u32 *p_eth_proto_cap, 4742 u32 *p_eth_proto_admin, 4743 u32 *p_eth_proto_oper) 4744 { 4745 if (p_eth_proto_cap) 4746 *p_eth_proto_cap = 4747 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4748 if (p_eth_proto_admin) 4749 *p_eth_proto_admin = 4750 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4751 if (p_eth_proto_oper) 4752 *p_eth_proto_oper = 4753 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4754 } 4755 4756 /* PPAD - Port Physical Address Register 4757 * ------------------------------------- 4758 * The PPAD register configures the per port physical MAC address. 4759 */ 4760 #define MLXSW_REG_PPAD_ID 0x5005 4761 #define MLXSW_REG_PPAD_LEN 0x10 4762 4763 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4764 4765 /* reg_ppad_single_base_mac 4766 * 0: base_mac, local port should be 0 and mac[7:0] is 4767 * reserved. HW will set incremental 4768 * 1: single_mac - mac of the local_port 4769 * Access: RW 4770 */ 4771 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4772 4773 /* reg_ppad_local_port 4774 * port number, if single_base_mac = 0 then local_port is reserved 4775 * Access: RW 4776 */ 4777 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4778 4779 /* reg_ppad_mac 4780 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4781 * If single_base_mac = 1 - the per port MAC address 4782 * Access: RW 4783 */ 4784 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4785 4786 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4787 u16 local_port) 4788 { 4789 MLXSW_REG_ZERO(ppad, payload); 4790 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4791 mlxsw_reg_ppad_local_port_set(payload, local_port); 4792 } 4793 4794 /* PAOS - Ports Administrative and Operational Status Register 4795 * ----------------------------------------------------------- 4796 * Configures and retrieves per port administrative and operational status. 4797 */ 4798 #define MLXSW_REG_PAOS_ID 0x5006 4799 #define MLXSW_REG_PAOS_LEN 0x10 4800 4801 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4802 4803 /* reg_paos_swid 4804 * Switch partition ID with which to associate the port. 4805 * Note: while external ports uses unique local port numbers (and thus swid is 4806 * redundant), router ports use the same local port number where swid is the 4807 * only indication for the relevant port. 4808 * Access: Index 4809 */ 4810 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4811 4812 /* reg_paos_local_port 4813 * Local port number. 4814 * Access: Index 4815 */ 4816 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4817 4818 /* reg_paos_admin_status 4819 * Port administrative state (the desired state of the port): 4820 * 1 - Up. 4821 * 2 - Down. 4822 * 3 - Up once. This means that in case of link failure, the port won't go 4823 * into polling mode, but will wait to be re-enabled by software. 4824 * 4 - Disabled by system. Can only be set by hardware. 4825 * Access: RW 4826 */ 4827 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4828 4829 /* reg_paos_oper_status 4830 * Port operational state (the current state): 4831 * 1 - Up. 4832 * 2 - Down. 4833 * 3 - Down by port failure. This means that the device will not let the 4834 * port up again until explicitly specified by software. 4835 * Access: RO 4836 */ 4837 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4838 4839 /* reg_paos_ase 4840 * Admin state update enabled. 4841 * Access: WO 4842 */ 4843 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4844 4845 /* reg_paos_ee 4846 * Event update enable. If this bit is set, event generation will be 4847 * updated based on the e field. 4848 * Access: WO 4849 */ 4850 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4851 4852 /* reg_paos_e 4853 * Event generation on operational state change: 4854 * 0 - Do not generate event. 4855 * 1 - Generate Event. 4856 * 2 - Generate Single Event. 4857 * Access: RW 4858 */ 4859 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4860 4861 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4862 enum mlxsw_port_admin_status status) 4863 { 4864 MLXSW_REG_ZERO(paos, payload); 4865 mlxsw_reg_paos_swid_set(payload, 0); 4866 mlxsw_reg_paos_local_port_set(payload, local_port); 4867 mlxsw_reg_paos_admin_status_set(payload, status); 4868 mlxsw_reg_paos_oper_status_set(payload, 0); 4869 mlxsw_reg_paos_ase_set(payload, 1); 4870 mlxsw_reg_paos_ee_set(payload, 1); 4871 mlxsw_reg_paos_e_set(payload, 1); 4872 } 4873 4874 /* PFCC - Ports Flow Control Configuration Register 4875 * ------------------------------------------------ 4876 * Configures and retrieves the per port flow control configuration. 4877 */ 4878 #define MLXSW_REG_PFCC_ID 0x5007 4879 #define MLXSW_REG_PFCC_LEN 0x20 4880 4881 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4882 4883 /* reg_pfcc_local_port 4884 * Local port number. 4885 * Access: Index 4886 */ 4887 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4888 4889 /* reg_pfcc_pnat 4890 * Port number access type. Determines the way local_port is interpreted: 4891 * 0 - Local port number. 4892 * 1 - IB / label port number. 4893 * Access: Index 4894 */ 4895 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4896 4897 /* reg_pfcc_shl_cap 4898 * Send to higher layers capabilities: 4899 * 0 - No capability of sending Pause and PFC frames to higher layers. 4900 * 1 - Device has capability of sending Pause and PFC frames to higher 4901 * layers. 4902 * Access: RO 4903 */ 4904 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4905 4906 /* reg_pfcc_shl_opr 4907 * Send to higher layers operation: 4908 * 0 - Pause and PFC frames are handled by the port (default). 4909 * 1 - Pause and PFC frames are handled by the port and also sent to 4910 * higher layers. Only valid if shl_cap = 1. 4911 * Access: RW 4912 */ 4913 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4914 4915 /* reg_pfcc_ppan 4916 * Pause policy auto negotiation. 4917 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4918 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4919 * based on the auto-negotiation resolution. 4920 * Access: RW 4921 * 4922 * Note: The auto-negotiation advertisement is set according to pptx and 4923 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4924 */ 4925 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4926 4927 /* reg_pfcc_prio_mask_tx 4928 * Bit per priority indicating if Tx flow control policy should be 4929 * updated based on bit pfctx. 4930 * Access: WO 4931 */ 4932 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4933 4934 /* reg_pfcc_prio_mask_rx 4935 * Bit per priority indicating if Rx flow control policy should be 4936 * updated based on bit pfcrx. 4937 * Access: WO 4938 */ 4939 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4940 4941 /* reg_pfcc_pptx 4942 * Admin Pause policy on Tx. 4943 * 0 - Never generate Pause frames (default). 4944 * 1 - Generate Pause frames according to Rx buffer threshold. 4945 * Access: RW 4946 */ 4947 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4948 4949 /* reg_pfcc_aptx 4950 * Active (operational) Pause policy on Tx. 4951 * 0 - Never generate Pause frames. 4952 * 1 - Generate Pause frames according to Rx buffer threshold. 4953 * Access: RO 4954 */ 4955 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4956 4957 /* reg_pfcc_pfctx 4958 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4959 * 0 - Never generate priority Pause frames on the specified priority 4960 * (default). 4961 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4962 * the specified priority. 4963 * Access: RW 4964 * 4965 * Note: pfctx and pptx must be mutually exclusive. 4966 */ 4967 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4968 4969 /* reg_pfcc_pprx 4970 * Admin Pause policy on Rx. 4971 * 0 - Ignore received Pause frames (default). 4972 * 1 - Respect received Pause frames. 4973 * Access: RW 4974 */ 4975 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4976 4977 /* reg_pfcc_aprx 4978 * Active (operational) Pause policy on Rx. 4979 * 0 - Ignore received Pause frames. 4980 * 1 - Respect received Pause frames. 4981 * Access: RO 4982 */ 4983 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4984 4985 /* reg_pfcc_pfcrx 4986 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4987 * 0 - Ignore incoming priority Pause frames on the specified priority 4988 * (default). 4989 * 1 - Respect incoming priority Pause frames on the specified priority. 4990 * Access: RW 4991 */ 4992 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4993 4994 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4995 4996 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4997 { 4998 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4999 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5000 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5001 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5002 } 5003 5004 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5005 { 5006 MLXSW_REG_ZERO(pfcc, payload); 5007 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5008 } 5009 5010 /* PPCNT - Ports Performance Counters Register 5011 * ------------------------------------------- 5012 * The PPCNT register retrieves per port performance counters. 5013 */ 5014 #define MLXSW_REG_PPCNT_ID 0x5008 5015 #define MLXSW_REG_PPCNT_LEN 0x100 5016 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5017 5018 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5019 5020 /* reg_ppcnt_swid 5021 * For HCA: must be always 0. 5022 * Switch partition ID to associate port with. 5023 * Switch partitions are numbered from 0 to 7 inclusively. 5024 * Switch partition 254 indicates stacking ports. 5025 * Switch partition 255 indicates all switch partitions. 5026 * Only valid on Set() operation with local_port=255. 5027 * Access: Index 5028 */ 5029 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5030 5031 /* reg_ppcnt_local_port 5032 * Local port number. 5033 * Access: Index 5034 */ 5035 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5036 5037 /* reg_ppcnt_pnat 5038 * Port number access type: 5039 * 0 - Local port number 5040 * 1 - IB port number 5041 * Access: Index 5042 */ 5043 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5044 5045 enum mlxsw_reg_ppcnt_grp { 5046 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5047 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5048 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5049 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5050 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5051 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5052 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5053 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5054 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5055 }; 5056 5057 /* reg_ppcnt_grp 5058 * Performance counter group. 5059 * Group 63 indicates all groups. Only valid on Set() operation with 5060 * clr bit set. 5061 * 0x0: IEEE 802.3 Counters 5062 * 0x1: RFC 2863 Counters 5063 * 0x2: RFC 2819 Counters 5064 * 0x3: RFC 3635 Counters 5065 * 0x5: Ethernet Extended Counters 5066 * 0x6: Ethernet Discard Counters 5067 * 0x8: Link Level Retransmission Counters 5068 * 0x10: Per Priority Counters 5069 * 0x11: Per Traffic Class Counters 5070 * 0x12: Physical Layer Counters 5071 * 0x13: Per Traffic Class Congestion Counters 5072 * Access: Index 5073 */ 5074 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5075 5076 /* reg_ppcnt_clr 5077 * Clear counters. Setting the clr bit will reset the counter value 5078 * for all counters in the counter group. This bit can be set 5079 * for both Set() and Get() operation. 5080 * Access: OP 5081 */ 5082 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5083 5084 /* reg_ppcnt_lp_gl 5085 * Local port global variable. 5086 * 0: local_port 255 = all ports of the device. 5087 * 1: local_port indicates local port number for all ports. 5088 * Access: OP 5089 */ 5090 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5091 5092 /* reg_ppcnt_prio_tc 5093 * Priority for counter set that support per priority, valid values: 0-7. 5094 * Traffic class for counter set that support per traffic class, 5095 * valid values: 0- cap_max_tclass-1 . 5096 * For HCA: cap_max_tclass is always 8. 5097 * Otherwise must be 0. 5098 * Access: Index 5099 */ 5100 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5101 5102 /* Ethernet IEEE 802.3 Counter Group */ 5103 5104 /* reg_ppcnt_a_frames_transmitted_ok 5105 * Access: RO 5106 */ 5107 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5108 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5109 5110 /* reg_ppcnt_a_frames_received_ok 5111 * Access: RO 5112 */ 5113 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5114 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5115 5116 /* reg_ppcnt_a_frame_check_sequence_errors 5117 * Access: RO 5118 */ 5119 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5120 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5121 5122 /* reg_ppcnt_a_alignment_errors 5123 * Access: RO 5124 */ 5125 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5126 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5127 5128 /* reg_ppcnt_a_octets_transmitted_ok 5129 * Access: RO 5130 */ 5131 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5132 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5133 5134 /* reg_ppcnt_a_octets_received_ok 5135 * Access: RO 5136 */ 5137 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5138 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5139 5140 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5141 * Access: RO 5142 */ 5143 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5144 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5145 5146 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5147 * Access: RO 5148 */ 5149 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5150 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5151 5152 /* reg_ppcnt_a_multicast_frames_received_ok 5153 * Access: RO 5154 */ 5155 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5156 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5157 5158 /* reg_ppcnt_a_broadcast_frames_received_ok 5159 * Access: RO 5160 */ 5161 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5162 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5163 5164 /* reg_ppcnt_a_in_range_length_errors 5165 * Access: RO 5166 */ 5167 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5168 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5169 5170 /* reg_ppcnt_a_out_of_range_length_field 5171 * Access: RO 5172 */ 5173 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5174 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5175 5176 /* reg_ppcnt_a_frame_too_long_errors 5177 * Access: RO 5178 */ 5179 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5180 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5181 5182 /* reg_ppcnt_a_symbol_error_during_carrier 5183 * Access: RO 5184 */ 5185 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5186 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5187 5188 /* reg_ppcnt_a_mac_control_frames_transmitted 5189 * Access: RO 5190 */ 5191 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5192 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5193 5194 /* reg_ppcnt_a_mac_control_frames_received 5195 * Access: RO 5196 */ 5197 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5198 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5199 5200 /* reg_ppcnt_a_unsupported_opcodes_received 5201 * Access: RO 5202 */ 5203 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5204 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5205 5206 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5207 * Access: RO 5208 */ 5209 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5210 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5211 5212 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5213 * Access: RO 5214 */ 5215 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5216 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5217 5218 /* Ethernet RFC 2863 Counter Group */ 5219 5220 /* reg_ppcnt_if_in_discards 5221 * Access: RO 5222 */ 5223 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5224 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5225 5226 /* reg_ppcnt_if_out_discards 5227 * Access: RO 5228 */ 5229 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5230 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5231 5232 /* reg_ppcnt_if_out_errors 5233 * Access: RO 5234 */ 5235 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5236 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5237 5238 /* Ethernet RFC 2819 Counter Group */ 5239 5240 /* reg_ppcnt_ether_stats_undersize_pkts 5241 * Access: RO 5242 */ 5243 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5244 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5245 5246 /* reg_ppcnt_ether_stats_oversize_pkts 5247 * Access: RO 5248 */ 5249 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5250 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5251 5252 /* reg_ppcnt_ether_stats_fragments 5253 * Access: RO 5254 */ 5255 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5256 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5257 5258 /* reg_ppcnt_ether_stats_pkts64octets 5259 * Access: RO 5260 */ 5261 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5262 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5263 5264 /* reg_ppcnt_ether_stats_pkts65to127octets 5265 * Access: RO 5266 */ 5267 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5268 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5269 5270 /* reg_ppcnt_ether_stats_pkts128to255octets 5271 * Access: RO 5272 */ 5273 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5274 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5275 5276 /* reg_ppcnt_ether_stats_pkts256to511octets 5277 * Access: RO 5278 */ 5279 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5281 5282 /* reg_ppcnt_ether_stats_pkts512to1023octets 5283 * Access: RO 5284 */ 5285 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5287 5288 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5289 * Access: RO 5290 */ 5291 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5293 5294 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5295 * Access: RO 5296 */ 5297 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5299 5300 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5301 * Access: RO 5302 */ 5303 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5305 5306 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5307 * Access: RO 5308 */ 5309 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5311 5312 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5313 * Access: RO 5314 */ 5315 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5317 5318 /* Ethernet RFC 3635 Counter Group */ 5319 5320 /* reg_ppcnt_dot3stats_fcs_errors 5321 * Access: RO 5322 */ 5323 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5324 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5325 5326 /* reg_ppcnt_dot3stats_symbol_errors 5327 * Access: RO 5328 */ 5329 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5330 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5331 5332 /* reg_ppcnt_dot3control_in_unknown_opcodes 5333 * Access: RO 5334 */ 5335 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5336 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5337 5338 /* reg_ppcnt_dot3in_pause_frames 5339 * Access: RO 5340 */ 5341 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5342 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5343 5344 /* Ethernet Extended Counter Group Counters */ 5345 5346 /* reg_ppcnt_ecn_marked 5347 * Access: RO 5348 */ 5349 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5350 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5351 5352 /* Ethernet Discard Counter Group Counters */ 5353 5354 /* reg_ppcnt_ingress_general 5355 * Access: RO 5356 */ 5357 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5358 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5359 5360 /* reg_ppcnt_ingress_policy_engine 5361 * Access: RO 5362 */ 5363 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5364 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5365 5366 /* reg_ppcnt_ingress_vlan_membership 5367 * Access: RO 5368 */ 5369 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5370 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5371 5372 /* reg_ppcnt_ingress_tag_frame_type 5373 * Access: RO 5374 */ 5375 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5376 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5377 5378 /* reg_ppcnt_egress_vlan_membership 5379 * Access: RO 5380 */ 5381 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5382 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5383 5384 /* reg_ppcnt_loopback_filter 5385 * Access: RO 5386 */ 5387 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5388 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5389 5390 /* reg_ppcnt_egress_general 5391 * Access: RO 5392 */ 5393 MLXSW_ITEM64(reg, ppcnt, egress_general, 5394 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5395 5396 /* reg_ppcnt_egress_hoq 5397 * Access: RO 5398 */ 5399 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5400 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5401 5402 /* reg_ppcnt_egress_policy_engine 5403 * Access: RO 5404 */ 5405 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5406 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5407 5408 /* reg_ppcnt_ingress_tx_link_down 5409 * Access: RO 5410 */ 5411 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5412 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5413 5414 /* reg_ppcnt_egress_stp_filter 5415 * Access: RO 5416 */ 5417 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5418 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5419 5420 /* reg_ppcnt_egress_sll 5421 * Access: RO 5422 */ 5423 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5424 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5425 5426 /* Ethernet Per Priority Group Counters */ 5427 5428 /* reg_ppcnt_rx_octets 5429 * Access: RO 5430 */ 5431 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5432 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5433 5434 /* reg_ppcnt_rx_frames 5435 * Access: RO 5436 */ 5437 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5438 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5439 5440 /* reg_ppcnt_tx_octets 5441 * Access: RO 5442 */ 5443 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5444 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5445 5446 /* reg_ppcnt_tx_frames 5447 * Access: RO 5448 */ 5449 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5450 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5451 5452 /* reg_ppcnt_rx_pause 5453 * Access: RO 5454 */ 5455 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5456 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5457 5458 /* reg_ppcnt_rx_pause_duration 5459 * Access: RO 5460 */ 5461 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5462 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5463 5464 /* reg_ppcnt_tx_pause 5465 * Access: RO 5466 */ 5467 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5468 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5469 5470 /* reg_ppcnt_tx_pause_duration 5471 * Access: RO 5472 */ 5473 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5474 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5475 5476 /* reg_ppcnt_rx_pause_transition 5477 * Access: RO 5478 */ 5479 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5480 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5481 5482 /* Ethernet Per Traffic Class Counters */ 5483 5484 /* reg_ppcnt_tc_transmit_queue 5485 * Contains the transmit queue depth in cells of traffic class 5486 * selected by prio_tc and the port selected by local_port. 5487 * The field cannot be cleared. 5488 * Access: RO 5489 */ 5490 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5492 5493 /* reg_ppcnt_tc_no_buffer_discard_uc 5494 * The number of unicast packets dropped due to lack of shared 5495 * buffer resources. 5496 * Access: RO 5497 */ 5498 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5499 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5500 5501 /* Ethernet Per Traffic Class Congestion Group Counters */ 5502 5503 /* reg_ppcnt_wred_discard 5504 * Access: RO 5505 */ 5506 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5507 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5508 5509 /* reg_ppcnt_ecn_marked_tc 5510 * Access: RO 5511 */ 5512 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5513 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5514 5515 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5516 enum mlxsw_reg_ppcnt_grp grp, 5517 u8 prio_tc) 5518 { 5519 MLXSW_REG_ZERO(ppcnt, payload); 5520 mlxsw_reg_ppcnt_swid_set(payload, 0); 5521 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5522 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5523 mlxsw_reg_ppcnt_grp_set(payload, grp); 5524 mlxsw_reg_ppcnt_clr_set(payload, 0); 5525 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5526 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5527 } 5528 5529 /* PPTB - Port Prio To Buffer Register 5530 * ----------------------------------- 5531 * Configures the switch priority to buffer table. 5532 */ 5533 #define MLXSW_REG_PPTB_ID 0x500B 5534 #define MLXSW_REG_PPTB_LEN 0x10 5535 5536 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5537 5538 enum { 5539 MLXSW_REG_PPTB_MM_UM, 5540 MLXSW_REG_PPTB_MM_UNICAST, 5541 MLXSW_REG_PPTB_MM_MULTICAST, 5542 }; 5543 5544 /* reg_pptb_mm 5545 * Mapping mode. 5546 * 0 - Map both unicast and multicast packets to the same buffer. 5547 * 1 - Map only unicast packets. 5548 * 2 - Map only multicast packets. 5549 * Access: Index 5550 * 5551 * Note: SwitchX-2 only supports the first option. 5552 */ 5553 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5554 5555 /* reg_pptb_local_port 5556 * Local port number. 5557 * Access: Index 5558 */ 5559 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5560 5561 /* reg_pptb_um 5562 * Enables the update of the untagged_buf field. 5563 * Access: RW 5564 */ 5565 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5566 5567 /* reg_pptb_pm 5568 * Enables the update of the prio_to_buff field. 5569 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5570 * Access: RW 5571 */ 5572 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5573 5574 /* reg_pptb_prio_to_buff 5575 * Mapping of switch priority <i> to one of the allocated receive port 5576 * buffers. 5577 * Access: RW 5578 */ 5579 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5580 5581 /* reg_pptb_pm_msb 5582 * Enables the update of the prio_to_buff field. 5583 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5584 * Access: RW 5585 */ 5586 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5587 5588 /* reg_pptb_untagged_buff 5589 * Mapping of untagged frames to one of the allocated receive port buffers. 5590 * Access: RW 5591 * 5592 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5593 * Spectrum, as it maps untagged packets based on the default switch priority. 5594 */ 5595 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5596 5597 /* reg_pptb_prio_to_buff_msb 5598 * Mapping of switch priority <i+8> to one of the allocated receive port 5599 * buffers. 5600 * Access: RW 5601 */ 5602 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5603 5604 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5605 5606 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5607 { 5608 MLXSW_REG_ZERO(pptb, payload); 5609 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5610 mlxsw_reg_pptb_local_port_set(payload, local_port); 5611 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5612 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5613 } 5614 5615 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5616 u8 buff) 5617 { 5618 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5619 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5620 } 5621 5622 /* PBMC - Port Buffer Management Control Register 5623 * ---------------------------------------------- 5624 * The PBMC register configures and retrieves the port packet buffer 5625 * allocation for different Prios, and the Pause threshold management. 5626 */ 5627 #define MLXSW_REG_PBMC_ID 0x500C 5628 #define MLXSW_REG_PBMC_LEN 0x6C 5629 5630 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5631 5632 /* reg_pbmc_local_port 5633 * Local port number. 5634 * Access: Index 5635 */ 5636 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5637 5638 /* reg_pbmc_xoff_timer_value 5639 * When device generates a pause frame, it uses this value as the pause 5640 * timer (time for the peer port to pause in quota-512 bit time). 5641 * Access: RW 5642 */ 5643 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5644 5645 /* reg_pbmc_xoff_refresh 5646 * The time before a new pause frame should be sent to refresh the pause RW 5647 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5648 * time). 5649 * Access: RW 5650 */ 5651 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5652 5653 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5654 5655 /* reg_pbmc_buf_lossy 5656 * The field indicates if the buffer is lossy. 5657 * 0 - Lossless 5658 * 1 - Lossy 5659 * Access: RW 5660 */ 5661 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5662 5663 /* reg_pbmc_buf_epsb 5664 * Eligible for Port Shared buffer. 5665 * If epsb is set, packets assigned to buffer are allowed to insert the port 5666 * shared buffer. 5667 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5668 * Access: RW 5669 */ 5670 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5671 5672 /* reg_pbmc_buf_size 5673 * The part of the packet buffer array is allocated for the specific buffer. 5674 * Units are represented in cells. 5675 * Access: RW 5676 */ 5677 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5678 5679 /* reg_pbmc_buf_xoff_threshold 5680 * Once the amount of data in the buffer goes above this value, device 5681 * starts sending PFC frames for all priorities associated with the 5682 * buffer. Units are represented in cells. Reserved in case of lossy 5683 * buffer. 5684 * Access: RW 5685 * 5686 * Note: In Spectrum, reserved for buffer[9]. 5687 */ 5688 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5689 0x08, 0x04, false); 5690 5691 /* reg_pbmc_buf_xon_threshold 5692 * When the amount of data in the buffer goes below this value, device 5693 * stops sending PFC frames for the priorities associated with the 5694 * buffer. Units are represented in cells. Reserved in case of lossy 5695 * buffer. 5696 * Access: RW 5697 * 5698 * Note: In Spectrum, reserved for buffer[9]. 5699 */ 5700 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5701 0x08, 0x04, false); 5702 5703 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5704 u16 xoff_timer_value, u16 xoff_refresh) 5705 { 5706 MLXSW_REG_ZERO(pbmc, payload); 5707 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5708 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5709 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5710 } 5711 5712 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5713 int buf_index, 5714 u16 size) 5715 { 5716 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5717 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5718 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5719 } 5720 5721 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5722 int buf_index, u16 size, 5723 u16 threshold) 5724 { 5725 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5726 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5727 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5728 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5729 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5730 } 5731 5732 /* PSPA - Port Switch Partition Allocation 5733 * --------------------------------------- 5734 * Controls the association of a port with a switch partition and enables 5735 * configuring ports as stacking ports. 5736 */ 5737 #define MLXSW_REG_PSPA_ID 0x500D 5738 #define MLXSW_REG_PSPA_LEN 0x8 5739 5740 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5741 5742 /* reg_pspa_swid 5743 * Switch partition ID. 5744 * Access: RW 5745 */ 5746 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5747 5748 /* reg_pspa_local_port 5749 * Local port number. 5750 * Access: Index 5751 */ 5752 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5753 5754 /* reg_pspa_sub_port 5755 * Virtual port within the local port. Set to 0 when virtual ports are 5756 * disabled on the local port. 5757 * Access: Index 5758 */ 5759 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5760 5761 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5762 { 5763 MLXSW_REG_ZERO(pspa, payload); 5764 mlxsw_reg_pspa_swid_set(payload, swid); 5765 mlxsw_reg_pspa_local_port_set(payload, local_port); 5766 mlxsw_reg_pspa_sub_port_set(payload, 0); 5767 } 5768 5769 /* PMAOS - Ports Module Administrative and Operational Status 5770 * ---------------------------------------------------------- 5771 * This register configures and retrieves the per module status. 5772 */ 5773 #define MLXSW_REG_PMAOS_ID 0x5012 5774 #define MLXSW_REG_PMAOS_LEN 0x10 5775 5776 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5777 5778 /* reg_pmaos_rst 5779 * Module reset toggle. 5780 * Note: Setting reset while module is plugged-in will result in transition to 5781 * "initializing" operational state. 5782 * Access: OP 5783 */ 5784 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5785 5786 /* reg_pmaos_slot_index 5787 * Slot index. 5788 * Access: Index 5789 */ 5790 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5791 5792 /* reg_pmaos_module 5793 * Module number. 5794 * Access: Index 5795 */ 5796 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5797 5798 enum mlxsw_reg_pmaos_admin_status { 5799 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5800 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5801 /* If the module is active and then unplugged, or experienced an error 5802 * event, the operational status should go to "disabled" and can only 5803 * be enabled upon explicit enable command. 5804 */ 5805 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5806 }; 5807 5808 /* reg_pmaos_admin_status 5809 * Module administrative state (the desired state of the module). 5810 * Note: To disable a module, all ports associated with the port must be 5811 * administatively down first. 5812 * Access: RW 5813 */ 5814 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5815 5816 /* reg_pmaos_ase 5817 * Admin state update enable. 5818 * If this bit is set, admin state will be updated based on admin_state field. 5819 * Only relevant on Set() operations. 5820 * Access: WO 5821 */ 5822 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5823 5824 /* reg_pmaos_ee 5825 * Event update enable. 5826 * If this bit is set, event generation will be updated based on the e field. 5827 * Only relevant on Set operations. 5828 * Access: WO 5829 */ 5830 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5831 5832 enum mlxsw_reg_pmaos_e { 5833 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5834 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5835 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5836 }; 5837 5838 /* reg_pmaos_e 5839 * Event Generation on operational state change. 5840 * Access: RW 5841 */ 5842 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5843 5844 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5845 { 5846 MLXSW_REG_ZERO(pmaos, payload); 5847 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5848 mlxsw_reg_pmaos_module_set(payload, module); 5849 } 5850 5851 /* PPLR - Port Physical Loopback Register 5852 * -------------------------------------- 5853 * This register allows configuration of the port's loopback mode. 5854 */ 5855 #define MLXSW_REG_PPLR_ID 0x5018 5856 #define MLXSW_REG_PPLR_LEN 0x8 5857 5858 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5859 5860 /* reg_pplr_local_port 5861 * Local port number. 5862 * Access: Index 5863 */ 5864 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5865 5866 /* Phy local loopback. When set the port's egress traffic is looped back 5867 * to the receiver and the port transmitter is disabled. 5868 */ 5869 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5870 5871 /* reg_pplr_lb_en 5872 * Loopback enable. 5873 * Access: RW 5874 */ 5875 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5876 5877 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5878 bool phy_local) 5879 { 5880 MLXSW_REG_ZERO(pplr, payload); 5881 mlxsw_reg_pplr_local_port_set(payload, local_port); 5882 mlxsw_reg_pplr_lb_en_set(payload, 5883 phy_local ? 5884 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5885 } 5886 5887 /* PMTDB - Port Module To local DataBase Register 5888 * ---------------------------------------------- 5889 * The PMTDB register allows to query the possible module<->local port 5890 * mapping than can be used in PMLP. It does not represent the actual/current 5891 * mapping of the local to module. Actual mapping is only defined by PMLP. 5892 */ 5893 #define MLXSW_REG_PMTDB_ID 0x501A 5894 #define MLXSW_REG_PMTDB_LEN 0x40 5895 5896 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 5897 5898 /* reg_pmtdb_slot_index 5899 * Slot index (0: Main board). 5900 * Access: Index 5901 */ 5902 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 5903 5904 /* reg_pmtdb_module 5905 * Module number. 5906 * Access: Index 5907 */ 5908 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 5909 5910 /* reg_pmtdb_ports_width 5911 * Port's width 5912 * Access: Index 5913 */ 5914 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 5915 5916 /* reg_pmtdb_num_ports 5917 * Number of ports in a single module (split/breakout) 5918 * Access: Index 5919 */ 5920 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 5921 5922 enum mlxsw_reg_pmtdb_status { 5923 MLXSW_REG_PMTDB_STATUS_SUCCESS, 5924 }; 5925 5926 /* reg_pmtdb_status 5927 * Status 5928 * Access: RO 5929 */ 5930 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 5931 5932 /* reg_pmtdb_port_num 5933 * The local_port value which can be assigned to the module. 5934 * In case of more than one port, port<x> represent the /<x> port of 5935 * the module. 5936 * Access: RO 5937 */ 5938 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 5939 5940 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 5941 u8 ports_width, u8 num_ports) 5942 { 5943 MLXSW_REG_ZERO(pmtdb, payload); 5944 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 5945 mlxsw_reg_pmtdb_module_set(payload, module); 5946 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 5947 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 5948 } 5949 5950 /* PMECR - Ports Mapping Event Configuration Register 5951 * -------------------------------------------------- 5952 * The PMECR register is used to enable/disable event triggering 5953 * in case of local port mapping change. 5954 */ 5955 #define MLXSW_REG_PMECR_ID 0x501B 5956 #define MLXSW_REG_PMECR_LEN 0x20 5957 5958 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 5959 5960 /* reg_pmecr_local_port 5961 * Local port number. 5962 * Access: Index 5963 */ 5964 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 5965 5966 /* reg_pmecr_ee 5967 * Event update enable. If this bit is set, event generation will be updated 5968 * based on the e field. Only relevant on Set operations. 5969 * Access: WO 5970 */ 5971 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 5972 5973 /* reg_pmecr_eswi 5974 * Software ignore enable bit. If this bit is set, the value of swi is used. 5975 * If this bit is clear, the value of swi is ignored. 5976 * Only relevant on Set operations. 5977 * Access: WO 5978 */ 5979 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 5980 5981 /* reg_pmecr_swi 5982 * Software ignore. If this bit is set, the device shouldn't generate events 5983 * in case of PMLP SET operation but only upon self local port mapping change 5984 * (if applicable according to e configuration). This is supplementary 5985 * configuration on top of e value. 5986 * Access: RW 5987 */ 5988 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 5989 5990 enum mlxsw_reg_pmecr_e { 5991 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 5992 MLXSW_REG_PMECR_E_GENERATE_EVENT, 5993 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 5994 }; 5995 5996 /* reg_pmecr_e 5997 * Event generation on local port mapping change. 5998 * Access: RW 5999 */ 6000 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6001 6002 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6003 enum mlxsw_reg_pmecr_e e) 6004 { 6005 MLXSW_REG_ZERO(pmecr, payload); 6006 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6007 mlxsw_reg_pmecr_e_set(payload, e); 6008 mlxsw_reg_pmecr_ee_set(payload, true); 6009 mlxsw_reg_pmecr_swi_set(payload, true); 6010 mlxsw_reg_pmecr_eswi_set(payload, true); 6011 } 6012 6013 /* PMPE - Port Module Plug/Unplug Event Register 6014 * --------------------------------------------- 6015 * This register reports any operational status change of a module. 6016 * A change in the module’s state will generate an event only if the change 6017 * happens after arming the event mechanism. Any changes to the module state 6018 * while the event mechanism is not armed will not be reported. Software can 6019 * query the PMPE register for module status. 6020 */ 6021 #define MLXSW_REG_PMPE_ID 0x5024 6022 #define MLXSW_REG_PMPE_LEN 0x10 6023 6024 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6025 6026 /* reg_pmpe_slot_index 6027 * Slot index. 6028 * Access: Index 6029 */ 6030 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6031 6032 /* reg_pmpe_module 6033 * Module number. 6034 * Access: Index 6035 */ 6036 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6037 6038 enum mlxsw_reg_pmpe_module_status { 6039 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6040 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6041 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6042 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6043 }; 6044 6045 /* reg_pmpe_module_status 6046 * Module status. 6047 * Access: RO 6048 */ 6049 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6050 6051 /* reg_pmpe_error_type 6052 * Module error details. 6053 * Access: RO 6054 */ 6055 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6056 6057 /* PDDR - Port Diagnostics Database Register 6058 * ----------------------------------------- 6059 * The PDDR enables to read the Phy debug database 6060 */ 6061 #define MLXSW_REG_PDDR_ID 0x5031 6062 #define MLXSW_REG_PDDR_LEN 0x100 6063 6064 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6065 6066 /* reg_pddr_local_port 6067 * Local port number. 6068 * Access: Index 6069 */ 6070 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6071 6072 enum mlxsw_reg_pddr_page_select { 6073 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6074 }; 6075 6076 /* reg_pddr_page_select 6077 * Page select index. 6078 * Access: Index 6079 */ 6080 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6081 6082 enum mlxsw_reg_pddr_trblsh_group_opcode { 6083 /* Monitor opcodes */ 6084 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6085 }; 6086 6087 /* reg_pddr_group_opcode 6088 * Group selector. 6089 * Access: Index 6090 */ 6091 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6092 6093 /* reg_pddr_status_opcode 6094 * Group selector. 6095 * Access: RO 6096 */ 6097 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6098 6099 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6100 u8 page_select) 6101 { 6102 MLXSW_REG_ZERO(pddr, payload); 6103 mlxsw_reg_pddr_local_port_set(payload, local_port); 6104 mlxsw_reg_pddr_page_select_set(payload, page_select); 6105 } 6106 6107 /* PMMP - Port Module Memory Map Properties Register 6108 * ------------------------------------------------- 6109 * The PMMP register allows to override the module memory map advertisement. 6110 * The register can only be set when the module is disabled by PMAOS register. 6111 */ 6112 #define MLXSW_REG_PMMP_ID 0x5044 6113 #define MLXSW_REG_PMMP_LEN 0x2C 6114 6115 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6116 6117 /* reg_pmmp_module 6118 * Module number. 6119 * Access: Index 6120 */ 6121 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6122 6123 /* reg_pmmp_slot_index 6124 * Slot index. 6125 * Access: Index 6126 */ 6127 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6128 6129 /* reg_pmmp_sticky 6130 * When set, will keep eeprom_override values after plug-out event. 6131 * Access: OP 6132 */ 6133 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6134 6135 /* reg_pmmp_eeprom_override_mask 6136 * Write mask bit (negative polarity). 6137 * 0 - Allow write 6138 * 1 - Ignore write 6139 * On write, indicates which of the bits from eeprom_override field are 6140 * updated. 6141 * Access: WO 6142 */ 6143 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6144 6145 enum { 6146 /* Set module to low power mode */ 6147 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6148 }; 6149 6150 /* reg_pmmp_eeprom_override 6151 * Override / ignore EEPROM advertisement properties bitmask 6152 * Access: RW 6153 */ 6154 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6155 6156 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6157 { 6158 MLXSW_REG_ZERO(pmmp, payload); 6159 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6160 mlxsw_reg_pmmp_module_set(payload, module); 6161 } 6162 6163 /* PLLP - Port Local port to Label Port mapping Register 6164 * ----------------------------------------------------- 6165 * The PLLP register returns the mapping from Local Port into Label Port. 6166 */ 6167 #define MLXSW_REG_PLLP_ID 0x504A 6168 #define MLXSW_REG_PLLP_LEN 0x10 6169 6170 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6171 6172 /* reg_pllp_local_port 6173 * Local port number. 6174 * Access: Index 6175 */ 6176 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6177 6178 /* reg_pllp_label_port 6179 * Front panel label of the port. 6180 * Access: RO 6181 */ 6182 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6183 6184 /* reg_pllp_split_num 6185 * Label split mapping for local_port. 6186 * Access: RO 6187 */ 6188 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6189 6190 /* reg_pllp_slot_index 6191 * Slot index (0: Main board). 6192 * Access: RO 6193 */ 6194 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6195 6196 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6197 { 6198 MLXSW_REG_ZERO(pllp, payload); 6199 mlxsw_reg_pllp_local_port_set(payload, local_port); 6200 } 6201 6202 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6203 u8 *split_num, u8 *slot_index) 6204 { 6205 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6206 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6207 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6208 } 6209 6210 /* PMTM - Port Module Type Mapping Register 6211 * ---------------------------------------- 6212 * The PMTM register allows query or configuration of module types. 6213 * The register can only be set when the module is disabled by PMAOS register 6214 */ 6215 #define MLXSW_REG_PMTM_ID 0x5067 6216 #define MLXSW_REG_PMTM_LEN 0x10 6217 6218 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6219 6220 /* reg_pmtm_slot_index 6221 * Slot index. 6222 * Access: Index 6223 */ 6224 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6225 6226 /* reg_pmtm_module 6227 * Module number. 6228 * Access: Index 6229 */ 6230 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6231 6232 enum mlxsw_reg_pmtm_module_type { 6233 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6234 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6235 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6236 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6237 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6238 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6239 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6240 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6241 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6242 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6243 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6244 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6245 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6246 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6247 }; 6248 6249 /* reg_pmtm_module_type 6250 * Module type. 6251 * Access: RW 6252 */ 6253 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6254 6255 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6256 { 6257 MLXSW_REG_ZERO(pmtm, payload); 6258 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6259 mlxsw_reg_pmtm_module_set(payload, module); 6260 } 6261 6262 /* HTGT - Host Trap Group Table 6263 * ---------------------------- 6264 * Configures the properties for forwarding to CPU. 6265 */ 6266 #define MLXSW_REG_HTGT_ID 0x7002 6267 #define MLXSW_REG_HTGT_LEN 0x20 6268 6269 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6270 6271 /* reg_htgt_swid 6272 * Switch partition ID. 6273 * Access: Index 6274 */ 6275 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6276 6277 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6278 6279 /* reg_htgt_type 6280 * CPU path type. 6281 * Access: RW 6282 */ 6283 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6284 6285 enum mlxsw_reg_htgt_trap_group { 6286 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6287 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6288 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6289 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6290 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6291 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6292 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6293 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6294 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6295 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6296 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6297 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6298 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6299 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6300 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6301 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6302 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6303 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6304 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6305 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6306 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6307 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6308 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6309 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6310 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6311 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6312 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6313 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6314 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6315 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6316 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6317 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6318 6319 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6320 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6321 }; 6322 6323 /* reg_htgt_trap_group 6324 * Trap group number. User defined number specifying which trap groups 6325 * should be forwarded to the CPU. The mapping between trap IDs and trap 6326 * groups is configured using HPKT register. 6327 * Access: Index 6328 */ 6329 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6330 6331 enum { 6332 MLXSW_REG_HTGT_POLICER_DISABLE, 6333 MLXSW_REG_HTGT_POLICER_ENABLE, 6334 }; 6335 6336 /* reg_htgt_pide 6337 * Enable policer ID specified using 'pid' field. 6338 * Access: RW 6339 */ 6340 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6341 6342 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6343 6344 /* reg_htgt_pid 6345 * Policer ID for the trap group. 6346 * Access: RW 6347 */ 6348 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6349 6350 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6351 6352 /* reg_htgt_mirror_action 6353 * Mirror action to use. 6354 * 0 - Trap to CPU. 6355 * 1 - Trap to CPU and mirror to a mirroring agent. 6356 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6357 * Access: RW 6358 * 6359 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6360 */ 6361 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6362 6363 /* reg_htgt_mirroring_agent 6364 * Mirroring agent. 6365 * Access: RW 6366 */ 6367 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6368 6369 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6370 6371 /* reg_htgt_priority 6372 * Trap group priority. 6373 * In case a packet matches multiple classification rules, the packet will 6374 * only be trapped once, based on the trap ID associated with the group (via 6375 * register HPKT) with the highest priority. 6376 * Supported values are 0-7, with 7 represnting the highest priority. 6377 * Access: RW 6378 * 6379 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6380 * by the 'trap_group' field. 6381 */ 6382 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6383 6384 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6385 6386 /* reg_htgt_local_path_cpu_tclass 6387 * CPU ingress traffic class for the trap group. 6388 * Access: RW 6389 */ 6390 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6391 6392 enum mlxsw_reg_htgt_local_path_rdq { 6393 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6394 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6395 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6396 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6397 }; 6398 /* reg_htgt_local_path_rdq 6399 * Receive descriptor queue (RDQ) to use for the trap group. 6400 * Access: RW 6401 */ 6402 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6403 6404 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6405 u8 priority, u8 tc) 6406 { 6407 MLXSW_REG_ZERO(htgt, payload); 6408 6409 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6410 mlxsw_reg_htgt_pide_set(payload, 6411 MLXSW_REG_HTGT_POLICER_DISABLE); 6412 } else { 6413 mlxsw_reg_htgt_pide_set(payload, 6414 MLXSW_REG_HTGT_POLICER_ENABLE); 6415 mlxsw_reg_htgt_pid_set(payload, policer_id); 6416 } 6417 6418 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6419 mlxsw_reg_htgt_trap_group_set(payload, group); 6420 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6421 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6422 mlxsw_reg_htgt_priority_set(payload, priority); 6423 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6424 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6425 } 6426 6427 /* HPKT - Host Packet Trap 6428 * ----------------------- 6429 * Configures trap IDs inside trap groups. 6430 */ 6431 #define MLXSW_REG_HPKT_ID 0x7003 6432 #define MLXSW_REG_HPKT_LEN 0x10 6433 6434 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6435 6436 enum { 6437 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6438 MLXSW_REG_HPKT_ACK_REQUIRED, 6439 }; 6440 6441 /* reg_hpkt_ack 6442 * Require acknowledgements from the host for events. 6443 * If set, then the device will wait for the event it sent to be acknowledged 6444 * by the host. This option is only relevant for event trap IDs. 6445 * Access: RW 6446 * 6447 * Note: Currently not supported by firmware. 6448 */ 6449 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6450 6451 enum mlxsw_reg_hpkt_action { 6452 MLXSW_REG_HPKT_ACTION_FORWARD, 6453 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6454 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6455 MLXSW_REG_HPKT_ACTION_DISCARD, 6456 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6457 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6458 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6459 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6460 }; 6461 6462 /* reg_hpkt_action 6463 * Action to perform on packet when trapped. 6464 * 0 - No action. Forward to CPU based on switching rules. 6465 * 1 - Trap to CPU (CPU receives sole copy). 6466 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6467 * 3 - Discard. 6468 * 4 - Soft discard (allow other traps to act on the packet). 6469 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6470 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6471 * 15 - Restore the firmware's default action. 6472 * Access: RW 6473 * 6474 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6475 * addressed to the CPU. 6476 */ 6477 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6478 6479 /* reg_hpkt_trap_group 6480 * Trap group to associate the trap with. 6481 * Access: RW 6482 */ 6483 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6484 6485 /* reg_hpkt_trap_id 6486 * Trap ID. 6487 * Access: Index 6488 * 6489 * Note: A trap ID can only be associated with a single trap group. The device 6490 * will associate the trap ID with the last trap group configured. 6491 */ 6492 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6493 6494 enum { 6495 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6496 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6497 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6498 }; 6499 6500 /* reg_hpkt_ctrl 6501 * Configure dedicated buffer resources for control packets. 6502 * Ignored by SwitchX-2. 6503 * 0 - Keep factory defaults. 6504 * 1 - Do not use control buffer for this trap ID. 6505 * 2 - Use control buffer for this trap ID. 6506 * Access: RW 6507 */ 6508 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6509 6510 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6511 enum mlxsw_reg_htgt_trap_group trap_group, 6512 bool is_ctrl) 6513 { 6514 MLXSW_REG_ZERO(hpkt, payload); 6515 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6516 mlxsw_reg_hpkt_action_set(payload, action); 6517 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6518 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6519 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6520 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6521 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6522 } 6523 6524 /* RGCR - Router General Configuration Register 6525 * -------------------------------------------- 6526 * The register is used for setting up the router configuration. 6527 */ 6528 #define MLXSW_REG_RGCR_ID 0x8001 6529 #define MLXSW_REG_RGCR_LEN 0x28 6530 6531 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6532 6533 /* reg_rgcr_ipv4_en 6534 * IPv4 router enable. 6535 * Access: RW 6536 */ 6537 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6538 6539 /* reg_rgcr_ipv6_en 6540 * IPv6 router enable. 6541 * Access: RW 6542 */ 6543 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6544 6545 /* reg_rgcr_max_router_interfaces 6546 * Defines the maximum number of active router interfaces for all virtual 6547 * routers. 6548 * Access: RW 6549 */ 6550 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6551 6552 /* reg_rgcr_usp 6553 * Update switch priority and packet color. 6554 * 0 - Preserve the value of Switch Priority and packet color. 6555 * 1 - Recalculate the value of Switch Priority and packet color. 6556 * Access: RW 6557 * 6558 * Note: Not supported by SwitchX and SwitchX-2. 6559 */ 6560 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6561 6562 /* reg_rgcr_pcp_rw 6563 * Indicates how to handle the pcp_rewrite_en value: 6564 * 0 - Preserve the value of pcp_rewrite_en. 6565 * 2 - Disable PCP rewrite. 6566 * 3 - Enable PCP rewrite. 6567 * Access: RW 6568 * 6569 * Note: Not supported by SwitchX and SwitchX-2. 6570 */ 6571 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6572 6573 /* reg_rgcr_activity_dis 6574 * Activity disable: 6575 * 0 - Activity will be set when an entry is hit (default). 6576 * 1 - Activity will not be set when an entry is hit. 6577 * 6578 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6579 * (RALUE). 6580 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6581 * Entry (RAUHT). 6582 * Bits 2:7 are reserved. 6583 * Access: RW 6584 * 6585 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6586 */ 6587 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6588 6589 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6590 bool ipv6_en) 6591 { 6592 MLXSW_REG_ZERO(rgcr, payload); 6593 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6594 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6595 } 6596 6597 /* RITR - Router Interface Table Register 6598 * -------------------------------------- 6599 * The register is used to configure the router interface table. 6600 */ 6601 #define MLXSW_REG_RITR_ID 0x8002 6602 #define MLXSW_REG_RITR_LEN 0x40 6603 6604 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6605 6606 /* reg_ritr_enable 6607 * Enables routing on the router interface. 6608 * Access: RW 6609 */ 6610 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6611 6612 /* reg_ritr_ipv4 6613 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6614 * interface. 6615 * Access: RW 6616 */ 6617 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6618 6619 /* reg_ritr_ipv6 6620 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6621 * interface. 6622 * Access: RW 6623 */ 6624 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6625 6626 /* reg_ritr_ipv4_mc 6627 * IPv4 multicast routing enable. 6628 * Access: RW 6629 */ 6630 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6631 6632 /* reg_ritr_ipv6_mc 6633 * IPv6 multicast routing enable. 6634 * Access: RW 6635 */ 6636 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6637 6638 enum mlxsw_reg_ritr_if_type { 6639 /* VLAN interface. */ 6640 MLXSW_REG_RITR_VLAN_IF, 6641 /* FID interface. */ 6642 MLXSW_REG_RITR_FID_IF, 6643 /* Sub-port interface. */ 6644 MLXSW_REG_RITR_SP_IF, 6645 /* Loopback Interface. */ 6646 MLXSW_REG_RITR_LOOPBACK_IF, 6647 }; 6648 6649 /* reg_ritr_type 6650 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6651 * Access: RW 6652 */ 6653 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6654 6655 enum { 6656 MLXSW_REG_RITR_RIF_CREATE, 6657 MLXSW_REG_RITR_RIF_DEL, 6658 }; 6659 6660 /* reg_ritr_op 6661 * Opcode: 6662 * 0 - Create or edit RIF. 6663 * 1 - Delete RIF. 6664 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6665 * is not supported. An interface must be deleted and re-created in order 6666 * to update properties. 6667 * Access: WO 6668 */ 6669 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6670 6671 /* reg_ritr_rif 6672 * Router interface index. A pointer to the Router Interface Table. 6673 * Access: Index 6674 */ 6675 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6676 6677 /* reg_ritr_ipv4_fe 6678 * IPv4 Forwarding Enable. 6679 * Enables routing of IPv4 traffic on the router interface. When disabled, 6680 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6681 * Not supported in SwitchX-2. 6682 * Access: RW 6683 */ 6684 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6685 6686 /* reg_ritr_ipv6_fe 6687 * IPv6 Forwarding Enable. 6688 * Enables routing of IPv6 traffic on the router interface. When disabled, 6689 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6690 * Not supported in SwitchX-2. 6691 * Access: RW 6692 */ 6693 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6694 6695 /* reg_ritr_ipv4_mc_fe 6696 * IPv4 Multicast Forwarding Enable. 6697 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6698 * will be enabled. 6699 * Access: RW 6700 */ 6701 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6702 6703 /* reg_ritr_ipv6_mc_fe 6704 * IPv6 Multicast Forwarding Enable. 6705 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6706 * will be enabled. 6707 * Access: RW 6708 */ 6709 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6710 6711 /* reg_ritr_lb_en 6712 * Loop-back filter enable for unicast packets. 6713 * If the flag is set then loop-back filter for unicast packets is 6714 * implemented on the RIF. Multicast packets are always subject to 6715 * loop-back filtering. 6716 * Access: RW 6717 */ 6718 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6719 6720 /* reg_ritr_virtual_router 6721 * Virtual router ID associated with the router interface. 6722 * Access: RW 6723 */ 6724 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6725 6726 /* reg_ritr_mtu 6727 * Router interface MTU. 6728 * Access: RW 6729 */ 6730 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6731 6732 /* reg_ritr_if_swid 6733 * Switch partition ID. 6734 * Access: RW 6735 */ 6736 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6737 6738 /* reg_ritr_if_mac_profile_id 6739 * MAC msb profile ID. 6740 * Access: RW 6741 */ 6742 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6743 6744 /* reg_ritr_if_mac 6745 * Router interface MAC address. 6746 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6747 * Access: RW 6748 */ 6749 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6750 6751 /* reg_ritr_if_vrrp_id_ipv6 6752 * VRRP ID for IPv6 6753 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6754 * Access: RW 6755 */ 6756 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6757 6758 /* reg_ritr_if_vrrp_id_ipv4 6759 * VRRP ID for IPv4 6760 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6761 * Access: RW 6762 */ 6763 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6764 6765 /* VLAN Interface */ 6766 6767 /* reg_ritr_vlan_if_vlan_id 6768 * VLAN ID. 6769 * Access: RW 6770 */ 6771 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6772 6773 /* reg_ritr_vlan_if_efid 6774 * Egress FID. 6775 * Used to connect the RIF to a bridge. 6776 * Access: RW 6777 * 6778 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6779 */ 6780 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6781 6782 /* FID Interface */ 6783 6784 /* reg_ritr_fid_if_fid 6785 * Filtering ID. Used to connect a bridge to the router. 6786 * When legacy bridge model is used, only FIDs from the vFID range are 6787 * supported. When unified bridge model is used, this is the egress FID for 6788 * router to bridge. 6789 * Access: RW 6790 */ 6791 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6792 6793 /* Sub-port Interface */ 6794 6795 /* reg_ritr_sp_if_lag 6796 * LAG indication. When this bit is set the system_port field holds the 6797 * LAG identifier. 6798 * Access: RW 6799 */ 6800 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6801 6802 /* reg_ritr_sp_system_port 6803 * Port unique indentifier. When lag bit is set, this field holds the 6804 * lag_id in bits 0:9. 6805 * Access: RW 6806 */ 6807 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6808 6809 /* reg_ritr_sp_if_efid 6810 * Egress filtering ID. 6811 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6812 * the VID. 6813 * Access: RW 6814 * 6815 * Note: Reserved when legacy bridge model is used. 6816 */ 6817 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6818 6819 /* reg_ritr_sp_if_vid 6820 * VLAN ID. 6821 * Access: RW 6822 */ 6823 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6824 6825 /* Loopback Interface */ 6826 6827 enum mlxsw_reg_ritr_loopback_protocol { 6828 /* IPinIP IPv4 underlay Unicast */ 6829 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6830 /* IPinIP IPv6 underlay Unicast */ 6831 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6832 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6833 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6834 }; 6835 6836 /* reg_ritr_loopback_protocol 6837 * Access: RW 6838 */ 6839 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6840 6841 enum mlxsw_reg_ritr_loopback_ipip_type { 6842 /* Tunnel is IPinIP. */ 6843 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6844 /* Tunnel is GRE, no key. */ 6845 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6846 /* Tunnel is GRE, with a key. */ 6847 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6848 }; 6849 6850 /* reg_ritr_loopback_ipip_type 6851 * Encapsulation type. 6852 * Access: RW 6853 */ 6854 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6855 6856 enum mlxsw_reg_ritr_loopback_ipip_options { 6857 /* The key is defined by gre_key. */ 6858 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6859 }; 6860 6861 /* reg_ritr_loopback_ipip_options 6862 * Access: RW 6863 */ 6864 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6865 6866 /* reg_ritr_loopback_ipip_uvr 6867 * Underlay Virtual Router ID. 6868 * Range is 0..cap_max_virtual_routers-1. 6869 * Reserved for Spectrum-2. 6870 * Access: RW 6871 */ 6872 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6873 6874 /* reg_ritr_loopback_ipip_underlay_rif 6875 * Underlay ingress router interface. 6876 * Reserved for Spectrum. 6877 * Access: RW 6878 */ 6879 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6880 6881 /* reg_ritr_loopback_ipip_usip* 6882 * Encapsulation Underlay source IP. 6883 * Access: RW 6884 */ 6885 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6886 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6887 6888 /* reg_ritr_loopback_ipip_gre_key 6889 * GRE Key. 6890 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6891 * Access: RW 6892 */ 6893 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6894 6895 /* Shared between ingress/egress */ 6896 enum mlxsw_reg_ritr_counter_set_type { 6897 /* No Count. */ 6898 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6899 /* Basic. Used for router interfaces, counting the following: 6900 * - Error and Discard counters. 6901 * - Unicast, Multicast and Broadcast counters. Sharing the 6902 * same set of counters for the different type of traffic 6903 * (IPv4, IPv6 and mpls). 6904 */ 6905 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6906 }; 6907 6908 /* reg_ritr_ingress_counter_index 6909 * Counter Index for flow counter. 6910 * Access: RW 6911 */ 6912 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6913 6914 /* reg_ritr_ingress_counter_set_type 6915 * Igress Counter Set Type for router interface counter. 6916 * Access: RW 6917 */ 6918 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6919 6920 /* reg_ritr_egress_counter_index 6921 * Counter Index for flow counter. 6922 * Access: RW 6923 */ 6924 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6925 6926 /* reg_ritr_egress_counter_set_type 6927 * Egress Counter Set Type for router interface counter. 6928 * Access: RW 6929 */ 6930 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6931 6932 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6933 bool enable, bool egress) 6934 { 6935 enum mlxsw_reg_ritr_counter_set_type set_type; 6936 6937 if (enable) 6938 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6939 else 6940 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6941 6942 if (egress) { 6943 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6944 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6945 } else { 6946 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 6947 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6948 } 6949 } 6950 6951 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6952 { 6953 MLXSW_REG_ZERO(ritr, payload); 6954 mlxsw_reg_ritr_rif_set(payload, rif); 6955 } 6956 6957 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6958 u16 system_port, u16 efid, u16 vid) 6959 { 6960 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6961 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6962 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 6963 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6964 } 6965 6966 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6967 enum mlxsw_reg_ritr_if_type type, 6968 u16 rif, u16 vr_id, u16 mtu) 6969 { 6970 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6971 6972 MLXSW_REG_ZERO(ritr, payload); 6973 mlxsw_reg_ritr_enable_set(payload, enable); 6974 mlxsw_reg_ritr_ipv4_set(payload, 1); 6975 mlxsw_reg_ritr_ipv6_set(payload, 1); 6976 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6977 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6978 mlxsw_reg_ritr_type_set(payload, type); 6979 mlxsw_reg_ritr_op_set(payload, op); 6980 mlxsw_reg_ritr_rif_set(payload, rif); 6981 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6982 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6983 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6984 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6985 mlxsw_reg_ritr_lb_en_set(payload, 1); 6986 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6987 mlxsw_reg_ritr_mtu_set(payload, mtu); 6988 } 6989 6990 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6991 { 6992 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6993 } 6994 6995 static inline void 6996 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 6997 u16 mtu, const char *mac, u8 mac_profile_id, 6998 u16 vlan_id, u16 efid) 6999 { 7000 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7001 7002 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7003 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7004 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7005 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7006 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7007 } 7008 7009 static inline void 7010 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7011 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7012 enum mlxsw_reg_ritr_loopback_ipip_options options, 7013 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7014 { 7015 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7016 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7017 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7018 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7019 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7020 } 7021 7022 static inline void 7023 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7024 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7025 enum mlxsw_reg_ritr_loopback_ipip_options options, 7026 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7027 { 7028 mlxsw_reg_ritr_loopback_protocol_set(payload, 7029 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7030 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7031 uvr_id, underlay_rif, gre_key); 7032 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7033 } 7034 7035 static inline void 7036 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7037 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7038 enum mlxsw_reg_ritr_loopback_ipip_options options, 7039 u16 uvr_id, u16 underlay_rif, 7040 const struct in6_addr *usip, u32 gre_key) 7041 { 7042 enum mlxsw_reg_ritr_loopback_protocol protocol = 7043 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7044 7045 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7046 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7047 uvr_id, underlay_rif, gre_key); 7048 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7049 (const char *)usip); 7050 } 7051 7052 /* RTAR - Router TCAM Allocation Register 7053 * -------------------------------------- 7054 * This register is used for allocation of regions in the TCAM table. 7055 */ 7056 #define MLXSW_REG_RTAR_ID 0x8004 7057 #define MLXSW_REG_RTAR_LEN 0x20 7058 7059 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7060 7061 enum mlxsw_reg_rtar_op { 7062 MLXSW_REG_RTAR_OP_ALLOCATE, 7063 MLXSW_REG_RTAR_OP_RESIZE, 7064 MLXSW_REG_RTAR_OP_DEALLOCATE, 7065 }; 7066 7067 /* reg_rtar_op 7068 * Access: WO 7069 */ 7070 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7071 7072 enum mlxsw_reg_rtar_key_type { 7073 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7074 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7075 }; 7076 7077 /* reg_rtar_key_type 7078 * TCAM key type for the region. 7079 * Access: WO 7080 */ 7081 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7082 7083 /* reg_rtar_region_size 7084 * TCAM region size. When allocating/resizing this is the requested 7085 * size, the response is the actual size. 7086 * Note: Actual size may be larger than requested. 7087 * Reserved for op = Deallocate 7088 * Access: WO 7089 */ 7090 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7091 7092 static inline void mlxsw_reg_rtar_pack(char *payload, 7093 enum mlxsw_reg_rtar_op op, 7094 enum mlxsw_reg_rtar_key_type key_type, 7095 u16 region_size) 7096 { 7097 MLXSW_REG_ZERO(rtar, payload); 7098 mlxsw_reg_rtar_op_set(payload, op); 7099 mlxsw_reg_rtar_key_type_set(payload, key_type); 7100 mlxsw_reg_rtar_region_size_set(payload, region_size); 7101 } 7102 7103 /* RATR - Router Adjacency Table Register 7104 * -------------------------------------- 7105 * The RATR register is used to configure the Router Adjacency (next-hop) 7106 * Table. 7107 */ 7108 #define MLXSW_REG_RATR_ID 0x8008 7109 #define MLXSW_REG_RATR_LEN 0x2C 7110 7111 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7112 7113 enum mlxsw_reg_ratr_op { 7114 /* Read */ 7115 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7116 /* Read and clear activity */ 7117 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7118 /* Write Adjacency entry */ 7119 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7120 /* Write Adjacency entry only if the activity is cleared. 7121 * The write may not succeed if the activity is set. There is not 7122 * direct feedback if the write has succeeded or not, however 7123 * the get will reveal the actual entry (SW can compare the get 7124 * response to the set command). 7125 */ 7126 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7127 }; 7128 7129 /* reg_ratr_op 7130 * Note that Write operation may also be used for updating 7131 * counter_set_type and counter_index. In this case all other 7132 * fields must not be updated. 7133 * Access: OP 7134 */ 7135 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7136 7137 /* reg_ratr_v 7138 * Valid bit. Indicates if the adjacency entry is valid. 7139 * Note: the device may need some time before reusing an invalidated 7140 * entry. During this time the entry can not be reused. It is 7141 * recommended to use another entry before reusing an invalidated 7142 * entry (e.g. software can put it at the end of the list for 7143 * reusing). Trying to access an invalidated entry not yet cleared 7144 * by the device results with failure indicating "Try Again" status. 7145 * When valid is '0' then egress_router_interface,trap_action, 7146 * adjacency_parameters and counters are reserved 7147 * Access: RW 7148 */ 7149 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7150 7151 /* reg_ratr_a 7152 * Activity. Set for new entries. Set if a packet lookup has hit on 7153 * the specific entry. To clear the a bit, use "clear activity". 7154 * Access: RO 7155 */ 7156 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7157 7158 enum mlxsw_reg_ratr_type { 7159 /* Ethernet */ 7160 MLXSW_REG_RATR_TYPE_ETHERNET, 7161 /* IPoIB Unicast without GRH. 7162 * Reserved for Spectrum. 7163 */ 7164 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7165 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7166 * adjacency). 7167 * Reserved for Spectrum. 7168 */ 7169 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7170 /* IPoIB Multicast. 7171 * Reserved for Spectrum. 7172 */ 7173 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7174 /* MPLS. 7175 * Reserved for SwitchX/-2. 7176 */ 7177 MLXSW_REG_RATR_TYPE_MPLS, 7178 /* IPinIP Encap. 7179 * Reserved for SwitchX/-2. 7180 */ 7181 MLXSW_REG_RATR_TYPE_IPIP, 7182 }; 7183 7184 /* reg_ratr_type 7185 * Adjacency entry type. 7186 * Access: RW 7187 */ 7188 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7189 7190 /* reg_ratr_adjacency_index_low 7191 * Bits 15:0 of index into the adjacency table. 7192 * For SwitchX and SwitchX-2, the adjacency table is linear and 7193 * used for adjacency entries only. 7194 * For Spectrum, the index is to the KVD linear. 7195 * Access: Index 7196 */ 7197 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7198 7199 /* reg_ratr_egress_router_interface 7200 * Range is 0 .. cap_max_router_interfaces - 1 7201 * Access: RW 7202 */ 7203 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7204 7205 enum mlxsw_reg_ratr_trap_action { 7206 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7207 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7208 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7209 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7210 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7211 }; 7212 7213 /* reg_ratr_trap_action 7214 * see mlxsw_reg_ratr_trap_action 7215 * Access: RW 7216 */ 7217 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7218 7219 /* reg_ratr_adjacency_index_high 7220 * Bits 23:16 of the adjacency_index. 7221 * Access: Index 7222 */ 7223 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7224 7225 enum mlxsw_reg_ratr_trap_id { 7226 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7227 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7228 }; 7229 7230 /* reg_ratr_trap_id 7231 * Trap ID to be reported to CPU. 7232 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7233 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7234 * Access: RW 7235 */ 7236 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7237 7238 /* reg_ratr_eth_destination_mac 7239 * MAC address of the destination next-hop. 7240 * Access: RW 7241 */ 7242 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7243 7244 enum mlxsw_reg_ratr_ipip_type { 7245 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7246 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7247 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7248 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7249 }; 7250 7251 /* reg_ratr_ipip_type 7252 * Underlay destination ip type. 7253 * Note: the type field must match the protocol of the router interface. 7254 * Access: RW 7255 */ 7256 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7257 7258 /* reg_ratr_ipip_ipv4_udip 7259 * Underlay ipv4 dip. 7260 * Reserved when ipip_type is IPv6. 7261 * Access: RW 7262 */ 7263 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7264 7265 /* reg_ratr_ipip_ipv6_ptr 7266 * Pointer to IPv6 underlay destination ip address. 7267 * For Spectrum: Pointer to KVD linear space. 7268 * Access: RW 7269 */ 7270 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7271 7272 enum mlxsw_reg_flow_counter_set_type { 7273 /* No count */ 7274 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7275 /* Count packets and bytes */ 7276 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7277 /* Count only packets */ 7278 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7279 }; 7280 7281 /* reg_ratr_counter_set_type 7282 * Counter set type for flow counters 7283 * Access: RW 7284 */ 7285 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7286 7287 /* reg_ratr_counter_index 7288 * Counter index for flow counters 7289 * Access: RW 7290 */ 7291 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7292 7293 static inline void 7294 mlxsw_reg_ratr_pack(char *payload, 7295 enum mlxsw_reg_ratr_op op, bool valid, 7296 enum mlxsw_reg_ratr_type type, 7297 u32 adjacency_index, u16 egress_rif) 7298 { 7299 MLXSW_REG_ZERO(ratr, payload); 7300 mlxsw_reg_ratr_op_set(payload, op); 7301 mlxsw_reg_ratr_v_set(payload, valid); 7302 mlxsw_reg_ratr_type_set(payload, type); 7303 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7304 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7305 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7306 } 7307 7308 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7309 const char *dest_mac) 7310 { 7311 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7312 } 7313 7314 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7315 { 7316 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7317 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7318 } 7319 7320 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7321 { 7322 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7323 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7324 } 7325 7326 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7327 bool counter_enable) 7328 { 7329 enum mlxsw_reg_flow_counter_set_type set_type; 7330 7331 if (counter_enable) 7332 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7333 else 7334 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7335 7336 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7337 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7338 } 7339 7340 /* RDPM - Router DSCP to Priority Mapping 7341 * -------------------------------------- 7342 * Controls the mapping from DSCP field to switch priority on routed packets 7343 */ 7344 #define MLXSW_REG_RDPM_ID 0x8009 7345 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7346 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7347 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7348 #define MLXSW_REG_RDPM_LEN 0x40 7349 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7350 MLXSW_REG_RDPM_LEN - \ 7351 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7352 7353 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7354 7355 /* reg_dscp_entry_e 7356 * Enable update of the specific entry 7357 * Access: Index 7358 */ 7359 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7360 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7361 7362 /* reg_dscp_entry_prio 7363 * Switch Priority 7364 * Access: RW 7365 */ 7366 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7367 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7368 7369 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7370 u8 prio) 7371 { 7372 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7373 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7374 } 7375 7376 /* RICNT - Router Interface Counter Register 7377 * ----------------------------------------- 7378 * The RICNT register retrieves per port performance counters 7379 */ 7380 #define MLXSW_REG_RICNT_ID 0x800B 7381 #define MLXSW_REG_RICNT_LEN 0x100 7382 7383 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7384 7385 /* reg_ricnt_counter_index 7386 * Counter index 7387 * Access: RW 7388 */ 7389 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7390 7391 enum mlxsw_reg_ricnt_counter_set_type { 7392 /* No Count. */ 7393 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7394 /* Basic. Used for router interfaces, counting the following: 7395 * - Error and Discard counters. 7396 * - Unicast, Multicast and Broadcast counters. Sharing the 7397 * same set of counters for the different type of traffic 7398 * (IPv4, IPv6 and mpls). 7399 */ 7400 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7401 }; 7402 7403 /* reg_ricnt_counter_set_type 7404 * Counter Set Type for router interface counter 7405 * Access: RW 7406 */ 7407 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7408 7409 enum mlxsw_reg_ricnt_opcode { 7410 /* Nop. Supported only for read access*/ 7411 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7412 /* Clear. Setting the clr bit will reset the counter value for 7413 * all counters of the specified Router Interface. 7414 */ 7415 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7416 }; 7417 7418 /* reg_ricnt_opcode 7419 * Opcode 7420 * Access: RW 7421 */ 7422 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7423 7424 /* reg_ricnt_good_unicast_packets 7425 * good unicast packets. 7426 * Access: RW 7427 */ 7428 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7429 7430 /* reg_ricnt_good_multicast_packets 7431 * good multicast packets. 7432 * Access: RW 7433 */ 7434 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7435 7436 /* reg_ricnt_good_broadcast_packets 7437 * good broadcast packets 7438 * Access: RW 7439 */ 7440 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7441 7442 /* reg_ricnt_good_unicast_bytes 7443 * A count of L3 data and padding octets not including L2 headers 7444 * for good unicast frames. 7445 * Access: RW 7446 */ 7447 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7448 7449 /* reg_ricnt_good_multicast_bytes 7450 * A count of L3 data and padding octets not including L2 headers 7451 * for good multicast frames. 7452 * Access: RW 7453 */ 7454 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7455 7456 /* reg_ritr_good_broadcast_bytes 7457 * A count of L3 data and padding octets not including L2 headers 7458 * for good broadcast frames. 7459 * Access: RW 7460 */ 7461 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7462 7463 /* reg_ricnt_error_packets 7464 * A count of errored frames that do not pass the router checks. 7465 * Access: RW 7466 */ 7467 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7468 7469 /* reg_ricnt_discrad_packets 7470 * A count of non-errored frames that do not pass the router checks. 7471 * Access: RW 7472 */ 7473 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7474 7475 /* reg_ricnt_error_bytes 7476 * A count of L3 data and padding octets not including L2 headers 7477 * for errored frames. 7478 * Access: RW 7479 */ 7480 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7481 7482 /* reg_ricnt_discard_bytes 7483 * A count of L3 data and padding octets not including L2 headers 7484 * for non-errored frames that do not pass the router checks. 7485 * Access: RW 7486 */ 7487 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7488 7489 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7490 enum mlxsw_reg_ricnt_opcode op) 7491 { 7492 MLXSW_REG_ZERO(ricnt, payload); 7493 mlxsw_reg_ricnt_op_set(payload, op); 7494 mlxsw_reg_ricnt_counter_index_set(payload, index); 7495 mlxsw_reg_ricnt_counter_set_type_set(payload, 7496 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7497 } 7498 7499 /* RRCR - Router Rules Copy Register Layout 7500 * ---------------------------------------- 7501 * This register is used for moving and copying route entry rules. 7502 */ 7503 #define MLXSW_REG_RRCR_ID 0x800F 7504 #define MLXSW_REG_RRCR_LEN 0x24 7505 7506 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7507 7508 enum mlxsw_reg_rrcr_op { 7509 /* Move rules */ 7510 MLXSW_REG_RRCR_OP_MOVE, 7511 /* Copy rules */ 7512 MLXSW_REG_RRCR_OP_COPY, 7513 }; 7514 7515 /* reg_rrcr_op 7516 * Access: WO 7517 */ 7518 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7519 7520 /* reg_rrcr_offset 7521 * Offset within the region from which to copy/move. 7522 * Access: Index 7523 */ 7524 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7525 7526 /* reg_rrcr_size 7527 * The number of rules to copy/move. 7528 * Access: WO 7529 */ 7530 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7531 7532 /* reg_rrcr_table_id 7533 * Identifier of the table on which to perform the operation. Encoding is the 7534 * same as in RTAR.key_type 7535 * Access: Index 7536 */ 7537 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7538 7539 /* reg_rrcr_dest_offset 7540 * Offset within the region to which to copy/move 7541 * Access: Index 7542 */ 7543 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7544 7545 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7546 u16 offset, u16 size, 7547 enum mlxsw_reg_rtar_key_type table_id, 7548 u16 dest_offset) 7549 { 7550 MLXSW_REG_ZERO(rrcr, payload); 7551 mlxsw_reg_rrcr_op_set(payload, op); 7552 mlxsw_reg_rrcr_offset_set(payload, offset); 7553 mlxsw_reg_rrcr_size_set(payload, size); 7554 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7555 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7556 } 7557 7558 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7559 * ------------------------------------------------------- 7560 * RALTA is used to allocate the LPM trees of the SHSPM method. 7561 */ 7562 #define MLXSW_REG_RALTA_ID 0x8010 7563 #define MLXSW_REG_RALTA_LEN 0x04 7564 7565 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7566 7567 /* reg_ralta_op 7568 * opcode (valid for Write, must be 0 on Read) 7569 * 0 - allocate a tree 7570 * 1 - deallocate a tree 7571 * Access: OP 7572 */ 7573 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7574 7575 enum mlxsw_reg_ralxx_protocol { 7576 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7577 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7578 }; 7579 7580 /* reg_ralta_protocol 7581 * Protocol. 7582 * Deallocation opcode: Reserved. 7583 * Access: RW 7584 */ 7585 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7586 7587 /* reg_ralta_tree_id 7588 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7589 * the tree identifier (managed by software). 7590 * Note that tree_id 0 is allocated for a default-route tree. 7591 * Access: Index 7592 */ 7593 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7594 7595 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7596 enum mlxsw_reg_ralxx_protocol protocol, 7597 u8 tree_id) 7598 { 7599 MLXSW_REG_ZERO(ralta, payload); 7600 mlxsw_reg_ralta_op_set(payload, !alloc); 7601 mlxsw_reg_ralta_protocol_set(payload, protocol); 7602 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7603 } 7604 7605 /* RALST - Router Algorithmic LPM Structure Tree Register 7606 * ------------------------------------------------------ 7607 * RALST is used to set and query the structure of an LPM tree. 7608 * The structure of the tree must be sorted as a sorted binary tree, while 7609 * each node is a bin that is tagged as the length of the prefixes the lookup 7610 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7611 * of X bits to match with the destination address. The bin 0 indicates 7612 * the default action, when there is no match of any prefix. 7613 */ 7614 #define MLXSW_REG_RALST_ID 0x8011 7615 #define MLXSW_REG_RALST_LEN 0x104 7616 7617 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7618 7619 /* reg_ralst_root_bin 7620 * The bin number of the root bin. 7621 * 0<root_bin=<(length of IP address) 7622 * For a default-route tree configure 0xff 7623 * Access: RW 7624 */ 7625 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7626 7627 /* reg_ralst_tree_id 7628 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7629 * Access: Index 7630 */ 7631 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7632 7633 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7634 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7635 #define MLXSW_REG_RALST_BIN_COUNT 128 7636 7637 /* reg_ralst_left_child_bin 7638 * Holding the children of the bin according to the stored tree's structure. 7639 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7640 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7641 * Access: RW 7642 */ 7643 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7644 7645 /* reg_ralst_right_child_bin 7646 * Holding the children of the bin according to the stored tree's structure. 7647 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7648 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7649 * Access: RW 7650 */ 7651 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7652 false); 7653 7654 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7655 { 7656 MLXSW_REG_ZERO(ralst, payload); 7657 7658 /* Initialize all bins to have no left or right child */ 7659 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7660 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7661 7662 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7663 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7664 } 7665 7666 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7667 u8 left_child_bin, 7668 u8 right_child_bin) 7669 { 7670 int bin_index = bin_number - 1; 7671 7672 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7673 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7674 right_child_bin); 7675 } 7676 7677 /* RALTB - Router Algorithmic LPM Tree Binding Register 7678 * ---------------------------------------------------- 7679 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7680 */ 7681 #define MLXSW_REG_RALTB_ID 0x8012 7682 #define MLXSW_REG_RALTB_LEN 0x04 7683 7684 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7685 7686 /* reg_raltb_virtual_router 7687 * Virtual Router ID 7688 * Range is 0..cap_max_virtual_routers-1 7689 * Access: Index 7690 */ 7691 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7692 7693 /* reg_raltb_protocol 7694 * Protocol. 7695 * Access: Index 7696 */ 7697 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7698 7699 /* reg_raltb_tree_id 7700 * Tree to be used for the {virtual_router, protocol} 7701 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7702 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7703 * Access: RW 7704 */ 7705 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7706 7707 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7708 enum mlxsw_reg_ralxx_protocol protocol, 7709 u8 tree_id) 7710 { 7711 MLXSW_REG_ZERO(raltb, payload); 7712 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7713 mlxsw_reg_raltb_protocol_set(payload, protocol); 7714 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7715 } 7716 7717 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7718 * ----------------------------------------------------- 7719 * RALUE is used to configure and query LPM entries that serve 7720 * the Unicast protocols. 7721 */ 7722 #define MLXSW_REG_RALUE_ID 0x8013 7723 #define MLXSW_REG_RALUE_LEN 0x38 7724 7725 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7726 7727 /* reg_ralue_protocol 7728 * Protocol. 7729 * Access: Index 7730 */ 7731 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7732 7733 enum mlxsw_reg_ralue_op { 7734 /* Read operation. If entry doesn't exist, the operation fails. */ 7735 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7736 /* Clear on read operation. Used to read entry and 7737 * clear Activity bit. 7738 */ 7739 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7740 /* Write operation. Used to write a new entry to the table. All RW 7741 * fields are written for new entry. Activity bit is set 7742 * for new entries. 7743 */ 7744 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7745 /* Update operation. Used to update an existing route entry and 7746 * only update the RW fields that are detailed in the field 7747 * op_u_mask. If entry doesn't exist, the operation fails. 7748 */ 7749 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7750 /* Clear activity. The Activity bit (the field a) is cleared 7751 * for the entry. 7752 */ 7753 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7754 /* Delete operation. Used to delete an existing entry. If entry 7755 * doesn't exist, the operation fails. 7756 */ 7757 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7758 }; 7759 7760 /* reg_ralue_op 7761 * Operation. 7762 * Access: OP 7763 */ 7764 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7765 7766 /* reg_ralue_a 7767 * Activity. Set for new entries. Set if a packet lookup has hit on the 7768 * specific entry, only if the entry is a route. To clear the a bit, use 7769 * "clear activity" op. 7770 * Enabled by activity_dis in RGCR 7771 * Access: RO 7772 */ 7773 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7774 7775 /* reg_ralue_virtual_router 7776 * Virtual Router ID 7777 * Range is 0..cap_max_virtual_routers-1 7778 * Access: Index 7779 */ 7780 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7781 7782 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7783 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7784 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7785 7786 /* reg_ralue_op_u_mask 7787 * opcode update mask. 7788 * On read operation, this field is reserved. 7789 * This field is valid for update opcode, otherwise - reserved. 7790 * This field is a bitmask of the fields that should be updated. 7791 * Access: WO 7792 */ 7793 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7794 7795 /* reg_ralue_prefix_len 7796 * Number of bits in the prefix of the LPM route. 7797 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7798 * two entries in the physical HW table. 7799 * Access: Index 7800 */ 7801 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7802 7803 /* reg_ralue_dip* 7804 * The prefix of the route or of the marker that the object of the LPM 7805 * is compared with. The most significant bits of the dip are the prefix. 7806 * The least significant bits must be '0' if the prefix_len is smaller 7807 * than 128 for IPv6 or smaller than 32 for IPv4. 7808 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7809 * Access: Index 7810 */ 7811 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7812 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7813 7814 enum mlxsw_reg_ralue_entry_type { 7815 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7816 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7817 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7818 }; 7819 7820 /* reg_ralue_entry_type 7821 * Entry type. 7822 * Note - for Marker entries, the action_type and action fields are reserved. 7823 * Access: RW 7824 */ 7825 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7826 7827 /* reg_ralue_bmp_len 7828 * The best match prefix length in the case that there is no match for 7829 * longer prefixes. 7830 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7831 * Note for any update operation with entry_type modification this 7832 * field must be set. 7833 * Access: RW 7834 */ 7835 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7836 7837 enum mlxsw_reg_ralue_action_type { 7838 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7839 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7840 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7841 }; 7842 7843 /* reg_ralue_action_type 7844 * Action Type 7845 * Indicates how the IP address is connected. 7846 * It can be connected to a local subnet through local_erif or can be 7847 * on a remote subnet connected through a next-hop router, 7848 * or transmitted to the CPU. 7849 * Reserved when entry_type = MARKER_ENTRY 7850 * Access: RW 7851 */ 7852 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7853 7854 enum mlxsw_reg_ralue_trap_action { 7855 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7856 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7857 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7858 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7859 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7860 }; 7861 7862 /* reg_ralue_trap_action 7863 * Trap action. 7864 * For IP2ME action, only NOP and MIRROR are possible. 7865 * Access: RW 7866 */ 7867 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7868 7869 /* reg_ralue_trap_id 7870 * Trap ID to be reported to CPU. 7871 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7872 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7873 * Access: RW 7874 */ 7875 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7876 7877 /* reg_ralue_adjacency_index 7878 * Points to the first entry of the group-based ECMP. 7879 * Only relevant in case of REMOTE action. 7880 * Access: RW 7881 */ 7882 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7883 7884 /* reg_ralue_ecmp_size 7885 * Amount of sequential entries starting 7886 * from the adjacency_index (the number of ECMPs). 7887 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7888 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7889 * Only relevant in case of REMOTE action. 7890 * Access: RW 7891 */ 7892 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7893 7894 /* reg_ralue_local_erif 7895 * Egress Router Interface. 7896 * Only relevant in case of LOCAL action. 7897 * Access: RW 7898 */ 7899 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7900 7901 /* reg_ralue_ip2me_v 7902 * Valid bit for the tunnel_ptr field. 7903 * If valid = 0 then trap to CPU as IP2ME trap ID. 7904 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7905 * decapsulation then tunnel decapsulation is done. 7906 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7907 * decapsulation then trap as IP2ME trap ID. 7908 * Only relevant in case of IP2ME action. 7909 * Access: RW 7910 */ 7911 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7912 7913 /* reg_ralue_ip2me_tunnel_ptr 7914 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7915 * For Spectrum, pointer to KVD Linear. 7916 * Only relevant in case of IP2ME action. 7917 * Access: RW 7918 */ 7919 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7920 7921 static inline void mlxsw_reg_ralue_pack(char *payload, 7922 enum mlxsw_reg_ralxx_protocol protocol, 7923 enum mlxsw_reg_ralue_op op, 7924 u16 virtual_router, u8 prefix_len) 7925 { 7926 MLXSW_REG_ZERO(ralue, payload); 7927 mlxsw_reg_ralue_protocol_set(payload, protocol); 7928 mlxsw_reg_ralue_op_set(payload, op); 7929 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7930 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7931 mlxsw_reg_ralue_entry_type_set(payload, 7932 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7933 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7934 } 7935 7936 static inline void mlxsw_reg_ralue_pack4(char *payload, 7937 enum mlxsw_reg_ralxx_protocol protocol, 7938 enum mlxsw_reg_ralue_op op, 7939 u16 virtual_router, u8 prefix_len, 7940 u32 dip) 7941 { 7942 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7943 mlxsw_reg_ralue_dip4_set(payload, dip); 7944 } 7945 7946 static inline void mlxsw_reg_ralue_pack6(char *payload, 7947 enum mlxsw_reg_ralxx_protocol protocol, 7948 enum mlxsw_reg_ralue_op op, 7949 u16 virtual_router, u8 prefix_len, 7950 const void *dip) 7951 { 7952 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7953 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7954 } 7955 7956 static inline void 7957 mlxsw_reg_ralue_act_remote_pack(char *payload, 7958 enum mlxsw_reg_ralue_trap_action trap_action, 7959 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7960 { 7961 mlxsw_reg_ralue_action_type_set(payload, 7962 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7963 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7964 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7965 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7966 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7967 } 7968 7969 static inline void 7970 mlxsw_reg_ralue_act_local_pack(char *payload, 7971 enum mlxsw_reg_ralue_trap_action trap_action, 7972 u16 trap_id, u16 local_erif) 7973 { 7974 mlxsw_reg_ralue_action_type_set(payload, 7975 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7976 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7977 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7978 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7979 } 7980 7981 static inline void 7982 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7983 { 7984 mlxsw_reg_ralue_action_type_set(payload, 7985 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7986 } 7987 7988 static inline void 7989 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7990 { 7991 mlxsw_reg_ralue_action_type_set(payload, 7992 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7993 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7994 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7995 } 7996 7997 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7998 * ---------------------------------------------------------- 7999 * The RAUHT register is used to configure and query the Unicast Host table in 8000 * devices that implement the Algorithmic LPM. 8001 */ 8002 #define MLXSW_REG_RAUHT_ID 0x8014 8003 #define MLXSW_REG_RAUHT_LEN 0x74 8004 8005 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8006 8007 enum mlxsw_reg_rauht_type { 8008 MLXSW_REG_RAUHT_TYPE_IPV4, 8009 MLXSW_REG_RAUHT_TYPE_IPV6, 8010 }; 8011 8012 /* reg_rauht_type 8013 * Access: Index 8014 */ 8015 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8016 8017 enum mlxsw_reg_rauht_op { 8018 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8019 /* Read operation */ 8020 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8021 /* Clear on read operation. Used to read entry and clear 8022 * activity bit. 8023 */ 8024 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8025 /* Add. Used to write a new entry to the table. All R/W fields are 8026 * relevant for new entry. Activity bit is set for new entries. 8027 */ 8028 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8029 /* Update action. Used to update an existing route entry and 8030 * only update the following fields: 8031 * trap_action, trap_id, mac, counter_set_type, counter_index 8032 */ 8033 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8034 /* Clear activity. A bit is cleared for the entry. */ 8035 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8036 /* Delete entry */ 8037 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8038 /* Delete all host entries on a RIF. In this command, dip 8039 * field is reserved. 8040 */ 8041 }; 8042 8043 /* reg_rauht_op 8044 * Access: OP 8045 */ 8046 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8047 8048 /* reg_rauht_a 8049 * Activity. Set for new entries. Set if a packet lookup has hit on 8050 * the specific entry. 8051 * To clear the a bit, use "clear activity" op. 8052 * Enabled by activity_dis in RGCR 8053 * Access: RO 8054 */ 8055 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8056 8057 /* reg_rauht_rif 8058 * Router Interface 8059 * Access: Index 8060 */ 8061 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8062 8063 /* reg_rauht_dip* 8064 * Destination address. 8065 * Access: Index 8066 */ 8067 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8068 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8069 8070 enum mlxsw_reg_rauht_trap_action { 8071 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8072 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8073 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8074 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8075 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8076 }; 8077 8078 /* reg_rauht_trap_action 8079 * Access: RW 8080 */ 8081 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8082 8083 enum mlxsw_reg_rauht_trap_id { 8084 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8085 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8086 }; 8087 8088 /* reg_rauht_trap_id 8089 * Trap ID to be reported to CPU. 8090 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8091 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8092 * trap_id is reserved. 8093 * Access: RW 8094 */ 8095 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8096 8097 /* reg_rauht_counter_set_type 8098 * Counter set type for flow counters 8099 * Access: RW 8100 */ 8101 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8102 8103 /* reg_rauht_counter_index 8104 * Counter index for flow counters 8105 * Access: RW 8106 */ 8107 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8108 8109 /* reg_rauht_mac 8110 * MAC address. 8111 * Access: RW 8112 */ 8113 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8114 8115 static inline void mlxsw_reg_rauht_pack(char *payload, 8116 enum mlxsw_reg_rauht_op op, u16 rif, 8117 const char *mac) 8118 { 8119 MLXSW_REG_ZERO(rauht, payload); 8120 mlxsw_reg_rauht_op_set(payload, op); 8121 mlxsw_reg_rauht_rif_set(payload, rif); 8122 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8123 } 8124 8125 static inline void mlxsw_reg_rauht_pack4(char *payload, 8126 enum mlxsw_reg_rauht_op op, u16 rif, 8127 const char *mac, u32 dip) 8128 { 8129 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8130 mlxsw_reg_rauht_dip4_set(payload, dip); 8131 } 8132 8133 static inline void mlxsw_reg_rauht_pack6(char *payload, 8134 enum mlxsw_reg_rauht_op op, u16 rif, 8135 const char *mac, const char *dip) 8136 { 8137 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8138 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8139 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8140 } 8141 8142 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8143 u64 counter_index) 8144 { 8145 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8146 mlxsw_reg_rauht_counter_set_type_set(payload, 8147 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8148 } 8149 8150 /* RALEU - Router Algorithmic LPM ECMP Update Register 8151 * --------------------------------------------------- 8152 * The register enables updating the ECMP section in the action for multiple 8153 * LPM Unicast entries in a single operation. The update is executed to 8154 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8155 */ 8156 #define MLXSW_REG_RALEU_ID 0x8015 8157 #define MLXSW_REG_RALEU_LEN 0x28 8158 8159 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8160 8161 /* reg_raleu_protocol 8162 * Protocol. 8163 * Access: Index 8164 */ 8165 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8166 8167 /* reg_raleu_virtual_router 8168 * Virtual Router ID 8169 * Range is 0..cap_max_virtual_routers-1 8170 * Access: Index 8171 */ 8172 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8173 8174 /* reg_raleu_adjacency_index 8175 * Adjacency Index used for matching on the existing entries. 8176 * Access: Index 8177 */ 8178 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8179 8180 /* reg_raleu_ecmp_size 8181 * ECMP Size used for matching on the existing entries. 8182 * Access: Index 8183 */ 8184 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8185 8186 /* reg_raleu_new_adjacency_index 8187 * New Adjacency Index. 8188 * Access: WO 8189 */ 8190 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8191 8192 /* reg_raleu_new_ecmp_size 8193 * New ECMP Size. 8194 * Access: WO 8195 */ 8196 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8197 8198 static inline void mlxsw_reg_raleu_pack(char *payload, 8199 enum mlxsw_reg_ralxx_protocol protocol, 8200 u16 virtual_router, 8201 u32 adjacency_index, u16 ecmp_size, 8202 u32 new_adjacency_index, 8203 u16 new_ecmp_size) 8204 { 8205 MLXSW_REG_ZERO(raleu, payload); 8206 mlxsw_reg_raleu_protocol_set(payload, protocol); 8207 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8208 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8209 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8210 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8211 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8212 } 8213 8214 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8215 * ---------------------------------------------------------------- 8216 * The RAUHTD register allows dumping entries from the Router Unicast Host 8217 * Table. For a given session an entry is dumped no more than one time. The 8218 * first RAUHTD access after reset is a new session. A session ends when the 8219 * num_rec response is smaller than num_rec request or for IPv4 when the 8220 * num_entries is smaller than 4. The clear activity affect the current session 8221 * or the last session if a new session has not started. 8222 */ 8223 #define MLXSW_REG_RAUHTD_ID 0x8018 8224 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8225 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8226 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8227 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8228 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8229 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8230 8231 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8232 8233 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8234 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8235 8236 /* reg_rauhtd_filter_fields 8237 * if a bit is '0' then the relevant field is ignored and dump is done 8238 * regardless of the field value 8239 * Bit0 - filter by activity: entry_a 8240 * Bit3 - filter by entry rip: entry_rif 8241 * Access: Index 8242 */ 8243 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8244 8245 enum mlxsw_reg_rauhtd_op { 8246 MLXSW_REG_RAUHTD_OP_DUMP, 8247 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8248 }; 8249 8250 /* reg_rauhtd_op 8251 * Access: OP 8252 */ 8253 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8254 8255 /* reg_rauhtd_num_rec 8256 * At request: number of records requested 8257 * At response: number of records dumped 8258 * For IPv4, each record has 4 entries at request and up to 4 entries 8259 * at response 8260 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8261 * Access: Index 8262 */ 8263 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8264 8265 /* reg_rauhtd_entry_a 8266 * Dump only if activity has value of entry_a 8267 * Reserved if filter_fields bit0 is '0' 8268 * Access: Index 8269 */ 8270 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8271 8272 enum mlxsw_reg_rauhtd_type { 8273 MLXSW_REG_RAUHTD_TYPE_IPV4, 8274 MLXSW_REG_RAUHTD_TYPE_IPV6, 8275 }; 8276 8277 /* reg_rauhtd_type 8278 * Dump only if record type is: 8279 * 0 - IPv4 8280 * 1 - IPv6 8281 * Access: Index 8282 */ 8283 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8284 8285 /* reg_rauhtd_entry_rif 8286 * Dump only if RIF has value of entry_rif 8287 * Reserved if filter_fields bit3 is '0' 8288 * Access: Index 8289 */ 8290 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8291 8292 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8293 enum mlxsw_reg_rauhtd_type type) 8294 { 8295 MLXSW_REG_ZERO(rauhtd, payload); 8296 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8297 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8298 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8299 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8300 mlxsw_reg_rauhtd_type_set(payload, type); 8301 } 8302 8303 /* reg_rauhtd_ipv4_rec_num_entries 8304 * Number of valid entries in this record: 8305 * 0 - 1 valid entry 8306 * 1 - 2 valid entries 8307 * 2 - 3 valid entries 8308 * 3 - 4 valid entries 8309 * Access: RO 8310 */ 8311 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8312 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8313 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8314 8315 /* reg_rauhtd_rec_type 8316 * Record type. 8317 * 0 - IPv4 8318 * 1 - IPv6 8319 * Access: RO 8320 */ 8321 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8322 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8323 8324 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8325 8326 /* reg_rauhtd_ipv4_ent_a 8327 * Activity. Set for new entries. Set if a packet lookup has hit on the 8328 * specific entry. 8329 * Access: RO 8330 */ 8331 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8332 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8333 8334 /* reg_rauhtd_ipv4_ent_rif 8335 * Router interface. 8336 * Access: RO 8337 */ 8338 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8339 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8340 8341 /* reg_rauhtd_ipv4_ent_dip 8342 * Destination IPv4 address. 8343 * Access: RO 8344 */ 8345 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8346 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8347 8348 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8349 8350 /* reg_rauhtd_ipv6_ent_a 8351 * Activity. Set for new entries. Set if a packet lookup has hit on the 8352 * specific entry. 8353 * Access: RO 8354 */ 8355 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8356 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8357 8358 /* reg_rauhtd_ipv6_ent_rif 8359 * Router interface. 8360 * Access: RO 8361 */ 8362 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8363 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8364 8365 /* reg_rauhtd_ipv6_ent_dip 8366 * Destination IPv6 address. 8367 * Access: RO 8368 */ 8369 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8370 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8371 8372 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8373 int ent_index, u16 *p_rif, 8374 u32 *p_dip) 8375 { 8376 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8377 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8378 } 8379 8380 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8381 int rec_index, u16 *p_rif, 8382 char *p_dip) 8383 { 8384 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8385 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8386 } 8387 8388 /* RTDP - Routing Tunnel Decap Properties Register 8389 * ----------------------------------------------- 8390 * The RTDP register is used for configuring the tunnel decap properties of NVE 8391 * and IPinIP. 8392 */ 8393 #define MLXSW_REG_RTDP_ID 0x8020 8394 #define MLXSW_REG_RTDP_LEN 0x44 8395 8396 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8397 8398 enum mlxsw_reg_rtdp_type { 8399 MLXSW_REG_RTDP_TYPE_NVE, 8400 MLXSW_REG_RTDP_TYPE_IPIP, 8401 }; 8402 8403 /* reg_rtdp_type 8404 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8405 * Access: RW 8406 */ 8407 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8408 8409 /* reg_rtdp_tunnel_index 8410 * Index to the Decap entry. 8411 * For Spectrum, Index to KVD Linear. 8412 * Access: Index 8413 */ 8414 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8415 8416 /* reg_rtdp_egress_router_interface 8417 * Underlay egress router interface. 8418 * Valid range is from 0 to cap_max_router_interfaces - 1 8419 * Access: RW 8420 */ 8421 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8422 8423 /* IPinIP */ 8424 8425 /* reg_rtdp_ipip_irif 8426 * Ingress Router Interface for the overlay router 8427 * Access: RW 8428 */ 8429 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8430 8431 enum mlxsw_reg_rtdp_ipip_sip_check { 8432 /* No sip checks. */ 8433 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8434 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8435 * equal ipv4_usip. 8436 */ 8437 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8438 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8439 * equal ipv6_usip. 8440 */ 8441 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8442 }; 8443 8444 /* reg_rtdp_ipip_sip_check 8445 * SIP check to perform. If decapsulation failed due to these configurations 8446 * then trap_id is IPIP_DECAP_ERROR. 8447 * Access: RW 8448 */ 8449 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8450 8451 /* If set, allow decapsulation of IPinIP (without GRE). */ 8452 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8453 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8454 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8455 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8456 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8457 8458 /* reg_rtdp_ipip_type_check 8459 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8460 * these configurations then trap_id is IPIP_DECAP_ERROR. 8461 * Access: RW 8462 */ 8463 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8464 8465 /* reg_rtdp_ipip_gre_key_check 8466 * Whether GRE key should be checked. When check is enabled: 8467 * - A packet received as IPinIP (without GRE) will always pass. 8468 * - A packet received as IPinGREinIP without a key will not pass the check. 8469 * - A packet received as IPinGREinIP with a key will pass the check only if the 8470 * key in the packet is equal to expected_gre_key. 8471 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8472 * Access: RW 8473 */ 8474 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8475 8476 /* reg_rtdp_ipip_ipv4_usip 8477 * Underlay IPv4 address for ipv4 source address check. 8478 * Reserved when sip_check is not '1'. 8479 * Access: RW 8480 */ 8481 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8482 8483 /* reg_rtdp_ipip_ipv6_usip_ptr 8484 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8485 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8486 * is to the KVD linear. 8487 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8488 * Access: RW 8489 */ 8490 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8491 8492 /* reg_rtdp_ipip_expected_gre_key 8493 * GRE key for checking. 8494 * Reserved when gre_key_check is '0'. 8495 * Access: RW 8496 */ 8497 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8498 8499 static inline void mlxsw_reg_rtdp_pack(char *payload, 8500 enum mlxsw_reg_rtdp_type type, 8501 u32 tunnel_index) 8502 { 8503 MLXSW_REG_ZERO(rtdp, payload); 8504 mlxsw_reg_rtdp_type_set(payload, type); 8505 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8506 } 8507 8508 static inline void 8509 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8510 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8511 unsigned int type_check, bool gre_key_check, 8512 u32 expected_gre_key) 8513 { 8514 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8515 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8516 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8517 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8518 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8519 } 8520 8521 static inline void 8522 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8523 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8524 unsigned int type_check, bool gre_key_check, 8525 u32 ipv4_usip, u32 expected_gre_key) 8526 { 8527 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8528 gre_key_check, expected_gre_key); 8529 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8530 } 8531 8532 static inline void 8533 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8534 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8535 unsigned int type_check, bool gre_key_check, 8536 u32 ipv6_usip_ptr, u32 expected_gre_key) 8537 { 8538 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8539 gre_key_check, expected_gre_key); 8540 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8541 } 8542 8543 /* RIPS - Router IP version Six Register 8544 * ------------------------------------- 8545 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8546 * IPinIP 8547 */ 8548 #define MLXSW_REG_RIPS_ID 0x8021 8549 #define MLXSW_REG_RIPS_LEN 0x14 8550 8551 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8552 8553 /* reg_rips_index 8554 * Index to IPv6 address. 8555 * For Spectrum, the index is to the KVD linear. 8556 * Access: Index 8557 */ 8558 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8559 8560 /* reg_rips_ipv6 8561 * IPv6 address 8562 * Access: RW 8563 */ 8564 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8565 8566 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8567 const struct in6_addr *ipv6) 8568 { 8569 MLXSW_REG_ZERO(rips, payload); 8570 mlxsw_reg_rips_index_set(payload, index); 8571 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8572 } 8573 8574 /* RATRAD - Router Adjacency Table Activity Dump Register 8575 * ------------------------------------------------------ 8576 * The RATRAD register is used to dump and optionally clear activity bits of 8577 * router adjacency table entries. 8578 */ 8579 #define MLXSW_REG_RATRAD_ID 0x8022 8580 #define MLXSW_REG_RATRAD_LEN 0x210 8581 8582 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8583 8584 enum { 8585 /* Read activity */ 8586 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8587 /* Read and clear activity */ 8588 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8589 }; 8590 8591 /* reg_ratrad_op 8592 * Access: Operation 8593 */ 8594 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8595 8596 /* reg_ratrad_ecmp_size 8597 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8598 * ranges: 8599 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8600 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8601 * Access: Index 8602 */ 8603 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8604 8605 /* reg_ratrad_adjacency_index 8606 * Index into the adjacency table. 8607 * Access: Index 8608 */ 8609 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8610 8611 /* reg_ratrad_activity_vector 8612 * Activity bit per adjacency index. 8613 * Bits higher than ecmp_size are reserved. 8614 * Access: RO 8615 */ 8616 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8617 8618 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8619 u16 ecmp_size) 8620 { 8621 MLXSW_REG_ZERO(ratrad, payload); 8622 mlxsw_reg_ratrad_op_set(payload, 8623 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8624 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8625 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8626 } 8627 8628 /* RIGR-V2 - Router Interface Group Register Version 2 8629 * --------------------------------------------------- 8630 * The RIGR_V2 register is used to add, remove and query egress interface list 8631 * of a multicast forwarding entry. 8632 */ 8633 #define MLXSW_REG_RIGR2_ID 0x8023 8634 #define MLXSW_REG_RIGR2_LEN 0xB0 8635 8636 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8637 8638 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8639 8640 /* reg_rigr2_rigr_index 8641 * KVD Linear index. 8642 * Access: Index 8643 */ 8644 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8645 8646 /* reg_rigr2_vnext 8647 * Next RIGR Index is valid. 8648 * Access: RW 8649 */ 8650 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8651 8652 /* reg_rigr2_next_rigr_index 8653 * Next RIGR Index. The index is to the KVD linear. 8654 * Reserved when vnxet = '0'. 8655 * Access: RW 8656 */ 8657 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8658 8659 /* reg_rigr2_vrmid 8660 * RMID Index is valid. 8661 * Access: RW 8662 */ 8663 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8664 8665 /* reg_rigr2_rmid_index 8666 * RMID Index. 8667 * Range 0 .. max_mid - 1 8668 * Reserved when vrmid = '0'. 8669 * The index is to the Port Group Table (PGT) 8670 * Access: RW 8671 */ 8672 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8673 8674 /* reg_rigr2_erif_entry_v 8675 * Egress Router Interface is valid. 8676 * Note that low-entries must be set if high-entries are set. For 8677 * example: if erif_entry[2].v is set then erif_entry[1].v and 8678 * erif_entry[0].v must be set. 8679 * Index can be from 0 to cap_mc_erif_list_entries-1 8680 * Access: RW 8681 */ 8682 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8683 8684 /* reg_rigr2_erif_entry_erif 8685 * Egress Router Interface. 8686 * Valid range is from 0 to cap_max_router_interfaces - 1 8687 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8688 * Access: RW 8689 */ 8690 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8691 8692 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8693 bool vnext, u32 next_rigr_index) 8694 { 8695 MLXSW_REG_ZERO(rigr2, payload); 8696 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8697 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8698 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8699 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8700 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8701 } 8702 8703 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8704 bool v, u16 erif) 8705 { 8706 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8707 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8708 } 8709 8710 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8711 * ------------------------------------------------------ 8712 */ 8713 #define MLXSW_REG_RECR2_ID 0x8025 8714 #define MLXSW_REG_RECR2_LEN 0x38 8715 8716 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8717 8718 /* reg_recr2_pp 8719 * Per-port configuration 8720 * Access: Index 8721 */ 8722 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8723 8724 /* reg_recr2_sh 8725 * Symmetric hash 8726 * Access: RW 8727 */ 8728 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8729 8730 /* reg_recr2_seed 8731 * Seed 8732 * Access: RW 8733 */ 8734 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8735 8736 enum { 8737 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8738 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8739 /* Enable IPv4 fields if packet is TCP or UDP */ 8740 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8741 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8742 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8743 /* Enable IPv6 fields if packet is TCP or UDP */ 8744 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8745 /* Enable TCP/UDP header fields if packet is IPv4 */ 8746 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8747 /* Enable TCP/UDP header fields if packet is IPv6 */ 8748 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8749 8750 __MLXSW_REG_RECR2_HEADER_CNT, 8751 }; 8752 8753 /* reg_recr2_outer_header_enables 8754 * Bit mask where each bit enables a specific layer to be included in 8755 * the hash calculation. 8756 * Access: RW 8757 */ 8758 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8759 8760 enum { 8761 /* IPv4 Source IP */ 8762 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8763 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8764 /* IPv4 Destination IP */ 8765 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8766 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8767 /* IP Protocol */ 8768 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8769 /* IPv6 Source IP */ 8770 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8771 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8772 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8773 /* IPv6 Destination IP */ 8774 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8775 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8776 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8777 /* IPv6 Next Header */ 8778 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8779 /* IPv6 Flow Label */ 8780 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8781 /* TCP/UDP Source Port */ 8782 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8783 /* TCP/UDP Destination Port */ 8784 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8785 8786 __MLXSW_REG_RECR2_FIELD_CNT, 8787 }; 8788 8789 /* reg_recr2_outer_header_fields_enable 8790 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8791 * Access: RW 8792 */ 8793 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8794 8795 /* reg_recr2_inner_header_enables 8796 * Bit mask where each bit enables a specific inner layer to be included in the 8797 * hash calculation. Same values as reg_recr2_outer_header_enables. 8798 * Access: RW 8799 */ 8800 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8801 8802 enum { 8803 /* Inner IPv4 Source IP */ 8804 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8805 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8806 /* Inner IPv4 Destination IP */ 8807 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8808 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8809 /* Inner IP Protocol */ 8810 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8811 /* Inner IPv6 Source IP */ 8812 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8813 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8814 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8815 /* Inner IPv6 Destination IP */ 8816 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8817 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8818 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8819 /* Inner IPv6 Next Header */ 8820 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8821 /* Inner IPv6 Flow Label */ 8822 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8823 /* Inner TCP/UDP Source Port */ 8824 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8825 /* Inner TCP/UDP Destination Port */ 8826 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8827 8828 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8829 }; 8830 8831 /* reg_recr2_inner_header_fields_enable 8832 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8833 * Access: RW 8834 */ 8835 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8836 8837 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8838 { 8839 MLXSW_REG_ZERO(recr2, payload); 8840 mlxsw_reg_recr2_pp_set(payload, false); 8841 mlxsw_reg_recr2_sh_set(payload, true); 8842 mlxsw_reg_recr2_seed_set(payload, seed); 8843 } 8844 8845 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8846 * -------------------------------------------------------------- 8847 * The RMFT_V2 register is used to configure and query the multicast table. 8848 */ 8849 #define MLXSW_REG_RMFT2_ID 0x8027 8850 #define MLXSW_REG_RMFT2_LEN 0x174 8851 8852 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8853 8854 /* reg_rmft2_v 8855 * Valid 8856 * Access: RW 8857 */ 8858 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8859 8860 enum mlxsw_reg_rmft2_type { 8861 MLXSW_REG_RMFT2_TYPE_IPV4, 8862 MLXSW_REG_RMFT2_TYPE_IPV6 8863 }; 8864 8865 /* reg_rmft2_type 8866 * Access: Index 8867 */ 8868 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8869 8870 enum mlxsw_sp_reg_rmft2_op { 8871 /* For Write: 8872 * Write operation. Used to write a new entry to the table. All RW 8873 * fields are relevant for new entry. Activity bit is set for new 8874 * entries - Note write with v (Valid) 0 will delete the entry. 8875 * For Query: 8876 * Read operation 8877 */ 8878 MLXSW_REG_RMFT2_OP_READ_WRITE, 8879 }; 8880 8881 /* reg_rmft2_op 8882 * Operation. 8883 * Access: OP 8884 */ 8885 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8886 8887 /* reg_rmft2_a 8888 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8889 * entry. 8890 * Access: RO 8891 */ 8892 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8893 8894 /* reg_rmft2_offset 8895 * Offset within the multicast forwarding table to write to. 8896 * Access: Index 8897 */ 8898 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8899 8900 /* reg_rmft2_virtual_router 8901 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8902 * Access: RW 8903 */ 8904 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8905 8906 enum mlxsw_reg_rmft2_irif_mask { 8907 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8908 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8909 }; 8910 8911 /* reg_rmft2_irif_mask 8912 * Ingress RIF mask. 8913 * Access: RW 8914 */ 8915 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8916 8917 /* reg_rmft2_irif 8918 * Ingress RIF index. 8919 * Access: RW 8920 */ 8921 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8922 8923 /* reg_rmft2_dip{4,6} 8924 * Destination IPv4/6 address 8925 * Access: RW 8926 */ 8927 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8928 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8929 8930 /* reg_rmft2_dip{4,6}_mask 8931 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8932 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8933 * Access: RW 8934 */ 8935 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8936 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8937 8938 /* reg_rmft2_sip{4,6} 8939 * Source IPv4/6 address 8940 * Access: RW 8941 */ 8942 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8943 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8944 8945 /* reg_rmft2_sip{4,6}_mask 8946 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8947 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8948 * Access: RW 8949 */ 8950 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8951 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8952 8953 /* reg_rmft2_flexible_action_set 8954 * ACL action set. The only supported action types in this field and in any 8955 * action-set pointed from here are as follows: 8956 * 00h: ACTION_NULL 8957 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8958 * 03h: ACTION_TRAP 8959 * 06h: ACTION_QOS 8960 * 08h: ACTION_POLICING_MONITORING 8961 * 10h: ACTION_ROUTER_MC 8962 * Access: RW 8963 */ 8964 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8965 MLXSW_REG_FLEX_ACTION_SET_LEN); 8966 8967 static inline void 8968 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8969 u16 virtual_router, 8970 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8971 const char *flex_action_set) 8972 { 8973 MLXSW_REG_ZERO(rmft2, payload); 8974 mlxsw_reg_rmft2_v_set(payload, v); 8975 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8976 mlxsw_reg_rmft2_offset_set(payload, offset); 8977 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8978 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8979 mlxsw_reg_rmft2_irif_set(payload, irif); 8980 if (flex_action_set) 8981 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8982 flex_action_set); 8983 } 8984 8985 static inline void 8986 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8987 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8988 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8989 const char *flexible_action_set) 8990 { 8991 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8992 irif_mask, irif, flexible_action_set); 8993 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8994 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8995 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8996 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8997 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8998 } 8999 9000 static inline void 9001 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9002 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9003 struct in6_addr dip6, struct in6_addr dip6_mask, 9004 struct in6_addr sip6, struct in6_addr sip6_mask, 9005 const char *flexible_action_set) 9006 { 9007 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9008 irif_mask, irif, flexible_action_set); 9009 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9010 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9011 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9012 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9013 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9014 } 9015 9016 /* REIV - Router Egress Interface to VID Register 9017 * ---------------------------------------------- 9018 * The REIV register maps {eRIF, egress_port} -> VID. 9019 * This mapping is done at the egress, after the ACLs. 9020 * This mapping always takes effect after router, regardless of cast 9021 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9022 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9023 * Reserved when the RIF is a loopback RIF. 9024 * 9025 * Note: Reserved when legacy bridge model is used. 9026 */ 9027 #define MLXSW_REG_REIV_ID 0x8034 9028 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9029 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9030 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9031 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9032 MLXSW_REG_REIV_REC_LEN * \ 9033 MLXSW_REG_REIV_REC_MAX_COUNT) 9034 9035 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9036 9037 /* reg_reiv_port_page 9038 * Port page - elport_record[0] is 256*port_page. 9039 * Access: Index 9040 */ 9041 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9042 9043 /* reg_reiv_erif 9044 * Egress RIF. 9045 * Range is 0..cap_max_router_interfaces-1. 9046 * Access: Index 9047 */ 9048 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9049 9050 /* reg_reiv_rec_update 9051 * Update enable (when write): 9052 * 0 - Do not update the entry. 9053 * 1 - Update the entry. 9054 * Access: OP 9055 */ 9056 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9057 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9058 9059 /* reg_reiv_rec_evid 9060 * Egress VID. 9061 * Range is 0..4095. 9062 * Access: RW 9063 */ 9064 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9065 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9066 9067 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9068 { 9069 MLXSW_REG_ZERO(reiv, payload); 9070 mlxsw_reg_reiv_port_page_set(payload, port_page); 9071 mlxsw_reg_reiv_erif_set(payload, erif); 9072 } 9073 9074 /* MFCR - Management Fan Control Register 9075 * -------------------------------------- 9076 * This register controls the settings of the Fan Speed PWM mechanism. 9077 */ 9078 #define MLXSW_REG_MFCR_ID 0x9001 9079 #define MLXSW_REG_MFCR_LEN 0x08 9080 9081 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9082 9083 enum mlxsw_reg_mfcr_pwm_frequency { 9084 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9085 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9086 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9087 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9088 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9089 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9090 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9091 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9092 }; 9093 9094 /* reg_mfcr_pwm_frequency 9095 * Controls the frequency of the PWM signal. 9096 * Access: RW 9097 */ 9098 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9099 9100 #define MLXSW_MFCR_TACHOS_MAX 10 9101 9102 /* reg_mfcr_tacho_active 9103 * Indicates which of the tachometer is active (bit per tachometer). 9104 * Access: RO 9105 */ 9106 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9107 9108 #define MLXSW_MFCR_PWMS_MAX 5 9109 9110 /* reg_mfcr_pwm_active 9111 * Indicates which of the PWM control is active (bit per PWM). 9112 * Access: RO 9113 */ 9114 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9115 9116 static inline void 9117 mlxsw_reg_mfcr_pack(char *payload, 9118 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9119 { 9120 MLXSW_REG_ZERO(mfcr, payload); 9121 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9122 } 9123 9124 static inline void 9125 mlxsw_reg_mfcr_unpack(char *payload, 9126 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9127 u16 *p_tacho_active, u8 *p_pwm_active) 9128 { 9129 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9130 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9131 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9132 } 9133 9134 /* MFSC - Management Fan Speed Control Register 9135 * -------------------------------------------- 9136 * This register controls the settings of the Fan Speed PWM mechanism. 9137 */ 9138 #define MLXSW_REG_MFSC_ID 0x9002 9139 #define MLXSW_REG_MFSC_LEN 0x08 9140 9141 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9142 9143 /* reg_mfsc_pwm 9144 * Fan pwm to control / monitor. 9145 * Access: Index 9146 */ 9147 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9148 9149 /* reg_mfsc_pwm_duty_cycle 9150 * Controls the duty cycle of the PWM. Value range from 0..255 to 9151 * represent duty cycle of 0%...100%. 9152 * Access: RW 9153 */ 9154 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9155 9156 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9157 u8 pwm_duty_cycle) 9158 { 9159 MLXSW_REG_ZERO(mfsc, payload); 9160 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9161 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9162 } 9163 9164 /* MFSM - Management Fan Speed Measurement 9165 * --------------------------------------- 9166 * This register controls the settings of the Tacho measurements and 9167 * enables reading the Tachometer measurements. 9168 */ 9169 #define MLXSW_REG_MFSM_ID 0x9003 9170 #define MLXSW_REG_MFSM_LEN 0x08 9171 9172 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9173 9174 /* reg_mfsm_tacho 9175 * Fan tachometer index. 9176 * Access: Index 9177 */ 9178 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9179 9180 /* reg_mfsm_rpm 9181 * Fan speed (round per minute). 9182 * Access: RO 9183 */ 9184 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9185 9186 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9187 { 9188 MLXSW_REG_ZERO(mfsm, payload); 9189 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9190 } 9191 9192 /* MFSL - Management Fan Speed Limit Register 9193 * ------------------------------------------ 9194 * The Fan Speed Limit register is used to configure the fan speed 9195 * event / interrupt notification mechanism. Fan speed threshold are 9196 * defined for both under-speed and over-speed. 9197 */ 9198 #define MLXSW_REG_MFSL_ID 0x9004 9199 #define MLXSW_REG_MFSL_LEN 0x0C 9200 9201 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9202 9203 /* reg_mfsl_tacho 9204 * Fan tachometer index. 9205 * Access: Index 9206 */ 9207 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9208 9209 /* reg_mfsl_tach_min 9210 * Tachometer minimum value (minimum RPM). 9211 * Access: RW 9212 */ 9213 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9214 9215 /* reg_mfsl_tach_max 9216 * Tachometer maximum value (maximum RPM). 9217 * Access: RW 9218 */ 9219 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9220 9221 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9222 u16 tach_min, u16 tach_max) 9223 { 9224 MLXSW_REG_ZERO(mfsl, payload); 9225 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9226 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9227 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9228 } 9229 9230 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9231 u16 *p_tach_min, u16 *p_tach_max) 9232 { 9233 if (p_tach_min) 9234 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9235 9236 if (p_tach_max) 9237 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9238 } 9239 9240 /* FORE - Fan Out of Range Event Register 9241 * -------------------------------------- 9242 * This register reports the status of the controlled fans compared to the 9243 * range defined by the MFSL register. 9244 */ 9245 #define MLXSW_REG_FORE_ID 0x9007 9246 #define MLXSW_REG_FORE_LEN 0x0C 9247 9248 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9249 9250 /* fan_under_limit 9251 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9252 * to a single tachometer and indicates the specific tachometer reading is 9253 * below the threshold. 9254 * Access: RO 9255 */ 9256 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9257 9258 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9259 bool *fault) 9260 { 9261 u16 limit; 9262 9263 if (fault) { 9264 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9265 *fault = limit & BIT(tacho); 9266 } 9267 } 9268 9269 /* MTCAP - Management Temperature Capabilities 9270 * ------------------------------------------- 9271 * This register exposes the capabilities of the device and 9272 * system temperature sensing. 9273 */ 9274 #define MLXSW_REG_MTCAP_ID 0x9009 9275 #define MLXSW_REG_MTCAP_LEN 0x08 9276 9277 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9278 9279 /* reg_mtcap_sensor_count 9280 * Number of sensors supported by the device. 9281 * This includes the QSFP module sensors (if exists in the QSFP module). 9282 * Access: RO 9283 */ 9284 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9285 9286 /* MTMP - Management Temperature 9287 * ----------------------------- 9288 * This register controls the settings of the temperature measurements 9289 * and enables reading the temperature measurements. Note that temperature 9290 * is in 0.125 degrees Celsius. 9291 */ 9292 #define MLXSW_REG_MTMP_ID 0x900A 9293 #define MLXSW_REG_MTMP_LEN 0x20 9294 9295 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9296 9297 /* reg_mtmp_slot_index 9298 * Slot index (0: Main board). 9299 * Access: Index 9300 */ 9301 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9302 9303 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9304 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9305 /* reg_mtmp_sensor_index 9306 * Sensors index to access. 9307 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9308 * (module 0 is mapped to sensor_index 64). 9309 * Access: Index 9310 */ 9311 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9312 9313 /* Convert to milli degrees Celsius */ 9314 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9315 ((v_) >= 0) ? ((v_) * 125) : \ 9316 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9317 * 125)); }) 9318 9319 /* reg_mtmp_max_operational_temperature 9320 * The highest temperature in the nominal operational range. Reading is in 9321 * 0.125 Celsius degrees units. 9322 * In case of module this is SFF critical temperature threshold. 9323 * Access: RO 9324 */ 9325 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9326 9327 /* reg_mtmp_temperature 9328 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9329 * degrees units. 9330 * Access: RO 9331 */ 9332 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9333 9334 /* reg_mtmp_mte 9335 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9336 * Access: RW 9337 */ 9338 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9339 9340 /* reg_mtmp_mtr 9341 * Max Temperature Reset - clears the value of the max temperature register. 9342 * Access: WO 9343 */ 9344 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9345 9346 /* reg_mtmp_max_temperature 9347 * The highest measured temperature from the sensor. 9348 * When the bit mte is cleared, the field max_temperature is reserved. 9349 * Access: RO 9350 */ 9351 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9352 9353 /* reg_mtmp_tee 9354 * Temperature Event Enable. 9355 * 0 - Do not generate event 9356 * 1 - Generate event 9357 * 2 - Generate single event 9358 * Access: RW 9359 */ 9360 9361 enum mlxsw_reg_mtmp_tee { 9362 MLXSW_REG_MTMP_TEE_NO_EVENT, 9363 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9364 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9365 }; 9366 9367 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9368 9369 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9370 9371 /* reg_mtmp_temperature_threshold_hi 9372 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9373 * Access: RW 9374 */ 9375 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9376 9377 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9378 /* reg_mtmp_temperature_threshold_lo 9379 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9380 * Access: RW 9381 */ 9382 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9383 9384 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9385 9386 /* reg_mtmp_sensor_name 9387 * Sensor Name 9388 * Access: RO 9389 */ 9390 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9391 9392 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9393 u16 sensor_index, bool max_temp_enable, 9394 bool max_temp_reset) 9395 { 9396 MLXSW_REG_ZERO(mtmp, payload); 9397 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9398 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9399 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9400 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9401 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9402 MLXSW_REG_MTMP_THRESH_HI); 9403 } 9404 9405 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9406 int *p_max_temp, int *p_temp_hi, 9407 int *p_max_oper_temp, 9408 char *sensor_name) 9409 { 9410 s16 temp; 9411 9412 if (p_temp) { 9413 temp = mlxsw_reg_mtmp_temperature_get(payload); 9414 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9415 } 9416 if (p_max_temp) { 9417 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9418 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9419 } 9420 if (p_temp_hi) { 9421 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9422 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9423 } 9424 if (p_max_oper_temp) { 9425 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9426 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9427 } 9428 if (sensor_name) 9429 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9430 } 9431 9432 /* MTWE - Management Temperature Warning Event 9433 * ------------------------------------------- 9434 * This register is used for over temperature warning. 9435 */ 9436 #define MLXSW_REG_MTWE_ID 0x900B 9437 #define MLXSW_REG_MTWE_LEN 0x10 9438 9439 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9440 9441 /* reg_mtwe_sensor_warning 9442 * Bit vector indicating which of the sensor reading is above threshold. 9443 * Address 00h bit31 is sensor_warning[127]. 9444 * Address 0Ch bit0 is sensor_warning[0]. 9445 * Access: RO 9446 */ 9447 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9448 9449 /* MTBR - Management Temperature Bulk Register 9450 * ------------------------------------------- 9451 * This register is used for bulk temperature reading. 9452 */ 9453 #define MLXSW_REG_MTBR_ID 0x900F 9454 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9455 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9456 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9457 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9458 MLXSW_REG_MTBR_REC_LEN * \ 9459 MLXSW_REG_MTBR_REC_MAX_COUNT) 9460 9461 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9462 9463 /* reg_mtbr_slot_index 9464 * Slot index (0: Main board). 9465 * Access: Index 9466 */ 9467 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9468 9469 /* reg_mtbr_base_sensor_index 9470 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9471 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9472 * Access: Index 9473 */ 9474 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9475 9476 /* reg_mtbr_num_rec 9477 * Request: Number of records to read 9478 * Response: Number of records read 9479 * See above description for more details. 9480 * Range 1..255 9481 * Access: RW 9482 */ 9483 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9484 9485 /* reg_mtbr_rec_max_temp 9486 * The highest measured temperature from the sensor. 9487 * When the bit mte is cleared, the field max_temperature is reserved. 9488 * Access: RO 9489 */ 9490 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9491 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9492 9493 /* reg_mtbr_rec_temp 9494 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9495 * degrees units. 9496 * Access: RO 9497 */ 9498 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9499 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9500 9501 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9502 u16 base_sensor_index, u8 num_rec) 9503 { 9504 MLXSW_REG_ZERO(mtbr, payload); 9505 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9506 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9507 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9508 } 9509 9510 /* Error codes from temperatute reading */ 9511 enum mlxsw_reg_mtbr_temp_status { 9512 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9513 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9514 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9515 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9516 }; 9517 9518 /* Base index for reading modules temperature */ 9519 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9520 9521 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9522 u16 *p_temp, u16 *p_max_temp) 9523 { 9524 if (p_temp) 9525 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9526 if (p_max_temp) 9527 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9528 } 9529 9530 /* MCIA - Management Cable Info Access 9531 * ----------------------------------- 9532 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9533 */ 9534 9535 #define MLXSW_REG_MCIA_ID 0x9014 9536 #define MLXSW_REG_MCIA_LEN 0x40 9537 9538 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9539 9540 /* reg_mcia_l 9541 * Lock bit. Setting this bit will lock the access to the specific 9542 * cable. Used for updating a full page in a cable EPROM. Any access 9543 * other then subsequence writes will fail while the port is locked. 9544 * Access: RW 9545 */ 9546 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9547 9548 /* reg_mcia_module 9549 * Module number. 9550 * Access: Index 9551 */ 9552 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9553 9554 /* reg_mcia_slot_index 9555 * Slot index (0: Main board) 9556 * Access: Index 9557 */ 9558 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9559 9560 enum { 9561 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9562 /* No response from module's EEPROM. */ 9563 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9564 /* Module type not supported by the device. */ 9565 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9566 /* No module present indication. */ 9567 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9568 /* Error occurred while trying to access module's EEPROM using I2C. */ 9569 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9570 /* Module is disabled. */ 9571 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9572 }; 9573 9574 /* reg_mcia_status 9575 * Module status. 9576 * Access: RO 9577 */ 9578 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9579 9580 /* reg_mcia_i2c_device_address 9581 * I2C device address. 9582 * Access: RW 9583 */ 9584 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9585 9586 /* reg_mcia_page_number 9587 * Page number. 9588 * Access: RW 9589 */ 9590 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9591 9592 /* reg_mcia_device_address 9593 * Device address. 9594 * Access: RW 9595 */ 9596 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9597 9598 /* reg_mcia_bank_number 9599 * Bank number. 9600 * Access: Index 9601 */ 9602 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9603 9604 /* reg_mcia_size 9605 * Number of bytes to read/write (up to 48 bytes). 9606 * Access: RW 9607 */ 9608 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9609 9610 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9611 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9612 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9613 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9614 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9615 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9616 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9617 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9618 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9619 #define MLXSW_REG_MCIA_PAGE0_LO 0 9620 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9621 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9622 9623 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9624 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9625 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9626 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9627 }; 9628 9629 enum mlxsw_reg_mcia_eeprom_module_info_id { 9630 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9631 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9632 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9633 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9634 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9635 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9636 }; 9637 9638 enum mlxsw_reg_mcia_eeprom_module_info { 9639 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9640 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9641 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9642 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9643 }; 9644 9645 /* reg_mcia_eeprom 9646 * Bytes to read/write. 9647 * Access: RW 9648 */ 9649 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9650 9651 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9652 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9653 * on offset 384 through 511, page 3 - on offset 512 through 639. 9654 */ 9655 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9656 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9657 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9658 9659 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9660 u8 lock, u8 page_number, 9661 u16 device_addr, u8 size, 9662 u8 i2c_device_addr) 9663 { 9664 MLXSW_REG_ZERO(mcia, payload); 9665 mlxsw_reg_mcia_slot_set(payload, slot_index); 9666 mlxsw_reg_mcia_module_set(payload, module); 9667 mlxsw_reg_mcia_l_set(payload, lock); 9668 mlxsw_reg_mcia_page_number_set(payload, page_number); 9669 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9670 mlxsw_reg_mcia_size_set(payload, size); 9671 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9672 } 9673 9674 /* MPAT - Monitoring Port Analyzer Table 9675 * ------------------------------------- 9676 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9677 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9678 */ 9679 #define MLXSW_REG_MPAT_ID 0x901A 9680 #define MLXSW_REG_MPAT_LEN 0x78 9681 9682 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9683 9684 /* reg_mpat_pa_id 9685 * Port Analyzer ID. 9686 * Access: Index 9687 */ 9688 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9689 9690 /* reg_mpat_session_id 9691 * Mirror Session ID. 9692 * Used for MIRROR_SESSION<i> trap. 9693 * Access: RW 9694 */ 9695 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9696 9697 /* reg_mpat_system_port 9698 * A unique port identifier for the final destination of the packet. 9699 * Access: RW 9700 */ 9701 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9702 9703 /* reg_mpat_e 9704 * Enable. Indicating the Port Analyzer is enabled. 9705 * Access: RW 9706 */ 9707 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9708 9709 /* reg_mpat_qos 9710 * Quality Of Service Mode. 9711 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9712 * PCP, DEI, DSCP or VL) are configured. 9713 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9714 * same as in the original packet that has triggered the mirroring. For 9715 * SPAN also the pcp,dei are maintained. 9716 * Access: RW 9717 */ 9718 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9719 9720 /* reg_mpat_be 9721 * Best effort mode. Indicates mirroring traffic should not cause packet 9722 * drop or back pressure, but will discard the mirrored packets. Mirrored 9723 * packets will be forwarded on a best effort manner. 9724 * 0: Do not discard mirrored packets 9725 * 1: Discard mirrored packets if causing congestion 9726 * Access: RW 9727 */ 9728 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9729 9730 enum mlxsw_reg_mpat_span_type { 9731 /* Local SPAN Ethernet. 9732 * The original packet is not encapsulated. 9733 */ 9734 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9735 9736 /* Remote SPAN Ethernet VLAN. 9737 * The packet is forwarded to the monitoring port on the monitoring 9738 * VLAN. 9739 */ 9740 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9741 9742 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9743 * The packet is encapsulated with GRE header. 9744 */ 9745 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9746 }; 9747 9748 /* reg_mpat_span_type 9749 * SPAN type. 9750 * Access: RW 9751 */ 9752 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9753 9754 /* reg_mpat_pide 9755 * Policer enable. 9756 * Access: RW 9757 */ 9758 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9759 9760 /* reg_mpat_pid 9761 * Policer ID. 9762 * Access: RW 9763 */ 9764 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9765 9766 /* Remote SPAN - Ethernet VLAN 9767 * - - - - - - - - - - - - - - 9768 */ 9769 9770 /* reg_mpat_eth_rspan_vid 9771 * Encapsulation header VLAN ID. 9772 * Access: RW 9773 */ 9774 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9775 9776 /* Encapsulated Remote SPAN - Ethernet L2 9777 * - - - - - - - - - - - - - - - - - - - 9778 */ 9779 9780 enum mlxsw_reg_mpat_eth_rspan_version { 9781 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9782 }; 9783 9784 /* reg_mpat_eth_rspan_version 9785 * RSPAN mirror header version. 9786 * Access: RW 9787 */ 9788 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9789 9790 /* reg_mpat_eth_rspan_mac 9791 * Destination MAC address. 9792 * Access: RW 9793 */ 9794 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9795 9796 /* reg_mpat_eth_rspan_tp 9797 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9798 * Access: RW 9799 */ 9800 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9801 9802 /* Encapsulated Remote SPAN - Ethernet L3 9803 * - - - - - - - - - - - - - - - - - - - 9804 */ 9805 9806 enum mlxsw_reg_mpat_eth_rspan_protocol { 9807 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9808 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9809 }; 9810 9811 /* reg_mpat_eth_rspan_protocol 9812 * SPAN encapsulation protocol. 9813 * Access: RW 9814 */ 9815 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9816 9817 /* reg_mpat_eth_rspan_ttl 9818 * Encapsulation header Time-to-Live/HopLimit. 9819 * Access: RW 9820 */ 9821 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9822 9823 /* reg_mpat_eth_rspan_smac 9824 * Source MAC address 9825 * Access: RW 9826 */ 9827 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9828 9829 /* reg_mpat_eth_rspan_dip* 9830 * Destination IP address. The IP version is configured by protocol. 9831 * Access: RW 9832 */ 9833 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9834 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9835 9836 /* reg_mpat_eth_rspan_sip* 9837 * Source IP address. The IP version is configured by protocol. 9838 * Access: RW 9839 */ 9840 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9841 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9842 9843 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9844 u16 system_port, bool e, 9845 enum mlxsw_reg_mpat_span_type span_type) 9846 { 9847 MLXSW_REG_ZERO(mpat, payload); 9848 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9849 mlxsw_reg_mpat_system_port_set(payload, system_port); 9850 mlxsw_reg_mpat_e_set(payload, e); 9851 mlxsw_reg_mpat_qos_set(payload, 1); 9852 mlxsw_reg_mpat_be_set(payload, 1); 9853 mlxsw_reg_mpat_span_type_set(payload, span_type); 9854 } 9855 9856 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9857 { 9858 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9859 } 9860 9861 static inline void 9862 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9863 enum mlxsw_reg_mpat_eth_rspan_version version, 9864 const char *mac, 9865 bool tp) 9866 { 9867 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9868 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9869 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9870 } 9871 9872 static inline void 9873 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9874 const char *smac, 9875 u32 sip, u32 dip) 9876 { 9877 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9878 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9879 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9880 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9881 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9882 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9883 } 9884 9885 static inline void 9886 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9887 const char *smac, 9888 struct in6_addr sip, struct in6_addr dip) 9889 { 9890 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9891 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9892 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9893 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9894 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9895 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9896 } 9897 9898 /* MPAR - Monitoring Port Analyzer Register 9899 * ---------------------------------------- 9900 * MPAR register is used to query and configure the port analyzer port mirroring 9901 * properties. 9902 */ 9903 #define MLXSW_REG_MPAR_ID 0x901B 9904 #define MLXSW_REG_MPAR_LEN 0x0C 9905 9906 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9907 9908 /* reg_mpar_local_port 9909 * The local port to mirror the packets from. 9910 * Access: Index 9911 */ 9912 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 9913 9914 enum mlxsw_reg_mpar_i_e { 9915 MLXSW_REG_MPAR_TYPE_EGRESS, 9916 MLXSW_REG_MPAR_TYPE_INGRESS, 9917 }; 9918 9919 /* reg_mpar_i_e 9920 * Ingress/Egress 9921 * Access: Index 9922 */ 9923 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9924 9925 /* reg_mpar_enable 9926 * Enable mirroring 9927 * By default, port mirroring is disabled for all ports. 9928 * Access: RW 9929 */ 9930 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9931 9932 /* reg_mpar_pa_id 9933 * Port Analyzer ID. 9934 * Access: RW 9935 */ 9936 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9937 9938 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 9939 9940 /* reg_mpar_probability_rate 9941 * Sampling rate. 9942 * Valid values are: 1 to 3.5*10^9 9943 * Value of 1 means "sample all". Default is 1. 9944 * Reserved when Spectrum-1. 9945 * Access: RW 9946 */ 9947 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 9948 9949 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 9950 enum mlxsw_reg_mpar_i_e i_e, 9951 bool enable, u8 pa_id, 9952 u32 probability_rate) 9953 { 9954 MLXSW_REG_ZERO(mpar, payload); 9955 mlxsw_reg_mpar_local_port_set(payload, local_port); 9956 mlxsw_reg_mpar_enable_set(payload, enable); 9957 mlxsw_reg_mpar_i_e_set(payload, i_e); 9958 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9959 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 9960 } 9961 9962 /* MGIR - Management General Information Register 9963 * ---------------------------------------------- 9964 * MGIR register allows software to query the hardware and firmware general 9965 * information. 9966 */ 9967 #define MLXSW_REG_MGIR_ID 0x9020 9968 #define MLXSW_REG_MGIR_LEN 0x9C 9969 9970 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9971 9972 /* reg_mgir_hw_info_device_hw_revision 9973 * Access: RO 9974 */ 9975 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 9976 9977 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 9978 9979 /* reg_mgir_fw_info_psid 9980 * PSID (ASCII string). 9981 * Access: RO 9982 */ 9983 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 9984 9985 /* reg_mgir_fw_info_extended_major 9986 * Access: RO 9987 */ 9988 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 9989 9990 /* reg_mgir_fw_info_extended_minor 9991 * Access: RO 9992 */ 9993 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 9994 9995 /* reg_mgir_fw_info_extended_sub_minor 9996 * Access: RO 9997 */ 9998 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 9999 10000 static inline void mlxsw_reg_mgir_pack(char *payload) 10001 { 10002 MLXSW_REG_ZERO(mgir, payload); 10003 } 10004 10005 static inline void 10006 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10007 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10008 { 10009 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10010 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10011 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10012 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10013 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10014 } 10015 10016 /* MRSR - Management Reset and Shutdown Register 10017 * --------------------------------------------- 10018 * MRSR register is used to reset or shutdown the switch or 10019 * the entire system (when applicable). 10020 */ 10021 #define MLXSW_REG_MRSR_ID 0x9023 10022 #define MLXSW_REG_MRSR_LEN 0x08 10023 10024 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10025 10026 /* reg_mrsr_command 10027 * Reset/shutdown command 10028 * 0 - do nothing 10029 * 1 - software reset 10030 * Access: WO 10031 */ 10032 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10033 10034 static inline void mlxsw_reg_mrsr_pack(char *payload) 10035 { 10036 MLXSW_REG_ZERO(mrsr, payload); 10037 mlxsw_reg_mrsr_command_set(payload, 1); 10038 } 10039 10040 /* MLCR - Management LED Control Register 10041 * -------------------------------------- 10042 * Controls the system LEDs. 10043 */ 10044 #define MLXSW_REG_MLCR_ID 0x902B 10045 #define MLXSW_REG_MLCR_LEN 0x0C 10046 10047 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10048 10049 /* reg_mlcr_local_port 10050 * Local port number. 10051 * Access: RW 10052 */ 10053 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10054 10055 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10056 10057 /* reg_mlcr_beacon_duration 10058 * Duration of the beacon to be active, in seconds. 10059 * 0x0 - Will turn off the beacon. 10060 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10061 * Access: RW 10062 */ 10063 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10064 10065 /* reg_mlcr_beacon_remain 10066 * Remaining duration of the beacon, in seconds. 10067 * 0xFFFF indicates an infinite amount of time. 10068 * Access: RO 10069 */ 10070 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10071 10072 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10073 bool active) 10074 { 10075 MLXSW_REG_ZERO(mlcr, payload); 10076 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10077 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10078 MLXSW_REG_MLCR_DURATION_MAX : 0); 10079 } 10080 10081 /* MCION - Management Cable IO and Notifications Register 10082 * ------------------------------------------------------ 10083 * The MCION register is used to query transceiver modules' IO pins and other 10084 * notifications. 10085 */ 10086 #define MLXSW_REG_MCION_ID 0x9052 10087 #define MLXSW_REG_MCION_LEN 0x18 10088 10089 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10090 10091 /* reg_mcion_module 10092 * Module number. 10093 * Access: Index 10094 */ 10095 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10096 10097 /* reg_mcion_slot_index 10098 * Slot index. 10099 * Access: Index 10100 */ 10101 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10102 10103 enum { 10104 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10105 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10106 }; 10107 10108 /* reg_mcion_module_status_bits 10109 * Module IO status as defined by SFF. 10110 * Access: RO 10111 */ 10112 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10113 10114 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10115 { 10116 MLXSW_REG_ZERO(mcion, payload); 10117 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10118 mlxsw_reg_mcion_module_set(payload, module); 10119 } 10120 10121 /* MTPPS - Management Pulse Per Second Register 10122 * -------------------------------------------- 10123 * This register provides the device PPS capabilities, configure the PPS in and 10124 * out modules and holds the PPS in time stamp. 10125 */ 10126 #define MLXSW_REG_MTPPS_ID 0x9053 10127 #define MLXSW_REG_MTPPS_LEN 0x3C 10128 10129 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10130 10131 /* reg_mtpps_enable 10132 * Enables the PPS functionality the specific pin. 10133 * A boolean variable. 10134 * Access: RW 10135 */ 10136 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10137 10138 enum mlxsw_reg_mtpps_pin_mode { 10139 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10140 }; 10141 10142 /* reg_mtpps_pin_mode 10143 * Pin mode to be used. The mode must comply with the supported modes of the 10144 * requested pin. 10145 * Access: RW 10146 */ 10147 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10148 10149 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10150 10151 /* reg_mtpps_pin 10152 * Pin to be configured or queried out of the supported pins. 10153 * Access: Index 10154 */ 10155 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10156 10157 /* reg_mtpps_time_stamp 10158 * When pin_mode = pps_in, the latched device time when it was triggered from 10159 * the external GPIO pin. 10160 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10161 * time to generate next output signal. 10162 * Time is in units of device clock. 10163 * Access: RW 10164 */ 10165 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10166 10167 static inline void 10168 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10169 { 10170 MLXSW_REG_ZERO(mtpps, payload); 10171 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10172 mlxsw_reg_mtpps_pin_mode_set(payload, 10173 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10174 mlxsw_reg_mtpps_enable_set(payload, true); 10175 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10176 } 10177 10178 /* MTUTC - Management UTC Register 10179 * ------------------------------- 10180 * Configures the HW UTC counter. 10181 */ 10182 #define MLXSW_REG_MTUTC_ID 0x9055 10183 #define MLXSW_REG_MTUTC_LEN 0x1C 10184 10185 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10186 10187 enum mlxsw_reg_mtutc_operation { 10188 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10189 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10190 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10191 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10192 }; 10193 10194 /* reg_mtutc_operation 10195 * Operation. 10196 * Access: OP 10197 */ 10198 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10199 10200 /* reg_mtutc_freq_adjustment 10201 * Frequency adjustment: Every PPS the HW frequency will be 10202 * adjusted by this value. Units of HW clock, where HW counts 10203 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10204 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10205 * frequency. 10206 * Access: RW 10207 */ 10208 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10209 10210 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10211 10212 /* reg_mtutc_utc_sec 10213 * UTC seconds. 10214 * Access: WO 10215 */ 10216 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10217 10218 /* reg_mtutc_utc_nsec 10219 * UTC nSecs. 10220 * Range 0..(10^9-1) 10221 * Updated when operation is SET_TIME_IMMEDIATE. 10222 * Reserved on Spectrum-1. 10223 * Access: WO 10224 */ 10225 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10226 10227 /* reg_mtutc_time_adjustment 10228 * Time adjustment. 10229 * Units of nSec. 10230 * Range is from -32768 to +32767. 10231 * Updated when operation is ADJUST_TIME. 10232 * Reserved on Spectrum-1. 10233 * Access: WO 10234 */ 10235 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10236 10237 static inline void 10238 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10239 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10240 { 10241 MLXSW_REG_ZERO(mtutc, payload); 10242 mlxsw_reg_mtutc_operation_set(payload, oper); 10243 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10244 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10245 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10246 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10247 } 10248 10249 /* MCQI - Management Component Query Information 10250 * --------------------------------------------- 10251 * This register allows querying information about firmware components. 10252 */ 10253 #define MLXSW_REG_MCQI_ID 0x9061 10254 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10255 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10256 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10257 10258 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10259 10260 /* reg_mcqi_component_index 10261 * Index of the accessed component. 10262 * Access: Index 10263 */ 10264 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10265 10266 enum mlxfw_reg_mcqi_info_type { 10267 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10268 }; 10269 10270 /* reg_mcqi_info_type 10271 * Component properties set. 10272 * Access: RW 10273 */ 10274 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10275 10276 /* reg_mcqi_offset 10277 * The requested/returned data offset from the section start, given in bytes. 10278 * Must be DWORD aligned. 10279 * Access: RW 10280 */ 10281 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10282 10283 /* reg_mcqi_data_size 10284 * The requested/returned data size, given in bytes. If data_size is not DWORD 10285 * aligned, the last bytes are zero padded. 10286 * Access: RW 10287 */ 10288 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10289 10290 /* reg_mcqi_cap_max_component_size 10291 * Maximum size for this component, given in bytes. 10292 * Access: RO 10293 */ 10294 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10295 10296 /* reg_mcqi_cap_log_mcda_word_size 10297 * Log 2 of the access word size in bytes. Read and write access must be aligned 10298 * to the word size. Write access must be done for an integer number of words. 10299 * Access: RO 10300 */ 10301 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10302 10303 /* reg_mcqi_cap_mcda_max_write_size 10304 * Maximal write size for MCDA register 10305 * Access: RO 10306 */ 10307 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10308 10309 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10310 { 10311 MLXSW_REG_ZERO(mcqi, payload); 10312 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10313 mlxsw_reg_mcqi_info_type_set(payload, 10314 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10315 mlxsw_reg_mcqi_offset_set(payload, 0); 10316 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10317 } 10318 10319 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10320 u32 *p_cap_max_component_size, 10321 u8 *p_cap_log_mcda_word_size, 10322 u16 *p_cap_mcda_max_write_size) 10323 { 10324 *p_cap_max_component_size = 10325 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10326 *p_cap_log_mcda_word_size = 10327 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10328 *p_cap_mcda_max_write_size = 10329 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10330 } 10331 10332 /* MCC - Management Component Control 10333 * ---------------------------------- 10334 * Controls the firmware component and updates the FSM. 10335 */ 10336 #define MLXSW_REG_MCC_ID 0x9062 10337 #define MLXSW_REG_MCC_LEN 0x1C 10338 10339 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10340 10341 enum mlxsw_reg_mcc_instruction { 10342 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10343 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10344 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10345 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10346 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10347 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10348 }; 10349 10350 /* reg_mcc_instruction 10351 * Command to be executed by the FSM. 10352 * Applicable for write operation only. 10353 * Access: RW 10354 */ 10355 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10356 10357 /* reg_mcc_component_index 10358 * Index of the accessed component. Applicable only for commands that 10359 * refer to components. Otherwise, this field is reserved. 10360 * Access: Index 10361 */ 10362 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10363 10364 /* reg_mcc_update_handle 10365 * Token representing the current flow executed by the FSM. 10366 * Access: WO 10367 */ 10368 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10369 10370 /* reg_mcc_error_code 10371 * Indicates the successful completion of the instruction, or the reason it 10372 * failed 10373 * Access: RO 10374 */ 10375 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10376 10377 /* reg_mcc_control_state 10378 * Current FSM state 10379 * Access: RO 10380 */ 10381 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10382 10383 /* reg_mcc_component_size 10384 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10385 * the size may shorten the update time. Value 0x0 means that size is 10386 * unspecified. 10387 * Access: WO 10388 */ 10389 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10390 10391 static inline void mlxsw_reg_mcc_pack(char *payload, 10392 enum mlxsw_reg_mcc_instruction instr, 10393 u16 component_index, u32 update_handle, 10394 u32 component_size) 10395 { 10396 MLXSW_REG_ZERO(mcc, payload); 10397 mlxsw_reg_mcc_instruction_set(payload, instr); 10398 mlxsw_reg_mcc_component_index_set(payload, component_index); 10399 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10400 mlxsw_reg_mcc_component_size_set(payload, component_size); 10401 } 10402 10403 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10404 u8 *p_error_code, u8 *p_control_state) 10405 { 10406 if (p_update_handle) 10407 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10408 if (p_error_code) 10409 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10410 if (p_control_state) 10411 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10412 } 10413 10414 /* MCDA - Management Component Data Access 10415 * --------------------------------------- 10416 * This register allows reading and writing a firmware component. 10417 */ 10418 #define MLXSW_REG_MCDA_ID 0x9063 10419 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10420 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10421 #define MLXSW_REG_MCDA_LEN \ 10422 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10423 10424 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10425 10426 /* reg_mcda_update_handle 10427 * Token representing the current flow executed by the FSM. 10428 * Access: RW 10429 */ 10430 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10431 10432 /* reg_mcda_offset 10433 * Offset of accessed address relative to component start. Accesses must be in 10434 * accordance to log_mcda_word_size in MCQI reg. 10435 * Access: RW 10436 */ 10437 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10438 10439 /* reg_mcda_size 10440 * Size of the data accessed, given in bytes. 10441 * Access: RW 10442 */ 10443 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10444 10445 /* reg_mcda_data 10446 * Data block accessed. 10447 * Access: RW 10448 */ 10449 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10450 10451 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10452 u32 offset, u16 size, u8 *data) 10453 { 10454 int i; 10455 10456 MLXSW_REG_ZERO(mcda, payload); 10457 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10458 mlxsw_reg_mcda_offset_set(payload, offset); 10459 mlxsw_reg_mcda_size_set(payload, size); 10460 10461 for (i = 0; i < size / 4; i++) 10462 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10463 } 10464 10465 /* MPSC - Monitoring Packet Sampling Configuration Register 10466 * -------------------------------------------------------- 10467 * MPSC Register is used to configure the Packet Sampling mechanism. 10468 */ 10469 #define MLXSW_REG_MPSC_ID 0x9080 10470 #define MLXSW_REG_MPSC_LEN 0x1C 10471 10472 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10473 10474 /* reg_mpsc_local_port 10475 * Local port number 10476 * Not supported for CPU port 10477 * Access: Index 10478 */ 10479 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10480 10481 /* reg_mpsc_e 10482 * Enable sampling on port local_port 10483 * Access: RW 10484 */ 10485 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10486 10487 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10488 10489 /* reg_mpsc_rate 10490 * Sampling rate = 1 out of rate packets (with randomization around 10491 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10492 * Access: RW 10493 */ 10494 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10495 10496 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10497 u32 rate) 10498 { 10499 MLXSW_REG_ZERO(mpsc, payload); 10500 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10501 mlxsw_reg_mpsc_e_set(payload, e); 10502 mlxsw_reg_mpsc_rate_set(payload, rate); 10503 } 10504 10505 /* MGPC - Monitoring General Purpose Counter Set Register 10506 * The MGPC register retrieves and sets the General Purpose Counter Set. 10507 */ 10508 #define MLXSW_REG_MGPC_ID 0x9081 10509 #define MLXSW_REG_MGPC_LEN 0x18 10510 10511 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10512 10513 /* reg_mgpc_counter_set_type 10514 * Counter set type. 10515 * Access: OP 10516 */ 10517 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10518 10519 /* reg_mgpc_counter_index 10520 * Counter index. 10521 * Access: Index 10522 */ 10523 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10524 10525 enum mlxsw_reg_mgpc_opcode { 10526 /* Nop */ 10527 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10528 /* Clear counters */ 10529 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10530 }; 10531 10532 /* reg_mgpc_opcode 10533 * Opcode. 10534 * Access: OP 10535 */ 10536 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10537 10538 /* reg_mgpc_byte_counter 10539 * Byte counter value. 10540 * Access: RW 10541 */ 10542 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10543 10544 /* reg_mgpc_packet_counter 10545 * Packet counter value. 10546 * Access: RW 10547 */ 10548 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10549 10550 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10551 enum mlxsw_reg_mgpc_opcode opcode, 10552 enum mlxsw_reg_flow_counter_set_type set_type) 10553 { 10554 MLXSW_REG_ZERO(mgpc, payload); 10555 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10556 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10557 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10558 } 10559 10560 /* MPRS - Monitoring Parsing State Register 10561 * ---------------------------------------- 10562 * The MPRS register is used for setting up the parsing for hash, 10563 * policy-engine and routing. 10564 */ 10565 #define MLXSW_REG_MPRS_ID 0x9083 10566 #define MLXSW_REG_MPRS_LEN 0x14 10567 10568 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10569 10570 /* reg_mprs_parsing_depth 10571 * Minimum parsing depth. 10572 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10573 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10574 * Access: RW 10575 */ 10576 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10577 10578 /* reg_mprs_parsing_en 10579 * Parsing enable. 10580 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10581 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10582 * Access: RW 10583 */ 10584 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10585 10586 /* reg_mprs_vxlan_udp_dport 10587 * VxLAN UDP destination port. 10588 * Used for identifying VxLAN packets and for dport field in 10589 * encapsulation. Default is 4789. 10590 * Access: RW 10591 */ 10592 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10593 10594 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10595 u16 vxlan_udp_dport) 10596 { 10597 MLXSW_REG_ZERO(mprs, payload); 10598 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10599 mlxsw_reg_mprs_parsing_en_set(payload, true); 10600 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10601 } 10602 10603 /* MOGCR - Monitoring Global Configuration Register 10604 * ------------------------------------------------ 10605 */ 10606 #define MLXSW_REG_MOGCR_ID 0x9086 10607 #define MLXSW_REG_MOGCR_LEN 0x20 10608 10609 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10610 10611 /* reg_mogcr_ptp_iftc 10612 * PTP Ingress FIFO Trap Clear 10613 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10614 * to this value. Default 0. 10615 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10616 * Access: RW 10617 */ 10618 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10619 10620 /* reg_mogcr_ptp_eftc 10621 * PTP Egress FIFO Trap Clear 10622 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10623 * to this value. Default 0. 10624 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10625 * Access: RW 10626 */ 10627 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10628 10629 /* reg_mogcr_mirroring_pid_base 10630 * Base policer id for mirroring policers. 10631 * Must have an even value (e.g. 1000, not 1001). 10632 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10633 * Access: RW 10634 */ 10635 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10636 10637 /* MPAGR - Monitoring Port Analyzer Global Register 10638 * ------------------------------------------------ 10639 * This register is used for global port analyzer configurations. 10640 * Note: This register is not supported by current FW versions for Spectrum-1. 10641 */ 10642 #define MLXSW_REG_MPAGR_ID 0x9089 10643 #define MLXSW_REG_MPAGR_LEN 0x0C 10644 10645 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10646 10647 enum mlxsw_reg_mpagr_trigger { 10648 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10649 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10650 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10651 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10652 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10653 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10654 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10655 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10656 }; 10657 10658 /* reg_mpagr_trigger 10659 * Mirror trigger. 10660 * Access: Index 10661 */ 10662 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10663 10664 /* reg_mpagr_pa_id 10665 * Port analyzer ID. 10666 * Access: RW 10667 */ 10668 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10669 10670 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10671 10672 /* reg_mpagr_probability_rate 10673 * Sampling rate. 10674 * Valid values are: 1 to 3.5*10^9 10675 * Value of 1 means "sample all". Default is 1. 10676 * Access: RW 10677 */ 10678 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10679 10680 static inline void mlxsw_reg_mpagr_pack(char *payload, 10681 enum mlxsw_reg_mpagr_trigger trigger, 10682 u8 pa_id, u32 probability_rate) 10683 { 10684 MLXSW_REG_ZERO(mpagr, payload); 10685 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10686 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10687 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10688 } 10689 10690 /* MOMTE - Monitoring Mirror Trigger Enable Register 10691 * ------------------------------------------------- 10692 * This register is used to configure the mirror enable for different mirror 10693 * reasons. 10694 */ 10695 #define MLXSW_REG_MOMTE_ID 0x908D 10696 #define MLXSW_REG_MOMTE_LEN 0x10 10697 10698 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10699 10700 /* reg_momte_local_port 10701 * Local port number. 10702 * Access: Index 10703 */ 10704 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10705 10706 enum mlxsw_reg_momte_type { 10707 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10708 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10709 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10710 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10711 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10712 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10713 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10714 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10715 }; 10716 10717 /* reg_momte_type 10718 * Type of mirroring. 10719 * Access: Index 10720 */ 10721 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10722 10723 /* reg_momte_tclass_en 10724 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10725 * 0: disable (default) 10726 * 1: enable 10727 * Access: RW 10728 */ 10729 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10730 10731 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10732 enum mlxsw_reg_momte_type type) 10733 { 10734 MLXSW_REG_ZERO(momte, payload); 10735 mlxsw_reg_momte_local_port_set(payload, local_port); 10736 mlxsw_reg_momte_type_set(payload, type); 10737 } 10738 10739 /* MTPPPC - Time Precision Packet Port Configuration 10740 * ------------------------------------------------- 10741 * This register serves for configuration of which PTP messages should be 10742 * timestamped. This is a global configuration, despite the register name. 10743 * 10744 * Reserved when Spectrum-2. 10745 */ 10746 #define MLXSW_REG_MTPPPC_ID 0x9090 10747 #define MLXSW_REG_MTPPPC_LEN 0x28 10748 10749 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10750 10751 /* reg_mtpppc_ing_timestamp_message_type 10752 * Bitwise vector of PTP message types to timestamp at ingress. 10753 * MessageType field as defined by IEEE 1588 10754 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10755 * Default all 0 10756 * Access: RW 10757 */ 10758 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10759 10760 /* reg_mtpppc_egr_timestamp_message_type 10761 * Bitwise vector of PTP message types to timestamp at egress. 10762 * MessageType field as defined by IEEE 1588 10763 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10764 * Default all 0 10765 * Access: RW 10766 */ 10767 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10768 10769 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10770 { 10771 MLXSW_REG_ZERO(mtpppc, payload); 10772 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10773 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10774 } 10775 10776 /* MTPPTR - Time Precision Packet Timestamping Reading 10777 * --------------------------------------------------- 10778 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10779 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10780 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10781 * trapped. The sequence number is used to synchronize the timestamp FIFO 10782 * entries and the trapped packets. 10783 * Reserved when Spectrum-2. 10784 */ 10785 10786 #define MLXSW_REG_MTPPTR_ID 0x9091 10787 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10788 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10789 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10790 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10791 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10792 10793 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10794 10795 /* reg_mtpptr_local_port 10796 * Not supported for CPU port. 10797 * Access: Index 10798 */ 10799 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10800 10801 enum mlxsw_reg_mtpptr_dir { 10802 MLXSW_REG_MTPPTR_DIR_INGRESS, 10803 MLXSW_REG_MTPPTR_DIR_EGRESS, 10804 }; 10805 10806 /* reg_mtpptr_dir 10807 * Direction. 10808 * Access: Index 10809 */ 10810 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10811 10812 /* reg_mtpptr_clr 10813 * Clear the records. 10814 * Access: OP 10815 */ 10816 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10817 10818 /* reg_mtpptr_num_rec 10819 * Number of valid records in the response 10820 * Range 0.. cap_ptp_timestamp_fifo 10821 * Access: RO 10822 */ 10823 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10824 10825 /* reg_mtpptr_rec_message_type 10826 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10827 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10828 * Access: RO 10829 */ 10830 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10831 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10832 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10833 10834 /* reg_mtpptr_rec_domain_number 10835 * DomainNumber field as defined by IEEE 1588 10836 * Access: RO 10837 */ 10838 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10839 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10840 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10841 10842 /* reg_mtpptr_rec_sequence_id 10843 * SequenceId field as defined by IEEE 1588 10844 * Access: RO 10845 */ 10846 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10847 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10848 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10849 10850 /* reg_mtpptr_rec_timestamp_high 10851 * Timestamp of when the PTP packet has passed through the port Units of PLL 10852 * clock time. 10853 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10854 * Access: RO 10855 */ 10856 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10857 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10858 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10859 10860 /* reg_mtpptr_rec_timestamp_low 10861 * See rec_timestamp_high. 10862 * Access: RO 10863 */ 10864 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10865 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10866 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10867 10868 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10869 unsigned int rec, 10870 u8 *p_message_type, 10871 u8 *p_domain_number, 10872 u16 *p_sequence_id, 10873 u64 *p_timestamp) 10874 { 10875 u32 timestamp_high, timestamp_low; 10876 10877 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10878 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10879 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10880 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10881 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10882 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10883 } 10884 10885 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10886 * --------------------------------------------------------- 10887 * This register is used for configuring under which trap to deliver PTP 10888 * packets depending on type of the packet. 10889 */ 10890 #define MLXSW_REG_MTPTPT_ID 0x9092 10891 #define MLXSW_REG_MTPTPT_LEN 0x08 10892 10893 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10894 10895 enum mlxsw_reg_mtptpt_trap_id { 10896 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10897 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10898 }; 10899 10900 /* reg_mtptpt_trap_id 10901 * Trap id. 10902 * Access: Index 10903 */ 10904 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10905 10906 /* reg_mtptpt_message_type 10907 * Bitwise vector of PTP message types to trap. This is a necessary but 10908 * non-sufficient condition since need to enable also per port. See MTPPPC. 10909 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10910 * Bit0: Sync, Bit1: Delay_Req) 10911 */ 10912 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10913 10914 static inline void mlxsw_reg_mtptpt_pack(char *payload, 10915 enum mlxsw_reg_mtptpt_trap_id trap_id, 10916 u16 message_type) 10917 { 10918 MLXSW_REG_ZERO(mtptpt, payload); 10919 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10920 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10921 } 10922 10923 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 10924 * ------------------------------------------------------------------------- 10925 */ 10926 #define MLXSW_REG_MTPCPC_ID 0x9093 10927 #define MLXSW_REG_MTPCPC_LEN 0x2C 10928 10929 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 10930 10931 /* reg_mtpcpc_pport 10932 * Per port: 10933 * 0: config is global. When reading - the local_port is 1. 10934 * 1: config is per port. 10935 * Access: Index 10936 */ 10937 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 10938 10939 /* reg_mtpcpc_local_port 10940 * Local port number. 10941 * Supported to/from CPU port. 10942 * Reserved when pport = 0. 10943 * Access: Index 10944 */ 10945 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 10946 10947 /* reg_mtpcpc_ptp_trap_en 10948 * Enable PTP traps. 10949 * The trap_id is configured by MTPTPT. 10950 * Access: RW 10951 */ 10952 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 10953 10954 /* reg_mtpcpc_ing_correction_message_type 10955 * Bitwise vector of PTP message types to update correction-field at ingress. 10956 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10957 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 10958 * Default all 0 10959 * Access: RW 10960 */ 10961 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 10962 10963 /* reg_mtpcpc_egr_correction_message_type 10964 * Bitwise vector of PTP message types to update correction-field at egress. 10965 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10966 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 10967 * Default all 0 10968 * Access: RW 10969 */ 10970 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 10971 10972 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 10973 u16 local_port, bool ptp_trap_en, 10974 u16 ing, u16 egr) 10975 { 10976 MLXSW_REG_ZERO(mtpcpc, payload); 10977 mlxsw_reg_mtpcpc_pport_set(payload, pport); 10978 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 10979 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 10980 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 10981 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 10982 } 10983 10984 /* MFGD - Monitoring FW General Debug Register 10985 * ------------------------------------------- 10986 */ 10987 #define MLXSW_REG_MFGD_ID 0x90F0 10988 #define MLXSW_REG_MFGD_LEN 0x0C 10989 10990 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 10991 10992 /* reg_mfgd_fw_fatal_event_mode 10993 * 0 - don't check FW fatal (default) 10994 * 1 - check FW fatal - enable MFDE trap 10995 * Access: RW 10996 */ 10997 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 10998 10999 /* reg_mfgd_trigger_test 11000 * Access: WO 11001 */ 11002 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11003 11004 /* MGPIR - Management General Peripheral Information Register 11005 * ---------------------------------------------------------- 11006 * MGPIR register allows software to query the hardware and 11007 * firmware general information of peripheral entities. 11008 */ 11009 #define MLXSW_REG_MGPIR_ID 0x9100 11010 #define MLXSW_REG_MGPIR_LEN 0xA0 11011 11012 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11013 11014 enum mlxsw_reg_mgpir_device_type { 11015 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11016 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11017 }; 11018 11019 /* mgpir_slot_index 11020 * Slot index (0: Main board). 11021 * Access: Index 11022 */ 11023 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11024 11025 /* mgpir_device_type 11026 * Access: RO 11027 */ 11028 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11029 11030 /* mgpir_devices_per_flash 11031 * Number of devices of device_type per flash (can be shared by few devices). 11032 * Access: RO 11033 */ 11034 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11035 11036 /* mgpir_num_of_devices 11037 * Number of devices of device_type. 11038 * Access: RO 11039 */ 11040 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11041 11042 /* max_modules_per_slot 11043 * Maximum number of modules that can be connected per slot. 11044 * Access: RO 11045 */ 11046 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11047 11048 /* mgpir_num_of_slots 11049 * Number of slots in the system. 11050 * Access: RO 11051 */ 11052 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11053 11054 /* mgpir_num_of_modules 11055 * Number of modules. 11056 * Access: RO 11057 */ 11058 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11059 11060 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11061 { 11062 MLXSW_REG_ZERO(mgpir, payload); 11063 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11064 } 11065 11066 static inline void 11067 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11068 enum mlxsw_reg_mgpir_device_type *device_type, 11069 u8 *devices_per_flash, u8 *num_of_modules, 11070 u8 *num_of_slots) 11071 { 11072 if (num_of_devices) 11073 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11074 if (device_type) 11075 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11076 if (devices_per_flash) 11077 *devices_per_flash = 11078 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11079 if (num_of_modules) 11080 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11081 if (num_of_slots) 11082 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11083 } 11084 11085 /* MBCT - Management Binary Code Transfer Register 11086 * ----------------------------------------------- 11087 * This register allows to transfer binary codes from the host to 11088 * the management FW by transferring it by chunks of maximum 1KB. 11089 */ 11090 #define MLXSW_REG_MBCT_ID 0x9120 11091 #define MLXSW_REG_MBCT_LEN 0x420 11092 11093 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11094 11095 /* reg_mbct_slot_index 11096 * Slot index. 0 is reserved. 11097 * Access: Index 11098 */ 11099 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11100 11101 /* reg_mbct_data_size 11102 * Actual data field size in bytes for the current data transfer. 11103 * Access: WO 11104 */ 11105 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11106 11107 enum mlxsw_reg_mbct_op { 11108 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11109 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11110 MLXSW_REG_MBCT_OP_ACTIVATE, 11111 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11112 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11113 }; 11114 11115 /* reg_mbct_op 11116 * Access: WO 11117 */ 11118 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11119 11120 /* reg_mbct_last 11121 * Indicates that the current data field is the last chunk of the INI. 11122 * Access: WO 11123 */ 11124 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11125 11126 /* reg_mbct_oee 11127 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11128 * was executed and the fsm_state has changed. 11129 * Access: WO 11130 */ 11131 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11132 11133 enum mlxsw_reg_mbct_status { 11134 /* Partial data transfer completed successfully and ready for next 11135 * data transfer. 11136 */ 11137 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11138 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11139 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11140 /* Error - trying to erase INI while it being used. */ 11141 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11142 /* Last data transfer completed, applying magic pattern. */ 11143 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11144 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11145 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11146 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11147 }; 11148 11149 /* reg_mbct_status 11150 * Status. 11151 * Access: RO 11152 */ 11153 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11154 11155 enum mlxsw_reg_mbct_fsm_state { 11156 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11157 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11158 }; 11159 11160 /* reg_mbct_fsm_state 11161 * FSM state. 11162 * Access: RO 11163 */ 11164 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11165 11166 #define MLXSW_REG_MBCT_DATA_LEN 1024 11167 11168 /* reg_mbct_data 11169 * Up to 1KB of data. 11170 * Access: WO 11171 */ 11172 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11173 11174 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11175 enum mlxsw_reg_mbct_op op, bool oee) 11176 { 11177 MLXSW_REG_ZERO(mbct, payload); 11178 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11179 mlxsw_reg_mbct_op_set(payload, op); 11180 mlxsw_reg_mbct_oee_set(payload, oee); 11181 } 11182 11183 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11184 u16 data_size, bool last, 11185 const char *data) 11186 { 11187 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11188 return; 11189 mlxsw_reg_mbct_data_size_set(payload, data_size); 11190 mlxsw_reg_mbct_last_set(payload, last); 11191 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11192 } 11193 11194 static inline void 11195 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11196 enum mlxsw_reg_mbct_status *p_status, 11197 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11198 { 11199 if (p_slot_index) 11200 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11201 *p_status = mlxsw_reg_mbct_status_get(payload); 11202 if (p_fsm_state) 11203 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11204 } 11205 11206 /* MDDT - Management DownStream Device Tunneling Register 11207 * ------------------------------------------------------ 11208 * This register allows to deliver query and request messages (PRM registers, 11209 * commands) to a DownStream device. 11210 */ 11211 #define MLXSW_REG_MDDT_ID 0x9160 11212 #define MLXSW_REG_MDDT_LEN 0x110 11213 11214 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11215 11216 /* reg_mddt_slot_index 11217 * Slot index. 11218 * Access: Index 11219 */ 11220 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11221 11222 /* reg_mddt_device_index 11223 * Device index. 11224 * Access: Index 11225 */ 11226 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11227 11228 /* reg_mddt_read_size 11229 * Read size in D-Words. 11230 * Access: OP 11231 */ 11232 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11233 11234 /* reg_mddt_write_size 11235 * Write size in D-Words. 11236 * Access: OP 11237 */ 11238 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11239 11240 enum mlxsw_reg_mddt_status { 11241 MLXSW_REG_MDDT_STATUS_OK, 11242 }; 11243 11244 /* reg_mddt_status 11245 * Return code of the Downstream Device to the register that was sent. 11246 * Access: RO 11247 */ 11248 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11249 11250 enum mlxsw_reg_mddt_method { 11251 MLXSW_REG_MDDT_METHOD_QUERY, 11252 MLXSW_REG_MDDT_METHOD_WRITE, 11253 }; 11254 11255 /* reg_mddt_method 11256 * Access: OP 11257 */ 11258 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11259 11260 /* reg_mddt_register_id 11261 * Access: Index 11262 */ 11263 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11264 11265 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11266 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11267 11268 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11269 { 11270 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11271 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11272 } 11273 11274 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11275 u8 device_index, 11276 enum mlxsw_reg_mddt_method method, 11277 const struct mlxsw_reg_info *reg, 11278 char **inner_payload) 11279 { 11280 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11281 11282 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11283 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11284 11285 MLXSW_REG_ZERO(mddt, payload); 11286 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11287 mlxsw_reg_mddt_device_index_set(payload, device_index); 11288 mlxsw_reg_mddt_method_set(payload, method); 11289 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11290 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11291 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11292 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11293 } 11294 11295 /* MDDQ - Management DownStream Device Query Register 11296 * -------------------------------------------------- 11297 * This register allows to query the DownStream device properties. The desired 11298 * information is chosen upon the query_type field and is delivered by 32B 11299 * of data blocks. 11300 */ 11301 #define MLXSW_REG_MDDQ_ID 0x9161 11302 #define MLXSW_REG_MDDQ_LEN 0x30 11303 11304 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11305 11306 /* reg_mddq_sie 11307 * Slot info event enable. 11308 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11309 * active / ready will generate a DSDSC event. 11310 * Access: RW 11311 */ 11312 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11313 11314 enum mlxsw_reg_mddq_query_type { 11315 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11316 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11317 * on the slot, data_valid 11318 * will be '0'. 11319 */ 11320 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11321 }; 11322 11323 /* reg_mddq_query_type 11324 * Access: Index 11325 */ 11326 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11327 11328 /* reg_mddq_slot_index 11329 * Slot index. 0 is reserved. 11330 * Access: Index 11331 */ 11332 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11333 11334 /* reg_mddq_response_msg_seq 11335 * Response message sequential number. For a specific request, the response 11336 * message sequential number is the following one. In addition, the last 11337 * message should be 0. 11338 * Access: RO 11339 */ 11340 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11341 11342 /* reg_mddq_request_msg_seq 11343 * Request message sequential number. 11344 * The first message number should be 0. 11345 * Access: Index 11346 */ 11347 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11348 11349 /* reg_mddq_data_valid 11350 * If set, the data in the data field is valid and contain the information 11351 * for the queried index. 11352 * Access: RO 11353 */ 11354 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11355 11356 /* reg_mddq_slot_info_provisioned 11357 * If set, the INI file is applied and the card is provisioned. 11358 * Access: RO 11359 */ 11360 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11361 11362 /* reg_mddq_slot_info_sr_valid 11363 * If set, Shift Register is valid (after being provisioned) and data 11364 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11365 * Access: RO 11366 */ 11367 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11368 11369 enum mlxsw_reg_mddq_slot_info_ready { 11370 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11371 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11372 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11373 }; 11374 11375 /* reg_mddq_slot_info_lc_ready 11376 * If set, the LC is powered on, matching the INI version and a new FW 11377 * version can be burnt (if necessary). 11378 * Access: RO 11379 */ 11380 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11381 11382 /* reg_mddq_slot_info_active 11383 * If set, the FW has completed the MDDC.device_enable command. 11384 * Access: RO 11385 */ 11386 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11387 11388 /* reg_mddq_slot_info_hw_revision 11389 * Major user-configured version number of the current INI file. 11390 * Valid only when active or ready are '1'. 11391 * Access: RO 11392 */ 11393 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11394 11395 /* reg_mddq_slot_info_ini_file_version 11396 * User-configured version number of the current INI file. 11397 * Valid only when active or lc_ready are '1'. 11398 * Access: RO 11399 */ 11400 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11401 11402 /* reg_mddq_slot_info_card_type 11403 * Access: RO 11404 */ 11405 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11406 11407 static inline void 11408 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11409 enum mlxsw_reg_mddq_query_type query_type) 11410 { 11411 MLXSW_REG_ZERO(mddq, payload); 11412 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11413 mlxsw_reg_mddq_query_type_set(payload, query_type); 11414 } 11415 11416 static inline void 11417 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11418 { 11419 __mlxsw_reg_mddq_pack(payload, slot_index, 11420 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11421 mlxsw_reg_mddq_sie_set(payload, sie); 11422 } 11423 11424 static inline void 11425 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11426 bool *p_provisioned, bool *p_sr_valid, 11427 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11428 bool *p_active, u16 *p_hw_revision, 11429 u16 *p_ini_file_version, 11430 u8 *p_card_type) 11431 { 11432 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11433 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11434 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11435 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11436 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11437 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11438 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11439 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11440 } 11441 11442 /* reg_mddq_device_info_flash_owner 11443 * If set, the device is the flash owner. Otherwise, a shared flash 11444 * is used by this device (another device is the flash owner). 11445 * Access: RO 11446 */ 11447 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11448 11449 /* reg_mddq_device_info_device_index 11450 * Device index. The first device should number 0. 11451 * Access: RO 11452 */ 11453 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11454 11455 /* reg_mddq_device_info_fw_major 11456 * Major FW version number. 11457 * Access: RO 11458 */ 11459 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11460 11461 /* reg_mddq_device_info_fw_minor 11462 * Minor FW version number. 11463 * Access: RO 11464 */ 11465 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11466 11467 /* reg_mddq_device_info_fw_sub_minor 11468 * Sub-minor FW version number. 11469 * Access: RO 11470 */ 11471 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11472 11473 static inline void 11474 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11475 u8 request_msg_seq) 11476 { 11477 __mlxsw_reg_mddq_pack(payload, slot_index, 11478 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11479 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11480 } 11481 11482 static inline void 11483 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11484 bool *p_data_valid, bool *p_flash_owner, 11485 u8 *p_device_index, u16 *p_fw_major, 11486 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11487 { 11488 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11489 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11490 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11491 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11492 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11493 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11494 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11495 } 11496 11497 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11498 11499 /* reg_mddq_slot_ascii_name 11500 * Slot's ASCII name. 11501 * Access: RO 11502 */ 11503 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11504 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11505 11506 static inline void 11507 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11508 { 11509 __mlxsw_reg_mddq_pack(payload, slot_index, 11510 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11511 } 11512 11513 static inline void 11514 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11515 { 11516 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11517 } 11518 11519 /* MDDC - Management DownStream Device Control Register 11520 * ---------------------------------------------------- 11521 * This register allows to control downstream devices and line cards. 11522 */ 11523 #define MLXSW_REG_MDDC_ID 0x9163 11524 #define MLXSW_REG_MDDC_LEN 0x30 11525 11526 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11527 11528 /* reg_mddc_slot_index 11529 * Slot index. 0 is reserved. 11530 * Access: Index 11531 */ 11532 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11533 11534 /* reg_mddc_rst 11535 * Reset request. 11536 * Access: OP 11537 */ 11538 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11539 11540 /* reg_mddc_device_enable 11541 * When set, FW is the manager and allowed to program the downstream device. 11542 * Access: RW 11543 */ 11544 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11545 11546 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11547 bool device_enable) 11548 { 11549 MLXSW_REG_ZERO(mddc, payload); 11550 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11551 mlxsw_reg_mddc_rst_set(payload, rst); 11552 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11553 } 11554 11555 /* MFDE - Monitoring FW Debug Register 11556 * ----------------------------------- 11557 */ 11558 #define MLXSW_REG_MFDE_ID 0x9200 11559 #define MLXSW_REG_MFDE_LEN 0x30 11560 11561 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11562 11563 /* reg_mfde_irisc_id 11564 * Which irisc triggered the event 11565 * Access: RO 11566 */ 11567 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11568 11569 enum mlxsw_reg_mfde_severity { 11570 /* Unrecoverable switch behavior */ 11571 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11572 /* Unexpected state with possible systemic failure */ 11573 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11574 /* Unexpected state without systemic failure */ 11575 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11576 }; 11577 11578 /* reg_mfde_severity 11579 * The severity of the event. 11580 * Access: RO 11581 */ 11582 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11583 11584 enum mlxsw_reg_mfde_event_id { 11585 /* CRspace timeout */ 11586 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11587 /* KVD insertion machine stopped */ 11588 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11589 /* Triggered by MFGD.trigger_test */ 11590 MLXSW_REG_MFDE_EVENT_ID_TEST, 11591 /* Triggered when firmware hits an assert */ 11592 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11593 /* Fatal error interrupt from hardware */ 11594 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11595 }; 11596 11597 /* reg_mfde_event_id 11598 * Access: RO 11599 */ 11600 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11601 11602 enum mlxsw_reg_mfde_method { 11603 MLXSW_REG_MFDE_METHOD_QUERY, 11604 MLXSW_REG_MFDE_METHOD_WRITE, 11605 }; 11606 11607 /* reg_mfde_method 11608 * Access: RO 11609 */ 11610 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11611 11612 /* reg_mfde_long_process 11613 * Indicates if the command is in long_process mode. 11614 * Access: RO 11615 */ 11616 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11617 11618 enum mlxsw_reg_mfde_command_type { 11619 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11620 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11621 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11622 }; 11623 11624 /* reg_mfde_command_type 11625 * Access: RO 11626 */ 11627 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11628 11629 /* reg_mfde_reg_attr_id 11630 * EMAD - register id, MAD - attibute id 11631 * Access: RO 11632 */ 11633 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11634 11635 /* reg_mfde_crspace_to_log_address 11636 * crspace address accessed, which resulted in timeout. 11637 * Access: RO 11638 */ 11639 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11640 11641 /* reg_mfde_crspace_to_oe 11642 * 0 - New event 11643 * 1 - Old event, occurred before MFGD activation. 11644 * Access: RO 11645 */ 11646 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11647 11648 /* reg_mfde_crspace_to_log_id 11649 * Which irisc triggered the timeout. 11650 * Access: RO 11651 */ 11652 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11653 11654 /* reg_mfde_crspace_to_log_ip 11655 * IP (instruction pointer) that triggered the timeout. 11656 * Access: RO 11657 */ 11658 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11659 11660 /* reg_mfde_kvd_im_stop_oe 11661 * 0 - New event 11662 * 1 - Old event, occurred before MFGD activation. 11663 * Access: RO 11664 */ 11665 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11666 11667 /* reg_mfde_kvd_im_stop_pipes_mask 11668 * Bit per kvh pipe. 11669 * Access: RO 11670 */ 11671 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11672 11673 /* reg_mfde_fw_assert_var0-4 11674 * Variables passed to assert. 11675 * Access: RO 11676 */ 11677 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11678 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11679 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11680 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11681 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11682 11683 /* reg_mfde_fw_assert_existptr 11684 * The instruction pointer when assert was triggered. 11685 * Access: RO 11686 */ 11687 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11688 11689 /* reg_mfde_fw_assert_callra 11690 * The return address after triggering assert. 11691 * Access: RO 11692 */ 11693 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11694 11695 /* reg_mfde_fw_assert_oe 11696 * 0 - New event 11697 * 1 - Old event, occurred before MFGD activation. 11698 * Access: RO 11699 */ 11700 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11701 11702 /* reg_mfde_fw_assert_tile_v 11703 * 0: The assert was from main 11704 * 1: The assert was from a tile 11705 * Access: RO 11706 */ 11707 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11708 11709 /* reg_mfde_fw_assert_tile_index 11710 * When tile_v=1, the tile_index that caused the assert. 11711 * Access: RO 11712 */ 11713 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11714 11715 /* reg_mfde_fw_assert_ext_synd 11716 * A generated one-to-one identifier which is specific per-assert. 11717 * Access: RO 11718 */ 11719 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11720 11721 /* reg_mfde_fatal_cause_id 11722 * HW interrupt cause id. 11723 * Access: RO 11724 */ 11725 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11726 11727 /* reg_mfde_fatal_cause_tile_v 11728 * 0: The assert was from main 11729 * 1: The assert was from a tile 11730 * Access: RO 11731 */ 11732 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11733 11734 /* reg_mfde_fatal_cause_tile_index 11735 * When tile_v=1, the tile_index that caused the assert. 11736 * Access: RO 11737 */ 11738 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11739 11740 /* TNGCR - Tunneling NVE General Configuration Register 11741 * ---------------------------------------------------- 11742 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11743 */ 11744 #define MLXSW_REG_TNGCR_ID 0xA001 11745 #define MLXSW_REG_TNGCR_LEN 0x44 11746 11747 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11748 11749 enum mlxsw_reg_tngcr_type { 11750 MLXSW_REG_TNGCR_TYPE_VXLAN, 11751 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11752 MLXSW_REG_TNGCR_TYPE_GENEVE, 11753 MLXSW_REG_TNGCR_TYPE_NVGRE, 11754 }; 11755 11756 /* reg_tngcr_type 11757 * Tunnel type for encapsulation and decapsulation. The types are mutually 11758 * exclusive. 11759 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11760 * Access: RW 11761 */ 11762 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11763 11764 /* reg_tngcr_nve_valid 11765 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11766 * Access: RW 11767 */ 11768 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11769 11770 /* reg_tngcr_nve_ttl_uc 11771 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11772 * Access: RW 11773 */ 11774 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11775 11776 /* reg_tngcr_nve_ttl_mc 11777 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11778 * Access: RW 11779 */ 11780 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11781 11782 enum { 11783 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11784 MLXSW_REG_TNGCR_FL_NO_COPY, 11785 /* Copy flow label from inner packet if packet is IPv6 and 11786 * encapsulation is by IPv6. Otherwise, calculate flow label using 11787 * nve_flh. 11788 */ 11789 MLXSW_REG_TNGCR_FL_COPY, 11790 }; 11791 11792 /* reg_tngcr_nve_flc 11793 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11794 * Access: RW 11795 */ 11796 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11797 11798 enum { 11799 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11800 * uses {nve_fl_prefix, nve_fl_suffix}. 11801 */ 11802 MLXSW_REG_TNGCR_FL_NO_HASH, 11803 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11804 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11805 */ 11806 MLXSW_REG_TNGCR_FL_HASH, 11807 }; 11808 11809 /* reg_tngcr_nve_flh 11810 * NVE flow label hash. 11811 * Access: RW 11812 */ 11813 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11814 11815 /* reg_tngcr_nve_fl_prefix 11816 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11817 * Access: RW 11818 */ 11819 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11820 11821 /* reg_tngcr_nve_fl_suffix 11822 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11823 * Reserved when nve_flh=1 and for Spectrum. 11824 * Access: RW 11825 */ 11826 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11827 11828 enum { 11829 /* Source UDP port is fixed (default '0') */ 11830 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11831 /* Source UDP port is calculated based on hash */ 11832 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11833 }; 11834 11835 /* reg_tngcr_nve_udp_sport_type 11836 * NVE UDP source port type. 11837 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11838 * When the source UDP port is calculated based on hash, then the 8 LSBs 11839 * are calculated from hash the 8 MSBs are configured by 11840 * nve_udp_sport_prefix. 11841 * Access: RW 11842 */ 11843 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11844 11845 /* reg_tngcr_nve_udp_sport_prefix 11846 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11847 * Reserved when NVE type is NVGRE. 11848 * Access: RW 11849 */ 11850 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11851 11852 /* reg_tngcr_nve_group_size_mc 11853 * The amount of sequential linked lists of MC entries. The first linked 11854 * list is configured by SFD.underlay_mc_ptr. 11855 * Valid values: 1, 2, 4, 8, 16, 32, 64 11856 * The linked list are configured by TNUMT. 11857 * The hash is set by LAG hash. 11858 * Access: RW 11859 */ 11860 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11861 11862 /* reg_tngcr_nve_group_size_flood 11863 * The amount of sequential linked lists of flooding entries. The first 11864 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11865 * Valid values: 1, 2, 4, 8, 16, 32, 64 11866 * The linked list are configured by TNUMT. 11867 * The hash is set by LAG hash. 11868 * Access: RW 11869 */ 11870 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11871 11872 /* reg_tngcr_learn_enable 11873 * During decapsulation, whether to learn from NVE port. 11874 * Reserved when Spectrum-2. See TNPC. 11875 * Access: RW 11876 */ 11877 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11878 11879 /* reg_tngcr_underlay_virtual_router 11880 * Underlay virtual router. 11881 * Reserved when Spectrum-2. 11882 * Access: RW 11883 */ 11884 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11885 11886 /* reg_tngcr_underlay_rif 11887 * Underlay ingress router interface. RIF type should be loopback generic. 11888 * Reserved when Spectrum. 11889 * Access: RW 11890 */ 11891 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11892 11893 /* reg_tngcr_usipv4 11894 * Underlay source IPv4 address of the NVE. 11895 * Access: RW 11896 */ 11897 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11898 11899 /* reg_tngcr_usipv6 11900 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11901 * modified under traffic of NVE tunneling encapsulation. 11902 * Access: RW 11903 */ 11904 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11905 11906 static inline void mlxsw_reg_tngcr_pack(char *payload, 11907 enum mlxsw_reg_tngcr_type type, 11908 bool valid, u8 ttl) 11909 { 11910 MLXSW_REG_ZERO(tngcr, payload); 11911 mlxsw_reg_tngcr_type_set(payload, type); 11912 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11913 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11914 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11915 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11916 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11917 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11918 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11919 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11920 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11921 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11922 } 11923 11924 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11925 * ------------------------------------------------------- 11926 * The TNUMT register is for building the underlay MC table. It is used 11927 * for MC, flooding and BC traffic into the NVE tunnel. 11928 */ 11929 #define MLXSW_REG_TNUMT_ID 0xA003 11930 #define MLXSW_REG_TNUMT_LEN 0x20 11931 11932 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11933 11934 enum mlxsw_reg_tnumt_record_type { 11935 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11936 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11937 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11938 }; 11939 11940 /* reg_tnumt_record_type 11941 * Record type. 11942 * Access: RW 11943 */ 11944 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11945 11946 /* reg_tnumt_tunnel_port 11947 * Tunnel port. 11948 * Access: RW 11949 */ 11950 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11951 11952 /* reg_tnumt_underlay_mc_ptr 11953 * Index to the underlay multicast table. 11954 * For Spectrum the index is to the KVD linear. 11955 * Access: Index 11956 */ 11957 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11958 11959 /* reg_tnumt_vnext 11960 * The next_underlay_mc_ptr is valid. 11961 * Access: RW 11962 */ 11963 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11964 11965 /* reg_tnumt_next_underlay_mc_ptr 11966 * The next index to the underlay multicast table. 11967 * Access: RW 11968 */ 11969 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11970 11971 /* reg_tnumt_record_size 11972 * Number of IP addresses in the record. 11973 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11974 * Access: RW 11975 */ 11976 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11977 11978 /* reg_tnumt_udip 11979 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11980 * Access: RW 11981 */ 11982 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11983 11984 /* reg_tnumt_udip_ptr 11985 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11986 * i >= size. The IPv6 addresses are configured by RIPS. 11987 * Access: RW 11988 */ 11989 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11990 11991 static inline void mlxsw_reg_tnumt_pack(char *payload, 11992 enum mlxsw_reg_tnumt_record_type type, 11993 enum mlxsw_reg_tunnel_port tport, 11994 u32 underlay_mc_ptr, bool vnext, 11995 u32 next_underlay_mc_ptr, 11996 u8 record_size) 11997 { 11998 MLXSW_REG_ZERO(tnumt, payload); 11999 mlxsw_reg_tnumt_record_type_set(payload, type); 12000 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12001 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12002 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12003 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12004 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12005 } 12006 12007 /* TNQCR - Tunneling NVE QoS Configuration Register 12008 * ------------------------------------------------ 12009 * The TNQCR register configures how QoS is set in encapsulation into the 12010 * underlay network. 12011 */ 12012 #define MLXSW_REG_TNQCR_ID 0xA010 12013 #define MLXSW_REG_TNQCR_LEN 0x0C 12014 12015 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12016 12017 /* reg_tnqcr_enc_set_dscp 12018 * For encapsulation: How to set DSCP field: 12019 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12020 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12021 * 1 - Set the DSCP field as TNQDR.dscp 12022 * Access: RW 12023 */ 12024 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12025 12026 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12027 { 12028 MLXSW_REG_ZERO(tnqcr, payload); 12029 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12030 } 12031 12032 /* TNQDR - Tunneling NVE QoS Default Register 12033 * ------------------------------------------ 12034 * The TNQDR register configures the default QoS settings for NVE 12035 * encapsulation. 12036 */ 12037 #define MLXSW_REG_TNQDR_ID 0xA011 12038 #define MLXSW_REG_TNQDR_LEN 0x08 12039 12040 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12041 12042 /* reg_tnqdr_local_port 12043 * Local port number (receive port). CPU port is supported. 12044 * Access: Index 12045 */ 12046 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12047 12048 /* reg_tnqdr_dscp 12049 * For encapsulation, the default DSCP. 12050 * Access: RW 12051 */ 12052 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12053 12054 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12055 { 12056 MLXSW_REG_ZERO(tnqdr, payload); 12057 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12058 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12059 } 12060 12061 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12062 * -------------------------------------------------------- 12063 * The TNEEM register maps ECN of the IP header at the ingress to the 12064 * encapsulation to the ECN of the underlay network. 12065 */ 12066 #define MLXSW_REG_TNEEM_ID 0xA012 12067 #define MLXSW_REG_TNEEM_LEN 0x0C 12068 12069 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12070 12071 /* reg_tneem_overlay_ecn 12072 * ECN of the IP header in the overlay network. 12073 * Access: Index 12074 */ 12075 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12076 12077 /* reg_tneem_underlay_ecn 12078 * ECN of the IP header in the underlay network. 12079 * Access: RW 12080 */ 12081 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12082 12083 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12084 u8 underlay_ecn) 12085 { 12086 MLXSW_REG_ZERO(tneem, payload); 12087 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12088 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12089 } 12090 12091 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12092 * -------------------------------------------------------- 12093 * The TNDEM register configures the actions that are done in the 12094 * decapsulation. 12095 */ 12096 #define MLXSW_REG_TNDEM_ID 0xA013 12097 #define MLXSW_REG_TNDEM_LEN 0x0C 12098 12099 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12100 12101 /* reg_tndem_underlay_ecn 12102 * ECN field of the IP header in the underlay network. 12103 * Access: Index 12104 */ 12105 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12106 12107 /* reg_tndem_overlay_ecn 12108 * ECN field of the IP header in the overlay network. 12109 * Access: Index 12110 */ 12111 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12112 12113 /* reg_tndem_eip_ecn 12114 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12115 * from the decapsulation. 12116 * Access: RW 12117 */ 12118 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12119 12120 /* reg_tndem_trap_en 12121 * Trap enable: 12122 * 0 - No trap due to decap ECN 12123 * 1 - Trap enable with trap_id 12124 * Access: RW 12125 */ 12126 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12127 12128 /* reg_tndem_trap_id 12129 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12130 * Reserved when trap_en is '0'. 12131 * Access: RW 12132 */ 12133 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12134 12135 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12136 u8 overlay_ecn, u8 ecn, bool trap_en, 12137 u16 trap_id) 12138 { 12139 MLXSW_REG_ZERO(tndem, payload); 12140 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12141 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12142 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12143 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12144 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12145 } 12146 12147 /* TNPC - Tunnel Port Configuration Register 12148 * ----------------------------------------- 12149 * The TNPC register is used for tunnel port configuration. 12150 * Reserved when Spectrum. 12151 */ 12152 #define MLXSW_REG_TNPC_ID 0xA020 12153 #define MLXSW_REG_TNPC_LEN 0x18 12154 12155 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12156 12157 /* reg_tnpc_tunnel_port 12158 * Tunnel port. 12159 * Access: Index 12160 */ 12161 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12162 12163 /* reg_tnpc_learn_enable_v6 12164 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12165 * Access: RW 12166 */ 12167 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12168 12169 /* reg_tnpc_learn_enable_v4 12170 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12171 * Access: RW 12172 */ 12173 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12174 12175 static inline void mlxsw_reg_tnpc_pack(char *payload, 12176 enum mlxsw_reg_tunnel_port tport, 12177 bool learn_enable) 12178 { 12179 MLXSW_REG_ZERO(tnpc, payload); 12180 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12181 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12182 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12183 } 12184 12185 /* TIGCR - Tunneling IPinIP General Configuration Register 12186 * ------------------------------------------------------- 12187 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12188 */ 12189 #define MLXSW_REG_TIGCR_ID 0xA801 12190 #define MLXSW_REG_TIGCR_LEN 0x10 12191 12192 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12193 12194 /* reg_tigcr_ipip_ttlc 12195 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12196 * header. 12197 * Access: RW 12198 */ 12199 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12200 12201 /* reg_tigcr_ipip_ttl_uc 12202 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12203 * reg_tigcr_ipip_ttlc is unset. 12204 * Access: RW 12205 */ 12206 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12207 12208 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12209 { 12210 MLXSW_REG_ZERO(tigcr, payload); 12211 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12212 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12213 } 12214 12215 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12216 * ----------------------------------------------------------- 12217 * The TIEEM register maps ECN of the IP header at the ingress to the 12218 * encapsulation to the ECN of the underlay network. 12219 */ 12220 #define MLXSW_REG_TIEEM_ID 0xA812 12221 #define MLXSW_REG_TIEEM_LEN 0x0C 12222 12223 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12224 12225 /* reg_tieem_overlay_ecn 12226 * ECN of the IP header in the overlay network. 12227 * Access: Index 12228 */ 12229 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12230 12231 /* reg_tineem_underlay_ecn 12232 * ECN of the IP header in the underlay network. 12233 * Access: RW 12234 */ 12235 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12236 12237 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12238 u8 underlay_ecn) 12239 { 12240 MLXSW_REG_ZERO(tieem, payload); 12241 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12242 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12243 } 12244 12245 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12246 * ----------------------------------------------------------- 12247 * The TIDEM register configures the actions that are done in the 12248 * decapsulation. 12249 */ 12250 #define MLXSW_REG_TIDEM_ID 0xA813 12251 #define MLXSW_REG_TIDEM_LEN 0x0C 12252 12253 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12254 12255 /* reg_tidem_underlay_ecn 12256 * ECN field of the IP header in the underlay network. 12257 * Access: Index 12258 */ 12259 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12260 12261 /* reg_tidem_overlay_ecn 12262 * ECN field of the IP header in the overlay network. 12263 * Access: Index 12264 */ 12265 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12266 12267 /* reg_tidem_eip_ecn 12268 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12269 * from the decapsulation. 12270 * Access: RW 12271 */ 12272 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12273 12274 /* reg_tidem_trap_en 12275 * Trap enable: 12276 * 0 - No trap due to decap ECN 12277 * 1 - Trap enable with trap_id 12278 * Access: RW 12279 */ 12280 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12281 12282 /* reg_tidem_trap_id 12283 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12284 * Reserved when trap_en is '0'. 12285 * Access: RW 12286 */ 12287 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12288 12289 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12290 u8 overlay_ecn, u8 eip_ecn, 12291 bool trap_en, u16 trap_id) 12292 { 12293 MLXSW_REG_ZERO(tidem, payload); 12294 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12295 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12296 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12297 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12298 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12299 } 12300 12301 /* SBPR - Shared Buffer Pools Register 12302 * ----------------------------------- 12303 * The SBPR configures and retrieves the shared buffer pools and configuration. 12304 */ 12305 #define MLXSW_REG_SBPR_ID 0xB001 12306 #define MLXSW_REG_SBPR_LEN 0x14 12307 12308 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12309 12310 /* reg_sbpr_desc 12311 * When set, configures descriptor buffer. 12312 * Access: Index 12313 */ 12314 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12315 12316 /* shared direstion enum for SBPR, SBCM, SBPM */ 12317 enum mlxsw_reg_sbxx_dir { 12318 MLXSW_REG_SBXX_DIR_INGRESS, 12319 MLXSW_REG_SBXX_DIR_EGRESS, 12320 }; 12321 12322 /* reg_sbpr_dir 12323 * Direction. 12324 * Access: Index 12325 */ 12326 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12327 12328 /* reg_sbpr_pool 12329 * Pool index. 12330 * Access: Index 12331 */ 12332 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12333 12334 /* reg_sbpr_infi_size 12335 * Size is infinite. 12336 * Access: RW 12337 */ 12338 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12339 12340 /* reg_sbpr_size 12341 * Pool size in buffer cells. 12342 * Reserved when infi_size = 1. 12343 * Access: RW 12344 */ 12345 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12346 12347 enum mlxsw_reg_sbpr_mode { 12348 MLXSW_REG_SBPR_MODE_STATIC, 12349 MLXSW_REG_SBPR_MODE_DYNAMIC, 12350 }; 12351 12352 /* reg_sbpr_mode 12353 * Pool quota calculation mode. 12354 * Access: RW 12355 */ 12356 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12357 12358 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12359 enum mlxsw_reg_sbxx_dir dir, 12360 enum mlxsw_reg_sbpr_mode mode, u32 size, 12361 bool infi_size) 12362 { 12363 MLXSW_REG_ZERO(sbpr, payload); 12364 mlxsw_reg_sbpr_pool_set(payload, pool); 12365 mlxsw_reg_sbpr_dir_set(payload, dir); 12366 mlxsw_reg_sbpr_mode_set(payload, mode); 12367 mlxsw_reg_sbpr_size_set(payload, size); 12368 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12369 } 12370 12371 /* SBCM - Shared Buffer Class Management Register 12372 * ---------------------------------------------- 12373 * The SBCM register configures and retrieves the shared buffer allocation 12374 * and configuration according to Port-PG, including the binding to pool 12375 * and definition of the associated quota. 12376 */ 12377 #define MLXSW_REG_SBCM_ID 0xB002 12378 #define MLXSW_REG_SBCM_LEN 0x28 12379 12380 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12381 12382 /* reg_sbcm_local_port 12383 * Local port number. 12384 * For Ingress: excludes CPU port and Router port 12385 * For Egress: excludes IP Router 12386 * Access: Index 12387 */ 12388 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12389 12390 /* reg_sbcm_pg_buff 12391 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12392 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12393 * For traffic class: range is 0..cap_max_tclass - 1 12394 * Note that when traffic class is in MC aware mode then the traffic 12395 * classes which are MC aware cannot be configured. 12396 * Access: Index 12397 */ 12398 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12399 12400 /* reg_sbcm_dir 12401 * Direction. 12402 * Access: Index 12403 */ 12404 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12405 12406 /* reg_sbcm_min_buff 12407 * Minimum buffer size for the limiter, in cells. 12408 * Access: RW 12409 */ 12410 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12411 12412 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12413 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12414 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12415 12416 /* reg_sbcm_infi_max 12417 * Max buffer is infinite. 12418 * Access: RW 12419 */ 12420 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12421 12422 /* reg_sbcm_max_buff 12423 * When the pool associated to the port-pg/tclass is configured to 12424 * static, Maximum buffer size for the limiter configured in cells. 12425 * When the pool associated to the port-pg/tclass is configured to 12426 * dynamic, the max_buff holds the "alpha" parameter, supporting 12427 * the following values: 12428 * 0: 0 12429 * i: (1/128)*2^(i-1), for i=1..14 12430 * 0xFF: Infinity 12431 * Reserved when infi_max = 1. 12432 * Access: RW 12433 */ 12434 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12435 12436 /* reg_sbcm_pool 12437 * Association of the port-priority to a pool. 12438 * Access: RW 12439 */ 12440 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12441 12442 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12443 enum mlxsw_reg_sbxx_dir dir, 12444 u32 min_buff, u32 max_buff, 12445 bool infi_max, u8 pool) 12446 { 12447 MLXSW_REG_ZERO(sbcm, payload); 12448 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12449 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12450 mlxsw_reg_sbcm_dir_set(payload, dir); 12451 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12452 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12453 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12454 mlxsw_reg_sbcm_pool_set(payload, pool); 12455 } 12456 12457 /* SBPM - Shared Buffer Port Management Register 12458 * --------------------------------------------- 12459 * The SBPM register configures and retrieves the shared buffer allocation 12460 * and configuration according to Port-Pool, including the definition 12461 * of the associated quota. 12462 */ 12463 #define MLXSW_REG_SBPM_ID 0xB003 12464 #define MLXSW_REG_SBPM_LEN 0x28 12465 12466 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12467 12468 /* reg_sbpm_local_port 12469 * Local port number. 12470 * For Ingress: excludes CPU port and Router port 12471 * For Egress: excludes IP Router 12472 * Access: Index 12473 */ 12474 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12475 12476 /* reg_sbpm_pool 12477 * The pool associated to quota counting on the local_port. 12478 * Access: Index 12479 */ 12480 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12481 12482 /* reg_sbpm_dir 12483 * Direction. 12484 * Access: Index 12485 */ 12486 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12487 12488 /* reg_sbpm_buff_occupancy 12489 * Current buffer occupancy in cells. 12490 * Access: RO 12491 */ 12492 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12493 12494 /* reg_sbpm_clr 12495 * Clear Max Buffer Occupancy 12496 * When this bit is set, max_buff_occupancy field is cleared (and a 12497 * new max value is tracked from the time the clear was performed). 12498 * Access: OP 12499 */ 12500 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12501 12502 /* reg_sbpm_max_buff_occupancy 12503 * Maximum value of buffer occupancy in cells monitored. Cleared by 12504 * writing to the clr field. 12505 * Access: RO 12506 */ 12507 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12508 12509 /* reg_sbpm_min_buff 12510 * Minimum buffer size for the limiter, in cells. 12511 * Access: RW 12512 */ 12513 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12514 12515 /* reg_sbpm_max_buff 12516 * When the pool associated to the port-pg/tclass is configured to 12517 * static, Maximum buffer size for the limiter configured in cells. 12518 * When the pool associated to the port-pg/tclass is configured to 12519 * dynamic, the max_buff holds the "alpha" parameter, supporting 12520 * the following values: 12521 * 0: 0 12522 * i: (1/128)*2^(i-1), for i=1..14 12523 * 0xFF: Infinity 12524 * Access: RW 12525 */ 12526 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12527 12528 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12529 enum mlxsw_reg_sbxx_dir dir, bool clr, 12530 u32 min_buff, u32 max_buff) 12531 { 12532 MLXSW_REG_ZERO(sbpm, payload); 12533 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12534 mlxsw_reg_sbpm_pool_set(payload, pool); 12535 mlxsw_reg_sbpm_dir_set(payload, dir); 12536 mlxsw_reg_sbpm_clr_set(payload, clr); 12537 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12538 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12539 } 12540 12541 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12542 u32 *p_max_buff_occupancy) 12543 { 12544 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12545 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12546 } 12547 12548 /* SBMM - Shared Buffer Multicast Management Register 12549 * -------------------------------------------------- 12550 * The SBMM register configures and retrieves the shared buffer allocation 12551 * and configuration for MC packets according to Switch-Priority, including 12552 * the binding to pool and definition of the associated quota. 12553 */ 12554 #define MLXSW_REG_SBMM_ID 0xB004 12555 #define MLXSW_REG_SBMM_LEN 0x28 12556 12557 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12558 12559 /* reg_sbmm_prio 12560 * Switch Priority. 12561 * Access: Index 12562 */ 12563 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12564 12565 /* reg_sbmm_min_buff 12566 * Minimum buffer size for the limiter, in cells. 12567 * Access: RW 12568 */ 12569 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12570 12571 /* reg_sbmm_max_buff 12572 * When the pool associated to the port-pg/tclass is configured to 12573 * static, Maximum buffer size for the limiter configured in cells. 12574 * When the pool associated to the port-pg/tclass is configured to 12575 * dynamic, the max_buff holds the "alpha" parameter, supporting 12576 * the following values: 12577 * 0: 0 12578 * i: (1/128)*2^(i-1), for i=1..14 12579 * 0xFF: Infinity 12580 * Access: RW 12581 */ 12582 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12583 12584 /* reg_sbmm_pool 12585 * Association of the port-priority to a pool. 12586 * Access: RW 12587 */ 12588 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12589 12590 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12591 u32 max_buff, u8 pool) 12592 { 12593 MLXSW_REG_ZERO(sbmm, payload); 12594 mlxsw_reg_sbmm_prio_set(payload, prio); 12595 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12596 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12597 mlxsw_reg_sbmm_pool_set(payload, pool); 12598 } 12599 12600 /* SBSR - Shared Buffer Status Register 12601 * ------------------------------------ 12602 * The SBSR register retrieves the shared buffer occupancy according to 12603 * Port-Pool. Note that this register enables reading a large amount of data. 12604 * It is the user's responsibility to limit the amount of data to ensure the 12605 * response can match the maximum transfer unit. In case the response exceeds 12606 * the maximum transport unit, it will be truncated with no special notice. 12607 */ 12608 #define MLXSW_REG_SBSR_ID 0xB005 12609 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12610 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12611 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12612 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12613 MLXSW_REG_SBSR_REC_LEN * \ 12614 MLXSW_REG_SBSR_REC_MAX_COUNT) 12615 12616 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12617 12618 /* reg_sbsr_clr 12619 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12620 * field is cleared (and a new max value is tracked from the time the clear 12621 * was performed). 12622 * Access: OP 12623 */ 12624 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12625 12626 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12627 12628 /* reg_sbsr_port_page 12629 * Determines the range of the ports specified in the 'ingress_port_mask' 12630 * and 'egress_port_mask' bit masks. 12631 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12632 * Access: Index 12633 */ 12634 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12635 12636 /* reg_sbsr_ingress_port_mask 12637 * Bit vector for all ingress network ports. 12638 * Indicates which of the ports (for which the relevant bit is set) 12639 * are affected by the set operation. Configuration of any other port 12640 * does not change. 12641 * Access: Index 12642 */ 12643 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12644 12645 /* reg_sbsr_pg_buff_mask 12646 * Bit vector for all switch priority groups. 12647 * Indicates which of the priorities (for which the relevant bit is set) 12648 * are affected by the set operation. Configuration of any other priority 12649 * does not change. 12650 * Range is 0..cap_max_pg_buffers - 1 12651 * Access: Index 12652 */ 12653 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12654 12655 /* reg_sbsr_egress_port_mask 12656 * Bit vector for all egress network ports. 12657 * Indicates which of the ports (for which the relevant bit is set) 12658 * are affected by the set operation. Configuration of any other port 12659 * does not change. 12660 * Access: Index 12661 */ 12662 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12663 12664 /* reg_sbsr_tclass_mask 12665 * Bit vector for all traffic classes. 12666 * Indicates which of the traffic classes (for which the relevant bit is 12667 * set) are affected by the set operation. Configuration of any other 12668 * traffic class does not change. 12669 * Range is 0..cap_max_tclass - 1 12670 * Access: Index 12671 */ 12672 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12673 12674 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12675 { 12676 MLXSW_REG_ZERO(sbsr, payload); 12677 mlxsw_reg_sbsr_clr_set(payload, clr); 12678 } 12679 12680 /* reg_sbsr_rec_buff_occupancy 12681 * Current buffer occupancy in cells. 12682 * Access: RO 12683 */ 12684 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12685 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12686 12687 /* reg_sbsr_rec_max_buff_occupancy 12688 * Maximum value of buffer occupancy in cells monitored. Cleared by 12689 * writing to the clr field. 12690 * Access: RO 12691 */ 12692 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12693 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12694 12695 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12696 u32 *p_buff_occupancy, 12697 u32 *p_max_buff_occupancy) 12698 { 12699 *p_buff_occupancy = 12700 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12701 *p_max_buff_occupancy = 12702 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12703 } 12704 12705 /* SBIB - Shared Buffer Internal Buffer Register 12706 * --------------------------------------------- 12707 * The SBIB register configures per port buffers for internal use. The internal 12708 * buffers consume memory on the port buffers (note that the port buffers are 12709 * used also by PBMC). 12710 * 12711 * For Spectrum this is used for egress mirroring. 12712 */ 12713 #define MLXSW_REG_SBIB_ID 0xB006 12714 #define MLXSW_REG_SBIB_LEN 0x10 12715 12716 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12717 12718 /* reg_sbib_local_port 12719 * Local port number 12720 * Not supported for CPU port and router port 12721 * Access: Index 12722 */ 12723 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12724 12725 /* reg_sbib_buff_size 12726 * Units represented in cells 12727 * Allowed range is 0 to (cap_max_headroom_size - 1) 12728 * Default is 0 12729 * Access: RW 12730 */ 12731 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12732 12733 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12734 u32 buff_size) 12735 { 12736 MLXSW_REG_ZERO(sbib, payload); 12737 mlxsw_reg_sbib_local_port_set(payload, local_port); 12738 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12739 } 12740 12741 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12742 MLXSW_REG(sgcr), 12743 MLXSW_REG(spad), 12744 MLXSW_REG(sspr), 12745 MLXSW_REG(sfdat), 12746 MLXSW_REG(sfd), 12747 MLXSW_REG(sfn), 12748 MLXSW_REG(spms), 12749 MLXSW_REG(spvid), 12750 MLXSW_REG(spvm), 12751 MLXSW_REG(spaft), 12752 MLXSW_REG(sfgc), 12753 MLXSW_REG(sfdf), 12754 MLXSW_REG(sldr), 12755 MLXSW_REG(slcr), 12756 MLXSW_REG(slcor), 12757 MLXSW_REG(spmlr), 12758 MLXSW_REG(svfa), 12759 MLXSW_REG(spvtr), 12760 MLXSW_REG(svpe), 12761 MLXSW_REG(sfmr), 12762 MLXSW_REG(spvmlr), 12763 MLXSW_REG(spvc), 12764 MLXSW_REG(spevet), 12765 MLXSW_REG(smpe), 12766 MLXSW_REG(smid2), 12767 MLXSW_REG(cwtp), 12768 MLXSW_REG(cwtpm), 12769 MLXSW_REG(pgcr), 12770 MLXSW_REG(ppbt), 12771 MLXSW_REG(pacl), 12772 MLXSW_REG(pagt), 12773 MLXSW_REG(ptar), 12774 MLXSW_REG(ppbs), 12775 MLXSW_REG(prcr), 12776 MLXSW_REG(pefa), 12777 MLXSW_REG(pemrbt), 12778 MLXSW_REG(ptce2), 12779 MLXSW_REG(perpt), 12780 MLXSW_REG(peabfe), 12781 MLXSW_REG(perar), 12782 MLXSW_REG(ptce3), 12783 MLXSW_REG(percr), 12784 MLXSW_REG(pererp), 12785 MLXSW_REG(iedr), 12786 MLXSW_REG(qpts), 12787 MLXSW_REG(qpcr), 12788 MLXSW_REG(qtct), 12789 MLXSW_REG(qeec), 12790 MLXSW_REG(qrwe), 12791 MLXSW_REG(qpdsm), 12792 MLXSW_REG(qpdp), 12793 MLXSW_REG(qpdpm), 12794 MLXSW_REG(qtctm), 12795 MLXSW_REG(qpsc), 12796 MLXSW_REG(pmlp), 12797 MLXSW_REG(pmtu), 12798 MLXSW_REG(ptys), 12799 MLXSW_REG(ppad), 12800 MLXSW_REG(paos), 12801 MLXSW_REG(pfcc), 12802 MLXSW_REG(ppcnt), 12803 MLXSW_REG(pptb), 12804 MLXSW_REG(pbmc), 12805 MLXSW_REG(pspa), 12806 MLXSW_REG(pmaos), 12807 MLXSW_REG(pplr), 12808 MLXSW_REG(pmtdb), 12809 MLXSW_REG(pmecr), 12810 MLXSW_REG(pmpe), 12811 MLXSW_REG(pddr), 12812 MLXSW_REG(pmmp), 12813 MLXSW_REG(pllp), 12814 MLXSW_REG(pmtm), 12815 MLXSW_REG(htgt), 12816 MLXSW_REG(hpkt), 12817 MLXSW_REG(rgcr), 12818 MLXSW_REG(ritr), 12819 MLXSW_REG(rtar), 12820 MLXSW_REG(ratr), 12821 MLXSW_REG(rtdp), 12822 MLXSW_REG(rips), 12823 MLXSW_REG(ratrad), 12824 MLXSW_REG(rdpm), 12825 MLXSW_REG(ricnt), 12826 MLXSW_REG(rrcr), 12827 MLXSW_REG(ralta), 12828 MLXSW_REG(ralst), 12829 MLXSW_REG(raltb), 12830 MLXSW_REG(ralue), 12831 MLXSW_REG(rauht), 12832 MLXSW_REG(raleu), 12833 MLXSW_REG(rauhtd), 12834 MLXSW_REG(rigr2), 12835 MLXSW_REG(recr2), 12836 MLXSW_REG(rmft2), 12837 MLXSW_REG(reiv), 12838 MLXSW_REG(mfcr), 12839 MLXSW_REG(mfsc), 12840 MLXSW_REG(mfsm), 12841 MLXSW_REG(mfsl), 12842 MLXSW_REG(fore), 12843 MLXSW_REG(mtcap), 12844 MLXSW_REG(mtmp), 12845 MLXSW_REG(mtwe), 12846 MLXSW_REG(mtbr), 12847 MLXSW_REG(mcia), 12848 MLXSW_REG(mpat), 12849 MLXSW_REG(mpar), 12850 MLXSW_REG(mgir), 12851 MLXSW_REG(mrsr), 12852 MLXSW_REG(mlcr), 12853 MLXSW_REG(mcion), 12854 MLXSW_REG(mtpps), 12855 MLXSW_REG(mtutc), 12856 MLXSW_REG(mpsc), 12857 MLXSW_REG(mcqi), 12858 MLXSW_REG(mcc), 12859 MLXSW_REG(mcda), 12860 MLXSW_REG(mgpc), 12861 MLXSW_REG(mprs), 12862 MLXSW_REG(mogcr), 12863 MLXSW_REG(mpagr), 12864 MLXSW_REG(momte), 12865 MLXSW_REG(mtpppc), 12866 MLXSW_REG(mtpptr), 12867 MLXSW_REG(mtptpt), 12868 MLXSW_REG(mtpcpc), 12869 MLXSW_REG(mfgd), 12870 MLXSW_REG(mgpir), 12871 MLXSW_REG(mbct), 12872 MLXSW_REG(mddt), 12873 MLXSW_REG(mddq), 12874 MLXSW_REG(mddc), 12875 MLXSW_REG(mfde), 12876 MLXSW_REG(tngcr), 12877 MLXSW_REG(tnumt), 12878 MLXSW_REG(tnqcr), 12879 MLXSW_REG(tnqdr), 12880 MLXSW_REG(tneem), 12881 MLXSW_REG(tndem), 12882 MLXSW_REG(tnpc), 12883 MLXSW_REG(tigcr), 12884 MLXSW_REG(tieem), 12885 MLXSW_REG(tidem), 12886 MLXSW_REG(sbpr), 12887 MLXSW_REG(sbcm), 12888 MLXSW_REG(sbpm), 12889 MLXSW_REG(sbmm), 12890 MLXSW_REG(sbsr), 12891 MLXSW_REG(sbib), 12892 }; 12893 12894 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12895 { 12896 const struct mlxsw_reg_info *reg_info; 12897 int i; 12898 12899 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12900 reg_info = mlxsw_reg_infos[i]; 12901 if (reg_info->id == reg_id) 12902 return reg_info->name; 12903 } 12904 return "*UNKNOWN*"; 12905 } 12906 12907 /* PUDE - Port Up / Down Event 12908 * --------------------------- 12909 * Reports the operational state change of a port. 12910 */ 12911 #define MLXSW_REG_PUDE_LEN 0x10 12912 12913 /* reg_pude_swid 12914 * Switch partition ID with which to associate the port. 12915 * Access: Index 12916 */ 12917 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12918 12919 /* reg_pude_local_port 12920 * Local port number. 12921 * Access: Index 12922 */ 12923 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12924 12925 /* reg_pude_admin_status 12926 * Port administrative state (the desired state). 12927 * 1 - Up. 12928 * 2 - Down. 12929 * 3 - Up once. This means that in case of link failure, the port won't go 12930 * into polling mode, but will wait to be re-enabled by software. 12931 * 4 - Disabled by system. Can only be set by hardware. 12932 * Access: RO 12933 */ 12934 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12935 12936 /* reg_pude_oper_status 12937 * Port operatioanl state. 12938 * 1 - Up. 12939 * 2 - Down. 12940 * 3 - Down by port failure. This means that the device will not let the 12941 * port up again until explicitly specified by software. 12942 * Access: RO 12943 */ 12944 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12945 12946 #endif 12947