1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_REG_H
5 #define _MLXSW_REG_H
6 
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
11 
12 #include "item.h"
13 #include "port.h"
14 
15 struct mlxsw_reg_info {
16 	u16 id;
17 	u16 len; /* In u8 */
18 	const char *name;
19 };
20 
21 #define MLXSW_REG_DEFINE(_name, _id, _len)				\
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {		\
23 	.id = _id,							\
24 	.len = _len,							\
25 	.name = #_name,							\
26 }
27 
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31 
32 /* SGCR - Switch General Configuration Register
33  * --------------------------------------------
34  * This register is used for configuration of the switch capabilities.
35  */
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
38 
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40 
41 /* reg_sgcr_llb
42  * Link Local Broadcast (Default=0)
43  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44  * packets and ignore the IGMP snooping entries.
45  * Access: RW
46  */
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48 
49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50 {
51 	MLXSW_REG_ZERO(sgcr, payload);
52 	mlxsw_reg_sgcr_llb_set(payload, !!llb);
53 }
54 
55 /* SPAD - Switch Physical Address Register
56  * ---------------------------------------
57  * The SPAD register configures the switch physical MAC address.
58  */
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
61 
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63 
64 /* reg_spad_base_mac
65  * Base MAC address for the switch partitions.
66  * Per switch partition MAC address is equal to:
67  * base_mac + swid
68  * Access: RW
69  */
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71 
72 /* SMID - Switch Multicast ID
73  * --------------------------
74  * The MID record maps from a MID (Multicast ID), which is a unique identifier
75  * of the multicast group within the stacking domain, into a list of local
76  * ports into which the packet is replicated.
77  */
78 #define MLXSW_REG_SMID_ID 0x2007
79 #define MLXSW_REG_SMID_LEN 0x240
80 
81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82 
83 /* reg_smid_swid
84  * Switch partition ID.
85  * Access: Index
86  */
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88 
89 /* reg_smid_mid
90  * Multicast identifier - global identifier that represents the multicast group
91  * across all devices.
92  * Access: Index
93  */
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95 
96 /* reg_smid_port
97  * Local port memebership (1 bit per port).
98  * Access: RW
99  */
100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101 
102 /* reg_smid_port_mask
103  * Local port mask (1 bit per port).
104  * Access: W
105  */
106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107 
108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 				       u8 port, bool set)
110 {
111 	MLXSW_REG_ZERO(smid, payload);
112 	mlxsw_reg_smid_swid_set(payload, 0);
113 	mlxsw_reg_smid_mid_set(payload, mid);
114 	mlxsw_reg_smid_port_set(payload, port, set);
115 	mlxsw_reg_smid_port_mask_set(payload, port, 1);
116 }
117 
118 /* SSPR - Switch System Port Record Register
119  * -----------------------------------------
120  * Configures the system port to local port mapping.
121  */
122 #define MLXSW_REG_SSPR_ID 0x2008
123 #define MLXSW_REG_SSPR_LEN 0x8
124 
125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126 
127 /* reg_sspr_m
128  * Master - if set, then the record describes the master system port.
129  * This is needed in case a local port is mapped into several system ports
130  * (for multipathing). That number will be reported as the source system
131  * port when packets are forwarded to the CPU. Only one master port is allowed
132  * per local port.
133  *
134  * Note: Must be set for Spectrum.
135  * Access: RW
136  */
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138 
139 /* reg_sspr_local_port
140  * Local port number.
141  *
142  * Access: RW
143  */
144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145 
146 /* reg_sspr_sub_port
147  * Virtual port within the physical port.
148  * Should be set to 0 when virtual ports are not enabled on the port.
149  *
150  * Access: RW
151  */
152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153 
154 /* reg_sspr_system_port
155  * Unique identifier within the stacking domain that represents all the ports
156  * that are available in the system (external ports).
157  *
158  * Currently, only single-ASIC configurations are supported, so we default to
159  * 1:1 mapping between system ports and local ports.
160  * Access: Index
161  */
162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163 
164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165 {
166 	MLXSW_REG_ZERO(sspr, payload);
167 	mlxsw_reg_sspr_m_set(payload, 1);
168 	mlxsw_reg_sspr_local_port_set(payload, local_port);
169 	mlxsw_reg_sspr_sub_port_set(payload, 0);
170 	mlxsw_reg_sspr_system_port_set(payload, local_port);
171 }
172 
173 /* SFDAT - Switch Filtering Database Aging Time
174  * --------------------------------------------
175  * Controls the Switch aging time. Aging time is able to be set per Switch
176  * Partition.
177  */
178 #define MLXSW_REG_SFDAT_ID 0x2009
179 #define MLXSW_REG_SFDAT_LEN 0x8
180 
181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182 
183 /* reg_sfdat_swid
184  * Switch partition ID.
185  * Access: Index
186  */
187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188 
189 /* reg_sfdat_age_time
190  * Aging time in seconds
191  * Min - 10 seconds
192  * Max - 1,000,000 seconds
193  * Default is 300 seconds.
194  * Access: RW
195  */
196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197 
198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199 {
200 	MLXSW_REG_ZERO(sfdat, payload);
201 	mlxsw_reg_sfdat_swid_set(payload, 0);
202 	mlxsw_reg_sfdat_age_time_set(payload, age_time);
203 }
204 
205 /* SFD - Switch Filtering Database
206  * -------------------------------
207  * The following register defines the access to the filtering database.
208  * The register supports querying, adding, removing and modifying the database.
209  * The access is optimized for bulk updates in which case more than one
210  * FDB record is present in the same command.
211  */
212 #define MLXSW_REG_SFD_ID 0x200A
213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +	\
217 			   MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218 
219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220 
221 /* reg_sfd_swid
222  * Switch partition ID for queries. Reserved on Write.
223  * Access: Index
224  */
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226 
227 enum mlxsw_reg_sfd_op {
228 	/* Dump entire FDB a (process according to record_locator) */
229 	MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230 	/* Query records by {MAC, VID/FID} value */
231 	MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232 	/* Query and clear activity. Query records by {MAC, VID/FID} value */
233 	MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234 	/* Test. Response indicates if each of the records could be
235 	 * added to the FDB.
236 	 */
237 	MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238 	/* Add/modify. Aged-out records cannot be added. This command removes
239 	 * the learning notification of the {MAC, VID/FID}. Response includes
240 	 * the entries that were added to the FDB.
241 	 */
242 	MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243 	/* Remove record by {MAC, VID/FID}. This command also removes
244 	 * the learning notification and aged-out notifications
245 	 * of the {MAC, VID/FID}. The response provides current (pre-removal)
246 	 * entries as non-aged-out.
247 	 */
248 	MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249 	/* Remove learned notification by {MAC, VID/FID}. The response provides
250 	 * the removed learning notification.
251 	 */
252 	MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253 };
254 
255 /* reg_sfd_op
256  * Operation.
257  * Access: OP
258  */
259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260 
261 /* reg_sfd_record_locator
262  * Used for querying the FDB. Use record_locator=0 to initiate the
263  * query. When a record is returned, a new record_locator is
264  * returned to be used in the subsequent query.
265  * Reserved for database update.
266  * Access: Index
267  */
268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269 
270 /* reg_sfd_num_rec
271  * Request: Number of records to read/add/modify/remove
272  * Response: Number of records read/added/replaced/removed
273  * See above description for more details.
274  * Ranges 0..64
275  * Access: RW
276  */
277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278 
279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 				      u32 record_locator)
281 {
282 	MLXSW_REG_ZERO(sfd, payload);
283 	mlxsw_reg_sfd_op_set(payload, op);
284 	mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285 }
286 
287 /* reg_sfd_rec_swid
288  * Switch partition ID.
289  * Access: Index
290  */
291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
293 
294 enum mlxsw_reg_sfd_rec_type {
295 	MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 	MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 	MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 	MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
299 };
300 
301 /* reg_sfd_rec_type
302  * FDB record type.
303  * Access: RW
304  */
305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
307 
308 enum mlxsw_reg_sfd_rec_policy {
309 	/* Replacement disabled, aging disabled. */
310 	MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311 	/* (mlag remote): Replacement enabled, aging disabled,
312 	 * learning notification enabled on this port.
313 	 */
314 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315 	/* (ingress device): Replacement enabled, aging enabled. */
316 	MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
317 };
318 
319 /* reg_sfd_rec_policy
320  * Policy.
321  * Access: RW
322  */
323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
325 
326 /* reg_sfd_rec_a
327  * Activity. Set for new static entries. Set for static entries if a frame SMAC
328  * lookup hits on the entry.
329  * To clear the a bit, use "query and clear activity" op.
330  * Access: RO
331  */
332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 		     MLXSW_REG_SFD_REC_LEN, 0x00, false);
334 
335 /* reg_sfd_rec_mac
336  * MAC address.
337  * Access: Index
338  */
339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 		       MLXSW_REG_SFD_REC_LEN, 0x02);
341 
342 enum mlxsw_reg_sfd_rec_action {
343 	/* forward */
344 	MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345 	/* forward and trap, trap_id is FDB_TRAP */
346 	MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347 	/* trap and do not forward, trap_id is FDB_TRAP */
348 	MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349 	/* forward to IP router */
350 	MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 	MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
352 };
353 
354 /* reg_sfd_rec_action
355  * Action to apply on the packet.
356  * Note: Dynamic entries can only be configured with NOP action.
357  * Access: RW
358  */
359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
361 
362 /* reg_sfd_uc_sub_port
363  * VEPA channel on local port.
364  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
365  * VEPA is not enabled.
366  * Access: RW
367  */
368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
370 
371 /* reg_sfd_uc_fid_vid
372  * Filtering ID or VLAN ID
373  * For SwitchX and SwitchX-2:
374  * - Dynamic entries (policy 2,3) use FID
375  * - Static entries (policy 0) use VID
376  * - When independent learning is configured, VID=FID
377  * For Spectrum: use FID for both Dynamic and Static entries.
378  * VID should not be used.
379  * Access: Index
380  */
381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
383 
384 /* reg_sfd_uc_system_port
385  * Unique port identifier for the final destination of the packet.
386  * Access: RW
387  */
388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
390 
391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 					  enum mlxsw_reg_sfd_rec_type rec_type,
393 					  const char *mac,
394 					  enum mlxsw_reg_sfd_rec_action action)
395 {
396 	u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
397 
398 	if (rec_index >= num_rec)
399 		mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 	mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 	mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 	mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 	mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404 }
405 
406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 					 enum mlxsw_reg_sfd_rec_policy policy,
408 					 const char *mac, u16 fid_vid,
409 					 enum mlxsw_reg_sfd_rec_action action,
410 					 u8 local_port)
411 {
412 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 			       MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 	mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 	mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 	mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418 }
419 
420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 					   char *mac, u16 *p_fid_vid,
422 					   u8 *p_local_port)
423 {
424 	mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 	*p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 	*p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
427 }
428 
429 /* reg_sfd_uc_lag_sub_port
430  * LAG sub port.
431  * Must be 0 if multichannel VEPA is not enabled.
432  * Access: RW
433  */
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
436 
437 /* reg_sfd_uc_lag_fid_vid
438  * Filtering ID or VLAN ID
439  * For SwitchX and SwitchX-2:
440  * - Dynamic entries (policy 2,3) use FID
441  * - Static entries (policy 0) use VID
442  * - When independent learning is configured, VID=FID
443  * For Spectrum: use FID for both Dynamic and Static entries.
444  * VID should not be used.
445  * Access: Index
446  */
447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
449 
450 /* reg_sfd_uc_lag_lag_vid
451  * Indicates VID in case of vFIDs. Reserved for FIDs.
452  * Access: RW
453  */
454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
456 
457 /* reg_sfd_uc_lag_lag_id
458  * LAG Identifier - pointer into the LAG descriptor table.
459  * Access: RW
460  */
461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
463 
464 static inline void
465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 			  enum mlxsw_reg_sfd_rec_policy policy,
467 			  const char *mac, u16 fid_vid,
468 			  enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
469 			  u16 lag_id)
470 {
471 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
473 			       mac, action);
474 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 	mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 	mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 	mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 	mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
479 }
480 
481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 					       char *mac, u16 *p_vid,
483 					       u16 *p_lag_id)
484 {
485 	mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 	*p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 	*p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
488 }
489 
490 /* reg_sfd_mc_pgi
491  *
492  * Multicast port group index - index into the port group table.
493  * Value 0x1FFF indicates the pgi should point to the MID entry.
494  * For Spectrum this value must be set to 0x1FFF
495  * Access: RW
496  */
497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
499 
500 /* reg_sfd_mc_fid_vid
501  *
502  * Filtering ID or VLAN ID
503  * Access: Index
504  */
505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
507 
508 /* reg_sfd_mc_mid
509  *
510  * Multicast identifier - global identifier that represents the multicast
511  * group across all devices.
512  * Access: RW
513  */
514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 		     MLXSW_REG_SFD_REC_LEN, 0x0C, false);
516 
517 static inline void
518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 		      const char *mac, u16 fid_vid,
520 		      enum mlxsw_reg_sfd_rec_action action, u16 mid)
521 {
522 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 			       MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 	mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 	mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 	mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
527 }
528 
529 /* reg_sfd_uc_tunnel_uip_msb
530  * When protocol is IPv4, the most significant byte of the underlay IPv4
531  * destination IP.
532  * When protocol is IPv6, reserved.
533  * Access: RW
534  */
535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 		     8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
537 
538 /* reg_sfd_uc_tunnel_fid
539  * Filtering ID.
540  * Access: Index
541  */
542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 		     MLXSW_REG_SFD_REC_LEN, 0x08, false);
544 
545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 	MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
548 };
549 
550 /* reg_sfd_uc_tunnel_protocol
551  * IP protocol.
552  * Access: RW
553  */
554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 		     1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
556 
557 /* reg_sfd_uc_tunnel_uip_lsb
558  * When protocol is IPv4, the least significant bytes of the underlay
559  * IPv4 destination IP.
560  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
561  * which is configured by RIPS.
562  * Access: RW
563  */
564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 		     24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
566 
567 static inline void
568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 			     enum mlxsw_reg_sfd_rec_policy policy,
570 			     const char *mac, u16 fid,
571 			     enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 			     enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
573 {
574 	mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 			       MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
576 			       action);
577 	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 	mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 	mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 	mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 	mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
582 }
583 
584 /* SFN - Switch FDB Notification Register
585  * -------------------------------------------
586  * The switch provides notifications on newly learned FDB entries and
587  * aged out entries. The notifications can be polled by software.
588  */
589 #define MLXSW_REG_SFN_ID 0x200B
590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +	\
594 			   MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
595 
596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
597 
598 /* reg_sfn_swid
599  * Switch partition ID.
600  * Access: Index
601  */
602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
603 
604 /* reg_sfn_end
605  * Forces the current session to end.
606  * Access: OP
607  */
608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
609 
610 /* reg_sfn_num_rec
611  * Request: Number of learned notifications and aged-out notification
612  * records requested.
613  * Response: Number of notification records returned (must be smaller
614  * than or equal to the value requested)
615  * Ranges 0..64
616  * Access: OP
617  */
618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
619 
620 static inline void mlxsw_reg_sfn_pack(char *payload)
621 {
622 	MLXSW_REG_ZERO(sfn, payload);
623 	mlxsw_reg_sfn_swid_set(payload, 0);
624 	mlxsw_reg_sfn_end_set(payload, 1);
625 	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
626 }
627 
628 /* reg_sfn_rec_swid
629  * Switch partition ID.
630  * Access: RO
631  */
632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
634 
635 enum mlxsw_reg_sfn_rec_type {
636 	/* MAC addresses learned on a regular port. */
637 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638 	/* MAC addresses learned on a LAG port. */
639 	MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640 	/* Aged-out MAC address on a regular port. */
641 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642 	/* Aged-out MAC address on a LAG port. */
643 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
644 	/* Learned unicast tunnel record. */
645 	MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
646 	/* Aged-out unicast tunnel record. */
647 	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
648 };
649 
650 /* reg_sfn_rec_type
651  * Notification record type.
652  * Access: RO
653  */
654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
655 		     MLXSW_REG_SFN_REC_LEN, 0x00, false);
656 
657 /* reg_sfn_rec_mac
658  * MAC address.
659  * Access: RO
660  */
661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
662 		       MLXSW_REG_SFN_REC_LEN, 0x02);
663 
664 /* reg_sfn_mac_sub_port
665  * VEPA channel on the local port.
666  * 0 if multichannel VEPA is not enabled.
667  * Access: RO
668  */
669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
670 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
671 
672 /* reg_sfn_mac_fid
673  * Filtering identifier.
674  * Access: RO
675  */
676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
677 		     MLXSW_REG_SFN_REC_LEN, 0x08, false);
678 
679 /* reg_sfn_mac_system_port
680  * Unique port identifier for the final destination of the packet.
681  * Access: RO
682  */
683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
684 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
685 
686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
687 					    char *mac, u16 *p_vid,
688 					    u8 *p_local_port)
689 {
690 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
691 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
692 	*p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
693 }
694 
695 /* reg_sfn_mac_lag_lag_id
696  * LAG ID (pointer into the LAG descriptor table).
697  * Access: RO
698  */
699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
700 		     MLXSW_REG_SFN_REC_LEN, 0x0C, false);
701 
702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
703 						char *mac, u16 *p_vid,
704 						u16 *p_lag_id)
705 {
706 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
707 	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
708 	*p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
709 }
710 
711 /* reg_sfn_uc_tunnel_uip_msb
712  * When protocol is IPv4, the most significant byte of the underlay IPv4
713  * address of the remote VTEP.
714  * When protocol is IPv6, reserved.
715  * Access: RO
716  */
717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
718 		     8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
719 
720 enum mlxsw_reg_sfn_uc_tunnel_protocol {
721 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
722 	MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
723 };
724 
725 /* reg_sfn_uc_tunnel_protocol
726  * IP protocol.
727  * Access: RO
728  */
729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
730 		     1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
731 
732 /* reg_sfn_uc_tunnel_uip_lsb
733  * When protocol is IPv4, the least significant bytes of the underlay
734  * IPv4 address of the remote VTEP.
735  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
736  * Access: RO
737  */
738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
739 		     24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
740 
741 enum mlxsw_reg_sfn_tunnel_port {
742 	MLXSW_REG_SFN_TUNNEL_PORT_NVE,
743 	MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
744 	MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
745 	MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
746 };
747 
748 /* reg_sfn_uc_tunnel_port
749  * Tunnel port.
750  * Reserved on Spectrum.
751  * Access: RO
752  */
753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
754 		     MLXSW_REG_SFN_REC_LEN, 0x10, false);
755 
756 static inline void
757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
758 			       u16 *p_fid, u32 *p_uip,
759 			       enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
760 {
761 	u32 uip_msb, uip_lsb;
762 
763 	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
764 	*p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
765 	uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
766 	uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
767 	*p_uip = uip_msb << 24 | uip_lsb;
768 	*p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
769 }
770 
771 /* SPMS - Switch Port MSTP/RSTP State Register
772  * -------------------------------------------
773  * Configures the spanning tree state of a physical port.
774  */
775 #define MLXSW_REG_SPMS_ID 0x200D
776 #define MLXSW_REG_SPMS_LEN 0x404
777 
778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
779 
780 /* reg_spms_local_port
781  * Local port number.
782  * Access: Index
783  */
784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
785 
786 enum mlxsw_reg_spms_state {
787 	MLXSW_REG_SPMS_STATE_NO_CHANGE,
788 	MLXSW_REG_SPMS_STATE_DISCARDING,
789 	MLXSW_REG_SPMS_STATE_LEARNING,
790 	MLXSW_REG_SPMS_STATE_FORWARDING,
791 };
792 
793 /* reg_spms_state
794  * Spanning tree state of each VLAN ID (VID) of the local port.
795  * 0 - Do not change spanning tree state (used only when writing).
796  * 1 - Discarding. No learning or forwarding to/from this port (default).
797  * 2 - Learning. Port is learning, but not forwarding.
798  * 3 - Forwarding. Port is learning and forwarding.
799  * Access: RW
800  */
801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
802 
803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
804 {
805 	MLXSW_REG_ZERO(spms, payload);
806 	mlxsw_reg_spms_local_port_set(payload, local_port);
807 }
808 
809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
810 					   enum mlxsw_reg_spms_state state)
811 {
812 	mlxsw_reg_spms_state_set(payload, vid, state);
813 }
814 
815 /* SPVID - Switch Port VID
816  * -----------------------
817  * The switch port VID configures the default VID for a port.
818  */
819 #define MLXSW_REG_SPVID_ID 0x200E
820 #define MLXSW_REG_SPVID_LEN 0x08
821 
822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
823 
824 /* reg_spvid_local_port
825  * Local port number.
826  * Access: Index
827  */
828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
829 
830 /* reg_spvid_sub_port
831  * Virtual port within the physical port.
832  * Should be set to 0 when virtual ports are not enabled on the port.
833  * Access: Index
834  */
835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
836 
837 /* reg_spvid_pvid
838  * Port default VID
839  * Access: RW
840  */
841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
842 
843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
844 {
845 	MLXSW_REG_ZERO(spvid, payload);
846 	mlxsw_reg_spvid_local_port_set(payload, local_port);
847 	mlxsw_reg_spvid_pvid_set(payload, pvid);
848 }
849 
850 /* SPVM - Switch Port VLAN Membership
851  * ----------------------------------
852  * The Switch Port VLAN Membership register configures the VLAN membership
853  * of a port in a VLAN denoted by VID. VLAN membership is managed per
854  * virtual port. The register can be used to add and remove VID(s) from a port.
855  */
856 #define MLXSW_REG_SPVM_ID 0x200F
857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +	\
861 		    MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
862 
863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
864 
865 /* reg_spvm_pt
866  * Priority tagged. If this bit is set, packets forwarded to the port with
867  * untagged VLAN membership (u bit is set) will be tagged with priority tag
868  * (VID=0)
869  * Access: RW
870  */
871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
872 
873 /* reg_spvm_pte
874  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
875  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
876  * Access: WO
877  */
878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
879 
880 /* reg_spvm_local_port
881  * Local port number.
882  * Access: Index
883  */
884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
885 
886 /* reg_spvm_sub_port
887  * Virtual port within the physical port.
888  * Should be set to 0 when virtual ports are not enabled on the port.
889  * Access: Index
890  */
891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
892 
893 /* reg_spvm_num_rec
894  * Number of records to update. Each record contains: i, e, u, vid.
895  * Access: OP
896  */
897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
898 
899 /* reg_spvm_rec_i
900  * Ingress membership in VLAN ID.
901  * Access: Index
902  */
903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
904 		     MLXSW_REG_SPVM_BASE_LEN, 14, 1,
905 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
906 
907 /* reg_spvm_rec_e
908  * Egress membership in VLAN ID.
909  * Access: Index
910  */
911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
912 		     MLXSW_REG_SPVM_BASE_LEN, 13, 1,
913 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
914 
915 /* reg_spvm_rec_u
916  * Untagged - port is an untagged member - egress transmission uses untagged
917  * frames on VID<n>
918  * Access: Index
919  */
920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
921 		     MLXSW_REG_SPVM_BASE_LEN, 12, 1,
922 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
923 
924 /* reg_spvm_rec_vid
925  * Egress membership in VLAN ID.
926  * Access: Index
927  */
928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
929 		     MLXSW_REG_SPVM_BASE_LEN, 0, 12,
930 		     MLXSW_REG_SPVM_REC_LEN, 0, false);
931 
932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
933 				       u16 vid_begin, u16 vid_end,
934 				       bool is_member, bool untagged)
935 {
936 	int size = vid_end - vid_begin + 1;
937 	int i;
938 
939 	MLXSW_REG_ZERO(spvm, payload);
940 	mlxsw_reg_spvm_local_port_set(payload, local_port);
941 	mlxsw_reg_spvm_num_rec_set(payload, size);
942 
943 	for (i = 0; i < size; i++) {
944 		mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
945 		mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
946 		mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
947 		mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
948 	}
949 }
950 
951 /* SPAFT - Switch Port Acceptable Frame Types
952  * ------------------------------------------
953  * The Switch Port Acceptable Frame Types register configures the frame
954  * admittance of the port.
955  */
956 #define MLXSW_REG_SPAFT_ID 0x2010
957 #define MLXSW_REG_SPAFT_LEN 0x08
958 
959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
960 
961 /* reg_spaft_local_port
962  * Local port number.
963  * Access: Index
964  *
965  * Note: CPU port is not supported (all tag types are allowed).
966  */
967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
968 
969 /* reg_spaft_sub_port
970  * Virtual port within the physical port.
971  * Should be set to 0 when virtual ports are not enabled on the port.
972  * Access: RW
973  */
974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
975 
976 /* reg_spaft_allow_untagged
977  * When set, untagged frames on the ingress are allowed (default).
978  * Access: RW
979  */
980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
981 
982 /* reg_spaft_allow_prio_tagged
983  * When set, priority tagged frames on the ingress are allowed (default).
984  * Access: RW
985  */
986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
987 
988 /* reg_spaft_allow_tagged
989  * When set, tagged frames on the ingress are allowed (default).
990  * Access: RW
991  */
992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
993 
994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
995 					bool allow_untagged)
996 {
997 	MLXSW_REG_ZERO(spaft, payload);
998 	mlxsw_reg_spaft_local_port_set(payload, local_port);
999 	mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000 	mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
1001 	mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002 }
1003 
1004 /* SFGC - Switch Flooding Group Configuration
1005  * ------------------------------------------
1006  * The following register controls the association of flooding tables and MIDs
1007  * to packet types used for flooding.
1008  */
1009 #define MLXSW_REG_SFGC_ID 0x2011
1010 #define MLXSW_REG_SFGC_LEN 0x10
1011 
1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013 
1014 enum mlxsw_reg_sfgc_type {
1015 	MLXSW_REG_SFGC_TYPE_BROADCAST,
1016 	MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019 	MLXSW_REG_SFGC_TYPE_RESERVED,
1020 	MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021 	MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022 	MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023 	MLXSW_REG_SFGC_TYPE_MAX,
1024 };
1025 
1026 /* reg_sfgc_type
1027  * The traffic type to reach the flooding table.
1028  * Access: Index
1029  */
1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031 
1032 enum mlxsw_reg_sfgc_bridge_type {
1033 	MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034 	MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035 };
1036 
1037 /* reg_sfgc_bridge_type
1038  * Access: Index
1039  *
1040  * Note: SwitchX-2 only supports 802.1Q mode.
1041  */
1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043 
1044 enum mlxsw_flood_table_type {
1045 	MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046 	MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047 	MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048 	MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049 	MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050 };
1051 
1052 /* reg_sfgc_table_type
1053  * See mlxsw_flood_table_type
1054  * Access: RW
1055  *
1056  * Note: FID offset and FID types are not supported in SwitchX-2.
1057  */
1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059 
1060 /* reg_sfgc_flood_table
1061  * Flooding table index to associate with the specific type on the specific
1062  * switch partition.
1063  * Access: RW
1064  */
1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066 
1067 /* reg_sfgc_mid
1068  * The multicast ID for the swid. Not supported for Spectrum
1069  * Access: RW
1070  */
1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072 
1073 /* reg_sfgc_counter_set_type
1074  * Counter Set Type for flow counters.
1075  * Access: RW
1076  */
1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078 
1079 /* reg_sfgc_counter_index
1080  * Counter Index for flow counters.
1081  * Access: RW
1082  */
1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084 
1085 static inline void
1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087 		    enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088 		    enum mlxsw_flood_table_type table_type,
1089 		    unsigned int flood_table)
1090 {
1091 	MLXSW_REG_ZERO(sfgc, payload);
1092 	mlxsw_reg_sfgc_type_set(payload, type);
1093 	mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094 	mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095 	mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096 	mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097 }
1098 
1099 /* SFTR - Switch Flooding Table Register
1100  * -------------------------------------
1101  * The switch flooding table is used for flooding packet replication. The table
1102  * defines a bit mask of ports for packet replication.
1103  */
1104 #define MLXSW_REG_SFTR_ID 0x2012
1105 #define MLXSW_REG_SFTR_LEN 0x420
1106 
1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108 
1109 /* reg_sftr_swid
1110  * Switch partition ID with which to associate the port.
1111  * Access: Index
1112  */
1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114 
1115 /* reg_sftr_flood_table
1116  * Flooding table index to associate with the specific type on the specific
1117  * switch partition.
1118  * Access: Index
1119  */
1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121 
1122 /* reg_sftr_index
1123  * Index. Used as an index into the Flooding Table in case the table is
1124  * configured to use VID / FID or FID Offset.
1125  * Access: Index
1126  */
1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128 
1129 /* reg_sftr_table_type
1130  * See mlxsw_flood_table_type
1131  * Access: RW
1132  */
1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134 
1135 /* reg_sftr_range
1136  * Range of entries to update
1137  * Access: Index
1138  */
1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140 
1141 /* reg_sftr_port
1142  * Local port membership (1 bit per port).
1143  * Access: RW
1144  */
1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146 
1147 /* reg_sftr_cpu_port_mask
1148  * CPU port mask (1 bit per port).
1149  * Access: W
1150  */
1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152 
1153 static inline void mlxsw_reg_sftr_pack(char *payload,
1154 				       unsigned int flood_table,
1155 				       unsigned int index,
1156 				       enum mlxsw_flood_table_type table_type,
1157 				       unsigned int range, u8 port, bool set)
1158 {
1159 	MLXSW_REG_ZERO(sftr, payload);
1160 	mlxsw_reg_sftr_swid_set(payload, 0);
1161 	mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162 	mlxsw_reg_sftr_index_set(payload, index);
1163 	mlxsw_reg_sftr_table_type_set(payload, table_type);
1164 	mlxsw_reg_sftr_range_set(payload, range);
1165 	mlxsw_reg_sftr_port_set(payload, port, set);
1166 	mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167 }
1168 
1169 /* SFDF - Switch Filtering DB Flush
1170  * --------------------------------
1171  * The switch filtering DB flush register is used to flush the FDB.
1172  * Note that FDB notifications are flushed as well.
1173  */
1174 #define MLXSW_REG_SFDF_ID 0x2013
1175 #define MLXSW_REG_SFDF_LEN 0x14
1176 
1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178 
1179 /* reg_sfdf_swid
1180  * Switch partition ID.
1181  * Access: Index
1182  */
1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184 
1185 enum mlxsw_reg_sfdf_flush_type {
1186 	MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187 	MLXSW_REG_SFDF_FLUSH_PER_FID,
1188 	MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189 	MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190 	MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191 	MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192 	MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193 	MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194 };
1195 
1196 /* reg_sfdf_flush_type
1197  * Flush type.
1198  * 0 - All SWID dynamic entries are flushed.
1199  * 1 - All FID dynamic entries are flushed.
1200  * 2 - All dynamic entries pointing to port are flushed.
1201  * 3 - All FID dynamic entries pointing to port are flushed.
1202  * 4 - All dynamic entries pointing to LAG are flushed.
1203  * 5 - All FID dynamic entries pointing to LAG are flushed.
1204  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1205  *     flushed.
1206  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1207  *     flushed, per FID.
1208  * Access: RW
1209  */
1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211 
1212 /* reg_sfdf_flush_static
1213  * Static.
1214  * 0 - Flush only dynamic entries.
1215  * 1 - Flush both dynamic and static entries.
1216  * Access: RW
1217  */
1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219 
1220 static inline void mlxsw_reg_sfdf_pack(char *payload,
1221 				       enum mlxsw_reg_sfdf_flush_type type)
1222 {
1223 	MLXSW_REG_ZERO(sfdf, payload);
1224 	mlxsw_reg_sfdf_flush_type_set(payload, type);
1225 	mlxsw_reg_sfdf_flush_static_set(payload, true);
1226 }
1227 
1228 /* reg_sfdf_fid
1229  * FID to flush.
1230  * Access: RW
1231  */
1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233 
1234 /* reg_sfdf_system_port
1235  * Port to flush.
1236  * Access: RW
1237  */
1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239 
1240 /* reg_sfdf_port_fid_system_port
1241  * Port to flush, pointed to by FID.
1242  * Access: RW
1243  */
1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245 
1246 /* reg_sfdf_lag_id
1247  * LAG ID to flush.
1248  * Access: RW
1249  */
1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251 
1252 /* reg_sfdf_lag_fid_lag_id
1253  * LAG ID to flush, pointed to by FID.
1254  * Access: RW
1255  */
1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257 
1258 /* SLDR - Switch LAG Descriptor Register
1259  * -----------------------------------------
1260  * The switch LAG descriptor register is populated by LAG descriptors.
1261  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1262  * max_lag-1.
1263  */
1264 #define MLXSW_REG_SLDR_ID 0x2014
1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1266 
1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268 
1269 enum mlxsw_reg_sldr_op {
1270 	/* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271 	MLXSW_REG_SLDR_OP_LAG_CREATE,
1272 	MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273 	/* Ports that appear in the list have the Distributor enabled */
1274 	MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275 	/* Removes ports from the disributor list */
1276 	MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277 };
1278 
1279 /* reg_sldr_op
1280  * Operation.
1281  * Access: RW
1282  */
1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284 
1285 /* reg_sldr_lag_id
1286  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1287  * Access: Index
1288  */
1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290 
1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292 {
1293 	MLXSW_REG_ZERO(sldr, payload);
1294 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296 }
1297 
1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299 {
1300 	MLXSW_REG_ZERO(sldr, payload);
1301 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303 }
1304 
1305 /* reg_sldr_num_ports
1306  * The number of member ports of the LAG.
1307  * Reserved for Create / Destroy operations
1308  * For Add / Remove operations - indicates the number of ports in the list.
1309  * Access: RW
1310  */
1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312 
1313 /* reg_sldr_system_port
1314  * System port.
1315  * Access: RW
1316  */
1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318 
1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320 						    u8 local_port)
1321 {
1322 	MLXSW_REG_ZERO(sldr, payload);
1323 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1326 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327 }
1328 
1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330 						       u8 local_port)
1331 {
1332 	MLXSW_REG_ZERO(sldr, payload);
1333 	mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334 	mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335 	mlxsw_reg_sldr_num_ports_set(payload, 1);
1336 	mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337 }
1338 
1339 /* SLCR - Switch LAG Configuration 2 Register
1340  * -------------------------------------------
1341  * The Switch LAG Configuration register is used for configuring the
1342  * LAG properties of the switch.
1343  */
1344 #define MLXSW_REG_SLCR_ID 0x2015
1345 #define MLXSW_REG_SLCR_LEN 0x10
1346 
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348 
1349 enum mlxsw_reg_slcr_pp {
1350 	/* Global Configuration (for all ports) */
1351 	MLXSW_REG_SLCR_PP_GLOBAL,
1352 	/* Per port configuration, based on local_port field */
1353 	MLXSW_REG_SLCR_PP_PER_PORT,
1354 };
1355 
1356 /* reg_slcr_pp
1357  * Per Port Configuration
1358  * Note: Reading at Global mode results in reading port 1 configuration.
1359  * Access: Index
1360  */
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362 
1363 /* reg_slcr_local_port
1364  * Local port number
1365  * Supported from CPU port
1366  * Not supported from router port
1367  * Reserved when pp = Global Configuration
1368  * Access: Index
1369  */
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371 
1372 enum mlxsw_reg_slcr_type {
1373 	MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374 	MLXSW_REG_SLCR_TYPE_XOR,
1375 	MLXSW_REG_SLCR_TYPE_RANDOM,
1376 };
1377 
1378 /* reg_slcr_type
1379  * Hash type
1380  * Access: RW
1381  */
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383 
1384 /* Ingress port */
1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT		BIT(0)
1386 /* SMAC - for IPv4 and IPv6 packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP		BIT(1)
1388 /* SMAC - for non-IP packets */
1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP	BIT(2)
1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391 	(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392 	 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393 /* DMAC - for IPv4 and IPv6 packets */
1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP		BIT(3)
1395 /* DMAC - for non-IP packets */
1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP	BIT(4)
1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398 	(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399 	 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400 /* Ethertype - for IPv4 and IPv6 packets */
1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP	BIT(5)
1402 /* Ethertype - for non-IP packets */
1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP	BIT(6)
1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405 	(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406 	 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407 /* VLAN ID - for IPv4 and IPv6 packets */
1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP	BIT(7)
1409 /* VLAN ID - for non-IP packets */
1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP	BIT(8)
1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412 	(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413 	 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414 /* Source IP address (can be IPv4 or IPv6) */
1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP		BIT(9)
1416 /* Destination IP address (can be IPv4 or IPv6) */
1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP		BIT(10)
1418 /* TCP/UDP source port */
1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT		BIT(11)
1420 /* TCP/UDP destination port*/
1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT		BIT(12)
1422 /* IPv4 Protocol/IPv6 Next Header */
1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO		BIT(13)
1424 /* IPv6 Flow label */
1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL	BIT(14)
1426 /* SID - FCoE source ID */
1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID	BIT(15)
1428 /* DID - FCoE destination ID */
1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID	BIT(16)
1430 /* OXID - FCoE originator exchange ID */
1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID	BIT(17)
1432 /* Destination QP number - for RoCE packets */
1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP	BIT(19)
1434 
1435 /* reg_slcr_lag_hash
1436  * LAG hashing configuration. This is a bitmask, in which each set
1437  * bit includes the corresponding item in the LAG hash calculation.
1438  * The default lag_hash contains SMAC, DMAC, VLANID and
1439  * Ethertype (for all packet types).
1440  * Access: RW
1441  */
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443 
1444 /* reg_slcr_seed
1445  * LAG seed value. The seed is the same for all ports.
1446  * Access: RW
1447  */
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449 
1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451 {
1452 	MLXSW_REG_ZERO(slcr, payload);
1453 	mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454 	mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455 	mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456 	mlxsw_reg_slcr_seed_set(payload, seed);
1457 }
1458 
1459 /* SLCOR - Switch LAG Collector Register
1460  * -------------------------------------
1461  * The Switch LAG Collector register controls the Local Port membership
1462  * in a LAG and enablement of the collector.
1463  */
1464 #define MLXSW_REG_SLCOR_ID 0x2016
1465 #define MLXSW_REG_SLCOR_LEN 0x10
1466 
1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468 
1469 enum mlxsw_reg_slcor_col {
1470 	/* Port is added with collector disabled */
1471 	MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473 	MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474 	MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475 };
1476 
1477 /* reg_slcor_col
1478  * Collector configuration
1479  * Access: RW
1480  */
1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482 
1483 /* reg_slcor_local_port
1484  * Local port number
1485  * Not supported for CPU port
1486  * Access: Index
1487  */
1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489 
1490 /* reg_slcor_lag_id
1491  * LAG Identifier. Index into the LAG descriptor table.
1492  * Access: Index
1493  */
1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495 
1496 /* reg_slcor_port_index
1497  * Port index in the LAG list. Only valid on Add Port to LAG col.
1498  * Valid range is from 0 to cap_max_lag_members-1
1499  * Access: RW
1500  */
1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502 
1503 static inline void mlxsw_reg_slcor_pack(char *payload,
1504 					u8 local_port, u16 lag_id,
1505 					enum mlxsw_reg_slcor_col col)
1506 {
1507 	MLXSW_REG_ZERO(slcor, payload);
1508 	mlxsw_reg_slcor_col_set(payload, col);
1509 	mlxsw_reg_slcor_local_port_set(payload, local_port);
1510 	mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511 }
1512 
1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514 						 u8 local_port, u16 lag_id,
1515 						 u8 port_index)
1516 {
1517 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518 			     MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519 	mlxsw_reg_slcor_port_index_set(payload, port_index);
1520 }
1521 
1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523 						    u8 local_port, u16 lag_id)
1524 {
1525 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526 			     MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527 }
1528 
1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530 						   u8 local_port, u16 lag_id)
1531 {
1532 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534 }
1535 
1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537 						    u8 local_port, u16 lag_id)
1538 {
1539 	mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540 			     MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541 }
1542 
1543 /* SPMLR - Switch Port MAC Learning Register
1544  * -----------------------------------------
1545  * Controls the Switch MAC learning policy per port.
1546  */
1547 #define MLXSW_REG_SPMLR_ID 0x2018
1548 #define MLXSW_REG_SPMLR_LEN 0x8
1549 
1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551 
1552 /* reg_spmlr_local_port
1553  * Local port number.
1554  * Access: Index
1555  */
1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557 
1558 /* reg_spmlr_sub_port
1559  * Virtual port within the physical port.
1560  * Should be set to 0 when virtual ports are not enabled on the port.
1561  * Access: Index
1562  */
1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564 
1565 enum mlxsw_reg_spmlr_learn_mode {
1566 	MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567 	MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568 	MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569 };
1570 
1571 /* reg_spmlr_learn_mode
1572  * Learning mode on the port.
1573  * 0 - Learning disabled.
1574  * 2 - Learning enabled.
1575  * 3 - Security mode.
1576  *
1577  * In security mode the switch does not learn MACs on the port, but uses the
1578  * SMAC to see if it exists on another ingress port. If so, the packet is
1579  * classified as a bad packet and is discarded unless the software registers
1580  * to receive port security error packets usign HPKT.
1581  */
1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583 
1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585 					enum mlxsw_reg_spmlr_learn_mode mode)
1586 {
1587 	MLXSW_REG_ZERO(spmlr, payload);
1588 	mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589 	mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590 	mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591 }
1592 
1593 /* SVFA - Switch VID to FID Allocation Register
1594  * --------------------------------------------
1595  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596  * virtualized ports.
1597  */
1598 #define MLXSW_REG_SVFA_ID 0x201C
1599 #define MLXSW_REG_SVFA_LEN 0x10
1600 
1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602 
1603 /* reg_svfa_swid
1604  * Switch partition ID.
1605  * Access: Index
1606  */
1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608 
1609 /* reg_svfa_local_port
1610  * Local port number.
1611  * Access: Index
1612  *
1613  * Note: Reserved for 802.1Q FIDs.
1614  */
1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616 
1617 enum mlxsw_reg_svfa_mt {
1618 	MLXSW_REG_SVFA_MT_VID_TO_FID,
1619 	MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620 };
1621 
1622 /* reg_svfa_mapping_table
1623  * Mapping table:
1624  * 0 - VID to FID
1625  * 1 - {Port, VID} to FID
1626  * Access: Index
1627  *
1628  * Note: Reserved for SwitchX-2.
1629  */
1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631 
1632 /* reg_svfa_v
1633  * Valid.
1634  * Valid if set.
1635  * Access: RW
1636  *
1637  * Note: Reserved for SwitchX-2.
1638  */
1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640 
1641 /* reg_svfa_fid
1642  * Filtering ID.
1643  * Access: RW
1644  */
1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646 
1647 /* reg_svfa_vid
1648  * VLAN ID.
1649  * Access: Index
1650  */
1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652 
1653 /* reg_svfa_counter_set_type
1654  * Counter set type for flow counters.
1655  * Access: RW
1656  *
1657  * Note: Reserved for SwitchX-2.
1658  */
1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660 
1661 /* reg_svfa_counter_index
1662  * Counter index for flow counters.
1663  * Access: RW
1664  *
1665  * Note: Reserved for SwitchX-2.
1666  */
1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668 
1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670 				       enum mlxsw_reg_svfa_mt mt, bool valid,
1671 				       u16 fid, u16 vid)
1672 {
1673 	MLXSW_REG_ZERO(svfa, payload);
1674 	local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675 	mlxsw_reg_svfa_swid_set(payload, 0);
1676 	mlxsw_reg_svfa_local_port_set(payload, local_port);
1677 	mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678 	mlxsw_reg_svfa_v_set(payload, valid);
1679 	mlxsw_reg_svfa_fid_set(payload, fid);
1680 	mlxsw_reg_svfa_vid_set(payload, vid);
1681 }
1682 
1683 /* SVPE - Switch Virtual-Port Enabling Register
1684  * --------------------------------------------
1685  * Enables port virtualization.
1686  */
1687 #define MLXSW_REG_SVPE_ID 0x201E
1688 #define MLXSW_REG_SVPE_LEN 0x4
1689 
1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691 
1692 /* reg_svpe_local_port
1693  * Local port number
1694  * Access: Index
1695  *
1696  * Note: CPU port is not supported (uses VLAN mode only).
1697  */
1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699 
1700 /* reg_svpe_vp_en
1701  * Virtual port enable.
1702  * 0 - Disable, VLAN mode (VID to FID).
1703  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1704  * Access: RW
1705  */
1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707 
1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709 				       bool enable)
1710 {
1711 	MLXSW_REG_ZERO(svpe, payload);
1712 	mlxsw_reg_svpe_local_port_set(payload, local_port);
1713 	mlxsw_reg_svpe_vp_en_set(payload, enable);
1714 }
1715 
1716 /* SFMR - Switch FID Management Register
1717  * -------------------------------------
1718  * Creates and configures FIDs.
1719  */
1720 #define MLXSW_REG_SFMR_ID 0x201F
1721 #define MLXSW_REG_SFMR_LEN 0x18
1722 
1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724 
1725 enum mlxsw_reg_sfmr_op {
1726 	MLXSW_REG_SFMR_OP_CREATE_FID,
1727 	MLXSW_REG_SFMR_OP_DESTROY_FID,
1728 };
1729 
1730 /* reg_sfmr_op
1731  * Operation.
1732  * 0 - Create or edit FID.
1733  * 1 - Destroy FID.
1734  * Access: WO
1735  */
1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737 
1738 /* reg_sfmr_fid
1739  * Filtering ID.
1740  * Access: Index
1741  */
1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743 
1744 /* reg_sfmr_fid_offset
1745  * FID offset.
1746  * Used to point into the flooding table selected by SFGC register if
1747  * the table is of type FID-Offset. Otherwise, this field is reserved.
1748  * Access: RW
1749  */
1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751 
1752 /* reg_sfmr_vtfp
1753  * Valid Tunnel Flood Pointer.
1754  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1755  * Access: RW
1756  *
1757  * Note: Reserved for 802.1Q FIDs.
1758  */
1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760 
1761 /* reg_sfmr_nve_tunnel_flood_ptr
1762  * Underlay Flooding and BC Pointer.
1763  * Used as a pointer to the first entry of the group based link lists of
1764  * flooding or BC entries (for NVE tunnels).
1765  * Access: RW
1766  */
1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768 
1769 /* reg_sfmr_vv
1770  * VNI Valid.
1771  * If not set, then vni is reserved.
1772  * Access: RW
1773  *
1774  * Note: Reserved for 802.1Q FIDs.
1775  */
1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777 
1778 /* reg_sfmr_vni
1779  * Virtual Network Identifier.
1780  * Access: RW
1781  *
1782  * Note: A given VNI can only be assigned to one FID.
1783  */
1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785 
1786 static inline void mlxsw_reg_sfmr_pack(char *payload,
1787 				       enum mlxsw_reg_sfmr_op op, u16 fid,
1788 				       u16 fid_offset)
1789 {
1790 	MLXSW_REG_ZERO(sfmr, payload);
1791 	mlxsw_reg_sfmr_op_set(payload, op);
1792 	mlxsw_reg_sfmr_fid_set(payload, fid);
1793 	mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794 	mlxsw_reg_sfmr_vtfp_set(payload, false);
1795 	mlxsw_reg_sfmr_vv_set(payload, false);
1796 }
1797 
1798 /* SPVMLR - Switch Port VLAN MAC Learning Register
1799  * -----------------------------------------------
1800  * Controls the switch MAC learning policy per {Port, VID}.
1801  */
1802 #define MLXSW_REG_SPVMLR_ID 0x2020
1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807 			      MLXSW_REG_SPVMLR_REC_LEN * \
1808 			      MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809 
1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811 
1812 /* reg_spvmlr_local_port
1813  * Local ingress port.
1814  * Access: Index
1815  *
1816  * Note: CPU port is not supported.
1817  */
1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819 
1820 /* reg_spvmlr_num_rec
1821  * Number of records to update.
1822  * Access: OP
1823  */
1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825 
1826 /* reg_spvmlr_rec_learn_enable
1827  * 0 - Disable learning for {Port, VID}.
1828  * 1 - Enable learning for {Port, VID}.
1829  * Access: RW
1830  */
1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832 		     31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833 
1834 /* reg_spvmlr_rec_vid
1835  * VLAN ID to be added/removed from port or for querying.
1836  * Access: Index
1837  */
1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839 		     MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840 
1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842 					 u16 vid_begin, u16 vid_end,
1843 					 bool learn_enable)
1844 {
1845 	int num_rec = vid_end - vid_begin + 1;
1846 	int i;
1847 
1848 	WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849 
1850 	MLXSW_REG_ZERO(spvmlr, payload);
1851 	mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852 	mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853 
1854 	for (i = 0; i < num_rec; i++) {
1855 		mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856 		mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857 	}
1858 }
1859 
1860 /* CWTP - Congetion WRED ECN TClass Profile
1861  * ----------------------------------------
1862  * Configures the profiles for queues of egress port and traffic class
1863  */
1864 #define MLXSW_REG_CWTP_ID 0x2802
1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867 #define MLXSW_REG_CWTP_LEN 0x40
1868 
1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870 
1871 /* reg_cwtp_local_port
1872  * Local port number
1873  * Not supported for CPU port
1874  * Access: Index
1875  */
1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877 
1878 /* reg_cwtp_traffic_class
1879  * Traffic Class to configure
1880  * Access: Index
1881  */
1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883 
1884 /* reg_cwtp_profile_min
1885  * Minimum Average Queue Size of the profile in cells.
1886  * Access: RW
1887  */
1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890 
1891 /* reg_cwtp_profile_percent
1892  * Percentage of WRED and ECN marking for maximum Average Queue size
1893  * Range is 0 to 100, units of integer percentage
1894  * Access: RW
1895  */
1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897 		     24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898 
1899 /* reg_cwtp_profile_max
1900  * Maximum Average Queue size of the profile in cells
1901  * Access: RW
1902  */
1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904 		     0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905 
1906 #define MLXSW_REG_CWTP_MIN_VALUE 64
1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909 
1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911 				       u8 traffic_class)
1912 {
1913 	int i;
1914 
1915 	MLXSW_REG_ZERO(cwtp, payload);
1916 	mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917 	mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918 
1919 	for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920 		mlxsw_reg_cwtp_profile_min_set(payload, i,
1921 					       MLXSW_REG_CWTP_MIN_VALUE);
1922 		mlxsw_reg_cwtp_profile_max_set(payload, i,
1923 					       MLXSW_REG_CWTP_MIN_VALUE);
1924 	}
1925 }
1926 
1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928 
1929 static inline void
1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931 			    u32 probability)
1932 {
1933 	u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934 
1935 	mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936 	mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937 	mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938 }
1939 
1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941  * ---------------------------------------------------
1942  * The CWTPM register maps each egress port and traffic class to profile num.
1943  */
1944 #define MLXSW_REG_CWTPM_ID 0x2803
1945 #define MLXSW_REG_CWTPM_LEN 0x44
1946 
1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948 
1949 /* reg_cwtpm_local_port
1950  * Local port number
1951  * Not supported for CPU port
1952  * Access: Index
1953  */
1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955 
1956 /* reg_cwtpm_traffic_class
1957  * Traffic Class to configure
1958  * Access: Index
1959  */
1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961 
1962 /* reg_cwtpm_ew
1963  * Control enablement of WRED for traffic class:
1964  * 0 - Disable
1965  * 1 - Enable
1966  * Access: RW
1967  */
1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969 
1970 /* reg_cwtpm_ee
1971  * Control enablement of ECN for traffic class:
1972  * 0 - Disable
1973  * 1 - Enable
1974  * Access: RW
1975  */
1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977 
1978 /* reg_cwtpm_tcp_g
1979  * TCP Green Profile.
1980  * Index of the profile within {port, traffic class} to use.
1981  * 0 for disabling both WRED and ECN for this type of traffic.
1982  * Access: RW
1983  */
1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985 
1986 /* reg_cwtpm_tcp_y
1987  * TCP Yellow Profile.
1988  * Index of the profile within {port, traffic class} to use.
1989  * 0 for disabling both WRED and ECN for this type of traffic.
1990  * Access: RW
1991  */
1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993 
1994 /* reg_cwtpm_tcp_r
1995  * TCP Red Profile.
1996  * Index of the profile within {port, traffic class} to use.
1997  * 0 for disabling both WRED and ECN for this type of traffic.
1998  * Access: RW
1999  */
2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001 
2002 /* reg_cwtpm_ntcp_g
2003  * Non-TCP Green Profile.
2004  * Index of the profile within {port, traffic class} to use.
2005  * 0 for disabling both WRED and ECN for this type of traffic.
2006  * Access: RW
2007  */
2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009 
2010 /* reg_cwtpm_ntcp_y
2011  * Non-TCP Yellow Profile.
2012  * Index of the profile within {port, traffic class} to use.
2013  * 0 for disabling both WRED and ECN for this type of traffic.
2014  * Access: RW
2015  */
2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017 
2018 /* reg_cwtpm_ntcp_r
2019  * Non-TCP Red Profile.
2020  * Index of the profile within {port, traffic class} to use.
2021  * 0 for disabling both WRED and ECN for this type of traffic.
2022  * Access: RW
2023  */
2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025 
2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027 
2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029 					u8 traffic_class, u8 profile,
2030 					bool wred, bool ecn)
2031 {
2032 	MLXSW_REG_ZERO(cwtpm, payload);
2033 	mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034 	mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035 	mlxsw_reg_cwtpm_ew_set(payload, wred);
2036 	mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037 	mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038 	mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039 	mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040 	mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041 	mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042 	mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043 }
2044 
2045 /* PGCR - Policy-Engine General Configuration Register
2046  * ---------------------------------------------------
2047  * This register configures general Policy-Engine settings.
2048  */
2049 #define MLXSW_REG_PGCR_ID 0x3001
2050 #define MLXSW_REG_PGCR_LEN 0x20
2051 
2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053 
2054 /* reg_pgcr_default_action_pointer_base
2055  * Default action pointer base. Each region has a default action pointer
2056  * which is equal to default_action_pointer_base + region_id.
2057  * Access: RW
2058  */
2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060 
2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062 {
2063 	MLXSW_REG_ZERO(pgcr, payload);
2064 	mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065 }
2066 
2067 /* PPBT - Policy-Engine Port Binding Table
2068  * ---------------------------------------
2069  * This register is used for configuration of the Port Binding Table.
2070  */
2071 #define MLXSW_REG_PPBT_ID 0x3002
2072 #define MLXSW_REG_PPBT_LEN 0x14
2073 
2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075 
2076 enum mlxsw_reg_pxbt_e {
2077 	MLXSW_REG_PXBT_E_IACL,
2078 	MLXSW_REG_PXBT_E_EACL,
2079 };
2080 
2081 /* reg_ppbt_e
2082  * Access: Index
2083  */
2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085 
2086 enum mlxsw_reg_pxbt_op {
2087 	MLXSW_REG_PXBT_OP_BIND,
2088 	MLXSW_REG_PXBT_OP_UNBIND,
2089 };
2090 
2091 /* reg_ppbt_op
2092  * Access: RW
2093  */
2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095 
2096 /* reg_ppbt_local_port
2097  * Local port. Not including CPU port.
2098  * Access: Index
2099  */
2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101 
2102 /* reg_ppbt_g
2103  * group - When set, the binding is of an ACL group. When cleared,
2104  * the binding is of an ACL.
2105  * Must be set to 1 for Spectrum.
2106  * Access: RW
2107  */
2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109 
2110 /* reg_ppbt_acl_info
2111  * ACL/ACL group identifier. If the g bit is set, this field should hold
2112  * the acl_group_id, else it should hold the acl_id.
2113  * Access: RW
2114  */
2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116 
2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118 				       enum mlxsw_reg_pxbt_op op,
2119 				       u8 local_port, u16 acl_info)
2120 {
2121 	MLXSW_REG_ZERO(ppbt, payload);
2122 	mlxsw_reg_ppbt_e_set(payload, e);
2123 	mlxsw_reg_ppbt_op_set(payload, op);
2124 	mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125 	mlxsw_reg_ppbt_g_set(payload, true);
2126 	mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127 }
2128 
2129 /* PACL - Policy-Engine ACL Register
2130  * ---------------------------------
2131  * This register is used for configuration of the ACL.
2132  */
2133 #define MLXSW_REG_PACL_ID 0x3004
2134 #define MLXSW_REG_PACL_LEN 0x70
2135 
2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137 
2138 /* reg_pacl_v
2139  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140  * while the ACL is bounded to either a port, VLAN or ACL rule.
2141  * Access: RW
2142  */
2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144 
2145 /* reg_pacl_acl_id
2146  * An identifier representing the ACL (managed by software)
2147  * Range 0 .. cap_max_acl_regions - 1
2148  * Access: Index
2149  */
2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151 
2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153 
2154 /* reg_pacl_tcam_region_info
2155  * Opaque object that represents a TCAM region.
2156  * Obtained through PTAR register.
2157  * Access: RW
2158  */
2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161 
2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163 				       bool valid, const char *tcam_region_info)
2164 {
2165 	MLXSW_REG_ZERO(pacl, payload);
2166 	mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167 	mlxsw_reg_pacl_v_set(payload, valid);
2168 	mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169 }
2170 
2171 /* PAGT - Policy-Engine ACL Group Table
2172  * ------------------------------------
2173  * This register is used for configuration of the ACL Group Table.
2174  */
2175 #define MLXSW_REG_PAGT_ID 0x3005
2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2177 #define MLXSW_REG_PAGT_ACL_LEN 4
2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180 		MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181 
2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183 
2184 /* reg_pagt_size
2185  * Number of ACLs in the group.
2186  * Size 0 invalidates a group.
2187  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188  * Total number of ACLs in all groups must be lower or equal
2189  * to cap_max_acl_tot_groups
2190  * Note: a group which is binded must not be invalidated
2191  * Access: Index
2192  */
2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194 
2195 /* reg_pagt_acl_group_id
2196  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197  * the ACL Group identifier (managed by software).
2198  * Access: Index
2199  */
2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201 
2202 /* reg_pagt_multi
2203  * Multi-ACL
2204  * 0 - This ACL is the last ACL in the multi-ACL
2205  * 1 - This ACL is part of a multi-ACL
2206  * Access: RW
2207  */
2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209 
2210 /* reg_pagt_acl_id
2211  * ACL identifier
2212  * Access: RW
2213  */
2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215 
2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217 {
2218 	MLXSW_REG_ZERO(pagt, payload);
2219 	mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220 }
2221 
2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223 					      u16 acl_id, bool multi)
2224 {
2225 	u8 size = mlxsw_reg_pagt_size_get(payload);
2226 
2227 	if (index >= size)
2228 		mlxsw_reg_pagt_size_set(payload, index + 1);
2229 	mlxsw_reg_pagt_multi_set(payload, index, multi);
2230 	mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231 }
2232 
2233 /* PTAR - Policy-Engine TCAM Allocation Register
2234  * ---------------------------------------------
2235  * This register is used for allocation of regions in the TCAM.
2236  * Note: Query method is not supported on this register.
2237  */
2238 #define MLXSW_REG_PTAR_ID 0x3006
2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243 		MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244 
2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246 
2247 enum mlxsw_reg_ptar_op {
2248 	/* allocate a TCAM region */
2249 	MLXSW_REG_PTAR_OP_ALLOC,
2250 	/* resize a TCAM region */
2251 	MLXSW_REG_PTAR_OP_RESIZE,
2252 	/* deallocate TCAM region */
2253 	MLXSW_REG_PTAR_OP_FREE,
2254 	/* test allocation */
2255 	MLXSW_REG_PTAR_OP_TEST,
2256 };
2257 
2258 /* reg_ptar_op
2259  * Access: OP
2260  */
2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262 
2263 /* reg_ptar_action_set_type
2264  * Type of action set to be used on this region.
2265  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2266  * Access: WO
2267  */
2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269 
2270 enum mlxsw_reg_ptar_key_type {
2271 	MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272 	MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2273 };
2274 
2275 /* reg_ptar_key_type
2276  * TCAM key type for the region.
2277  * Access: WO
2278  */
2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280 
2281 /* reg_ptar_region_size
2282  * TCAM region size. When allocating/resizing this is the requested size,
2283  * the response is the actual size. Note that actual size may be
2284  * larger than requested.
2285  * Allowed range 1 .. cap_max_rules-1
2286  * Reserved during op deallocate.
2287  * Access: WO
2288  */
2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290 
2291 /* reg_ptar_region_id
2292  * Region identifier
2293  * Range 0 .. cap_max_regions-1
2294  * Access: Index
2295  */
2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297 
2298 /* reg_ptar_tcam_region_info
2299  * Opaque object that represents the TCAM region.
2300  * Returned when allocating a region.
2301  * Provided by software for ACL generation and region deallocation and resize.
2302  * Access: RW
2303  */
2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306 
2307 /* reg_ptar_flexible_key_id
2308  * Identifier of the Flexible Key.
2309  * Only valid if key_type == "FLEX_KEY"
2310  * The key size will be rounded up to one of the following values:
2311  * 9B, 18B, 36B, 54B.
2312  * This field is reserved for in resize operation.
2313  * Access: WO
2314  */
2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316 		    MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317 
2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319 				       enum mlxsw_reg_ptar_key_type key_type,
2320 				       u16 region_size, u16 region_id,
2321 				       const char *tcam_region_info)
2322 {
2323 	MLXSW_REG_ZERO(ptar, payload);
2324 	mlxsw_reg_ptar_op_set(payload, op);
2325 	mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326 	mlxsw_reg_ptar_key_type_set(payload, key_type);
2327 	mlxsw_reg_ptar_region_size_set(payload, region_size);
2328 	mlxsw_reg_ptar_region_id_set(payload, region_id);
2329 	mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330 }
2331 
2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333 					      u16 key_id)
2334 {
2335 	mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336 }
2337 
2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339 {
2340 	mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341 }
2342 
2343 /* PPBS - Policy-Engine Policy Based Switching Register
2344  * ----------------------------------------------------
2345  * This register retrieves and sets Policy Based Switching Table entries.
2346  */
2347 #define MLXSW_REG_PPBS_ID 0x300C
2348 #define MLXSW_REG_PPBS_LEN 0x14
2349 
2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351 
2352 /* reg_ppbs_pbs_ptr
2353  * Index into the PBS table.
2354  * For Spectrum, the index points to the KVD Linear.
2355  * Access: Index
2356  */
2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358 
2359 /* reg_ppbs_system_port
2360  * Unique port identifier for the final destination of the packet.
2361  * Access: RW
2362  */
2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364 
2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366 				       u16 system_port)
2367 {
2368 	MLXSW_REG_ZERO(ppbs, payload);
2369 	mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370 	mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371 }
2372 
2373 /* PRCR - Policy-Engine Rules Copy Register
2374  * ----------------------------------------
2375  * This register is used for accessing rules within a TCAM region.
2376  */
2377 #define MLXSW_REG_PRCR_ID 0x300D
2378 #define MLXSW_REG_PRCR_LEN 0x40
2379 
2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381 
2382 enum mlxsw_reg_prcr_op {
2383 	/* Move rules. Moves the rules from "tcam_region_info" starting
2384 	 * at offset "offset" to "dest_tcam_region_info"
2385 	 * at offset "dest_offset."
2386 	 */
2387 	MLXSW_REG_PRCR_OP_MOVE,
2388 	/* Copy rules. Copies the rules from "tcam_region_info" starting
2389 	 * at offset "offset" to "dest_tcam_region_info"
2390 	 * at offset "dest_offset."
2391 	 */
2392 	MLXSW_REG_PRCR_OP_COPY,
2393 };
2394 
2395 /* reg_prcr_op
2396  * Access: OP
2397  */
2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399 
2400 /* reg_prcr_offset
2401  * Offset within the source region to copy/move from.
2402  * Access: Index
2403  */
2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405 
2406 /* reg_prcr_size
2407  * The number of rules to copy/move.
2408  * Access: WO
2409  */
2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411 
2412 /* reg_prcr_tcam_region_info
2413  * Opaque object that represents the source TCAM region.
2414  * Access: Index
2415  */
2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418 
2419 /* reg_prcr_dest_offset
2420  * Offset within the source region to copy/move to.
2421  * Access: Index
2422  */
2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424 
2425 /* reg_prcr_dest_tcam_region_info
2426  * Opaque object that represents the destination TCAM region.
2427  * Access: Index
2428  */
2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431 
2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433 				       const char *src_tcam_region_info,
2434 				       u16 src_offset,
2435 				       const char *dest_tcam_region_info,
2436 				       u16 dest_offset, u16 size)
2437 {
2438 	MLXSW_REG_ZERO(prcr, payload);
2439 	mlxsw_reg_prcr_op_set(payload, op);
2440 	mlxsw_reg_prcr_offset_set(payload, src_offset);
2441 	mlxsw_reg_prcr_size_set(payload, size);
2442 	mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443 						  src_tcam_region_info);
2444 	mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445 	mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446 						       dest_tcam_region_info);
2447 }
2448 
2449 /* PEFA - Policy-Engine Extended Flexible Action Register
2450  * ------------------------------------------------------
2451  * This register is used for accessing an extended flexible action entry
2452  * in the central KVD Linear Database.
2453  */
2454 #define MLXSW_REG_PEFA_ID 0x300F
2455 #define MLXSW_REG_PEFA_LEN 0xB0
2456 
2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458 
2459 /* reg_pefa_index
2460  * Index in the KVD Linear Centralized Database.
2461  * Access: Index
2462  */
2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464 
2465 /* reg_pefa_a
2466  * Index in the KVD Linear Centralized Database.
2467  * Activity
2468  * For a new entry: set if ca=0, clear if ca=1
2469  * Set if a packet lookup has hit on the specific entry
2470  * Access: RO
2471  */
2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473 
2474 /* reg_pefa_ca
2475  * Clear activity
2476  * When write: activity is according to this field
2477  * When read: after reading the activity is cleared according to ca
2478  * Access: OP
2479  */
2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481 
2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483 
2484 /* reg_pefa_flex_action_set
2485  * Action-set to perform when rule is matched.
2486  * Must be zero padded if action set is shorter.
2487  * Access: RW
2488  */
2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490 
2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492 				       const char *flex_action_set)
2493 {
2494 	MLXSW_REG_ZERO(pefa, payload);
2495 	mlxsw_reg_pefa_index_set(payload, index);
2496 	mlxsw_reg_pefa_ca_set(payload, ca);
2497 	if (flex_action_set)
2498 		mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499 							 flex_action_set);
2500 }
2501 
2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503 {
2504 	*p_a = mlxsw_reg_pefa_a_get(payload);
2505 }
2506 
2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508  * --------------------------------------------------------------
2509  * This register is used for binding Multicast router to an ACL group
2510  * that serves the MC router.
2511  * This register is not supported by SwitchX/-2 and Spectrum.
2512  */
2513 #define MLXSW_REG_PEMRBT_ID 0x3014
2514 #define MLXSW_REG_PEMRBT_LEN 0x14
2515 
2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517 
2518 enum mlxsw_reg_pemrbt_protocol {
2519 	MLXSW_REG_PEMRBT_PROTO_IPV4,
2520 	MLXSW_REG_PEMRBT_PROTO_IPV6,
2521 };
2522 
2523 /* reg_pemrbt_protocol
2524  * Access: Index
2525  */
2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527 
2528 /* reg_pemrbt_group_id
2529  * ACL group identifier.
2530  * Range 0..cap_max_acl_groups-1
2531  * Access: RW
2532  */
2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534 
2535 static inline void
2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537 		      u16 group_id)
2538 {
2539 	MLXSW_REG_ZERO(pemrbt, payload);
2540 	mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541 	mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542 }
2543 
2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545  * -----------------------------------------------------
2546  * This register is used for accessing rules within a TCAM region.
2547  * It is a new version of PTCE in order to support wider key,
2548  * mask and action within a TCAM region. This register is not supported
2549  * by SwitchX and SwitchX-2.
2550  */
2551 #define MLXSW_REG_PTCE2_ID 0x3017
2552 #define MLXSW_REG_PTCE2_LEN 0x1D8
2553 
2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555 
2556 /* reg_ptce2_v
2557  * Valid.
2558  * Access: RW
2559  */
2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561 
2562 /* reg_ptce2_a
2563  * Activity. Set if a packet lookup has hit on the specific entry.
2564  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2565  * Access: RO
2566  */
2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568 
2569 enum mlxsw_reg_ptce2_op {
2570 	/* Read operation. */
2571 	MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572 	/* clear on read operation. Used to read entry
2573 	 * and clear Activity bit.
2574 	 */
2575 	MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576 	/* Write operation. Used to write a new entry to the table.
2577 	 * All R/W fields are relevant for new entry. Activity bit is set
2578 	 * for new entries - Note write with v = 0 will delete the entry.
2579 	 */
2580 	MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581 	/* Update action. Only action set will be updated. */
2582 	MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583 	/* Clear activity. A bit is cleared for the entry. */
2584 	MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585 };
2586 
2587 /* reg_ptce2_op
2588  * Access: OP
2589  */
2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591 
2592 /* reg_ptce2_offset
2593  * Access: Index
2594  */
2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596 
2597 /* reg_ptce2_priority
2598  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599  * Note: priority does not have to be unique per rule.
2600  * Within a region, higher priority should have lower offset (no limitation
2601  * between regions in a multi-region).
2602  * Access: RW
2603  */
2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605 
2606 /* reg_ptce2_tcam_region_info
2607  * Opaque object that represents the TCAM region.
2608  * Access: Index
2609  */
2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612 
2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614 
2615 /* reg_ptce2_flex_key_blocks
2616  * ACL Key.
2617  * Access: RW
2618  */
2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621 
2622 /* reg_ptce2_mask
2623  * mask- in the same size as key. A bit that is set directs the TCAM
2624  * to compare the corresponding bit in key. A bit that is clear directs
2625  * the TCAM to ignore the corresponding bit in key.
2626  * Access: RW
2627  */
2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630 
2631 /* reg_ptce2_flex_action_set
2632  * ACL action set.
2633  * Access: RW
2634  */
2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
2637 
2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639 					enum mlxsw_reg_ptce2_op op,
2640 					const char *tcam_region_info,
2641 					u16 offset, u32 priority)
2642 {
2643 	MLXSW_REG_ZERO(ptce2, payload);
2644 	mlxsw_reg_ptce2_v_set(payload, valid);
2645 	mlxsw_reg_ptce2_op_set(payload, op);
2646 	mlxsw_reg_ptce2_offset_set(payload, offset);
2647 	mlxsw_reg_ptce2_priority_set(payload, priority);
2648 	mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649 }
2650 
2651 /* PERPT - Policy-Engine ERP Table Register
2652  * ----------------------------------------
2653  * This register adds and removes eRPs from the eRP table.
2654  */
2655 #define MLXSW_REG_PERPT_ID 0x3021
2656 #define MLXSW_REG_PERPT_LEN 0x80
2657 
2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659 
2660 /* reg_perpt_erpt_bank
2661  * eRP table bank.
2662  * Range 0 .. cap_max_erp_table_banks - 1
2663  * Access: Index
2664  */
2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666 
2667 /* reg_perpt_erpt_index
2668  * Index to eRP table within the eRP bank.
2669  * Range is 0 .. cap_max_erp_table_bank_size - 1
2670  * Access: Index
2671  */
2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673 
2674 enum mlxsw_reg_perpt_key_size {
2675 	MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676 	MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677 	MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678 	MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679 };
2680 
2681 /* reg_perpt_key_size
2682  * Access: OP
2683  */
2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685 
2686 /* reg_perpt_bf_bypass
2687  * 0 - The eRP is used only if bloom filter state is set for the given
2688  * rule.
2689  * 1 - The eRP is used regardless of bloom filter state.
2690  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2691  * Access: RW
2692  */
2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694 
2695 /* reg_perpt_erp_id
2696  * eRP ID for use by the rules.
2697  * Access: RW
2698  */
2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700 
2701 /* reg_perpt_erpt_base_bank
2702  * Base eRP table bank, points to head of erp_vector
2703  * Range is 0 .. cap_max_erp_table_banks - 1
2704  * Access: OP
2705  */
2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707 
2708 /* reg_perpt_erpt_base_index
2709  * Base index to eRP table within the eRP bank
2710  * Range is 0 .. cap_max_erp_table_bank_size - 1
2711  * Access: OP
2712  */
2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714 
2715 /* reg_perpt_erp_index_in_vector
2716  * eRP index in the vector.
2717  * Access: OP
2718  */
2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720 
2721 /* reg_perpt_erp_vector
2722  * eRP vector.
2723  * Access: OP
2724  */
2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726 
2727 /* reg_perpt_mask
2728  * Mask
2729  * 0 - A-TCAM will ignore the bit in key
2730  * 1 - A-TCAM will compare the bit in key
2731  * Access: RW
2732  */
2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734 
2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736 						   unsigned long *erp_vector,
2737 						   unsigned long size)
2738 {
2739 	unsigned long bit;
2740 
2741 	for_each_set_bit(bit, erp_vector, size)
2742 		mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743 }
2744 
2745 static inline void
2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747 		     enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748 		     u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749 		     char *mask)
2750 {
2751 	MLXSW_REG_ZERO(perpt, payload);
2752 	mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753 	mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754 	mlxsw_reg_perpt_key_size_set(payload, key_size);
2755 	mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756 	mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757 	mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758 	mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759 	mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760 	mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761 }
2762 
2763 /* PERAR - Policy-Engine Region Association Register
2764  * -------------------------------------------------
2765  * This register associates a hw region for region_id's. Changing on the fly
2766  * is supported by the device.
2767  */
2768 #define MLXSW_REG_PERAR_ID 0x3026
2769 #define MLXSW_REG_PERAR_LEN 0x08
2770 
2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772 
2773 /* reg_perar_region_id
2774  * Region identifier
2775  * Range 0 .. cap_max_regions-1
2776  * Access: Index
2777  */
2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779 
2780 static inline unsigned int
2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782 {
2783 	return DIV_ROUND_UP(block_num, 4);
2784 }
2785 
2786 /* reg_perar_hw_region
2787  * HW Region
2788  * Range 0 .. cap_max_regions-1
2789  * Default: hw_region = region_id
2790  * For a 8 key block region, 2 consecutive regions are used
2791  * For a 12 key block region, 3 consecutive regions are used
2792  * Access: RW
2793  */
2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795 
2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797 					u16 hw_region)
2798 {
2799 	MLXSW_REG_ZERO(perar, payload);
2800 	mlxsw_reg_perar_region_id_set(payload, region_id);
2801 	mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802 }
2803 
2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805  * -----------------------------------------------------
2806  * This register is a new version of PTCE-V2 in order to support the
2807  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2808  */
2809 #define MLXSW_REG_PTCE3_ID 0x3027
2810 #define MLXSW_REG_PTCE3_LEN 0xF0
2811 
2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813 
2814 /* reg_ptce3_v
2815  * Valid.
2816  * Access: RW
2817  */
2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819 
2820 enum mlxsw_reg_ptce3_op {
2821 	/* Write operation. Used to write a new entry to the table.
2822 	 * All R/W fields are relevant for new entry. Activity bit is set
2823 	 * for new entries. Write with v = 0 will delete the entry. Must
2824 	 * not be used if an entry exists.
2825 	 */
2826 	 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827 	 /* Update operation */
2828 	 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829 	 /* Read operation */
2830 	 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831 };
2832 
2833 /* reg_ptce3_op
2834  * Access: OP
2835  */
2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837 
2838 /* reg_ptce3_priority
2839  * Priority of the rule. Higher values win.
2840  * For Spectrum-2 range is 1..cap_kvd_size - 1
2841  * Note: Priority does not have to be unique per rule.
2842  * Access: RW
2843  */
2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845 
2846 /* reg_ptce3_tcam_region_info
2847  * Opaque object that represents the TCAM region.
2848  * Access: Index
2849  */
2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851 	       MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852 
2853 /* reg_ptce3_flex2_key_blocks
2854  * ACL key. The key must be masked according to eRP (if exists) or
2855  * according to master mask.
2856  * Access: Index
2857  */
2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859 	       MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860 
2861 /* reg_ptce3_erp_id
2862  * eRP ID.
2863  * Access: Index
2864  */
2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866 
2867 /* reg_ptce3_delta_start
2868  * Start point of delta_value and delta_mask, in bits. Must not exceed
2869  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2870  * Access: Index
2871  */
2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873 
2874 /* reg_ptce3_delta_mask
2875  * Delta mask.
2876  * 0 - Ignore relevant bit in delta_value
2877  * 1 - Compare relevant bit in delta_value
2878  * Delta mask must not be set for reserved fields in the key blocks.
2879  * Note: No delta when no eRPs. Thus, for regions with
2880  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2881  * Access: Index
2882  */
2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884 
2885 /* reg_ptce3_delta_value
2886  * Delta value.
2887  * Bits which are masked by delta_mask must be 0.
2888  * Access: Index
2889  */
2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891 
2892 /* reg_ptce3_prune_vector
2893  * Pruning vector relative to the PERPT.erp_id.
2894  * Used for reducing lookups.
2895  * 0 - NEED: Do a lookup using the eRP.
2896  * 1 - PRUNE: Do not perform a lookup using the eRP.
2897  * Maybe be modified by PEAPBL and PEAPBM.
2898  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899  * all 1's or all 0's.
2900  * Access: RW
2901  */
2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903 
2904 /* reg_ptce3_prune_ctcam
2905  * Pruning on C-TCAM. Used for reducing lookups.
2906  * 0 - NEED: Do a lookup in the C-TCAM.
2907  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2908  * Access: RW
2909  */
2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911 
2912 /* reg_ptce3_large_exists
2913  * Large entry key ID exists.
2914  * Within the region:
2915  * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916  * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917  * For rule delete: The MSB of the key will be removed.
2918  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920  * For rule delete: The MSB of the key will not be removed.
2921  * Access: WO
2922  */
2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924 
2925 /* reg_ptce3_large_entry_key_id
2926  * Large entry key ID.
2927  * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928  * blocks. Must be different for different keys which have the same common
2929  * 6 key blocks (MSB, blocks 6..11) key within a region.
2930  * Range is 0..cap_max_pe_large_key_id - 1
2931  * Access: RW
2932  */
2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934 
2935 /* reg_ptce3_action_pointer
2936  * Pointer to action.
2937  * Range is 0..cap_max_kvd_action_sets - 1
2938  * Access: RW
2939  */
2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941 
2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943 					enum mlxsw_reg_ptce3_op op,
2944 					u32 priority,
2945 					const char *tcam_region_info,
2946 					const char *key, u8 erp_id,
2947 					u16 delta_start, u8 delta_mask,
2948 					u8 delta_value, bool large_exists,
2949 					u32 lkey_id, u32 action_pointer)
2950 {
2951 	MLXSW_REG_ZERO(ptce3, payload);
2952 	mlxsw_reg_ptce3_v_set(payload, valid);
2953 	mlxsw_reg_ptce3_op_set(payload, op);
2954 	mlxsw_reg_ptce3_priority_set(payload, priority);
2955 	mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956 	mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957 	mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958 	mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959 	mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960 	mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961 	mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962 	mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963 	mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964 }
2965 
2966 /* PERCR - Policy-Engine Region Configuration Register
2967  * ---------------------------------------------------
2968  * This register configures the region parameters. The region_id must be
2969  * allocated.
2970  */
2971 #define MLXSW_REG_PERCR_ID 0x302A
2972 #define MLXSW_REG_PERCR_LEN 0x80
2973 
2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975 
2976 /* reg_percr_region_id
2977  * Region identifier.
2978  * Range 0..cap_max_regions-1
2979  * Access: Index
2980  */
2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982 
2983 /* reg_percr_atcam_ignore_prune
2984  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2985  * Access: RW
2986  */
2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988 
2989 /* reg_percr_ctcam_ignore_prune
2990  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2991  * Access: RW
2992  */
2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994 
2995 /* reg_percr_bf_bypass
2996  * Bloom filter bypass.
2997  * 0 - Bloom filter is used (default)
2998  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999  * region_id or eRP. See PERPT.bf_bypass
3000  * Access: RW
3001  */
3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003 
3004 /* reg_percr_master_mask
3005  * Master mask. Logical OR mask of all masks of all rules of a region
3006  * (both A-TCAM and C-TCAM). When there are no eRPs
3007  * (erpt_pointer_valid = 0), then this provides the mask.
3008  * Access: RW
3009  */
3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011 
3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013 {
3014 	MLXSW_REG_ZERO(percr, payload);
3015 	mlxsw_reg_percr_region_id_set(payload, region_id);
3016 	mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017 	mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018 	mlxsw_reg_percr_bf_bypass_set(payload, false);
3019 }
3020 
3021 /* PERERP - Policy-Engine Region eRP Register
3022  * ------------------------------------------
3023  * This register configures the region eRP. The region_id must be
3024  * allocated.
3025  */
3026 #define MLXSW_REG_PERERP_ID 0x302B
3027 #define MLXSW_REG_PERERP_LEN 0x1C
3028 
3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030 
3031 /* reg_pererp_region_id
3032  * Region identifier.
3033  * Range 0..cap_max_regions-1
3034  * Access: Index
3035  */
3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037 
3038 /* reg_pererp_ctcam_le
3039  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3040  * Access: RW
3041  */
3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043 
3044 /* reg_pererp_erpt_pointer_valid
3045  * erpt_pointer is valid.
3046  * Access: RW
3047  */
3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049 
3050 /* reg_pererp_erpt_bank_pointer
3051  * Pointer to eRP table bank. May be modified at any time.
3052  * Range 0..cap_max_erp_table_banks-1
3053  * Reserved when erpt_pointer_valid = 0
3054  */
3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056 
3057 /* reg_pererp_erpt_pointer
3058  * Pointer to eRP table within the eRP bank. Can be changed for an
3059  * existing region.
3060  * Range 0..cap_max_erp_table_size-1
3061  * Reserved when erpt_pointer_valid = 0
3062  * Access: RW
3063  */
3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065 
3066 /* reg_pererp_erpt_vector
3067  * Vector of allowed eRP indexes starting from erpt_pointer within the
3068  * erpt_bank_pointer. Next entries will be in next bank.
3069  * Note that eRP index is used and not eRP ID.
3070  * Reserved when erpt_pointer_valid = 0
3071  * Access: RW
3072  */
3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074 
3075 /* reg_pererp_master_rp_id
3076  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077  * for the lookup. Can be changed for an existing region.
3078  * Reserved when erpt_pointer_valid = 1
3079  * Access: RW
3080  */
3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082 
3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084 						    unsigned long *erp_vector,
3085 						    unsigned long size)
3086 {
3087 	unsigned long bit;
3088 
3089 	for_each_set_bit(bit, erp_vector, size)
3090 		mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091 }
3092 
3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094 					 bool ctcam_le, bool erpt_pointer_valid,
3095 					 u8 erpt_bank_pointer, u8 erpt_pointer,
3096 					 u8 master_rp_id)
3097 {
3098 	MLXSW_REG_ZERO(pererp, payload);
3099 	mlxsw_reg_pererp_region_id_set(payload, region_id);
3100 	mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101 	mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102 	mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103 	mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104 	mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105 }
3106 
3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108  * ----------------------------------------------------------------
3109  * This register configures the Bloom filter entries.
3110  */
3111 #define MLXSW_REG_PEABFE_ID 0x3022
3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116 			      MLXSW_REG_PEABFE_BF_REC_LEN * \
3117 			      MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118 
3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120 
3121 /* reg_peabfe_size
3122  * Number of BF entries to be updated.
3123  * Range 1..256
3124  * Access: Op
3125  */
3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127 
3128 /* reg_peabfe_bf_entry_state
3129  * Bloom filter state
3130  * 0 - Clear
3131  * 1 - Set
3132  * Access: RW
3133  */
3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135 		     MLXSW_REG_PEABFE_BASE_LEN,	31, 1,
3136 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137 
3138 /* reg_peabfe_bf_entry_bank
3139  * Bloom filter bank ID
3140  * Range 0..cap_max_erp_table_banks-1
3141  * Access: Index
3142  */
3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144 		     MLXSW_REG_PEABFE_BASE_LEN,	24, 4,
3145 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146 
3147 /* reg_peabfe_bf_entry_index
3148  * Bloom filter entry index
3149  * Range 0..2^cap_max_bf_log-1
3150  * Access: Index
3151  */
3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153 		     MLXSW_REG_PEABFE_BASE_LEN,	0, 24,
3154 		     MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155 
3156 static inline void mlxsw_reg_peabfe_pack(char *payload)
3157 {
3158 	MLXSW_REG_ZERO(peabfe, payload);
3159 }
3160 
3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162 					     u8 state, u8 bank, u32 bf_index)
3163 {
3164 	u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165 
3166 	if (rec_index >= num_rec)
3167 		mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168 	mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169 	mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170 	mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171 }
3172 
3173 /* IEDR - Infrastructure Entry Delete Register
3174  * ----------------------------------------------------
3175  * This register is used for deleting entries from the entry tables.
3176  * It is legitimate to attempt to delete a nonexisting entry (the device will
3177  * respond as a good flow).
3178  */
3179 #define MLXSW_REG_IEDR_ID 0x3804
3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +	\
3184 			    MLXSW_REG_IEDR_REC_LEN *	\
3185 			    MLXSW_REG_IEDR_REC_MAX_COUNT)
3186 
3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188 
3189 /* reg_iedr_num_rec
3190  * Number of records.
3191  * Access: OP
3192  */
3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194 
3195 /* reg_iedr_rec_type
3196  * Resource type.
3197  * Access: OP
3198  */
3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201 
3202 /* reg_iedr_rec_size
3203  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3204  * Access: OP
3205  */
3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207 		     MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208 
3209 /* reg_iedr_rec_index_start
3210  * Resource index start.
3211  * Access: OP
3212  */
3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214 		     MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215 
3216 static inline void mlxsw_reg_iedr_pack(char *payload)
3217 {
3218 	MLXSW_REG_ZERO(iedr, payload);
3219 }
3220 
3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222 					   u8 rec_type, u16 rec_size,
3223 					   u32 rec_index_start)
3224 {
3225 	u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226 
3227 	if (rec_index >= num_rec)
3228 		mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229 	mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230 	mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231 	mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232 }
3233 
3234 /* QPTS - QoS Priority Trust State Register
3235  * ----------------------------------------
3236  * This register controls the port policy to calculate the switch priority and
3237  * packet color based on incoming packet fields.
3238  */
3239 #define MLXSW_REG_QPTS_ID 0x4002
3240 #define MLXSW_REG_QPTS_LEN 0x8
3241 
3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243 
3244 /* reg_qpts_local_port
3245  * Local port number.
3246  * Access: Index
3247  *
3248  * Note: CPU port is supported.
3249  */
3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251 
3252 enum mlxsw_reg_qpts_trust_state {
3253 	MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254 	MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3255 };
3256 
3257 /* reg_qpts_trust_state
3258  * Trust state for a given port.
3259  * Access: RW
3260  */
3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262 
3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264 				       enum mlxsw_reg_qpts_trust_state ts)
3265 {
3266 	MLXSW_REG_ZERO(qpts, payload);
3267 
3268 	mlxsw_reg_qpts_local_port_set(payload, local_port);
3269 	mlxsw_reg_qpts_trust_state_set(payload, ts);
3270 }
3271 
3272 /* QPCR - QoS Policer Configuration Register
3273  * -----------------------------------------
3274  * The QPCR register is used to create policers - that limit
3275  * the rate of bytes or packets via some trap group.
3276  */
3277 #define MLXSW_REG_QPCR_ID 0x4004
3278 #define MLXSW_REG_QPCR_LEN 0x28
3279 
3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281 
3282 enum mlxsw_reg_qpcr_g {
3283 	MLXSW_REG_QPCR_G_GLOBAL = 2,
3284 	MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285 };
3286 
3287 /* reg_qpcr_g
3288  * The policer type.
3289  * Access: Index
3290  */
3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292 
3293 /* reg_qpcr_pid
3294  * Policer ID.
3295  * Access: Index
3296  */
3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298 
3299 /* reg_qpcr_color_aware
3300  * Is the policer aware of colors.
3301  * Must be 0 (unaware) for cpu port.
3302  * Access: RW for unbounded policer. RO for bounded policer.
3303  */
3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305 
3306 /* reg_qpcr_bytes
3307  * Is policer limit is for bytes per sec or packets per sec.
3308  * 0 - packets
3309  * 1 - bytes
3310  * Access: RW for unbounded policer. RO for bounded policer.
3311  */
3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313 
3314 enum mlxsw_reg_qpcr_ir_units {
3315 	MLXSW_REG_QPCR_IR_UNITS_M,
3316 	MLXSW_REG_QPCR_IR_UNITS_K,
3317 };
3318 
3319 /* reg_qpcr_ir_units
3320  * Policer's units for cir and eir fields (for bytes limits only)
3321  * 1 - 10^3
3322  * 0 - 10^6
3323  * Access: OP
3324  */
3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326 
3327 enum mlxsw_reg_qpcr_rate_type {
3328 	MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329 	MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330 };
3331 
3332 /* reg_qpcr_rate_type
3333  * Policer can have one limit (single rate) or 2 limits with specific operation
3334  * for packets that exceed the lower rate but not the upper one.
3335  * (For cpu port must be single rate)
3336  * Access: RW for unbounded policer. RO for bounded policer.
3337  */
3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339 
3340 /* reg_qpc_cbs
3341  * Policer's committed burst size.
3342  * The policer is working with time slices of 50 nano sec. By default every
3343  * slice is granted the proportionate share of the committed rate. If we want to
3344  * allow a slice to exceed that share (while still keeping the rate per sec) we
3345  * can allow burst. The burst size is between the default proportionate share
3346  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347  * committed rate will result in exceeding the rate). The burst size must be a
3348  * log of 2 and will be determined by 2^cbs.
3349  * Access: RW
3350  */
3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352 
3353 /* reg_qpcr_cir
3354  * Policer's committed rate.
3355  * The rate used for sungle rate, the lower rate for double rate.
3356  * For bytes limits, the rate will be this value * the unit from ir_units.
3357  * (Resolution error is up to 1%).
3358  * Access: RW
3359  */
3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361 
3362 /* reg_qpcr_eir
3363  * Policer's exceed rate.
3364  * The higher rate for double rate, reserved for single rate.
3365  * Lower rate for double rate policer.
3366  * For bytes limits, the rate will be this value * the unit from ir_units.
3367  * (Resolution error is up to 1%).
3368  * Access: RW
3369  */
3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371 
3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373 
3374 /* reg_qpcr_exceed_action.
3375  * What to do with packets between the 2 limits for double rate.
3376  * Access: RW for unbounded policer. RO for bounded policer.
3377  */
3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379 
3380 enum mlxsw_reg_qpcr_action {
3381 	/* Discard */
3382 	MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383 	/* Forward and set color to red.
3384 	 * If the packet is intended to cpu port, it will be dropped.
3385 	 */
3386 	MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387 };
3388 
3389 /* reg_qpcr_violate_action
3390  * What to do with packets that cross the cir limit (for single rate) or the eir
3391  * limit (for double rate).
3392  * Access: RW for unbounded policer. RO for bounded policer.
3393  */
3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395 
3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397 				       enum mlxsw_reg_qpcr_ir_units ir_units,
3398 				       bool bytes, u32 cir, u16 cbs)
3399 {
3400 	MLXSW_REG_ZERO(qpcr, payload);
3401 	mlxsw_reg_qpcr_pid_set(payload, pid);
3402 	mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403 	mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404 	mlxsw_reg_qpcr_violate_action_set(payload,
3405 					  MLXSW_REG_QPCR_ACTION_DISCARD);
3406 	mlxsw_reg_qpcr_cir_set(payload, cir);
3407 	mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408 	mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409 	mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410 }
3411 
3412 /* QTCT - QoS Switch Traffic Class Table
3413  * -------------------------------------
3414  * Configures the mapping between the packet switch priority and the
3415  * traffic class on the transmit port.
3416  */
3417 #define MLXSW_REG_QTCT_ID 0x400A
3418 #define MLXSW_REG_QTCT_LEN 0x08
3419 
3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421 
3422 /* reg_qtct_local_port
3423  * Local port number.
3424  * Access: Index
3425  *
3426  * Note: CPU port is not supported.
3427  */
3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429 
3430 /* reg_qtct_sub_port
3431  * Virtual port within the physical port.
3432  * Should be set to 0 when virtual ports are not enabled on the port.
3433  * Access: Index
3434  */
3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436 
3437 /* reg_qtct_switch_prio
3438  * Switch priority.
3439  * Access: Index
3440  */
3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442 
3443 /* reg_qtct_tclass
3444  * Traffic class.
3445  * Default values:
3446  * switch_prio 0 : tclass 1
3447  * switch_prio 1 : tclass 0
3448  * switch_prio i : tclass i, for i > 1
3449  * Access: RW
3450  */
3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452 
3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454 				       u8 switch_prio, u8 tclass)
3455 {
3456 	MLXSW_REG_ZERO(qtct, payload);
3457 	mlxsw_reg_qtct_local_port_set(payload, local_port);
3458 	mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459 	mlxsw_reg_qtct_tclass_set(payload, tclass);
3460 }
3461 
3462 /* QEEC - QoS ETS Element Configuration Register
3463  * ---------------------------------------------
3464  * Configures the ETS elements.
3465  */
3466 #define MLXSW_REG_QEEC_ID 0x400D
3467 #define MLXSW_REG_QEEC_LEN 0x20
3468 
3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470 
3471 /* reg_qeec_local_port
3472  * Local port number.
3473  * Access: Index
3474  *
3475  * Note: CPU port is supported.
3476  */
3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478 
3479 enum mlxsw_reg_qeec_hr {
3480 	MLXSW_REG_QEEC_HIERARCY_PORT,
3481 	MLXSW_REG_QEEC_HIERARCY_GROUP,
3482 	MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483 	MLXSW_REG_QEEC_HIERARCY_TC,
3484 };
3485 
3486 /* reg_qeec_element_hierarchy
3487  * 0 - Port
3488  * 1 - Group
3489  * 2 - Subgroup
3490  * 3 - Traffic Class
3491  * Access: Index
3492  */
3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494 
3495 /* reg_qeec_element_index
3496  * The index of the element in the hierarchy.
3497  * Access: Index
3498  */
3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500 
3501 /* reg_qeec_next_element_index
3502  * The index of the next (lower) element in the hierarchy.
3503  * Access: RW
3504  *
3505  * Note: Reserved for element_hierarchy 0.
3506  */
3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508 
3509 /* reg_qeec_mise
3510  * Min shaper configuration enable. Enables configuration of the min
3511  * shaper on this ETS element
3512  * 0 - Disable
3513  * 1 - Enable
3514  * Access: RW
3515  */
3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517 
3518 enum {
3519 	MLXSW_REG_QEEC_BYTES_MODE,
3520 	MLXSW_REG_QEEC_PACKETS_MODE,
3521 };
3522 
3523 /* reg_qeec_pb
3524  * Packets or bytes mode.
3525  * 0 - Bytes mode
3526  * 1 - Packets mode
3527  * Access: RW
3528  *
3529  * Note: Used for max shaper configuration. For Spectrum, packets mode
3530  * is supported only for traffic classes of CPU port.
3531  */
3532 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3533 
3534 /* The smallest permitted min shaper rate. */
3535 #define MLXSW_REG_QEEC_MIS_MIN	200000		/* Kbps */
3536 
3537 /* reg_qeec_min_shaper_rate
3538  * Min shaper information rate.
3539  * For CPU port, can only be configured for port hierarchy.
3540  * When in bytes mode, value is specified in units of 1000bps.
3541  * Access: RW
3542  */
3543 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3544 
3545 /* reg_qeec_mase
3546  * Max shaper configuration enable. Enables configuration of the max
3547  * shaper on this ETS element.
3548  * 0 - Disable
3549  * 1 - Enable
3550  * Access: RW
3551  */
3552 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3553 
3554 /* A large max rate will disable the max shaper. */
3555 #define MLXSW_REG_QEEC_MAS_DIS	200000000	/* Kbps */
3556 
3557 /* reg_qeec_max_shaper_rate
3558  * Max shaper information rate.
3559  * For CPU port, can only be configured for port hierarchy.
3560  * When in bytes mode, value is specified in units of 1000bps.
3561  * Access: RW
3562  */
3563 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3564 
3565 /* reg_qeec_de
3566  * DWRR configuration enable. Enables configuration of the dwrr and
3567  * dwrr_weight.
3568  * 0 - Disable
3569  * 1 - Enable
3570  * Access: RW
3571  */
3572 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3573 
3574 /* reg_qeec_dwrr
3575  * Transmission selection algorithm to use on the link going down from
3576  * the ETS element.
3577  * 0 - Strict priority
3578  * 1 - DWRR
3579  * Access: RW
3580  */
3581 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3582 
3583 /* reg_qeec_dwrr_weight
3584  * DWRR weight on the link going down from the ETS element. The
3585  * percentage of bandwidth guaranteed to an ETS element within
3586  * its hierarchy. The sum of all weights across all ETS elements
3587  * within one hierarchy should be equal to 100. Reserved when
3588  * transmission selection algorithm is strict priority.
3589  * Access: RW
3590  */
3591 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3592 
3593 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3594 				       enum mlxsw_reg_qeec_hr hr, u8 index,
3595 				       u8 next_index)
3596 {
3597 	MLXSW_REG_ZERO(qeec, payload);
3598 	mlxsw_reg_qeec_local_port_set(payload, local_port);
3599 	mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3600 	mlxsw_reg_qeec_element_index_set(payload, index);
3601 	mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3602 }
3603 
3604 /* QRWE - QoS ReWrite Enable
3605  * -------------------------
3606  * This register configures the rewrite enable per receive port.
3607  */
3608 #define MLXSW_REG_QRWE_ID 0x400F
3609 #define MLXSW_REG_QRWE_LEN 0x08
3610 
3611 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3612 
3613 /* reg_qrwe_local_port
3614  * Local port number.
3615  * Access: Index
3616  *
3617  * Note: CPU port is supported. No support for router port.
3618  */
3619 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3620 
3621 /* reg_qrwe_dscp
3622  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3623  * Access: RW
3624  */
3625 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3626 
3627 /* reg_qrwe_pcp
3628  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3629  * Access: RW
3630  */
3631 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3632 
3633 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3634 				       bool rewrite_pcp, bool rewrite_dscp)
3635 {
3636 	MLXSW_REG_ZERO(qrwe, payload);
3637 	mlxsw_reg_qrwe_local_port_set(payload, local_port);
3638 	mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3639 	mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3640 }
3641 
3642 /* QPDSM - QoS Priority to DSCP Mapping
3643  * ------------------------------------
3644  * QoS Priority to DSCP Mapping Register
3645  */
3646 #define MLXSW_REG_QPDSM_ID 0x4011
3647 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3648 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3649 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3650 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +			\
3651 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *	\
3652 			     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3653 
3654 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3655 
3656 /* reg_qpdsm_local_port
3657  * Local Port. Supported for data packets from CPU port.
3658  * Access: Index
3659  */
3660 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3661 
3662 /* reg_qpdsm_prio_entry_color0_e
3663  * Enable update of the entry for color 0 and a given port.
3664  * Access: WO
3665  */
3666 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3667 		     MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3668 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3669 
3670 /* reg_qpdsm_prio_entry_color0_dscp
3671  * DSCP field in the outer label of the packet for color 0 and a given port.
3672  * Reserved when e=0.
3673  * Access: RW
3674  */
3675 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3676 		     MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3677 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3678 
3679 /* reg_qpdsm_prio_entry_color1_e
3680  * Enable update of the entry for color 1 and a given port.
3681  * Access: WO
3682  */
3683 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3684 		     MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3685 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3686 
3687 /* reg_qpdsm_prio_entry_color1_dscp
3688  * DSCP field in the outer label of the packet for color 1 and a given port.
3689  * Reserved when e=0.
3690  * Access: RW
3691  */
3692 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3693 		     MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3694 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3695 
3696 /* reg_qpdsm_prio_entry_color2_e
3697  * Enable update of the entry for color 2 and a given port.
3698  * Access: WO
3699  */
3700 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3701 		     MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3702 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3703 
3704 /* reg_qpdsm_prio_entry_color2_dscp
3705  * DSCP field in the outer label of the packet for color 2 and a given port.
3706  * Reserved when e=0.
3707  * Access: RW
3708  */
3709 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3710 		     MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3711 		     MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3712 
3713 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3714 {
3715 	MLXSW_REG_ZERO(qpdsm, payload);
3716 	mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3717 }
3718 
3719 static inline void
3720 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3721 {
3722 	mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3723 	mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3724 	mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3725 	mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3726 	mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3727 	mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3728 }
3729 
3730 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3731  * --------------------------------------------------
3732  * This register controls the mapping from DSCP field to
3733  * Switch Priority for IP packets.
3734  */
3735 #define MLXSW_REG_QPDPM_ID 0x4013
3736 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3737 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3738 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3739 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +			\
3740 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *	\
3741 			     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3742 
3743 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3744 
3745 /* reg_qpdpm_local_port
3746  * Local Port. Supported for data packets from CPU port.
3747  * Access: Index
3748  */
3749 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3750 
3751 /* reg_qpdpm_dscp_e
3752  * Enable update of the specific entry. When cleared, the switch_prio and color
3753  * fields are ignored and the previous switch_prio and color values are
3754  * preserved.
3755  * Access: WO
3756  */
3757 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3758 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3759 
3760 /* reg_qpdpm_dscp_prio
3761  * The new Switch Priority value for the relevant DSCP value.
3762  * Access: RW
3763  */
3764 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3765 		     MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3766 		     MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3767 
3768 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3769 {
3770 	MLXSW_REG_ZERO(qpdpm, payload);
3771 	mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3772 }
3773 
3774 static inline void
3775 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3776 {
3777 	mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3778 	mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3779 }
3780 
3781 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3782  * ------------------------------------------------------------------
3783  * This register configures if the Switch Priority to Traffic Class mapping is
3784  * based on Multicast packet indication. If so, then multicast packets will get
3785  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3786  * QTCT.
3787  * By default, Switch Priority to Traffic Class mapping is not based on
3788  * Multicast packet indication.
3789  */
3790 #define MLXSW_REG_QTCTM_ID 0x401A
3791 #define MLXSW_REG_QTCTM_LEN 0x08
3792 
3793 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3794 
3795 /* reg_qtctm_local_port
3796  * Local port number.
3797  * No support for CPU port.
3798  * Access: Index
3799  */
3800 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3801 
3802 /* reg_qtctm_mc
3803  * Multicast Mode
3804  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3805  * indication (default is 0, not based on Multicast packet indication).
3806  */
3807 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3808 
3809 static inline void
3810 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3811 {
3812 	MLXSW_REG_ZERO(qtctm, payload);
3813 	mlxsw_reg_qtctm_local_port_set(payload, local_port);
3814 	mlxsw_reg_qtctm_mc_set(payload, mc);
3815 }
3816 
3817 /* PMLP - Ports Module to Local Port Register
3818  * ------------------------------------------
3819  * Configures the assignment of modules to local ports.
3820  */
3821 #define MLXSW_REG_PMLP_ID 0x5002
3822 #define MLXSW_REG_PMLP_LEN 0x40
3823 
3824 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3825 
3826 /* reg_pmlp_rxtx
3827  * 0 - Tx value is used for both Tx and Rx.
3828  * 1 - Rx value is taken from a separte field.
3829  * Access: RW
3830  */
3831 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3832 
3833 /* reg_pmlp_local_port
3834  * Local port number.
3835  * Access: Index
3836  */
3837 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3838 
3839 /* reg_pmlp_width
3840  * 0 - Unmap local port.
3841  * 1 - Lane 0 is used.
3842  * 2 - Lanes 0 and 1 are used.
3843  * 4 - Lanes 0, 1, 2 and 3 are used.
3844  * Access: RW
3845  */
3846 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3847 
3848 /* reg_pmlp_module
3849  * Module number.
3850  * Access: RW
3851  */
3852 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3853 
3854 /* reg_pmlp_tx_lane
3855  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3856  * Access: RW
3857  */
3858 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3859 
3860 /* reg_pmlp_rx_lane
3861  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3862  * equal to Tx lane.
3863  * Access: RW
3864  */
3865 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3866 
3867 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3868 {
3869 	MLXSW_REG_ZERO(pmlp, payload);
3870 	mlxsw_reg_pmlp_local_port_set(payload, local_port);
3871 }
3872 
3873 /* PMTU - Port MTU Register
3874  * ------------------------
3875  * Configures and reports the port MTU.
3876  */
3877 #define MLXSW_REG_PMTU_ID 0x5003
3878 #define MLXSW_REG_PMTU_LEN 0x10
3879 
3880 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
3881 
3882 /* reg_pmtu_local_port
3883  * Local port number.
3884  * Access: Index
3885  */
3886 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
3887 
3888 /* reg_pmtu_max_mtu
3889  * Maximum MTU.
3890  * When port type (e.g. Ethernet) is configured, the relevant MTU is
3891  * reported, otherwise the minimum between the max_mtu of the different
3892  * types is reported.
3893  * Access: RO
3894  */
3895 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
3896 
3897 /* reg_pmtu_admin_mtu
3898  * MTU value to set port to. Must be smaller or equal to max_mtu.
3899  * Note: If port type is Infiniband, then port must be disabled, when its
3900  * MTU is set.
3901  * Access: RW
3902  */
3903 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
3904 
3905 /* reg_pmtu_oper_mtu
3906  * The actual MTU configured on the port. Packets exceeding this size
3907  * will be dropped.
3908  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
3909  * oper_mtu might be smaller than admin_mtu.
3910  * Access: RO
3911  */
3912 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
3913 
3914 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
3915 				       u16 new_mtu)
3916 {
3917 	MLXSW_REG_ZERO(pmtu, payload);
3918 	mlxsw_reg_pmtu_local_port_set(payload, local_port);
3919 	mlxsw_reg_pmtu_max_mtu_set(payload, 0);
3920 	mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
3921 	mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
3922 }
3923 
3924 /* PTYS - Port Type and Speed Register
3925  * -----------------------------------
3926  * Configures and reports the port speed type.
3927  *
3928  * Note: When set while the link is up, the changes will not take effect
3929  * until the port transitions from down to up state.
3930  */
3931 #define MLXSW_REG_PTYS_ID 0x5004
3932 #define MLXSW_REG_PTYS_LEN 0x40
3933 
3934 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
3935 
3936 /* an_disable_admin
3937  * Auto negotiation disable administrative configuration
3938  * 0 - Device doesn't support AN disable.
3939  * 1 - Device supports AN disable.
3940  * Access: RW
3941  */
3942 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
3943 
3944 /* reg_ptys_local_port
3945  * Local port number.
3946  * Access: Index
3947  */
3948 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
3949 
3950 #define MLXSW_REG_PTYS_PROTO_MASK_IB	BIT(0)
3951 #define MLXSW_REG_PTYS_PROTO_MASK_ETH	BIT(2)
3952 
3953 /* reg_ptys_proto_mask
3954  * Protocol mask. Indicates which protocol is used.
3955  * 0 - Infiniband.
3956  * 1 - Fibre Channel.
3957  * 2 - Ethernet.
3958  * Access: Index
3959  */
3960 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
3961 
3962 enum {
3963 	MLXSW_REG_PTYS_AN_STATUS_NA,
3964 	MLXSW_REG_PTYS_AN_STATUS_OK,
3965 	MLXSW_REG_PTYS_AN_STATUS_FAIL,
3966 };
3967 
3968 /* reg_ptys_an_status
3969  * Autonegotiation status.
3970  * Access: RO
3971  */
3972 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3973 
3974 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M				BIT(0)
3975 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII			BIT(1)
3976 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII			BIT(2)
3977 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R				BIT(3)
3978 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G			BIT(4)
3979 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G		BIT(5)
3980 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR		BIT(6)
3981 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	BIT(7)
3982 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR	BIT(8)
3983 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)
3984 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)
3985 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)
3986 
3987 /* reg_ptys_ext_eth_proto_cap
3988  * Extended Ethernet port supported speeds and protocols.
3989  * Access: RO
3990  */
3991 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
3992 
3993 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII			BIT(0)
3994 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX		BIT(1)
3995 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4		BIT(2)
3996 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4		BIT(3)
3997 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR		BIT(4)
3998 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2		BIT(5)
3999 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4		BIT(6)
4000 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4		BIT(7)
4001 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4		BIT(8)
4002 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR		BIT(12)
4003 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR		BIT(13)
4004 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR		BIT(14)
4005 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4		BIT(15)
4006 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4	BIT(16)
4007 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2		BIT(18)
4008 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4		BIT(19)
4009 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)
4010 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)
4011 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)
4012 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)
4013 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX		BIT(24)
4014 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T		BIT(25)
4015 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T		BIT(26)
4016 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)
4017 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)
4018 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)
4019 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2		BIT(30)
4020 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2		BIT(31)
4021 
4022 /* reg_ptys_eth_proto_cap
4023  * Ethernet port supported speeds and protocols.
4024  * Access: RO
4025  */
4026 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4027 
4028 /* reg_ptys_ib_link_width_cap
4029  * IB port supported widths.
4030  * Access: RO
4031  */
4032 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4033 
4034 #define MLXSW_REG_PTYS_IB_SPEED_SDR	BIT(0)
4035 #define MLXSW_REG_PTYS_IB_SPEED_DDR	BIT(1)
4036 #define MLXSW_REG_PTYS_IB_SPEED_QDR	BIT(2)
4037 #define MLXSW_REG_PTYS_IB_SPEED_FDR10	BIT(3)
4038 #define MLXSW_REG_PTYS_IB_SPEED_FDR	BIT(4)
4039 #define MLXSW_REG_PTYS_IB_SPEED_EDR	BIT(5)
4040 
4041 /* reg_ptys_ib_proto_cap
4042  * IB port supported speeds and protocols.
4043  * Access: RO
4044  */
4045 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4046 
4047 /* reg_ptys_ext_eth_proto_admin
4048  * Extended speed and protocol to set port to.
4049  * Access: RW
4050  */
4051 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4052 
4053 /* reg_ptys_eth_proto_admin
4054  * Speed and protocol to set port to.
4055  * Access: RW
4056  */
4057 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4058 
4059 /* reg_ptys_ib_link_width_admin
4060  * IB width to set port to.
4061  * Access: RW
4062  */
4063 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4064 
4065 /* reg_ptys_ib_proto_admin
4066  * IB speeds and protocols to set port to.
4067  * Access: RW
4068  */
4069 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4070 
4071 /* reg_ptys_ext_eth_proto_oper
4072  * The extended current speed and protocol configured for the port.
4073  * Access: RO
4074  */
4075 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4076 
4077 /* reg_ptys_eth_proto_oper
4078  * The current speed and protocol configured for the port.
4079  * Access: RO
4080  */
4081 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4082 
4083 /* reg_ptys_ib_link_width_oper
4084  * The current IB width to set port to.
4085  * Access: RO
4086  */
4087 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4088 
4089 /* reg_ptys_ib_proto_oper
4090  * The current IB speed and protocol.
4091  * Access: RO
4092  */
4093 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4094 
4095 enum mlxsw_reg_ptys_connector_type {
4096 	MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4097 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4098 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4099 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4100 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4101 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4102 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4103 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4104 	MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4105 };
4106 
4107 /* reg_ptys_connector_type
4108  * Connector type indication.
4109  * Access: RO
4110  */
4111 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4112 
4113 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4114 					   u32 proto_admin, bool autoneg)
4115 {
4116 	MLXSW_REG_ZERO(ptys, payload);
4117 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4118 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4119 	mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4120 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4121 }
4122 
4123 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4124 					       u32 proto_admin, bool autoneg)
4125 {
4126 	MLXSW_REG_ZERO(ptys, payload);
4127 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4128 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4129 	mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4130 	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4131 }
4132 
4133 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4134 					     u32 *p_eth_proto_cap,
4135 					     u32 *p_eth_proto_admin,
4136 					     u32 *p_eth_proto_oper)
4137 {
4138 	if (p_eth_proto_cap)
4139 		*p_eth_proto_cap =
4140 			mlxsw_reg_ptys_eth_proto_cap_get(payload);
4141 	if (p_eth_proto_admin)
4142 		*p_eth_proto_admin =
4143 			mlxsw_reg_ptys_eth_proto_admin_get(payload);
4144 	if (p_eth_proto_oper)
4145 		*p_eth_proto_oper =
4146 			mlxsw_reg_ptys_eth_proto_oper_get(payload);
4147 }
4148 
4149 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4150 						 u32 *p_eth_proto_cap,
4151 						 u32 *p_eth_proto_admin,
4152 						 u32 *p_eth_proto_oper)
4153 {
4154 	if (p_eth_proto_cap)
4155 		*p_eth_proto_cap =
4156 			mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4157 	if (p_eth_proto_admin)
4158 		*p_eth_proto_admin =
4159 			mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4160 	if (p_eth_proto_oper)
4161 		*p_eth_proto_oper =
4162 			mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4163 }
4164 
4165 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4166 					  u16 proto_admin, u16 link_width)
4167 {
4168 	MLXSW_REG_ZERO(ptys, payload);
4169 	mlxsw_reg_ptys_local_port_set(payload, local_port);
4170 	mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4171 	mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4172 	mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4173 }
4174 
4175 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4176 					    u16 *p_ib_link_width_cap,
4177 					    u16 *p_ib_proto_oper,
4178 					    u16 *p_ib_link_width_oper)
4179 {
4180 	if (p_ib_proto_cap)
4181 		*p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4182 	if (p_ib_link_width_cap)
4183 		*p_ib_link_width_cap =
4184 			mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4185 	if (p_ib_proto_oper)
4186 		*p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4187 	if (p_ib_link_width_oper)
4188 		*p_ib_link_width_oper =
4189 			mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4190 }
4191 
4192 /* PPAD - Port Physical Address Register
4193  * -------------------------------------
4194  * The PPAD register configures the per port physical MAC address.
4195  */
4196 #define MLXSW_REG_PPAD_ID 0x5005
4197 #define MLXSW_REG_PPAD_LEN 0x10
4198 
4199 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4200 
4201 /* reg_ppad_single_base_mac
4202  * 0: base_mac, local port should be 0 and mac[7:0] is
4203  * reserved. HW will set incremental
4204  * 1: single_mac - mac of the local_port
4205  * Access: RW
4206  */
4207 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4208 
4209 /* reg_ppad_local_port
4210  * port number, if single_base_mac = 0 then local_port is reserved
4211  * Access: RW
4212  */
4213 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4214 
4215 /* reg_ppad_mac
4216  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4217  * If single_base_mac = 1 - the per port MAC address
4218  * Access: RW
4219  */
4220 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4221 
4222 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4223 				       u8 local_port)
4224 {
4225 	MLXSW_REG_ZERO(ppad, payload);
4226 	mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4227 	mlxsw_reg_ppad_local_port_set(payload, local_port);
4228 }
4229 
4230 /* PAOS - Ports Administrative and Operational Status Register
4231  * -----------------------------------------------------------
4232  * Configures and retrieves per port administrative and operational status.
4233  */
4234 #define MLXSW_REG_PAOS_ID 0x5006
4235 #define MLXSW_REG_PAOS_LEN 0x10
4236 
4237 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4238 
4239 /* reg_paos_swid
4240  * Switch partition ID with which to associate the port.
4241  * Note: while external ports uses unique local port numbers (and thus swid is
4242  * redundant), router ports use the same local port number where swid is the
4243  * only indication for the relevant port.
4244  * Access: Index
4245  */
4246 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4247 
4248 /* reg_paos_local_port
4249  * Local port number.
4250  * Access: Index
4251  */
4252 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4253 
4254 /* reg_paos_admin_status
4255  * Port administrative state (the desired state of the port):
4256  * 1 - Up.
4257  * 2 - Down.
4258  * 3 - Up once. This means that in case of link failure, the port won't go
4259  *     into polling mode, but will wait to be re-enabled by software.
4260  * 4 - Disabled by system. Can only be set by hardware.
4261  * Access: RW
4262  */
4263 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4264 
4265 /* reg_paos_oper_status
4266  * Port operational state (the current state):
4267  * 1 - Up.
4268  * 2 - Down.
4269  * 3 - Down by port failure. This means that the device will not let the
4270  *     port up again until explicitly specified by software.
4271  * Access: RO
4272  */
4273 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4274 
4275 /* reg_paos_ase
4276  * Admin state update enabled.
4277  * Access: WO
4278  */
4279 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4280 
4281 /* reg_paos_ee
4282  * Event update enable. If this bit is set, event generation will be
4283  * updated based on the e field.
4284  * Access: WO
4285  */
4286 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4287 
4288 /* reg_paos_e
4289  * Event generation on operational state change:
4290  * 0 - Do not generate event.
4291  * 1 - Generate Event.
4292  * 2 - Generate Single Event.
4293  * Access: RW
4294  */
4295 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4296 
4297 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4298 				       enum mlxsw_port_admin_status status)
4299 {
4300 	MLXSW_REG_ZERO(paos, payload);
4301 	mlxsw_reg_paos_swid_set(payload, 0);
4302 	mlxsw_reg_paos_local_port_set(payload, local_port);
4303 	mlxsw_reg_paos_admin_status_set(payload, status);
4304 	mlxsw_reg_paos_oper_status_set(payload, 0);
4305 	mlxsw_reg_paos_ase_set(payload, 1);
4306 	mlxsw_reg_paos_ee_set(payload, 1);
4307 	mlxsw_reg_paos_e_set(payload, 1);
4308 }
4309 
4310 /* PFCC - Ports Flow Control Configuration Register
4311  * ------------------------------------------------
4312  * Configures and retrieves the per port flow control configuration.
4313  */
4314 #define MLXSW_REG_PFCC_ID 0x5007
4315 #define MLXSW_REG_PFCC_LEN 0x20
4316 
4317 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4318 
4319 /* reg_pfcc_local_port
4320  * Local port number.
4321  * Access: Index
4322  */
4323 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4324 
4325 /* reg_pfcc_pnat
4326  * Port number access type. Determines the way local_port is interpreted:
4327  * 0 - Local port number.
4328  * 1 - IB / label port number.
4329  * Access: Index
4330  */
4331 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4332 
4333 /* reg_pfcc_shl_cap
4334  * Send to higher layers capabilities:
4335  * 0 - No capability of sending Pause and PFC frames to higher layers.
4336  * 1 - Device has capability of sending Pause and PFC frames to higher
4337  *     layers.
4338  * Access: RO
4339  */
4340 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4341 
4342 /* reg_pfcc_shl_opr
4343  * Send to higher layers operation:
4344  * 0 - Pause and PFC frames are handled by the port (default).
4345  * 1 - Pause and PFC frames are handled by the port and also sent to
4346  *     higher layers. Only valid if shl_cap = 1.
4347  * Access: RW
4348  */
4349 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4350 
4351 /* reg_pfcc_ppan
4352  * Pause policy auto negotiation.
4353  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4354  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4355  *     based on the auto-negotiation resolution.
4356  * Access: RW
4357  *
4358  * Note: The auto-negotiation advertisement is set according to pptx and
4359  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4360  */
4361 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4362 
4363 /* reg_pfcc_prio_mask_tx
4364  * Bit per priority indicating if Tx flow control policy should be
4365  * updated based on bit pfctx.
4366  * Access: WO
4367  */
4368 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4369 
4370 /* reg_pfcc_prio_mask_rx
4371  * Bit per priority indicating if Rx flow control policy should be
4372  * updated based on bit pfcrx.
4373  * Access: WO
4374  */
4375 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4376 
4377 /* reg_pfcc_pptx
4378  * Admin Pause policy on Tx.
4379  * 0 - Never generate Pause frames (default).
4380  * 1 - Generate Pause frames according to Rx buffer threshold.
4381  * Access: RW
4382  */
4383 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4384 
4385 /* reg_pfcc_aptx
4386  * Active (operational) Pause policy on Tx.
4387  * 0 - Never generate Pause frames.
4388  * 1 - Generate Pause frames according to Rx buffer threshold.
4389  * Access: RO
4390  */
4391 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4392 
4393 /* reg_pfcc_pfctx
4394  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4395  * 0 - Never generate priority Pause frames on the specified priority
4396  *     (default).
4397  * 1 - Generate priority Pause frames according to Rx buffer threshold on
4398  *     the specified priority.
4399  * Access: RW
4400  *
4401  * Note: pfctx and pptx must be mutually exclusive.
4402  */
4403 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4404 
4405 /* reg_pfcc_pprx
4406  * Admin Pause policy on Rx.
4407  * 0 - Ignore received Pause frames (default).
4408  * 1 - Respect received Pause frames.
4409  * Access: RW
4410  */
4411 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4412 
4413 /* reg_pfcc_aprx
4414  * Active (operational) Pause policy on Rx.
4415  * 0 - Ignore received Pause frames.
4416  * 1 - Respect received Pause frames.
4417  * Access: RO
4418  */
4419 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4420 
4421 /* reg_pfcc_pfcrx
4422  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4423  * 0 - Ignore incoming priority Pause frames on the specified priority
4424  *     (default).
4425  * 1 - Respect incoming priority Pause frames on the specified priority.
4426  * Access: RW
4427  */
4428 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4429 
4430 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4431 
4432 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4433 {
4434 	mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4435 	mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4436 	mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4437 	mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4438 }
4439 
4440 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4441 {
4442 	MLXSW_REG_ZERO(pfcc, payload);
4443 	mlxsw_reg_pfcc_local_port_set(payload, local_port);
4444 }
4445 
4446 /* PPCNT - Ports Performance Counters Register
4447  * -------------------------------------------
4448  * The PPCNT register retrieves per port performance counters.
4449  */
4450 #define MLXSW_REG_PPCNT_ID 0x5008
4451 #define MLXSW_REG_PPCNT_LEN 0x100
4452 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4453 
4454 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4455 
4456 /* reg_ppcnt_swid
4457  * For HCA: must be always 0.
4458  * Switch partition ID to associate port with.
4459  * Switch partitions are numbered from 0 to 7 inclusively.
4460  * Switch partition 254 indicates stacking ports.
4461  * Switch partition 255 indicates all switch partitions.
4462  * Only valid on Set() operation with local_port=255.
4463  * Access: Index
4464  */
4465 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4466 
4467 /* reg_ppcnt_local_port
4468  * Local port number.
4469  * 255 indicates all ports on the device, and is only allowed
4470  * for Set() operation.
4471  * Access: Index
4472  */
4473 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4474 
4475 /* reg_ppcnt_pnat
4476  * Port number access type:
4477  * 0 - Local port number
4478  * 1 - IB port number
4479  * Access: Index
4480  */
4481 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4482 
4483 enum mlxsw_reg_ppcnt_grp {
4484 	MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4485 	MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4486 	MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4487 	MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4488 	MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4489 	MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4490 	MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4491 	MLXSW_REG_PPCNT_TC_CNT = 0x11,
4492 	MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4493 };
4494 
4495 /* reg_ppcnt_grp
4496  * Performance counter group.
4497  * Group 63 indicates all groups. Only valid on Set() operation with
4498  * clr bit set.
4499  * 0x0: IEEE 802.3 Counters
4500  * 0x1: RFC 2863 Counters
4501  * 0x2: RFC 2819 Counters
4502  * 0x3: RFC 3635 Counters
4503  * 0x5: Ethernet Extended Counters
4504  * 0x6: Ethernet Discard Counters
4505  * 0x8: Link Level Retransmission Counters
4506  * 0x10: Per Priority Counters
4507  * 0x11: Per Traffic Class Counters
4508  * 0x12: Physical Layer Counters
4509  * 0x13: Per Traffic Class Congestion Counters
4510  * Access: Index
4511  */
4512 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4513 
4514 /* reg_ppcnt_clr
4515  * Clear counters. Setting the clr bit will reset the counter value
4516  * for all counters in the counter group. This bit can be set
4517  * for both Set() and Get() operation.
4518  * Access: OP
4519  */
4520 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4521 
4522 /* reg_ppcnt_prio_tc
4523  * Priority for counter set that support per priority, valid values: 0-7.
4524  * Traffic class for counter set that support per traffic class,
4525  * valid values: 0- cap_max_tclass-1 .
4526  * For HCA: cap_max_tclass is always 8.
4527  * Otherwise must be 0.
4528  * Access: Index
4529  */
4530 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4531 
4532 /* Ethernet IEEE 802.3 Counter Group */
4533 
4534 /* reg_ppcnt_a_frames_transmitted_ok
4535  * Access: RO
4536  */
4537 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4538 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4539 
4540 /* reg_ppcnt_a_frames_received_ok
4541  * Access: RO
4542  */
4543 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4544 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4545 
4546 /* reg_ppcnt_a_frame_check_sequence_errors
4547  * Access: RO
4548  */
4549 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4550 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4551 
4552 /* reg_ppcnt_a_alignment_errors
4553  * Access: RO
4554  */
4555 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4556 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4557 
4558 /* reg_ppcnt_a_octets_transmitted_ok
4559  * Access: RO
4560  */
4561 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4562 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4563 
4564 /* reg_ppcnt_a_octets_received_ok
4565  * Access: RO
4566  */
4567 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4568 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4569 
4570 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4571  * Access: RO
4572  */
4573 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4574 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4575 
4576 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4577  * Access: RO
4578  */
4579 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4580 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4581 
4582 /* reg_ppcnt_a_multicast_frames_received_ok
4583  * Access: RO
4584  */
4585 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4586 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4587 
4588 /* reg_ppcnt_a_broadcast_frames_received_ok
4589  * Access: RO
4590  */
4591 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4592 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4593 
4594 /* reg_ppcnt_a_in_range_length_errors
4595  * Access: RO
4596  */
4597 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4598 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4599 
4600 /* reg_ppcnt_a_out_of_range_length_field
4601  * Access: RO
4602  */
4603 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4604 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4605 
4606 /* reg_ppcnt_a_frame_too_long_errors
4607  * Access: RO
4608  */
4609 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4610 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4611 
4612 /* reg_ppcnt_a_symbol_error_during_carrier
4613  * Access: RO
4614  */
4615 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4616 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4617 
4618 /* reg_ppcnt_a_mac_control_frames_transmitted
4619  * Access: RO
4620  */
4621 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4622 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4623 
4624 /* reg_ppcnt_a_mac_control_frames_received
4625  * Access: RO
4626  */
4627 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4628 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4629 
4630 /* reg_ppcnt_a_unsupported_opcodes_received
4631  * Access: RO
4632  */
4633 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4634 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4635 
4636 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4637  * Access: RO
4638  */
4639 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4640 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4641 
4642 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4643  * Access: RO
4644  */
4645 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4646 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4647 
4648 /* Ethernet RFC 2863 Counter Group */
4649 
4650 /* reg_ppcnt_if_in_discards
4651  * Access: RO
4652  */
4653 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4654 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4655 
4656 /* reg_ppcnt_if_out_discards
4657  * Access: RO
4658  */
4659 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4660 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4661 
4662 /* reg_ppcnt_if_out_errors
4663  * Access: RO
4664  */
4665 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4666 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4667 
4668 /* Ethernet RFC 2819 Counter Group */
4669 
4670 /* reg_ppcnt_ether_stats_undersize_pkts
4671  * Access: RO
4672  */
4673 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4674 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4675 
4676 /* reg_ppcnt_ether_stats_oversize_pkts
4677  * Access: RO
4678  */
4679 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4680 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4681 
4682 /* reg_ppcnt_ether_stats_fragments
4683  * Access: RO
4684  */
4685 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4686 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4687 
4688 /* reg_ppcnt_ether_stats_pkts64octets
4689  * Access: RO
4690  */
4691 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4692 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4693 
4694 /* reg_ppcnt_ether_stats_pkts65to127octets
4695  * Access: RO
4696  */
4697 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4698 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4699 
4700 /* reg_ppcnt_ether_stats_pkts128to255octets
4701  * Access: RO
4702  */
4703 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4704 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4705 
4706 /* reg_ppcnt_ether_stats_pkts256to511octets
4707  * Access: RO
4708  */
4709 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4710 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4711 
4712 /* reg_ppcnt_ether_stats_pkts512to1023octets
4713  * Access: RO
4714  */
4715 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4716 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4717 
4718 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4719  * Access: RO
4720  */
4721 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4722 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4723 
4724 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4725  * Access: RO
4726  */
4727 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4728 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4729 
4730 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4731  * Access: RO
4732  */
4733 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4734 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4735 
4736 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4737  * Access: RO
4738  */
4739 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4740 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4741 
4742 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4743  * Access: RO
4744  */
4745 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4746 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4747 
4748 /* Ethernet RFC 3635 Counter Group */
4749 
4750 /* reg_ppcnt_dot3stats_fcs_errors
4751  * Access: RO
4752  */
4753 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4754 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4755 
4756 /* reg_ppcnt_dot3stats_symbol_errors
4757  * Access: RO
4758  */
4759 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4760 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4761 
4762 /* reg_ppcnt_dot3control_in_unknown_opcodes
4763  * Access: RO
4764  */
4765 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4766 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4767 
4768 /* reg_ppcnt_dot3in_pause_frames
4769  * Access: RO
4770  */
4771 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4772 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4773 
4774 /* Ethernet Extended Counter Group Counters */
4775 
4776 /* reg_ppcnt_ecn_marked
4777  * Access: RO
4778  */
4779 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4780 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4781 
4782 /* Ethernet Discard Counter Group Counters */
4783 
4784 /* reg_ppcnt_ingress_general
4785  * Access: RO
4786  */
4787 MLXSW_ITEM64(reg, ppcnt, ingress_general,
4788 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4789 
4790 /* reg_ppcnt_ingress_policy_engine
4791  * Access: RO
4792  */
4793 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4794 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4795 
4796 /* reg_ppcnt_ingress_vlan_membership
4797  * Access: RO
4798  */
4799 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4800 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4801 
4802 /* reg_ppcnt_ingress_tag_frame_type
4803  * Access: RO
4804  */
4805 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4806 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4807 
4808 /* reg_ppcnt_egress_vlan_membership
4809  * Access: RO
4810  */
4811 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4812 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4813 
4814 /* reg_ppcnt_loopback_filter
4815  * Access: RO
4816  */
4817 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4818 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4819 
4820 /* reg_ppcnt_egress_general
4821  * Access: RO
4822  */
4823 MLXSW_ITEM64(reg, ppcnt, egress_general,
4824 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4825 
4826 /* reg_ppcnt_egress_hoq
4827  * Access: RO
4828  */
4829 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
4830 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4831 
4832 /* reg_ppcnt_egress_policy_engine
4833  * Access: RO
4834  */
4835 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
4836 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4837 
4838 /* reg_ppcnt_ingress_tx_link_down
4839  * Access: RO
4840  */
4841 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
4842 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4843 
4844 /* reg_ppcnt_egress_stp_filter
4845  * Access: RO
4846  */
4847 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
4848 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4849 
4850 /* reg_ppcnt_egress_sll
4851  * Access: RO
4852  */
4853 MLXSW_ITEM64(reg, ppcnt, egress_sll,
4854 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4855 
4856 /* Ethernet Per Priority Group Counters */
4857 
4858 /* reg_ppcnt_rx_octets
4859  * Access: RO
4860  */
4861 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4862 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4863 
4864 /* reg_ppcnt_rx_frames
4865  * Access: RO
4866  */
4867 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4868 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4869 
4870 /* reg_ppcnt_tx_octets
4871  * Access: RO
4872  */
4873 MLXSW_ITEM64(reg, ppcnt, tx_octets,
4874 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4875 
4876 /* reg_ppcnt_tx_frames
4877  * Access: RO
4878  */
4879 MLXSW_ITEM64(reg, ppcnt, tx_frames,
4880 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4881 
4882 /* reg_ppcnt_rx_pause
4883  * Access: RO
4884  */
4885 MLXSW_ITEM64(reg, ppcnt, rx_pause,
4886 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4887 
4888 /* reg_ppcnt_rx_pause_duration
4889  * Access: RO
4890  */
4891 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
4892 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4893 
4894 /* reg_ppcnt_tx_pause
4895  * Access: RO
4896  */
4897 MLXSW_ITEM64(reg, ppcnt, tx_pause,
4898 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4899 
4900 /* reg_ppcnt_tx_pause_duration
4901  * Access: RO
4902  */
4903 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
4904 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4905 
4906 /* reg_ppcnt_rx_pause_transition
4907  * Access: RO
4908  */
4909 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
4910 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4911 
4912 /* Ethernet Per Traffic Group Counters */
4913 
4914 /* reg_ppcnt_tc_transmit_queue
4915  * Contains the transmit queue depth in cells of traffic class
4916  * selected by prio_tc and the port selected by local_port.
4917  * The field cannot be cleared.
4918  * Access: RO
4919  */
4920 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
4921 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4922 
4923 /* reg_ppcnt_tc_no_buffer_discard_uc
4924  * The number of unicast packets dropped due to lack of shared
4925  * buffer resources.
4926  * Access: RO
4927  */
4928 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
4929 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4930 
4931 /* Ethernet Per Traffic Class Congestion Group Counters */
4932 
4933 /* reg_ppcnt_wred_discard
4934  * Access: RO
4935  */
4936 MLXSW_ITEM64(reg, ppcnt, wred_discard,
4937 	     MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4938 
4939 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
4940 					enum mlxsw_reg_ppcnt_grp grp,
4941 					u8 prio_tc)
4942 {
4943 	MLXSW_REG_ZERO(ppcnt, payload);
4944 	mlxsw_reg_ppcnt_swid_set(payload, 0);
4945 	mlxsw_reg_ppcnt_local_port_set(payload, local_port);
4946 	mlxsw_reg_ppcnt_pnat_set(payload, 0);
4947 	mlxsw_reg_ppcnt_grp_set(payload, grp);
4948 	mlxsw_reg_ppcnt_clr_set(payload, 0);
4949 	mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
4950 }
4951 
4952 /* PLIB - Port Local to InfiniBand Port
4953  * ------------------------------------
4954  * The PLIB register performs mapping from Local Port into InfiniBand Port.
4955  */
4956 #define MLXSW_REG_PLIB_ID 0x500A
4957 #define MLXSW_REG_PLIB_LEN 0x10
4958 
4959 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
4960 
4961 /* reg_plib_local_port
4962  * Local port number.
4963  * Access: Index
4964  */
4965 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
4966 
4967 /* reg_plib_ib_port
4968  * InfiniBand port remapping for local_port.
4969  * Access: RW
4970  */
4971 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
4972 
4973 /* PPTB - Port Prio To Buffer Register
4974  * -----------------------------------
4975  * Configures the switch priority to buffer table.
4976  */
4977 #define MLXSW_REG_PPTB_ID 0x500B
4978 #define MLXSW_REG_PPTB_LEN 0x10
4979 
4980 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
4981 
4982 enum {
4983 	MLXSW_REG_PPTB_MM_UM,
4984 	MLXSW_REG_PPTB_MM_UNICAST,
4985 	MLXSW_REG_PPTB_MM_MULTICAST,
4986 };
4987 
4988 /* reg_pptb_mm
4989  * Mapping mode.
4990  * 0 - Map both unicast and multicast packets to the same buffer.
4991  * 1 - Map only unicast packets.
4992  * 2 - Map only multicast packets.
4993  * Access: Index
4994  *
4995  * Note: SwitchX-2 only supports the first option.
4996  */
4997 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
4998 
4999 /* reg_pptb_local_port
5000  * Local port number.
5001  * Access: Index
5002  */
5003 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5004 
5005 /* reg_pptb_um
5006  * Enables the update of the untagged_buf field.
5007  * Access: RW
5008  */
5009 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5010 
5011 /* reg_pptb_pm
5012  * Enables the update of the prio_to_buff field.
5013  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5014  * Access: RW
5015  */
5016 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5017 
5018 /* reg_pptb_prio_to_buff
5019  * Mapping of switch priority <i> to one of the allocated receive port
5020  * buffers.
5021  * Access: RW
5022  */
5023 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5024 
5025 /* reg_pptb_pm_msb
5026  * Enables the update of the prio_to_buff field.
5027  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5028  * Access: RW
5029  */
5030 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5031 
5032 /* reg_pptb_untagged_buff
5033  * Mapping of untagged frames to one of the allocated receive port buffers.
5034  * Access: RW
5035  *
5036  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5037  * Spectrum, as it maps untagged packets based on the default switch priority.
5038  */
5039 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5040 
5041 /* reg_pptb_prio_to_buff_msb
5042  * Mapping of switch priority <i+8> to one of the allocated receive port
5043  * buffers.
5044  * Access: RW
5045  */
5046 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5047 
5048 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5049 
5050 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5051 {
5052 	MLXSW_REG_ZERO(pptb, payload);
5053 	mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5054 	mlxsw_reg_pptb_local_port_set(payload, local_port);
5055 	mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5056 	mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5057 }
5058 
5059 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5060 						    u8 buff)
5061 {
5062 	mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5063 	mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5064 }
5065 
5066 /* PBMC - Port Buffer Management Control Register
5067  * ----------------------------------------------
5068  * The PBMC register configures and retrieves the port packet buffer
5069  * allocation for different Prios, and the Pause threshold management.
5070  */
5071 #define MLXSW_REG_PBMC_ID 0x500C
5072 #define MLXSW_REG_PBMC_LEN 0x6C
5073 
5074 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5075 
5076 /* reg_pbmc_local_port
5077  * Local port number.
5078  * Access: Index
5079  */
5080 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5081 
5082 /* reg_pbmc_xoff_timer_value
5083  * When device generates a pause frame, it uses this value as the pause
5084  * timer (time for the peer port to pause in quota-512 bit time).
5085  * Access: RW
5086  */
5087 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5088 
5089 /* reg_pbmc_xoff_refresh
5090  * The time before a new pause frame should be sent to refresh the pause RW
5091  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5092  * time).
5093  * Access: RW
5094  */
5095 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5096 
5097 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5098 
5099 /* reg_pbmc_buf_lossy
5100  * The field indicates if the buffer is lossy.
5101  * 0 - Lossless
5102  * 1 - Lossy
5103  * Access: RW
5104  */
5105 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5106 
5107 /* reg_pbmc_buf_epsb
5108  * Eligible for Port Shared buffer.
5109  * If epsb is set, packets assigned to buffer are allowed to insert the port
5110  * shared buffer.
5111  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5112  * Access: RW
5113  */
5114 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5115 
5116 /* reg_pbmc_buf_size
5117  * The part of the packet buffer array is allocated for the specific buffer.
5118  * Units are represented in cells.
5119  * Access: RW
5120  */
5121 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5122 
5123 /* reg_pbmc_buf_xoff_threshold
5124  * Once the amount of data in the buffer goes above this value, device
5125  * starts sending PFC frames for all priorities associated with the
5126  * buffer. Units are represented in cells. Reserved in case of lossy
5127  * buffer.
5128  * Access: RW
5129  *
5130  * Note: In Spectrum, reserved for buffer[9].
5131  */
5132 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5133 		     0x08, 0x04, false);
5134 
5135 /* reg_pbmc_buf_xon_threshold
5136  * When the amount of data in the buffer goes below this value, device
5137  * stops sending PFC frames for the priorities associated with the
5138  * buffer. Units are represented in cells. Reserved in case of lossy
5139  * buffer.
5140  * Access: RW
5141  *
5142  * Note: In Spectrum, reserved for buffer[9].
5143  */
5144 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5145 		     0x08, 0x04, false);
5146 
5147 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5148 				       u16 xoff_timer_value, u16 xoff_refresh)
5149 {
5150 	MLXSW_REG_ZERO(pbmc, payload);
5151 	mlxsw_reg_pbmc_local_port_set(payload, local_port);
5152 	mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5153 	mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5154 }
5155 
5156 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5157 						    int buf_index,
5158 						    u16 size)
5159 {
5160 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5161 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5162 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5163 }
5164 
5165 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5166 						       int buf_index, u16 size,
5167 						       u16 threshold)
5168 {
5169 	mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5170 	mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5171 	mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5172 	mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5173 	mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5174 }
5175 
5176 /* PSPA - Port Switch Partition Allocation
5177  * ---------------------------------------
5178  * Controls the association of a port with a switch partition and enables
5179  * configuring ports as stacking ports.
5180  */
5181 #define MLXSW_REG_PSPA_ID 0x500D
5182 #define MLXSW_REG_PSPA_LEN 0x8
5183 
5184 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5185 
5186 /* reg_pspa_swid
5187  * Switch partition ID.
5188  * Access: RW
5189  */
5190 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5191 
5192 /* reg_pspa_local_port
5193  * Local port number.
5194  * Access: Index
5195  */
5196 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5197 
5198 /* reg_pspa_sub_port
5199  * Virtual port within the local port. Set to 0 when virtual ports are
5200  * disabled on the local port.
5201  * Access: Index
5202  */
5203 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5204 
5205 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5206 {
5207 	MLXSW_REG_ZERO(pspa, payload);
5208 	mlxsw_reg_pspa_swid_set(payload, swid);
5209 	mlxsw_reg_pspa_local_port_set(payload, local_port);
5210 	mlxsw_reg_pspa_sub_port_set(payload, 0);
5211 }
5212 
5213 /* PPLR - Port Physical Loopback Register
5214  * --------------------------------------
5215  * This register allows configuration of the port's loopback mode.
5216  */
5217 #define MLXSW_REG_PPLR_ID 0x5018
5218 #define MLXSW_REG_PPLR_LEN 0x8
5219 
5220 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5221 
5222 /* reg_pplr_local_port
5223  * Local port number.
5224  * Access: Index
5225  */
5226 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5227 
5228 /* Phy local loopback. When set the port's egress traffic is looped back
5229  * to the receiver and the port transmitter is disabled.
5230  */
5231 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5232 
5233 /* reg_pplr_lb_en
5234  * Loopback enable.
5235  * Access: RW
5236  */
5237 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5238 
5239 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5240 				       bool phy_local)
5241 {
5242 	MLXSW_REG_ZERO(pplr, payload);
5243 	mlxsw_reg_pplr_local_port_set(payload, local_port);
5244 	mlxsw_reg_pplr_lb_en_set(payload,
5245 				 phy_local ?
5246 				 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5247 }
5248 
5249 /* HTGT - Host Trap Group Table
5250  * ----------------------------
5251  * Configures the properties for forwarding to CPU.
5252  */
5253 #define MLXSW_REG_HTGT_ID 0x7002
5254 #define MLXSW_REG_HTGT_LEN 0x20
5255 
5256 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5257 
5258 /* reg_htgt_swid
5259  * Switch partition ID.
5260  * Access: Index
5261  */
5262 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5263 
5264 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0	/* For locally attached CPU */
5265 
5266 /* reg_htgt_type
5267  * CPU path type.
5268  * Access: RW
5269  */
5270 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5271 
5272 enum mlxsw_reg_htgt_trap_group {
5273 	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5274 	MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5275 	MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5276 	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5277 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5278 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5279 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5280 	MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5281 	MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5282 	MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5283 	MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5284 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5285 	MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5286 	MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5287 	MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5288 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5289 	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5290 	MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5291 	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5292 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5293 	MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5294 	MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5295 };
5296 
5297 /* reg_htgt_trap_group
5298  * Trap group number. User defined number specifying which trap groups
5299  * should be forwarded to the CPU. The mapping between trap IDs and trap
5300  * groups is configured using HPKT register.
5301  * Access: Index
5302  */
5303 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5304 
5305 enum {
5306 	MLXSW_REG_HTGT_POLICER_DISABLE,
5307 	MLXSW_REG_HTGT_POLICER_ENABLE,
5308 };
5309 
5310 /* reg_htgt_pide
5311  * Enable policer ID specified using 'pid' field.
5312  * Access: RW
5313  */
5314 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5315 
5316 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5317 
5318 /* reg_htgt_pid
5319  * Policer ID for the trap group.
5320  * Access: RW
5321  */
5322 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5323 
5324 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5325 
5326 /* reg_htgt_mirror_action
5327  * Mirror action to use.
5328  * 0 - Trap to CPU.
5329  * 1 - Trap to CPU and mirror to a mirroring agent.
5330  * 2 - Mirror to a mirroring agent and do not trap to CPU.
5331  * Access: RW
5332  *
5333  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
5334  */
5335 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5336 
5337 /* reg_htgt_mirroring_agent
5338  * Mirroring agent.
5339  * Access: RW
5340  */
5341 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5342 
5343 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5344 
5345 /* reg_htgt_priority
5346  * Trap group priority.
5347  * In case a packet matches multiple classification rules, the packet will
5348  * only be trapped once, based on the trap ID associated with the group (via
5349  * register HPKT) with the highest priority.
5350  * Supported values are 0-7, with 7 represnting the highest priority.
5351  * Access: RW
5352  *
5353  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
5354  * by the 'trap_group' field.
5355  */
5356 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5357 
5358 #define MLXSW_REG_HTGT_DEFAULT_TC 7
5359 
5360 /* reg_htgt_local_path_cpu_tclass
5361  * CPU ingress traffic class for the trap group.
5362  * Access: RW
5363  */
5364 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5365 
5366 enum mlxsw_reg_htgt_local_path_rdq {
5367 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5368 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5369 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5370 	MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5371 };
5372 /* reg_htgt_local_path_rdq
5373  * Receive descriptor queue (RDQ) to use for the trap group.
5374  * Access: RW
5375  */
5376 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5377 
5378 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5379 				       u8 priority, u8 tc)
5380 {
5381 	MLXSW_REG_ZERO(htgt, payload);
5382 
5383 	if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5384 		mlxsw_reg_htgt_pide_set(payload,
5385 					MLXSW_REG_HTGT_POLICER_DISABLE);
5386 	} else {
5387 		mlxsw_reg_htgt_pide_set(payload,
5388 					MLXSW_REG_HTGT_POLICER_ENABLE);
5389 		mlxsw_reg_htgt_pid_set(payload, policer_id);
5390 	}
5391 
5392 	mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5393 	mlxsw_reg_htgt_trap_group_set(payload, group);
5394 	mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5395 	mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5396 	mlxsw_reg_htgt_priority_set(payload, priority);
5397 	mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5398 	mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5399 }
5400 
5401 /* HPKT - Host Packet Trap
5402  * -----------------------
5403  * Configures trap IDs inside trap groups.
5404  */
5405 #define MLXSW_REG_HPKT_ID 0x7003
5406 #define MLXSW_REG_HPKT_LEN 0x10
5407 
5408 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5409 
5410 enum {
5411 	MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5412 	MLXSW_REG_HPKT_ACK_REQUIRED,
5413 };
5414 
5415 /* reg_hpkt_ack
5416  * Require acknowledgements from the host for events.
5417  * If set, then the device will wait for the event it sent to be acknowledged
5418  * by the host. This option is only relevant for event trap IDs.
5419  * Access: RW
5420  *
5421  * Note: Currently not supported by firmware.
5422  */
5423 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5424 
5425 enum mlxsw_reg_hpkt_action {
5426 	MLXSW_REG_HPKT_ACTION_FORWARD,
5427 	MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5428 	MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5429 	MLXSW_REG_HPKT_ACTION_DISCARD,
5430 	MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5431 	MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5432 };
5433 
5434 /* reg_hpkt_action
5435  * Action to perform on packet when trapped.
5436  * 0 - No action. Forward to CPU based on switching rules.
5437  * 1 - Trap to CPU (CPU receives sole copy).
5438  * 2 - Mirror to CPU (CPU receives a replica of the packet).
5439  * 3 - Discard.
5440  * 4 - Soft discard (allow other traps to act on the packet).
5441  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
5442  * Access: RW
5443  *
5444  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
5445  * addressed to the CPU.
5446  */
5447 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5448 
5449 /* reg_hpkt_trap_group
5450  * Trap group to associate the trap with.
5451  * Access: RW
5452  */
5453 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5454 
5455 /* reg_hpkt_trap_id
5456  * Trap ID.
5457  * Access: Index
5458  *
5459  * Note: A trap ID can only be associated with a single trap group. The device
5460  * will associate the trap ID with the last trap group configured.
5461  */
5462 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5463 
5464 enum {
5465 	MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5466 	MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5467 	MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5468 };
5469 
5470 /* reg_hpkt_ctrl
5471  * Configure dedicated buffer resources for control packets.
5472  * Ignored by SwitchX-2.
5473  * 0 - Keep factory defaults.
5474  * 1 - Do not use control buffer for this trap ID.
5475  * 2 - Use control buffer for this trap ID.
5476  * Access: RW
5477  */
5478 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5479 
5480 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5481 				       enum mlxsw_reg_htgt_trap_group trap_group,
5482 				       bool is_ctrl)
5483 {
5484 	MLXSW_REG_ZERO(hpkt, payload);
5485 	mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5486 	mlxsw_reg_hpkt_action_set(payload, action);
5487 	mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5488 	mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5489 	mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5490 				MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5491 				MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5492 }
5493 
5494 /* RGCR - Router General Configuration Register
5495  * --------------------------------------------
5496  * The register is used for setting up the router configuration.
5497  */
5498 #define MLXSW_REG_RGCR_ID 0x8001
5499 #define MLXSW_REG_RGCR_LEN 0x28
5500 
5501 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5502 
5503 /* reg_rgcr_ipv4_en
5504  * IPv4 router enable.
5505  * Access: RW
5506  */
5507 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5508 
5509 /* reg_rgcr_ipv6_en
5510  * IPv6 router enable.
5511  * Access: RW
5512  */
5513 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5514 
5515 /* reg_rgcr_max_router_interfaces
5516  * Defines the maximum number of active router interfaces for all virtual
5517  * routers.
5518  * Access: RW
5519  */
5520 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5521 
5522 /* reg_rgcr_usp
5523  * Update switch priority and packet color.
5524  * 0 - Preserve the value of Switch Priority and packet color.
5525  * 1 - Recalculate the value of Switch Priority and packet color.
5526  * Access: RW
5527  *
5528  * Note: Not supported by SwitchX and SwitchX-2.
5529  */
5530 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5531 
5532 /* reg_rgcr_pcp_rw
5533  * Indicates how to handle the pcp_rewrite_en value:
5534  * 0 - Preserve the value of pcp_rewrite_en.
5535  * 2 - Disable PCP rewrite.
5536  * 3 - Enable PCP rewrite.
5537  * Access: RW
5538  *
5539  * Note: Not supported by SwitchX and SwitchX-2.
5540  */
5541 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5542 
5543 /* reg_rgcr_activity_dis
5544  * Activity disable:
5545  * 0 - Activity will be set when an entry is hit (default).
5546  * 1 - Activity will not be set when an entry is hit.
5547  *
5548  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5549  * (RALUE).
5550  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5551  * Entry (RAUHT).
5552  * Bits 2:7 are reserved.
5553  * Access: RW
5554  *
5555  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5556  */
5557 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5558 
5559 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5560 				       bool ipv6_en)
5561 {
5562 	MLXSW_REG_ZERO(rgcr, payload);
5563 	mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5564 	mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5565 }
5566 
5567 /* RITR - Router Interface Table Register
5568  * --------------------------------------
5569  * The register is used to configure the router interface table.
5570  */
5571 #define MLXSW_REG_RITR_ID 0x8002
5572 #define MLXSW_REG_RITR_LEN 0x40
5573 
5574 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5575 
5576 /* reg_ritr_enable
5577  * Enables routing on the router interface.
5578  * Access: RW
5579  */
5580 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5581 
5582 /* reg_ritr_ipv4
5583  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5584  * interface.
5585  * Access: RW
5586  */
5587 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5588 
5589 /* reg_ritr_ipv6
5590  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5591  * interface.
5592  * Access: RW
5593  */
5594 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5595 
5596 /* reg_ritr_ipv4_mc
5597  * IPv4 multicast routing enable.
5598  * Access: RW
5599  */
5600 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5601 
5602 /* reg_ritr_ipv6_mc
5603  * IPv6 multicast routing enable.
5604  * Access: RW
5605  */
5606 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5607 
5608 enum mlxsw_reg_ritr_if_type {
5609 	/* VLAN interface. */
5610 	MLXSW_REG_RITR_VLAN_IF,
5611 	/* FID interface. */
5612 	MLXSW_REG_RITR_FID_IF,
5613 	/* Sub-port interface. */
5614 	MLXSW_REG_RITR_SP_IF,
5615 	/* Loopback Interface. */
5616 	MLXSW_REG_RITR_LOOPBACK_IF,
5617 };
5618 
5619 /* reg_ritr_type
5620  * Router interface type as per enum mlxsw_reg_ritr_if_type.
5621  * Access: RW
5622  */
5623 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5624 
5625 enum {
5626 	MLXSW_REG_RITR_RIF_CREATE,
5627 	MLXSW_REG_RITR_RIF_DEL,
5628 };
5629 
5630 /* reg_ritr_op
5631  * Opcode:
5632  * 0 - Create or edit RIF.
5633  * 1 - Delete RIF.
5634  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5635  * is not supported. An interface must be deleted and re-created in order
5636  * to update properties.
5637  * Access: WO
5638  */
5639 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5640 
5641 /* reg_ritr_rif
5642  * Router interface index. A pointer to the Router Interface Table.
5643  * Access: Index
5644  */
5645 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5646 
5647 /* reg_ritr_ipv4_fe
5648  * IPv4 Forwarding Enable.
5649  * Enables routing of IPv4 traffic on the router interface. When disabled,
5650  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5651  * Not supported in SwitchX-2.
5652  * Access: RW
5653  */
5654 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5655 
5656 /* reg_ritr_ipv6_fe
5657  * IPv6 Forwarding Enable.
5658  * Enables routing of IPv6 traffic on the router interface. When disabled,
5659  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5660  * Not supported in SwitchX-2.
5661  * Access: RW
5662  */
5663 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5664 
5665 /* reg_ritr_ipv4_mc_fe
5666  * IPv4 Multicast Forwarding Enable.
5667  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5668  * will be enabled.
5669  * Access: RW
5670  */
5671 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5672 
5673 /* reg_ritr_ipv6_mc_fe
5674  * IPv6 Multicast Forwarding Enable.
5675  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5676  * will be enabled.
5677  * Access: RW
5678  */
5679 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5680 
5681 /* reg_ritr_lb_en
5682  * Loop-back filter enable for unicast packets.
5683  * If the flag is set then loop-back filter for unicast packets is
5684  * implemented on the RIF. Multicast packets are always subject to
5685  * loop-back filtering.
5686  * Access: RW
5687  */
5688 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5689 
5690 /* reg_ritr_virtual_router
5691  * Virtual router ID associated with the router interface.
5692  * Access: RW
5693  */
5694 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5695 
5696 /* reg_ritr_mtu
5697  * Router interface MTU.
5698  * Access: RW
5699  */
5700 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5701 
5702 /* reg_ritr_if_swid
5703  * Switch partition ID.
5704  * Access: RW
5705  */
5706 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5707 
5708 /* reg_ritr_if_mac
5709  * Router interface MAC address.
5710  * In Spectrum, all MAC addresses must have the same 38 MSBits.
5711  * Access: RW
5712  */
5713 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5714 
5715 /* reg_ritr_if_vrrp_id_ipv6
5716  * VRRP ID for IPv6
5717  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5718  * Access: RW
5719  */
5720 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5721 
5722 /* reg_ritr_if_vrrp_id_ipv4
5723  * VRRP ID for IPv4
5724  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5725  * Access: RW
5726  */
5727 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5728 
5729 /* VLAN Interface */
5730 
5731 /* reg_ritr_vlan_if_vid
5732  * VLAN ID.
5733  * Access: RW
5734  */
5735 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5736 
5737 /* FID Interface */
5738 
5739 /* reg_ritr_fid_if_fid
5740  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5741  * the vFID range are supported.
5742  * Access: RW
5743  */
5744 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5745 
5746 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5747 					  enum mlxsw_reg_ritr_if_type rif_type,
5748 					  u16 fid)
5749 {
5750 	if (rif_type == MLXSW_REG_RITR_FID_IF)
5751 		mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5752 	else
5753 		mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5754 }
5755 
5756 /* Sub-port Interface */
5757 
5758 /* reg_ritr_sp_if_lag
5759  * LAG indication. When this bit is set the system_port field holds the
5760  * LAG identifier.
5761  * Access: RW
5762  */
5763 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5764 
5765 /* reg_ritr_sp_system_port
5766  * Port unique indentifier. When lag bit is set, this field holds the
5767  * lag_id in bits 0:9.
5768  * Access: RW
5769  */
5770 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5771 
5772 /* reg_ritr_sp_if_vid
5773  * VLAN ID.
5774  * Access: RW
5775  */
5776 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5777 
5778 /* Loopback Interface */
5779 
5780 enum mlxsw_reg_ritr_loopback_protocol {
5781 	/* IPinIP IPv4 underlay Unicast */
5782 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5783 	/* IPinIP IPv6 underlay Unicast */
5784 	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5785 	/* IPinIP generic - used for Spectrum-2 underlay RIF */
5786 	MLXSW_REG_RITR_LOOPBACK_GENERIC,
5787 };
5788 
5789 /* reg_ritr_loopback_protocol
5790  * Access: RW
5791  */
5792 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5793 
5794 enum mlxsw_reg_ritr_loopback_ipip_type {
5795 	/* Tunnel is IPinIP. */
5796 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5797 	/* Tunnel is GRE, no key. */
5798 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5799 	/* Tunnel is GRE, with a key. */
5800 	MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5801 };
5802 
5803 /* reg_ritr_loopback_ipip_type
5804  * Encapsulation type.
5805  * Access: RW
5806  */
5807 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5808 
5809 enum mlxsw_reg_ritr_loopback_ipip_options {
5810 	/* The key is defined by gre_key. */
5811 	MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5812 };
5813 
5814 /* reg_ritr_loopback_ipip_options
5815  * Access: RW
5816  */
5817 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5818 
5819 /* reg_ritr_loopback_ipip_uvr
5820  * Underlay Virtual Router ID.
5821  * Range is 0..cap_max_virtual_routers-1.
5822  * Reserved for Spectrum-2.
5823  * Access: RW
5824  */
5825 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5826 
5827 /* reg_ritr_loopback_ipip_underlay_rif
5828  * Underlay ingress router interface.
5829  * Reserved for Spectrum.
5830  * Access: RW
5831  */
5832 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5833 
5834 /* reg_ritr_loopback_ipip_usip*
5835  * Encapsulation Underlay source IP.
5836  * Access: RW
5837  */
5838 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5839 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5840 
5841 /* reg_ritr_loopback_ipip_gre_key
5842  * GRE Key.
5843  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5844  * Access: RW
5845  */
5846 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5847 
5848 /* Shared between ingress/egress */
5849 enum mlxsw_reg_ritr_counter_set_type {
5850 	/* No Count. */
5851 	MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5852 	/* Basic. Used for router interfaces, counting the following:
5853 	 *	- Error and Discard counters.
5854 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
5855 	 *	  same set of counters for the different type of traffic
5856 	 *	  (IPv4, IPv6 and mpls).
5857 	 */
5858 	MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5859 };
5860 
5861 /* reg_ritr_ingress_counter_index
5862  * Counter Index for flow counter.
5863  * Access: RW
5864  */
5865 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5866 
5867 /* reg_ritr_ingress_counter_set_type
5868  * Igress Counter Set Type for router interface counter.
5869  * Access: RW
5870  */
5871 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
5872 
5873 /* reg_ritr_egress_counter_index
5874  * Counter Index for flow counter.
5875  * Access: RW
5876  */
5877 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
5878 
5879 /* reg_ritr_egress_counter_set_type
5880  * Egress Counter Set Type for router interface counter.
5881  * Access: RW
5882  */
5883 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
5884 
5885 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
5886 					       bool enable, bool egress)
5887 {
5888 	enum mlxsw_reg_ritr_counter_set_type set_type;
5889 
5890 	if (enable)
5891 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
5892 	else
5893 		set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
5894 	mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
5895 
5896 	if (egress)
5897 		mlxsw_reg_ritr_egress_counter_index_set(payload, index);
5898 	else
5899 		mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
5900 }
5901 
5902 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
5903 {
5904 	MLXSW_REG_ZERO(ritr, payload);
5905 	mlxsw_reg_ritr_rif_set(payload, rif);
5906 }
5907 
5908 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
5909 					     u16 system_port, u16 vid)
5910 {
5911 	mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
5912 	mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
5913 	mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
5914 }
5915 
5916 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
5917 				       enum mlxsw_reg_ritr_if_type type,
5918 				       u16 rif, u16 vr_id, u16 mtu)
5919 {
5920 	bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
5921 
5922 	MLXSW_REG_ZERO(ritr, payload);
5923 	mlxsw_reg_ritr_enable_set(payload, enable);
5924 	mlxsw_reg_ritr_ipv4_set(payload, 1);
5925 	mlxsw_reg_ritr_ipv6_set(payload, 1);
5926 	mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
5927 	mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
5928 	mlxsw_reg_ritr_type_set(payload, type);
5929 	mlxsw_reg_ritr_op_set(payload, op);
5930 	mlxsw_reg_ritr_rif_set(payload, rif);
5931 	mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
5932 	mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
5933 	mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
5934 	mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
5935 	mlxsw_reg_ritr_lb_en_set(payload, 1);
5936 	mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
5937 	mlxsw_reg_ritr_mtu_set(payload, mtu);
5938 }
5939 
5940 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
5941 {
5942 	mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
5943 }
5944 
5945 static inline void
5946 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
5947 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5948 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
5949 			    u16 uvr_id, u16 underlay_rif, u32 gre_key)
5950 {
5951 	mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
5952 	mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
5953 	mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
5954 	mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
5955 	mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
5956 }
5957 
5958 static inline void
5959 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
5960 			    enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5961 			    enum mlxsw_reg_ritr_loopback_ipip_options options,
5962 			    u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
5963 {
5964 	mlxsw_reg_ritr_loopback_protocol_set(payload,
5965 				    MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
5966 	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
5967 						 uvr_id, underlay_rif, gre_key);
5968 	mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
5969 }
5970 
5971 /* RTAR - Router TCAM Allocation Register
5972  * --------------------------------------
5973  * This register is used for allocation of regions in the TCAM table.
5974  */
5975 #define MLXSW_REG_RTAR_ID 0x8004
5976 #define MLXSW_REG_RTAR_LEN 0x20
5977 
5978 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
5979 
5980 enum mlxsw_reg_rtar_op {
5981 	MLXSW_REG_RTAR_OP_ALLOCATE,
5982 	MLXSW_REG_RTAR_OP_RESIZE,
5983 	MLXSW_REG_RTAR_OP_DEALLOCATE,
5984 };
5985 
5986 /* reg_rtar_op
5987  * Access: WO
5988  */
5989 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
5990 
5991 enum mlxsw_reg_rtar_key_type {
5992 	MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
5993 	MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
5994 };
5995 
5996 /* reg_rtar_key_type
5997  * TCAM key type for the region.
5998  * Access: WO
5999  */
6000 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6001 
6002 /* reg_rtar_region_size
6003  * TCAM region size. When allocating/resizing this is the requested
6004  * size, the response is the actual size.
6005  * Note: Actual size may be larger than requested.
6006  * Reserved for op = Deallocate
6007  * Access: WO
6008  */
6009 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6010 
6011 static inline void mlxsw_reg_rtar_pack(char *payload,
6012 				       enum mlxsw_reg_rtar_op op,
6013 				       enum mlxsw_reg_rtar_key_type key_type,
6014 				       u16 region_size)
6015 {
6016 	MLXSW_REG_ZERO(rtar, payload);
6017 	mlxsw_reg_rtar_op_set(payload, op);
6018 	mlxsw_reg_rtar_key_type_set(payload, key_type);
6019 	mlxsw_reg_rtar_region_size_set(payload, region_size);
6020 }
6021 
6022 /* RATR - Router Adjacency Table Register
6023  * --------------------------------------
6024  * The RATR register is used to configure the Router Adjacency (next-hop)
6025  * Table.
6026  */
6027 #define MLXSW_REG_RATR_ID 0x8008
6028 #define MLXSW_REG_RATR_LEN 0x2C
6029 
6030 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6031 
6032 enum mlxsw_reg_ratr_op {
6033 	/* Read */
6034 	MLXSW_REG_RATR_OP_QUERY_READ = 0,
6035 	/* Read and clear activity */
6036 	MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6037 	/* Write Adjacency entry */
6038 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6039 	/* Write Adjacency entry only if the activity is cleared.
6040 	 * The write may not succeed if the activity is set. There is not
6041 	 * direct feedback if the write has succeeded or not, however
6042 	 * the get will reveal the actual entry (SW can compare the get
6043 	 * response to the set command).
6044 	 */
6045 	MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6046 };
6047 
6048 /* reg_ratr_op
6049  * Note that Write operation may also be used for updating
6050  * counter_set_type and counter_index. In this case all other
6051  * fields must not be updated.
6052  * Access: OP
6053  */
6054 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6055 
6056 /* reg_ratr_v
6057  * Valid bit. Indicates if the adjacency entry is valid.
6058  * Note: the device may need some time before reusing an invalidated
6059  * entry. During this time the entry can not be reused. It is
6060  * recommended to use another entry before reusing an invalidated
6061  * entry (e.g. software can put it at the end of the list for
6062  * reusing). Trying to access an invalidated entry not yet cleared
6063  * by the device results with failure indicating "Try Again" status.
6064  * When valid is '0' then egress_router_interface,trap_action,
6065  * adjacency_parameters and counters are reserved
6066  * Access: RW
6067  */
6068 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6069 
6070 /* reg_ratr_a
6071  * Activity. Set for new entries. Set if a packet lookup has hit on
6072  * the specific entry. To clear the a bit, use "clear activity".
6073  * Access: RO
6074  */
6075 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6076 
6077 enum mlxsw_reg_ratr_type {
6078 	/* Ethernet */
6079 	MLXSW_REG_RATR_TYPE_ETHERNET,
6080 	/* IPoIB Unicast without GRH.
6081 	 * Reserved for Spectrum.
6082 	 */
6083 	MLXSW_REG_RATR_TYPE_IPOIB_UC,
6084 	/* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
6085 	 * adjacency).
6086 	 * Reserved for Spectrum.
6087 	 */
6088 	MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6089 	/* IPoIB Multicast.
6090 	 * Reserved for Spectrum.
6091 	 */
6092 	MLXSW_REG_RATR_TYPE_IPOIB_MC,
6093 	/* MPLS.
6094 	 * Reserved for SwitchX/-2.
6095 	 */
6096 	MLXSW_REG_RATR_TYPE_MPLS,
6097 	/* IPinIP Encap.
6098 	 * Reserved for SwitchX/-2.
6099 	 */
6100 	MLXSW_REG_RATR_TYPE_IPIP,
6101 };
6102 
6103 /* reg_ratr_type
6104  * Adjacency entry type.
6105  * Access: RW
6106  */
6107 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6108 
6109 /* reg_ratr_adjacency_index_low
6110  * Bits 15:0 of index into the adjacency table.
6111  * For SwitchX and SwitchX-2, the adjacency table is linear and
6112  * used for adjacency entries only.
6113  * For Spectrum, the index is to the KVD linear.
6114  * Access: Index
6115  */
6116 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6117 
6118 /* reg_ratr_egress_router_interface
6119  * Range is 0 .. cap_max_router_interfaces - 1
6120  * Access: RW
6121  */
6122 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6123 
6124 enum mlxsw_reg_ratr_trap_action {
6125 	MLXSW_REG_RATR_TRAP_ACTION_NOP,
6126 	MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6127 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6128 	MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6129 	MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6130 };
6131 
6132 /* reg_ratr_trap_action
6133  * see mlxsw_reg_ratr_trap_action
6134  * Access: RW
6135  */
6136 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6137 
6138 /* reg_ratr_adjacency_index_high
6139  * Bits 23:16 of the adjacency_index.
6140  * Access: Index
6141  */
6142 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6143 
6144 enum mlxsw_reg_ratr_trap_id {
6145 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6146 	MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6147 };
6148 
6149 /* reg_ratr_trap_id
6150  * Trap ID to be reported to CPU.
6151  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6152  * For trap_action of NOP, MIRROR and DISCARD_ERROR
6153  * Access: RW
6154  */
6155 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6156 
6157 /* reg_ratr_eth_destination_mac
6158  * MAC address of the destination next-hop.
6159  * Access: RW
6160  */
6161 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6162 
6163 enum mlxsw_reg_ratr_ipip_type {
6164 	/* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
6165 	MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6166 	/* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
6167 	MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6168 };
6169 
6170 /* reg_ratr_ipip_type
6171  * Underlay destination ip type.
6172  * Note: the type field must match the protocol of the router interface.
6173  * Access: RW
6174  */
6175 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6176 
6177 /* reg_ratr_ipip_ipv4_udip
6178  * Underlay ipv4 dip.
6179  * Reserved when ipip_type is IPv6.
6180  * Access: RW
6181  */
6182 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6183 
6184 /* reg_ratr_ipip_ipv6_ptr
6185  * Pointer to IPv6 underlay destination ip address.
6186  * For Spectrum: Pointer to KVD linear space.
6187  * Access: RW
6188  */
6189 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6190 
6191 enum mlxsw_reg_flow_counter_set_type {
6192 	/* No count */
6193 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6194 	/* Count packets and bytes */
6195 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6196 	/* Count only packets */
6197 	MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6198 };
6199 
6200 /* reg_ratr_counter_set_type
6201  * Counter set type for flow counters
6202  * Access: RW
6203  */
6204 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6205 
6206 /* reg_ratr_counter_index
6207  * Counter index for flow counters
6208  * Access: RW
6209  */
6210 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6211 
6212 static inline void
6213 mlxsw_reg_ratr_pack(char *payload,
6214 		    enum mlxsw_reg_ratr_op op, bool valid,
6215 		    enum mlxsw_reg_ratr_type type,
6216 		    u32 adjacency_index, u16 egress_rif)
6217 {
6218 	MLXSW_REG_ZERO(ratr, payload);
6219 	mlxsw_reg_ratr_op_set(payload, op);
6220 	mlxsw_reg_ratr_v_set(payload, valid);
6221 	mlxsw_reg_ratr_type_set(payload, type);
6222 	mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6223 	mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6224 	mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6225 }
6226 
6227 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6228 						 const char *dest_mac)
6229 {
6230 	mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6231 }
6232 
6233 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6234 {
6235 	mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6236 	mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6237 }
6238 
6239 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6240 					       bool counter_enable)
6241 {
6242 	enum mlxsw_reg_flow_counter_set_type set_type;
6243 
6244 	if (counter_enable)
6245 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6246 	else
6247 		set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6248 
6249 	mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6250 	mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6251 }
6252 
6253 /* RDPM - Router DSCP to Priority Mapping
6254  * --------------------------------------
6255  * Controls the mapping from DSCP field to switch priority on routed packets
6256  */
6257 #define MLXSW_REG_RDPM_ID 0x8009
6258 #define MLXSW_REG_RDPM_BASE_LEN 0x00
6259 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6260 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6261 #define MLXSW_REG_RDPM_LEN 0x40
6262 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6263 				   MLXSW_REG_RDPM_LEN - \
6264 				   MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6265 
6266 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6267 
6268 /* reg_dscp_entry_e
6269  * Enable update of the specific entry
6270  * Access: Index
6271  */
6272 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6273 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6274 
6275 /* reg_dscp_entry_prio
6276  * Switch Priority
6277  * Access: RW
6278  */
6279 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6280 		    -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6281 
6282 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6283 				       u8 prio)
6284 {
6285 	mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6286 	mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6287 }
6288 
6289 /* RICNT - Router Interface Counter Register
6290  * -----------------------------------------
6291  * The RICNT register retrieves per port performance counters
6292  */
6293 #define MLXSW_REG_RICNT_ID 0x800B
6294 #define MLXSW_REG_RICNT_LEN 0x100
6295 
6296 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6297 
6298 /* reg_ricnt_counter_index
6299  * Counter index
6300  * Access: RW
6301  */
6302 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6303 
6304 enum mlxsw_reg_ricnt_counter_set_type {
6305 	/* No Count. */
6306 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6307 	/* Basic. Used for router interfaces, counting the following:
6308 	 *	- Error and Discard counters.
6309 	 *	- Unicast, Multicast and Broadcast counters. Sharing the
6310 	 *	  same set of counters for the different type of traffic
6311 	 *	  (IPv4, IPv6 and mpls).
6312 	 */
6313 	MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6314 };
6315 
6316 /* reg_ricnt_counter_set_type
6317  * Counter Set Type for router interface counter
6318  * Access: RW
6319  */
6320 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6321 
6322 enum mlxsw_reg_ricnt_opcode {
6323 	/* Nop. Supported only for read access*/
6324 	MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6325 	/* Clear. Setting the clr bit will reset the counter value for
6326 	 * all counters of the specified Router Interface.
6327 	 */
6328 	MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6329 };
6330 
6331 /* reg_ricnt_opcode
6332  * Opcode
6333  * Access: RW
6334  */
6335 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6336 
6337 /* reg_ricnt_good_unicast_packets
6338  * good unicast packets.
6339  * Access: RW
6340  */
6341 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6342 
6343 /* reg_ricnt_good_multicast_packets
6344  * good multicast packets.
6345  * Access: RW
6346  */
6347 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6348 
6349 /* reg_ricnt_good_broadcast_packets
6350  * good broadcast packets
6351  * Access: RW
6352  */
6353 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6354 
6355 /* reg_ricnt_good_unicast_bytes
6356  * A count of L3 data and padding octets not including L2 headers
6357  * for good unicast frames.
6358  * Access: RW
6359  */
6360 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6361 
6362 /* reg_ricnt_good_multicast_bytes
6363  * A count of L3 data and padding octets not including L2 headers
6364  * for good multicast frames.
6365  * Access: RW
6366  */
6367 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6368 
6369 /* reg_ritr_good_broadcast_bytes
6370  * A count of L3 data and padding octets not including L2 headers
6371  * for good broadcast frames.
6372  * Access: RW
6373  */
6374 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6375 
6376 /* reg_ricnt_error_packets
6377  * A count of errored frames that do not pass the router checks.
6378  * Access: RW
6379  */
6380 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6381 
6382 /* reg_ricnt_discrad_packets
6383  * A count of non-errored frames that do not pass the router checks.
6384  * Access: RW
6385  */
6386 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6387 
6388 /* reg_ricnt_error_bytes
6389  * A count of L3 data and padding octets not including L2 headers
6390  * for errored frames.
6391  * Access: RW
6392  */
6393 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6394 
6395 /* reg_ricnt_discard_bytes
6396  * A count of L3 data and padding octets not including L2 headers
6397  * for non-errored frames that do not pass the router checks.
6398  * Access: RW
6399  */
6400 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6401 
6402 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6403 					enum mlxsw_reg_ricnt_opcode op)
6404 {
6405 	MLXSW_REG_ZERO(ricnt, payload);
6406 	mlxsw_reg_ricnt_op_set(payload, op);
6407 	mlxsw_reg_ricnt_counter_index_set(payload, index);
6408 	mlxsw_reg_ricnt_counter_set_type_set(payload,
6409 					     MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6410 }
6411 
6412 /* RRCR - Router Rules Copy Register Layout
6413  * ----------------------------------------
6414  * This register is used for moving and copying route entry rules.
6415  */
6416 #define MLXSW_REG_RRCR_ID 0x800F
6417 #define MLXSW_REG_RRCR_LEN 0x24
6418 
6419 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6420 
6421 enum mlxsw_reg_rrcr_op {
6422 	/* Move rules */
6423 	MLXSW_REG_RRCR_OP_MOVE,
6424 	/* Copy rules */
6425 	MLXSW_REG_RRCR_OP_COPY,
6426 };
6427 
6428 /* reg_rrcr_op
6429  * Access: WO
6430  */
6431 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6432 
6433 /* reg_rrcr_offset
6434  * Offset within the region from which to copy/move.
6435  * Access: Index
6436  */
6437 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6438 
6439 /* reg_rrcr_size
6440  * The number of rules to copy/move.
6441  * Access: WO
6442  */
6443 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6444 
6445 /* reg_rrcr_table_id
6446  * Identifier of the table on which to perform the operation. Encoding is the
6447  * same as in RTAR.key_type
6448  * Access: Index
6449  */
6450 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6451 
6452 /* reg_rrcr_dest_offset
6453  * Offset within the region to which to copy/move
6454  * Access: Index
6455  */
6456 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6457 
6458 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6459 				       u16 offset, u16 size,
6460 				       enum mlxsw_reg_rtar_key_type table_id,
6461 				       u16 dest_offset)
6462 {
6463 	MLXSW_REG_ZERO(rrcr, payload);
6464 	mlxsw_reg_rrcr_op_set(payload, op);
6465 	mlxsw_reg_rrcr_offset_set(payload, offset);
6466 	mlxsw_reg_rrcr_size_set(payload, size);
6467 	mlxsw_reg_rrcr_table_id_set(payload, table_id);
6468 	mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6469 }
6470 
6471 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6472  * -------------------------------------------------------
6473  * RALTA is used to allocate the LPM trees of the SHSPM method.
6474  */
6475 #define MLXSW_REG_RALTA_ID 0x8010
6476 #define MLXSW_REG_RALTA_LEN 0x04
6477 
6478 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6479 
6480 /* reg_ralta_op
6481  * opcode (valid for Write, must be 0 on Read)
6482  * 0 - allocate a tree
6483  * 1 - deallocate a tree
6484  * Access: OP
6485  */
6486 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6487 
6488 enum mlxsw_reg_ralxx_protocol {
6489 	MLXSW_REG_RALXX_PROTOCOL_IPV4,
6490 	MLXSW_REG_RALXX_PROTOCOL_IPV6,
6491 };
6492 
6493 /* reg_ralta_protocol
6494  * Protocol.
6495  * Deallocation opcode: Reserved.
6496  * Access: RW
6497  */
6498 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6499 
6500 /* reg_ralta_tree_id
6501  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6502  * the tree identifier (managed by software).
6503  * Note that tree_id 0 is allocated for a default-route tree.
6504  * Access: Index
6505  */
6506 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6507 
6508 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6509 					enum mlxsw_reg_ralxx_protocol protocol,
6510 					u8 tree_id)
6511 {
6512 	MLXSW_REG_ZERO(ralta, payload);
6513 	mlxsw_reg_ralta_op_set(payload, !alloc);
6514 	mlxsw_reg_ralta_protocol_set(payload, protocol);
6515 	mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6516 }
6517 
6518 /* RALST - Router Algorithmic LPM Structure Tree Register
6519  * ------------------------------------------------------
6520  * RALST is used to set and query the structure of an LPM tree.
6521  * The structure of the tree must be sorted as a sorted binary tree, while
6522  * each node is a bin that is tagged as the length of the prefixes the lookup
6523  * will refer to. Therefore, bin X refers to a set of entries with prefixes
6524  * of X bits to match with the destination address. The bin 0 indicates
6525  * the default action, when there is no match of any prefix.
6526  */
6527 #define MLXSW_REG_RALST_ID 0x8011
6528 #define MLXSW_REG_RALST_LEN 0x104
6529 
6530 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6531 
6532 /* reg_ralst_root_bin
6533  * The bin number of the root bin.
6534  * 0<root_bin=<(length of IP address)
6535  * For a default-route tree configure 0xff
6536  * Access: RW
6537  */
6538 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6539 
6540 /* reg_ralst_tree_id
6541  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6542  * Access: Index
6543  */
6544 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6545 
6546 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6547 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6548 #define MLXSW_REG_RALST_BIN_COUNT 128
6549 
6550 /* reg_ralst_left_child_bin
6551  * Holding the children of the bin according to the stored tree's structure.
6552  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6553  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6554  * Access: RW
6555  */
6556 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6557 
6558 /* reg_ralst_right_child_bin
6559  * Holding the children of the bin according to the stored tree's structure.
6560  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6561  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6562  * Access: RW
6563  */
6564 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6565 		     false);
6566 
6567 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6568 {
6569 	MLXSW_REG_ZERO(ralst, payload);
6570 
6571 	/* Initialize all bins to have no left or right child */
6572 	memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6573 	       MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6574 
6575 	mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6576 	mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6577 }
6578 
6579 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6580 					    u8 left_child_bin,
6581 					    u8 right_child_bin)
6582 {
6583 	int bin_index = bin_number - 1;
6584 
6585 	mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6586 	mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6587 					    right_child_bin);
6588 }
6589 
6590 /* RALTB - Router Algorithmic LPM Tree Binding Register
6591  * ----------------------------------------------------
6592  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6593  */
6594 #define MLXSW_REG_RALTB_ID 0x8012
6595 #define MLXSW_REG_RALTB_LEN 0x04
6596 
6597 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6598 
6599 /* reg_raltb_virtual_router
6600  * Virtual Router ID
6601  * Range is 0..cap_max_virtual_routers-1
6602  * Access: Index
6603  */
6604 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6605 
6606 /* reg_raltb_protocol
6607  * Protocol.
6608  * Access: Index
6609  */
6610 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6611 
6612 /* reg_raltb_tree_id
6613  * Tree to be used for the {virtual_router, protocol}
6614  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6615  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6616  * Access: RW
6617  */
6618 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6619 
6620 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6621 					enum mlxsw_reg_ralxx_protocol protocol,
6622 					u8 tree_id)
6623 {
6624 	MLXSW_REG_ZERO(raltb, payload);
6625 	mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6626 	mlxsw_reg_raltb_protocol_set(payload, protocol);
6627 	mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6628 }
6629 
6630 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6631  * -----------------------------------------------------
6632  * RALUE is used to configure and query LPM entries that serve
6633  * the Unicast protocols.
6634  */
6635 #define MLXSW_REG_RALUE_ID 0x8013
6636 #define MLXSW_REG_RALUE_LEN 0x38
6637 
6638 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6639 
6640 /* reg_ralue_protocol
6641  * Protocol.
6642  * Access: Index
6643  */
6644 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6645 
6646 enum mlxsw_reg_ralue_op {
6647 	/* Read operation. If entry doesn't exist, the operation fails. */
6648 	MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6649 	/* Clear on read operation. Used to read entry and
6650 	 * clear Activity bit.
6651 	 */
6652 	MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6653 	/* Write operation. Used to write a new entry to the table. All RW
6654 	 * fields are written for new entry. Activity bit is set
6655 	 * for new entries.
6656 	 */
6657 	MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6658 	/* Update operation. Used to update an existing route entry and
6659 	 * only update the RW fields that are detailed in the field
6660 	 * op_u_mask. If entry doesn't exist, the operation fails.
6661 	 */
6662 	MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6663 	/* Clear activity. The Activity bit (the field a) is cleared
6664 	 * for the entry.
6665 	 */
6666 	MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6667 	/* Delete operation. Used to delete an existing entry. If entry
6668 	 * doesn't exist, the operation fails.
6669 	 */
6670 	MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6671 };
6672 
6673 /* reg_ralue_op
6674  * Operation.
6675  * Access: OP
6676  */
6677 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6678 
6679 /* reg_ralue_a
6680  * Activity. Set for new entries. Set if a packet lookup has hit on the
6681  * specific entry, only if the entry is a route. To clear the a bit, use
6682  * "clear activity" op.
6683  * Enabled by activity_dis in RGCR
6684  * Access: RO
6685  */
6686 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6687 
6688 /* reg_ralue_virtual_router
6689  * Virtual Router ID
6690  * Range is 0..cap_max_virtual_routers-1
6691  * Access: Index
6692  */
6693 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6694 
6695 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE	BIT(0)
6696 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN	BIT(1)
6697 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION	BIT(2)
6698 
6699 /* reg_ralue_op_u_mask
6700  * opcode update mask.
6701  * On read operation, this field is reserved.
6702  * This field is valid for update opcode, otherwise - reserved.
6703  * This field is a bitmask of the fields that should be updated.
6704  * Access: WO
6705  */
6706 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6707 
6708 /* reg_ralue_prefix_len
6709  * Number of bits in the prefix of the LPM route.
6710  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6711  * two entries in the physical HW table.
6712  * Access: Index
6713  */
6714 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6715 
6716 /* reg_ralue_dip*
6717  * The prefix of the route or of the marker that the object of the LPM
6718  * is compared with. The most significant bits of the dip are the prefix.
6719  * The least significant bits must be '0' if the prefix_len is smaller
6720  * than 128 for IPv6 or smaller than 32 for IPv4.
6721  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6722  * Access: Index
6723  */
6724 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6725 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6726 
6727 enum mlxsw_reg_ralue_entry_type {
6728 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6729 	MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6730 	MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6731 };
6732 
6733 /* reg_ralue_entry_type
6734  * Entry type.
6735  * Note - for Marker entries, the action_type and action fields are reserved.
6736  * Access: RW
6737  */
6738 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6739 
6740 /* reg_ralue_bmp_len
6741  * The best match prefix length in the case that there is no match for
6742  * longer prefixes.
6743  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6744  * Note for any update operation with entry_type modification this
6745  * field must be set.
6746  * Access: RW
6747  */
6748 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6749 
6750 enum mlxsw_reg_ralue_action_type {
6751 	MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6752 	MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6753 	MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6754 };
6755 
6756 /* reg_ralue_action_type
6757  * Action Type
6758  * Indicates how the IP address is connected.
6759  * It can be connected to a local subnet through local_erif or can be
6760  * on a remote subnet connected through a next-hop router,
6761  * or transmitted to the CPU.
6762  * Reserved when entry_type = MARKER_ENTRY
6763  * Access: RW
6764  */
6765 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6766 
6767 enum mlxsw_reg_ralue_trap_action {
6768 	MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6769 	MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6770 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6771 	MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6772 	MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6773 };
6774 
6775 /* reg_ralue_trap_action
6776  * Trap action.
6777  * For IP2ME action, only NOP and MIRROR are possible.
6778  * Access: RW
6779  */
6780 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6781 
6782 /* reg_ralue_trap_id
6783  * Trap ID to be reported to CPU.
6784  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6785  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6786  * Access: RW
6787  */
6788 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6789 
6790 /* reg_ralue_adjacency_index
6791  * Points to the first entry of the group-based ECMP.
6792  * Only relevant in case of REMOTE action.
6793  * Access: RW
6794  */
6795 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6796 
6797 /* reg_ralue_ecmp_size
6798  * Amount of sequential entries starting
6799  * from the adjacency_index (the number of ECMPs).
6800  * The valid range is 1-64, 512, 1024, 2048 and 4096.
6801  * Reserved when trap_action is TRAP or DISCARD_ERROR.
6802  * Only relevant in case of REMOTE action.
6803  * Access: RW
6804  */
6805 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6806 
6807 /* reg_ralue_local_erif
6808  * Egress Router Interface.
6809  * Only relevant in case of LOCAL action.
6810  * Access: RW
6811  */
6812 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6813 
6814 /* reg_ralue_ip2me_v
6815  * Valid bit for the tunnel_ptr field.
6816  * If valid = 0 then trap to CPU as IP2ME trap ID.
6817  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6818  * decapsulation then tunnel decapsulation is done.
6819  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6820  * decapsulation then trap as IP2ME trap ID.
6821  * Only relevant in case of IP2ME action.
6822  * Access: RW
6823  */
6824 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6825 
6826 /* reg_ralue_ip2me_tunnel_ptr
6827  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6828  * For Spectrum, pointer to KVD Linear.
6829  * Only relevant in case of IP2ME action.
6830  * Access: RW
6831  */
6832 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6833 
6834 static inline void mlxsw_reg_ralue_pack(char *payload,
6835 					enum mlxsw_reg_ralxx_protocol protocol,
6836 					enum mlxsw_reg_ralue_op op,
6837 					u16 virtual_router, u8 prefix_len)
6838 {
6839 	MLXSW_REG_ZERO(ralue, payload);
6840 	mlxsw_reg_ralue_protocol_set(payload, protocol);
6841 	mlxsw_reg_ralue_op_set(payload, op);
6842 	mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6843 	mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6844 	mlxsw_reg_ralue_entry_type_set(payload,
6845 				       MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6846 	mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6847 }
6848 
6849 static inline void mlxsw_reg_ralue_pack4(char *payload,
6850 					 enum mlxsw_reg_ralxx_protocol protocol,
6851 					 enum mlxsw_reg_ralue_op op,
6852 					 u16 virtual_router, u8 prefix_len,
6853 					 u32 dip)
6854 {
6855 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6856 	mlxsw_reg_ralue_dip4_set(payload, dip);
6857 }
6858 
6859 static inline void mlxsw_reg_ralue_pack6(char *payload,
6860 					 enum mlxsw_reg_ralxx_protocol protocol,
6861 					 enum mlxsw_reg_ralue_op op,
6862 					 u16 virtual_router, u8 prefix_len,
6863 					 const void *dip)
6864 {
6865 	mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6866 	mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6867 }
6868 
6869 static inline void
6870 mlxsw_reg_ralue_act_remote_pack(char *payload,
6871 				enum mlxsw_reg_ralue_trap_action trap_action,
6872 				u16 trap_id, u32 adjacency_index, u16 ecmp_size)
6873 {
6874 	mlxsw_reg_ralue_action_type_set(payload,
6875 					MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
6876 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6877 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6878 	mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
6879 	mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
6880 }
6881 
6882 static inline void
6883 mlxsw_reg_ralue_act_local_pack(char *payload,
6884 			       enum mlxsw_reg_ralue_trap_action trap_action,
6885 			       u16 trap_id, u16 local_erif)
6886 {
6887 	mlxsw_reg_ralue_action_type_set(payload,
6888 					MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
6889 	mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6890 	mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6891 	mlxsw_reg_ralue_local_erif_set(payload, local_erif);
6892 }
6893 
6894 static inline void
6895 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
6896 {
6897 	mlxsw_reg_ralue_action_type_set(payload,
6898 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6899 }
6900 
6901 static inline void
6902 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
6903 {
6904 	mlxsw_reg_ralue_action_type_set(payload,
6905 					MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6906 	mlxsw_reg_ralue_ip2me_v_set(payload, 1);
6907 	mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
6908 }
6909 
6910 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
6911  * ----------------------------------------------------------
6912  * The RAUHT register is used to configure and query the Unicast Host table in
6913  * devices that implement the Algorithmic LPM.
6914  */
6915 #define MLXSW_REG_RAUHT_ID 0x8014
6916 #define MLXSW_REG_RAUHT_LEN 0x74
6917 
6918 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
6919 
6920 enum mlxsw_reg_rauht_type {
6921 	MLXSW_REG_RAUHT_TYPE_IPV4,
6922 	MLXSW_REG_RAUHT_TYPE_IPV6,
6923 };
6924 
6925 /* reg_rauht_type
6926  * Access: Index
6927  */
6928 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
6929 
6930 enum mlxsw_reg_rauht_op {
6931 	MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
6932 	/* Read operation */
6933 	MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
6934 	/* Clear on read operation. Used to read entry and clear
6935 	 * activity bit.
6936 	 */
6937 	MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
6938 	/* Add. Used to write a new entry to the table. All R/W fields are
6939 	 * relevant for new entry. Activity bit is set for new entries.
6940 	 */
6941 	MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
6942 	/* Update action. Used to update an existing route entry and
6943 	 * only update the following fields:
6944 	 * trap_action, trap_id, mac, counter_set_type, counter_index
6945 	 */
6946 	MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
6947 	/* Clear activity. A bit is cleared for the entry. */
6948 	MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
6949 	/* Delete entry */
6950 	MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
6951 	/* Delete all host entries on a RIF. In this command, dip
6952 	 * field is reserved.
6953 	 */
6954 };
6955 
6956 /* reg_rauht_op
6957  * Access: OP
6958  */
6959 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
6960 
6961 /* reg_rauht_a
6962  * Activity. Set for new entries. Set if a packet lookup has hit on
6963  * the specific entry.
6964  * To clear the a bit, use "clear activity" op.
6965  * Enabled by activity_dis in RGCR
6966  * Access: RO
6967  */
6968 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
6969 
6970 /* reg_rauht_rif
6971  * Router Interface
6972  * Access: Index
6973  */
6974 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
6975 
6976 /* reg_rauht_dip*
6977  * Destination address.
6978  * Access: Index
6979  */
6980 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
6981 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
6982 
6983 enum mlxsw_reg_rauht_trap_action {
6984 	MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
6985 	MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
6986 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
6987 	MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
6988 	MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
6989 };
6990 
6991 /* reg_rauht_trap_action
6992  * Access: RW
6993  */
6994 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
6995 
6996 enum mlxsw_reg_rauht_trap_id {
6997 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
6998 	MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
6999 };
7000 
7001 /* reg_rauht_trap_id
7002  * Trap ID to be reported to CPU.
7003  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7004  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
7005  * trap_id is reserved.
7006  * Access: RW
7007  */
7008 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7009 
7010 /* reg_rauht_counter_set_type
7011  * Counter set type for flow counters
7012  * Access: RW
7013  */
7014 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7015 
7016 /* reg_rauht_counter_index
7017  * Counter index for flow counters
7018  * Access: RW
7019  */
7020 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7021 
7022 /* reg_rauht_mac
7023  * MAC address.
7024  * Access: RW
7025  */
7026 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7027 
7028 static inline void mlxsw_reg_rauht_pack(char *payload,
7029 					enum mlxsw_reg_rauht_op op, u16 rif,
7030 					const char *mac)
7031 {
7032 	MLXSW_REG_ZERO(rauht, payload);
7033 	mlxsw_reg_rauht_op_set(payload, op);
7034 	mlxsw_reg_rauht_rif_set(payload, rif);
7035 	mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7036 }
7037 
7038 static inline void mlxsw_reg_rauht_pack4(char *payload,
7039 					 enum mlxsw_reg_rauht_op op, u16 rif,
7040 					 const char *mac, u32 dip)
7041 {
7042 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
7043 	mlxsw_reg_rauht_dip4_set(payload, dip);
7044 }
7045 
7046 static inline void mlxsw_reg_rauht_pack6(char *payload,
7047 					 enum mlxsw_reg_rauht_op op, u16 rif,
7048 					 const char *mac, const char *dip)
7049 {
7050 	mlxsw_reg_rauht_pack(payload, op, rif, mac);
7051 	mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7052 	mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7053 }
7054 
7055 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7056 						u64 counter_index)
7057 {
7058 	mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7059 	mlxsw_reg_rauht_counter_set_type_set(payload,
7060 					     MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7061 }
7062 
7063 /* RALEU - Router Algorithmic LPM ECMP Update Register
7064  * ---------------------------------------------------
7065  * The register enables updating the ECMP section in the action for multiple
7066  * LPM Unicast entries in a single operation. The update is executed to
7067  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
7068  */
7069 #define MLXSW_REG_RALEU_ID 0x8015
7070 #define MLXSW_REG_RALEU_LEN 0x28
7071 
7072 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7073 
7074 /* reg_raleu_protocol
7075  * Protocol.
7076  * Access: Index
7077  */
7078 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7079 
7080 /* reg_raleu_virtual_router
7081  * Virtual Router ID
7082  * Range is 0..cap_max_virtual_routers-1
7083  * Access: Index
7084  */
7085 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7086 
7087 /* reg_raleu_adjacency_index
7088  * Adjacency Index used for matching on the existing entries.
7089  * Access: Index
7090  */
7091 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7092 
7093 /* reg_raleu_ecmp_size
7094  * ECMP Size used for matching on the existing entries.
7095  * Access: Index
7096  */
7097 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7098 
7099 /* reg_raleu_new_adjacency_index
7100  * New Adjacency Index.
7101  * Access: WO
7102  */
7103 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7104 
7105 /* reg_raleu_new_ecmp_size
7106  * New ECMP Size.
7107  * Access: WO
7108  */
7109 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7110 
7111 static inline void mlxsw_reg_raleu_pack(char *payload,
7112 					enum mlxsw_reg_ralxx_protocol protocol,
7113 					u16 virtual_router,
7114 					u32 adjacency_index, u16 ecmp_size,
7115 					u32 new_adjacency_index,
7116 					u16 new_ecmp_size)
7117 {
7118 	MLXSW_REG_ZERO(raleu, payload);
7119 	mlxsw_reg_raleu_protocol_set(payload, protocol);
7120 	mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7121 	mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7122 	mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7123 	mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7124 	mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7125 }
7126 
7127 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
7128  * ----------------------------------------------------------------
7129  * The RAUHTD register allows dumping entries from the Router Unicast Host
7130  * Table. For a given session an entry is dumped no more than one time. The
7131  * first RAUHTD access after reset is a new session. A session ends when the
7132  * num_rec response is smaller than num_rec request or for IPv4 when the
7133  * num_entries is smaller than 4. The clear activity affect the current session
7134  * or the last session if a new session has not started.
7135  */
7136 #define MLXSW_REG_RAUHTD_ID 0x8018
7137 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7138 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
7139 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7140 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7141 		MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7142 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7143 
7144 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7145 
7146 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7147 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7148 
7149 /* reg_rauhtd_filter_fields
7150  * if a bit is '0' then the relevant field is ignored and dump is done
7151  * regardless of the field value
7152  * Bit0 - filter by activity: entry_a
7153  * Bit3 - filter by entry rip: entry_rif
7154  * Access: Index
7155  */
7156 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7157 
7158 enum mlxsw_reg_rauhtd_op {
7159 	MLXSW_REG_RAUHTD_OP_DUMP,
7160 	MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7161 };
7162 
7163 /* reg_rauhtd_op
7164  * Access: OP
7165  */
7166 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7167 
7168 /* reg_rauhtd_num_rec
7169  * At request: number of records requested
7170  * At response: number of records dumped
7171  * For IPv4, each record has 4 entries at request and up to 4 entries
7172  * at response
7173  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
7174  * Access: Index
7175  */
7176 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7177 
7178 /* reg_rauhtd_entry_a
7179  * Dump only if activity has value of entry_a
7180  * Reserved if filter_fields bit0 is '0'
7181  * Access: Index
7182  */
7183 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7184 
7185 enum mlxsw_reg_rauhtd_type {
7186 	MLXSW_REG_RAUHTD_TYPE_IPV4,
7187 	MLXSW_REG_RAUHTD_TYPE_IPV6,
7188 };
7189 
7190 /* reg_rauhtd_type
7191  * Dump only if record type is:
7192  * 0 - IPv4
7193  * 1 - IPv6
7194  * Access: Index
7195  */
7196 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7197 
7198 /* reg_rauhtd_entry_rif
7199  * Dump only if RIF has value of entry_rif
7200  * Reserved if filter_fields bit3 is '0'
7201  * Access: Index
7202  */
7203 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7204 
7205 static inline void mlxsw_reg_rauhtd_pack(char *payload,
7206 					 enum mlxsw_reg_rauhtd_type type)
7207 {
7208 	MLXSW_REG_ZERO(rauhtd, payload);
7209 	mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7210 	mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7211 	mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7212 	mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7213 	mlxsw_reg_rauhtd_type_set(payload, type);
7214 }
7215 
7216 /* reg_rauhtd_ipv4_rec_num_entries
7217  * Number of valid entries in this record:
7218  * 0 - 1 valid entry
7219  * 1 - 2 valid entries
7220  * 2 - 3 valid entries
7221  * 3 - 4 valid entries
7222  * Access: RO
7223  */
7224 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7225 		     MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7226 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7227 
7228 /* reg_rauhtd_rec_type
7229  * Record type.
7230  * 0 - IPv4
7231  * 1 - IPv6
7232  * Access: RO
7233  */
7234 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7235 		     MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7236 
7237 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7238 
7239 /* reg_rauhtd_ipv4_ent_a
7240  * Activity. Set for new entries. Set if a packet lookup has hit on the
7241  * specific entry.
7242  * Access: RO
7243  */
7244 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7245 		     MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7246 
7247 /* reg_rauhtd_ipv4_ent_rif
7248  * Router interface.
7249  * Access: RO
7250  */
7251 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7252 		     16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7253 
7254 /* reg_rauhtd_ipv4_ent_dip
7255  * Destination IPv4 address.
7256  * Access: RO
7257  */
7258 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7259 		     32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7260 
7261 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7262 
7263 /* reg_rauhtd_ipv6_ent_a
7264  * Activity. Set for new entries. Set if a packet lookup has hit on the
7265  * specific entry.
7266  * Access: RO
7267  */
7268 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7269 		     MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7270 
7271 /* reg_rauhtd_ipv6_ent_rif
7272  * Router interface.
7273  * Access: RO
7274  */
7275 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7276 		     16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7277 
7278 /* reg_rauhtd_ipv6_ent_dip
7279  * Destination IPv6 address.
7280  * Access: RO
7281  */
7282 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7283 		       16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7284 
7285 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7286 						    int ent_index, u16 *p_rif,
7287 						    u32 *p_dip)
7288 {
7289 	*p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7290 	*p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7291 }
7292 
7293 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7294 						    int rec_index, u16 *p_rif,
7295 						    char *p_dip)
7296 {
7297 	*p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7298 	mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7299 }
7300 
7301 /* RTDP - Routing Tunnel Decap Properties Register
7302  * -----------------------------------------------
7303  * The RTDP register is used for configuring the tunnel decap properties of NVE
7304  * and IPinIP.
7305  */
7306 #define MLXSW_REG_RTDP_ID 0x8020
7307 #define MLXSW_REG_RTDP_LEN 0x44
7308 
7309 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7310 
7311 enum mlxsw_reg_rtdp_type {
7312 	MLXSW_REG_RTDP_TYPE_NVE,
7313 	MLXSW_REG_RTDP_TYPE_IPIP,
7314 };
7315 
7316 /* reg_rtdp_type
7317  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
7318  * Access: RW
7319  */
7320 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7321 
7322 /* reg_rtdp_tunnel_index
7323  * Index to the Decap entry.
7324  * For Spectrum, Index to KVD Linear.
7325  * Access: Index
7326  */
7327 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7328 
7329 /* reg_rtdp_egress_router_interface
7330  * Underlay egress router interface.
7331  * Valid range is from 0 to cap_max_router_interfaces - 1
7332  * Access: RW
7333  */
7334 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7335 
7336 /* IPinIP */
7337 
7338 /* reg_rtdp_ipip_irif
7339  * Ingress Router Interface for the overlay router
7340  * Access: RW
7341  */
7342 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7343 
7344 enum mlxsw_reg_rtdp_ipip_sip_check {
7345 	/* No sip checks. */
7346 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7347 	/* Filter packet if underlay is not IPv4 or if underlay SIP does not
7348 	 * equal ipv4_usip.
7349 	 */
7350 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7351 	/* Filter packet if underlay is not IPv6 or if underlay SIP does not
7352 	 * equal ipv6_usip.
7353 	 */
7354 	MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7355 };
7356 
7357 /* reg_rtdp_ipip_sip_check
7358  * SIP check to perform. If decapsulation failed due to these configurations
7359  * then trap_id is IPIP_DECAP_ERROR.
7360  * Access: RW
7361  */
7362 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7363 
7364 /* If set, allow decapsulation of IPinIP (without GRE). */
7365 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP	BIT(0)
7366 /* If set, allow decapsulation of IPinGREinIP without a key. */
7367 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE	BIT(1)
7368 /* If set, allow decapsulation of IPinGREinIP with a key. */
7369 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY	BIT(2)
7370 
7371 /* reg_rtdp_ipip_type_check
7372  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
7373  * these configurations then trap_id is IPIP_DECAP_ERROR.
7374  * Access: RW
7375  */
7376 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7377 
7378 /* reg_rtdp_ipip_gre_key_check
7379  * Whether GRE key should be checked. When check is enabled:
7380  * - A packet received as IPinIP (without GRE) will always pass.
7381  * - A packet received as IPinGREinIP without a key will not pass the check.
7382  * - A packet received as IPinGREinIP with a key will pass the check only if the
7383  *   key in the packet is equal to expected_gre_key.
7384  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
7385  * Access: RW
7386  */
7387 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7388 
7389 /* reg_rtdp_ipip_ipv4_usip
7390  * Underlay IPv4 address for ipv4 source address check.
7391  * Reserved when sip_check is not '1'.
7392  * Access: RW
7393  */
7394 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7395 
7396 /* reg_rtdp_ipip_ipv6_usip_ptr
7397  * This field is valid when sip_check is "sipv6 check explicitly". This is a
7398  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
7399  * is to the KVD linear.
7400  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
7401  * Access: RW
7402  */
7403 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7404 
7405 /* reg_rtdp_ipip_expected_gre_key
7406  * GRE key for checking.
7407  * Reserved when gre_key_check is '0'.
7408  * Access: RW
7409  */
7410 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7411 
7412 static inline void mlxsw_reg_rtdp_pack(char *payload,
7413 				       enum mlxsw_reg_rtdp_type type,
7414 				       u32 tunnel_index)
7415 {
7416 	MLXSW_REG_ZERO(rtdp, payload);
7417 	mlxsw_reg_rtdp_type_set(payload, type);
7418 	mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7419 }
7420 
7421 static inline void
7422 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7423 			  enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7424 			  unsigned int type_check, bool gre_key_check,
7425 			  u32 ipv4_usip, u32 expected_gre_key)
7426 {
7427 	mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7428 	mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7429 	mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7430 	mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7431 	mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7432 	mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7433 }
7434 
7435 /* RIGR-V2 - Router Interface Group Register Version 2
7436  * ---------------------------------------------------
7437  * The RIGR_V2 register is used to add, remove and query egress interface list
7438  * of a multicast forwarding entry.
7439  */
7440 #define MLXSW_REG_RIGR2_ID 0x8023
7441 #define MLXSW_REG_RIGR2_LEN 0xB0
7442 
7443 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
7444 
7445 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7446 
7447 /* reg_rigr2_rigr_index
7448  * KVD Linear index.
7449  * Access: Index
7450  */
7451 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7452 
7453 /* reg_rigr2_vnext
7454  * Next RIGR Index is valid.
7455  * Access: RW
7456  */
7457 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7458 
7459 /* reg_rigr2_next_rigr_index
7460  * Next RIGR Index. The index is to the KVD linear.
7461  * Reserved when vnxet = '0'.
7462  * Access: RW
7463  */
7464 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7465 
7466 /* reg_rigr2_vrmid
7467  * RMID Index is valid.
7468  * Access: RW
7469  */
7470 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7471 
7472 /* reg_rigr2_rmid_index
7473  * RMID Index.
7474  * Range 0 .. max_mid - 1
7475  * Reserved when vrmid = '0'.
7476  * The index is to the Port Group Table (PGT)
7477  * Access: RW
7478  */
7479 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7480 
7481 /* reg_rigr2_erif_entry_v
7482  * Egress Router Interface is valid.
7483  * Note that low-entries must be set if high-entries are set. For
7484  * example: if erif_entry[2].v is set then erif_entry[1].v and
7485  * erif_entry[0].v must be set.
7486  * Index can be from 0 to cap_mc_erif_list_entries-1
7487  * Access: RW
7488  */
7489 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7490 
7491 /* reg_rigr2_erif_entry_erif
7492  * Egress Router Interface.
7493  * Valid range is from 0 to cap_max_router_interfaces - 1
7494  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7495  * Access: RW
7496  */
7497 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7498 
7499 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7500 					bool vnext, u32 next_rigr_index)
7501 {
7502 	MLXSW_REG_ZERO(rigr2, payload);
7503 	mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7504 	mlxsw_reg_rigr2_vnext_set(payload, vnext);
7505 	mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7506 	mlxsw_reg_rigr2_vrmid_set(payload, 0);
7507 	mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7508 }
7509 
7510 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7511 						   bool v, u16 erif)
7512 {
7513 	mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7514 	mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7515 }
7516 
7517 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7518  * ------------------------------------------------------
7519  */
7520 #define MLXSW_REG_RECR2_ID 0x8025
7521 #define MLXSW_REG_RECR2_LEN 0x38
7522 
7523 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7524 
7525 /* reg_recr2_pp
7526  * Per-port configuration
7527  * Access: Index
7528  */
7529 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7530 
7531 /* reg_recr2_sh
7532  * Symmetric hash
7533  * Access: RW
7534  */
7535 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7536 
7537 /* reg_recr2_seed
7538  * Seed
7539  * Access: RW
7540  */
7541 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7542 
7543 enum {
7544 	/* Enable IPv4 fields if packet is not TCP and not UDP */
7545 	MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP	= 3,
7546 	/* Enable IPv4 fields if packet is TCP or UDP */
7547 	MLXSW_REG_RECR2_IPV4_EN_TCP_UDP		= 4,
7548 	/* Enable IPv6 fields if packet is not TCP and not UDP */
7549 	MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP	= 5,
7550 	/* Enable IPv6 fields if packet is TCP or UDP */
7551 	MLXSW_REG_RECR2_IPV6_EN_TCP_UDP		= 6,
7552 	/* Enable TCP/UDP header fields if packet is IPv4 */
7553 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV4		= 7,
7554 	/* Enable TCP/UDP header fields if packet is IPv6 */
7555 	MLXSW_REG_RECR2_TCP_UDP_EN_IPV6		= 8,
7556 };
7557 
7558 /* reg_recr2_outer_header_enables
7559  * Bit mask where each bit enables a specific layer to be included in
7560  * the hash calculation.
7561  * Access: RW
7562  */
7563 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7564 
7565 enum {
7566 	/* IPv4 Source IP */
7567 	MLXSW_REG_RECR2_IPV4_SIP0			= 9,
7568 	MLXSW_REG_RECR2_IPV4_SIP3			= 12,
7569 	/* IPv4 Destination IP */
7570 	MLXSW_REG_RECR2_IPV4_DIP0			= 13,
7571 	MLXSW_REG_RECR2_IPV4_DIP3			= 16,
7572 	/* IP Protocol */
7573 	MLXSW_REG_RECR2_IPV4_PROTOCOL			= 17,
7574 	/* IPv6 Source IP */
7575 	MLXSW_REG_RECR2_IPV6_SIP0_7			= 21,
7576 	MLXSW_REG_RECR2_IPV6_SIP8			= 29,
7577 	MLXSW_REG_RECR2_IPV6_SIP15			= 36,
7578 	/* IPv6 Destination IP */
7579 	MLXSW_REG_RECR2_IPV6_DIP0_7			= 37,
7580 	MLXSW_REG_RECR2_IPV6_DIP8			= 45,
7581 	MLXSW_REG_RECR2_IPV6_DIP15			= 52,
7582 	/* IPv6 Next Header */
7583 	MLXSW_REG_RECR2_IPV6_NEXT_HEADER		= 53,
7584 	/* IPv6 Flow Label */
7585 	MLXSW_REG_RECR2_IPV6_FLOW_LABEL			= 57,
7586 	/* TCP/UDP Source Port */
7587 	MLXSW_REG_RECR2_TCP_UDP_SPORT			= 74,
7588 	/* TCP/UDP Destination Port */
7589 	MLXSW_REG_RECR2_TCP_UDP_DPORT			= 75,
7590 };
7591 
7592 /* reg_recr2_outer_header_fields_enable
7593  * Packet fields to enable for ECMP hash subject to outer_header_enable.
7594  * Access: RW
7595  */
7596 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7597 
7598 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7599 {
7600 	int i;
7601 
7602 	for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7603 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7604 							       true);
7605 }
7606 
7607 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7608 {
7609 	int i;
7610 
7611 	for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7612 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7613 							       true);
7614 }
7615 
7616 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7617 {
7618 	int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7619 
7620 	mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7621 
7622 	i = MLXSW_REG_RECR2_IPV6_SIP8;
7623 	for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7624 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7625 							       true);
7626 }
7627 
7628 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7629 {
7630 	int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7631 
7632 	mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7633 
7634 	i = MLXSW_REG_RECR2_IPV6_DIP8;
7635 	for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7636 		mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7637 							       true);
7638 }
7639 
7640 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7641 {
7642 	MLXSW_REG_ZERO(recr2, payload);
7643 	mlxsw_reg_recr2_pp_set(payload, false);
7644 	mlxsw_reg_recr2_sh_set(payload, true);
7645 	mlxsw_reg_recr2_seed_set(payload, seed);
7646 }
7647 
7648 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7649  * --------------------------------------------------------------
7650  * The RMFT_V2 register is used to configure and query the multicast table.
7651  */
7652 #define MLXSW_REG_RMFT2_ID 0x8027
7653 #define MLXSW_REG_RMFT2_LEN 0x174
7654 
7655 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7656 
7657 /* reg_rmft2_v
7658  * Valid
7659  * Access: RW
7660  */
7661 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7662 
7663 enum mlxsw_reg_rmft2_type {
7664 	MLXSW_REG_RMFT2_TYPE_IPV4,
7665 	MLXSW_REG_RMFT2_TYPE_IPV6
7666 };
7667 
7668 /* reg_rmft2_type
7669  * Access: Index
7670  */
7671 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7672 
7673 enum mlxsw_sp_reg_rmft2_op {
7674 	/* For Write:
7675 	 * Write operation. Used to write a new entry to the table. All RW
7676 	 * fields are relevant for new entry. Activity bit is set for new
7677 	 * entries - Note write with v (Valid) 0 will delete the entry.
7678 	 * For Query:
7679 	 * Read operation
7680 	 */
7681 	MLXSW_REG_RMFT2_OP_READ_WRITE,
7682 };
7683 
7684 /* reg_rmft2_op
7685  * Operation.
7686  * Access: OP
7687  */
7688 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7689 
7690 /* reg_rmft2_a
7691  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7692  * entry.
7693  * Access: RO
7694  */
7695 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7696 
7697 /* reg_rmft2_offset
7698  * Offset within the multicast forwarding table to write to.
7699  * Access: Index
7700  */
7701 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7702 
7703 /* reg_rmft2_virtual_router
7704  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7705  * Access: RW
7706  */
7707 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7708 
7709 enum mlxsw_reg_rmft2_irif_mask {
7710 	MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7711 	MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7712 };
7713 
7714 /* reg_rmft2_irif_mask
7715  * Ingress RIF mask.
7716  * Access: RW
7717  */
7718 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7719 
7720 /* reg_rmft2_irif
7721  * Ingress RIF index.
7722  * Access: RW
7723  */
7724 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7725 
7726 /* reg_rmft2_dip{4,6}
7727  * Destination IPv4/6 address
7728  * Access: RW
7729  */
7730 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7731 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7732 
7733 /* reg_rmft2_dip{4,6}_mask
7734  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7735  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7736  * Access: RW
7737  */
7738 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7739 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7740 
7741 /* reg_rmft2_sip{4,6}
7742  * Source IPv4/6 address
7743  * Access: RW
7744  */
7745 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7746 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7747 
7748 /* reg_rmft2_sip{4,6}_mask
7749  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7750  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7751  * Access: RW
7752  */
7753 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7754 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7755 
7756 /* reg_rmft2_flexible_action_set
7757  * ACL action set. The only supported action types in this field and in any
7758  * action-set pointed from here are as follows:
7759  * 00h: ACTION_NULL
7760  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7761  * 03h: ACTION_TRAP
7762  * 06h: ACTION_QOS
7763  * 08h: ACTION_POLICING_MONITORING
7764  * 10h: ACTION_ROUTER_MC
7765  * Access: RW
7766  */
7767 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7768 	       MLXSW_REG_FLEX_ACTION_SET_LEN);
7769 
7770 static inline void
7771 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7772 			    u16 virtual_router,
7773 			    enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7774 			    const char *flex_action_set)
7775 {
7776 	MLXSW_REG_ZERO(rmft2, payload);
7777 	mlxsw_reg_rmft2_v_set(payload, v);
7778 	mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7779 	mlxsw_reg_rmft2_offset_set(payload, offset);
7780 	mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7781 	mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7782 	mlxsw_reg_rmft2_irif_set(payload, irif);
7783 	if (flex_action_set)
7784 		mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7785 							      flex_action_set);
7786 }
7787 
7788 static inline void
7789 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7790 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7791 			  u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7792 			  const char *flexible_action_set)
7793 {
7794 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7795 				    irif_mask, irif, flexible_action_set);
7796 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7797 	mlxsw_reg_rmft2_dip4_set(payload, dip4);
7798 	mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7799 	mlxsw_reg_rmft2_sip4_set(payload, sip4);
7800 	mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7801 }
7802 
7803 static inline void
7804 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7805 			  enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7806 			  struct in6_addr dip6, struct in6_addr dip6_mask,
7807 			  struct in6_addr sip6, struct in6_addr sip6_mask,
7808 			  const char *flexible_action_set)
7809 {
7810 	mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7811 				    irif_mask, irif, flexible_action_set);
7812 	mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7813 	mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7814 	mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7815 	mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7816 	mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7817 }
7818 
7819 /* MFCR - Management Fan Control Register
7820  * --------------------------------------
7821  * This register controls the settings of the Fan Speed PWM mechanism.
7822  */
7823 #define MLXSW_REG_MFCR_ID 0x9001
7824 #define MLXSW_REG_MFCR_LEN 0x08
7825 
7826 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7827 
7828 enum mlxsw_reg_mfcr_pwm_frequency {
7829 	MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7830 	MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7831 	MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7832 	MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7833 	MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7834 	MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7835 	MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7836 	MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7837 };
7838 
7839 /* reg_mfcr_pwm_frequency
7840  * Controls the frequency of the PWM signal.
7841  * Access: RW
7842  */
7843 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7844 
7845 #define MLXSW_MFCR_TACHOS_MAX 10
7846 
7847 /* reg_mfcr_tacho_active
7848  * Indicates which of the tachometer is active (bit per tachometer).
7849  * Access: RO
7850  */
7851 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7852 
7853 #define MLXSW_MFCR_PWMS_MAX 5
7854 
7855 /* reg_mfcr_pwm_active
7856  * Indicates which of the PWM control is active (bit per PWM).
7857  * Access: RO
7858  */
7859 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7860 
7861 static inline void
7862 mlxsw_reg_mfcr_pack(char *payload,
7863 		    enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7864 {
7865 	MLXSW_REG_ZERO(mfcr, payload);
7866 	mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7867 }
7868 
7869 static inline void
7870 mlxsw_reg_mfcr_unpack(char *payload,
7871 		      enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
7872 		      u16 *p_tacho_active, u8 *p_pwm_active)
7873 {
7874 	*p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
7875 	*p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
7876 	*p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
7877 }
7878 
7879 /* MFSC - Management Fan Speed Control Register
7880  * --------------------------------------------
7881  * This register controls the settings of the Fan Speed PWM mechanism.
7882  */
7883 #define MLXSW_REG_MFSC_ID 0x9002
7884 #define MLXSW_REG_MFSC_LEN 0x08
7885 
7886 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
7887 
7888 /* reg_mfsc_pwm
7889  * Fan pwm to control / monitor.
7890  * Access: Index
7891  */
7892 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
7893 
7894 /* reg_mfsc_pwm_duty_cycle
7895  * Controls the duty cycle of the PWM. Value range from 0..255 to
7896  * represent duty cycle of 0%...100%.
7897  * Access: RW
7898  */
7899 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
7900 
7901 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
7902 				       u8 pwm_duty_cycle)
7903 {
7904 	MLXSW_REG_ZERO(mfsc, payload);
7905 	mlxsw_reg_mfsc_pwm_set(payload, pwm);
7906 	mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
7907 }
7908 
7909 /* MFSM - Management Fan Speed Measurement
7910  * ---------------------------------------
7911  * This register controls the settings of the Tacho measurements and
7912  * enables reading the Tachometer measurements.
7913  */
7914 #define MLXSW_REG_MFSM_ID 0x9003
7915 #define MLXSW_REG_MFSM_LEN 0x08
7916 
7917 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
7918 
7919 /* reg_mfsm_tacho
7920  * Fan tachometer index.
7921  * Access: Index
7922  */
7923 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
7924 
7925 /* reg_mfsm_rpm
7926  * Fan speed (round per minute).
7927  * Access: RO
7928  */
7929 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
7930 
7931 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
7932 {
7933 	MLXSW_REG_ZERO(mfsm, payload);
7934 	mlxsw_reg_mfsm_tacho_set(payload, tacho);
7935 }
7936 
7937 /* MFSL - Management Fan Speed Limit Register
7938  * ------------------------------------------
7939  * The Fan Speed Limit register is used to configure the fan speed
7940  * event / interrupt notification mechanism. Fan speed threshold are
7941  * defined for both under-speed and over-speed.
7942  */
7943 #define MLXSW_REG_MFSL_ID 0x9004
7944 #define MLXSW_REG_MFSL_LEN 0x0C
7945 
7946 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
7947 
7948 /* reg_mfsl_tacho
7949  * Fan tachometer index.
7950  * Access: Index
7951  */
7952 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
7953 
7954 /* reg_mfsl_tach_min
7955  * Tachometer minimum value (minimum RPM).
7956  * Access: RW
7957  */
7958 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
7959 
7960 /* reg_mfsl_tach_max
7961  * Tachometer maximum value (maximum RPM).
7962  * Access: RW
7963  */
7964 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
7965 
7966 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
7967 				       u16 tach_min, u16 tach_max)
7968 {
7969 	MLXSW_REG_ZERO(mfsl, payload);
7970 	mlxsw_reg_mfsl_tacho_set(payload, tacho);
7971 	mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
7972 	mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
7973 }
7974 
7975 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
7976 					 u16 *p_tach_min, u16 *p_tach_max)
7977 {
7978 	if (p_tach_min)
7979 		*p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
7980 
7981 	if (p_tach_max)
7982 		*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
7983 }
7984 
7985 /* FORE - Fan Out of Range Event Register
7986  * --------------------------------------
7987  * This register reports the status of the controlled fans compared to the
7988  * range defined by the MFSL register.
7989  */
7990 #define MLXSW_REG_FORE_ID 0x9007
7991 #define MLXSW_REG_FORE_LEN 0x0C
7992 
7993 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
7994 
7995 /* fan_under_limit
7996  * Fan speed is below the low limit defined in MFSL register. Each bit relates
7997  * to a single tachometer and indicates the specific tachometer reading is
7998  * below the threshold.
7999  * Access: RO
8000  */
8001 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8002 
8003 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8004 					 bool *fault)
8005 {
8006 	u16 limit;
8007 
8008 	if (fault) {
8009 		limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8010 		*fault = limit & BIT(tacho);
8011 	}
8012 }
8013 
8014 /* MTCAP - Management Temperature Capabilities
8015  * -------------------------------------------
8016  * This register exposes the capabilities of the device and
8017  * system temperature sensing.
8018  */
8019 #define MLXSW_REG_MTCAP_ID 0x9009
8020 #define MLXSW_REG_MTCAP_LEN 0x08
8021 
8022 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8023 
8024 /* reg_mtcap_sensor_count
8025  * Number of sensors supported by the device.
8026  * This includes the QSFP module sensors (if exists in the QSFP module).
8027  * Access: RO
8028  */
8029 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8030 
8031 /* MTMP - Management Temperature
8032  * -----------------------------
8033  * This register controls the settings of the temperature measurements
8034  * and enables reading the temperature measurements. Note that temperature
8035  * is in 0.125 degrees Celsius.
8036  */
8037 #define MLXSW_REG_MTMP_ID 0x900A
8038 #define MLXSW_REG_MTMP_LEN 0x20
8039 
8040 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8041 
8042 /* reg_mtmp_sensor_index
8043  * Sensors index to access.
8044  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
8045  * (module 0 is mapped to sensor_index 64).
8046  * Access: Index
8047  */
8048 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
8049 
8050 /* Convert to milli degrees Celsius */
8051 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
8052 
8053 /* reg_mtmp_temperature
8054  * Temperature reading from the sensor. Reading is in 0.125 Celsius
8055  * degrees units.
8056  * Access: RO
8057  */
8058 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8059 
8060 /* reg_mtmp_mte
8061  * Max Temperature Enable - enables measuring the max temperature on a sensor.
8062  * Access: RW
8063  */
8064 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8065 
8066 /* reg_mtmp_mtr
8067  * Max Temperature Reset - clears the value of the max temperature register.
8068  * Access: WO
8069  */
8070 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8071 
8072 /* reg_mtmp_max_temperature
8073  * The highest measured temperature from the sensor.
8074  * When the bit mte is cleared, the field max_temperature is reserved.
8075  * Access: RO
8076  */
8077 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8078 
8079 /* reg_mtmp_tee
8080  * Temperature Event Enable.
8081  * 0 - Do not generate event
8082  * 1 - Generate event
8083  * 2 - Generate single event
8084  * Access: RW
8085  */
8086 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8087 
8088 #define MLXSW_REG_MTMP_THRESH_HI 0x348	/* 105 Celsius */
8089 
8090 /* reg_mtmp_temperature_threshold_hi
8091  * High threshold for Temperature Warning Event. In 0.125 Celsius.
8092  * Access: RW
8093  */
8094 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8095 
8096 /* reg_mtmp_temperature_threshold_lo
8097  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
8098  * Access: RW
8099  */
8100 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8101 
8102 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8103 
8104 /* reg_mtmp_sensor_name
8105  * Sensor Name
8106  * Access: RO
8107  */
8108 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8109 
8110 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
8111 				       bool max_temp_enable,
8112 				       bool max_temp_reset)
8113 {
8114 	MLXSW_REG_ZERO(mtmp, payload);
8115 	mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8116 	mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8117 	mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8118 	mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8119 						    MLXSW_REG_MTMP_THRESH_HI);
8120 }
8121 
8122 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
8123 					 unsigned int *p_max_temp,
8124 					 char *sensor_name)
8125 {
8126 	u16 temp;
8127 
8128 	if (p_temp) {
8129 		temp = mlxsw_reg_mtmp_temperature_get(payload);
8130 		*p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8131 	}
8132 	if (p_max_temp) {
8133 		temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8134 		*p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8135 	}
8136 	if (sensor_name)
8137 		mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8138 }
8139 
8140 /* MTBR - Management Temperature Bulk Register
8141  * -------------------------------------------
8142  * This register is used for bulk temperature reading.
8143  */
8144 #define MLXSW_REG_MTBR_ID 0x900F
8145 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
8146 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
8147 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
8148 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +	\
8149 			    MLXSW_REG_MTBR_REC_LEN *	\
8150 			    MLXSW_REG_MTBR_REC_MAX_COUNT)
8151 
8152 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8153 
8154 /* reg_mtbr_base_sensor_index
8155  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
8156  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
8157  * Access: Index
8158  */
8159 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 7);
8160 
8161 /* reg_mtbr_num_rec
8162  * Request: Number of records to read
8163  * Response: Number of records read
8164  * See above description for more details.
8165  * Range 1..255
8166  * Access: RW
8167  */
8168 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8169 
8170 /* reg_mtbr_rec_max_temp
8171  * The highest measured temperature from the sensor.
8172  * When the bit mte is cleared, the field max_temperature is reserved.
8173  * Access: RO
8174  */
8175 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8176 		     16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8177 
8178 /* reg_mtbr_rec_temp
8179  * Temperature reading from the sensor. Reading is in 0..125 Celsius
8180  * degrees units.
8181  * Access: RO
8182  */
8183 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8184 		     MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8185 
8186 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 base_sensor_index,
8187 				       u8 num_rec)
8188 {
8189 	MLXSW_REG_ZERO(mtbr, payload);
8190 	mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8191 	mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8192 }
8193 
8194 /* Error codes from temperatute reading */
8195 enum mlxsw_reg_mtbr_temp_status {
8196 	MLXSW_REG_MTBR_NO_CONN		= 0x8000,
8197 	MLXSW_REG_MTBR_NO_TEMP_SENS	= 0x8001,
8198 	MLXSW_REG_MTBR_INDEX_NA		= 0x8002,
8199 	MLXSW_REG_MTBR_BAD_SENS_INFO	= 0x8003,
8200 };
8201 
8202 /* Base index for reading modules temperature */
8203 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8204 
8205 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8206 					      u16 *p_temp, u16 *p_max_temp)
8207 {
8208 	if (p_temp)
8209 		*p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8210 	if (p_max_temp)
8211 		*p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8212 }
8213 
8214 /* MCIA - Management Cable Info Access
8215  * -----------------------------------
8216  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
8217  */
8218 
8219 #define MLXSW_REG_MCIA_ID 0x9014
8220 #define MLXSW_REG_MCIA_LEN 0x40
8221 
8222 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8223 
8224 /* reg_mcia_l
8225  * Lock bit. Setting this bit will lock the access to the specific
8226  * cable. Used for updating a full page in a cable EPROM. Any access
8227  * other then subsequence writes will fail while the port is locked.
8228  * Access: RW
8229  */
8230 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8231 
8232 /* reg_mcia_module
8233  * Module number.
8234  * Access: Index
8235  */
8236 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8237 
8238 /* reg_mcia_status
8239  * Module status.
8240  * Access: RO
8241  */
8242 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8243 
8244 /* reg_mcia_i2c_device_address
8245  * I2C device address.
8246  * Access: RW
8247  */
8248 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8249 
8250 /* reg_mcia_page_number
8251  * Page number.
8252  * Access: RW
8253  */
8254 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8255 
8256 /* reg_mcia_device_address
8257  * Device address.
8258  * Access: RW
8259  */
8260 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8261 
8262 /* reg_mcia_size
8263  * Number of bytes to read/write (up to 48 bytes).
8264  * Access: RW
8265  */
8266 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8267 
8268 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH	256
8269 #define MLXSW_REG_MCIA_EEPROM_SIZE		48
8270 #define MLXSW_REG_MCIA_I2C_ADDR_LOW		0x50
8271 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH		0x51
8272 #define MLXSW_REG_MCIA_PAGE0_LO_OFF		0xa0
8273 #define MLXSW_REG_MCIA_TH_ITEM_SIZE		2
8274 #define MLXSW_REG_MCIA_TH_PAGE_NUM		3
8275 #define MLXSW_REG_MCIA_PAGE0_LO			0
8276 #define MLXSW_REG_MCIA_TH_PAGE_OFF		0x80
8277 
8278 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8279 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC	= 0x00,
8280 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436	= 0x01,
8281 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636	= 0x03,
8282 };
8283 
8284 enum mlxsw_reg_mcia_eeprom_module_info_id {
8285 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP	= 0x03,
8286 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP	= 0x0C,
8287 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS	= 0x0D,
8288 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28	= 0x11,
8289 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD	= 0x18,
8290 };
8291 
8292 enum mlxsw_reg_mcia_eeprom_module_info {
8293 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8294 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8295 	MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8296 };
8297 
8298 /* reg_mcia_eeprom
8299  * Bytes to read/write.
8300  * Access: RW
8301  */
8302 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8303 
8304 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8305 				       u8 page_number, u16 device_addr,
8306 				       u8 size, u8 i2c_device_addr)
8307 {
8308 	MLXSW_REG_ZERO(mcia, payload);
8309 	mlxsw_reg_mcia_module_set(payload, module);
8310 	mlxsw_reg_mcia_l_set(payload, lock);
8311 	mlxsw_reg_mcia_page_number_set(payload, page_number);
8312 	mlxsw_reg_mcia_device_address_set(payload, device_addr);
8313 	mlxsw_reg_mcia_size_set(payload, size);
8314 	mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8315 }
8316 
8317 /* MPAT - Monitoring Port Analyzer Table
8318  * -------------------------------------
8319  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
8320  * For an enabled analyzer, all fields except e (enable) cannot be modified.
8321  */
8322 #define MLXSW_REG_MPAT_ID 0x901A
8323 #define MLXSW_REG_MPAT_LEN 0x78
8324 
8325 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8326 
8327 /* reg_mpat_pa_id
8328  * Port Analyzer ID.
8329  * Access: Index
8330  */
8331 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8332 
8333 /* reg_mpat_system_port
8334  * A unique port identifier for the final destination of the packet.
8335  * Access: RW
8336  */
8337 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8338 
8339 /* reg_mpat_e
8340  * Enable. Indicating the Port Analyzer is enabled.
8341  * Access: RW
8342  */
8343 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8344 
8345 /* reg_mpat_qos
8346  * Quality Of Service Mode.
8347  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
8348  * PCP, DEI, DSCP or VL) are configured.
8349  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
8350  * same as in the original packet that has triggered the mirroring. For
8351  * SPAN also the pcp,dei are maintained.
8352  * Access: RW
8353  */
8354 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8355 
8356 /* reg_mpat_be
8357  * Best effort mode. Indicates mirroring traffic should not cause packet
8358  * drop or back pressure, but will discard the mirrored packets. Mirrored
8359  * packets will be forwarded on a best effort manner.
8360  * 0: Do not discard mirrored packets
8361  * 1: Discard mirrored packets if causing congestion
8362  * Access: RW
8363  */
8364 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8365 
8366 enum mlxsw_reg_mpat_span_type {
8367 	/* Local SPAN Ethernet.
8368 	 * The original packet is not encapsulated.
8369 	 */
8370 	MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8371 
8372 	/* Remote SPAN Ethernet VLAN.
8373 	 * The packet is forwarded to the monitoring port on the monitoring
8374 	 * VLAN.
8375 	 */
8376 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8377 
8378 	/* Encapsulated Remote SPAN Ethernet L3 GRE.
8379 	 * The packet is encapsulated with GRE header.
8380 	 */
8381 	MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8382 };
8383 
8384 /* reg_mpat_span_type
8385  * SPAN type.
8386  * Access: RW
8387  */
8388 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8389 
8390 /* Remote SPAN - Ethernet VLAN
8391  * - - - - - - - - - - - - - -
8392  */
8393 
8394 /* reg_mpat_eth_rspan_vid
8395  * Encapsulation header VLAN ID.
8396  * Access: RW
8397  */
8398 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8399 
8400 /* Encapsulated Remote SPAN - Ethernet L2
8401  * - - - - - - - - - - - - - - - - - - -
8402  */
8403 
8404 enum mlxsw_reg_mpat_eth_rspan_version {
8405 	MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8406 };
8407 
8408 /* reg_mpat_eth_rspan_version
8409  * RSPAN mirror header version.
8410  * Access: RW
8411  */
8412 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8413 
8414 /* reg_mpat_eth_rspan_mac
8415  * Destination MAC address.
8416  * Access: RW
8417  */
8418 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8419 
8420 /* reg_mpat_eth_rspan_tp
8421  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
8422  * Access: RW
8423  */
8424 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8425 
8426 /* Encapsulated Remote SPAN - Ethernet L3
8427  * - - - - - - - - - - - - - - - - - - -
8428  */
8429 
8430 enum mlxsw_reg_mpat_eth_rspan_protocol {
8431 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8432 	MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8433 };
8434 
8435 /* reg_mpat_eth_rspan_protocol
8436  * SPAN encapsulation protocol.
8437  * Access: RW
8438  */
8439 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8440 
8441 /* reg_mpat_eth_rspan_ttl
8442  * Encapsulation header Time-to-Live/HopLimit.
8443  * Access: RW
8444  */
8445 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8446 
8447 /* reg_mpat_eth_rspan_smac
8448  * Source MAC address
8449  * Access: RW
8450  */
8451 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8452 
8453 /* reg_mpat_eth_rspan_dip*
8454  * Destination IP address. The IP version is configured by protocol.
8455  * Access: RW
8456  */
8457 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8458 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8459 
8460 /* reg_mpat_eth_rspan_sip*
8461  * Source IP address. The IP version is configured by protocol.
8462  * Access: RW
8463  */
8464 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8465 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8466 
8467 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8468 				       u16 system_port, bool e,
8469 				       enum mlxsw_reg_mpat_span_type span_type)
8470 {
8471 	MLXSW_REG_ZERO(mpat, payload);
8472 	mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8473 	mlxsw_reg_mpat_system_port_set(payload, system_port);
8474 	mlxsw_reg_mpat_e_set(payload, e);
8475 	mlxsw_reg_mpat_qos_set(payload, 1);
8476 	mlxsw_reg_mpat_be_set(payload, 1);
8477 	mlxsw_reg_mpat_span_type_set(payload, span_type);
8478 }
8479 
8480 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8481 {
8482 	mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8483 }
8484 
8485 static inline void
8486 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8487 				 enum mlxsw_reg_mpat_eth_rspan_version version,
8488 				 const char *mac,
8489 				 bool tp)
8490 {
8491 	mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8492 	mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8493 	mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8494 }
8495 
8496 static inline void
8497 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8498 				      const char *smac,
8499 				      u32 sip, u32 dip)
8500 {
8501 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8502 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8503 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8504 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8505 	mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8506 	mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8507 }
8508 
8509 static inline void
8510 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8511 				      const char *smac,
8512 				      struct in6_addr sip, struct in6_addr dip)
8513 {
8514 	mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8515 	mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8516 	mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8517 				    MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8518 	mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8519 	mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8520 }
8521 
8522 /* MPAR - Monitoring Port Analyzer Register
8523  * ----------------------------------------
8524  * MPAR register is used to query and configure the port analyzer port mirroring
8525  * properties.
8526  */
8527 #define MLXSW_REG_MPAR_ID 0x901B
8528 #define MLXSW_REG_MPAR_LEN 0x08
8529 
8530 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8531 
8532 /* reg_mpar_local_port
8533  * The local port to mirror the packets from.
8534  * Access: Index
8535  */
8536 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8537 
8538 enum mlxsw_reg_mpar_i_e {
8539 	MLXSW_REG_MPAR_TYPE_EGRESS,
8540 	MLXSW_REG_MPAR_TYPE_INGRESS,
8541 };
8542 
8543 /* reg_mpar_i_e
8544  * Ingress/Egress
8545  * Access: Index
8546  */
8547 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8548 
8549 /* reg_mpar_enable
8550  * Enable mirroring
8551  * By default, port mirroring is disabled for all ports.
8552  * Access: RW
8553  */
8554 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8555 
8556 /* reg_mpar_pa_id
8557  * Port Analyzer ID.
8558  * Access: RW
8559  */
8560 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8561 
8562 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8563 				       enum mlxsw_reg_mpar_i_e i_e,
8564 				       bool enable, u8 pa_id)
8565 {
8566 	MLXSW_REG_ZERO(mpar, payload);
8567 	mlxsw_reg_mpar_local_port_set(payload, local_port);
8568 	mlxsw_reg_mpar_enable_set(payload, enable);
8569 	mlxsw_reg_mpar_i_e_set(payload, i_e);
8570 	mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8571 }
8572 
8573 /* MGIR - Management General Information Register
8574  * ----------------------------------------------
8575  * MGIR register allows software to query the hardware and firmware general
8576  * information.
8577  */
8578 #define MLXSW_REG_MGIR_ID 0x9020
8579 #define MLXSW_REG_MGIR_LEN 0x9C
8580 
8581 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8582 
8583 /* reg_mgir_hw_info_device_hw_revision
8584  * Access: RO
8585  */
8586 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8587 
8588 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8589 
8590 /* reg_mgir_fw_info_psid
8591  * PSID (ASCII string).
8592  * Access: RO
8593  */
8594 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8595 
8596 /* reg_mgir_fw_info_extended_major
8597  * Access: RO
8598  */
8599 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8600 
8601 /* reg_mgir_fw_info_extended_minor
8602  * Access: RO
8603  */
8604 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8605 
8606 /* reg_mgir_fw_info_extended_sub_minor
8607  * Access: RO
8608  */
8609 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8610 
8611 static inline void mlxsw_reg_mgir_pack(char *payload)
8612 {
8613 	MLXSW_REG_ZERO(mgir, payload);
8614 }
8615 
8616 static inline void
8617 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8618 		      u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8619 {
8620 	*hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8621 	mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8622 	*fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8623 	*fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8624 	*fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8625 }
8626 
8627 /* MRSR - Management Reset and Shutdown Register
8628  * ---------------------------------------------
8629  * MRSR register is used to reset or shutdown the switch or
8630  * the entire system (when applicable).
8631  */
8632 #define MLXSW_REG_MRSR_ID 0x9023
8633 #define MLXSW_REG_MRSR_LEN 0x08
8634 
8635 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8636 
8637 /* reg_mrsr_command
8638  * Reset/shutdown command
8639  * 0 - do nothing
8640  * 1 - software reset
8641  * Access: WO
8642  */
8643 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8644 
8645 static inline void mlxsw_reg_mrsr_pack(char *payload)
8646 {
8647 	MLXSW_REG_ZERO(mrsr, payload);
8648 	mlxsw_reg_mrsr_command_set(payload, 1);
8649 }
8650 
8651 /* MLCR - Management LED Control Register
8652  * --------------------------------------
8653  * Controls the system LEDs.
8654  */
8655 #define MLXSW_REG_MLCR_ID 0x902B
8656 #define MLXSW_REG_MLCR_LEN 0x0C
8657 
8658 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8659 
8660 /* reg_mlcr_local_port
8661  * Local port number.
8662  * Access: RW
8663  */
8664 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8665 
8666 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8667 
8668 /* reg_mlcr_beacon_duration
8669  * Duration of the beacon to be active, in seconds.
8670  * 0x0 - Will turn off the beacon.
8671  * 0xFFFF - Will turn on the beacon until explicitly turned off.
8672  * Access: RW
8673  */
8674 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8675 
8676 /* reg_mlcr_beacon_remain
8677  * Remaining duration of the beacon, in seconds.
8678  * 0xFFFF indicates an infinite amount of time.
8679  * Access: RO
8680  */
8681 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8682 
8683 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8684 				       bool active)
8685 {
8686 	MLXSW_REG_ZERO(mlcr, payload);
8687 	mlxsw_reg_mlcr_local_port_set(payload, local_port);
8688 	mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8689 					   MLXSW_REG_MLCR_DURATION_MAX : 0);
8690 }
8691 
8692 /* MCQI - Management Component Query Information
8693  * ---------------------------------------------
8694  * This register allows querying information about firmware components.
8695  */
8696 #define MLXSW_REG_MCQI_ID 0x9061
8697 #define MLXSW_REG_MCQI_BASE_LEN 0x18
8698 #define MLXSW_REG_MCQI_CAP_LEN 0x14
8699 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8700 
8701 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8702 
8703 /* reg_mcqi_component_index
8704  * Index of the accessed component.
8705  * Access: Index
8706  */
8707 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8708 
8709 enum mlxfw_reg_mcqi_info_type {
8710 	MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8711 };
8712 
8713 /* reg_mcqi_info_type
8714  * Component properties set.
8715  * Access: RW
8716  */
8717 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8718 
8719 /* reg_mcqi_offset
8720  * The requested/returned data offset from the section start, given in bytes.
8721  * Must be DWORD aligned.
8722  * Access: RW
8723  */
8724 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8725 
8726 /* reg_mcqi_data_size
8727  * The requested/returned data size, given in bytes. If data_size is not DWORD
8728  * aligned, the last bytes are zero padded.
8729  * Access: RW
8730  */
8731 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8732 
8733 /* reg_mcqi_cap_max_component_size
8734  * Maximum size for this component, given in bytes.
8735  * Access: RO
8736  */
8737 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8738 
8739 /* reg_mcqi_cap_log_mcda_word_size
8740  * Log 2 of the access word size in bytes. Read and write access must be aligned
8741  * to the word size. Write access must be done for an integer number of words.
8742  * Access: RO
8743  */
8744 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8745 
8746 /* reg_mcqi_cap_mcda_max_write_size
8747  * Maximal write size for MCDA register
8748  * Access: RO
8749  */
8750 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8751 
8752 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8753 {
8754 	MLXSW_REG_ZERO(mcqi, payload);
8755 	mlxsw_reg_mcqi_component_index_set(payload, component_index);
8756 	mlxsw_reg_mcqi_info_type_set(payload,
8757 				     MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8758 	mlxsw_reg_mcqi_offset_set(payload, 0);
8759 	mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8760 }
8761 
8762 static inline void mlxsw_reg_mcqi_unpack(char *payload,
8763 					 u32 *p_cap_max_component_size,
8764 					 u8 *p_cap_log_mcda_word_size,
8765 					 u16 *p_cap_mcda_max_write_size)
8766 {
8767 	*p_cap_max_component_size =
8768 		mlxsw_reg_mcqi_cap_max_component_size_get(payload);
8769 	*p_cap_log_mcda_word_size =
8770 		mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
8771 	*p_cap_mcda_max_write_size =
8772 		mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
8773 }
8774 
8775 /* MCC - Management Component Control
8776  * ----------------------------------
8777  * Controls the firmware component and updates the FSM.
8778  */
8779 #define MLXSW_REG_MCC_ID 0x9062
8780 #define MLXSW_REG_MCC_LEN 0x1C
8781 
8782 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
8783 
8784 enum mlxsw_reg_mcc_instruction {
8785 	MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
8786 	MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
8787 	MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
8788 	MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
8789 	MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
8790 	MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
8791 };
8792 
8793 /* reg_mcc_instruction
8794  * Command to be executed by the FSM.
8795  * Applicable for write operation only.
8796  * Access: RW
8797  */
8798 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
8799 
8800 /* reg_mcc_component_index
8801  * Index of the accessed component. Applicable only for commands that
8802  * refer to components. Otherwise, this field is reserved.
8803  * Access: Index
8804  */
8805 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
8806 
8807 /* reg_mcc_update_handle
8808  * Token representing the current flow executed by the FSM.
8809  * Access: WO
8810  */
8811 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
8812 
8813 /* reg_mcc_error_code
8814  * Indicates the successful completion of the instruction, or the reason it
8815  * failed
8816  * Access: RO
8817  */
8818 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
8819 
8820 /* reg_mcc_control_state
8821  * Current FSM state
8822  * Access: RO
8823  */
8824 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
8825 
8826 /* reg_mcc_component_size
8827  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
8828  * the size may shorten the update time. Value 0x0 means that size is
8829  * unspecified.
8830  * Access: WO
8831  */
8832 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
8833 
8834 static inline void mlxsw_reg_mcc_pack(char *payload,
8835 				      enum mlxsw_reg_mcc_instruction instr,
8836 				      u16 component_index, u32 update_handle,
8837 				      u32 component_size)
8838 {
8839 	MLXSW_REG_ZERO(mcc, payload);
8840 	mlxsw_reg_mcc_instruction_set(payload, instr);
8841 	mlxsw_reg_mcc_component_index_set(payload, component_index);
8842 	mlxsw_reg_mcc_update_handle_set(payload, update_handle);
8843 	mlxsw_reg_mcc_component_size_set(payload, component_size);
8844 }
8845 
8846 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
8847 					u8 *p_error_code, u8 *p_control_state)
8848 {
8849 	if (p_update_handle)
8850 		*p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
8851 	if (p_error_code)
8852 		*p_error_code = mlxsw_reg_mcc_error_code_get(payload);
8853 	if (p_control_state)
8854 		*p_control_state = mlxsw_reg_mcc_control_state_get(payload);
8855 }
8856 
8857 /* MCDA - Management Component Data Access
8858  * ---------------------------------------
8859  * This register allows reading and writing a firmware component.
8860  */
8861 #define MLXSW_REG_MCDA_ID 0x9063
8862 #define MLXSW_REG_MCDA_BASE_LEN 0x10
8863 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
8864 #define MLXSW_REG_MCDA_LEN \
8865 		(MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
8866 
8867 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
8868 
8869 /* reg_mcda_update_handle
8870  * Token representing the current flow executed by the FSM.
8871  * Access: RW
8872  */
8873 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
8874 
8875 /* reg_mcda_offset
8876  * Offset of accessed address relative to component start. Accesses must be in
8877  * accordance to log_mcda_word_size in MCQI reg.
8878  * Access: RW
8879  */
8880 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
8881 
8882 /* reg_mcda_size
8883  * Size of the data accessed, given in bytes.
8884  * Access: RW
8885  */
8886 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
8887 
8888 /* reg_mcda_data
8889  * Data block accessed.
8890  * Access: RW
8891  */
8892 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
8893 
8894 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
8895 				       u32 offset, u16 size, u8 *data)
8896 {
8897 	int i;
8898 
8899 	MLXSW_REG_ZERO(mcda, payload);
8900 	mlxsw_reg_mcda_update_handle_set(payload, update_handle);
8901 	mlxsw_reg_mcda_offset_set(payload, offset);
8902 	mlxsw_reg_mcda_size_set(payload, size);
8903 
8904 	for (i = 0; i < size / 4; i++)
8905 		mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
8906 }
8907 
8908 /* MPSC - Monitoring Packet Sampling Configuration Register
8909  * --------------------------------------------------------
8910  * MPSC Register is used to configure the Packet Sampling mechanism.
8911  */
8912 #define MLXSW_REG_MPSC_ID 0x9080
8913 #define MLXSW_REG_MPSC_LEN 0x1C
8914 
8915 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
8916 
8917 /* reg_mpsc_local_port
8918  * Local port number
8919  * Not supported for CPU port
8920  * Access: Index
8921  */
8922 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
8923 
8924 /* reg_mpsc_e
8925  * Enable sampling on port local_port
8926  * Access: RW
8927  */
8928 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
8929 
8930 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
8931 
8932 /* reg_mpsc_rate
8933  * Sampling rate = 1 out of rate packets (with randomization around
8934  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
8935  * Access: RW
8936  */
8937 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
8938 
8939 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
8940 				       u32 rate)
8941 {
8942 	MLXSW_REG_ZERO(mpsc, payload);
8943 	mlxsw_reg_mpsc_local_port_set(payload, local_port);
8944 	mlxsw_reg_mpsc_e_set(payload, e);
8945 	mlxsw_reg_mpsc_rate_set(payload, rate);
8946 }
8947 
8948 /* MGPC - Monitoring General Purpose Counter Set Register
8949  * The MGPC register retrieves and sets the General Purpose Counter Set.
8950  */
8951 #define MLXSW_REG_MGPC_ID 0x9081
8952 #define MLXSW_REG_MGPC_LEN 0x18
8953 
8954 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
8955 
8956 /* reg_mgpc_counter_set_type
8957  * Counter set type.
8958  * Access: OP
8959  */
8960 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
8961 
8962 /* reg_mgpc_counter_index
8963  * Counter index.
8964  * Access: Index
8965  */
8966 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
8967 
8968 enum mlxsw_reg_mgpc_opcode {
8969 	/* Nop */
8970 	MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
8971 	/* Clear counters */
8972 	MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
8973 };
8974 
8975 /* reg_mgpc_opcode
8976  * Opcode.
8977  * Access: OP
8978  */
8979 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
8980 
8981 /* reg_mgpc_byte_counter
8982  * Byte counter value.
8983  * Access: RW
8984  */
8985 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
8986 
8987 /* reg_mgpc_packet_counter
8988  * Packet counter value.
8989  * Access: RW
8990  */
8991 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
8992 
8993 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
8994 				       enum mlxsw_reg_mgpc_opcode opcode,
8995 				       enum mlxsw_reg_flow_counter_set_type set_type)
8996 {
8997 	MLXSW_REG_ZERO(mgpc, payload);
8998 	mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
8999 	mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9000 	mlxsw_reg_mgpc_opcode_set(payload, opcode);
9001 }
9002 
9003 /* MPRS - Monitoring Parsing State Register
9004  * ----------------------------------------
9005  * The MPRS register is used for setting up the parsing for hash,
9006  * policy-engine and routing.
9007  */
9008 #define MLXSW_REG_MPRS_ID 0x9083
9009 #define MLXSW_REG_MPRS_LEN 0x14
9010 
9011 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9012 
9013 /* reg_mprs_parsing_depth
9014  * Minimum parsing depth.
9015  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
9016  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
9017  * Access: RW
9018  */
9019 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9020 
9021 /* reg_mprs_parsing_en
9022  * Parsing enable.
9023  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
9024  * NVGRE. Default is enabled. Reserved when SwitchX-2.
9025  * Access: RW
9026  */
9027 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9028 
9029 /* reg_mprs_vxlan_udp_dport
9030  * VxLAN UDP destination port.
9031  * Used for identifying VxLAN packets and for dport field in
9032  * encapsulation. Default is 4789.
9033  * Access: RW
9034  */
9035 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9036 
9037 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9038 				       u16 vxlan_udp_dport)
9039 {
9040 	MLXSW_REG_ZERO(mprs, payload);
9041 	mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9042 	mlxsw_reg_mprs_parsing_en_set(payload, true);
9043 	mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9044 }
9045 
9046 /* TNGCR - Tunneling NVE General Configuration Register
9047  * ----------------------------------------------------
9048  * The TNGCR register is used for setting up the NVE Tunneling configuration.
9049  */
9050 #define MLXSW_REG_TNGCR_ID 0xA001
9051 #define MLXSW_REG_TNGCR_LEN 0x44
9052 
9053 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9054 
9055 enum mlxsw_reg_tngcr_type {
9056 	MLXSW_REG_TNGCR_TYPE_VXLAN,
9057 	MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9058 	MLXSW_REG_TNGCR_TYPE_GENEVE,
9059 	MLXSW_REG_TNGCR_TYPE_NVGRE,
9060 };
9061 
9062 /* reg_tngcr_type
9063  * Tunnel type for encapsulation and decapsulation. The types are mutually
9064  * exclusive.
9065  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
9066  * Access: RW
9067  */
9068 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9069 
9070 /* reg_tngcr_nve_valid
9071  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
9072  * Access: RW
9073  */
9074 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9075 
9076 /* reg_tngcr_nve_ttl_uc
9077  * The TTL for NVE tunnel encapsulation underlay unicast packets.
9078  * Access: RW
9079  */
9080 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9081 
9082 /* reg_tngcr_nve_ttl_mc
9083  * The TTL for NVE tunnel encapsulation underlay multicast packets.
9084  * Access: RW
9085  */
9086 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9087 
9088 enum {
9089 	/* Do not copy flow label. Calculate flow label using nve_flh. */
9090 	MLXSW_REG_TNGCR_FL_NO_COPY,
9091 	/* Copy flow label from inner packet if packet is IPv6 and
9092 	 * encapsulation is by IPv6. Otherwise, calculate flow label using
9093 	 * nve_flh.
9094 	 */
9095 	MLXSW_REG_TNGCR_FL_COPY,
9096 };
9097 
9098 /* reg_tngcr_nve_flc
9099  * For NVE tunnel encapsulation: Flow label copy from inner packet.
9100  * Access: RW
9101  */
9102 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9103 
9104 enum {
9105 	/* Flow label is static. In Spectrum this means '0'. Spectrum-2
9106 	 * uses {nve_fl_prefix, nve_fl_suffix}.
9107 	 */
9108 	MLXSW_REG_TNGCR_FL_NO_HASH,
9109 	/* 8 LSBs of the flow label are calculated from ECMP hash of the
9110 	 * inner packet. 12 MSBs are configured by nve_fl_prefix.
9111 	 */
9112 	MLXSW_REG_TNGCR_FL_HASH,
9113 };
9114 
9115 /* reg_tngcr_nve_flh
9116  * NVE flow label hash.
9117  * Access: RW
9118  */
9119 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9120 
9121 /* reg_tngcr_nve_fl_prefix
9122  * NVE flow label prefix. Constant 12 MSBs of the flow label.
9123  * Access: RW
9124  */
9125 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9126 
9127 /* reg_tngcr_nve_fl_suffix
9128  * NVE flow label suffix. Constant 8 LSBs of the flow label.
9129  * Reserved when nve_flh=1 and for Spectrum.
9130  * Access: RW
9131  */
9132 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9133 
9134 enum {
9135 	/* Source UDP port is fixed (default '0') */
9136 	MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9137 	/* Source UDP port is calculated based on hash */
9138 	MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9139 };
9140 
9141 /* reg_tngcr_nve_udp_sport_type
9142  * NVE UDP source port type.
9143  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
9144  * When the source UDP port is calculated based on hash, then the 8 LSBs
9145  * are calculated from hash the 8 MSBs are configured by
9146  * nve_udp_sport_prefix.
9147  * Access: RW
9148  */
9149 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9150 
9151 /* reg_tngcr_nve_udp_sport_prefix
9152  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
9153  * Reserved when NVE type is NVGRE.
9154  * Access: RW
9155  */
9156 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9157 
9158 /* reg_tngcr_nve_group_size_mc
9159  * The amount of sequential linked lists of MC entries. The first linked
9160  * list is configured by SFD.underlay_mc_ptr.
9161  * Valid values: 1, 2, 4, 8, 16, 32, 64
9162  * The linked list are configured by TNUMT.
9163  * The hash is set by LAG hash.
9164  * Access: RW
9165  */
9166 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9167 
9168 /* reg_tngcr_nve_group_size_flood
9169  * The amount of sequential linked lists of flooding entries. The first
9170  * linked list is configured by SFMR.nve_tunnel_flood_ptr
9171  * Valid values: 1, 2, 4, 8, 16, 32, 64
9172  * The linked list are configured by TNUMT.
9173  * The hash is set by LAG hash.
9174  * Access: RW
9175  */
9176 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9177 
9178 /* reg_tngcr_learn_enable
9179  * During decapsulation, whether to learn from NVE port.
9180  * Reserved when Spectrum-2. See TNPC.
9181  * Access: RW
9182  */
9183 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9184 
9185 /* reg_tngcr_underlay_virtual_router
9186  * Underlay virtual router.
9187  * Reserved when Spectrum-2.
9188  * Access: RW
9189  */
9190 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9191 
9192 /* reg_tngcr_underlay_rif
9193  * Underlay ingress router interface. RIF type should be loopback generic.
9194  * Reserved when Spectrum.
9195  * Access: RW
9196  */
9197 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9198 
9199 /* reg_tngcr_usipv4
9200  * Underlay source IPv4 address of the NVE.
9201  * Access: RW
9202  */
9203 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9204 
9205 /* reg_tngcr_usipv6
9206  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
9207  * modified under traffic of NVE tunneling encapsulation.
9208  * Access: RW
9209  */
9210 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9211 
9212 static inline void mlxsw_reg_tngcr_pack(char *payload,
9213 					enum mlxsw_reg_tngcr_type type,
9214 					bool valid, u8 ttl)
9215 {
9216 	MLXSW_REG_ZERO(tngcr, payload);
9217 	mlxsw_reg_tngcr_type_set(payload, type);
9218 	mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9219 	mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9220 	mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9221 	mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9222 	mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9223 	mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9224 					       MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9225 	mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9226 	mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9227 	mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9228 }
9229 
9230 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
9231  * -------------------------------------------------------
9232  * The TNUMT register is for building the underlay MC table. It is used
9233  * for MC, flooding and BC traffic into the NVE tunnel.
9234  */
9235 #define MLXSW_REG_TNUMT_ID 0xA003
9236 #define MLXSW_REG_TNUMT_LEN 0x20
9237 
9238 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9239 
9240 enum mlxsw_reg_tnumt_record_type {
9241 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9242 	MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9243 	MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9244 };
9245 
9246 /* reg_tnumt_record_type
9247  * Record type.
9248  * Access: RW
9249  */
9250 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9251 
9252 enum mlxsw_reg_tnumt_tunnel_port {
9253 	MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9254 	MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9255 	MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9256 	MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9257 };
9258 
9259 /* reg_tnumt_tunnel_port
9260  * Tunnel port.
9261  * Access: RW
9262  */
9263 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9264 
9265 /* reg_tnumt_underlay_mc_ptr
9266  * Index to the underlay multicast table.
9267  * For Spectrum the index is to the KVD linear.
9268  * Access: Index
9269  */
9270 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9271 
9272 /* reg_tnumt_vnext
9273  * The next_underlay_mc_ptr is valid.
9274  * Access: RW
9275  */
9276 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9277 
9278 /* reg_tnumt_next_underlay_mc_ptr
9279  * The next index to the underlay multicast table.
9280  * Access: RW
9281  */
9282 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9283 
9284 /* reg_tnumt_record_size
9285  * Number of IP addresses in the record.
9286  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
9287  * Access: RW
9288  */
9289 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9290 
9291 /* reg_tnumt_udip
9292  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
9293  * Access: RW
9294  */
9295 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9296 
9297 /* reg_tnumt_udip_ptr
9298  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
9299  * i >= size. The IPv6 addresses are configured by RIPS.
9300  * Access: RW
9301  */
9302 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9303 
9304 static inline void mlxsw_reg_tnumt_pack(char *payload,
9305 					enum mlxsw_reg_tnumt_record_type type,
9306 					enum mlxsw_reg_tnumt_tunnel_port tport,
9307 					u32 underlay_mc_ptr, bool vnext,
9308 					u32 next_underlay_mc_ptr,
9309 					u8 record_size)
9310 {
9311 	MLXSW_REG_ZERO(tnumt, payload);
9312 	mlxsw_reg_tnumt_record_type_set(payload, type);
9313 	mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9314 	mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9315 	mlxsw_reg_tnumt_vnext_set(payload, vnext);
9316 	mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9317 	mlxsw_reg_tnumt_record_size_set(payload, record_size);
9318 }
9319 
9320 /* TNQCR - Tunneling NVE QoS Configuration Register
9321  * ------------------------------------------------
9322  * The TNQCR register configures how QoS is set in encapsulation into the
9323  * underlay network.
9324  */
9325 #define MLXSW_REG_TNQCR_ID 0xA010
9326 #define MLXSW_REG_TNQCR_LEN 0x0C
9327 
9328 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9329 
9330 /* reg_tnqcr_enc_set_dscp
9331  * For encapsulation: How to set DSCP field:
9332  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
9333  * (outer) IP header. If there is no IP header, use TNQDR.dscp
9334  * 1 - Set the DSCP field as TNQDR.dscp
9335  * Access: RW
9336  */
9337 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9338 
9339 static inline void mlxsw_reg_tnqcr_pack(char *payload)
9340 {
9341 	MLXSW_REG_ZERO(tnqcr, payload);
9342 	mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9343 }
9344 
9345 /* TNQDR - Tunneling NVE QoS Default Register
9346  * ------------------------------------------
9347  * The TNQDR register configures the default QoS settings for NVE
9348  * encapsulation.
9349  */
9350 #define MLXSW_REG_TNQDR_ID 0xA011
9351 #define MLXSW_REG_TNQDR_LEN 0x08
9352 
9353 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9354 
9355 /* reg_tnqdr_local_port
9356  * Local port number (receive port). CPU port is supported.
9357  * Access: Index
9358  */
9359 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9360 
9361 /* reg_tnqdr_dscp
9362  * For encapsulation, the default DSCP.
9363  * Access: RW
9364  */
9365 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9366 
9367 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9368 {
9369 	MLXSW_REG_ZERO(tnqdr, payload);
9370 	mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9371 	mlxsw_reg_tnqdr_dscp_set(payload, 0);
9372 }
9373 
9374 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
9375  * --------------------------------------------------------
9376  * The TNEEM register maps ECN of the IP header at the ingress to the
9377  * encapsulation to the ECN of the underlay network.
9378  */
9379 #define MLXSW_REG_TNEEM_ID 0xA012
9380 #define MLXSW_REG_TNEEM_LEN 0x0C
9381 
9382 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
9383 
9384 /* reg_tneem_overlay_ecn
9385  * ECN of the IP header in the overlay network.
9386  * Access: Index
9387  */
9388 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
9389 
9390 /* reg_tneem_underlay_ecn
9391  * ECN of the IP header in the underlay network.
9392  * Access: RW
9393  */
9394 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
9395 
9396 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
9397 					u8 underlay_ecn)
9398 {
9399 	MLXSW_REG_ZERO(tneem, payload);
9400 	mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
9401 	mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
9402 }
9403 
9404 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
9405  * --------------------------------------------------------
9406  * The TNDEM register configures the actions that are done in the
9407  * decapsulation.
9408  */
9409 #define MLXSW_REG_TNDEM_ID 0xA013
9410 #define MLXSW_REG_TNDEM_LEN 0x0C
9411 
9412 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
9413 
9414 /* reg_tndem_underlay_ecn
9415  * ECN field of the IP header in the underlay network.
9416  * Access: Index
9417  */
9418 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
9419 
9420 /* reg_tndem_overlay_ecn
9421  * ECN field of the IP header in the overlay network.
9422  * Access: Index
9423  */
9424 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
9425 
9426 /* reg_tndem_eip_ecn
9427  * Egress IP ECN. ECN field of the IP header of the packet which goes out
9428  * from the decapsulation.
9429  * Access: RW
9430  */
9431 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
9432 
9433 /* reg_tndem_trap_en
9434  * Trap enable:
9435  * 0 - No trap due to decap ECN
9436  * 1 - Trap enable with trap_id
9437  * Access: RW
9438  */
9439 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
9440 
9441 /* reg_tndem_trap_id
9442  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
9443  * Reserved when trap_en is '0'.
9444  * Access: RW
9445  */
9446 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
9447 
9448 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
9449 					u8 overlay_ecn, u8 ecn, bool trap_en,
9450 					u16 trap_id)
9451 {
9452 	MLXSW_REG_ZERO(tndem, payload);
9453 	mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
9454 	mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
9455 	mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
9456 	mlxsw_reg_tndem_trap_en_set(payload, trap_en);
9457 	mlxsw_reg_tndem_trap_id_set(payload, trap_id);
9458 }
9459 
9460 /* TNPC - Tunnel Port Configuration Register
9461  * -----------------------------------------
9462  * The TNPC register is used for tunnel port configuration.
9463  * Reserved when Spectrum.
9464  */
9465 #define MLXSW_REG_TNPC_ID 0xA020
9466 #define MLXSW_REG_TNPC_LEN 0x18
9467 
9468 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
9469 
9470 enum mlxsw_reg_tnpc_tunnel_port {
9471 	MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
9472 	MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
9473 	MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
9474 	MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
9475 };
9476 
9477 /* reg_tnpc_tunnel_port
9478  * Tunnel port.
9479  * Access: Index
9480  */
9481 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
9482 
9483 /* reg_tnpc_learn_enable_v6
9484  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
9485  * Access: RW
9486  */
9487 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
9488 
9489 /* reg_tnpc_learn_enable_v4
9490  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
9491  * Access: RW
9492  */
9493 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
9494 
9495 static inline void mlxsw_reg_tnpc_pack(char *payload,
9496 				       enum mlxsw_reg_tnpc_tunnel_port tport,
9497 				       bool learn_enable)
9498 {
9499 	MLXSW_REG_ZERO(tnpc, payload);
9500 	mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
9501 	mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
9502 	mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
9503 }
9504 
9505 /* TIGCR - Tunneling IPinIP General Configuration Register
9506  * -------------------------------------------------------
9507  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
9508  */
9509 #define MLXSW_REG_TIGCR_ID 0xA801
9510 #define MLXSW_REG_TIGCR_LEN 0x10
9511 
9512 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
9513 
9514 /* reg_tigcr_ipip_ttlc
9515  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
9516  * header.
9517  * Access: RW
9518  */
9519 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
9520 
9521 /* reg_tigcr_ipip_ttl_uc
9522  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
9523  * reg_tigcr_ipip_ttlc is unset.
9524  * Access: RW
9525  */
9526 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
9527 
9528 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
9529 {
9530 	MLXSW_REG_ZERO(tigcr, payload);
9531 	mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
9532 	mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
9533 }
9534 
9535 /* SBPR - Shared Buffer Pools Register
9536  * -----------------------------------
9537  * The SBPR configures and retrieves the shared buffer pools and configuration.
9538  */
9539 #define MLXSW_REG_SBPR_ID 0xB001
9540 #define MLXSW_REG_SBPR_LEN 0x14
9541 
9542 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
9543 
9544 /* shared direstion enum for SBPR, SBCM, SBPM */
9545 enum mlxsw_reg_sbxx_dir {
9546 	MLXSW_REG_SBXX_DIR_INGRESS,
9547 	MLXSW_REG_SBXX_DIR_EGRESS,
9548 };
9549 
9550 /* reg_sbpr_dir
9551  * Direction.
9552  * Access: Index
9553  */
9554 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
9555 
9556 /* reg_sbpr_pool
9557  * Pool index.
9558  * Access: Index
9559  */
9560 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
9561 
9562 /* reg_sbpr_infi_size
9563  * Size is infinite.
9564  * Access: RW
9565  */
9566 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
9567 
9568 /* reg_sbpr_size
9569  * Pool size in buffer cells.
9570  * Reserved when infi_size = 1.
9571  * Access: RW
9572  */
9573 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
9574 
9575 enum mlxsw_reg_sbpr_mode {
9576 	MLXSW_REG_SBPR_MODE_STATIC,
9577 	MLXSW_REG_SBPR_MODE_DYNAMIC,
9578 };
9579 
9580 /* reg_sbpr_mode
9581  * Pool quota calculation mode.
9582  * Access: RW
9583  */
9584 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
9585 
9586 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
9587 				       enum mlxsw_reg_sbxx_dir dir,
9588 				       enum mlxsw_reg_sbpr_mode mode, u32 size,
9589 				       bool infi_size)
9590 {
9591 	MLXSW_REG_ZERO(sbpr, payload);
9592 	mlxsw_reg_sbpr_pool_set(payload, pool);
9593 	mlxsw_reg_sbpr_dir_set(payload, dir);
9594 	mlxsw_reg_sbpr_mode_set(payload, mode);
9595 	mlxsw_reg_sbpr_size_set(payload, size);
9596 	mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
9597 }
9598 
9599 /* SBCM - Shared Buffer Class Management Register
9600  * ----------------------------------------------
9601  * The SBCM register configures and retrieves the shared buffer allocation
9602  * and configuration according to Port-PG, including the binding to pool
9603  * and definition of the associated quota.
9604  */
9605 #define MLXSW_REG_SBCM_ID 0xB002
9606 #define MLXSW_REG_SBCM_LEN 0x28
9607 
9608 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
9609 
9610 /* reg_sbcm_local_port
9611  * Local port number.
9612  * For Ingress: excludes CPU port and Router port
9613  * For Egress: excludes IP Router
9614  * Access: Index
9615  */
9616 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
9617 
9618 /* reg_sbcm_pg_buff
9619  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
9620  * For PG buffer: range is 0..cap_max_pg_buffers - 1
9621  * For traffic class: range is 0..cap_max_tclass - 1
9622  * Note that when traffic class is in MC aware mode then the traffic
9623  * classes which are MC aware cannot be configured.
9624  * Access: Index
9625  */
9626 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
9627 
9628 /* reg_sbcm_dir
9629  * Direction.
9630  * Access: Index
9631  */
9632 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
9633 
9634 /* reg_sbcm_min_buff
9635  * Minimum buffer size for the limiter, in cells.
9636  * Access: RW
9637  */
9638 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
9639 
9640 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
9641 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
9642 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
9643 
9644 /* reg_sbcm_infi_max
9645  * Max buffer is infinite.
9646  * Access: RW
9647  */
9648 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
9649 
9650 /* reg_sbcm_max_buff
9651  * When the pool associated to the port-pg/tclass is configured to
9652  * static, Maximum buffer size for the limiter configured in cells.
9653  * When the pool associated to the port-pg/tclass is configured to
9654  * dynamic, the max_buff holds the "alpha" parameter, supporting
9655  * the following values:
9656  * 0: 0
9657  * i: (1/128)*2^(i-1), for i=1..14
9658  * 0xFF: Infinity
9659  * Reserved when infi_max = 1.
9660  * Access: RW
9661  */
9662 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
9663 
9664 /* reg_sbcm_pool
9665  * Association of the port-priority to a pool.
9666  * Access: RW
9667  */
9668 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
9669 
9670 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
9671 				       enum mlxsw_reg_sbxx_dir dir,
9672 				       u32 min_buff, u32 max_buff,
9673 				       bool infi_max, u8 pool)
9674 {
9675 	MLXSW_REG_ZERO(sbcm, payload);
9676 	mlxsw_reg_sbcm_local_port_set(payload, local_port);
9677 	mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
9678 	mlxsw_reg_sbcm_dir_set(payload, dir);
9679 	mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
9680 	mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
9681 	mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
9682 	mlxsw_reg_sbcm_pool_set(payload, pool);
9683 }
9684 
9685 /* SBPM - Shared Buffer Port Management Register
9686  * ---------------------------------------------
9687  * The SBPM register configures and retrieves the shared buffer allocation
9688  * and configuration according to Port-Pool, including the definition
9689  * of the associated quota.
9690  */
9691 #define MLXSW_REG_SBPM_ID 0xB003
9692 #define MLXSW_REG_SBPM_LEN 0x28
9693 
9694 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
9695 
9696 /* reg_sbpm_local_port
9697  * Local port number.
9698  * For Ingress: excludes CPU port and Router port
9699  * For Egress: excludes IP Router
9700  * Access: Index
9701  */
9702 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
9703 
9704 /* reg_sbpm_pool
9705  * The pool associated to quota counting on the local_port.
9706  * Access: Index
9707  */
9708 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
9709 
9710 /* reg_sbpm_dir
9711  * Direction.
9712  * Access: Index
9713  */
9714 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
9715 
9716 /* reg_sbpm_buff_occupancy
9717  * Current buffer occupancy in cells.
9718  * Access: RO
9719  */
9720 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
9721 
9722 /* reg_sbpm_clr
9723  * Clear Max Buffer Occupancy
9724  * When this bit is set, max_buff_occupancy field is cleared (and a
9725  * new max value is tracked from the time the clear was performed).
9726  * Access: OP
9727  */
9728 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
9729 
9730 /* reg_sbpm_max_buff_occupancy
9731  * Maximum value of buffer occupancy in cells monitored. Cleared by
9732  * writing to the clr field.
9733  * Access: RO
9734  */
9735 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
9736 
9737 /* reg_sbpm_min_buff
9738  * Minimum buffer size for the limiter, in cells.
9739  * Access: RW
9740  */
9741 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
9742 
9743 /* reg_sbpm_max_buff
9744  * When the pool associated to the port-pg/tclass is configured to
9745  * static, Maximum buffer size for the limiter configured in cells.
9746  * When the pool associated to the port-pg/tclass is configured to
9747  * dynamic, the max_buff holds the "alpha" parameter, supporting
9748  * the following values:
9749  * 0: 0
9750  * i: (1/128)*2^(i-1), for i=1..14
9751  * 0xFF: Infinity
9752  * Access: RW
9753  */
9754 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
9755 
9756 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
9757 				       enum mlxsw_reg_sbxx_dir dir, bool clr,
9758 				       u32 min_buff, u32 max_buff)
9759 {
9760 	MLXSW_REG_ZERO(sbpm, payload);
9761 	mlxsw_reg_sbpm_local_port_set(payload, local_port);
9762 	mlxsw_reg_sbpm_pool_set(payload, pool);
9763 	mlxsw_reg_sbpm_dir_set(payload, dir);
9764 	mlxsw_reg_sbpm_clr_set(payload, clr);
9765 	mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
9766 	mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
9767 }
9768 
9769 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
9770 					 u32 *p_max_buff_occupancy)
9771 {
9772 	*p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
9773 	*p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
9774 }
9775 
9776 /* SBMM - Shared Buffer Multicast Management Register
9777  * --------------------------------------------------
9778  * The SBMM register configures and retrieves the shared buffer allocation
9779  * and configuration for MC packets according to Switch-Priority, including
9780  * the binding to pool and definition of the associated quota.
9781  */
9782 #define MLXSW_REG_SBMM_ID 0xB004
9783 #define MLXSW_REG_SBMM_LEN 0x28
9784 
9785 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
9786 
9787 /* reg_sbmm_prio
9788  * Switch Priority.
9789  * Access: Index
9790  */
9791 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
9792 
9793 /* reg_sbmm_min_buff
9794  * Minimum buffer size for the limiter, in cells.
9795  * Access: RW
9796  */
9797 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
9798 
9799 /* reg_sbmm_max_buff
9800  * When the pool associated to the port-pg/tclass is configured to
9801  * static, Maximum buffer size for the limiter configured in cells.
9802  * When the pool associated to the port-pg/tclass is configured to
9803  * dynamic, the max_buff holds the "alpha" parameter, supporting
9804  * the following values:
9805  * 0: 0
9806  * i: (1/128)*2^(i-1), for i=1..14
9807  * 0xFF: Infinity
9808  * Access: RW
9809  */
9810 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
9811 
9812 /* reg_sbmm_pool
9813  * Association of the port-priority to a pool.
9814  * Access: RW
9815  */
9816 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
9817 
9818 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
9819 				       u32 max_buff, u8 pool)
9820 {
9821 	MLXSW_REG_ZERO(sbmm, payload);
9822 	mlxsw_reg_sbmm_prio_set(payload, prio);
9823 	mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
9824 	mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
9825 	mlxsw_reg_sbmm_pool_set(payload, pool);
9826 }
9827 
9828 /* SBSR - Shared Buffer Status Register
9829  * ------------------------------------
9830  * The SBSR register retrieves the shared buffer occupancy according to
9831  * Port-Pool. Note that this register enables reading a large amount of data.
9832  * It is the user's responsibility to limit the amount of data to ensure the
9833  * response can match the maximum transfer unit. In case the response exceeds
9834  * the maximum transport unit, it will be truncated with no special notice.
9835  */
9836 #define MLXSW_REG_SBSR_ID 0xB005
9837 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
9838 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
9839 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
9840 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +	\
9841 			    MLXSW_REG_SBSR_REC_LEN *	\
9842 			    MLXSW_REG_SBSR_REC_MAX_COUNT)
9843 
9844 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
9845 
9846 /* reg_sbsr_clr
9847  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
9848  * field is cleared (and a new max value is tracked from the time the clear
9849  * was performed).
9850  * Access: OP
9851  */
9852 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
9853 
9854 /* reg_sbsr_ingress_port_mask
9855  * Bit vector for all ingress network ports.
9856  * Indicates which of the ports (for which the relevant bit is set)
9857  * are affected by the set operation. Configuration of any other port
9858  * does not change.
9859  * Access: Index
9860  */
9861 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
9862 
9863 /* reg_sbsr_pg_buff_mask
9864  * Bit vector for all switch priority groups.
9865  * Indicates which of the priorities (for which the relevant bit is set)
9866  * are affected by the set operation. Configuration of any other priority
9867  * does not change.
9868  * Range is 0..cap_max_pg_buffers - 1
9869  * Access: Index
9870  */
9871 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
9872 
9873 /* reg_sbsr_egress_port_mask
9874  * Bit vector for all egress network ports.
9875  * Indicates which of the ports (for which the relevant bit is set)
9876  * are affected by the set operation. Configuration of any other port
9877  * does not change.
9878  * Access: Index
9879  */
9880 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
9881 
9882 /* reg_sbsr_tclass_mask
9883  * Bit vector for all traffic classes.
9884  * Indicates which of the traffic classes (for which the relevant bit is
9885  * set) are affected by the set operation. Configuration of any other
9886  * traffic class does not change.
9887  * Range is 0..cap_max_tclass - 1
9888  * Access: Index
9889  */
9890 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
9891 
9892 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
9893 {
9894 	MLXSW_REG_ZERO(sbsr, payload);
9895 	mlxsw_reg_sbsr_clr_set(payload, clr);
9896 }
9897 
9898 /* reg_sbsr_rec_buff_occupancy
9899  * Current buffer occupancy in cells.
9900  * Access: RO
9901  */
9902 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
9903 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
9904 
9905 /* reg_sbsr_rec_max_buff_occupancy
9906  * Maximum value of buffer occupancy in cells monitored. Cleared by
9907  * writing to the clr field.
9908  * Access: RO
9909  */
9910 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
9911 		     0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
9912 
9913 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
9914 					     u32 *p_buff_occupancy,
9915 					     u32 *p_max_buff_occupancy)
9916 {
9917 	*p_buff_occupancy =
9918 		mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
9919 	*p_max_buff_occupancy =
9920 		mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
9921 }
9922 
9923 /* SBIB - Shared Buffer Internal Buffer Register
9924  * ---------------------------------------------
9925  * The SBIB register configures per port buffers for internal use. The internal
9926  * buffers consume memory on the port buffers (note that the port buffers are
9927  * used also by PBMC).
9928  *
9929  * For Spectrum this is used for egress mirroring.
9930  */
9931 #define MLXSW_REG_SBIB_ID 0xB006
9932 #define MLXSW_REG_SBIB_LEN 0x10
9933 
9934 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
9935 
9936 /* reg_sbib_local_port
9937  * Local port number
9938  * Not supported for CPU port and router port
9939  * Access: Index
9940  */
9941 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
9942 
9943 /* reg_sbib_buff_size
9944  * Units represented in cells
9945  * Allowed range is 0 to (cap_max_headroom_size - 1)
9946  * Default is 0
9947  * Access: RW
9948  */
9949 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
9950 
9951 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
9952 				       u32 buff_size)
9953 {
9954 	MLXSW_REG_ZERO(sbib, payload);
9955 	mlxsw_reg_sbib_local_port_set(payload, local_port);
9956 	mlxsw_reg_sbib_buff_size_set(payload, buff_size);
9957 }
9958 
9959 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
9960 	MLXSW_REG(sgcr),
9961 	MLXSW_REG(spad),
9962 	MLXSW_REG(smid),
9963 	MLXSW_REG(sspr),
9964 	MLXSW_REG(sfdat),
9965 	MLXSW_REG(sfd),
9966 	MLXSW_REG(sfn),
9967 	MLXSW_REG(spms),
9968 	MLXSW_REG(spvid),
9969 	MLXSW_REG(spvm),
9970 	MLXSW_REG(spaft),
9971 	MLXSW_REG(sfgc),
9972 	MLXSW_REG(sftr),
9973 	MLXSW_REG(sfdf),
9974 	MLXSW_REG(sldr),
9975 	MLXSW_REG(slcr),
9976 	MLXSW_REG(slcor),
9977 	MLXSW_REG(spmlr),
9978 	MLXSW_REG(svfa),
9979 	MLXSW_REG(svpe),
9980 	MLXSW_REG(sfmr),
9981 	MLXSW_REG(spvmlr),
9982 	MLXSW_REG(cwtp),
9983 	MLXSW_REG(cwtpm),
9984 	MLXSW_REG(pgcr),
9985 	MLXSW_REG(ppbt),
9986 	MLXSW_REG(pacl),
9987 	MLXSW_REG(pagt),
9988 	MLXSW_REG(ptar),
9989 	MLXSW_REG(ppbs),
9990 	MLXSW_REG(prcr),
9991 	MLXSW_REG(pefa),
9992 	MLXSW_REG(pemrbt),
9993 	MLXSW_REG(ptce2),
9994 	MLXSW_REG(perpt),
9995 	MLXSW_REG(peabfe),
9996 	MLXSW_REG(perar),
9997 	MLXSW_REG(ptce3),
9998 	MLXSW_REG(percr),
9999 	MLXSW_REG(pererp),
10000 	MLXSW_REG(iedr),
10001 	MLXSW_REG(qpts),
10002 	MLXSW_REG(qpcr),
10003 	MLXSW_REG(qtct),
10004 	MLXSW_REG(qeec),
10005 	MLXSW_REG(qrwe),
10006 	MLXSW_REG(qpdsm),
10007 	MLXSW_REG(qpdpm),
10008 	MLXSW_REG(qtctm),
10009 	MLXSW_REG(pmlp),
10010 	MLXSW_REG(pmtu),
10011 	MLXSW_REG(ptys),
10012 	MLXSW_REG(ppad),
10013 	MLXSW_REG(paos),
10014 	MLXSW_REG(pfcc),
10015 	MLXSW_REG(ppcnt),
10016 	MLXSW_REG(plib),
10017 	MLXSW_REG(pptb),
10018 	MLXSW_REG(pbmc),
10019 	MLXSW_REG(pspa),
10020 	MLXSW_REG(pplr),
10021 	MLXSW_REG(htgt),
10022 	MLXSW_REG(hpkt),
10023 	MLXSW_REG(rgcr),
10024 	MLXSW_REG(ritr),
10025 	MLXSW_REG(rtar),
10026 	MLXSW_REG(ratr),
10027 	MLXSW_REG(rtdp),
10028 	MLXSW_REG(rdpm),
10029 	MLXSW_REG(ricnt),
10030 	MLXSW_REG(rrcr),
10031 	MLXSW_REG(ralta),
10032 	MLXSW_REG(ralst),
10033 	MLXSW_REG(raltb),
10034 	MLXSW_REG(ralue),
10035 	MLXSW_REG(rauht),
10036 	MLXSW_REG(raleu),
10037 	MLXSW_REG(rauhtd),
10038 	MLXSW_REG(rigr2),
10039 	MLXSW_REG(recr2),
10040 	MLXSW_REG(rmft2),
10041 	MLXSW_REG(mfcr),
10042 	MLXSW_REG(mfsc),
10043 	MLXSW_REG(mfsm),
10044 	MLXSW_REG(mfsl),
10045 	MLXSW_REG(fore),
10046 	MLXSW_REG(mtcap),
10047 	MLXSW_REG(mtmp),
10048 	MLXSW_REG(mtbr),
10049 	MLXSW_REG(mcia),
10050 	MLXSW_REG(mpat),
10051 	MLXSW_REG(mpar),
10052 	MLXSW_REG(mgir),
10053 	MLXSW_REG(mrsr),
10054 	MLXSW_REG(mlcr),
10055 	MLXSW_REG(mpsc),
10056 	MLXSW_REG(mcqi),
10057 	MLXSW_REG(mcc),
10058 	MLXSW_REG(mcda),
10059 	MLXSW_REG(mgpc),
10060 	MLXSW_REG(mprs),
10061 	MLXSW_REG(tngcr),
10062 	MLXSW_REG(tnumt),
10063 	MLXSW_REG(tnqcr),
10064 	MLXSW_REG(tnqdr),
10065 	MLXSW_REG(tneem),
10066 	MLXSW_REG(tndem),
10067 	MLXSW_REG(tnpc),
10068 	MLXSW_REG(tigcr),
10069 	MLXSW_REG(sbpr),
10070 	MLXSW_REG(sbcm),
10071 	MLXSW_REG(sbpm),
10072 	MLXSW_REG(sbmm),
10073 	MLXSW_REG(sbsr),
10074 	MLXSW_REG(sbib),
10075 };
10076 
10077 static inline const char *mlxsw_reg_id_str(u16 reg_id)
10078 {
10079 	const struct mlxsw_reg_info *reg_info;
10080 	int i;
10081 
10082 	for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10083 		reg_info = mlxsw_reg_infos[i];
10084 		if (reg_info->id == reg_id)
10085 			return reg_info->name;
10086 	}
10087 	return "*UNKNOWN*";
10088 }
10089 
10090 /* PUDE - Port Up / Down Event
10091  * ---------------------------
10092  * Reports the operational state change of a port.
10093  */
10094 #define MLXSW_REG_PUDE_LEN 0x10
10095 
10096 /* reg_pude_swid
10097  * Switch partition ID with which to associate the port.
10098  * Access: Index
10099  */
10100 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10101 
10102 /* reg_pude_local_port
10103  * Local port number.
10104  * Access: Index
10105  */
10106 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10107 
10108 /* reg_pude_admin_status
10109  * Port administrative state (the desired state).
10110  * 1 - Up.
10111  * 2 - Down.
10112  * 3 - Up once. This means that in case of link failure, the port won't go
10113  *     into polling mode, but will wait to be re-enabled by software.
10114  * 4 - Disabled by system. Can only be set by hardware.
10115  * Access: RO
10116  */
10117 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10118 
10119 /* reg_pude_oper_status
10120  * Port operatioanl state.
10121  * 1 - Up.
10122  * 2 - Down.
10123  * 3 - Down by port failure. This means that the device will not let the
10124  *     port up again until explicitly specified by software.
10125  * Access: RO
10126  */
10127 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
10128 
10129 #endif
10130