1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, u16 vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 393 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 394 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 395 } 396 397 /* reg_sfd_uc_lag_sub_port 398 * LAG sub port. 399 * Must be 0 if multichannel VEPA is not enabled. 400 * Access: RW 401 */ 402 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 403 MLXSW_REG_SFD_REC_LEN, 0x08, false); 404 405 /* reg_sfd_uc_lag_set_vid 406 * Set VID. 407 * 0 - Do not update VID. 408 * 1 - Set VID. 409 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 410 * Access: RW 411 * 412 * Note: Reserved when legacy bridge model is used. 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_lag_fid_vid 418 * Filtering ID or VLAN ID 419 * For SwitchX and SwitchX-2: 420 * - Dynamic entries (policy 2,3) use FID 421 * - Static entries (policy 0) use VID 422 * - When independent learning is configured, VID=FID 423 * For Spectrum: use FID for both Dynamic and Static entries. 424 * VID should not be used. 425 * Access: Index 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 428 MLXSW_REG_SFD_REC_LEN, 0x08, false); 429 430 /* reg_sfd_uc_lag_lag_vid 431 * New vlan ID. 432 * Access: RW 433 * 434 * Note: Reserved when legacy bridge model is used and set_vid=0. 435 */ 436 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 437 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 438 439 /* reg_sfd_uc_lag_lag_id 440 * LAG Identifier - pointer into the LAG descriptor table. 441 * Access: RW 442 */ 443 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 444 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 445 446 static inline void 447 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 448 enum mlxsw_reg_sfd_rec_policy policy, 449 const char *mac, u16 fid_vid, 450 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 451 u16 lag_id) 452 { 453 mlxsw_reg_sfd_rec_pack(payload, rec_index, 454 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 455 mac, action); 456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 457 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 458 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 459 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 460 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 461 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 462 } 463 464 /* reg_sfd_mc_pgi 465 * 466 * Multicast port group index - index into the port group table. 467 * Value 0x1FFF indicates the pgi should point to the MID entry. 468 * For Spectrum this value must be set to 0x1FFF 469 * Access: RW 470 */ 471 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 472 MLXSW_REG_SFD_REC_LEN, 0x08, false); 473 474 /* reg_sfd_mc_fid_vid 475 * 476 * Filtering ID or VLAN ID 477 * Access: Index 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x08, false); 481 482 /* reg_sfd_mc_mid 483 * 484 * Multicast identifier - global identifier that represents the multicast 485 * group across all devices. 486 * Access: RW 487 */ 488 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 489 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 490 491 static inline void 492 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 493 const char *mac, u16 fid_vid, 494 enum mlxsw_reg_sfd_rec_action action, u16 mid) 495 { 496 mlxsw_reg_sfd_rec_pack(payload, rec_index, 497 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 498 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 499 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 500 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 501 } 502 503 /* reg_sfd_uc_tunnel_uip_msb 504 * When protocol is IPv4, the most significant byte of the underlay IPv4 505 * destination IP. 506 * When protocol is IPv6, reserved. 507 * Access: RW 508 */ 509 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 510 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 511 512 /* reg_sfd_uc_tunnel_fid 513 * Filtering ID. 514 * Access: Index 515 */ 516 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 517 MLXSW_REG_SFD_REC_LEN, 0x08, false); 518 519 enum mlxsw_reg_sfd_uc_tunnel_protocol { 520 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 521 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 522 }; 523 524 /* reg_sfd_uc_tunnel_protocol 525 * IP protocol. 526 * Access: RW 527 */ 528 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 529 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 530 531 /* reg_sfd_uc_tunnel_uip_lsb 532 * When protocol is IPv4, the least significant bytes of the underlay 533 * IPv4 destination IP. 534 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 535 * which is configured by RIPS. 536 * Access: RW 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 539 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 540 541 static inline void 542 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 543 enum mlxsw_reg_sfd_rec_policy policy, 544 const char *mac, u16 fid, 545 enum mlxsw_reg_sfd_rec_action action, 546 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 547 { 548 mlxsw_reg_sfd_rec_pack(payload, rec_index, 549 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 550 action); 551 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 552 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 553 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 554 } 555 556 static inline void 557 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 558 enum mlxsw_reg_sfd_rec_policy policy, 559 const char *mac, u16 fid, 560 enum mlxsw_reg_sfd_rec_action action, u32 uip) 561 { 562 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 563 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 564 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 565 action, 566 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 567 } 568 569 static inline void 570 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 571 u16 fid, enum mlxsw_reg_sfd_rec_action action, 572 u32 uip_ptr) 573 { 574 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 575 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 576 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 577 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 578 mac, fid, action, 579 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 580 } 581 582 enum mlxsw_reg_tunnel_port { 583 MLXSW_REG_TUNNEL_PORT_NVE, 584 MLXSW_REG_TUNNEL_PORT_VPLS, 585 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 586 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 587 }; 588 589 /* SFN - Switch FDB Notification Register 590 * ------------------------------------------- 591 * The switch provides notifications on newly learned FDB entries and 592 * aged out entries. The notifications can be polled by software. 593 */ 594 #define MLXSW_REG_SFN_ID 0x200B 595 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 596 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 597 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 598 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 599 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 600 601 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 602 603 /* reg_sfn_swid 604 * Switch partition ID. 605 * Access: Index 606 */ 607 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 608 609 /* reg_sfn_end 610 * Forces the current session to end. 611 * Access: OP 612 */ 613 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 614 615 /* reg_sfn_num_rec 616 * Request: Number of learned notifications and aged-out notification 617 * records requested. 618 * Response: Number of notification records returned (must be smaller 619 * than or equal to the value requested) 620 * Ranges 0..64 621 * Access: OP 622 */ 623 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 624 625 static inline void mlxsw_reg_sfn_pack(char *payload) 626 { 627 MLXSW_REG_ZERO(sfn, payload); 628 mlxsw_reg_sfn_swid_set(payload, 0); 629 mlxsw_reg_sfn_end_set(payload, 0); 630 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 631 } 632 633 /* reg_sfn_rec_swid 634 * Switch partition ID. 635 * Access: RO 636 */ 637 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 638 MLXSW_REG_SFN_REC_LEN, 0x00, false); 639 640 enum mlxsw_reg_sfn_rec_type { 641 /* MAC addresses learned on a regular port. */ 642 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 643 /* MAC addresses learned on a LAG port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 645 /* Aged-out MAC address on a regular port. */ 646 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 647 /* Aged-out MAC address on a LAG port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 649 /* Learned unicast tunnel record. */ 650 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 651 /* Aged-out unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 653 }; 654 655 /* reg_sfn_rec_type 656 * Notification record type. 657 * Access: RO 658 */ 659 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 660 MLXSW_REG_SFN_REC_LEN, 0x00, false); 661 662 /* reg_sfn_rec_mac 663 * MAC address. 664 * Access: RO 665 */ 666 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 667 MLXSW_REG_SFN_REC_LEN, 0x02); 668 669 /* reg_sfn_mac_sub_port 670 * VEPA channel on the local port. 671 * 0 if multichannel VEPA is not enabled. 672 * Access: RO 673 */ 674 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 675 MLXSW_REG_SFN_REC_LEN, 0x08, false); 676 677 /* reg_sfn_mac_fid 678 * Filtering identifier. 679 * Access: RO 680 */ 681 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 682 MLXSW_REG_SFN_REC_LEN, 0x08, false); 683 684 /* reg_sfn_mac_system_port 685 * Unique port identifier for the final destination of the packet. 686 * Access: RO 687 */ 688 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 689 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 690 691 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 692 char *mac, u16 *p_vid, 693 u16 *p_local_port) 694 { 695 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 696 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 697 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 698 } 699 700 /* reg_sfn_mac_lag_lag_id 701 * LAG ID (pointer into the LAG descriptor table). 702 * Access: RO 703 */ 704 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 705 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 706 707 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 708 char *mac, u16 *p_vid, 709 u16 *p_lag_id) 710 { 711 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 712 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 713 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 714 } 715 716 /* reg_sfn_uc_tunnel_uip_msb 717 * When protocol is IPv4, the most significant byte of the underlay IPv4 718 * address of the remote VTEP. 719 * When protocol is IPv6, reserved. 720 * Access: RO 721 */ 722 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 723 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 724 725 enum mlxsw_reg_sfn_uc_tunnel_protocol { 726 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 727 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 728 }; 729 730 /* reg_sfn_uc_tunnel_protocol 731 * IP protocol. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 735 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_uip_lsb 738 * When protocol is IPv4, the least significant bytes of the underlay 739 * IPv4 address of the remote VTEP. 740 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 741 * Access: RO 742 */ 743 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 744 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 745 746 /* reg_sfn_uc_tunnel_port 747 * Tunnel port. 748 * Reserved on Spectrum. 749 * Access: RO 750 */ 751 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 752 MLXSW_REG_SFN_REC_LEN, 0x10, false); 753 754 static inline void 755 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 756 u16 *p_fid, u32 *p_uip, 757 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 758 { 759 u32 uip_msb, uip_lsb; 760 761 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 762 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 763 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 764 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 765 *p_uip = uip_msb << 24 | uip_lsb; 766 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 767 } 768 769 /* SPMS - Switch Port MSTP/RSTP State Register 770 * ------------------------------------------- 771 * Configures the spanning tree state of a physical port. 772 */ 773 #define MLXSW_REG_SPMS_ID 0x200D 774 #define MLXSW_REG_SPMS_LEN 0x404 775 776 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 777 778 /* reg_spms_local_port 779 * Local port number. 780 * Access: Index 781 */ 782 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 783 784 enum mlxsw_reg_spms_state { 785 MLXSW_REG_SPMS_STATE_NO_CHANGE, 786 MLXSW_REG_SPMS_STATE_DISCARDING, 787 MLXSW_REG_SPMS_STATE_LEARNING, 788 MLXSW_REG_SPMS_STATE_FORWARDING, 789 }; 790 791 /* reg_spms_state 792 * Spanning tree state of each VLAN ID (VID) of the local port. 793 * 0 - Do not change spanning tree state (used only when writing). 794 * 1 - Discarding. No learning or forwarding to/from this port (default). 795 * 2 - Learning. Port is learning, but not forwarding. 796 * 3 - Forwarding. Port is learning and forwarding. 797 * Access: RW 798 */ 799 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 800 801 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 802 { 803 MLXSW_REG_ZERO(spms, payload); 804 mlxsw_reg_spms_local_port_set(payload, local_port); 805 } 806 807 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 808 enum mlxsw_reg_spms_state state) 809 { 810 mlxsw_reg_spms_state_set(payload, vid, state); 811 } 812 813 /* SPVID - Switch Port VID 814 * ----------------------- 815 * The switch port VID configures the default VID for a port. 816 */ 817 #define MLXSW_REG_SPVID_ID 0x200E 818 #define MLXSW_REG_SPVID_LEN 0x08 819 820 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 821 822 /* reg_spvid_tport 823 * Port is tunnel port. 824 * Reserved when SwitchX/-2 or Spectrum-1. 825 * Access: Index 826 */ 827 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 828 829 /* reg_spvid_local_port 830 * When tport = 0: Local port number. Not supported for CPU port. 831 * When tport = 1: Tunnel port. 832 * Access: Index 833 */ 834 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 835 836 /* reg_spvid_sub_port 837 * Virtual port within the physical port. 838 * Should be set to 0 when virtual ports are not enabled on the port. 839 * Access: Index 840 */ 841 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 842 843 /* reg_spvid_egr_et_set 844 * When VLAN is pushed at ingress (for untagged packets or for 845 * QinQ push mode) then the EtherType is decided at the egress port. 846 * Reserved when Spectrum-1. 847 * Access: RW 848 */ 849 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 850 851 /* reg_spvid_et_vlan 852 * EtherType used for when VLAN is pushed at ingress (for untagged 853 * packets or for QinQ push mode). 854 * 0: ether_type0 - (default) 855 * 1: ether_type1 856 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 857 * Ethertype IDs are configured by SVER. 858 * Reserved when egr_et_set = 1. 859 * Access: RW 860 */ 861 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 862 863 /* reg_spvid_pvid 864 * Port default VID 865 * Access: RW 866 */ 867 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 868 869 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 870 u8 et_vlan) 871 { 872 MLXSW_REG_ZERO(spvid, payload); 873 mlxsw_reg_spvid_local_port_set(payload, local_port); 874 mlxsw_reg_spvid_pvid_set(payload, pvid); 875 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 876 } 877 878 /* SPVM - Switch Port VLAN Membership 879 * ---------------------------------- 880 * The Switch Port VLAN Membership register configures the VLAN membership 881 * of a port in a VLAN denoted by VID. VLAN membership is managed per 882 * virtual port. The register can be used to add and remove VID(s) from a port. 883 */ 884 #define MLXSW_REG_SPVM_ID 0x200F 885 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 886 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 887 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 888 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 889 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 890 891 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 892 893 /* reg_spvm_pt 894 * Priority tagged. If this bit is set, packets forwarded to the port with 895 * untagged VLAN membership (u bit is set) will be tagged with priority tag 896 * (VID=0) 897 * Access: RW 898 */ 899 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 900 901 /* reg_spvm_pte 902 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 903 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 904 * Access: WO 905 */ 906 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 907 908 /* reg_spvm_local_port 909 * Local port number. 910 * Access: Index 911 */ 912 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 913 914 /* reg_spvm_sub_port 915 * Virtual port within the physical port. 916 * Should be set to 0 when virtual ports are not enabled on the port. 917 * Access: Index 918 */ 919 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 920 921 /* reg_spvm_num_rec 922 * Number of records to update. Each record contains: i, e, u, vid. 923 * Access: OP 924 */ 925 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 926 927 /* reg_spvm_rec_i 928 * Ingress membership in VLAN ID. 929 * Access: Index 930 */ 931 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 932 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 933 MLXSW_REG_SPVM_REC_LEN, 0, false); 934 935 /* reg_spvm_rec_e 936 * Egress membership in VLAN ID. 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 940 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_u 944 * Untagged - port is an untagged member - egress transmission uses untagged 945 * frames on VID<n> 946 * Access: Index 947 */ 948 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 949 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 950 MLXSW_REG_SPVM_REC_LEN, 0, false); 951 952 /* reg_spvm_rec_vid 953 * Egress membership in VLAN ID. 954 * Access: Index 955 */ 956 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 957 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 958 MLXSW_REG_SPVM_REC_LEN, 0, false); 959 960 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 961 u16 vid_begin, u16 vid_end, 962 bool is_member, bool untagged) 963 { 964 int size = vid_end - vid_begin + 1; 965 int i; 966 967 MLXSW_REG_ZERO(spvm, payload); 968 mlxsw_reg_spvm_local_port_set(payload, local_port); 969 mlxsw_reg_spvm_num_rec_set(payload, size); 970 971 for (i = 0; i < size; i++) { 972 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 973 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 974 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 975 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 976 } 977 } 978 979 /* SPAFT - Switch Port Acceptable Frame Types 980 * ------------------------------------------ 981 * The Switch Port Acceptable Frame Types register configures the frame 982 * admittance of the port. 983 */ 984 #define MLXSW_REG_SPAFT_ID 0x2010 985 #define MLXSW_REG_SPAFT_LEN 0x08 986 987 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 988 989 /* reg_spaft_local_port 990 * Local port number. 991 * Access: Index 992 * 993 * Note: CPU port is not supported (all tag types are allowed). 994 */ 995 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 996 997 /* reg_spaft_sub_port 998 * Virtual port within the physical port. 999 * Should be set to 0 when virtual ports are not enabled on the port. 1000 * Access: RW 1001 */ 1002 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1003 1004 /* reg_spaft_allow_untagged 1005 * When set, untagged frames on the ingress are allowed (default). 1006 * Access: RW 1007 */ 1008 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1009 1010 /* reg_spaft_allow_prio_tagged 1011 * When set, priority tagged frames on the ingress are allowed (default). 1012 * Access: RW 1013 */ 1014 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1015 1016 /* reg_spaft_allow_tagged 1017 * When set, tagged frames on the ingress are allowed (default). 1018 * Access: RW 1019 */ 1020 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1021 1022 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1023 bool allow_untagged) 1024 { 1025 MLXSW_REG_ZERO(spaft, payload); 1026 mlxsw_reg_spaft_local_port_set(payload, local_port); 1027 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1028 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1029 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1030 } 1031 1032 /* SFGC - Switch Flooding Group Configuration 1033 * ------------------------------------------ 1034 * The following register controls the association of flooding tables and MIDs 1035 * to packet types used for flooding. 1036 */ 1037 #define MLXSW_REG_SFGC_ID 0x2011 1038 #define MLXSW_REG_SFGC_LEN 0x14 1039 1040 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1041 1042 enum mlxsw_reg_sfgc_type { 1043 MLXSW_REG_SFGC_TYPE_BROADCAST, 1044 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1046 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1047 MLXSW_REG_SFGC_TYPE_RESERVED, 1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1049 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1050 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1051 MLXSW_REG_SFGC_TYPE_MAX, 1052 }; 1053 1054 /* reg_sfgc_type 1055 * The traffic type to reach the flooding table. 1056 * Access: Index 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1059 1060 /* bridge_type is used in SFGC and SFMR. */ 1061 enum mlxsw_reg_bridge_type { 1062 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1063 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1064 }; 1065 1066 /* reg_sfgc_bridge_type 1067 * Access: Index 1068 * 1069 * Note: SwitchX-2 only supports 802.1Q mode. 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1072 1073 enum mlxsw_flood_table_type { 1074 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1075 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1076 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1077 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1078 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1079 }; 1080 1081 /* reg_sfgc_table_type 1082 * See mlxsw_flood_table_type 1083 * Access: RW 1084 * 1085 * Note: FID offset and FID types are not supported in SwitchX-2. 1086 */ 1087 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1088 1089 /* reg_sfgc_flood_table 1090 * Flooding table index to associate with the specific type on the specific 1091 * switch partition. 1092 * Access: RW 1093 */ 1094 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1095 1096 /* reg_sfgc_counter_set_type 1097 * Counter Set Type for flow counters. 1098 * Access: RW 1099 */ 1100 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1101 1102 /* reg_sfgc_counter_index 1103 * Counter Index for flow counters. 1104 * Access: RW 1105 */ 1106 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1107 1108 /* reg_sfgc_mid_base 1109 * MID Base. 1110 * Access: RW 1111 * 1112 * Note: Reserved when legacy bridge model is used. 1113 */ 1114 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1115 1116 static inline void 1117 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1118 enum mlxsw_reg_bridge_type bridge_type, 1119 enum mlxsw_flood_table_type table_type, 1120 unsigned int flood_table, u16 mid_base) 1121 { 1122 MLXSW_REG_ZERO(sfgc, payload); 1123 mlxsw_reg_sfgc_type_set(payload, type); 1124 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1125 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1126 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1127 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1128 } 1129 1130 /* SFDF - Switch Filtering DB Flush 1131 * -------------------------------- 1132 * The switch filtering DB flush register is used to flush the FDB. 1133 * Note that FDB notifications are flushed as well. 1134 */ 1135 #define MLXSW_REG_SFDF_ID 0x2013 1136 #define MLXSW_REG_SFDF_LEN 0x14 1137 1138 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1139 1140 /* reg_sfdf_swid 1141 * Switch partition ID. 1142 * Access: Index 1143 */ 1144 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1145 1146 enum mlxsw_reg_sfdf_flush_type { 1147 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1148 MLXSW_REG_SFDF_FLUSH_PER_FID, 1149 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1150 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1151 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1152 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1153 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1154 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1155 }; 1156 1157 /* reg_sfdf_flush_type 1158 * Flush type. 1159 * 0 - All SWID dynamic entries are flushed. 1160 * 1 - All FID dynamic entries are flushed. 1161 * 2 - All dynamic entries pointing to port are flushed. 1162 * 3 - All FID dynamic entries pointing to port are flushed. 1163 * 4 - All dynamic entries pointing to LAG are flushed. 1164 * 5 - All FID dynamic entries pointing to LAG are flushed. 1165 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1166 * flushed. 1167 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1168 * flushed, per FID. 1169 * Access: RW 1170 */ 1171 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1172 1173 /* reg_sfdf_flush_static 1174 * Static. 1175 * 0 - Flush only dynamic entries. 1176 * 1 - Flush both dynamic and static entries. 1177 * Access: RW 1178 */ 1179 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1180 1181 static inline void mlxsw_reg_sfdf_pack(char *payload, 1182 enum mlxsw_reg_sfdf_flush_type type) 1183 { 1184 MLXSW_REG_ZERO(sfdf, payload); 1185 mlxsw_reg_sfdf_flush_type_set(payload, type); 1186 mlxsw_reg_sfdf_flush_static_set(payload, true); 1187 } 1188 1189 /* reg_sfdf_fid 1190 * FID to flush. 1191 * Access: RW 1192 */ 1193 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1194 1195 /* reg_sfdf_system_port 1196 * Port to flush. 1197 * Access: RW 1198 */ 1199 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1200 1201 /* reg_sfdf_port_fid_system_port 1202 * Port to flush, pointed to by FID. 1203 * Access: RW 1204 */ 1205 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1206 1207 /* reg_sfdf_lag_id 1208 * LAG ID to flush. 1209 * Access: RW 1210 */ 1211 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1212 1213 /* reg_sfdf_lag_fid_lag_id 1214 * LAG ID to flush, pointed to by FID. 1215 * Access: RW 1216 */ 1217 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1218 1219 /* SLDR - Switch LAG Descriptor Register 1220 * ----------------------------------------- 1221 * The switch LAG descriptor register is populated by LAG descriptors. 1222 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1223 * max_lag-1. 1224 */ 1225 #define MLXSW_REG_SLDR_ID 0x2014 1226 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1227 1228 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1229 1230 enum mlxsw_reg_sldr_op { 1231 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1232 MLXSW_REG_SLDR_OP_LAG_CREATE, 1233 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1234 /* Ports that appear in the list have the Distributor enabled */ 1235 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1236 /* Removes ports from the disributor list */ 1237 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1238 }; 1239 1240 /* reg_sldr_op 1241 * Operation. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1245 1246 /* reg_sldr_lag_id 1247 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1248 * Access: Index 1249 */ 1250 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1251 1252 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1253 { 1254 MLXSW_REG_ZERO(sldr, payload); 1255 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1256 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1257 } 1258 1259 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1260 { 1261 MLXSW_REG_ZERO(sldr, payload); 1262 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1263 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1264 } 1265 1266 /* reg_sldr_num_ports 1267 * The number of member ports of the LAG. 1268 * Reserved for Create / Destroy operations 1269 * For Add / Remove operations - indicates the number of ports in the list. 1270 * Access: RW 1271 */ 1272 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1273 1274 /* reg_sldr_system_port 1275 * System port. 1276 * Access: RW 1277 */ 1278 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1279 1280 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1281 u16 local_port) 1282 { 1283 MLXSW_REG_ZERO(sldr, payload); 1284 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1285 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1286 mlxsw_reg_sldr_num_ports_set(payload, 1); 1287 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1288 } 1289 1290 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1291 u16 local_port) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 mlxsw_reg_sldr_num_ports_set(payload, 1); 1297 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1298 } 1299 1300 /* SLCR - Switch LAG Configuration 2 Register 1301 * ------------------------------------------- 1302 * The Switch LAG Configuration register is used for configuring the 1303 * LAG properties of the switch. 1304 */ 1305 #define MLXSW_REG_SLCR_ID 0x2015 1306 #define MLXSW_REG_SLCR_LEN 0x10 1307 1308 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1309 1310 enum mlxsw_reg_slcr_pp { 1311 /* Global Configuration (for all ports) */ 1312 MLXSW_REG_SLCR_PP_GLOBAL, 1313 /* Per port configuration, based on local_port field */ 1314 MLXSW_REG_SLCR_PP_PER_PORT, 1315 }; 1316 1317 /* reg_slcr_pp 1318 * Per Port Configuration 1319 * Note: Reading at Global mode results in reading port 1 configuration. 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1323 1324 /* reg_slcr_local_port 1325 * Local port number 1326 * Supported from CPU port 1327 * Not supported from router port 1328 * Reserved when pp = Global Configuration 1329 * Access: Index 1330 */ 1331 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1332 1333 enum mlxsw_reg_slcr_type { 1334 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1335 MLXSW_REG_SLCR_TYPE_XOR, 1336 MLXSW_REG_SLCR_TYPE_RANDOM, 1337 }; 1338 1339 /* reg_slcr_type 1340 * Hash type 1341 * Access: RW 1342 */ 1343 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1344 1345 /* Ingress port */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1347 /* SMAC - for IPv4 and IPv6 packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1349 /* SMAC - for non-IP packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1351 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1352 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1353 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1354 /* DMAC - for IPv4 and IPv6 packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1356 /* DMAC - for non-IP packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1358 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1359 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1360 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1361 /* Ethertype - for IPv4 and IPv6 packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1363 /* Ethertype - for non-IP packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1365 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1366 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1367 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1368 /* VLAN ID - for IPv4 and IPv6 packets */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1370 /* VLAN ID - for non-IP packets */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1372 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1373 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1374 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1375 /* Source IP address (can be IPv4 or IPv6) */ 1376 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1377 /* Destination IP address (can be IPv4 or IPv6) */ 1378 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1379 /* TCP/UDP source port */ 1380 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1381 /* TCP/UDP destination port*/ 1382 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1383 /* IPv4 Protocol/IPv6 Next Header */ 1384 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1385 /* IPv6 Flow label */ 1386 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1387 /* SID - FCoE source ID */ 1388 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1389 /* DID - FCoE destination ID */ 1390 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1391 /* OXID - FCoE originator exchange ID */ 1392 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1393 /* Destination QP number - for RoCE packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1395 1396 /* reg_slcr_lag_hash 1397 * LAG hashing configuration. This is a bitmask, in which each set 1398 * bit includes the corresponding item in the LAG hash calculation. 1399 * The default lag_hash contains SMAC, DMAC, VLANID and 1400 * Ethertype (for all packet types). 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1404 1405 /* reg_slcr_seed 1406 * LAG seed value. The seed is the same for all ports. 1407 * Access: RW 1408 */ 1409 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1410 1411 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1412 { 1413 MLXSW_REG_ZERO(slcr, payload); 1414 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1415 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1416 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1417 mlxsw_reg_slcr_seed_set(payload, seed); 1418 } 1419 1420 /* SLCOR - Switch LAG Collector Register 1421 * ------------------------------------- 1422 * The Switch LAG Collector register controls the Local Port membership 1423 * in a LAG and enablement of the collector. 1424 */ 1425 #define MLXSW_REG_SLCOR_ID 0x2016 1426 #define MLXSW_REG_SLCOR_LEN 0x10 1427 1428 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1429 1430 enum mlxsw_reg_slcor_col { 1431 /* Port is added with collector disabled */ 1432 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1433 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1435 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1436 }; 1437 1438 /* reg_slcor_col 1439 * Collector configuration 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1443 1444 /* reg_slcor_local_port 1445 * Local port number 1446 * Not supported for CPU port 1447 * Access: Index 1448 */ 1449 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1450 1451 /* reg_slcor_lag_id 1452 * LAG Identifier. Index into the LAG descriptor table. 1453 * Access: Index 1454 */ 1455 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1456 1457 /* reg_slcor_port_index 1458 * Port index in the LAG list. Only valid on Add Port to LAG col. 1459 * Valid range is from 0 to cap_max_lag_members-1 1460 * Access: RW 1461 */ 1462 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1463 1464 static inline void mlxsw_reg_slcor_pack(char *payload, 1465 u16 local_port, u16 lag_id, 1466 enum mlxsw_reg_slcor_col col) 1467 { 1468 MLXSW_REG_ZERO(slcor, payload); 1469 mlxsw_reg_slcor_col_set(payload, col); 1470 mlxsw_reg_slcor_local_port_set(payload, local_port); 1471 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1475 u16 local_port, u16 lag_id, 1476 u8 port_index) 1477 { 1478 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1479 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1480 mlxsw_reg_slcor_port_index_set(payload, port_index); 1481 } 1482 1483 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1484 u16 local_port, u16 lag_id) 1485 { 1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1487 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1488 } 1489 1490 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1491 u16 local_port, u16 lag_id) 1492 { 1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1495 } 1496 1497 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1498 u16 local_port, u16 lag_id) 1499 { 1500 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1501 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1502 } 1503 1504 /* SPMLR - Switch Port MAC Learning Register 1505 * ----------------------------------------- 1506 * Controls the Switch MAC learning policy per port. 1507 */ 1508 #define MLXSW_REG_SPMLR_ID 0x2018 1509 #define MLXSW_REG_SPMLR_LEN 0x8 1510 1511 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1512 1513 /* reg_spmlr_local_port 1514 * Local port number. 1515 * Access: Index 1516 */ 1517 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1518 1519 /* reg_spmlr_sub_port 1520 * Virtual port within the physical port. 1521 * Should be set to 0 when virtual ports are not enabled on the port. 1522 * Access: Index 1523 */ 1524 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1525 1526 enum mlxsw_reg_spmlr_learn_mode { 1527 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1528 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1529 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1530 }; 1531 1532 /* reg_spmlr_learn_mode 1533 * Learning mode on the port. 1534 * 0 - Learning disabled. 1535 * 2 - Learning enabled. 1536 * 3 - Security mode. 1537 * 1538 * In security mode the switch does not learn MACs on the port, but uses the 1539 * SMAC to see if it exists on another ingress port. If so, the packet is 1540 * classified as a bad packet and is discarded unless the software registers 1541 * to receive port security error packets usign HPKT. 1542 */ 1543 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1544 1545 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1546 enum mlxsw_reg_spmlr_learn_mode mode) 1547 { 1548 MLXSW_REG_ZERO(spmlr, payload); 1549 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1550 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1551 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1552 } 1553 1554 /* SVFA - Switch VID to FID Allocation Register 1555 * -------------------------------------------- 1556 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1557 * virtualized ports. 1558 */ 1559 #define MLXSW_REG_SVFA_ID 0x201C 1560 #define MLXSW_REG_SVFA_LEN 0x18 1561 1562 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1563 1564 /* reg_svfa_swid 1565 * Switch partition ID. 1566 * Access: Index 1567 */ 1568 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1569 1570 /* reg_svfa_local_port 1571 * Local port number. 1572 * Access: Index 1573 * 1574 * Note: Reserved for 802.1Q FIDs. 1575 */ 1576 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1577 1578 enum mlxsw_reg_svfa_mt { 1579 MLXSW_REG_SVFA_MT_VID_TO_FID, 1580 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1581 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1582 }; 1583 1584 /* reg_svfa_mapping_table 1585 * Mapping table: 1586 * 0 - VID to FID 1587 * 1 - {Port, VID} to FID 1588 * Access: Index 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1593 1594 /* reg_svfa_v 1595 * Valid. 1596 * Valid if set. 1597 * Access: RW 1598 * 1599 * Note: Reserved for SwitchX-2. 1600 */ 1601 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1602 1603 /* reg_svfa_fid 1604 * Filtering ID. 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1608 1609 /* reg_svfa_vid 1610 * VLAN ID. 1611 * Access: Index 1612 */ 1613 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1614 1615 /* reg_svfa_counter_set_type 1616 * Counter set type for flow counters. 1617 * Access: RW 1618 * 1619 * Note: Reserved for SwitchX-2. 1620 */ 1621 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1622 1623 /* reg_svfa_counter_index 1624 * Counter index for flow counters. 1625 * Access: RW 1626 * 1627 * Note: Reserved for SwitchX-2. 1628 */ 1629 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1630 1631 /* reg_svfa_vni 1632 * Virtual Network Identifier. 1633 * Access: Index 1634 * 1635 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1636 */ 1637 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1638 1639 /* reg_svfa_irif_v 1640 * Ingress RIF valid. 1641 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1642 * 1 - Ingress RIF valid. 1643 * Must not be set for a non enabled RIF. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1649 1650 /* reg_svfa_irif 1651 * Ingress RIF (Router Interface). 1652 * Range is 0..cap_max_router_interfaces-1. 1653 * Access: RW 1654 * 1655 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1656 */ 1657 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1658 1659 static inline void __mlxsw_reg_svfa_pack(char *payload, 1660 enum mlxsw_reg_svfa_mt mt, bool valid, 1661 u16 fid, bool irif_v, u16 irif) 1662 { 1663 MLXSW_REG_ZERO(svfa, payload); 1664 mlxsw_reg_svfa_swid_set(payload, 0); 1665 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1666 mlxsw_reg_svfa_v_set(payload, valid); 1667 mlxsw_reg_svfa_fid_set(payload, fid); 1668 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1669 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1670 } 1671 1672 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1673 bool valid, u16 fid, u16 vid, 1674 bool irif_v, u16 irif) 1675 { 1676 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1677 1678 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1679 mlxsw_reg_svfa_local_port_set(payload, local_port); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1684 u16 vid, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vid_set(payload, vid); 1690 } 1691 1692 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1693 u32 vni, bool irif_v, u16 irif) 1694 { 1695 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1696 1697 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1698 mlxsw_reg_svfa_vni_set(payload, vni); 1699 } 1700 1701 /* SPVTR - Switch Port VLAN Stacking Register 1702 * ------------------------------------------ 1703 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1704 * to enable VLAN stacking. 1705 */ 1706 #define MLXSW_REG_SPVTR_ID 0x201D 1707 #define MLXSW_REG_SPVTR_LEN 0x10 1708 1709 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1710 1711 /* reg_spvtr_tport 1712 * Port is tunnel port. 1713 * Access: Index 1714 * 1715 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1716 */ 1717 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1718 1719 /* reg_spvtr_local_port 1720 * When tport = 0: local port number (Not supported from/to CPU). 1721 * When tport = 1: tunnel port. 1722 * Access: Index 1723 */ 1724 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1725 1726 /* reg_spvtr_ippe 1727 * Ingress Port Prio Mode Update Enable. 1728 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1733 1734 /* reg_spvtr_ipve 1735 * Ingress Port VID Mode Update Enable. 1736 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1737 * field. 1738 * Reserved on Get operations. 1739 * Access: OP 1740 */ 1741 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1742 1743 /* reg_spvtr_epve 1744 * Egress Port VID Mode Update Enable. 1745 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1746 * field. 1747 * Access: OP 1748 */ 1749 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1750 1751 /* reg_spvtr_ipprio_mode 1752 * Ingress Port Priority Mode. 1753 * This controls the PCP and DEI of the new outer VLAN 1754 * Note: for SwitchX/-2 the DEI is not affected. 1755 * 0: use port default PCP and DEI (configured by QPDPC). 1756 * 1: use C-VLAN PCP and DEI. 1757 * Has no effect when ipvid_mode = 0. 1758 * Reserved when tport = 1. 1759 * Access: RW 1760 */ 1761 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1762 1763 enum mlxsw_reg_spvtr_ipvid_mode { 1764 /* IEEE Compliant PVID (default) */ 1765 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1766 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1767 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1768 /* Always push VLAN (also for prio tagged packets) */ 1769 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1770 }; 1771 1772 /* reg_spvtr_ipvid_mode 1773 * Ingress Port VLAN-ID Mode. 1774 * For Spectrum family, this affects the values of SPVM.i 1775 * Access: RW 1776 */ 1777 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1778 1779 enum mlxsw_reg_spvtr_epvid_mode { 1780 /* IEEE Compliant VLAN membership */ 1781 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1782 /* Pop VLAN (for VLAN stacking) */ 1783 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1784 }; 1785 1786 /* reg_spvtr_epvid_mode 1787 * Egress Port VLAN-ID Mode. 1788 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1789 * Access: WO 1790 */ 1791 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1792 1793 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1794 u16 local_port, 1795 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1796 { 1797 MLXSW_REG_ZERO(spvtr, payload); 1798 mlxsw_reg_spvtr_tport_set(payload, tport); 1799 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1800 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1801 mlxsw_reg_spvtr_ipve_set(payload, true); 1802 } 1803 1804 /* SVPE - Switch Virtual-Port Enabling Register 1805 * -------------------------------------------- 1806 * Enables port virtualization. 1807 */ 1808 #define MLXSW_REG_SVPE_ID 0x201E 1809 #define MLXSW_REG_SVPE_LEN 0x4 1810 1811 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1812 1813 /* reg_svpe_local_port 1814 * Local port number 1815 * Access: Index 1816 * 1817 * Note: CPU port is not supported (uses VLAN mode only). 1818 */ 1819 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1820 1821 /* reg_svpe_vp_en 1822 * Virtual port enable. 1823 * 0 - Disable, VLAN mode (VID to FID). 1824 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1825 * Access: RW 1826 */ 1827 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1828 1829 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1830 bool enable) 1831 { 1832 MLXSW_REG_ZERO(svpe, payload); 1833 mlxsw_reg_svpe_local_port_set(payload, local_port); 1834 mlxsw_reg_svpe_vp_en_set(payload, enable); 1835 } 1836 1837 /* SFMR - Switch FID Management Register 1838 * ------------------------------------- 1839 * Creates and configures FIDs. 1840 */ 1841 #define MLXSW_REG_SFMR_ID 0x201F 1842 #define MLXSW_REG_SFMR_LEN 0x30 1843 1844 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1845 1846 enum mlxsw_reg_sfmr_op { 1847 MLXSW_REG_SFMR_OP_CREATE_FID, 1848 MLXSW_REG_SFMR_OP_DESTROY_FID, 1849 }; 1850 1851 /* reg_sfmr_op 1852 * Operation. 1853 * 0 - Create or edit FID. 1854 * 1 - Destroy FID. 1855 * Access: WO 1856 */ 1857 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1858 1859 /* reg_sfmr_fid 1860 * Filtering ID. 1861 * Access: Index 1862 */ 1863 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1864 1865 /* reg_sfmr_flood_rsp 1866 * Router sub-port flooding table. 1867 * 0 - Regular flooding table. 1868 * 1 - Router sub-port flooding table. For this FID the flooding is per 1869 * router-sub-port local_port. Must not be set for a FID which is not a 1870 * router-sub-port and must be set prior to enabling the relevant RIF. 1871 * Access: RW 1872 * 1873 * Note: Reserved when legacy bridge model is used. 1874 */ 1875 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1876 1877 /* reg_sfmr_flood_bridge_type 1878 * Flood bridge type (see SFGC.bridge_type). 1879 * 0 - type_0. 1880 * 1 - type_1. 1881 * Access: RW 1882 * 1883 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1884 */ 1885 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1886 1887 /* reg_sfmr_fid_offset 1888 * FID offset. 1889 * Used to point into the flooding table selected by SFGC register if 1890 * the table is of type FID-Offset. Otherwise, this field is reserved. 1891 * Access: RW 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1894 1895 /* reg_sfmr_vtfp 1896 * Valid Tunnel Flood Pointer. 1897 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1898 * Access: RW 1899 * 1900 * Note: Reserved for 802.1Q FIDs. 1901 */ 1902 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1903 1904 /* reg_sfmr_nve_tunnel_flood_ptr 1905 * Underlay Flooding and BC Pointer. 1906 * Used as a pointer to the first entry of the group based link lists of 1907 * flooding or BC entries (for NVE tunnels). 1908 * Access: RW 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1911 1912 /* reg_sfmr_vv 1913 * VNI Valid. 1914 * If not set, then vni is reserved. 1915 * Access: RW 1916 * 1917 * Note: Reserved for 802.1Q FIDs. 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1920 1921 /* reg_sfmr_vni 1922 * Virtual Network Identifier. 1923 * When legacy bridge model is used, a given VNI can only be assigned to one 1924 * FID. When unified bridge model is used, it configures only the FID->VNI, 1925 * the VNI->FID is done by SVFA. 1926 * Access: RW 1927 */ 1928 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1929 1930 /* reg_sfmr_irif_v 1931 * Ingress RIF valid. 1932 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1933 * 1 - Ingress RIF valid. 1934 * Must not be set for a non valid RIF. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1940 1941 /* reg_sfmr_irif 1942 * Ingress RIF (Router Interface). 1943 * Range is 0..cap_max_router_interfaces-1. 1944 * Access: RW 1945 * 1946 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1949 1950 /* reg_sfmr_smpe_valid 1951 * SMPE is valid. 1952 * Access: RW 1953 * 1954 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1955 * Spectrum-1. 1956 */ 1957 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1958 1959 /* reg_sfmr_smpe 1960 * Switch multicast port to egress VID. 1961 * Range is 0..cap_max_rmpe-1 1962 * Access: RW 1963 * 1964 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1965 * Spectrum-1. 1966 */ 1967 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1968 1969 static inline void mlxsw_reg_sfmr_pack(char *payload, 1970 enum mlxsw_reg_sfmr_op op, u16 fid, 1971 u16 fid_offset, bool flood_rsp, 1972 enum mlxsw_reg_bridge_type bridge_type, 1973 bool smpe_valid, u16 smpe) 1974 { 1975 MLXSW_REG_ZERO(sfmr, payload); 1976 mlxsw_reg_sfmr_op_set(payload, op); 1977 mlxsw_reg_sfmr_fid_set(payload, fid); 1978 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1979 mlxsw_reg_sfmr_vtfp_set(payload, false); 1980 mlxsw_reg_sfmr_vv_set(payload, false); 1981 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1982 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1983 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1984 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1985 } 1986 1987 /* SPVMLR - Switch Port VLAN MAC Learning Register 1988 * ----------------------------------------------- 1989 * Controls the switch MAC learning policy per {Port, VID}. 1990 */ 1991 #define MLXSW_REG_SPVMLR_ID 0x2020 1992 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1993 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1994 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1995 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1996 MLXSW_REG_SPVMLR_REC_LEN * \ 1997 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1998 1999 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 2000 2001 /* reg_spvmlr_local_port 2002 * Local ingress port. 2003 * Access: Index 2004 * 2005 * Note: CPU port is not supported. 2006 */ 2007 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 2008 2009 /* reg_spvmlr_num_rec 2010 * Number of records to update. 2011 * Access: OP 2012 */ 2013 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2014 2015 /* reg_spvmlr_rec_learn_enable 2016 * 0 - Disable learning for {Port, VID}. 2017 * 1 - Enable learning for {Port, VID}. 2018 * Access: RW 2019 */ 2020 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2021 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2022 2023 /* reg_spvmlr_rec_vid 2024 * VLAN ID to be added/removed from port or for querying. 2025 * Access: Index 2026 */ 2027 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2028 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2029 2030 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2031 u16 vid_begin, u16 vid_end, 2032 bool learn_enable) 2033 { 2034 int num_rec = vid_end - vid_begin + 1; 2035 int i; 2036 2037 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2038 2039 MLXSW_REG_ZERO(spvmlr, payload); 2040 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2041 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2042 2043 for (i = 0; i < num_rec; i++) { 2044 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2045 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2046 } 2047 } 2048 2049 /* SPFSR - Switch Port FDB Security Register 2050 * ----------------------------------------- 2051 * Configures the security mode per port. 2052 */ 2053 #define MLXSW_REG_SPFSR_ID 0x2023 2054 #define MLXSW_REG_SPFSR_LEN 0x08 2055 2056 MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN); 2057 2058 /* reg_spfsr_local_port 2059 * Local port. 2060 * Access: Index 2061 * 2062 * Note: not supported for CPU port. 2063 */ 2064 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12); 2065 2066 /* reg_spfsr_security 2067 * Security checks. 2068 * 0: disabled (default) 2069 * 1: enabled 2070 * Access: RW 2071 */ 2072 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1); 2073 2074 static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port, 2075 bool security) 2076 { 2077 MLXSW_REG_ZERO(spfsr, payload); 2078 mlxsw_reg_spfsr_local_port_set(payload, local_port); 2079 mlxsw_reg_spfsr_security_set(payload, security); 2080 } 2081 2082 /* SPVC - Switch Port VLAN Classification Register 2083 * ----------------------------------------------- 2084 * Configures the port to identify packets as untagged / single tagged / 2085 * double packets based on the packet EtherTypes. 2086 * Ethertype IDs are configured by SVER. 2087 */ 2088 #define MLXSW_REG_SPVC_ID 0x2026 2089 #define MLXSW_REG_SPVC_LEN 0x0C 2090 2091 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2092 2093 /* reg_spvc_local_port 2094 * Local port. 2095 * Access: Index 2096 * 2097 * Note: applies both to Rx port and Tx port, so if a packet traverses 2098 * through Rx port i and a Tx port j then port i and port j must have the 2099 * same configuration. 2100 */ 2101 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2102 2103 /* reg_spvc_inner_et2 2104 * Vlan Tag1 EtherType2 enable. 2105 * Packet is initially classified as double VLAN Tag if in addition to 2106 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2107 * equal to ether_type2. 2108 * 0: disable (default) 2109 * 1: enable 2110 * Access: RW 2111 */ 2112 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2113 2114 /* reg_spvc_et2 2115 * Vlan Tag0 EtherType2 enable. 2116 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2117 * equal to ether_type2. 2118 * 0: disable (default) 2119 * 1: enable 2120 * Access: RW 2121 */ 2122 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2123 2124 /* reg_spvc_inner_et1 2125 * Vlan Tag1 EtherType1 enable. 2126 * Packet is initially classified as double VLAN Tag if in addition to 2127 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2128 * equal to ether_type1. 2129 * 0: disable 2130 * 1: enable (default) 2131 * Access: RW 2132 */ 2133 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2134 2135 /* reg_spvc_et1 2136 * Vlan Tag0 EtherType1 enable. 2137 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2138 * equal to ether_type1. 2139 * 0: disable 2140 * 1: enable (default) 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2144 2145 /* reg_inner_et0 2146 * Vlan Tag1 EtherType0 enable. 2147 * Packet is initially classified as double VLAN Tag if in addition to 2148 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2149 * equal to ether_type0. 2150 * 0: disable 2151 * 1: enable (default) 2152 * Access: RW 2153 */ 2154 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2155 2156 /* reg_et0 2157 * Vlan Tag0 EtherType0 enable. 2158 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2159 * equal to ether_type0. 2160 * 0: disable 2161 * 1: enable (default) 2162 * Access: RW 2163 */ 2164 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2165 2166 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2167 bool et0) 2168 { 2169 MLXSW_REG_ZERO(spvc, payload); 2170 mlxsw_reg_spvc_local_port_set(payload, local_port); 2171 /* Enable inner_et1 and inner_et0 to enable identification of double 2172 * tagged packets. 2173 */ 2174 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2175 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2176 mlxsw_reg_spvc_et1_set(payload, et1); 2177 mlxsw_reg_spvc_et0_set(payload, et0); 2178 } 2179 2180 /* SPEVET - Switch Port Egress VLAN EtherType 2181 * ------------------------------------------ 2182 * The switch port egress VLAN EtherType configures which EtherType to push at 2183 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2184 * is set. 2185 */ 2186 #define MLXSW_REG_SPEVET_ID 0x202A 2187 #define MLXSW_REG_SPEVET_LEN 0x08 2188 2189 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2190 2191 /* reg_spevet_local_port 2192 * Egress Local port number. 2193 * Not supported to CPU port. 2194 * Access: Index 2195 */ 2196 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2197 2198 /* reg_spevet_et_vlan 2199 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2200 * 0: ether_type0 - (default) 2201 * 1: ether_type1 2202 * 2: ether_type2 2203 * Access: RW 2204 */ 2205 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2206 2207 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2208 u8 et_vlan) 2209 { 2210 MLXSW_REG_ZERO(spevet, payload); 2211 mlxsw_reg_spevet_local_port_set(payload, local_port); 2212 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2213 } 2214 2215 /* SMPE - Switch Multicast Port to Egress VID 2216 * ------------------------------------------ 2217 * The switch multicast port to egress VID maps 2218 * {egress_port, SMPE index} -> {VID}. 2219 */ 2220 #define MLXSW_REG_SMPE_ID 0x202B 2221 #define MLXSW_REG_SMPE_LEN 0x0C 2222 2223 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2224 2225 /* reg_smpe_local_port 2226 * Local port number. 2227 * CPU port is not supported. 2228 * Access: Index 2229 */ 2230 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2231 2232 /* reg_smpe_smpe_index 2233 * Switch multicast port to egress VID. 2234 * Range is 0..cap_max_rmpe-1. 2235 * Access: Index 2236 */ 2237 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2238 2239 /* reg_smpe_evid 2240 * Egress VID. 2241 * Access: RW 2242 */ 2243 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2244 2245 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2246 u16 smpe_index, u16 evid) 2247 { 2248 MLXSW_REG_ZERO(smpe, payload); 2249 mlxsw_reg_smpe_local_port_set(payload, local_port); 2250 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2251 mlxsw_reg_smpe_evid_set(payload, evid); 2252 } 2253 2254 /* SMID-V2 - Switch Multicast ID Version 2 Register 2255 * ------------------------------------------------ 2256 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2257 * of the multicast group within the stacking domain, into a list of local 2258 * ports into which the packet is replicated. 2259 */ 2260 #define MLXSW_REG_SMID2_ID 0x2034 2261 #define MLXSW_REG_SMID2_LEN 0x120 2262 2263 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2264 2265 /* reg_smid2_swid 2266 * Switch partition ID. 2267 * Access: Index 2268 */ 2269 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2270 2271 /* reg_smid2_mid 2272 * Multicast identifier - global identifier that represents the multicast group 2273 * across all devices. 2274 * Access: Index 2275 */ 2276 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2277 2278 /* reg_smid2_smpe_valid 2279 * SMPE is valid. 2280 * When not valid, the egress VID will not be modified by the SMPE table. 2281 * Access: RW 2282 * 2283 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2284 */ 2285 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2286 2287 /* reg_smid2_smpe 2288 * Switch multicast port to egress VID. 2289 * Access: RW 2290 * 2291 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2292 */ 2293 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2294 2295 /* reg_smid2_port 2296 * Local port memebership (1 bit per port). 2297 * Access: RW 2298 */ 2299 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2300 2301 /* reg_smid2_port_mask 2302 * Local port mask (1 bit per port). 2303 * Access: WO 2304 */ 2305 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2306 2307 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2308 bool set, bool smpe_valid, u16 smpe) 2309 { 2310 MLXSW_REG_ZERO(smid2, payload); 2311 mlxsw_reg_smid2_swid_set(payload, 0); 2312 mlxsw_reg_smid2_mid_set(payload, mid); 2313 mlxsw_reg_smid2_port_set(payload, port, set); 2314 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2315 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2316 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2317 } 2318 2319 /* CWTP - Congetion WRED ECN TClass Profile 2320 * ---------------------------------------- 2321 * Configures the profiles for queues of egress port and traffic class 2322 */ 2323 #define MLXSW_REG_CWTP_ID 0x2802 2324 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2325 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2326 #define MLXSW_REG_CWTP_LEN 0x40 2327 2328 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2329 2330 /* reg_cwtp_local_port 2331 * Local port number 2332 * Not supported for CPU port 2333 * Access: Index 2334 */ 2335 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2336 2337 /* reg_cwtp_traffic_class 2338 * Traffic Class to configure 2339 * Access: Index 2340 */ 2341 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2342 2343 /* reg_cwtp_profile_min 2344 * Minimum Average Queue Size of the profile in cells. 2345 * Access: RW 2346 */ 2347 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2348 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2349 2350 /* reg_cwtp_profile_percent 2351 * Percentage of WRED and ECN marking for maximum Average Queue size 2352 * Range is 0 to 100, units of integer percentage 2353 * Access: RW 2354 */ 2355 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2356 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2357 2358 /* reg_cwtp_profile_max 2359 * Maximum Average Queue size of the profile in cells 2360 * Access: RW 2361 */ 2362 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2363 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2364 2365 #define MLXSW_REG_CWTP_MIN_VALUE 64 2366 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2367 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2368 2369 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2370 u8 traffic_class) 2371 { 2372 int i; 2373 2374 MLXSW_REG_ZERO(cwtp, payload); 2375 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2376 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2377 2378 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2379 mlxsw_reg_cwtp_profile_min_set(payload, i, 2380 MLXSW_REG_CWTP_MIN_VALUE); 2381 mlxsw_reg_cwtp_profile_max_set(payload, i, 2382 MLXSW_REG_CWTP_MIN_VALUE); 2383 } 2384 } 2385 2386 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2387 2388 static inline void 2389 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2390 u32 probability) 2391 { 2392 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2393 2394 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2395 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2396 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2397 } 2398 2399 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2400 * --------------------------------------------------- 2401 * The CWTPM register maps each egress port and traffic class to profile num. 2402 */ 2403 #define MLXSW_REG_CWTPM_ID 0x2803 2404 #define MLXSW_REG_CWTPM_LEN 0x44 2405 2406 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2407 2408 /* reg_cwtpm_local_port 2409 * Local port number 2410 * Not supported for CPU port 2411 * Access: Index 2412 */ 2413 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2414 2415 /* reg_cwtpm_traffic_class 2416 * Traffic Class to configure 2417 * Access: Index 2418 */ 2419 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2420 2421 /* reg_cwtpm_ew 2422 * Control enablement of WRED for traffic class: 2423 * 0 - Disable 2424 * 1 - Enable 2425 * Access: RW 2426 */ 2427 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2428 2429 /* reg_cwtpm_ee 2430 * Control enablement of ECN for traffic class: 2431 * 0 - Disable 2432 * 1 - Enable 2433 * Access: RW 2434 */ 2435 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2436 2437 /* reg_cwtpm_tcp_g 2438 * TCP Green Profile. 2439 * Index of the profile within {port, traffic class} to use. 2440 * 0 for disabling both WRED and ECN for this type of traffic. 2441 * Access: RW 2442 */ 2443 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2444 2445 /* reg_cwtpm_tcp_y 2446 * TCP Yellow Profile. 2447 * Index of the profile within {port, traffic class} to use. 2448 * 0 for disabling both WRED and ECN for this type of traffic. 2449 * Access: RW 2450 */ 2451 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2452 2453 /* reg_cwtpm_tcp_r 2454 * TCP Red Profile. 2455 * Index of the profile within {port, traffic class} to use. 2456 * 0 for disabling both WRED and ECN for this type of traffic. 2457 * Access: RW 2458 */ 2459 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2460 2461 /* reg_cwtpm_ntcp_g 2462 * Non-TCP Green Profile. 2463 * Index of the profile within {port, traffic class} to use. 2464 * 0 for disabling both WRED and ECN for this type of traffic. 2465 * Access: RW 2466 */ 2467 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2468 2469 /* reg_cwtpm_ntcp_y 2470 * Non-TCP Yellow Profile. 2471 * Index of the profile within {port, traffic class} to use. 2472 * 0 for disabling both WRED and ECN for this type of traffic. 2473 * Access: RW 2474 */ 2475 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2476 2477 /* reg_cwtpm_ntcp_r 2478 * Non-TCP Red Profile. 2479 * Index of the profile within {port, traffic class} to use. 2480 * 0 for disabling both WRED and ECN for this type of traffic. 2481 * Access: RW 2482 */ 2483 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2484 2485 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2486 2487 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2488 u8 traffic_class, u8 profile, 2489 bool wred, bool ecn) 2490 { 2491 MLXSW_REG_ZERO(cwtpm, payload); 2492 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2493 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2494 mlxsw_reg_cwtpm_ew_set(payload, wred); 2495 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2496 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2497 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2498 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2499 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2500 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2501 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2502 } 2503 2504 /* PGCR - Policy-Engine General Configuration Register 2505 * --------------------------------------------------- 2506 * This register configures general Policy-Engine settings. 2507 */ 2508 #define MLXSW_REG_PGCR_ID 0x3001 2509 #define MLXSW_REG_PGCR_LEN 0x20 2510 2511 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2512 2513 /* reg_pgcr_default_action_pointer_base 2514 * Default action pointer base. Each region has a default action pointer 2515 * which is equal to default_action_pointer_base + region_id. 2516 * Access: RW 2517 */ 2518 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2519 2520 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2521 { 2522 MLXSW_REG_ZERO(pgcr, payload); 2523 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2524 } 2525 2526 /* PPBT - Policy-Engine Port Binding Table 2527 * --------------------------------------- 2528 * This register is used for configuration of the Port Binding Table. 2529 */ 2530 #define MLXSW_REG_PPBT_ID 0x3002 2531 #define MLXSW_REG_PPBT_LEN 0x14 2532 2533 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2534 2535 enum mlxsw_reg_pxbt_e { 2536 MLXSW_REG_PXBT_E_IACL, 2537 MLXSW_REG_PXBT_E_EACL, 2538 }; 2539 2540 /* reg_ppbt_e 2541 * Access: Index 2542 */ 2543 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2544 2545 enum mlxsw_reg_pxbt_op { 2546 MLXSW_REG_PXBT_OP_BIND, 2547 MLXSW_REG_PXBT_OP_UNBIND, 2548 }; 2549 2550 /* reg_ppbt_op 2551 * Access: RW 2552 */ 2553 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2554 2555 /* reg_ppbt_local_port 2556 * Local port. Not including CPU port. 2557 * Access: Index 2558 */ 2559 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2560 2561 /* reg_ppbt_g 2562 * group - When set, the binding is of an ACL group. When cleared, 2563 * the binding is of an ACL. 2564 * Must be set to 1 for Spectrum. 2565 * Access: RW 2566 */ 2567 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2568 2569 /* reg_ppbt_acl_info 2570 * ACL/ACL group identifier. If the g bit is set, this field should hold 2571 * the acl_group_id, else it should hold the acl_id. 2572 * Access: RW 2573 */ 2574 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2575 2576 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2577 enum mlxsw_reg_pxbt_op op, 2578 u16 local_port, u16 acl_info) 2579 { 2580 MLXSW_REG_ZERO(ppbt, payload); 2581 mlxsw_reg_ppbt_e_set(payload, e); 2582 mlxsw_reg_ppbt_op_set(payload, op); 2583 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2584 mlxsw_reg_ppbt_g_set(payload, true); 2585 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2586 } 2587 2588 /* PACL - Policy-Engine ACL Register 2589 * --------------------------------- 2590 * This register is used for configuration of the ACL. 2591 */ 2592 #define MLXSW_REG_PACL_ID 0x3004 2593 #define MLXSW_REG_PACL_LEN 0x70 2594 2595 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2596 2597 /* reg_pacl_v 2598 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2599 * while the ACL is bounded to either a port, VLAN or ACL rule. 2600 * Access: RW 2601 */ 2602 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2603 2604 /* reg_pacl_acl_id 2605 * An identifier representing the ACL (managed by software) 2606 * Range 0 .. cap_max_acl_regions - 1 2607 * Access: Index 2608 */ 2609 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2610 2611 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2612 2613 /* reg_pacl_tcam_region_info 2614 * Opaque object that represents a TCAM region. 2615 * Obtained through PTAR register. 2616 * Access: RW 2617 */ 2618 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2619 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2620 2621 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2622 bool valid, const char *tcam_region_info) 2623 { 2624 MLXSW_REG_ZERO(pacl, payload); 2625 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2626 mlxsw_reg_pacl_v_set(payload, valid); 2627 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2628 } 2629 2630 /* PAGT - Policy-Engine ACL Group Table 2631 * ------------------------------------ 2632 * This register is used for configuration of the ACL Group Table. 2633 */ 2634 #define MLXSW_REG_PAGT_ID 0x3005 2635 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2636 #define MLXSW_REG_PAGT_ACL_LEN 4 2637 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2638 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2639 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2640 2641 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2642 2643 /* reg_pagt_size 2644 * Number of ACLs in the group. 2645 * Size 0 invalidates a group. 2646 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2647 * Total number of ACLs in all groups must be lower or equal 2648 * to cap_max_acl_tot_groups 2649 * Note: a group which is binded must not be invalidated 2650 * Access: Index 2651 */ 2652 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2653 2654 /* reg_pagt_acl_group_id 2655 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2656 * the ACL Group identifier (managed by software). 2657 * Access: Index 2658 */ 2659 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2660 2661 /* reg_pagt_multi 2662 * Multi-ACL 2663 * 0 - This ACL is the last ACL in the multi-ACL 2664 * 1 - This ACL is part of a multi-ACL 2665 * Access: RW 2666 */ 2667 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2668 2669 /* reg_pagt_acl_id 2670 * ACL identifier 2671 * Access: RW 2672 */ 2673 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2674 2675 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2676 { 2677 MLXSW_REG_ZERO(pagt, payload); 2678 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2679 } 2680 2681 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2682 u16 acl_id, bool multi) 2683 { 2684 u8 size = mlxsw_reg_pagt_size_get(payload); 2685 2686 if (index >= size) 2687 mlxsw_reg_pagt_size_set(payload, index + 1); 2688 mlxsw_reg_pagt_multi_set(payload, index, multi); 2689 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2690 } 2691 2692 /* PTAR - Policy-Engine TCAM Allocation Register 2693 * --------------------------------------------- 2694 * This register is used for allocation of regions in the TCAM. 2695 * Note: Query method is not supported on this register. 2696 */ 2697 #define MLXSW_REG_PTAR_ID 0x3006 2698 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2699 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2700 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2701 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2702 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2703 2704 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2705 2706 enum mlxsw_reg_ptar_op { 2707 /* allocate a TCAM region */ 2708 MLXSW_REG_PTAR_OP_ALLOC, 2709 /* resize a TCAM region */ 2710 MLXSW_REG_PTAR_OP_RESIZE, 2711 /* deallocate TCAM region */ 2712 MLXSW_REG_PTAR_OP_FREE, 2713 /* test allocation */ 2714 MLXSW_REG_PTAR_OP_TEST, 2715 }; 2716 2717 /* reg_ptar_op 2718 * Access: OP 2719 */ 2720 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2721 2722 /* reg_ptar_action_set_type 2723 * Type of action set to be used on this region. 2724 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2725 * Access: WO 2726 */ 2727 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2728 2729 enum mlxsw_reg_ptar_key_type { 2730 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2731 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2732 }; 2733 2734 /* reg_ptar_key_type 2735 * TCAM key type for the region. 2736 * Access: WO 2737 */ 2738 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2739 2740 /* reg_ptar_region_size 2741 * TCAM region size. When allocating/resizing this is the requested size, 2742 * the response is the actual size. Note that actual size may be 2743 * larger than requested. 2744 * Allowed range 1 .. cap_max_rules-1 2745 * Reserved during op deallocate. 2746 * Access: WO 2747 */ 2748 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2749 2750 /* reg_ptar_region_id 2751 * Region identifier 2752 * Range 0 .. cap_max_regions-1 2753 * Access: Index 2754 */ 2755 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2756 2757 /* reg_ptar_tcam_region_info 2758 * Opaque object that represents the TCAM region. 2759 * Returned when allocating a region. 2760 * Provided by software for ACL generation and region deallocation and resize. 2761 * Access: RW 2762 */ 2763 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2764 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2765 2766 /* reg_ptar_flexible_key_id 2767 * Identifier of the Flexible Key. 2768 * Only valid if key_type == "FLEX_KEY" 2769 * The key size will be rounded up to one of the following values: 2770 * 9B, 18B, 36B, 54B. 2771 * This field is reserved for in resize operation. 2772 * Access: WO 2773 */ 2774 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2775 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2776 2777 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2778 enum mlxsw_reg_ptar_key_type key_type, 2779 u16 region_size, u16 region_id, 2780 const char *tcam_region_info) 2781 { 2782 MLXSW_REG_ZERO(ptar, payload); 2783 mlxsw_reg_ptar_op_set(payload, op); 2784 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2785 mlxsw_reg_ptar_key_type_set(payload, key_type); 2786 mlxsw_reg_ptar_region_size_set(payload, region_size); 2787 mlxsw_reg_ptar_region_id_set(payload, region_id); 2788 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2789 } 2790 2791 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2792 u16 key_id) 2793 { 2794 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2795 } 2796 2797 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2798 { 2799 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2800 } 2801 2802 /* PPRR - Policy-Engine Port Range Register 2803 * ---------------------------------------- 2804 * This register is used for configuring port range identification. 2805 */ 2806 #define MLXSW_REG_PPRR_ID 0x3008 2807 #define MLXSW_REG_PPRR_LEN 0x14 2808 2809 MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN); 2810 2811 /* reg_pprr_ipv4 2812 * Apply port range register to IPv4 packets. 2813 * Access: RW 2814 */ 2815 MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1); 2816 2817 /* reg_pprr_ipv6 2818 * Apply port range register to IPv6 packets. 2819 * Access: RW 2820 */ 2821 MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1); 2822 2823 /* reg_pprr_src 2824 * Apply port range register to source L4 ports. 2825 * Access: RW 2826 */ 2827 MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1); 2828 2829 /* reg_pprr_dst 2830 * Apply port range register to destination L4 ports. 2831 * Access: RW 2832 */ 2833 MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1); 2834 2835 /* reg_pprr_tcp 2836 * Apply port range register to TCP packets. 2837 * Access: RW 2838 */ 2839 MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1); 2840 2841 /* reg_pprr_udp 2842 * Apply port range register to UDP packets. 2843 * Access: RW 2844 */ 2845 MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1); 2846 2847 /* reg_pprr_register_index 2848 * Index of Port Range Register being accessed. 2849 * Range is 0..cap_max_acl_l4_port_range-1. 2850 * Access: Index 2851 */ 2852 MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8); 2853 2854 /* reg_prrr_port_range_min 2855 * Minimum port range for comparison. 2856 * Match is defined as: 2857 * port_range_min <= packet_port <= port_range_max. 2858 * Access: RW 2859 */ 2860 MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16); 2861 2862 /* reg_prrr_port_range_max 2863 * Maximum port range for comparison. 2864 * Access: RW 2865 */ 2866 MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16); 2867 2868 static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index) 2869 { 2870 MLXSW_REG_ZERO(pprr, payload); 2871 mlxsw_reg_pprr_register_index_set(payload, register_index); 2872 } 2873 2874 /* PPBS - Policy-Engine Policy Based Switching Register 2875 * ---------------------------------------------------- 2876 * This register retrieves and sets Policy Based Switching Table entries. 2877 */ 2878 #define MLXSW_REG_PPBS_ID 0x300C 2879 #define MLXSW_REG_PPBS_LEN 0x14 2880 2881 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2882 2883 /* reg_ppbs_pbs_ptr 2884 * Index into the PBS table. 2885 * For Spectrum, the index points to the KVD Linear. 2886 * Access: Index 2887 */ 2888 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2889 2890 /* reg_ppbs_system_port 2891 * Unique port identifier for the final destination of the packet. 2892 * Access: RW 2893 */ 2894 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2895 2896 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2897 u16 system_port) 2898 { 2899 MLXSW_REG_ZERO(ppbs, payload); 2900 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2901 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2902 } 2903 2904 /* PRCR - Policy-Engine Rules Copy Register 2905 * ---------------------------------------- 2906 * This register is used for accessing rules within a TCAM region. 2907 */ 2908 #define MLXSW_REG_PRCR_ID 0x300D 2909 #define MLXSW_REG_PRCR_LEN 0x40 2910 2911 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2912 2913 enum mlxsw_reg_prcr_op { 2914 /* Move rules. Moves the rules from "tcam_region_info" starting 2915 * at offset "offset" to "dest_tcam_region_info" 2916 * at offset "dest_offset." 2917 */ 2918 MLXSW_REG_PRCR_OP_MOVE, 2919 /* Copy rules. Copies the rules from "tcam_region_info" starting 2920 * at offset "offset" to "dest_tcam_region_info" 2921 * at offset "dest_offset." 2922 */ 2923 MLXSW_REG_PRCR_OP_COPY, 2924 }; 2925 2926 /* reg_prcr_op 2927 * Access: OP 2928 */ 2929 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2930 2931 /* reg_prcr_offset 2932 * Offset within the source region to copy/move from. 2933 * Access: Index 2934 */ 2935 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2936 2937 /* reg_prcr_size 2938 * The number of rules to copy/move. 2939 * Access: WO 2940 */ 2941 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2942 2943 /* reg_prcr_tcam_region_info 2944 * Opaque object that represents the source TCAM region. 2945 * Access: Index 2946 */ 2947 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2948 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2949 2950 /* reg_prcr_dest_offset 2951 * Offset within the source region to copy/move to. 2952 * Access: Index 2953 */ 2954 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2955 2956 /* reg_prcr_dest_tcam_region_info 2957 * Opaque object that represents the destination TCAM region. 2958 * Access: Index 2959 */ 2960 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2961 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2962 2963 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2964 const char *src_tcam_region_info, 2965 u16 src_offset, 2966 const char *dest_tcam_region_info, 2967 u16 dest_offset, u16 size) 2968 { 2969 MLXSW_REG_ZERO(prcr, payload); 2970 mlxsw_reg_prcr_op_set(payload, op); 2971 mlxsw_reg_prcr_offset_set(payload, src_offset); 2972 mlxsw_reg_prcr_size_set(payload, size); 2973 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2974 src_tcam_region_info); 2975 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2976 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2977 dest_tcam_region_info); 2978 } 2979 2980 /* PEFA - Policy-Engine Extended Flexible Action Register 2981 * ------------------------------------------------------ 2982 * This register is used for accessing an extended flexible action entry 2983 * in the central KVD Linear Database. 2984 */ 2985 #define MLXSW_REG_PEFA_ID 0x300F 2986 #define MLXSW_REG_PEFA_LEN 0xB0 2987 2988 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2989 2990 /* reg_pefa_index 2991 * Index in the KVD Linear Centralized Database. 2992 * Access: Index 2993 */ 2994 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2995 2996 /* reg_pefa_a 2997 * Index in the KVD Linear Centralized Database. 2998 * Activity 2999 * For a new entry: set if ca=0, clear if ca=1 3000 * Set if a packet lookup has hit on the specific entry 3001 * Access: RO 3002 */ 3003 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 3004 3005 /* reg_pefa_ca 3006 * Clear activity 3007 * When write: activity is according to this field 3008 * When read: after reading the activity is cleared according to ca 3009 * Access: OP 3010 */ 3011 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 3012 3013 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 3014 3015 /* reg_pefa_flex_action_set 3016 * Action-set to perform when rule is matched. 3017 * Must be zero padded if action set is shorter. 3018 * Access: RW 3019 */ 3020 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 3021 3022 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 3023 const char *flex_action_set) 3024 { 3025 MLXSW_REG_ZERO(pefa, payload); 3026 mlxsw_reg_pefa_index_set(payload, index); 3027 mlxsw_reg_pefa_ca_set(payload, ca); 3028 if (flex_action_set) 3029 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 3030 flex_action_set); 3031 } 3032 3033 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 3034 { 3035 *p_a = mlxsw_reg_pefa_a_get(payload); 3036 } 3037 3038 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 3039 * -------------------------------------------------------------- 3040 * This register is used for binding Multicast router to an ACL group 3041 * that serves the MC router. 3042 * This register is not supported by SwitchX/-2 and Spectrum. 3043 */ 3044 #define MLXSW_REG_PEMRBT_ID 0x3014 3045 #define MLXSW_REG_PEMRBT_LEN 0x14 3046 3047 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 3048 3049 enum mlxsw_reg_pemrbt_protocol { 3050 MLXSW_REG_PEMRBT_PROTO_IPV4, 3051 MLXSW_REG_PEMRBT_PROTO_IPV6, 3052 }; 3053 3054 /* reg_pemrbt_protocol 3055 * Access: Index 3056 */ 3057 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 3058 3059 /* reg_pemrbt_group_id 3060 * ACL group identifier. 3061 * Range 0..cap_max_acl_groups-1 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 3065 3066 static inline void 3067 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 3068 u16 group_id) 3069 { 3070 MLXSW_REG_ZERO(pemrbt, payload); 3071 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3072 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3073 } 3074 3075 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3076 * ----------------------------------------------------- 3077 * This register is used for accessing rules within a TCAM region. 3078 * It is a new version of PTCE in order to support wider key, 3079 * mask and action within a TCAM region. This register is not supported 3080 * by SwitchX and SwitchX-2. 3081 */ 3082 #define MLXSW_REG_PTCE2_ID 0x3017 3083 #define MLXSW_REG_PTCE2_LEN 0x1D8 3084 3085 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3086 3087 /* reg_ptce2_v 3088 * Valid. 3089 * Access: RW 3090 */ 3091 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3092 3093 /* reg_ptce2_a 3094 * Activity. Set if a packet lookup has hit on the specific entry. 3095 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3096 * Access: RO 3097 */ 3098 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3099 3100 enum mlxsw_reg_ptce2_op { 3101 /* Read operation. */ 3102 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3103 /* clear on read operation. Used to read entry 3104 * and clear Activity bit. 3105 */ 3106 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3107 /* Write operation. Used to write a new entry to the table. 3108 * All R/W fields are relevant for new entry. Activity bit is set 3109 * for new entries - Note write with v = 0 will delete the entry. 3110 */ 3111 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3112 /* Update action. Only action set will be updated. */ 3113 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3114 /* Clear activity. A bit is cleared for the entry. */ 3115 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3116 }; 3117 3118 /* reg_ptce2_op 3119 * Access: OP 3120 */ 3121 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3122 3123 /* reg_ptce2_offset 3124 * Access: Index 3125 */ 3126 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3127 3128 /* reg_ptce2_priority 3129 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3130 * Note: priority does not have to be unique per rule. 3131 * Within a region, higher priority should have lower offset (no limitation 3132 * between regions in a multi-region). 3133 * Access: RW 3134 */ 3135 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3136 3137 /* reg_ptce2_tcam_region_info 3138 * Opaque object that represents the TCAM region. 3139 * Access: Index 3140 */ 3141 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3142 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3143 3144 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3145 3146 /* reg_ptce2_flex_key_blocks 3147 * ACL Key. 3148 * Access: RW 3149 */ 3150 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3151 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3152 3153 /* reg_ptce2_mask 3154 * mask- in the same size as key. A bit that is set directs the TCAM 3155 * to compare the corresponding bit in key. A bit that is clear directs 3156 * the TCAM to ignore the corresponding bit in key. 3157 * Access: RW 3158 */ 3159 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3160 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3161 3162 /* reg_ptce2_flex_action_set 3163 * ACL action set. 3164 * Access: RW 3165 */ 3166 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3167 MLXSW_REG_FLEX_ACTION_SET_LEN); 3168 3169 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3170 enum mlxsw_reg_ptce2_op op, 3171 const char *tcam_region_info, 3172 u16 offset, u32 priority) 3173 { 3174 MLXSW_REG_ZERO(ptce2, payload); 3175 mlxsw_reg_ptce2_v_set(payload, valid); 3176 mlxsw_reg_ptce2_op_set(payload, op); 3177 mlxsw_reg_ptce2_offset_set(payload, offset); 3178 mlxsw_reg_ptce2_priority_set(payload, priority); 3179 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3180 } 3181 3182 /* PERPT - Policy-Engine ERP Table Register 3183 * ---------------------------------------- 3184 * This register adds and removes eRPs from the eRP table. 3185 */ 3186 #define MLXSW_REG_PERPT_ID 0x3021 3187 #define MLXSW_REG_PERPT_LEN 0x80 3188 3189 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3190 3191 /* reg_perpt_erpt_bank 3192 * eRP table bank. 3193 * Range 0 .. cap_max_erp_table_banks - 1 3194 * Access: Index 3195 */ 3196 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3197 3198 /* reg_perpt_erpt_index 3199 * Index to eRP table within the eRP bank. 3200 * Range is 0 .. cap_max_erp_table_bank_size - 1 3201 * Access: Index 3202 */ 3203 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3204 3205 enum mlxsw_reg_perpt_key_size { 3206 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3207 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3208 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3209 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3210 }; 3211 3212 /* reg_perpt_key_size 3213 * Access: OP 3214 */ 3215 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3216 3217 /* reg_perpt_bf_bypass 3218 * 0 - The eRP is used only if bloom filter state is set for the given 3219 * rule. 3220 * 1 - The eRP is used regardless of bloom filter state. 3221 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3222 * Access: RW 3223 */ 3224 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3225 3226 /* reg_perpt_erp_id 3227 * eRP ID for use by the rules. 3228 * Access: RW 3229 */ 3230 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3231 3232 /* reg_perpt_erpt_base_bank 3233 * Base eRP table bank, points to head of erp_vector 3234 * Range is 0 .. cap_max_erp_table_banks - 1 3235 * Access: OP 3236 */ 3237 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3238 3239 /* reg_perpt_erpt_base_index 3240 * Base index to eRP table within the eRP bank 3241 * Range is 0 .. cap_max_erp_table_bank_size - 1 3242 * Access: OP 3243 */ 3244 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3245 3246 /* reg_perpt_erp_index_in_vector 3247 * eRP index in the vector. 3248 * Access: OP 3249 */ 3250 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3251 3252 /* reg_perpt_erp_vector 3253 * eRP vector. 3254 * Access: OP 3255 */ 3256 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3257 3258 /* reg_perpt_mask 3259 * Mask 3260 * 0 - A-TCAM will ignore the bit in key 3261 * 1 - A-TCAM will compare the bit in key 3262 * Access: RW 3263 */ 3264 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3265 3266 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3267 unsigned long *erp_vector, 3268 unsigned long size) 3269 { 3270 unsigned long bit; 3271 3272 for_each_set_bit(bit, erp_vector, size) 3273 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3274 } 3275 3276 static inline void 3277 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3278 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3279 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3280 char *mask) 3281 { 3282 MLXSW_REG_ZERO(perpt, payload); 3283 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3284 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3285 mlxsw_reg_perpt_key_size_set(payload, key_size); 3286 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3287 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3288 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3289 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3290 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3291 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3292 } 3293 3294 /* PERAR - Policy-Engine Region Association Register 3295 * ------------------------------------------------- 3296 * This register associates a hw region for region_id's. Changing on the fly 3297 * is supported by the device. 3298 */ 3299 #define MLXSW_REG_PERAR_ID 0x3026 3300 #define MLXSW_REG_PERAR_LEN 0x08 3301 3302 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3303 3304 /* reg_perar_region_id 3305 * Region identifier 3306 * Range 0 .. cap_max_regions-1 3307 * Access: Index 3308 */ 3309 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3310 3311 static inline unsigned int 3312 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3313 { 3314 return DIV_ROUND_UP(block_num, 4); 3315 } 3316 3317 /* reg_perar_hw_region 3318 * HW Region 3319 * Range 0 .. cap_max_regions-1 3320 * Default: hw_region = region_id 3321 * For a 8 key block region, 2 consecutive regions are used 3322 * For a 12 key block region, 3 consecutive regions are used 3323 * Access: RW 3324 */ 3325 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3326 3327 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3328 u16 hw_region) 3329 { 3330 MLXSW_REG_ZERO(perar, payload); 3331 mlxsw_reg_perar_region_id_set(payload, region_id); 3332 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3333 } 3334 3335 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3336 * ----------------------------------------------------- 3337 * This register is a new version of PTCE-V2 in order to support the 3338 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3339 */ 3340 #define MLXSW_REG_PTCE3_ID 0x3027 3341 #define MLXSW_REG_PTCE3_LEN 0xF0 3342 3343 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3344 3345 /* reg_ptce3_v 3346 * Valid. 3347 * Access: RW 3348 */ 3349 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3350 3351 enum mlxsw_reg_ptce3_op { 3352 /* Write operation. Used to write a new entry to the table. 3353 * All R/W fields are relevant for new entry. Activity bit is set 3354 * for new entries. Write with v = 0 will delete the entry. Must 3355 * not be used if an entry exists. 3356 */ 3357 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3358 /* Update operation */ 3359 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3360 /* Read operation */ 3361 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3362 }; 3363 3364 /* reg_ptce3_op 3365 * Access: OP 3366 */ 3367 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3368 3369 /* reg_ptce3_priority 3370 * Priority of the rule. Higher values win. 3371 * For Spectrum-2 range is 1..cap_kvd_size - 1 3372 * Note: Priority does not have to be unique per rule. 3373 * Access: RW 3374 */ 3375 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3376 3377 /* reg_ptce3_tcam_region_info 3378 * Opaque object that represents the TCAM region. 3379 * Access: Index 3380 */ 3381 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3382 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3383 3384 /* reg_ptce3_flex2_key_blocks 3385 * ACL key. The key must be masked according to eRP (if exists) or 3386 * according to master mask. 3387 * Access: Index 3388 */ 3389 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3390 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3391 3392 /* reg_ptce3_erp_id 3393 * eRP ID. 3394 * Access: Index 3395 */ 3396 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3397 3398 /* reg_ptce3_delta_start 3399 * Start point of delta_value and delta_mask, in bits. Must not exceed 3400 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3401 * Access: Index 3402 */ 3403 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3404 3405 /* reg_ptce3_delta_mask 3406 * Delta mask. 3407 * 0 - Ignore relevant bit in delta_value 3408 * 1 - Compare relevant bit in delta_value 3409 * Delta mask must not be set for reserved fields in the key blocks. 3410 * Note: No delta when no eRPs. Thus, for regions with 3411 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3412 * Access: Index 3413 */ 3414 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3415 3416 /* reg_ptce3_delta_value 3417 * Delta value. 3418 * Bits which are masked by delta_mask must be 0. 3419 * Access: Index 3420 */ 3421 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3422 3423 /* reg_ptce3_prune_vector 3424 * Pruning vector relative to the PERPT.erp_id. 3425 * Used for reducing lookups. 3426 * 0 - NEED: Do a lookup using the eRP. 3427 * 1 - PRUNE: Do not perform a lookup using the eRP. 3428 * Maybe be modified by PEAPBL and PEAPBM. 3429 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3430 * all 1's or all 0's. 3431 * Access: RW 3432 */ 3433 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3434 3435 /* reg_ptce3_prune_ctcam 3436 * Pruning on C-TCAM. Used for reducing lookups. 3437 * 0 - NEED: Do a lookup in the C-TCAM. 3438 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3439 * Access: RW 3440 */ 3441 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3442 3443 /* reg_ptce3_large_exists 3444 * Large entry key ID exists. 3445 * Within the region: 3446 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3447 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3448 * For rule delete: The MSB of the key will be removed. 3449 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3450 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3451 * For rule delete: The MSB of the key will not be removed. 3452 * Access: WO 3453 */ 3454 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3455 3456 /* reg_ptce3_large_entry_key_id 3457 * Large entry key ID. 3458 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3459 * blocks. Must be different for different keys which have the same common 3460 * 6 key blocks (MSB, blocks 6..11) key within a region. 3461 * Range is 0..cap_max_pe_large_key_id - 1 3462 * Access: RW 3463 */ 3464 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3465 3466 /* reg_ptce3_action_pointer 3467 * Pointer to action. 3468 * Range is 0..cap_max_kvd_action_sets - 1 3469 * Access: RW 3470 */ 3471 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3472 3473 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3474 enum mlxsw_reg_ptce3_op op, 3475 u32 priority, 3476 const char *tcam_region_info, 3477 const char *key, u8 erp_id, 3478 u16 delta_start, u8 delta_mask, 3479 u8 delta_value, bool large_exists, 3480 u32 lkey_id, u32 action_pointer) 3481 { 3482 MLXSW_REG_ZERO(ptce3, payload); 3483 mlxsw_reg_ptce3_v_set(payload, valid); 3484 mlxsw_reg_ptce3_op_set(payload, op); 3485 mlxsw_reg_ptce3_priority_set(payload, priority); 3486 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3487 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3488 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3489 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3490 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3491 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3492 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3493 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3494 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3495 } 3496 3497 /* PERCR - Policy-Engine Region Configuration Register 3498 * --------------------------------------------------- 3499 * This register configures the region parameters. The region_id must be 3500 * allocated. 3501 */ 3502 #define MLXSW_REG_PERCR_ID 0x302A 3503 #define MLXSW_REG_PERCR_LEN 0x80 3504 3505 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3506 3507 /* reg_percr_region_id 3508 * Region identifier. 3509 * Range 0..cap_max_regions-1 3510 * Access: Index 3511 */ 3512 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3513 3514 /* reg_percr_atcam_ignore_prune 3515 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3516 * Access: RW 3517 */ 3518 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3519 3520 /* reg_percr_ctcam_ignore_prune 3521 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3522 * Access: RW 3523 */ 3524 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3525 3526 /* reg_percr_bf_bypass 3527 * Bloom filter bypass. 3528 * 0 - Bloom filter is used (default) 3529 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3530 * region_id or eRP. See PERPT.bf_bypass 3531 * Access: RW 3532 */ 3533 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3534 3535 /* reg_percr_master_mask 3536 * Master mask. Logical OR mask of all masks of all rules of a region 3537 * (both A-TCAM and C-TCAM). When there are no eRPs 3538 * (erpt_pointer_valid = 0), then this provides the mask. 3539 * Access: RW 3540 */ 3541 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3542 3543 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3544 { 3545 MLXSW_REG_ZERO(percr, payload); 3546 mlxsw_reg_percr_region_id_set(payload, region_id); 3547 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3548 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3549 mlxsw_reg_percr_bf_bypass_set(payload, false); 3550 } 3551 3552 /* PERERP - Policy-Engine Region eRP Register 3553 * ------------------------------------------ 3554 * This register configures the region eRP. The region_id must be 3555 * allocated. 3556 */ 3557 #define MLXSW_REG_PERERP_ID 0x302B 3558 #define MLXSW_REG_PERERP_LEN 0x1C 3559 3560 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3561 3562 /* reg_pererp_region_id 3563 * Region identifier. 3564 * Range 0..cap_max_regions-1 3565 * Access: Index 3566 */ 3567 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3568 3569 /* reg_pererp_ctcam_le 3570 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3571 * Access: RW 3572 */ 3573 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3574 3575 /* reg_pererp_erpt_pointer_valid 3576 * erpt_pointer is valid. 3577 * Access: RW 3578 */ 3579 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3580 3581 /* reg_pererp_erpt_bank_pointer 3582 * Pointer to eRP table bank. May be modified at any time. 3583 * Range 0..cap_max_erp_table_banks-1 3584 * Reserved when erpt_pointer_valid = 0 3585 */ 3586 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3587 3588 /* reg_pererp_erpt_pointer 3589 * Pointer to eRP table within the eRP bank. Can be changed for an 3590 * existing region. 3591 * Range 0..cap_max_erp_table_size-1 3592 * Reserved when erpt_pointer_valid = 0 3593 * Access: RW 3594 */ 3595 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3596 3597 /* reg_pererp_erpt_vector 3598 * Vector of allowed eRP indexes starting from erpt_pointer within the 3599 * erpt_bank_pointer. Next entries will be in next bank. 3600 * Note that eRP index is used and not eRP ID. 3601 * Reserved when erpt_pointer_valid = 0 3602 * Access: RW 3603 */ 3604 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3605 3606 /* reg_pererp_master_rp_id 3607 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3608 * for the lookup. Can be changed for an existing region. 3609 * Reserved when erpt_pointer_valid = 1 3610 * Access: RW 3611 */ 3612 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3613 3614 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3615 unsigned long *erp_vector, 3616 unsigned long size) 3617 { 3618 unsigned long bit; 3619 3620 for_each_set_bit(bit, erp_vector, size) 3621 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3622 } 3623 3624 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3625 bool ctcam_le, bool erpt_pointer_valid, 3626 u8 erpt_bank_pointer, u8 erpt_pointer, 3627 u8 master_rp_id) 3628 { 3629 MLXSW_REG_ZERO(pererp, payload); 3630 mlxsw_reg_pererp_region_id_set(payload, region_id); 3631 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3632 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3633 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3634 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3635 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3636 } 3637 3638 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3639 * ---------------------------------------------------------------- 3640 * This register configures the Bloom filter entries. 3641 */ 3642 #define MLXSW_REG_PEABFE_ID 0x3022 3643 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3644 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3645 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3646 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3647 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3648 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3649 3650 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3651 3652 /* reg_peabfe_size 3653 * Number of BF entries to be updated. 3654 * Range 1..256 3655 * Access: Op 3656 */ 3657 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3658 3659 /* reg_peabfe_bf_entry_state 3660 * Bloom filter state 3661 * 0 - Clear 3662 * 1 - Set 3663 * Access: RW 3664 */ 3665 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3666 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3667 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3668 3669 /* reg_peabfe_bf_entry_bank 3670 * Bloom filter bank ID 3671 * Range 0..cap_max_erp_table_banks-1 3672 * Access: Index 3673 */ 3674 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3675 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3676 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3677 3678 /* reg_peabfe_bf_entry_index 3679 * Bloom filter entry index 3680 * Range 0..2^cap_max_bf_log-1 3681 * Access: Index 3682 */ 3683 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3684 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3685 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3686 3687 static inline void mlxsw_reg_peabfe_pack(char *payload) 3688 { 3689 MLXSW_REG_ZERO(peabfe, payload); 3690 } 3691 3692 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3693 u8 state, u8 bank, u32 bf_index) 3694 { 3695 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3696 3697 if (rec_index >= num_rec) 3698 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3699 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3700 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3701 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3702 } 3703 3704 /* IEDR - Infrastructure Entry Delete Register 3705 * ---------------------------------------------------- 3706 * This register is used for deleting entries from the entry tables. 3707 * It is legitimate to attempt to delete a nonexisting entry (the device will 3708 * respond as a good flow). 3709 */ 3710 #define MLXSW_REG_IEDR_ID 0x3804 3711 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3712 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3713 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3714 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3715 MLXSW_REG_IEDR_REC_LEN * \ 3716 MLXSW_REG_IEDR_REC_MAX_COUNT) 3717 3718 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3719 3720 /* reg_iedr_num_rec 3721 * Number of records. 3722 * Access: OP 3723 */ 3724 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3725 3726 /* reg_iedr_rec_type 3727 * Resource type. 3728 * Access: OP 3729 */ 3730 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3731 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3732 3733 /* reg_iedr_rec_size 3734 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3735 * Access: OP 3736 */ 3737 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3738 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3739 3740 /* reg_iedr_rec_index_start 3741 * Resource index start. 3742 * Access: OP 3743 */ 3744 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3745 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3746 3747 static inline void mlxsw_reg_iedr_pack(char *payload) 3748 { 3749 MLXSW_REG_ZERO(iedr, payload); 3750 } 3751 3752 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3753 u8 rec_type, u16 rec_size, 3754 u32 rec_index_start) 3755 { 3756 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3757 3758 if (rec_index >= num_rec) 3759 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3760 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3761 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3762 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3763 } 3764 3765 /* QPTS - QoS Priority Trust State Register 3766 * ---------------------------------------- 3767 * This register controls the port policy to calculate the switch priority and 3768 * packet color based on incoming packet fields. 3769 */ 3770 #define MLXSW_REG_QPTS_ID 0x4002 3771 #define MLXSW_REG_QPTS_LEN 0x8 3772 3773 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3774 3775 /* reg_qpts_local_port 3776 * Local port number. 3777 * Access: Index 3778 * 3779 * Note: CPU port is supported. 3780 */ 3781 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3782 3783 enum mlxsw_reg_qpts_trust_state { 3784 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3785 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3786 }; 3787 3788 /* reg_qpts_trust_state 3789 * Trust state for a given port. 3790 * Access: RW 3791 */ 3792 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3793 3794 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3795 enum mlxsw_reg_qpts_trust_state ts) 3796 { 3797 MLXSW_REG_ZERO(qpts, payload); 3798 3799 mlxsw_reg_qpts_local_port_set(payload, local_port); 3800 mlxsw_reg_qpts_trust_state_set(payload, ts); 3801 } 3802 3803 /* QPCR - QoS Policer Configuration Register 3804 * ----------------------------------------- 3805 * The QPCR register is used to create policers - that limit 3806 * the rate of bytes or packets via some trap group. 3807 */ 3808 #define MLXSW_REG_QPCR_ID 0x4004 3809 #define MLXSW_REG_QPCR_LEN 0x28 3810 3811 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3812 3813 enum mlxsw_reg_qpcr_g { 3814 MLXSW_REG_QPCR_G_GLOBAL = 2, 3815 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3816 }; 3817 3818 /* reg_qpcr_g 3819 * The policer type. 3820 * Access: Index 3821 */ 3822 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3823 3824 /* reg_qpcr_pid 3825 * Policer ID. 3826 * Access: Index 3827 */ 3828 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3829 3830 /* reg_qpcr_clear_counter 3831 * Clear counters. 3832 * Access: OP 3833 */ 3834 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3835 3836 /* reg_qpcr_color_aware 3837 * Is the policer aware of colors. 3838 * Must be 0 (unaware) for cpu port. 3839 * Access: RW for unbounded policer. RO for bounded policer. 3840 */ 3841 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3842 3843 /* reg_qpcr_bytes 3844 * Is policer limit is for bytes per sec or packets per sec. 3845 * 0 - packets 3846 * 1 - bytes 3847 * Access: RW for unbounded policer. RO for bounded policer. 3848 */ 3849 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3850 3851 enum mlxsw_reg_qpcr_ir_units { 3852 MLXSW_REG_QPCR_IR_UNITS_M, 3853 MLXSW_REG_QPCR_IR_UNITS_K, 3854 }; 3855 3856 /* reg_qpcr_ir_units 3857 * Policer's units for cir and eir fields (for bytes limits only) 3858 * 1 - 10^3 3859 * 0 - 10^6 3860 * Access: OP 3861 */ 3862 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3863 3864 enum mlxsw_reg_qpcr_rate_type { 3865 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3866 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3867 }; 3868 3869 /* reg_qpcr_rate_type 3870 * Policer can have one limit (single rate) or 2 limits with specific operation 3871 * for packets that exceed the lower rate but not the upper one. 3872 * (For cpu port must be single rate) 3873 * Access: RW for unbounded policer. RO for bounded policer. 3874 */ 3875 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3876 3877 /* reg_qpc_cbs 3878 * Policer's committed burst size. 3879 * The policer is working with time slices of 50 nano sec. By default every 3880 * slice is granted the proportionate share of the committed rate. If we want to 3881 * allow a slice to exceed that share (while still keeping the rate per sec) we 3882 * can allow burst. The burst size is between the default proportionate share 3883 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3884 * committed rate will result in exceeding the rate). The burst size must be a 3885 * log of 2 and will be determined by 2^cbs. 3886 * Access: RW 3887 */ 3888 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3889 3890 /* reg_qpcr_cir 3891 * Policer's committed rate. 3892 * The rate used for sungle rate, the lower rate for double rate. 3893 * For bytes limits, the rate will be this value * the unit from ir_units. 3894 * (Resolution error is up to 1%). 3895 * Access: RW 3896 */ 3897 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3898 3899 /* reg_qpcr_eir 3900 * Policer's exceed rate. 3901 * The higher rate for double rate, reserved for single rate. 3902 * Lower rate for double rate policer. 3903 * For bytes limits, the rate will be this value * the unit from ir_units. 3904 * (Resolution error is up to 1%). 3905 * Access: RW 3906 */ 3907 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3908 3909 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3910 3911 /* reg_qpcr_exceed_action. 3912 * What to do with packets between the 2 limits for double rate. 3913 * Access: RW for unbounded policer. RO for bounded policer. 3914 */ 3915 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3916 3917 enum mlxsw_reg_qpcr_action { 3918 /* Discard */ 3919 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3920 /* Forward and set color to red. 3921 * If the packet is intended to cpu port, it will be dropped. 3922 */ 3923 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3924 }; 3925 3926 /* reg_qpcr_violate_action 3927 * What to do with packets that cross the cir limit (for single rate) or the eir 3928 * limit (for double rate). 3929 * Access: RW for unbounded policer. RO for bounded policer. 3930 */ 3931 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3932 3933 /* reg_qpcr_violate_count 3934 * Counts the number of times violate_action happened on this PID. 3935 * Access: RW 3936 */ 3937 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3938 3939 /* Packets */ 3940 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3941 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3942 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3943 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3944 3945 /* Bandwidth */ 3946 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3947 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3948 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3949 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3950 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3951 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3952 3953 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3954 enum mlxsw_reg_qpcr_ir_units ir_units, 3955 bool bytes, u32 cir, u16 cbs) 3956 { 3957 MLXSW_REG_ZERO(qpcr, payload); 3958 mlxsw_reg_qpcr_pid_set(payload, pid); 3959 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3960 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3961 mlxsw_reg_qpcr_violate_action_set(payload, 3962 MLXSW_REG_QPCR_ACTION_DISCARD); 3963 mlxsw_reg_qpcr_cir_set(payload, cir); 3964 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3965 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3966 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3967 } 3968 3969 /* QTCT - QoS Switch Traffic Class Table 3970 * ------------------------------------- 3971 * Configures the mapping between the packet switch priority and the 3972 * traffic class on the transmit port. 3973 */ 3974 #define MLXSW_REG_QTCT_ID 0x400A 3975 #define MLXSW_REG_QTCT_LEN 0x08 3976 3977 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3978 3979 /* reg_qtct_local_port 3980 * Local port number. 3981 * Access: Index 3982 * 3983 * Note: CPU port is not supported. 3984 */ 3985 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3986 3987 /* reg_qtct_sub_port 3988 * Virtual port within the physical port. 3989 * Should be set to 0 when virtual ports are not enabled on the port. 3990 * Access: Index 3991 */ 3992 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3993 3994 /* reg_qtct_switch_prio 3995 * Switch priority. 3996 * Access: Index 3997 */ 3998 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3999 4000 /* reg_qtct_tclass 4001 * Traffic class. 4002 * Default values: 4003 * switch_prio 0 : tclass 1 4004 * switch_prio 1 : tclass 0 4005 * switch_prio i : tclass i, for i > 1 4006 * Access: RW 4007 */ 4008 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 4009 4010 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 4011 u8 switch_prio, u8 tclass) 4012 { 4013 MLXSW_REG_ZERO(qtct, payload); 4014 mlxsw_reg_qtct_local_port_set(payload, local_port); 4015 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 4016 mlxsw_reg_qtct_tclass_set(payload, tclass); 4017 } 4018 4019 /* QEEC - QoS ETS Element Configuration Register 4020 * --------------------------------------------- 4021 * Configures the ETS elements. 4022 */ 4023 #define MLXSW_REG_QEEC_ID 0x400D 4024 #define MLXSW_REG_QEEC_LEN 0x20 4025 4026 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 4027 4028 /* reg_qeec_local_port 4029 * Local port number. 4030 * Access: Index 4031 * 4032 * Note: CPU port is supported. 4033 */ 4034 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 4035 4036 enum mlxsw_reg_qeec_hr { 4037 MLXSW_REG_QEEC_HR_PORT, 4038 MLXSW_REG_QEEC_HR_GROUP, 4039 MLXSW_REG_QEEC_HR_SUBGROUP, 4040 MLXSW_REG_QEEC_HR_TC, 4041 }; 4042 4043 /* reg_qeec_element_hierarchy 4044 * 0 - Port 4045 * 1 - Group 4046 * 2 - Subgroup 4047 * 3 - Traffic Class 4048 * Access: Index 4049 */ 4050 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 4051 4052 /* reg_qeec_element_index 4053 * The index of the element in the hierarchy. 4054 * Access: Index 4055 */ 4056 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 4057 4058 /* reg_qeec_next_element_index 4059 * The index of the next (lower) element in the hierarchy. 4060 * Access: RW 4061 * 4062 * Note: Reserved for element_hierarchy 0. 4063 */ 4064 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 4065 4066 /* reg_qeec_mise 4067 * Min shaper configuration enable. Enables configuration of the min 4068 * shaper on this ETS element 4069 * 0 - Disable 4070 * 1 - Enable 4071 * Access: RW 4072 */ 4073 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4074 4075 /* reg_qeec_ptps 4076 * PTP shaper 4077 * 0: regular shaper mode 4078 * 1: PTP oriented shaper 4079 * Allowed only for hierarchy 0 4080 * Not supported for CPU port 4081 * Note that ptps mode may affect the shaper rates of all hierarchies 4082 * Supported only on Spectrum-1 4083 * Access: RW 4084 */ 4085 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4086 4087 enum { 4088 MLXSW_REG_QEEC_BYTES_MODE, 4089 MLXSW_REG_QEEC_PACKETS_MODE, 4090 }; 4091 4092 /* reg_qeec_pb 4093 * Packets or bytes mode. 4094 * 0 - Bytes mode 4095 * 1 - Packets mode 4096 * Access: RW 4097 * 4098 * Note: Used for max shaper configuration. For Spectrum, packets mode 4099 * is supported only for traffic classes of CPU port. 4100 */ 4101 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4102 4103 /* The smallest permitted min shaper rate. */ 4104 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4105 4106 /* reg_qeec_min_shaper_rate 4107 * Min shaper information rate. 4108 * For CPU port, can only be configured for port hierarchy. 4109 * When in bytes mode, value is specified in units of 1000bps. 4110 * Access: RW 4111 */ 4112 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4113 4114 /* reg_qeec_mase 4115 * Max shaper configuration enable. Enables configuration of the max 4116 * shaper on this ETS element. 4117 * 0 - Disable 4118 * 1 - Enable 4119 * Access: RW 4120 */ 4121 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4122 4123 /* The largest max shaper value possible to disable the shaper. */ 4124 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4125 4126 /* reg_qeec_max_shaper_rate 4127 * Max shaper information rate. 4128 * For CPU port, can only be configured for port hierarchy. 4129 * When in bytes mode, value is specified in units of 1000bps. 4130 * Access: RW 4131 */ 4132 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4133 4134 /* reg_qeec_de 4135 * DWRR configuration enable. Enables configuration of the dwrr and 4136 * dwrr_weight. 4137 * 0 - Disable 4138 * 1 - Enable 4139 * Access: RW 4140 */ 4141 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4142 4143 /* reg_qeec_dwrr 4144 * Transmission selection algorithm to use on the link going down from 4145 * the ETS element. 4146 * 0 - Strict priority 4147 * 1 - DWRR 4148 * Access: RW 4149 */ 4150 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4151 4152 /* reg_qeec_dwrr_weight 4153 * DWRR weight on the link going down from the ETS element. The 4154 * percentage of bandwidth guaranteed to an ETS element within 4155 * its hierarchy. The sum of all weights across all ETS elements 4156 * within one hierarchy should be equal to 100. Reserved when 4157 * transmission selection algorithm is strict priority. 4158 * Access: RW 4159 */ 4160 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4161 4162 /* reg_qeec_max_shaper_bs 4163 * Max shaper burst size 4164 * Burst size is 2^max_shaper_bs * 512 bits 4165 * For Spectrum-1: Range is: 5..25 4166 * For Spectrum-2: Range is: 11..25 4167 * Reserved when ptps = 1 4168 * Access: RW 4169 */ 4170 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4171 4172 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4173 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4174 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4175 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4176 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4177 4178 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4179 enum mlxsw_reg_qeec_hr hr, u8 index, 4180 u8 next_index) 4181 { 4182 MLXSW_REG_ZERO(qeec, payload); 4183 mlxsw_reg_qeec_local_port_set(payload, local_port); 4184 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4185 mlxsw_reg_qeec_element_index_set(payload, index); 4186 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4187 } 4188 4189 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4190 bool ptps) 4191 { 4192 MLXSW_REG_ZERO(qeec, payload); 4193 mlxsw_reg_qeec_local_port_set(payload, local_port); 4194 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4195 mlxsw_reg_qeec_ptps_set(payload, ptps); 4196 } 4197 4198 /* QRWE - QoS ReWrite Enable 4199 * ------------------------- 4200 * This register configures the rewrite enable per receive port. 4201 */ 4202 #define MLXSW_REG_QRWE_ID 0x400F 4203 #define MLXSW_REG_QRWE_LEN 0x08 4204 4205 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4206 4207 /* reg_qrwe_local_port 4208 * Local port number. 4209 * Access: Index 4210 * 4211 * Note: CPU port is supported. No support for router port. 4212 */ 4213 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4214 4215 /* reg_qrwe_dscp 4216 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4217 * Access: RW 4218 */ 4219 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4220 4221 /* reg_qrwe_pcp 4222 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4223 * Access: RW 4224 */ 4225 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4226 4227 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4228 bool rewrite_pcp, bool rewrite_dscp) 4229 { 4230 MLXSW_REG_ZERO(qrwe, payload); 4231 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4232 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4233 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4234 } 4235 4236 /* QPDSM - QoS Priority to DSCP Mapping 4237 * ------------------------------------ 4238 * QoS Priority to DSCP Mapping Register 4239 */ 4240 #define MLXSW_REG_QPDSM_ID 0x4011 4241 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4242 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4243 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4244 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4245 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4246 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4247 4248 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4249 4250 /* reg_qpdsm_local_port 4251 * Local Port. Supported for data packets from CPU port. 4252 * Access: Index 4253 */ 4254 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4255 4256 /* reg_qpdsm_prio_entry_color0_e 4257 * Enable update of the entry for color 0 and a given port. 4258 * Access: WO 4259 */ 4260 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4261 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4262 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4263 4264 /* reg_qpdsm_prio_entry_color0_dscp 4265 * DSCP field in the outer label of the packet for color 0 and a given port. 4266 * Reserved when e=0. 4267 * Access: RW 4268 */ 4269 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4270 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4271 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4272 4273 /* reg_qpdsm_prio_entry_color1_e 4274 * Enable update of the entry for color 1 and a given port. 4275 * Access: WO 4276 */ 4277 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4278 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4279 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4280 4281 /* reg_qpdsm_prio_entry_color1_dscp 4282 * DSCP field in the outer label of the packet for color 1 and a given port. 4283 * Reserved when e=0. 4284 * Access: RW 4285 */ 4286 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4287 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4288 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4289 4290 /* reg_qpdsm_prio_entry_color2_e 4291 * Enable update of the entry for color 2 and a given port. 4292 * Access: WO 4293 */ 4294 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4295 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4296 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4297 4298 /* reg_qpdsm_prio_entry_color2_dscp 4299 * DSCP field in the outer label of the packet for color 2 and a given port. 4300 * Reserved when e=0. 4301 * Access: RW 4302 */ 4303 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4304 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4305 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4306 4307 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4308 { 4309 MLXSW_REG_ZERO(qpdsm, payload); 4310 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4311 } 4312 4313 static inline void 4314 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4315 { 4316 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4317 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4318 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4319 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4320 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4321 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4322 } 4323 4324 /* QPDP - QoS Port DSCP to Priority Mapping Register 4325 * ------------------------------------------------- 4326 * This register controls the port default Switch Priority and Color. The 4327 * default Switch Priority and Color are used for frames where the trust state 4328 * uses default values. All member ports of a LAG should be configured with the 4329 * same default values. 4330 */ 4331 #define MLXSW_REG_QPDP_ID 0x4007 4332 #define MLXSW_REG_QPDP_LEN 0x8 4333 4334 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4335 4336 /* reg_qpdp_local_port 4337 * Local Port. Supported for data packets from CPU port. 4338 * Access: Index 4339 */ 4340 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4341 4342 /* reg_qpdp_switch_prio 4343 * Default port Switch Priority (default 0) 4344 * Access: RW 4345 */ 4346 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4347 4348 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4349 u8 switch_prio) 4350 { 4351 MLXSW_REG_ZERO(qpdp, payload); 4352 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4353 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4354 } 4355 4356 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4357 * -------------------------------------------------- 4358 * This register controls the mapping from DSCP field to 4359 * Switch Priority for IP packets. 4360 */ 4361 #define MLXSW_REG_QPDPM_ID 0x4013 4362 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4363 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4364 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4365 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4366 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4367 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4368 4369 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4370 4371 /* reg_qpdpm_local_port 4372 * Local Port. Supported for data packets from CPU port. 4373 * Access: Index 4374 */ 4375 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4376 4377 /* reg_qpdpm_dscp_e 4378 * Enable update of the specific entry. When cleared, the switch_prio and color 4379 * fields are ignored and the previous switch_prio and color values are 4380 * preserved. 4381 * Access: WO 4382 */ 4383 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4384 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4385 4386 /* reg_qpdpm_dscp_prio 4387 * The new Switch Priority value for the relevant DSCP value. 4388 * Access: RW 4389 */ 4390 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4391 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4392 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4393 4394 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4395 { 4396 MLXSW_REG_ZERO(qpdpm, payload); 4397 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4398 } 4399 4400 static inline void 4401 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4402 { 4403 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4404 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4405 } 4406 4407 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4408 * ------------------------------------------------------------------ 4409 * This register configures if the Switch Priority to Traffic Class mapping is 4410 * based on Multicast packet indication. If so, then multicast packets will get 4411 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4412 * QTCT. 4413 * By default, Switch Priority to Traffic Class mapping is not based on 4414 * Multicast packet indication. 4415 */ 4416 #define MLXSW_REG_QTCTM_ID 0x401A 4417 #define MLXSW_REG_QTCTM_LEN 0x08 4418 4419 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4420 4421 /* reg_qtctm_local_port 4422 * Local port number. 4423 * No support for CPU port. 4424 * Access: Index 4425 */ 4426 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4427 4428 /* reg_qtctm_mc 4429 * Multicast Mode 4430 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4431 * indication (default is 0, not based on Multicast packet indication). 4432 */ 4433 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4434 4435 static inline void 4436 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4437 { 4438 MLXSW_REG_ZERO(qtctm, payload); 4439 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4440 mlxsw_reg_qtctm_mc_set(payload, mc); 4441 } 4442 4443 /* QPSC - QoS PTP Shaper Configuration Register 4444 * -------------------------------------------- 4445 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4446 * Supported only on Spectrum-1. 4447 */ 4448 #define MLXSW_REG_QPSC_ID 0x401B 4449 #define MLXSW_REG_QPSC_LEN 0x28 4450 4451 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4452 4453 enum mlxsw_reg_qpsc_port_speed { 4454 MLXSW_REG_QPSC_PORT_SPEED_100M, 4455 MLXSW_REG_QPSC_PORT_SPEED_1G, 4456 MLXSW_REG_QPSC_PORT_SPEED_10G, 4457 MLXSW_REG_QPSC_PORT_SPEED_25G, 4458 }; 4459 4460 /* reg_qpsc_port_speed 4461 * Port speed. 4462 * Access: Index 4463 */ 4464 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4465 4466 /* reg_qpsc_shaper_time_exp 4467 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4468 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4469 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4470 * Access: RW 4471 */ 4472 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4473 4474 /* reg_qpsc_shaper_time_mantissa 4475 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4476 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4477 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4478 * Access: RW 4479 */ 4480 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4481 4482 /* reg_qpsc_shaper_inc 4483 * Number of tokens added to shaper on each update. 4484 * Units of 8B. 4485 * Access: RW 4486 */ 4487 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4488 4489 /* reg_qpsc_shaper_bs 4490 * Max shaper Burst size. 4491 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4492 * Range is: 5..25 (from 2KB..2GB) 4493 * Access: RW 4494 */ 4495 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4496 4497 /* reg_qpsc_ptsc_we 4498 * Write enable to port_to_shaper_credits. 4499 * Access: WO 4500 */ 4501 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4502 4503 /* reg_qpsc_port_to_shaper_credits 4504 * For split ports: range 1..57 4505 * For non-split ports: range 1..112 4506 * Written only when ptsc_we is set. 4507 * Access: RW 4508 */ 4509 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4510 4511 /* reg_qpsc_ing_timestamp_inc 4512 * Ingress timestamp increment. 4513 * 2's complement. 4514 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4515 * value for all ports. 4516 * Same units as used by MTPPTR. 4517 * Access: RW 4518 */ 4519 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4520 4521 /* reg_qpsc_egr_timestamp_inc 4522 * Egress timestamp increment. 4523 * 2's complement. 4524 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4525 * value for all ports. 4526 * Same units as used by MTPPTR. 4527 * Access: RW 4528 */ 4529 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4530 4531 static inline void 4532 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4533 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4534 u8 shaper_bs, u8 port_to_shaper_credits, 4535 int ing_timestamp_inc, int egr_timestamp_inc) 4536 { 4537 MLXSW_REG_ZERO(qpsc, payload); 4538 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4539 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4540 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4541 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4542 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4543 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4544 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4545 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4546 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4547 } 4548 4549 /* PMLP - Ports Module to Local Port Register 4550 * ------------------------------------------ 4551 * Configures the assignment of modules to local ports. 4552 */ 4553 #define MLXSW_REG_PMLP_ID 0x5002 4554 #define MLXSW_REG_PMLP_LEN 0x40 4555 4556 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4557 4558 /* reg_pmlp_rxtx 4559 * 0 - Tx value is used for both Tx and Rx. 4560 * 1 - Rx value is taken from a separte field. 4561 * Access: RW 4562 */ 4563 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4564 4565 /* reg_pmlp_local_port 4566 * Local port number. 4567 * Access: Index 4568 */ 4569 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4570 4571 /* reg_pmlp_width 4572 * 0 - Unmap local port. 4573 * 1 - Lane 0 is used. 4574 * 2 - Lanes 0 and 1 are used. 4575 * 4 - Lanes 0, 1, 2 and 3 are used. 4576 * 8 - Lanes 0-7 are used. 4577 * Access: RW 4578 */ 4579 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4580 4581 /* reg_pmlp_module 4582 * Module number. 4583 * Access: RW 4584 */ 4585 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4586 4587 /* reg_pmlp_slot_index 4588 * Module number. 4589 * Slot_index 4590 * Slot_index = 0 represent the onboard (motherboard). 4591 * In case of non-modular system only slot_index = 0 is available. 4592 * Access: RW 4593 */ 4594 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4595 4596 /* reg_pmlp_tx_lane 4597 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4598 * Access: RW 4599 */ 4600 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4601 4602 /* reg_pmlp_rx_lane 4603 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4604 * equal to Tx lane. 4605 * Access: RW 4606 */ 4607 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4608 4609 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4610 { 4611 MLXSW_REG_ZERO(pmlp, payload); 4612 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4613 } 4614 4615 /* PMTU - Port MTU Register 4616 * ------------------------ 4617 * Configures and reports the port MTU. 4618 */ 4619 #define MLXSW_REG_PMTU_ID 0x5003 4620 #define MLXSW_REG_PMTU_LEN 0x10 4621 4622 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4623 4624 /* reg_pmtu_local_port 4625 * Local port number. 4626 * Access: Index 4627 */ 4628 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4629 4630 /* reg_pmtu_max_mtu 4631 * Maximum MTU. 4632 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4633 * reported, otherwise the minimum between the max_mtu of the different 4634 * types is reported. 4635 * Access: RO 4636 */ 4637 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4638 4639 /* reg_pmtu_admin_mtu 4640 * MTU value to set port to. Must be smaller or equal to max_mtu. 4641 * Note: If port type is Infiniband, then port must be disabled, when its 4642 * MTU is set. 4643 * Access: RW 4644 */ 4645 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4646 4647 /* reg_pmtu_oper_mtu 4648 * The actual MTU configured on the port. Packets exceeding this size 4649 * will be dropped. 4650 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4651 * oper_mtu might be smaller than admin_mtu. 4652 * Access: RO 4653 */ 4654 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4655 4656 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4657 u16 new_mtu) 4658 { 4659 MLXSW_REG_ZERO(pmtu, payload); 4660 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4661 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4662 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4663 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4664 } 4665 4666 /* PTYS - Port Type and Speed Register 4667 * ----------------------------------- 4668 * Configures and reports the port speed type. 4669 * 4670 * Note: When set while the link is up, the changes will not take effect 4671 * until the port transitions from down to up state. 4672 */ 4673 #define MLXSW_REG_PTYS_ID 0x5004 4674 #define MLXSW_REG_PTYS_LEN 0x40 4675 4676 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4677 4678 /* an_disable_admin 4679 * Auto negotiation disable administrative configuration 4680 * 0 - Device doesn't support AN disable. 4681 * 1 - Device supports AN disable. 4682 * Access: RW 4683 */ 4684 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4685 4686 /* reg_ptys_local_port 4687 * Local port number. 4688 * Access: Index 4689 */ 4690 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4691 4692 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4693 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4694 4695 /* reg_ptys_proto_mask 4696 * Protocol mask. Indicates which protocol is used. 4697 * 0 - Infiniband. 4698 * 1 - Fibre Channel. 4699 * 2 - Ethernet. 4700 * Access: Index 4701 */ 4702 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4703 4704 enum { 4705 MLXSW_REG_PTYS_AN_STATUS_NA, 4706 MLXSW_REG_PTYS_AN_STATUS_OK, 4707 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4708 }; 4709 4710 /* reg_ptys_an_status 4711 * Autonegotiation status. 4712 * Access: RO 4713 */ 4714 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4715 4716 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4717 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4718 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4719 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4720 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4721 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4722 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4723 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4724 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4725 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4726 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4727 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4728 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19) 4729 4730 /* reg_ptys_ext_eth_proto_cap 4731 * Extended Ethernet port supported speeds and protocols. 4732 * Access: RO 4733 */ 4734 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4735 4736 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4737 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4738 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4739 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4740 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4741 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4742 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4743 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4744 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4745 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4746 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4747 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4748 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4749 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4750 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4751 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4752 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4753 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4754 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4755 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4756 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4757 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4758 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4759 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4760 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4761 4762 /* reg_ptys_eth_proto_cap 4763 * Ethernet port supported speeds and protocols. 4764 * Access: RO 4765 */ 4766 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4767 4768 /* reg_ptys_ext_eth_proto_admin 4769 * Extended speed and protocol to set port to. 4770 * Access: RW 4771 */ 4772 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4773 4774 /* reg_ptys_eth_proto_admin 4775 * Speed and protocol to set port to. 4776 * Access: RW 4777 */ 4778 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4779 4780 /* reg_ptys_ext_eth_proto_oper 4781 * The extended current speed and protocol configured for the port. 4782 * Access: RO 4783 */ 4784 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4785 4786 /* reg_ptys_eth_proto_oper 4787 * The current speed and protocol configured for the port. 4788 * Access: RO 4789 */ 4790 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4791 4792 enum mlxsw_reg_ptys_connector_type { 4793 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4794 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4795 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4796 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4797 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4798 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4799 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4800 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4801 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4802 }; 4803 4804 /* reg_ptys_connector_type 4805 * Connector type indication. 4806 * Access: RO 4807 */ 4808 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4809 4810 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4811 u32 proto_admin, bool autoneg) 4812 { 4813 MLXSW_REG_ZERO(ptys, payload); 4814 mlxsw_reg_ptys_local_port_set(payload, local_port); 4815 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4816 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4817 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4818 } 4819 4820 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4821 u32 proto_admin, bool autoneg) 4822 { 4823 MLXSW_REG_ZERO(ptys, payload); 4824 mlxsw_reg_ptys_local_port_set(payload, local_port); 4825 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4826 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4827 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4828 } 4829 4830 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4831 u32 *p_eth_proto_cap, 4832 u32 *p_eth_proto_admin, 4833 u32 *p_eth_proto_oper) 4834 { 4835 if (p_eth_proto_cap) 4836 *p_eth_proto_cap = 4837 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4838 if (p_eth_proto_admin) 4839 *p_eth_proto_admin = 4840 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4841 if (p_eth_proto_oper) 4842 *p_eth_proto_oper = 4843 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4844 } 4845 4846 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4847 u32 *p_eth_proto_cap, 4848 u32 *p_eth_proto_admin, 4849 u32 *p_eth_proto_oper) 4850 { 4851 if (p_eth_proto_cap) 4852 *p_eth_proto_cap = 4853 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4854 if (p_eth_proto_admin) 4855 *p_eth_proto_admin = 4856 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4857 if (p_eth_proto_oper) 4858 *p_eth_proto_oper = 4859 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4860 } 4861 4862 /* PPAD - Port Physical Address Register 4863 * ------------------------------------- 4864 * The PPAD register configures the per port physical MAC address. 4865 */ 4866 #define MLXSW_REG_PPAD_ID 0x5005 4867 #define MLXSW_REG_PPAD_LEN 0x10 4868 4869 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4870 4871 /* reg_ppad_single_base_mac 4872 * 0: base_mac, local port should be 0 and mac[7:0] is 4873 * reserved. HW will set incremental 4874 * 1: single_mac - mac of the local_port 4875 * Access: RW 4876 */ 4877 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4878 4879 /* reg_ppad_local_port 4880 * port number, if single_base_mac = 0 then local_port is reserved 4881 * Access: RW 4882 */ 4883 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4884 4885 /* reg_ppad_mac 4886 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4887 * If single_base_mac = 1 - the per port MAC address 4888 * Access: RW 4889 */ 4890 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4891 4892 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4893 u16 local_port) 4894 { 4895 MLXSW_REG_ZERO(ppad, payload); 4896 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4897 mlxsw_reg_ppad_local_port_set(payload, local_port); 4898 } 4899 4900 /* PAOS - Ports Administrative and Operational Status Register 4901 * ----------------------------------------------------------- 4902 * Configures and retrieves per port administrative and operational status. 4903 */ 4904 #define MLXSW_REG_PAOS_ID 0x5006 4905 #define MLXSW_REG_PAOS_LEN 0x10 4906 4907 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4908 4909 /* reg_paos_swid 4910 * Switch partition ID with which to associate the port. 4911 * Note: while external ports uses unique local port numbers (and thus swid is 4912 * redundant), router ports use the same local port number where swid is the 4913 * only indication for the relevant port. 4914 * Access: Index 4915 */ 4916 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4917 4918 /* reg_paos_local_port 4919 * Local port number. 4920 * Access: Index 4921 */ 4922 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4923 4924 /* reg_paos_admin_status 4925 * Port administrative state (the desired state of the port): 4926 * 1 - Up. 4927 * 2 - Down. 4928 * 3 - Up once. This means that in case of link failure, the port won't go 4929 * into polling mode, but will wait to be re-enabled by software. 4930 * 4 - Disabled by system. Can only be set by hardware. 4931 * Access: RW 4932 */ 4933 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4934 4935 /* reg_paos_oper_status 4936 * Port operational state (the current state): 4937 * 1 - Up. 4938 * 2 - Down. 4939 * 3 - Down by port failure. This means that the device will not let the 4940 * port up again until explicitly specified by software. 4941 * Access: RO 4942 */ 4943 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4944 4945 /* reg_paos_ase 4946 * Admin state update enabled. 4947 * Access: WO 4948 */ 4949 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4950 4951 /* reg_paos_ee 4952 * Event update enable. If this bit is set, event generation will be 4953 * updated based on the e field. 4954 * Access: WO 4955 */ 4956 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4957 4958 /* reg_paos_e 4959 * Event generation on operational state change: 4960 * 0 - Do not generate event. 4961 * 1 - Generate Event. 4962 * 2 - Generate Single Event. 4963 * Access: RW 4964 */ 4965 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4966 4967 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4968 enum mlxsw_port_admin_status status) 4969 { 4970 MLXSW_REG_ZERO(paos, payload); 4971 mlxsw_reg_paos_swid_set(payload, 0); 4972 mlxsw_reg_paos_local_port_set(payload, local_port); 4973 mlxsw_reg_paos_admin_status_set(payload, status); 4974 mlxsw_reg_paos_oper_status_set(payload, 0); 4975 mlxsw_reg_paos_ase_set(payload, 1); 4976 mlxsw_reg_paos_ee_set(payload, 1); 4977 mlxsw_reg_paos_e_set(payload, 1); 4978 } 4979 4980 /* PFCC - Ports Flow Control Configuration Register 4981 * ------------------------------------------------ 4982 * Configures and retrieves the per port flow control configuration. 4983 */ 4984 #define MLXSW_REG_PFCC_ID 0x5007 4985 #define MLXSW_REG_PFCC_LEN 0x20 4986 4987 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4988 4989 /* reg_pfcc_local_port 4990 * Local port number. 4991 * Access: Index 4992 */ 4993 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4994 4995 /* reg_pfcc_pnat 4996 * Port number access type. Determines the way local_port is interpreted: 4997 * 0 - Local port number. 4998 * 1 - IB / label port number. 4999 * Access: Index 5000 */ 5001 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 5002 5003 /* reg_pfcc_shl_cap 5004 * Send to higher layers capabilities: 5005 * 0 - No capability of sending Pause and PFC frames to higher layers. 5006 * 1 - Device has capability of sending Pause and PFC frames to higher 5007 * layers. 5008 * Access: RO 5009 */ 5010 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 5011 5012 /* reg_pfcc_shl_opr 5013 * Send to higher layers operation: 5014 * 0 - Pause and PFC frames are handled by the port (default). 5015 * 1 - Pause and PFC frames are handled by the port and also sent to 5016 * higher layers. Only valid if shl_cap = 1. 5017 * Access: RW 5018 */ 5019 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 5020 5021 /* reg_pfcc_ppan 5022 * Pause policy auto negotiation. 5023 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 5024 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 5025 * based on the auto-negotiation resolution. 5026 * Access: RW 5027 * 5028 * Note: The auto-negotiation advertisement is set according to pptx and 5029 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 5030 */ 5031 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 5032 5033 /* reg_pfcc_prio_mask_tx 5034 * Bit per priority indicating if Tx flow control policy should be 5035 * updated based on bit pfctx. 5036 * Access: WO 5037 */ 5038 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 5039 5040 /* reg_pfcc_prio_mask_rx 5041 * Bit per priority indicating if Rx flow control policy should be 5042 * updated based on bit pfcrx. 5043 * Access: WO 5044 */ 5045 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 5046 5047 /* reg_pfcc_pptx 5048 * Admin Pause policy on Tx. 5049 * 0 - Never generate Pause frames (default). 5050 * 1 - Generate Pause frames according to Rx buffer threshold. 5051 * Access: RW 5052 */ 5053 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 5054 5055 /* reg_pfcc_aptx 5056 * Active (operational) Pause policy on Tx. 5057 * 0 - Never generate Pause frames. 5058 * 1 - Generate Pause frames according to Rx buffer threshold. 5059 * Access: RO 5060 */ 5061 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 5062 5063 /* reg_pfcc_pfctx 5064 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 5065 * 0 - Never generate priority Pause frames on the specified priority 5066 * (default). 5067 * 1 - Generate priority Pause frames according to Rx buffer threshold on 5068 * the specified priority. 5069 * Access: RW 5070 * 5071 * Note: pfctx and pptx must be mutually exclusive. 5072 */ 5073 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5074 5075 /* reg_pfcc_pprx 5076 * Admin Pause policy on Rx. 5077 * 0 - Ignore received Pause frames (default). 5078 * 1 - Respect received Pause frames. 5079 * Access: RW 5080 */ 5081 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5082 5083 /* reg_pfcc_aprx 5084 * Active (operational) Pause policy on Rx. 5085 * 0 - Ignore received Pause frames. 5086 * 1 - Respect received Pause frames. 5087 * Access: RO 5088 */ 5089 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5090 5091 /* reg_pfcc_pfcrx 5092 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5093 * 0 - Ignore incoming priority Pause frames on the specified priority 5094 * (default). 5095 * 1 - Respect incoming priority Pause frames on the specified priority. 5096 * Access: RW 5097 */ 5098 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5099 5100 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5101 5102 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5103 { 5104 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5105 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5106 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5107 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5108 } 5109 5110 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5111 { 5112 MLXSW_REG_ZERO(pfcc, payload); 5113 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5114 } 5115 5116 /* PPCNT - Ports Performance Counters Register 5117 * ------------------------------------------- 5118 * The PPCNT register retrieves per port performance counters. 5119 */ 5120 #define MLXSW_REG_PPCNT_ID 0x5008 5121 #define MLXSW_REG_PPCNT_LEN 0x100 5122 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5123 5124 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5125 5126 /* reg_ppcnt_swid 5127 * For HCA: must be always 0. 5128 * Switch partition ID to associate port with. 5129 * Switch partitions are numbered from 0 to 7 inclusively. 5130 * Switch partition 254 indicates stacking ports. 5131 * Switch partition 255 indicates all switch partitions. 5132 * Only valid on Set() operation with local_port=255. 5133 * Access: Index 5134 */ 5135 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5136 5137 /* reg_ppcnt_local_port 5138 * Local port number. 5139 * Access: Index 5140 */ 5141 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5142 5143 /* reg_ppcnt_pnat 5144 * Port number access type: 5145 * 0 - Local port number 5146 * 1 - IB port number 5147 * Access: Index 5148 */ 5149 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5150 5151 enum mlxsw_reg_ppcnt_grp { 5152 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5153 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5154 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5155 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5156 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5157 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5158 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5159 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5160 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5161 }; 5162 5163 /* reg_ppcnt_grp 5164 * Performance counter group. 5165 * Group 63 indicates all groups. Only valid on Set() operation with 5166 * clr bit set. 5167 * 0x0: IEEE 802.3 Counters 5168 * 0x1: RFC 2863 Counters 5169 * 0x2: RFC 2819 Counters 5170 * 0x3: RFC 3635 Counters 5171 * 0x5: Ethernet Extended Counters 5172 * 0x6: Ethernet Discard Counters 5173 * 0x8: Link Level Retransmission Counters 5174 * 0x10: Per Priority Counters 5175 * 0x11: Per Traffic Class Counters 5176 * 0x12: Physical Layer Counters 5177 * 0x13: Per Traffic Class Congestion Counters 5178 * Access: Index 5179 */ 5180 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5181 5182 /* reg_ppcnt_clr 5183 * Clear counters. Setting the clr bit will reset the counter value 5184 * for all counters in the counter group. This bit can be set 5185 * for both Set() and Get() operation. 5186 * Access: OP 5187 */ 5188 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5189 5190 /* reg_ppcnt_lp_gl 5191 * Local port global variable. 5192 * 0: local_port 255 = all ports of the device. 5193 * 1: local_port indicates local port number for all ports. 5194 * Access: OP 5195 */ 5196 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5197 5198 /* reg_ppcnt_prio_tc 5199 * Priority for counter set that support per priority, valid values: 0-7. 5200 * Traffic class for counter set that support per traffic class, 5201 * valid values: 0- cap_max_tclass-1 . 5202 * For HCA: cap_max_tclass is always 8. 5203 * Otherwise must be 0. 5204 * Access: Index 5205 */ 5206 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5207 5208 /* Ethernet IEEE 802.3 Counter Group */ 5209 5210 /* reg_ppcnt_a_frames_transmitted_ok 5211 * Access: RO 5212 */ 5213 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5214 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5215 5216 /* reg_ppcnt_a_frames_received_ok 5217 * Access: RO 5218 */ 5219 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5220 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5221 5222 /* reg_ppcnt_a_frame_check_sequence_errors 5223 * Access: RO 5224 */ 5225 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5226 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5227 5228 /* reg_ppcnt_a_alignment_errors 5229 * Access: RO 5230 */ 5231 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5232 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5233 5234 /* reg_ppcnt_a_octets_transmitted_ok 5235 * Access: RO 5236 */ 5237 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5238 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5239 5240 /* reg_ppcnt_a_octets_received_ok 5241 * Access: RO 5242 */ 5243 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5244 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5245 5246 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5247 * Access: RO 5248 */ 5249 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5250 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5251 5252 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5253 * Access: RO 5254 */ 5255 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5256 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5257 5258 /* reg_ppcnt_a_multicast_frames_received_ok 5259 * Access: RO 5260 */ 5261 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5262 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5263 5264 /* reg_ppcnt_a_broadcast_frames_received_ok 5265 * Access: RO 5266 */ 5267 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5268 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5269 5270 /* reg_ppcnt_a_in_range_length_errors 5271 * Access: RO 5272 */ 5273 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5274 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5275 5276 /* reg_ppcnt_a_out_of_range_length_field 5277 * Access: RO 5278 */ 5279 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5281 5282 /* reg_ppcnt_a_frame_too_long_errors 5283 * Access: RO 5284 */ 5285 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5287 5288 /* reg_ppcnt_a_symbol_error_during_carrier 5289 * Access: RO 5290 */ 5291 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5293 5294 /* reg_ppcnt_a_mac_control_frames_transmitted 5295 * Access: RO 5296 */ 5297 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5299 5300 /* reg_ppcnt_a_mac_control_frames_received 5301 * Access: RO 5302 */ 5303 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5305 5306 /* reg_ppcnt_a_unsupported_opcodes_received 5307 * Access: RO 5308 */ 5309 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5311 5312 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5313 * Access: RO 5314 */ 5315 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5317 5318 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5319 * Access: RO 5320 */ 5321 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5322 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5323 5324 /* Ethernet RFC 2863 Counter Group */ 5325 5326 /* reg_ppcnt_if_in_discards 5327 * Access: RO 5328 */ 5329 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5330 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5331 5332 /* reg_ppcnt_if_out_discards 5333 * Access: RO 5334 */ 5335 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5336 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5337 5338 /* reg_ppcnt_if_out_errors 5339 * Access: RO 5340 */ 5341 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5342 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5343 5344 /* Ethernet RFC 2819 Counter Group */ 5345 5346 /* reg_ppcnt_ether_stats_undersize_pkts 5347 * Access: RO 5348 */ 5349 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5350 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5351 5352 /* reg_ppcnt_ether_stats_oversize_pkts 5353 * Access: RO 5354 */ 5355 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5356 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5357 5358 /* reg_ppcnt_ether_stats_fragments 5359 * Access: RO 5360 */ 5361 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5362 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5363 5364 /* reg_ppcnt_ether_stats_pkts64octets 5365 * Access: RO 5366 */ 5367 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5368 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5369 5370 /* reg_ppcnt_ether_stats_pkts65to127octets 5371 * Access: RO 5372 */ 5373 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5374 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5375 5376 /* reg_ppcnt_ether_stats_pkts128to255octets 5377 * Access: RO 5378 */ 5379 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5380 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5381 5382 /* reg_ppcnt_ether_stats_pkts256to511octets 5383 * Access: RO 5384 */ 5385 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5386 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5387 5388 /* reg_ppcnt_ether_stats_pkts512to1023octets 5389 * Access: RO 5390 */ 5391 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5392 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5393 5394 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5395 * Access: RO 5396 */ 5397 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5398 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5399 5400 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5401 * Access: RO 5402 */ 5403 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5404 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5405 5406 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5407 * Access: RO 5408 */ 5409 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5410 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5411 5412 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5413 * Access: RO 5414 */ 5415 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5416 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5417 5418 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5419 * Access: RO 5420 */ 5421 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5422 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5423 5424 /* Ethernet RFC 3635 Counter Group */ 5425 5426 /* reg_ppcnt_dot3stats_fcs_errors 5427 * Access: RO 5428 */ 5429 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5430 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5431 5432 /* reg_ppcnt_dot3stats_symbol_errors 5433 * Access: RO 5434 */ 5435 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5436 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5437 5438 /* reg_ppcnt_dot3control_in_unknown_opcodes 5439 * Access: RO 5440 */ 5441 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5442 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5443 5444 /* reg_ppcnt_dot3in_pause_frames 5445 * Access: RO 5446 */ 5447 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5448 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5449 5450 /* Ethernet Extended Counter Group Counters */ 5451 5452 /* reg_ppcnt_ecn_marked 5453 * Access: RO 5454 */ 5455 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5456 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5457 5458 /* Ethernet Discard Counter Group Counters */ 5459 5460 /* reg_ppcnt_ingress_general 5461 * Access: RO 5462 */ 5463 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5464 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5465 5466 /* reg_ppcnt_ingress_policy_engine 5467 * Access: RO 5468 */ 5469 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5470 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5471 5472 /* reg_ppcnt_ingress_vlan_membership 5473 * Access: RO 5474 */ 5475 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5477 5478 /* reg_ppcnt_ingress_tag_frame_type 5479 * Access: RO 5480 */ 5481 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5482 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5483 5484 /* reg_ppcnt_egress_vlan_membership 5485 * Access: RO 5486 */ 5487 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5488 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5489 5490 /* reg_ppcnt_loopback_filter 5491 * Access: RO 5492 */ 5493 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5494 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5495 5496 /* reg_ppcnt_egress_general 5497 * Access: RO 5498 */ 5499 MLXSW_ITEM64(reg, ppcnt, egress_general, 5500 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5501 5502 /* reg_ppcnt_egress_hoq 5503 * Access: RO 5504 */ 5505 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5506 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5507 5508 /* reg_ppcnt_egress_policy_engine 5509 * Access: RO 5510 */ 5511 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5512 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5513 5514 /* reg_ppcnt_ingress_tx_link_down 5515 * Access: RO 5516 */ 5517 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5518 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5519 5520 /* reg_ppcnt_egress_stp_filter 5521 * Access: RO 5522 */ 5523 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5524 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5525 5526 /* reg_ppcnt_egress_sll 5527 * Access: RO 5528 */ 5529 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5530 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5531 5532 /* Ethernet Per Priority Group Counters */ 5533 5534 /* reg_ppcnt_rx_octets 5535 * Access: RO 5536 */ 5537 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5538 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5539 5540 /* reg_ppcnt_rx_frames 5541 * Access: RO 5542 */ 5543 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5544 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5545 5546 /* reg_ppcnt_tx_octets 5547 * Access: RO 5548 */ 5549 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5550 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5551 5552 /* reg_ppcnt_tx_frames 5553 * Access: RO 5554 */ 5555 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5556 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5557 5558 /* reg_ppcnt_rx_pause 5559 * Access: RO 5560 */ 5561 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5562 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5563 5564 /* reg_ppcnt_rx_pause_duration 5565 * Access: RO 5566 */ 5567 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5568 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5569 5570 /* reg_ppcnt_tx_pause 5571 * Access: RO 5572 */ 5573 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5574 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5575 5576 /* reg_ppcnt_tx_pause_duration 5577 * Access: RO 5578 */ 5579 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5580 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5581 5582 /* reg_ppcnt_rx_pause_transition 5583 * Access: RO 5584 */ 5585 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5586 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5587 5588 /* Ethernet Per Traffic Class Counters */ 5589 5590 /* reg_ppcnt_tc_transmit_queue 5591 * Contains the transmit queue depth in cells of traffic class 5592 * selected by prio_tc and the port selected by local_port. 5593 * The field cannot be cleared. 5594 * Access: RO 5595 */ 5596 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5597 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5598 5599 /* reg_ppcnt_tc_no_buffer_discard_uc 5600 * The number of unicast packets dropped due to lack of shared 5601 * buffer resources. 5602 * Access: RO 5603 */ 5604 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5605 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5606 5607 /* Ethernet Per Traffic Class Congestion Group Counters */ 5608 5609 /* reg_ppcnt_wred_discard 5610 * Access: RO 5611 */ 5612 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5613 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5614 5615 /* reg_ppcnt_ecn_marked_tc 5616 * Access: RO 5617 */ 5618 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5619 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5620 5621 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5622 enum mlxsw_reg_ppcnt_grp grp, 5623 u8 prio_tc) 5624 { 5625 MLXSW_REG_ZERO(ppcnt, payload); 5626 mlxsw_reg_ppcnt_swid_set(payload, 0); 5627 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5628 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5629 mlxsw_reg_ppcnt_grp_set(payload, grp); 5630 mlxsw_reg_ppcnt_clr_set(payload, 0); 5631 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5632 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5633 } 5634 5635 /* PPTB - Port Prio To Buffer Register 5636 * ----------------------------------- 5637 * Configures the switch priority to buffer table. 5638 */ 5639 #define MLXSW_REG_PPTB_ID 0x500B 5640 #define MLXSW_REG_PPTB_LEN 0x10 5641 5642 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5643 5644 enum { 5645 MLXSW_REG_PPTB_MM_UM, 5646 MLXSW_REG_PPTB_MM_UNICAST, 5647 MLXSW_REG_PPTB_MM_MULTICAST, 5648 }; 5649 5650 /* reg_pptb_mm 5651 * Mapping mode. 5652 * 0 - Map both unicast and multicast packets to the same buffer. 5653 * 1 - Map only unicast packets. 5654 * 2 - Map only multicast packets. 5655 * Access: Index 5656 * 5657 * Note: SwitchX-2 only supports the first option. 5658 */ 5659 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5660 5661 /* reg_pptb_local_port 5662 * Local port number. 5663 * Access: Index 5664 */ 5665 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5666 5667 /* reg_pptb_um 5668 * Enables the update of the untagged_buf field. 5669 * Access: RW 5670 */ 5671 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5672 5673 /* reg_pptb_pm 5674 * Enables the update of the prio_to_buff field. 5675 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5676 * Access: RW 5677 */ 5678 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5679 5680 /* reg_pptb_prio_to_buff 5681 * Mapping of switch priority <i> to one of the allocated receive port 5682 * buffers. 5683 * Access: RW 5684 */ 5685 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5686 5687 /* reg_pptb_pm_msb 5688 * Enables the update of the prio_to_buff field. 5689 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5690 * Access: RW 5691 */ 5692 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5693 5694 /* reg_pptb_untagged_buff 5695 * Mapping of untagged frames to one of the allocated receive port buffers. 5696 * Access: RW 5697 * 5698 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5699 * Spectrum, as it maps untagged packets based on the default switch priority. 5700 */ 5701 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5702 5703 /* reg_pptb_prio_to_buff_msb 5704 * Mapping of switch priority <i+8> to one of the allocated receive port 5705 * buffers. 5706 * Access: RW 5707 */ 5708 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5709 5710 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5711 5712 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5713 { 5714 MLXSW_REG_ZERO(pptb, payload); 5715 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5716 mlxsw_reg_pptb_local_port_set(payload, local_port); 5717 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5718 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5719 } 5720 5721 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5722 u8 buff) 5723 { 5724 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5725 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5726 } 5727 5728 /* PBMC - Port Buffer Management Control Register 5729 * ---------------------------------------------- 5730 * The PBMC register configures and retrieves the port packet buffer 5731 * allocation for different Prios, and the Pause threshold management. 5732 */ 5733 #define MLXSW_REG_PBMC_ID 0x500C 5734 #define MLXSW_REG_PBMC_LEN 0x6C 5735 5736 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5737 5738 /* reg_pbmc_local_port 5739 * Local port number. 5740 * Access: Index 5741 */ 5742 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5743 5744 /* reg_pbmc_xoff_timer_value 5745 * When device generates a pause frame, it uses this value as the pause 5746 * timer (time for the peer port to pause in quota-512 bit time). 5747 * Access: RW 5748 */ 5749 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5750 5751 /* reg_pbmc_xoff_refresh 5752 * The time before a new pause frame should be sent to refresh the pause RW 5753 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5754 * time). 5755 * Access: RW 5756 */ 5757 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5758 5759 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5760 5761 /* reg_pbmc_buf_lossy 5762 * The field indicates if the buffer is lossy. 5763 * 0 - Lossless 5764 * 1 - Lossy 5765 * Access: RW 5766 */ 5767 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5768 5769 /* reg_pbmc_buf_epsb 5770 * Eligible for Port Shared buffer. 5771 * If epsb is set, packets assigned to buffer are allowed to insert the port 5772 * shared buffer. 5773 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5774 * Access: RW 5775 */ 5776 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5777 5778 /* reg_pbmc_buf_size 5779 * The part of the packet buffer array is allocated for the specific buffer. 5780 * Units are represented in cells. 5781 * Access: RW 5782 */ 5783 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5784 5785 /* reg_pbmc_buf_xoff_threshold 5786 * Once the amount of data in the buffer goes above this value, device 5787 * starts sending PFC frames for all priorities associated with the 5788 * buffer. Units are represented in cells. Reserved in case of lossy 5789 * buffer. 5790 * Access: RW 5791 * 5792 * Note: In Spectrum, reserved for buffer[9]. 5793 */ 5794 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5795 0x08, 0x04, false); 5796 5797 /* reg_pbmc_buf_xon_threshold 5798 * When the amount of data in the buffer goes below this value, device 5799 * stops sending PFC frames for the priorities associated with the 5800 * buffer. Units are represented in cells. Reserved in case of lossy 5801 * buffer. 5802 * Access: RW 5803 * 5804 * Note: In Spectrum, reserved for buffer[9]. 5805 */ 5806 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5807 0x08, 0x04, false); 5808 5809 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5810 u16 xoff_timer_value, u16 xoff_refresh) 5811 { 5812 MLXSW_REG_ZERO(pbmc, payload); 5813 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5814 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5815 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5816 } 5817 5818 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5819 int buf_index, 5820 u16 size) 5821 { 5822 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5823 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5824 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5825 } 5826 5827 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5828 int buf_index, u16 size, 5829 u16 threshold) 5830 { 5831 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5832 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5833 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5834 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5835 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5836 } 5837 5838 /* PSPA - Port Switch Partition Allocation 5839 * --------------------------------------- 5840 * Controls the association of a port with a switch partition and enables 5841 * configuring ports as stacking ports. 5842 */ 5843 #define MLXSW_REG_PSPA_ID 0x500D 5844 #define MLXSW_REG_PSPA_LEN 0x8 5845 5846 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5847 5848 /* reg_pspa_swid 5849 * Switch partition ID. 5850 * Access: RW 5851 */ 5852 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5853 5854 /* reg_pspa_local_port 5855 * Local port number. 5856 * Access: Index 5857 */ 5858 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5859 5860 /* reg_pspa_sub_port 5861 * Virtual port within the local port. Set to 0 when virtual ports are 5862 * disabled on the local port. 5863 * Access: Index 5864 */ 5865 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5866 5867 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5868 { 5869 MLXSW_REG_ZERO(pspa, payload); 5870 mlxsw_reg_pspa_swid_set(payload, swid); 5871 mlxsw_reg_pspa_local_port_set(payload, local_port); 5872 mlxsw_reg_pspa_sub_port_set(payload, 0); 5873 } 5874 5875 /* PMAOS - Ports Module Administrative and Operational Status 5876 * ---------------------------------------------------------- 5877 * This register configures and retrieves the per module status. 5878 */ 5879 #define MLXSW_REG_PMAOS_ID 0x5012 5880 #define MLXSW_REG_PMAOS_LEN 0x10 5881 5882 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5883 5884 /* reg_pmaos_rst 5885 * Module reset toggle. 5886 * Note: Setting reset while module is plugged-in will result in transition to 5887 * "initializing" operational state. 5888 * Access: OP 5889 */ 5890 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5891 5892 /* reg_pmaos_slot_index 5893 * Slot index. 5894 * Access: Index 5895 */ 5896 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5897 5898 /* reg_pmaos_module 5899 * Module number. 5900 * Access: Index 5901 */ 5902 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5903 5904 enum mlxsw_reg_pmaos_admin_status { 5905 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5906 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5907 /* If the module is active and then unplugged, or experienced an error 5908 * event, the operational status should go to "disabled" and can only 5909 * be enabled upon explicit enable command. 5910 */ 5911 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5912 }; 5913 5914 /* reg_pmaos_admin_status 5915 * Module administrative state (the desired state of the module). 5916 * Note: To disable a module, all ports associated with the port must be 5917 * administatively down first. 5918 * Access: RW 5919 */ 5920 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5921 5922 /* reg_pmaos_ase 5923 * Admin state update enable. 5924 * If this bit is set, admin state will be updated based on admin_state field. 5925 * Only relevant on Set() operations. 5926 * Access: WO 5927 */ 5928 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5929 5930 /* reg_pmaos_ee 5931 * Event update enable. 5932 * If this bit is set, event generation will be updated based on the e field. 5933 * Only relevant on Set operations. 5934 * Access: WO 5935 */ 5936 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5937 5938 enum mlxsw_reg_pmaos_e { 5939 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5940 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5941 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5942 }; 5943 5944 /* reg_pmaos_e 5945 * Event Generation on operational state change. 5946 * Access: RW 5947 */ 5948 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5949 5950 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5951 { 5952 MLXSW_REG_ZERO(pmaos, payload); 5953 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5954 mlxsw_reg_pmaos_module_set(payload, module); 5955 } 5956 5957 /* PPLR - Port Physical Loopback Register 5958 * -------------------------------------- 5959 * This register allows configuration of the port's loopback mode. 5960 */ 5961 #define MLXSW_REG_PPLR_ID 0x5018 5962 #define MLXSW_REG_PPLR_LEN 0x8 5963 5964 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5965 5966 /* reg_pplr_local_port 5967 * Local port number. 5968 * Access: Index 5969 */ 5970 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5971 5972 /* Phy local loopback. When set the port's egress traffic is looped back 5973 * to the receiver and the port transmitter is disabled. 5974 */ 5975 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5976 5977 /* reg_pplr_lb_en 5978 * Loopback enable. 5979 * Access: RW 5980 */ 5981 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5982 5983 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5984 bool phy_local) 5985 { 5986 MLXSW_REG_ZERO(pplr, payload); 5987 mlxsw_reg_pplr_local_port_set(payload, local_port); 5988 mlxsw_reg_pplr_lb_en_set(payload, 5989 phy_local ? 5990 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5991 } 5992 5993 /* PMTDB - Port Module To local DataBase Register 5994 * ---------------------------------------------- 5995 * The PMTDB register allows to query the possible module<->local port 5996 * mapping than can be used in PMLP. It does not represent the actual/current 5997 * mapping of the local to module. Actual mapping is only defined by PMLP. 5998 */ 5999 #define MLXSW_REG_PMTDB_ID 0x501A 6000 #define MLXSW_REG_PMTDB_LEN 0x40 6001 6002 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 6003 6004 /* reg_pmtdb_slot_index 6005 * Slot index (0: Main board). 6006 * Access: Index 6007 */ 6008 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 6009 6010 /* reg_pmtdb_module 6011 * Module number. 6012 * Access: Index 6013 */ 6014 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 6015 6016 /* reg_pmtdb_ports_width 6017 * Port's width 6018 * Access: Index 6019 */ 6020 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 6021 6022 /* reg_pmtdb_num_ports 6023 * Number of ports in a single module (split/breakout) 6024 * Access: Index 6025 */ 6026 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 6027 6028 enum mlxsw_reg_pmtdb_status { 6029 MLXSW_REG_PMTDB_STATUS_SUCCESS, 6030 }; 6031 6032 /* reg_pmtdb_status 6033 * Status 6034 * Access: RO 6035 */ 6036 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 6037 6038 /* reg_pmtdb_port_num 6039 * The local_port value which can be assigned to the module. 6040 * In case of more than one port, port<x> represent the /<x> port of 6041 * the module. 6042 * Access: RO 6043 */ 6044 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 6045 6046 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 6047 u8 ports_width, u8 num_ports) 6048 { 6049 MLXSW_REG_ZERO(pmtdb, payload); 6050 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 6051 mlxsw_reg_pmtdb_module_set(payload, module); 6052 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 6053 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 6054 } 6055 6056 /* PMECR - Ports Mapping Event Configuration Register 6057 * -------------------------------------------------- 6058 * The PMECR register is used to enable/disable event triggering 6059 * in case of local port mapping change. 6060 */ 6061 #define MLXSW_REG_PMECR_ID 0x501B 6062 #define MLXSW_REG_PMECR_LEN 0x20 6063 6064 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 6065 6066 /* reg_pmecr_local_port 6067 * Local port number. 6068 * Access: Index 6069 */ 6070 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 6071 6072 /* reg_pmecr_ee 6073 * Event update enable. If this bit is set, event generation will be updated 6074 * based on the e field. Only relevant on Set operations. 6075 * Access: WO 6076 */ 6077 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6078 6079 /* reg_pmecr_eswi 6080 * Software ignore enable bit. If this bit is set, the value of swi is used. 6081 * If this bit is clear, the value of swi is ignored. 6082 * Only relevant on Set operations. 6083 * Access: WO 6084 */ 6085 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6086 6087 /* reg_pmecr_swi 6088 * Software ignore. If this bit is set, the device shouldn't generate events 6089 * in case of PMLP SET operation but only upon self local port mapping change 6090 * (if applicable according to e configuration). This is supplementary 6091 * configuration on top of e value. 6092 * Access: RW 6093 */ 6094 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6095 6096 enum mlxsw_reg_pmecr_e { 6097 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6098 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6099 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6100 }; 6101 6102 /* reg_pmecr_e 6103 * Event generation on local port mapping change. 6104 * Access: RW 6105 */ 6106 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6107 6108 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6109 enum mlxsw_reg_pmecr_e e) 6110 { 6111 MLXSW_REG_ZERO(pmecr, payload); 6112 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6113 mlxsw_reg_pmecr_e_set(payload, e); 6114 mlxsw_reg_pmecr_ee_set(payload, true); 6115 mlxsw_reg_pmecr_swi_set(payload, true); 6116 mlxsw_reg_pmecr_eswi_set(payload, true); 6117 } 6118 6119 /* PMPE - Port Module Plug/Unplug Event Register 6120 * --------------------------------------------- 6121 * This register reports any operational status change of a module. 6122 * A change in the module’s state will generate an event only if the change 6123 * happens after arming the event mechanism. Any changes to the module state 6124 * while the event mechanism is not armed will not be reported. Software can 6125 * query the PMPE register for module status. 6126 */ 6127 #define MLXSW_REG_PMPE_ID 0x5024 6128 #define MLXSW_REG_PMPE_LEN 0x10 6129 6130 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6131 6132 /* reg_pmpe_slot_index 6133 * Slot index. 6134 * Access: Index 6135 */ 6136 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6137 6138 /* reg_pmpe_module 6139 * Module number. 6140 * Access: Index 6141 */ 6142 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6143 6144 enum mlxsw_reg_pmpe_module_status { 6145 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6146 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6147 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6148 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6149 }; 6150 6151 /* reg_pmpe_module_status 6152 * Module status. 6153 * Access: RO 6154 */ 6155 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6156 6157 /* reg_pmpe_error_type 6158 * Module error details. 6159 * Access: RO 6160 */ 6161 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6162 6163 /* PDDR - Port Diagnostics Database Register 6164 * ----------------------------------------- 6165 * The PDDR enables to read the Phy debug database 6166 */ 6167 #define MLXSW_REG_PDDR_ID 0x5031 6168 #define MLXSW_REG_PDDR_LEN 0x100 6169 6170 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6171 6172 /* reg_pddr_local_port 6173 * Local port number. 6174 * Access: Index 6175 */ 6176 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6177 6178 enum mlxsw_reg_pddr_page_select { 6179 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6180 }; 6181 6182 /* reg_pddr_page_select 6183 * Page select index. 6184 * Access: Index 6185 */ 6186 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6187 6188 enum mlxsw_reg_pddr_trblsh_group_opcode { 6189 /* Monitor opcodes */ 6190 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6191 }; 6192 6193 /* reg_pddr_group_opcode 6194 * Group selector. 6195 * Access: Index 6196 */ 6197 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6198 6199 /* reg_pddr_status_opcode 6200 * Group selector. 6201 * Access: RO 6202 */ 6203 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6204 6205 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6206 u8 page_select) 6207 { 6208 MLXSW_REG_ZERO(pddr, payload); 6209 mlxsw_reg_pddr_local_port_set(payload, local_port); 6210 mlxsw_reg_pddr_page_select_set(payload, page_select); 6211 } 6212 6213 /* PMMP - Port Module Memory Map Properties Register 6214 * ------------------------------------------------- 6215 * The PMMP register allows to override the module memory map advertisement. 6216 * The register can only be set when the module is disabled by PMAOS register. 6217 */ 6218 #define MLXSW_REG_PMMP_ID 0x5044 6219 #define MLXSW_REG_PMMP_LEN 0x2C 6220 6221 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6222 6223 /* reg_pmmp_module 6224 * Module number. 6225 * Access: Index 6226 */ 6227 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6228 6229 /* reg_pmmp_slot_index 6230 * Slot index. 6231 * Access: Index 6232 */ 6233 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6234 6235 /* reg_pmmp_sticky 6236 * When set, will keep eeprom_override values after plug-out event. 6237 * Access: OP 6238 */ 6239 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6240 6241 /* reg_pmmp_eeprom_override_mask 6242 * Write mask bit (negative polarity). 6243 * 0 - Allow write 6244 * 1 - Ignore write 6245 * On write, indicates which of the bits from eeprom_override field are 6246 * updated. 6247 * Access: WO 6248 */ 6249 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6250 6251 enum { 6252 /* Set module to low power mode */ 6253 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6254 }; 6255 6256 /* reg_pmmp_eeprom_override 6257 * Override / ignore EEPROM advertisement properties bitmask 6258 * Access: RW 6259 */ 6260 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6261 6262 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6263 { 6264 MLXSW_REG_ZERO(pmmp, payload); 6265 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6266 mlxsw_reg_pmmp_module_set(payload, module); 6267 } 6268 6269 /* PLLP - Port Local port to Label Port mapping Register 6270 * ----------------------------------------------------- 6271 * The PLLP register returns the mapping from Local Port into Label Port. 6272 */ 6273 #define MLXSW_REG_PLLP_ID 0x504A 6274 #define MLXSW_REG_PLLP_LEN 0x10 6275 6276 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6277 6278 /* reg_pllp_local_port 6279 * Local port number. 6280 * Access: Index 6281 */ 6282 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6283 6284 /* reg_pllp_label_port 6285 * Front panel label of the port. 6286 * Access: RO 6287 */ 6288 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6289 6290 /* reg_pllp_split_num 6291 * Label split mapping for local_port. 6292 * Access: RO 6293 */ 6294 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6295 6296 /* reg_pllp_slot_index 6297 * Slot index (0: Main board). 6298 * Access: RO 6299 */ 6300 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6301 6302 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6303 { 6304 MLXSW_REG_ZERO(pllp, payload); 6305 mlxsw_reg_pllp_local_port_set(payload, local_port); 6306 } 6307 6308 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6309 u8 *split_num, u8 *slot_index) 6310 { 6311 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6312 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6313 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6314 } 6315 6316 /* PMTM - Port Module Type Mapping Register 6317 * ---------------------------------------- 6318 * The PMTM register allows query or configuration of module types. 6319 * The register can only be set when the module is disabled by PMAOS register 6320 */ 6321 #define MLXSW_REG_PMTM_ID 0x5067 6322 #define MLXSW_REG_PMTM_LEN 0x10 6323 6324 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6325 6326 /* reg_pmtm_slot_index 6327 * Slot index. 6328 * Access: Index 6329 */ 6330 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6331 6332 /* reg_pmtm_module 6333 * Module number. 6334 * Access: Index 6335 */ 6336 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6337 6338 enum mlxsw_reg_pmtm_module_type { 6339 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6340 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6341 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6342 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6343 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6344 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6345 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6346 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6347 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6348 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6349 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6350 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6351 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6352 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6353 }; 6354 6355 /* reg_pmtm_module_type 6356 * Module type. 6357 * Access: RW 6358 */ 6359 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6360 6361 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6362 { 6363 MLXSW_REG_ZERO(pmtm, payload); 6364 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6365 mlxsw_reg_pmtm_module_set(payload, module); 6366 } 6367 6368 /* HTGT - Host Trap Group Table 6369 * ---------------------------- 6370 * Configures the properties for forwarding to CPU. 6371 */ 6372 #define MLXSW_REG_HTGT_ID 0x7002 6373 #define MLXSW_REG_HTGT_LEN 0x20 6374 6375 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6376 6377 /* reg_htgt_swid 6378 * Switch partition ID. 6379 * Access: Index 6380 */ 6381 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6382 6383 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6384 6385 /* reg_htgt_type 6386 * CPU path type. 6387 * Access: RW 6388 */ 6389 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6390 6391 enum mlxsw_reg_htgt_trap_group { 6392 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6393 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6394 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6395 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6396 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6397 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6398 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6399 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6400 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6401 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6402 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6403 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6404 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6405 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6406 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6407 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6408 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6409 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6410 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6411 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6412 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6413 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6414 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6415 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6416 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6417 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6418 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6419 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6420 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6421 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6422 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6423 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6424 MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL, 6425 6426 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6427 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6428 }; 6429 6430 /* reg_htgt_trap_group 6431 * Trap group number. User defined number specifying which trap groups 6432 * should be forwarded to the CPU. The mapping between trap IDs and trap 6433 * groups is configured using HPKT register. 6434 * Access: Index 6435 */ 6436 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6437 6438 enum { 6439 MLXSW_REG_HTGT_POLICER_DISABLE, 6440 MLXSW_REG_HTGT_POLICER_ENABLE, 6441 }; 6442 6443 /* reg_htgt_pide 6444 * Enable policer ID specified using 'pid' field. 6445 * Access: RW 6446 */ 6447 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6448 6449 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6450 6451 /* reg_htgt_pid 6452 * Policer ID for the trap group. 6453 * Access: RW 6454 */ 6455 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6456 6457 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6458 6459 /* reg_htgt_mirror_action 6460 * Mirror action to use. 6461 * 0 - Trap to CPU. 6462 * 1 - Trap to CPU and mirror to a mirroring agent. 6463 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6464 * Access: RW 6465 * 6466 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6467 */ 6468 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6469 6470 /* reg_htgt_mirroring_agent 6471 * Mirroring agent. 6472 * Access: RW 6473 */ 6474 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6475 6476 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6477 6478 /* reg_htgt_priority 6479 * Trap group priority. 6480 * In case a packet matches multiple classification rules, the packet will 6481 * only be trapped once, based on the trap ID associated with the group (via 6482 * register HPKT) with the highest priority. 6483 * Supported values are 0-7, with 7 represnting the highest priority. 6484 * Access: RW 6485 * 6486 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6487 * by the 'trap_group' field. 6488 */ 6489 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6490 6491 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6492 6493 /* reg_htgt_local_path_cpu_tclass 6494 * CPU ingress traffic class for the trap group. 6495 * Access: RW 6496 */ 6497 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6498 6499 enum mlxsw_reg_htgt_local_path_rdq { 6500 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6501 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6502 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6503 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6504 }; 6505 /* reg_htgt_local_path_rdq 6506 * Receive descriptor queue (RDQ) to use for the trap group. 6507 * Access: RW 6508 */ 6509 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6510 6511 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6512 u8 priority, u8 tc) 6513 { 6514 MLXSW_REG_ZERO(htgt, payload); 6515 6516 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6517 mlxsw_reg_htgt_pide_set(payload, 6518 MLXSW_REG_HTGT_POLICER_DISABLE); 6519 } else { 6520 mlxsw_reg_htgt_pide_set(payload, 6521 MLXSW_REG_HTGT_POLICER_ENABLE); 6522 mlxsw_reg_htgt_pid_set(payload, policer_id); 6523 } 6524 6525 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6526 mlxsw_reg_htgt_trap_group_set(payload, group); 6527 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6528 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6529 mlxsw_reg_htgt_priority_set(payload, priority); 6530 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6531 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6532 } 6533 6534 /* HPKT - Host Packet Trap 6535 * ----------------------- 6536 * Configures trap IDs inside trap groups. 6537 */ 6538 #define MLXSW_REG_HPKT_ID 0x7003 6539 #define MLXSW_REG_HPKT_LEN 0x10 6540 6541 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6542 6543 enum { 6544 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6545 MLXSW_REG_HPKT_ACK_REQUIRED, 6546 }; 6547 6548 /* reg_hpkt_ack 6549 * Require acknowledgements from the host for events. 6550 * If set, then the device will wait for the event it sent to be acknowledged 6551 * by the host. This option is only relevant for event trap IDs. 6552 * Access: RW 6553 * 6554 * Note: Currently not supported by firmware. 6555 */ 6556 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6557 6558 enum mlxsw_reg_hpkt_action { 6559 MLXSW_REG_HPKT_ACTION_FORWARD, 6560 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6561 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6562 MLXSW_REG_HPKT_ACTION_DISCARD, 6563 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6564 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6565 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6566 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6567 }; 6568 6569 /* reg_hpkt_action 6570 * Action to perform on packet when trapped. 6571 * 0 - No action. Forward to CPU based on switching rules. 6572 * 1 - Trap to CPU (CPU receives sole copy). 6573 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6574 * 3 - Discard. 6575 * 4 - Soft discard (allow other traps to act on the packet). 6576 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6577 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6578 * 15 - Restore the firmware's default action. 6579 * Access: RW 6580 * 6581 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6582 * addressed to the CPU. 6583 */ 6584 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6585 6586 /* reg_hpkt_trap_group 6587 * Trap group to associate the trap with. 6588 * Access: RW 6589 */ 6590 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6591 6592 /* reg_hpkt_trap_id 6593 * Trap ID. 6594 * Access: Index 6595 * 6596 * Note: A trap ID can only be associated with a single trap group. The device 6597 * will associate the trap ID with the last trap group configured. 6598 */ 6599 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6600 6601 enum { 6602 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6603 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6604 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6605 }; 6606 6607 /* reg_hpkt_ctrl 6608 * Configure dedicated buffer resources for control packets. 6609 * Ignored by SwitchX-2. 6610 * 0 - Keep factory defaults. 6611 * 1 - Do not use control buffer for this trap ID. 6612 * 2 - Use control buffer for this trap ID. 6613 * Access: RW 6614 */ 6615 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6616 6617 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6618 enum mlxsw_reg_htgt_trap_group trap_group, 6619 bool is_ctrl) 6620 { 6621 MLXSW_REG_ZERO(hpkt, payload); 6622 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6623 mlxsw_reg_hpkt_action_set(payload, action); 6624 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6625 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6626 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6627 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6628 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6629 } 6630 6631 /* RGCR - Router General Configuration Register 6632 * -------------------------------------------- 6633 * The register is used for setting up the router configuration. 6634 */ 6635 #define MLXSW_REG_RGCR_ID 0x8001 6636 #define MLXSW_REG_RGCR_LEN 0x28 6637 6638 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6639 6640 /* reg_rgcr_ipv4_en 6641 * IPv4 router enable. 6642 * Access: RW 6643 */ 6644 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6645 6646 /* reg_rgcr_ipv6_en 6647 * IPv6 router enable. 6648 * Access: RW 6649 */ 6650 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6651 6652 /* reg_rgcr_max_router_interfaces 6653 * Defines the maximum number of active router interfaces for all virtual 6654 * routers. 6655 * Access: RW 6656 */ 6657 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6658 6659 /* reg_rgcr_usp 6660 * Update switch priority and packet color. 6661 * 0 - Preserve the value of Switch Priority and packet color. 6662 * 1 - Recalculate the value of Switch Priority and packet color. 6663 * Access: RW 6664 * 6665 * Note: Not supported by SwitchX and SwitchX-2. 6666 */ 6667 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6668 6669 /* reg_rgcr_pcp_rw 6670 * Indicates how to handle the pcp_rewrite_en value: 6671 * 0 - Preserve the value of pcp_rewrite_en. 6672 * 2 - Disable PCP rewrite. 6673 * 3 - Enable PCP rewrite. 6674 * Access: RW 6675 * 6676 * Note: Not supported by SwitchX and SwitchX-2. 6677 */ 6678 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6679 6680 /* reg_rgcr_activity_dis 6681 * Activity disable: 6682 * 0 - Activity will be set when an entry is hit (default). 6683 * 1 - Activity will not be set when an entry is hit. 6684 * 6685 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6686 * (RALUE). 6687 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6688 * Entry (RAUHT). 6689 * Bits 2:7 are reserved. 6690 * Access: RW 6691 * 6692 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6693 */ 6694 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6695 6696 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6697 bool ipv6_en) 6698 { 6699 MLXSW_REG_ZERO(rgcr, payload); 6700 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6701 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6702 } 6703 6704 /* RITR - Router Interface Table Register 6705 * -------------------------------------- 6706 * The register is used to configure the router interface table. 6707 */ 6708 #define MLXSW_REG_RITR_ID 0x8002 6709 #define MLXSW_REG_RITR_LEN 0x40 6710 6711 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6712 6713 /* reg_ritr_enable 6714 * Enables routing on the router interface. 6715 * Access: RW 6716 */ 6717 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6718 6719 /* reg_ritr_ipv4 6720 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6721 * interface. 6722 * Access: RW 6723 */ 6724 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6725 6726 /* reg_ritr_ipv6 6727 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6728 * interface. 6729 * Access: RW 6730 */ 6731 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6732 6733 /* reg_ritr_ipv4_mc 6734 * IPv4 multicast routing enable. 6735 * Access: RW 6736 */ 6737 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6738 6739 /* reg_ritr_ipv6_mc 6740 * IPv6 multicast routing enable. 6741 * Access: RW 6742 */ 6743 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6744 6745 enum mlxsw_reg_ritr_if_type { 6746 /* VLAN interface. */ 6747 MLXSW_REG_RITR_VLAN_IF, 6748 /* FID interface. */ 6749 MLXSW_REG_RITR_FID_IF, 6750 /* Sub-port interface. */ 6751 MLXSW_REG_RITR_SP_IF, 6752 /* Loopback Interface. */ 6753 MLXSW_REG_RITR_LOOPBACK_IF, 6754 }; 6755 6756 /* reg_ritr_type 6757 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6758 * Access: RW 6759 */ 6760 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6761 6762 enum { 6763 MLXSW_REG_RITR_RIF_CREATE, 6764 MLXSW_REG_RITR_RIF_DEL, 6765 }; 6766 6767 /* reg_ritr_op 6768 * Opcode: 6769 * 0 - Create or edit RIF. 6770 * 1 - Delete RIF. 6771 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6772 * is not supported. An interface must be deleted and re-created in order 6773 * to update properties. 6774 * Access: WO 6775 */ 6776 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6777 6778 /* reg_ritr_rif 6779 * Router interface index. A pointer to the Router Interface Table. 6780 * Access: Index 6781 */ 6782 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6783 6784 /* reg_ritr_ipv4_fe 6785 * IPv4 Forwarding Enable. 6786 * Enables routing of IPv4 traffic on the router interface. When disabled, 6787 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6788 * Not supported in SwitchX-2. 6789 * Access: RW 6790 */ 6791 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6792 6793 /* reg_ritr_ipv6_fe 6794 * IPv6 Forwarding Enable. 6795 * Enables routing of IPv6 traffic on the router interface. When disabled, 6796 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6797 * Not supported in SwitchX-2. 6798 * Access: RW 6799 */ 6800 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6801 6802 /* reg_ritr_ipv4_mc_fe 6803 * IPv4 Multicast Forwarding Enable. 6804 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6805 * will be enabled. 6806 * Access: RW 6807 */ 6808 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6809 6810 /* reg_ritr_ipv6_mc_fe 6811 * IPv6 Multicast Forwarding Enable. 6812 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6813 * will be enabled. 6814 * Access: RW 6815 */ 6816 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6817 6818 /* reg_ritr_lb_en 6819 * Loop-back filter enable for unicast packets. 6820 * If the flag is set then loop-back filter for unicast packets is 6821 * implemented on the RIF. Multicast packets are always subject to 6822 * loop-back filtering. 6823 * Access: RW 6824 */ 6825 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6826 6827 /* reg_ritr_virtual_router 6828 * Virtual router ID associated with the router interface. 6829 * Access: RW 6830 */ 6831 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6832 6833 /* reg_ritr_mtu 6834 * Router interface MTU. 6835 * Access: RW 6836 */ 6837 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6838 6839 /* reg_ritr_if_swid 6840 * Switch partition ID. 6841 * Access: RW 6842 */ 6843 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6844 6845 /* reg_ritr_if_mac_profile_id 6846 * MAC msb profile ID. 6847 * Access: RW 6848 */ 6849 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6850 6851 /* reg_ritr_if_mac 6852 * Router interface MAC address. 6853 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6854 * Access: RW 6855 */ 6856 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6857 6858 /* reg_ritr_if_vrrp_id_ipv6 6859 * VRRP ID for IPv6 6860 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6861 * Access: RW 6862 */ 6863 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6864 6865 /* reg_ritr_if_vrrp_id_ipv4 6866 * VRRP ID for IPv4 6867 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6868 * Access: RW 6869 */ 6870 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6871 6872 /* VLAN Interface */ 6873 6874 /* reg_ritr_vlan_if_vlan_id 6875 * VLAN ID. 6876 * Access: RW 6877 */ 6878 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6879 6880 /* reg_ritr_vlan_if_efid 6881 * Egress FID. 6882 * Used to connect the RIF to a bridge. 6883 * Access: RW 6884 * 6885 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6886 */ 6887 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6888 6889 /* FID Interface */ 6890 6891 /* reg_ritr_fid_if_fid 6892 * Filtering ID. Used to connect a bridge to the router. 6893 * When legacy bridge model is used, only FIDs from the vFID range are 6894 * supported. When unified bridge model is used, this is the egress FID for 6895 * router to bridge. 6896 * Access: RW 6897 */ 6898 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6899 6900 /* Sub-port Interface */ 6901 6902 /* reg_ritr_sp_if_lag 6903 * LAG indication. When this bit is set the system_port field holds the 6904 * LAG identifier. 6905 * Access: RW 6906 */ 6907 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6908 6909 /* reg_ritr_sp_system_port 6910 * Port unique indentifier. When lag bit is set, this field holds the 6911 * lag_id in bits 0:9. 6912 * Access: RW 6913 */ 6914 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6915 6916 /* reg_ritr_sp_if_efid 6917 * Egress filtering ID. 6918 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6919 * the VID. 6920 * Access: RW 6921 * 6922 * Note: Reserved when legacy bridge model is used. 6923 */ 6924 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6925 6926 /* reg_ritr_sp_if_vid 6927 * VLAN ID. 6928 * Access: RW 6929 */ 6930 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6931 6932 /* Loopback Interface */ 6933 6934 enum mlxsw_reg_ritr_loopback_protocol { 6935 /* IPinIP IPv4 underlay Unicast */ 6936 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6937 /* IPinIP IPv6 underlay Unicast */ 6938 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6939 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6940 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6941 }; 6942 6943 /* reg_ritr_loopback_protocol 6944 * Access: RW 6945 */ 6946 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6947 6948 enum mlxsw_reg_ritr_loopback_ipip_type { 6949 /* Tunnel is IPinIP. */ 6950 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6951 /* Tunnel is GRE, no key. */ 6952 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6953 /* Tunnel is GRE, with a key. */ 6954 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6955 }; 6956 6957 /* reg_ritr_loopback_ipip_type 6958 * Encapsulation type. 6959 * Access: RW 6960 */ 6961 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6962 6963 enum mlxsw_reg_ritr_loopback_ipip_options { 6964 /* The key is defined by gre_key. */ 6965 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6966 }; 6967 6968 /* reg_ritr_loopback_ipip_options 6969 * Access: RW 6970 */ 6971 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6972 6973 /* reg_ritr_loopback_ipip_uvr 6974 * Underlay Virtual Router ID. 6975 * Range is 0..cap_max_virtual_routers-1. 6976 * Reserved for Spectrum-2. 6977 * Access: RW 6978 */ 6979 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6980 6981 /* reg_ritr_loopback_ipip_underlay_rif 6982 * Underlay ingress router interface. 6983 * Reserved for Spectrum. 6984 * Access: RW 6985 */ 6986 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6987 6988 /* reg_ritr_loopback_ipip_usip* 6989 * Encapsulation Underlay source IP. 6990 * Access: RW 6991 */ 6992 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6993 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6994 6995 /* reg_ritr_loopback_ipip_gre_key 6996 * GRE Key. 6997 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6998 * Access: RW 6999 */ 7000 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 7001 7002 /* Shared between ingress/egress */ 7003 enum mlxsw_reg_ritr_counter_set_type { 7004 /* No Count. */ 7005 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 7006 /* Basic. Used for router interfaces, counting the following: 7007 * - Error and Discard counters. 7008 * - Unicast, Multicast and Broadcast counters. Sharing the 7009 * same set of counters for the different type of traffic 7010 * (IPv4, IPv6 and mpls). 7011 */ 7012 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 7013 }; 7014 7015 /* reg_ritr_ingress_counter_index 7016 * Counter Index for flow counter. 7017 * Access: RW 7018 */ 7019 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 7020 7021 /* reg_ritr_ingress_counter_set_type 7022 * Igress Counter Set Type for router interface counter. 7023 * Access: RW 7024 */ 7025 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 7026 7027 /* reg_ritr_egress_counter_index 7028 * Counter Index for flow counter. 7029 * Access: RW 7030 */ 7031 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 7032 7033 /* reg_ritr_egress_counter_set_type 7034 * Egress Counter Set Type for router interface counter. 7035 * Access: RW 7036 */ 7037 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 7038 7039 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 7040 bool enable, bool egress) 7041 { 7042 enum mlxsw_reg_ritr_counter_set_type set_type; 7043 7044 if (enable) 7045 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 7046 else 7047 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 7048 7049 if (egress) { 7050 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 7051 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 7052 } else { 7053 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 7054 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 7055 } 7056 } 7057 7058 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 7059 { 7060 MLXSW_REG_ZERO(ritr, payload); 7061 mlxsw_reg_ritr_rif_set(payload, rif); 7062 } 7063 7064 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 7065 u16 system_port, u16 efid, u16 vid) 7066 { 7067 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 7068 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 7069 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 7070 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 7071 } 7072 7073 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7074 enum mlxsw_reg_ritr_if_type type, 7075 u16 rif, u16 vr_id, u16 mtu) 7076 { 7077 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7078 7079 MLXSW_REG_ZERO(ritr, payload); 7080 mlxsw_reg_ritr_enable_set(payload, enable); 7081 mlxsw_reg_ritr_ipv4_set(payload, 1); 7082 mlxsw_reg_ritr_ipv6_set(payload, 1); 7083 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7084 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7085 mlxsw_reg_ritr_type_set(payload, type); 7086 mlxsw_reg_ritr_op_set(payload, op); 7087 mlxsw_reg_ritr_rif_set(payload, rif); 7088 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7089 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7090 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7091 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7092 mlxsw_reg_ritr_lb_en_set(payload, 1); 7093 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7094 mlxsw_reg_ritr_mtu_set(payload, mtu); 7095 } 7096 7097 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7098 { 7099 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7100 } 7101 7102 static inline void 7103 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7104 u16 mtu, const char *mac, u8 mac_profile_id, 7105 u16 vlan_id, u16 efid) 7106 { 7107 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7108 7109 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7110 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7111 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7112 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7113 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7114 } 7115 7116 static inline void 7117 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7118 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7119 enum mlxsw_reg_ritr_loopback_ipip_options options, 7120 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7121 { 7122 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7123 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7124 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7125 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7126 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7127 } 7128 7129 static inline void 7130 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7131 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7132 enum mlxsw_reg_ritr_loopback_ipip_options options, 7133 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7134 { 7135 mlxsw_reg_ritr_loopback_protocol_set(payload, 7136 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7137 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7138 uvr_id, underlay_rif, gre_key); 7139 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7140 } 7141 7142 static inline void 7143 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7144 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7145 enum mlxsw_reg_ritr_loopback_ipip_options options, 7146 u16 uvr_id, u16 underlay_rif, 7147 const struct in6_addr *usip, u32 gre_key) 7148 { 7149 enum mlxsw_reg_ritr_loopback_protocol protocol = 7150 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7151 7152 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7153 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7154 uvr_id, underlay_rif, gre_key); 7155 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7156 (const char *)usip); 7157 } 7158 7159 /* RTAR - Router TCAM Allocation Register 7160 * -------------------------------------- 7161 * This register is used for allocation of regions in the TCAM table. 7162 */ 7163 #define MLXSW_REG_RTAR_ID 0x8004 7164 #define MLXSW_REG_RTAR_LEN 0x20 7165 7166 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7167 7168 enum mlxsw_reg_rtar_op { 7169 MLXSW_REG_RTAR_OP_ALLOCATE, 7170 MLXSW_REG_RTAR_OP_RESIZE, 7171 MLXSW_REG_RTAR_OP_DEALLOCATE, 7172 }; 7173 7174 /* reg_rtar_op 7175 * Access: WO 7176 */ 7177 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7178 7179 enum mlxsw_reg_rtar_key_type { 7180 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7181 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7182 }; 7183 7184 /* reg_rtar_key_type 7185 * TCAM key type for the region. 7186 * Access: WO 7187 */ 7188 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7189 7190 /* reg_rtar_region_size 7191 * TCAM region size. When allocating/resizing this is the requested 7192 * size, the response is the actual size. 7193 * Note: Actual size may be larger than requested. 7194 * Reserved for op = Deallocate 7195 * Access: WO 7196 */ 7197 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7198 7199 static inline void mlxsw_reg_rtar_pack(char *payload, 7200 enum mlxsw_reg_rtar_op op, 7201 enum mlxsw_reg_rtar_key_type key_type, 7202 u16 region_size) 7203 { 7204 MLXSW_REG_ZERO(rtar, payload); 7205 mlxsw_reg_rtar_op_set(payload, op); 7206 mlxsw_reg_rtar_key_type_set(payload, key_type); 7207 mlxsw_reg_rtar_region_size_set(payload, region_size); 7208 } 7209 7210 /* RATR - Router Adjacency Table Register 7211 * -------------------------------------- 7212 * The RATR register is used to configure the Router Adjacency (next-hop) 7213 * Table. 7214 */ 7215 #define MLXSW_REG_RATR_ID 0x8008 7216 #define MLXSW_REG_RATR_LEN 0x2C 7217 7218 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7219 7220 enum mlxsw_reg_ratr_op { 7221 /* Read */ 7222 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7223 /* Read and clear activity */ 7224 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7225 /* Write Adjacency entry */ 7226 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7227 /* Write Adjacency entry only if the activity is cleared. 7228 * The write may not succeed if the activity is set. There is not 7229 * direct feedback if the write has succeeded or not, however 7230 * the get will reveal the actual entry (SW can compare the get 7231 * response to the set command). 7232 */ 7233 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7234 }; 7235 7236 /* reg_ratr_op 7237 * Note that Write operation may also be used for updating 7238 * counter_set_type and counter_index. In this case all other 7239 * fields must not be updated. 7240 * Access: OP 7241 */ 7242 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7243 7244 /* reg_ratr_v 7245 * Valid bit. Indicates if the adjacency entry is valid. 7246 * Note: the device may need some time before reusing an invalidated 7247 * entry. During this time the entry can not be reused. It is 7248 * recommended to use another entry before reusing an invalidated 7249 * entry (e.g. software can put it at the end of the list for 7250 * reusing). Trying to access an invalidated entry not yet cleared 7251 * by the device results with failure indicating "Try Again" status. 7252 * When valid is '0' then egress_router_interface,trap_action, 7253 * adjacency_parameters and counters are reserved 7254 * Access: RW 7255 */ 7256 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7257 7258 /* reg_ratr_a 7259 * Activity. Set for new entries. Set if a packet lookup has hit on 7260 * the specific entry. To clear the a bit, use "clear activity". 7261 * Access: RO 7262 */ 7263 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7264 7265 enum mlxsw_reg_ratr_type { 7266 /* Ethernet */ 7267 MLXSW_REG_RATR_TYPE_ETHERNET, 7268 /* IPoIB Unicast without GRH. 7269 * Reserved for Spectrum. 7270 */ 7271 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7272 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7273 * adjacency). 7274 * Reserved for Spectrum. 7275 */ 7276 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7277 /* IPoIB Multicast. 7278 * Reserved for Spectrum. 7279 */ 7280 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7281 /* MPLS. 7282 * Reserved for SwitchX/-2. 7283 */ 7284 MLXSW_REG_RATR_TYPE_MPLS, 7285 /* IPinIP Encap. 7286 * Reserved for SwitchX/-2. 7287 */ 7288 MLXSW_REG_RATR_TYPE_IPIP, 7289 }; 7290 7291 /* reg_ratr_type 7292 * Adjacency entry type. 7293 * Access: RW 7294 */ 7295 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7296 7297 /* reg_ratr_adjacency_index_low 7298 * Bits 15:0 of index into the adjacency table. 7299 * For SwitchX and SwitchX-2, the adjacency table is linear and 7300 * used for adjacency entries only. 7301 * For Spectrum, the index is to the KVD linear. 7302 * Access: Index 7303 */ 7304 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7305 7306 /* reg_ratr_egress_router_interface 7307 * Range is 0 .. cap_max_router_interfaces - 1 7308 * Access: RW 7309 */ 7310 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7311 7312 enum mlxsw_reg_ratr_trap_action { 7313 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7314 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7315 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7316 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7317 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7318 }; 7319 7320 /* reg_ratr_trap_action 7321 * see mlxsw_reg_ratr_trap_action 7322 * Access: RW 7323 */ 7324 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7325 7326 /* reg_ratr_adjacency_index_high 7327 * Bits 23:16 of the adjacency_index. 7328 * Access: Index 7329 */ 7330 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7331 7332 enum mlxsw_reg_ratr_trap_id { 7333 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7334 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7335 }; 7336 7337 /* reg_ratr_trap_id 7338 * Trap ID to be reported to CPU. 7339 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7340 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7341 * Access: RW 7342 */ 7343 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7344 7345 /* reg_ratr_eth_destination_mac 7346 * MAC address of the destination next-hop. 7347 * Access: RW 7348 */ 7349 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7350 7351 enum mlxsw_reg_ratr_ipip_type { 7352 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7353 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7354 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7355 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7356 }; 7357 7358 /* reg_ratr_ipip_type 7359 * Underlay destination ip type. 7360 * Note: the type field must match the protocol of the router interface. 7361 * Access: RW 7362 */ 7363 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7364 7365 /* reg_ratr_ipip_ipv4_udip 7366 * Underlay ipv4 dip. 7367 * Reserved when ipip_type is IPv6. 7368 * Access: RW 7369 */ 7370 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7371 7372 /* reg_ratr_ipip_ipv6_ptr 7373 * Pointer to IPv6 underlay destination ip address. 7374 * For Spectrum: Pointer to KVD linear space. 7375 * Access: RW 7376 */ 7377 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7378 7379 enum mlxsw_reg_flow_counter_set_type { 7380 /* No count */ 7381 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7382 /* Count packets and bytes */ 7383 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7384 /* Count only packets */ 7385 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7386 }; 7387 7388 /* reg_ratr_counter_set_type 7389 * Counter set type for flow counters 7390 * Access: RW 7391 */ 7392 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7393 7394 /* reg_ratr_counter_index 7395 * Counter index for flow counters 7396 * Access: RW 7397 */ 7398 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7399 7400 static inline void 7401 mlxsw_reg_ratr_pack(char *payload, 7402 enum mlxsw_reg_ratr_op op, bool valid, 7403 enum mlxsw_reg_ratr_type type, 7404 u32 adjacency_index, u16 egress_rif) 7405 { 7406 MLXSW_REG_ZERO(ratr, payload); 7407 mlxsw_reg_ratr_op_set(payload, op); 7408 mlxsw_reg_ratr_v_set(payload, valid); 7409 mlxsw_reg_ratr_type_set(payload, type); 7410 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7411 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7412 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7413 } 7414 7415 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7416 const char *dest_mac) 7417 { 7418 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7419 } 7420 7421 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7422 { 7423 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7424 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7425 } 7426 7427 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7428 { 7429 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7430 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7431 } 7432 7433 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7434 bool counter_enable) 7435 { 7436 enum mlxsw_reg_flow_counter_set_type set_type; 7437 7438 if (counter_enable) 7439 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7440 else 7441 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7442 7443 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7444 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7445 } 7446 7447 /* RDPM - Router DSCP to Priority Mapping 7448 * -------------------------------------- 7449 * Controls the mapping from DSCP field to switch priority on routed packets 7450 */ 7451 #define MLXSW_REG_RDPM_ID 0x8009 7452 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7453 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7454 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7455 #define MLXSW_REG_RDPM_LEN 0x40 7456 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7457 MLXSW_REG_RDPM_LEN - \ 7458 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7459 7460 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7461 7462 /* reg_dscp_entry_e 7463 * Enable update of the specific entry 7464 * Access: Index 7465 */ 7466 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7467 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7468 7469 /* reg_dscp_entry_prio 7470 * Switch Priority 7471 * Access: RW 7472 */ 7473 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7474 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7475 7476 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7477 u8 prio) 7478 { 7479 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7480 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7481 } 7482 7483 /* RICNT - Router Interface Counter Register 7484 * ----------------------------------------- 7485 * The RICNT register retrieves per port performance counters 7486 */ 7487 #define MLXSW_REG_RICNT_ID 0x800B 7488 #define MLXSW_REG_RICNT_LEN 0x100 7489 7490 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7491 7492 /* reg_ricnt_counter_index 7493 * Counter index 7494 * Access: RW 7495 */ 7496 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7497 7498 enum mlxsw_reg_ricnt_counter_set_type { 7499 /* No Count. */ 7500 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7501 /* Basic. Used for router interfaces, counting the following: 7502 * - Error and Discard counters. 7503 * - Unicast, Multicast and Broadcast counters. Sharing the 7504 * same set of counters for the different type of traffic 7505 * (IPv4, IPv6 and mpls). 7506 */ 7507 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7508 }; 7509 7510 /* reg_ricnt_counter_set_type 7511 * Counter Set Type for router interface counter 7512 * Access: RW 7513 */ 7514 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7515 7516 enum mlxsw_reg_ricnt_opcode { 7517 /* Nop. Supported only for read access*/ 7518 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7519 /* Clear. Setting the clr bit will reset the counter value for 7520 * all counters of the specified Router Interface. 7521 */ 7522 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7523 }; 7524 7525 /* reg_ricnt_opcode 7526 * Opcode 7527 * Access: RW 7528 */ 7529 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7530 7531 /* reg_ricnt_good_unicast_packets 7532 * good unicast packets. 7533 * Access: RW 7534 */ 7535 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7536 7537 /* reg_ricnt_good_multicast_packets 7538 * good multicast packets. 7539 * Access: RW 7540 */ 7541 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7542 7543 /* reg_ricnt_good_broadcast_packets 7544 * good broadcast packets 7545 * Access: RW 7546 */ 7547 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7548 7549 /* reg_ricnt_good_unicast_bytes 7550 * A count of L3 data and padding octets not including L2 headers 7551 * for good unicast frames. 7552 * Access: RW 7553 */ 7554 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7555 7556 /* reg_ricnt_good_multicast_bytes 7557 * A count of L3 data and padding octets not including L2 headers 7558 * for good multicast frames. 7559 * Access: RW 7560 */ 7561 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7562 7563 /* reg_ritr_good_broadcast_bytes 7564 * A count of L3 data and padding octets not including L2 headers 7565 * for good broadcast frames. 7566 * Access: RW 7567 */ 7568 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7569 7570 /* reg_ricnt_error_packets 7571 * A count of errored frames that do not pass the router checks. 7572 * Access: RW 7573 */ 7574 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7575 7576 /* reg_ricnt_discrad_packets 7577 * A count of non-errored frames that do not pass the router checks. 7578 * Access: RW 7579 */ 7580 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7581 7582 /* reg_ricnt_error_bytes 7583 * A count of L3 data and padding octets not including L2 headers 7584 * for errored frames. 7585 * Access: RW 7586 */ 7587 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7588 7589 /* reg_ricnt_discard_bytes 7590 * A count of L3 data and padding octets not including L2 headers 7591 * for non-errored frames that do not pass the router checks. 7592 * Access: RW 7593 */ 7594 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7595 7596 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7597 enum mlxsw_reg_ricnt_opcode op) 7598 { 7599 MLXSW_REG_ZERO(ricnt, payload); 7600 mlxsw_reg_ricnt_op_set(payload, op); 7601 mlxsw_reg_ricnt_counter_index_set(payload, index); 7602 mlxsw_reg_ricnt_counter_set_type_set(payload, 7603 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7604 } 7605 7606 /* RRCR - Router Rules Copy Register Layout 7607 * ---------------------------------------- 7608 * This register is used for moving and copying route entry rules. 7609 */ 7610 #define MLXSW_REG_RRCR_ID 0x800F 7611 #define MLXSW_REG_RRCR_LEN 0x24 7612 7613 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7614 7615 enum mlxsw_reg_rrcr_op { 7616 /* Move rules */ 7617 MLXSW_REG_RRCR_OP_MOVE, 7618 /* Copy rules */ 7619 MLXSW_REG_RRCR_OP_COPY, 7620 }; 7621 7622 /* reg_rrcr_op 7623 * Access: WO 7624 */ 7625 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7626 7627 /* reg_rrcr_offset 7628 * Offset within the region from which to copy/move. 7629 * Access: Index 7630 */ 7631 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7632 7633 /* reg_rrcr_size 7634 * The number of rules to copy/move. 7635 * Access: WO 7636 */ 7637 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7638 7639 /* reg_rrcr_table_id 7640 * Identifier of the table on which to perform the operation. Encoding is the 7641 * same as in RTAR.key_type 7642 * Access: Index 7643 */ 7644 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7645 7646 /* reg_rrcr_dest_offset 7647 * Offset within the region to which to copy/move 7648 * Access: Index 7649 */ 7650 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7651 7652 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7653 u16 offset, u16 size, 7654 enum mlxsw_reg_rtar_key_type table_id, 7655 u16 dest_offset) 7656 { 7657 MLXSW_REG_ZERO(rrcr, payload); 7658 mlxsw_reg_rrcr_op_set(payload, op); 7659 mlxsw_reg_rrcr_offset_set(payload, offset); 7660 mlxsw_reg_rrcr_size_set(payload, size); 7661 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7662 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7663 } 7664 7665 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7666 * ------------------------------------------------------- 7667 * RALTA is used to allocate the LPM trees of the SHSPM method. 7668 */ 7669 #define MLXSW_REG_RALTA_ID 0x8010 7670 #define MLXSW_REG_RALTA_LEN 0x04 7671 7672 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7673 7674 /* reg_ralta_op 7675 * opcode (valid for Write, must be 0 on Read) 7676 * 0 - allocate a tree 7677 * 1 - deallocate a tree 7678 * Access: OP 7679 */ 7680 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7681 7682 enum mlxsw_reg_ralxx_protocol { 7683 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7684 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7685 }; 7686 7687 /* reg_ralta_protocol 7688 * Protocol. 7689 * Deallocation opcode: Reserved. 7690 * Access: RW 7691 */ 7692 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7693 7694 /* reg_ralta_tree_id 7695 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7696 * the tree identifier (managed by software). 7697 * Note that tree_id 0 is allocated for a default-route tree. 7698 * Access: Index 7699 */ 7700 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7701 7702 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7703 enum mlxsw_reg_ralxx_protocol protocol, 7704 u8 tree_id) 7705 { 7706 MLXSW_REG_ZERO(ralta, payload); 7707 mlxsw_reg_ralta_op_set(payload, !alloc); 7708 mlxsw_reg_ralta_protocol_set(payload, protocol); 7709 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7710 } 7711 7712 /* RALST - Router Algorithmic LPM Structure Tree Register 7713 * ------------------------------------------------------ 7714 * RALST is used to set and query the structure of an LPM tree. 7715 * The structure of the tree must be sorted as a sorted binary tree, while 7716 * each node is a bin that is tagged as the length of the prefixes the lookup 7717 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7718 * of X bits to match with the destination address. The bin 0 indicates 7719 * the default action, when there is no match of any prefix. 7720 */ 7721 #define MLXSW_REG_RALST_ID 0x8011 7722 #define MLXSW_REG_RALST_LEN 0x104 7723 7724 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7725 7726 /* reg_ralst_root_bin 7727 * The bin number of the root bin. 7728 * 0<root_bin=<(length of IP address) 7729 * For a default-route tree configure 0xff 7730 * Access: RW 7731 */ 7732 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7733 7734 /* reg_ralst_tree_id 7735 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7736 * Access: Index 7737 */ 7738 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7739 7740 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7741 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7742 #define MLXSW_REG_RALST_BIN_COUNT 128 7743 7744 /* reg_ralst_left_child_bin 7745 * Holding the children of the bin according to the stored tree's structure. 7746 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7747 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7748 * Access: RW 7749 */ 7750 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7751 7752 /* reg_ralst_right_child_bin 7753 * Holding the children of the bin according to the stored tree's structure. 7754 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7755 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7756 * Access: RW 7757 */ 7758 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7759 false); 7760 7761 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7762 { 7763 MLXSW_REG_ZERO(ralst, payload); 7764 7765 /* Initialize all bins to have no left or right child */ 7766 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7767 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7768 7769 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7770 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7771 } 7772 7773 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7774 u8 left_child_bin, 7775 u8 right_child_bin) 7776 { 7777 int bin_index = bin_number - 1; 7778 7779 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7780 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7781 right_child_bin); 7782 } 7783 7784 /* RALTB - Router Algorithmic LPM Tree Binding Register 7785 * ---------------------------------------------------- 7786 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7787 */ 7788 #define MLXSW_REG_RALTB_ID 0x8012 7789 #define MLXSW_REG_RALTB_LEN 0x04 7790 7791 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7792 7793 /* reg_raltb_virtual_router 7794 * Virtual Router ID 7795 * Range is 0..cap_max_virtual_routers-1 7796 * Access: Index 7797 */ 7798 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7799 7800 /* reg_raltb_protocol 7801 * Protocol. 7802 * Access: Index 7803 */ 7804 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7805 7806 /* reg_raltb_tree_id 7807 * Tree to be used for the {virtual_router, protocol} 7808 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7809 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7810 * Access: RW 7811 */ 7812 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7813 7814 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7815 enum mlxsw_reg_ralxx_protocol protocol, 7816 u8 tree_id) 7817 { 7818 MLXSW_REG_ZERO(raltb, payload); 7819 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7820 mlxsw_reg_raltb_protocol_set(payload, protocol); 7821 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7822 } 7823 7824 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7825 * ----------------------------------------------------- 7826 * RALUE is used to configure and query LPM entries that serve 7827 * the Unicast protocols. 7828 */ 7829 #define MLXSW_REG_RALUE_ID 0x8013 7830 #define MLXSW_REG_RALUE_LEN 0x38 7831 7832 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7833 7834 /* reg_ralue_protocol 7835 * Protocol. 7836 * Access: Index 7837 */ 7838 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7839 7840 enum mlxsw_reg_ralue_op { 7841 /* Read operation. If entry doesn't exist, the operation fails. */ 7842 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7843 /* Clear on read operation. Used to read entry and 7844 * clear Activity bit. 7845 */ 7846 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7847 /* Write operation. Used to write a new entry to the table. All RW 7848 * fields are written for new entry. Activity bit is set 7849 * for new entries. 7850 */ 7851 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7852 /* Update operation. Used to update an existing route entry and 7853 * only update the RW fields that are detailed in the field 7854 * op_u_mask. If entry doesn't exist, the operation fails. 7855 */ 7856 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7857 /* Clear activity. The Activity bit (the field a) is cleared 7858 * for the entry. 7859 */ 7860 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7861 /* Delete operation. Used to delete an existing entry. If entry 7862 * doesn't exist, the operation fails. 7863 */ 7864 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7865 }; 7866 7867 /* reg_ralue_op 7868 * Operation. 7869 * Access: OP 7870 */ 7871 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7872 7873 /* reg_ralue_a 7874 * Activity. Set for new entries. Set if a packet lookup has hit on the 7875 * specific entry, only if the entry is a route. To clear the a bit, use 7876 * "clear activity" op. 7877 * Enabled by activity_dis in RGCR 7878 * Access: RO 7879 */ 7880 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7881 7882 /* reg_ralue_virtual_router 7883 * Virtual Router ID 7884 * Range is 0..cap_max_virtual_routers-1 7885 * Access: Index 7886 */ 7887 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7888 7889 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7890 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7891 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7892 7893 /* reg_ralue_op_u_mask 7894 * opcode update mask. 7895 * On read operation, this field is reserved. 7896 * This field is valid for update opcode, otherwise - reserved. 7897 * This field is a bitmask of the fields that should be updated. 7898 * Access: WO 7899 */ 7900 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7901 7902 /* reg_ralue_prefix_len 7903 * Number of bits in the prefix of the LPM route. 7904 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7905 * two entries in the physical HW table. 7906 * Access: Index 7907 */ 7908 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7909 7910 /* reg_ralue_dip* 7911 * The prefix of the route or of the marker that the object of the LPM 7912 * is compared with. The most significant bits of the dip are the prefix. 7913 * The least significant bits must be '0' if the prefix_len is smaller 7914 * than 128 for IPv6 or smaller than 32 for IPv4. 7915 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7916 * Access: Index 7917 */ 7918 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7919 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7920 7921 enum mlxsw_reg_ralue_entry_type { 7922 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7923 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7924 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7925 }; 7926 7927 /* reg_ralue_entry_type 7928 * Entry type. 7929 * Note - for Marker entries, the action_type and action fields are reserved. 7930 * Access: RW 7931 */ 7932 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7933 7934 /* reg_ralue_bmp_len 7935 * The best match prefix length in the case that there is no match for 7936 * longer prefixes. 7937 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7938 * Note for any update operation with entry_type modification this 7939 * field must be set. 7940 * Access: RW 7941 */ 7942 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7943 7944 enum mlxsw_reg_ralue_action_type { 7945 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7946 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7947 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7948 }; 7949 7950 /* reg_ralue_action_type 7951 * Action Type 7952 * Indicates how the IP address is connected. 7953 * It can be connected to a local subnet through local_erif or can be 7954 * on a remote subnet connected through a next-hop router, 7955 * or transmitted to the CPU. 7956 * Reserved when entry_type = MARKER_ENTRY 7957 * Access: RW 7958 */ 7959 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7960 7961 enum mlxsw_reg_ralue_trap_action { 7962 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7963 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7964 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7965 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7966 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7967 }; 7968 7969 /* reg_ralue_trap_action 7970 * Trap action. 7971 * For IP2ME action, only NOP and MIRROR are possible. 7972 * Access: RW 7973 */ 7974 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7975 7976 /* reg_ralue_trap_id 7977 * Trap ID to be reported to CPU. 7978 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7979 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7980 * Access: RW 7981 */ 7982 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7983 7984 /* reg_ralue_adjacency_index 7985 * Points to the first entry of the group-based ECMP. 7986 * Only relevant in case of REMOTE action. 7987 * Access: RW 7988 */ 7989 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7990 7991 /* reg_ralue_ecmp_size 7992 * Amount of sequential entries starting 7993 * from the adjacency_index (the number of ECMPs). 7994 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7995 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7996 * Only relevant in case of REMOTE action. 7997 * Access: RW 7998 */ 7999 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 8000 8001 /* reg_ralue_local_erif 8002 * Egress Router Interface. 8003 * Only relevant in case of LOCAL action. 8004 * Access: RW 8005 */ 8006 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 8007 8008 /* reg_ralue_ip2me_v 8009 * Valid bit for the tunnel_ptr field. 8010 * If valid = 0 then trap to CPU as IP2ME trap ID. 8011 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 8012 * decapsulation then tunnel decapsulation is done. 8013 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 8014 * decapsulation then trap as IP2ME trap ID. 8015 * Only relevant in case of IP2ME action. 8016 * Access: RW 8017 */ 8018 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 8019 8020 /* reg_ralue_ip2me_tunnel_ptr 8021 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 8022 * For Spectrum, pointer to KVD Linear. 8023 * Only relevant in case of IP2ME action. 8024 * Access: RW 8025 */ 8026 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 8027 8028 static inline void mlxsw_reg_ralue_pack(char *payload, 8029 enum mlxsw_reg_ralxx_protocol protocol, 8030 enum mlxsw_reg_ralue_op op, 8031 u16 virtual_router, u8 prefix_len) 8032 { 8033 MLXSW_REG_ZERO(ralue, payload); 8034 mlxsw_reg_ralue_protocol_set(payload, protocol); 8035 mlxsw_reg_ralue_op_set(payload, op); 8036 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 8037 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 8038 mlxsw_reg_ralue_entry_type_set(payload, 8039 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8040 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 8041 } 8042 8043 static inline void mlxsw_reg_ralue_pack4(char *payload, 8044 enum mlxsw_reg_ralxx_protocol protocol, 8045 enum mlxsw_reg_ralue_op op, 8046 u16 virtual_router, u8 prefix_len, 8047 u32 dip) 8048 { 8049 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8050 mlxsw_reg_ralue_dip4_set(payload, dip); 8051 } 8052 8053 static inline void mlxsw_reg_ralue_pack6(char *payload, 8054 enum mlxsw_reg_ralxx_protocol protocol, 8055 enum mlxsw_reg_ralue_op op, 8056 u16 virtual_router, u8 prefix_len, 8057 const void *dip) 8058 { 8059 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8060 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 8061 } 8062 8063 static inline void 8064 mlxsw_reg_ralue_act_remote_pack(char *payload, 8065 enum mlxsw_reg_ralue_trap_action trap_action, 8066 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 8067 { 8068 mlxsw_reg_ralue_action_type_set(payload, 8069 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 8070 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8071 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8072 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8073 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8074 } 8075 8076 static inline void 8077 mlxsw_reg_ralue_act_local_pack(char *payload, 8078 enum mlxsw_reg_ralue_trap_action trap_action, 8079 u16 trap_id, u16 local_erif) 8080 { 8081 mlxsw_reg_ralue_action_type_set(payload, 8082 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8083 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8084 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8085 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8086 } 8087 8088 static inline void 8089 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8090 { 8091 mlxsw_reg_ralue_action_type_set(payload, 8092 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8093 } 8094 8095 static inline void 8096 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8097 { 8098 mlxsw_reg_ralue_action_type_set(payload, 8099 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8100 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8101 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8102 } 8103 8104 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8105 * ---------------------------------------------------------- 8106 * The RAUHT register is used to configure and query the Unicast Host table in 8107 * devices that implement the Algorithmic LPM. 8108 */ 8109 #define MLXSW_REG_RAUHT_ID 0x8014 8110 #define MLXSW_REG_RAUHT_LEN 0x74 8111 8112 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8113 8114 enum mlxsw_reg_rauht_type { 8115 MLXSW_REG_RAUHT_TYPE_IPV4, 8116 MLXSW_REG_RAUHT_TYPE_IPV6, 8117 }; 8118 8119 /* reg_rauht_type 8120 * Access: Index 8121 */ 8122 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8123 8124 enum mlxsw_reg_rauht_op { 8125 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8126 /* Read operation */ 8127 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8128 /* Clear on read operation. Used to read entry and clear 8129 * activity bit. 8130 */ 8131 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8132 /* Add. Used to write a new entry to the table. All R/W fields are 8133 * relevant for new entry. Activity bit is set for new entries. 8134 */ 8135 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8136 /* Update action. Used to update an existing route entry and 8137 * only update the following fields: 8138 * trap_action, trap_id, mac, counter_set_type, counter_index 8139 */ 8140 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8141 /* Clear activity. A bit is cleared for the entry. */ 8142 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8143 /* Delete entry */ 8144 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8145 /* Delete all host entries on a RIF. In this command, dip 8146 * field is reserved. 8147 */ 8148 }; 8149 8150 /* reg_rauht_op 8151 * Access: OP 8152 */ 8153 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8154 8155 /* reg_rauht_a 8156 * Activity. Set for new entries. Set if a packet lookup has hit on 8157 * the specific entry. 8158 * To clear the a bit, use "clear activity" op. 8159 * Enabled by activity_dis in RGCR 8160 * Access: RO 8161 */ 8162 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8163 8164 /* reg_rauht_rif 8165 * Router Interface 8166 * Access: Index 8167 */ 8168 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8169 8170 /* reg_rauht_dip* 8171 * Destination address. 8172 * Access: Index 8173 */ 8174 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8175 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8176 8177 enum mlxsw_reg_rauht_trap_action { 8178 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8179 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8180 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8181 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8182 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8183 }; 8184 8185 /* reg_rauht_trap_action 8186 * Access: RW 8187 */ 8188 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8189 8190 enum mlxsw_reg_rauht_trap_id { 8191 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8192 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8193 }; 8194 8195 /* reg_rauht_trap_id 8196 * Trap ID to be reported to CPU. 8197 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8198 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8199 * trap_id is reserved. 8200 * Access: RW 8201 */ 8202 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8203 8204 /* reg_rauht_counter_set_type 8205 * Counter set type for flow counters 8206 * Access: RW 8207 */ 8208 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8209 8210 /* reg_rauht_counter_index 8211 * Counter index for flow counters 8212 * Access: RW 8213 */ 8214 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8215 8216 /* reg_rauht_mac 8217 * MAC address. 8218 * Access: RW 8219 */ 8220 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8221 8222 static inline void mlxsw_reg_rauht_pack(char *payload, 8223 enum mlxsw_reg_rauht_op op, u16 rif, 8224 const char *mac) 8225 { 8226 MLXSW_REG_ZERO(rauht, payload); 8227 mlxsw_reg_rauht_op_set(payload, op); 8228 mlxsw_reg_rauht_rif_set(payload, rif); 8229 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8230 } 8231 8232 static inline void mlxsw_reg_rauht_pack4(char *payload, 8233 enum mlxsw_reg_rauht_op op, u16 rif, 8234 const char *mac, u32 dip) 8235 { 8236 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8237 mlxsw_reg_rauht_dip4_set(payload, dip); 8238 } 8239 8240 static inline void mlxsw_reg_rauht_pack6(char *payload, 8241 enum mlxsw_reg_rauht_op op, u16 rif, 8242 const char *mac, const char *dip) 8243 { 8244 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8245 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8246 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8247 } 8248 8249 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8250 u64 counter_index) 8251 { 8252 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8253 mlxsw_reg_rauht_counter_set_type_set(payload, 8254 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8255 } 8256 8257 /* RALEU - Router Algorithmic LPM ECMP Update Register 8258 * --------------------------------------------------- 8259 * The register enables updating the ECMP section in the action for multiple 8260 * LPM Unicast entries in a single operation. The update is executed to 8261 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8262 */ 8263 #define MLXSW_REG_RALEU_ID 0x8015 8264 #define MLXSW_REG_RALEU_LEN 0x28 8265 8266 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8267 8268 /* reg_raleu_protocol 8269 * Protocol. 8270 * Access: Index 8271 */ 8272 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8273 8274 /* reg_raleu_virtual_router 8275 * Virtual Router ID 8276 * Range is 0..cap_max_virtual_routers-1 8277 * Access: Index 8278 */ 8279 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8280 8281 /* reg_raleu_adjacency_index 8282 * Adjacency Index used for matching on the existing entries. 8283 * Access: Index 8284 */ 8285 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8286 8287 /* reg_raleu_ecmp_size 8288 * ECMP Size used for matching on the existing entries. 8289 * Access: Index 8290 */ 8291 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8292 8293 /* reg_raleu_new_adjacency_index 8294 * New Adjacency Index. 8295 * Access: WO 8296 */ 8297 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8298 8299 /* reg_raleu_new_ecmp_size 8300 * New ECMP Size. 8301 * Access: WO 8302 */ 8303 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8304 8305 static inline void mlxsw_reg_raleu_pack(char *payload, 8306 enum mlxsw_reg_ralxx_protocol protocol, 8307 u16 virtual_router, 8308 u32 adjacency_index, u16 ecmp_size, 8309 u32 new_adjacency_index, 8310 u16 new_ecmp_size) 8311 { 8312 MLXSW_REG_ZERO(raleu, payload); 8313 mlxsw_reg_raleu_protocol_set(payload, protocol); 8314 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8315 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8316 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8317 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8318 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8319 } 8320 8321 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8322 * ---------------------------------------------------------------- 8323 * The RAUHTD register allows dumping entries from the Router Unicast Host 8324 * Table. For a given session an entry is dumped no more than one time. The 8325 * first RAUHTD access after reset is a new session. A session ends when the 8326 * num_rec response is smaller than num_rec request or for IPv4 when the 8327 * num_entries is smaller than 4. The clear activity affect the current session 8328 * or the last session if a new session has not started. 8329 */ 8330 #define MLXSW_REG_RAUHTD_ID 0x8018 8331 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8332 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8333 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8334 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8335 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8336 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8337 8338 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8339 8340 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8341 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8342 8343 /* reg_rauhtd_filter_fields 8344 * if a bit is '0' then the relevant field is ignored and dump is done 8345 * regardless of the field value 8346 * Bit0 - filter by activity: entry_a 8347 * Bit3 - filter by entry rip: entry_rif 8348 * Access: Index 8349 */ 8350 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8351 8352 enum mlxsw_reg_rauhtd_op { 8353 MLXSW_REG_RAUHTD_OP_DUMP, 8354 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8355 }; 8356 8357 /* reg_rauhtd_op 8358 * Access: OP 8359 */ 8360 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8361 8362 /* reg_rauhtd_num_rec 8363 * At request: number of records requested 8364 * At response: number of records dumped 8365 * For IPv4, each record has 4 entries at request and up to 4 entries 8366 * at response 8367 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8368 * Access: Index 8369 */ 8370 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8371 8372 /* reg_rauhtd_entry_a 8373 * Dump only if activity has value of entry_a 8374 * Reserved if filter_fields bit0 is '0' 8375 * Access: Index 8376 */ 8377 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8378 8379 enum mlxsw_reg_rauhtd_type { 8380 MLXSW_REG_RAUHTD_TYPE_IPV4, 8381 MLXSW_REG_RAUHTD_TYPE_IPV6, 8382 }; 8383 8384 /* reg_rauhtd_type 8385 * Dump only if record type is: 8386 * 0 - IPv4 8387 * 1 - IPv6 8388 * Access: Index 8389 */ 8390 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8391 8392 /* reg_rauhtd_entry_rif 8393 * Dump only if RIF has value of entry_rif 8394 * Reserved if filter_fields bit3 is '0' 8395 * Access: Index 8396 */ 8397 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8398 8399 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8400 enum mlxsw_reg_rauhtd_type type) 8401 { 8402 MLXSW_REG_ZERO(rauhtd, payload); 8403 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8404 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8405 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8406 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8407 mlxsw_reg_rauhtd_type_set(payload, type); 8408 } 8409 8410 /* reg_rauhtd_ipv4_rec_num_entries 8411 * Number of valid entries in this record: 8412 * 0 - 1 valid entry 8413 * 1 - 2 valid entries 8414 * 2 - 3 valid entries 8415 * 3 - 4 valid entries 8416 * Access: RO 8417 */ 8418 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8419 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8420 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8421 8422 /* reg_rauhtd_rec_type 8423 * Record type. 8424 * 0 - IPv4 8425 * 1 - IPv6 8426 * Access: RO 8427 */ 8428 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8429 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8430 8431 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8432 8433 /* reg_rauhtd_ipv4_ent_a 8434 * Activity. Set for new entries. Set if a packet lookup has hit on the 8435 * specific entry. 8436 * Access: RO 8437 */ 8438 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8439 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8440 8441 /* reg_rauhtd_ipv4_ent_rif 8442 * Router interface. 8443 * Access: RO 8444 */ 8445 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8446 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8447 8448 /* reg_rauhtd_ipv4_ent_dip 8449 * Destination IPv4 address. 8450 * Access: RO 8451 */ 8452 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8453 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8454 8455 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8456 8457 /* reg_rauhtd_ipv6_ent_a 8458 * Activity. Set for new entries. Set if a packet lookup has hit on the 8459 * specific entry. 8460 * Access: RO 8461 */ 8462 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8463 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8464 8465 /* reg_rauhtd_ipv6_ent_rif 8466 * Router interface. 8467 * Access: RO 8468 */ 8469 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8470 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8471 8472 /* reg_rauhtd_ipv6_ent_dip 8473 * Destination IPv6 address. 8474 * Access: RO 8475 */ 8476 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8477 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8478 8479 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8480 int ent_index, u16 *p_rif, 8481 u32 *p_dip) 8482 { 8483 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8484 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8485 } 8486 8487 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8488 int rec_index, u16 *p_rif, 8489 char *p_dip) 8490 { 8491 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8492 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8493 } 8494 8495 /* RTDP - Routing Tunnel Decap Properties Register 8496 * ----------------------------------------------- 8497 * The RTDP register is used for configuring the tunnel decap properties of NVE 8498 * and IPinIP. 8499 */ 8500 #define MLXSW_REG_RTDP_ID 0x8020 8501 #define MLXSW_REG_RTDP_LEN 0x44 8502 8503 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8504 8505 enum mlxsw_reg_rtdp_type { 8506 MLXSW_REG_RTDP_TYPE_NVE, 8507 MLXSW_REG_RTDP_TYPE_IPIP, 8508 }; 8509 8510 /* reg_rtdp_type 8511 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8512 * Access: RW 8513 */ 8514 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8515 8516 /* reg_rtdp_tunnel_index 8517 * Index to the Decap entry. 8518 * For Spectrum, Index to KVD Linear. 8519 * Access: Index 8520 */ 8521 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8522 8523 /* reg_rtdp_egress_router_interface 8524 * Underlay egress router interface. 8525 * Valid range is from 0 to cap_max_router_interfaces - 1 8526 * Access: RW 8527 */ 8528 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8529 8530 /* IPinIP */ 8531 8532 /* reg_rtdp_ipip_irif 8533 * Ingress Router Interface for the overlay router 8534 * Access: RW 8535 */ 8536 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8537 8538 enum mlxsw_reg_rtdp_ipip_sip_check { 8539 /* No sip checks. */ 8540 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8541 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8542 * equal ipv4_usip. 8543 */ 8544 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8545 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8546 * equal ipv6_usip. 8547 */ 8548 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8549 }; 8550 8551 /* reg_rtdp_ipip_sip_check 8552 * SIP check to perform. If decapsulation failed due to these configurations 8553 * then trap_id is IPIP_DECAP_ERROR. 8554 * Access: RW 8555 */ 8556 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8557 8558 /* If set, allow decapsulation of IPinIP (without GRE). */ 8559 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8560 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8561 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8562 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8563 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8564 8565 /* reg_rtdp_ipip_type_check 8566 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8567 * these configurations then trap_id is IPIP_DECAP_ERROR. 8568 * Access: RW 8569 */ 8570 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8571 8572 /* reg_rtdp_ipip_gre_key_check 8573 * Whether GRE key should be checked. When check is enabled: 8574 * - A packet received as IPinIP (without GRE) will always pass. 8575 * - A packet received as IPinGREinIP without a key will not pass the check. 8576 * - A packet received as IPinGREinIP with a key will pass the check only if the 8577 * key in the packet is equal to expected_gre_key. 8578 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8579 * Access: RW 8580 */ 8581 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8582 8583 /* reg_rtdp_ipip_ipv4_usip 8584 * Underlay IPv4 address for ipv4 source address check. 8585 * Reserved when sip_check is not '1'. 8586 * Access: RW 8587 */ 8588 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8589 8590 /* reg_rtdp_ipip_ipv6_usip_ptr 8591 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8592 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8593 * is to the KVD linear. 8594 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8595 * Access: RW 8596 */ 8597 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8598 8599 /* reg_rtdp_ipip_expected_gre_key 8600 * GRE key for checking. 8601 * Reserved when gre_key_check is '0'. 8602 * Access: RW 8603 */ 8604 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8605 8606 static inline void mlxsw_reg_rtdp_pack(char *payload, 8607 enum mlxsw_reg_rtdp_type type, 8608 u32 tunnel_index) 8609 { 8610 MLXSW_REG_ZERO(rtdp, payload); 8611 mlxsw_reg_rtdp_type_set(payload, type); 8612 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8613 } 8614 8615 static inline void 8616 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8617 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8618 unsigned int type_check, bool gre_key_check, 8619 u32 expected_gre_key) 8620 { 8621 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8622 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8623 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8624 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8625 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8626 } 8627 8628 static inline void 8629 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8630 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8631 unsigned int type_check, bool gre_key_check, 8632 u32 ipv4_usip, u32 expected_gre_key) 8633 { 8634 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8635 gre_key_check, expected_gre_key); 8636 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8637 } 8638 8639 static inline void 8640 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8641 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8642 unsigned int type_check, bool gre_key_check, 8643 u32 ipv6_usip_ptr, u32 expected_gre_key) 8644 { 8645 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8646 gre_key_check, expected_gre_key); 8647 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8648 } 8649 8650 /* RIPS - Router IP version Six Register 8651 * ------------------------------------- 8652 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8653 * IPinIP 8654 */ 8655 #define MLXSW_REG_RIPS_ID 0x8021 8656 #define MLXSW_REG_RIPS_LEN 0x14 8657 8658 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8659 8660 /* reg_rips_index 8661 * Index to IPv6 address. 8662 * For Spectrum, the index is to the KVD linear. 8663 * Access: Index 8664 */ 8665 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8666 8667 /* reg_rips_ipv6 8668 * IPv6 address 8669 * Access: RW 8670 */ 8671 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8672 8673 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8674 const struct in6_addr *ipv6) 8675 { 8676 MLXSW_REG_ZERO(rips, payload); 8677 mlxsw_reg_rips_index_set(payload, index); 8678 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8679 } 8680 8681 /* RATRAD - Router Adjacency Table Activity Dump Register 8682 * ------------------------------------------------------ 8683 * The RATRAD register is used to dump and optionally clear activity bits of 8684 * router adjacency table entries. 8685 */ 8686 #define MLXSW_REG_RATRAD_ID 0x8022 8687 #define MLXSW_REG_RATRAD_LEN 0x210 8688 8689 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8690 8691 enum { 8692 /* Read activity */ 8693 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8694 /* Read and clear activity */ 8695 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8696 }; 8697 8698 /* reg_ratrad_op 8699 * Access: Operation 8700 */ 8701 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8702 8703 /* reg_ratrad_ecmp_size 8704 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8705 * ranges: 8706 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8707 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8708 * Access: Index 8709 */ 8710 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8711 8712 /* reg_ratrad_adjacency_index 8713 * Index into the adjacency table. 8714 * Access: Index 8715 */ 8716 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8717 8718 /* reg_ratrad_activity_vector 8719 * Activity bit per adjacency index. 8720 * Bits higher than ecmp_size are reserved. 8721 * Access: RO 8722 */ 8723 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8724 8725 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8726 u16 ecmp_size) 8727 { 8728 MLXSW_REG_ZERO(ratrad, payload); 8729 mlxsw_reg_ratrad_op_set(payload, 8730 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8731 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8732 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8733 } 8734 8735 /* RIGR-V2 - Router Interface Group Register Version 2 8736 * --------------------------------------------------- 8737 * The RIGR_V2 register is used to add, remove and query egress interface list 8738 * of a multicast forwarding entry. 8739 */ 8740 #define MLXSW_REG_RIGR2_ID 0x8023 8741 #define MLXSW_REG_RIGR2_LEN 0xB0 8742 8743 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8744 8745 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8746 8747 /* reg_rigr2_rigr_index 8748 * KVD Linear index. 8749 * Access: Index 8750 */ 8751 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8752 8753 /* reg_rigr2_vnext 8754 * Next RIGR Index is valid. 8755 * Access: RW 8756 */ 8757 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8758 8759 /* reg_rigr2_next_rigr_index 8760 * Next RIGR Index. The index is to the KVD linear. 8761 * Reserved when vnxet = '0'. 8762 * Access: RW 8763 */ 8764 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8765 8766 /* reg_rigr2_vrmid 8767 * RMID Index is valid. 8768 * Access: RW 8769 */ 8770 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8771 8772 /* reg_rigr2_rmid_index 8773 * RMID Index. 8774 * Range 0 .. max_mid - 1 8775 * Reserved when vrmid = '0'. 8776 * The index is to the Port Group Table (PGT) 8777 * Access: RW 8778 */ 8779 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8780 8781 /* reg_rigr2_erif_entry_v 8782 * Egress Router Interface is valid. 8783 * Note that low-entries must be set if high-entries are set. For 8784 * example: if erif_entry[2].v is set then erif_entry[1].v and 8785 * erif_entry[0].v must be set. 8786 * Index can be from 0 to cap_mc_erif_list_entries-1 8787 * Access: RW 8788 */ 8789 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8790 8791 /* reg_rigr2_erif_entry_erif 8792 * Egress Router Interface. 8793 * Valid range is from 0 to cap_max_router_interfaces - 1 8794 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8795 * Access: RW 8796 */ 8797 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8798 8799 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8800 bool vnext, u32 next_rigr_index) 8801 { 8802 MLXSW_REG_ZERO(rigr2, payload); 8803 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8804 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8805 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8806 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8807 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8808 } 8809 8810 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8811 bool v, u16 erif) 8812 { 8813 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8814 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8815 } 8816 8817 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8818 * ------------------------------------------------------ 8819 */ 8820 #define MLXSW_REG_RECR2_ID 0x8025 8821 #define MLXSW_REG_RECR2_LEN 0x38 8822 8823 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8824 8825 /* reg_recr2_pp 8826 * Per-port configuration 8827 * Access: Index 8828 */ 8829 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8830 8831 /* reg_recr2_sh 8832 * Symmetric hash 8833 * Access: RW 8834 */ 8835 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8836 8837 /* reg_recr2_seed 8838 * Seed 8839 * Access: RW 8840 */ 8841 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8842 8843 enum { 8844 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8845 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8846 /* Enable IPv4 fields if packet is TCP or UDP */ 8847 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8848 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8849 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8850 /* Enable IPv6 fields if packet is TCP or UDP */ 8851 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8852 /* Enable TCP/UDP header fields if packet is IPv4 */ 8853 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8854 /* Enable TCP/UDP header fields if packet is IPv6 */ 8855 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8856 8857 __MLXSW_REG_RECR2_HEADER_CNT, 8858 }; 8859 8860 /* reg_recr2_outer_header_enables 8861 * Bit mask where each bit enables a specific layer to be included in 8862 * the hash calculation. 8863 * Access: RW 8864 */ 8865 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8866 8867 enum { 8868 /* IPv4 Source IP */ 8869 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8870 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8871 /* IPv4 Destination IP */ 8872 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8873 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8874 /* IP Protocol */ 8875 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8876 /* IPv6 Source IP */ 8877 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8878 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8879 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8880 /* IPv6 Destination IP */ 8881 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8882 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8883 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8884 /* IPv6 Next Header */ 8885 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8886 /* IPv6 Flow Label */ 8887 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8888 /* TCP/UDP Source Port */ 8889 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8890 /* TCP/UDP Destination Port */ 8891 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8892 8893 __MLXSW_REG_RECR2_FIELD_CNT, 8894 }; 8895 8896 /* reg_recr2_outer_header_fields_enable 8897 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8898 * Access: RW 8899 */ 8900 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8901 8902 /* reg_recr2_inner_header_enables 8903 * Bit mask where each bit enables a specific inner layer to be included in the 8904 * hash calculation. Same values as reg_recr2_outer_header_enables. 8905 * Access: RW 8906 */ 8907 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8908 8909 enum { 8910 /* Inner IPv4 Source IP */ 8911 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8912 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8913 /* Inner IPv4 Destination IP */ 8914 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8915 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8916 /* Inner IP Protocol */ 8917 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8918 /* Inner IPv6 Source IP */ 8919 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8920 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8921 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8922 /* Inner IPv6 Destination IP */ 8923 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8924 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8925 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8926 /* Inner IPv6 Next Header */ 8927 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8928 /* Inner IPv6 Flow Label */ 8929 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8930 /* Inner TCP/UDP Source Port */ 8931 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8932 /* Inner TCP/UDP Destination Port */ 8933 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8934 8935 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8936 }; 8937 8938 /* reg_recr2_inner_header_fields_enable 8939 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8940 * Access: RW 8941 */ 8942 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8943 8944 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8945 { 8946 MLXSW_REG_ZERO(recr2, payload); 8947 mlxsw_reg_recr2_pp_set(payload, false); 8948 mlxsw_reg_recr2_sh_set(payload, true); 8949 mlxsw_reg_recr2_seed_set(payload, seed); 8950 } 8951 8952 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8953 * -------------------------------------------------------------- 8954 * The RMFT_V2 register is used to configure and query the multicast table. 8955 */ 8956 #define MLXSW_REG_RMFT2_ID 0x8027 8957 #define MLXSW_REG_RMFT2_LEN 0x174 8958 8959 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8960 8961 /* reg_rmft2_v 8962 * Valid 8963 * Access: RW 8964 */ 8965 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8966 8967 enum mlxsw_reg_rmft2_type { 8968 MLXSW_REG_RMFT2_TYPE_IPV4, 8969 MLXSW_REG_RMFT2_TYPE_IPV6 8970 }; 8971 8972 /* reg_rmft2_type 8973 * Access: Index 8974 */ 8975 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8976 8977 enum mlxsw_sp_reg_rmft2_op { 8978 /* For Write: 8979 * Write operation. Used to write a new entry to the table. All RW 8980 * fields are relevant for new entry. Activity bit is set for new 8981 * entries - Note write with v (Valid) 0 will delete the entry. 8982 * For Query: 8983 * Read operation 8984 */ 8985 MLXSW_REG_RMFT2_OP_READ_WRITE, 8986 }; 8987 8988 /* reg_rmft2_op 8989 * Operation. 8990 * Access: OP 8991 */ 8992 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8993 8994 /* reg_rmft2_a 8995 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8996 * entry. 8997 * Access: RO 8998 */ 8999 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 9000 9001 /* reg_rmft2_offset 9002 * Offset within the multicast forwarding table to write to. 9003 * Access: Index 9004 */ 9005 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 9006 9007 /* reg_rmft2_virtual_router 9008 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 9009 * Access: RW 9010 */ 9011 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 9012 9013 enum mlxsw_reg_rmft2_irif_mask { 9014 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 9015 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 9016 }; 9017 9018 /* reg_rmft2_irif_mask 9019 * Ingress RIF mask. 9020 * Access: RW 9021 */ 9022 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 9023 9024 /* reg_rmft2_irif 9025 * Ingress RIF index. 9026 * Access: RW 9027 */ 9028 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 9029 9030 /* reg_rmft2_dip{4,6} 9031 * Destination IPv4/6 address 9032 * Access: RW 9033 */ 9034 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 9035 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 9036 9037 /* reg_rmft2_dip{4,6}_mask 9038 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9039 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9040 * Access: RW 9041 */ 9042 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 9043 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 9044 9045 /* reg_rmft2_sip{4,6} 9046 * Source IPv4/6 address 9047 * Access: RW 9048 */ 9049 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 9050 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 9051 9052 /* reg_rmft2_sip{4,6}_mask 9053 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9054 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9055 * Access: RW 9056 */ 9057 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 9058 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 9059 9060 /* reg_rmft2_flexible_action_set 9061 * ACL action set. The only supported action types in this field and in any 9062 * action-set pointed from here are as follows: 9063 * 00h: ACTION_NULL 9064 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 9065 * 03h: ACTION_TRAP 9066 * 06h: ACTION_QOS 9067 * 08h: ACTION_POLICING_MONITORING 9068 * 10h: ACTION_ROUTER_MC 9069 * Access: RW 9070 */ 9071 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9072 MLXSW_REG_FLEX_ACTION_SET_LEN); 9073 9074 static inline void 9075 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9076 u16 virtual_router, 9077 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9078 const char *flex_action_set) 9079 { 9080 MLXSW_REG_ZERO(rmft2, payload); 9081 mlxsw_reg_rmft2_v_set(payload, v); 9082 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9083 mlxsw_reg_rmft2_offset_set(payload, offset); 9084 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9085 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9086 mlxsw_reg_rmft2_irif_set(payload, irif); 9087 if (flex_action_set) 9088 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9089 flex_action_set); 9090 } 9091 9092 static inline void 9093 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9094 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9095 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9096 const char *flexible_action_set) 9097 { 9098 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9099 irif_mask, irif, flexible_action_set); 9100 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9101 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9102 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9103 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9104 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9105 } 9106 9107 static inline void 9108 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9109 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9110 struct in6_addr dip6, struct in6_addr dip6_mask, 9111 struct in6_addr sip6, struct in6_addr sip6_mask, 9112 const char *flexible_action_set) 9113 { 9114 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9115 irif_mask, irif, flexible_action_set); 9116 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9117 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9118 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9119 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9120 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9121 } 9122 9123 /* REIV - Router Egress Interface to VID Register 9124 * ---------------------------------------------- 9125 * The REIV register maps {eRIF, egress_port} -> VID. 9126 * This mapping is done at the egress, after the ACLs. 9127 * This mapping always takes effect after router, regardless of cast 9128 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9129 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9130 * Reserved when the RIF is a loopback RIF. 9131 * 9132 * Note: Reserved when legacy bridge model is used. 9133 */ 9134 #define MLXSW_REG_REIV_ID 0x8034 9135 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9136 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9137 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9138 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9139 MLXSW_REG_REIV_REC_LEN * \ 9140 MLXSW_REG_REIV_REC_MAX_COUNT) 9141 9142 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9143 9144 /* reg_reiv_port_page 9145 * Port page - elport_record[0] is 256*port_page. 9146 * Access: Index 9147 */ 9148 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9149 9150 /* reg_reiv_erif 9151 * Egress RIF. 9152 * Range is 0..cap_max_router_interfaces-1. 9153 * Access: Index 9154 */ 9155 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9156 9157 /* reg_reiv_rec_update 9158 * Update enable (when write): 9159 * 0 - Do not update the entry. 9160 * 1 - Update the entry. 9161 * Access: OP 9162 */ 9163 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9164 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9165 9166 /* reg_reiv_rec_evid 9167 * Egress VID. 9168 * Range is 0..4095. 9169 * Access: RW 9170 */ 9171 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9172 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9173 9174 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9175 { 9176 MLXSW_REG_ZERO(reiv, payload); 9177 mlxsw_reg_reiv_port_page_set(payload, port_page); 9178 mlxsw_reg_reiv_erif_set(payload, erif); 9179 } 9180 9181 /* MFCR - Management Fan Control Register 9182 * -------------------------------------- 9183 * This register controls the settings of the Fan Speed PWM mechanism. 9184 */ 9185 #define MLXSW_REG_MFCR_ID 0x9001 9186 #define MLXSW_REG_MFCR_LEN 0x08 9187 9188 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9189 9190 enum mlxsw_reg_mfcr_pwm_frequency { 9191 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9192 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9193 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9194 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9195 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9196 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9197 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9198 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9199 }; 9200 9201 /* reg_mfcr_pwm_frequency 9202 * Controls the frequency of the PWM signal. 9203 * Access: RW 9204 */ 9205 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9206 9207 #define MLXSW_MFCR_TACHOS_MAX 10 9208 9209 /* reg_mfcr_tacho_active 9210 * Indicates which of the tachometer is active (bit per tachometer). 9211 * Access: RO 9212 */ 9213 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9214 9215 #define MLXSW_MFCR_PWMS_MAX 5 9216 9217 /* reg_mfcr_pwm_active 9218 * Indicates which of the PWM control is active (bit per PWM). 9219 * Access: RO 9220 */ 9221 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9222 9223 static inline void 9224 mlxsw_reg_mfcr_pack(char *payload, 9225 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9226 { 9227 MLXSW_REG_ZERO(mfcr, payload); 9228 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9229 } 9230 9231 static inline void 9232 mlxsw_reg_mfcr_unpack(char *payload, 9233 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9234 u16 *p_tacho_active, u8 *p_pwm_active) 9235 { 9236 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9237 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9238 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9239 } 9240 9241 /* MFSC - Management Fan Speed Control Register 9242 * -------------------------------------------- 9243 * This register controls the settings of the Fan Speed PWM mechanism. 9244 */ 9245 #define MLXSW_REG_MFSC_ID 0x9002 9246 #define MLXSW_REG_MFSC_LEN 0x08 9247 9248 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9249 9250 /* reg_mfsc_pwm 9251 * Fan pwm to control / monitor. 9252 * Access: Index 9253 */ 9254 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9255 9256 /* reg_mfsc_pwm_duty_cycle 9257 * Controls the duty cycle of the PWM. Value range from 0..255 to 9258 * represent duty cycle of 0%...100%. 9259 * Access: RW 9260 */ 9261 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9262 9263 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9264 u8 pwm_duty_cycle) 9265 { 9266 MLXSW_REG_ZERO(mfsc, payload); 9267 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9268 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9269 } 9270 9271 /* MFSM - Management Fan Speed Measurement 9272 * --------------------------------------- 9273 * This register controls the settings of the Tacho measurements and 9274 * enables reading the Tachometer measurements. 9275 */ 9276 #define MLXSW_REG_MFSM_ID 0x9003 9277 #define MLXSW_REG_MFSM_LEN 0x08 9278 9279 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9280 9281 /* reg_mfsm_tacho 9282 * Fan tachometer index. 9283 * Access: Index 9284 */ 9285 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9286 9287 /* reg_mfsm_rpm 9288 * Fan speed (round per minute). 9289 * Access: RO 9290 */ 9291 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9292 9293 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9294 { 9295 MLXSW_REG_ZERO(mfsm, payload); 9296 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9297 } 9298 9299 /* MFSL - Management Fan Speed Limit Register 9300 * ------------------------------------------ 9301 * The Fan Speed Limit register is used to configure the fan speed 9302 * event / interrupt notification mechanism. Fan speed threshold are 9303 * defined for both under-speed and over-speed. 9304 */ 9305 #define MLXSW_REG_MFSL_ID 0x9004 9306 #define MLXSW_REG_MFSL_LEN 0x0C 9307 9308 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9309 9310 /* reg_mfsl_tacho 9311 * Fan tachometer index. 9312 * Access: Index 9313 */ 9314 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9315 9316 /* reg_mfsl_tach_min 9317 * Tachometer minimum value (minimum RPM). 9318 * Access: RW 9319 */ 9320 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9321 9322 /* reg_mfsl_tach_max 9323 * Tachometer maximum value (maximum RPM). 9324 * Access: RW 9325 */ 9326 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9327 9328 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9329 u16 tach_min, u16 tach_max) 9330 { 9331 MLXSW_REG_ZERO(mfsl, payload); 9332 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9333 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9334 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9335 } 9336 9337 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9338 u16 *p_tach_min, u16 *p_tach_max) 9339 { 9340 if (p_tach_min) 9341 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9342 9343 if (p_tach_max) 9344 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9345 } 9346 9347 /* FORE - Fan Out of Range Event Register 9348 * -------------------------------------- 9349 * This register reports the status of the controlled fans compared to the 9350 * range defined by the MFSL register. 9351 */ 9352 #define MLXSW_REG_FORE_ID 0x9007 9353 #define MLXSW_REG_FORE_LEN 0x0C 9354 9355 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9356 9357 /* fan_under_limit 9358 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9359 * to a single tachometer and indicates the specific tachometer reading is 9360 * below the threshold. 9361 * Access: RO 9362 */ 9363 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9364 9365 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9366 bool *fault) 9367 { 9368 u16 limit; 9369 9370 if (fault) { 9371 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9372 *fault = limit & BIT(tacho); 9373 } 9374 } 9375 9376 /* MTCAP - Management Temperature Capabilities 9377 * ------------------------------------------- 9378 * This register exposes the capabilities of the device and 9379 * system temperature sensing. 9380 */ 9381 #define MLXSW_REG_MTCAP_ID 0x9009 9382 #define MLXSW_REG_MTCAP_LEN 0x08 9383 9384 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9385 9386 /* reg_mtcap_sensor_count 9387 * Number of sensors supported by the device. 9388 * This includes the QSFP module sensors (if exists in the QSFP module). 9389 * Access: RO 9390 */ 9391 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9392 9393 /* MTMP - Management Temperature 9394 * ----------------------------- 9395 * This register controls the settings of the temperature measurements 9396 * and enables reading the temperature measurements. Note that temperature 9397 * is in 0.125 degrees Celsius. 9398 */ 9399 #define MLXSW_REG_MTMP_ID 0x900A 9400 #define MLXSW_REG_MTMP_LEN 0x20 9401 9402 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9403 9404 /* reg_mtmp_slot_index 9405 * Slot index (0: Main board). 9406 * Access: Index 9407 */ 9408 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9409 9410 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9411 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9412 /* reg_mtmp_sensor_index 9413 * Sensors index to access. 9414 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9415 * (module 0 is mapped to sensor_index 64). 9416 * Access: Index 9417 */ 9418 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9419 9420 /* Convert to milli degrees Celsius */ 9421 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9422 ((v_) >= 0) ? ((v_) * 125) : \ 9423 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9424 * 125)); }) 9425 9426 /* reg_mtmp_max_operational_temperature 9427 * The highest temperature in the nominal operational range. Reading is in 9428 * 0.125 Celsius degrees units. 9429 * In case of module this is SFF critical temperature threshold. 9430 * Access: RO 9431 */ 9432 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9433 9434 /* reg_mtmp_temperature 9435 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9436 * degrees units. 9437 * Access: RO 9438 */ 9439 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9440 9441 /* reg_mtmp_mte 9442 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9443 * Access: RW 9444 */ 9445 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9446 9447 /* reg_mtmp_mtr 9448 * Max Temperature Reset - clears the value of the max temperature register. 9449 * Access: WO 9450 */ 9451 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9452 9453 /* reg_mtmp_max_temperature 9454 * The highest measured temperature from the sensor. 9455 * When the bit mte is cleared, the field max_temperature is reserved. 9456 * Access: RO 9457 */ 9458 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9459 9460 /* reg_mtmp_tee 9461 * Temperature Event Enable. 9462 * 0 - Do not generate event 9463 * 1 - Generate event 9464 * 2 - Generate single event 9465 * Access: RW 9466 */ 9467 9468 enum mlxsw_reg_mtmp_tee { 9469 MLXSW_REG_MTMP_TEE_NO_EVENT, 9470 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9471 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9472 }; 9473 9474 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9475 9476 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9477 9478 /* reg_mtmp_temperature_threshold_hi 9479 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9480 * Access: RW 9481 */ 9482 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9483 9484 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9485 /* reg_mtmp_temperature_threshold_lo 9486 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9487 * Access: RW 9488 */ 9489 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9490 9491 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9492 9493 /* reg_mtmp_sensor_name 9494 * Sensor Name 9495 * Access: RO 9496 */ 9497 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9498 9499 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9500 u16 sensor_index, bool max_temp_enable, 9501 bool max_temp_reset) 9502 { 9503 MLXSW_REG_ZERO(mtmp, payload); 9504 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9505 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9506 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9507 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9508 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9509 MLXSW_REG_MTMP_THRESH_HI); 9510 } 9511 9512 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9513 int *p_max_temp, int *p_temp_hi, 9514 int *p_max_oper_temp, 9515 char *sensor_name) 9516 { 9517 s16 temp; 9518 9519 if (p_temp) { 9520 temp = mlxsw_reg_mtmp_temperature_get(payload); 9521 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9522 } 9523 if (p_max_temp) { 9524 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9525 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9526 } 9527 if (p_temp_hi) { 9528 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9529 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9530 } 9531 if (p_max_oper_temp) { 9532 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9533 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9534 } 9535 if (sensor_name) 9536 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9537 } 9538 9539 /* MTWE - Management Temperature Warning Event 9540 * ------------------------------------------- 9541 * This register is used for over temperature warning. 9542 */ 9543 #define MLXSW_REG_MTWE_ID 0x900B 9544 #define MLXSW_REG_MTWE_LEN 0x10 9545 9546 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9547 9548 /* reg_mtwe_sensor_warning 9549 * Bit vector indicating which of the sensor reading is above threshold. 9550 * Address 00h bit31 is sensor_warning[127]. 9551 * Address 0Ch bit0 is sensor_warning[0]. 9552 * Access: RO 9553 */ 9554 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9555 9556 /* MTBR - Management Temperature Bulk Register 9557 * ------------------------------------------- 9558 * This register is used for bulk temperature reading. 9559 */ 9560 #define MLXSW_REG_MTBR_ID 0x900F 9561 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9562 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9563 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9564 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9565 MLXSW_REG_MTBR_REC_LEN * \ 9566 MLXSW_REG_MTBR_REC_MAX_COUNT) 9567 9568 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9569 9570 /* reg_mtbr_slot_index 9571 * Slot index (0: Main board). 9572 * Access: Index 9573 */ 9574 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9575 9576 /* reg_mtbr_base_sensor_index 9577 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9578 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9579 * Access: Index 9580 */ 9581 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9582 9583 /* reg_mtbr_num_rec 9584 * Request: Number of records to read 9585 * Response: Number of records read 9586 * See above description for more details. 9587 * Range 1..255 9588 * Access: RW 9589 */ 9590 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9591 9592 /* reg_mtbr_rec_max_temp 9593 * The highest measured temperature from the sensor. 9594 * When the bit mte is cleared, the field max_temperature is reserved. 9595 * Access: RO 9596 */ 9597 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9598 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9599 9600 /* reg_mtbr_rec_temp 9601 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9602 * degrees units. 9603 * Access: RO 9604 */ 9605 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9606 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9607 9608 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9609 u16 base_sensor_index, u8 num_rec) 9610 { 9611 MLXSW_REG_ZERO(mtbr, payload); 9612 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9613 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9614 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9615 } 9616 9617 /* Error codes from temperatute reading */ 9618 enum mlxsw_reg_mtbr_temp_status { 9619 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9620 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9621 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9622 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9623 }; 9624 9625 /* Base index for reading modules temperature */ 9626 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9627 9628 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9629 u16 *p_temp, u16 *p_max_temp) 9630 { 9631 if (p_temp) 9632 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9633 if (p_max_temp) 9634 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9635 } 9636 9637 /* MCIA - Management Cable Info Access 9638 * ----------------------------------- 9639 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9640 */ 9641 9642 #define MLXSW_REG_MCIA_ID 0x9014 9643 #define MLXSW_REG_MCIA_LEN 0x94 9644 9645 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9646 9647 /* reg_mcia_module 9648 * Module number. 9649 * Access: Index 9650 */ 9651 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9652 9653 /* reg_mcia_slot_index 9654 * Slot index (0: Main board) 9655 * Access: Index 9656 */ 9657 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9658 9659 enum { 9660 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9661 /* No response from module's EEPROM. */ 9662 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9663 /* Module type not supported by the device. */ 9664 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9665 /* No module present indication. */ 9666 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9667 /* Error occurred while trying to access module's EEPROM using I2C. */ 9668 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9669 /* Module is disabled. */ 9670 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9671 }; 9672 9673 /* reg_mcia_status 9674 * Module status. 9675 * Access: RO 9676 */ 9677 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9678 9679 /* reg_mcia_i2c_device_address 9680 * I2C device address. 9681 * Access: RW 9682 */ 9683 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9684 9685 /* reg_mcia_page_number 9686 * Page number. 9687 * Access: RW 9688 */ 9689 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9690 9691 /* reg_mcia_device_address 9692 * Device address. 9693 * Access: RW 9694 */ 9695 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9696 9697 /* reg_mcia_bank_number 9698 * Bank number. 9699 * Access: Index 9700 */ 9701 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9702 9703 /* reg_mcia_size 9704 * Number of bytes to read/write (up to 48 bytes). 9705 * Access: RW 9706 */ 9707 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9708 9709 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9710 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9711 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9712 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9713 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9714 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9715 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9716 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9717 #define MLXSW_REG_MCIA_PAGE0_LO 0 9718 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9719 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9720 9721 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9722 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9723 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9724 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9725 }; 9726 9727 enum mlxsw_reg_mcia_eeprom_module_info_id { 9728 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9729 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9730 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9731 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9732 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9733 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9734 }; 9735 9736 enum mlxsw_reg_mcia_eeprom_module_info { 9737 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9738 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9739 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9740 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9741 }; 9742 9743 /* reg_mcia_eeprom 9744 * Bytes to read/write. 9745 * Access: RW 9746 */ 9747 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, 128); 9748 9749 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9750 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9751 * on offset 384 through 511, page 3 - on offset 512 through 639. 9752 */ 9753 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9754 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9755 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9756 9757 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9758 u8 page_number, u16 device_addr, u8 size, 9759 u8 i2c_device_addr) 9760 { 9761 MLXSW_REG_ZERO(mcia, payload); 9762 mlxsw_reg_mcia_slot_set(payload, slot_index); 9763 mlxsw_reg_mcia_module_set(payload, module); 9764 mlxsw_reg_mcia_page_number_set(payload, page_number); 9765 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9766 mlxsw_reg_mcia_size_set(payload, size); 9767 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9768 } 9769 9770 /* MPAT - Monitoring Port Analyzer Table 9771 * ------------------------------------- 9772 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9773 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9774 */ 9775 #define MLXSW_REG_MPAT_ID 0x901A 9776 #define MLXSW_REG_MPAT_LEN 0x78 9777 9778 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9779 9780 /* reg_mpat_pa_id 9781 * Port Analyzer ID. 9782 * Access: Index 9783 */ 9784 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9785 9786 /* reg_mpat_session_id 9787 * Mirror Session ID. 9788 * Used for MIRROR_SESSION<i> trap. 9789 * Access: RW 9790 */ 9791 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9792 9793 /* reg_mpat_system_port 9794 * A unique port identifier for the final destination of the packet. 9795 * Access: RW 9796 */ 9797 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9798 9799 /* reg_mpat_e 9800 * Enable. Indicating the Port Analyzer is enabled. 9801 * Access: RW 9802 */ 9803 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9804 9805 /* reg_mpat_qos 9806 * Quality Of Service Mode. 9807 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9808 * PCP, DEI, DSCP or VL) are configured. 9809 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9810 * same as in the original packet that has triggered the mirroring. For 9811 * SPAN also the pcp,dei are maintained. 9812 * Access: RW 9813 */ 9814 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9815 9816 /* reg_mpat_be 9817 * Best effort mode. Indicates mirroring traffic should not cause packet 9818 * drop or back pressure, but will discard the mirrored packets. Mirrored 9819 * packets will be forwarded on a best effort manner. 9820 * 0: Do not discard mirrored packets 9821 * 1: Discard mirrored packets if causing congestion 9822 * Access: RW 9823 */ 9824 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9825 9826 enum mlxsw_reg_mpat_span_type { 9827 /* Local SPAN Ethernet. 9828 * The original packet is not encapsulated. 9829 */ 9830 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9831 9832 /* Remote SPAN Ethernet VLAN. 9833 * The packet is forwarded to the monitoring port on the monitoring 9834 * VLAN. 9835 */ 9836 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9837 9838 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9839 * The packet is encapsulated with GRE header. 9840 */ 9841 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9842 }; 9843 9844 /* reg_mpat_span_type 9845 * SPAN type. 9846 * Access: RW 9847 */ 9848 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9849 9850 /* reg_mpat_pide 9851 * Policer enable. 9852 * Access: RW 9853 */ 9854 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9855 9856 /* reg_mpat_pid 9857 * Policer ID. 9858 * Access: RW 9859 */ 9860 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9861 9862 /* Remote SPAN - Ethernet VLAN 9863 * - - - - - - - - - - - - - - 9864 */ 9865 9866 /* reg_mpat_eth_rspan_vid 9867 * Encapsulation header VLAN ID. 9868 * Access: RW 9869 */ 9870 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9871 9872 /* Encapsulated Remote SPAN - Ethernet L2 9873 * - - - - - - - - - - - - - - - - - - - 9874 */ 9875 9876 enum mlxsw_reg_mpat_eth_rspan_version { 9877 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9878 }; 9879 9880 /* reg_mpat_eth_rspan_version 9881 * RSPAN mirror header version. 9882 * Access: RW 9883 */ 9884 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9885 9886 /* reg_mpat_eth_rspan_mac 9887 * Destination MAC address. 9888 * Access: RW 9889 */ 9890 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9891 9892 /* reg_mpat_eth_rspan_tp 9893 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9894 * Access: RW 9895 */ 9896 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9897 9898 /* Encapsulated Remote SPAN - Ethernet L3 9899 * - - - - - - - - - - - - - - - - - - - 9900 */ 9901 9902 enum mlxsw_reg_mpat_eth_rspan_protocol { 9903 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9904 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9905 }; 9906 9907 /* reg_mpat_eth_rspan_protocol 9908 * SPAN encapsulation protocol. 9909 * Access: RW 9910 */ 9911 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9912 9913 /* reg_mpat_eth_rspan_ttl 9914 * Encapsulation header Time-to-Live/HopLimit. 9915 * Access: RW 9916 */ 9917 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9918 9919 /* reg_mpat_eth_rspan_smac 9920 * Source MAC address 9921 * Access: RW 9922 */ 9923 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9924 9925 /* reg_mpat_eth_rspan_dip* 9926 * Destination IP address. The IP version is configured by protocol. 9927 * Access: RW 9928 */ 9929 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9930 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9931 9932 /* reg_mpat_eth_rspan_sip* 9933 * Source IP address. The IP version is configured by protocol. 9934 * Access: RW 9935 */ 9936 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9937 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9938 9939 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9940 u16 system_port, bool e, 9941 enum mlxsw_reg_mpat_span_type span_type) 9942 { 9943 MLXSW_REG_ZERO(mpat, payload); 9944 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9945 mlxsw_reg_mpat_system_port_set(payload, system_port); 9946 mlxsw_reg_mpat_e_set(payload, e); 9947 mlxsw_reg_mpat_qos_set(payload, 1); 9948 mlxsw_reg_mpat_be_set(payload, 1); 9949 mlxsw_reg_mpat_span_type_set(payload, span_type); 9950 } 9951 9952 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9953 { 9954 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9955 } 9956 9957 static inline void 9958 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9959 enum mlxsw_reg_mpat_eth_rspan_version version, 9960 const char *mac, 9961 bool tp) 9962 { 9963 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9964 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9965 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9966 } 9967 9968 static inline void 9969 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9970 const char *smac, 9971 u32 sip, u32 dip) 9972 { 9973 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9974 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9975 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9976 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9977 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9978 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9979 } 9980 9981 static inline void 9982 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9983 const char *smac, 9984 struct in6_addr sip, struct in6_addr dip) 9985 { 9986 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9987 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9988 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9989 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9990 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9991 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9992 } 9993 9994 /* MPAR - Monitoring Port Analyzer Register 9995 * ---------------------------------------- 9996 * MPAR register is used to query and configure the port analyzer port mirroring 9997 * properties. 9998 */ 9999 #define MLXSW_REG_MPAR_ID 0x901B 10000 #define MLXSW_REG_MPAR_LEN 0x0C 10001 10002 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10003 10004 /* reg_mpar_local_port 10005 * The local port to mirror the packets from. 10006 * Access: Index 10007 */ 10008 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10009 10010 enum mlxsw_reg_mpar_i_e { 10011 MLXSW_REG_MPAR_TYPE_EGRESS, 10012 MLXSW_REG_MPAR_TYPE_INGRESS, 10013 }; 10014 10015 /* reg_mpar_i_e 10016 * Ingress/Egress 10017 * Access: Index 10018 */ 10019 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10020 10021 /* reg_mpar_enable 10022 * Enable mirroring 10023 * By default, port mirroring is disabled for all ports. 10024 * Access: RW 10025 */ 10026 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10027 10028 /* reg_mpar_pa_id 10029 * Port Analyzer ID. 10030 * Access: RW 10031 */ 10032 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10033 10034 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10035 10036 /* reg_mpar_probability_rate 10037 * Sampling rate. 10038 * Valid values are: 1 to 3.5*10^9 10039 * Value of 1 means "sample all". Default is 1. 10040 * Reserved when Spectrum-1. 10041 * Access: RW 10042 */ 10043 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10044 10045 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10046 enum mlxsw_reg_mpar_i_e i_e, 10047 bool enable, u8 pa_id, 10048 u32 probability_rate) 10049 { 10050 MLXSW_REG_ZERO(mpar, payload); 10051 mlxsw_reg_mpar_local_port_set(payload, local_port); 10052 mlxsw_reg_mpar_enable_set(payload, enable); 10053 mlxsw_reg_mpar_i_e_set(payload, i_e); 10054 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10055 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10056 } 10057 10058 /* MGIR - Management General Information Register 10059 * ---------------------------------------------- 10060 * MGIR register allows software to query the hardware and firmware general 10061 * information. 10062 */ 10063 #define MLXSW_REG_MGIR_ID 0x9020 10064 #define MLXSW_REG_MGIR_LEN 0x9C 10065 10066 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10067 10068 /* reg_mgir_hw_info_device_hw_revision 10069 * Access: RO 10070 */ 10071 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10072 10073 /* reg_mgir_fw_info_latency_tlv 10074 * When set, latency-TLV is supported. 10075 * Access: RO 10076 */ 10077 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1); 10078 10079 /* reg_mgir_fw_info_string_tlv 10080 * When set, string-TLV is supported. 10081 * Access: RO 10082 */ 10083 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1); 10084 10085 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10086 10087 /* reg_mgir_fw_info_psid 10088 * PSID (ASCII string). 10089 * Access: RO 10090 */ 10091 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10092 10093 /* reg_mgir_fw_info_extended_major 10094 * Access: RO 10095 */ 10096 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10097 10098 /* reg_mgir_fw_info_extended_minor 10099 * Access: RO 10100 */ 10101 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10102 10103 /* reg_mgir_fw_info_extended_sub_minor 10104 * Access: RO 10105 */ 10106 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10107 10108 static inline void mlxsw_reg_mgir_pack(char *payload) 10109 { 10110 MLXSW_REG_ZERO(mgir, payload); 10111 } 10112 10113 static inline void 10114 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10115 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10116 { 10117 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10118 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10119 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10120 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10121 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10122 } 10123 10124 /* MRSR - Management Reset and Shutdown Register 10125 * --------------------------------------------- 10126 * MRSR register is used to reset or shutdown the switch or 10127 * the entire system (when applicable). 10128 */ 10129 #define MLXSW_REG_MRSR_ID 0x9023 10130 #define MLXSW_REG_MRSR_LEN 0x08 10131 10132 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10133 10134 /* reg_mrsr_command 10135 * Reset/shutdown command 10136 * 0 - do nothing 10137 * 1 - software reset 10138 * Access: WO 10139 */ 10140 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10141 10142 static inline void mlxsw_reg_mrsr_pack(char *payload) 10143 { 10144 MLXSW_REG_ZERO(mrsr, payload); 10145 mlxsw_reg_mrsr_command_set(payload, 1); 10146 } 10147 10148 /* MLCR - Management LED Control Register 10149 * -------------------------------------- 10150 * Controls the system LEDs. 10151 */ 10152 #define MLXSW_REG_MLCR_ID 0x902B 10153 #define MLXSW_REG_MLCR_LEN 0x0C 10154 10155 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10156 10157 /* reg_mlcr_local_port 10158 * Local port number. 10159 * Access: RW 10160 */ 10161 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10162 10163 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10164 10165 /* reg_mlcr_beacon_duration 10166 * Duration of the beacon to be active, in seconds. 10167 * 0x0 - Will turn off the beacon. 10168 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10169 * Access: RW 10170 */ 10171 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10172 10173 /* reg_mlcr_beacon_remain 10174 * Remaining duration of the beacon, in seconds. 10175 * 0xFFFF indicates an infinite amount of time. 10176 * Access: RO 10177 */ 10178 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10179 10180 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10181 bool active) 10182 { 10183 MLXSW_REG_ZERO(mlcr, payload); 10184 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10185 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10186 MLXSW_REG_MLCR_DURATION_MAX : 0); 10187 } 10188 10189 /* MCION - Management Cable IO and Notifications Register 10190 * ------------------------------------------------------ 10191 * The MCION register is used to query transceiver modules' IO pins and other 10192 * notifications. 10193 */ 10194 #define MLXSW_REG_MCION_ID 0x9052 10195 #define MLXSW_REG_MCION_LEN 0x18 10196 10197 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10198 10199 /* reg_mcion_module 10200 * Module number. 10201 * Access: Index 10202 */ 10203 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10204 10205 /* reg_mcion_slot_index 10206 * Slot index. 10207 * Access: Index 10208 */ 10209 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10210 10211 enum { 10212 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10213 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10214 }; 10215 10216 /* reg_mcion_module_status_bits 10217 * Module IO status as defined by SFF. 10218 * Access: RO 10219 */ 10220 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10221 10222 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10223 { 10224 MLXSW_REG_ZERO(mcion, payload); 10225 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10226 mlxsw_reg_mcion_module_set(payload, module); 10227 } 10228 10229 /* MTPPS - Management Pulse Per Second Register 10230 * -------------------------------------------- 10231 * This register provides the device PPS capabilities, configure the PPS in and 10232 * out modules and holds the PPS in time stamp. 10233 */ 10234 #define MLXSW_REG_MTPPS_ID 0x9053 10235 #define MLXSW_REG_MTPPS_LEN 0x3C 10236 10237 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10238 10239 /* reg_mtpps_enable 10240 * Enables the PPS functionality the specific pin. 10241 * A boolean variable. 10242 * Access: RW 10243 */ 10244 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10245 10246 enum mlxsw_reg_mtpps_pin_mode { 10247 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10248 }; 10249 10250 /* reg_mtpps_pin_mode 10251 * Pin mode to be used. The mode must comply with the supported modes of the 10252 * requested pin. 10253 * Access: RW 10254 */ 10255 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10256 10257 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10258 10259 /* reg_mtpps_pin 10260 * Pin to be configured or queried out of the supported pins. 10261 * Access: Index 10262 */ 10263 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10264 10265 /* reg_mtpps_time_stamp 10266 * When pin_mode = pps_in, the latched device time when it was triggered from 10267 * the external GPIO pin. 10268 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10269 * time to generate next output signal. 10270 * Time is in units of device clock. 10271 * Access: RW 10272 */ 10273 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10274 10275 static inline void 10276 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10277 { 10278 MLXSW_REG_ZERO(mtpps, payload); 10279 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10280 mlxsw_reg_mtpps_pin_mode_set(payload, 10281 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10282 mlxsw_reg_mtpps_enable_set(payload, true); 10283 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10284 } 10285 10286 /* MTUTC - Management UTC Register 10287 * ------------------------------- 10288 * Configures the HW UTC counter. 10289 */ 10290 #define MLXSW_REG_MTUTC_ID 0x9055 10291 #define MLXSW_REG_MTUTC_LEN 0x1C 10292 10293 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10294 10295 enum mlxsw_reg_mtutc_operation { 10296 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10297 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10298 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10299 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10300 }; 10301 10302 /* reg_mtutc_operation 10303 * Operation. 10304 * Access: OP 10305 */ 10306 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10307 10308 /* reg_mtutc_freq_adjustment 10309 * Frequency adjustment: Every PPS the HW frequency will be 10310 * adjusted by this value. Units of HW clock, where HW counts 10311 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10312 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10313 * frequency. 10314 * Access: RW 10315 */ 10316 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10317 10318 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10319 10320 /* reg_mtutc_utc_sec 10321 * UTC seconds. 10322 * Access: WO 10323 */ 10324 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10325 10326 /* reg_mtutc_utc_nsec 10327 * UTC nSecs. 10328 * Range 0..(10^9-1) 10329 * Updated when operation is SET_TIME_IMMEDIATE. 10330 * Reserved on Spectrum-1. 10331 * Access: WO 10332 */ 10333 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10334 10335 /* reg_mtutc_time_adjustment 10336 * Time adjustment. 10337 * Units of nSec. 10338 * Range is from -32768 to +32767. 10339 * Updated when operation is ADJUST_TIME. 10340 * Reserved on Spectrum-1. 10341 * Access: WO 10342 */ 10343 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10344 10345 static inline void 10346 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10347 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10348 { 10349 MLXSW_REG_ZERO(mtutc, payload); 10350 mlxsw_reg_mtutc_operation_set(payload, oper); 10351 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10352 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10353 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10354 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10355 } 10356 10357 /* MCQI - Management Component Query Information 10358 * --------------------------------------------- 10359 * This register allows querying information about firmware components. 10360 */ 10361 #define MLXSW_REG_MCQI_ID 0x9061 10362 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10363 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10364 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10365 10366 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10367 10368 /* reg_mcqi_component_index 10369 * Index of the accessed component. 10370 * Access: Index 10371 */ 10372 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10373 10374 enum mlxfw_reg_mcqi_info_type { 10375 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10376 }; 10377 10378 /* reg_mcqi_info_type 10379 * Component properties set. 10380 * Access: RW 10381 */ 10382 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10383 10384 /* reg_mcqi_offset 10385 * The requested/returned data offset from the section start, given in bytes. 10386 * Must be DWORD aligned. 10387 * Access: RW 10388 */ 10389 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10390 10391 /* reg_mcqi_data_size 10392 * The requested/returned data size, given in bytes. If data_size is not DWORD 10393 * aligned, the last bytes are zero padded. 10394 * Access: RW 10395 */ 10396 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10397 10398 /* reg_mcqi_cap_max_component_size 10399 * Maximum size for this component, given in bytes. 10400 * Access: RO 10401 */ 10402 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10403 10404 /* reg_mcqi_cap_log_mcda_word_size 10405 * Log 2 of the access word size in bytes. Read and write access must be aligned 10406 * to the word size. Write access must be done for an integer number of words. 10407 * Access: RO 10408 */ 10409 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10410 10411 /* reg_mcqi_cap_mcda_max_write_size 10412 * Maximal write size for MCDA register 10413 * Access: RO 10414 */ 10415 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10416 10417 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10418 { 10419 MLXSW_REG_ZERO(mcqi, payload); 10420 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10421 mlxsw_reg_mcqi_info_type_set(payload, 10422 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10423 mlxsw_reg_mcqi_offset_set(payload, 0); 10424 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10425 } 10426 10427 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10428 u32 *p_cap_max_component_size, 10429 u8 *p_cap_log_mcda_word_size, 10430 u16 *p_cap_mcda_max_write_size) 10431 { 10432 *p_cap_max_component_size = 10433 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10434 *p_cap_log_mcda_word_size = 10435 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10436 *p_cap_mcda_max_write_size = 10437 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10438 } 10439 10440 /* MCC - Management Component Control 10441 * ---------------------------------- 10442 * Controls the firmware component and updates the FSM. 10443 */ 10444 #define MLXSW_REG_MCC_ID 0x9062 10445 #define MLXSW_REG_MCC_LEN 0x1C 10446 10447 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10448 10449 enum mlxsw_reg_mcc_instruction { 10450 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10451 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10452 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10453 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10454 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10455 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10456 }; 10457 10458 /* reg_mcc_instruction 10459 * Command to be executed by the FSM. 10460 * Applicable for write operation only. 10461 * Access: RW 10462 */ 10463 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10464 10465 /* reg_mcc_component_index 10466 * Index of the accessed component. Applicable only for commands that 10467 * refer to components. Otherwise, this field is reserved. 10468 * Access: Index 10469 */ 10470 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10471 10472 /* reg_mcc_update_handle 10473 * Token representing the current flow executed by the FSM. 10474 * Access: WO 10475 */ 10476 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10477 10478 /* reg_mcc_error_code 10479 * Indicates the successful completion of the instruction, or the reason it 10480 * failed 10481 * Access: RO 10482 */ 10483 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10484 10485 /* reg_mcc_control_state 10486 * Current FSM state 10487 * Access: RO 10488 */ 10489 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10490 10491 /* reg_mcc_component_size 10492 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10493 * the size may shorten the update time. Value 0x0 means that size is 10494 * unspecified. 10495 * Access: WO 10496 */ 10497 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10498 10499 static inline void mlxsw_reg_mcc_pack(char *payload, 10500 enum mlxsw_reg_mcc_instruction instr, 10501 u16 component_index, u32 update_handle, 10502 u32 component_size) 10503 { 10504 MLXSW_REG_ZERO(mcc, payload); 10505 mlxsw_reg_mcc_instruction_set(payload, instr); 10506 mlxsw_reg_mcc_component_index_set(payload, component_index); 10507 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10508 mlxsw_reg_mcc_component_size_set(payload, component_size); 10509 } 10510 10511 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10512 u8 *p_error_code, u8 *p_control_state) 10513 { 10514 if (p_update_handle) 10515 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10516 if (p_error_code) 10517 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10518 if (p_control_state) 10519 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10520 } 10521 10522 /* MCDA - Management Component Data Access 10523 * --------------------------------------- 10524 * This register allows reading and writing a firmware component. 10525 */ 10526 #define MLXSW_REG_MCDA_ID 0x9063 10527 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10528 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10529 #define MLXSW_REG_MCDA_LEN \ 10530 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10531 10532 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10533 10534 /* reg_mcda_update_handle 10535 * Token representing the current flow executed by the FSM. 10536 * Access: RW 10537 */ 10538 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10539 10540 /* reg_mcda_offset 10541 * Offset of accessed address relative to component start. Accesses must be in 10542 * accordance to log_mcda_word_size in MCQI reg. 10543 * Access: RW 10544 */ 10545 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10546 10547 /* reg_mcda_size 10548 * Size of the data accessed, given in bytes. 10549 * Access: RW 10550 */ 10551 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10552 10553 /* reg_mcda_data 10554 * Data block accessed. 10555 * Access: RW 10556 */ 10557 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10558 10559 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10560 u32 offset, u16 size, u8 *data) 10561 { 10562 int i; 10563 10564 MLXSW_REG_ZERO(mcda, payload); 10565 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10566 mlxsw_reg_mcda_offset_set(payload, offset); 10567 mlxsw_reg_mcda_size_set(payload, size); 10568 10569 for (i = 0; i < size / 4; i++) 10570 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10571 } 10572 10573 /* MCAM - Management Capabilities Mask Register 10574 * -------------------------------------------- 10575 * Reports the device supported management features. 10576 */ 10577 #define MLXSW_REG_MCAM_ID 0x907F 10578 #define MLXSW_REG_MCAM_LEN 0x48 10579 10580 MLXSW_REG_DEFINE(mcam, MLXSW_REG_MCAM_ID, MLXSW_REG_MCAM_LEN); 10581 10582 enum mlxsw_reg_mcam_feature_group { 10583 /* Enhanced features. */ 10584 MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES, 10585 }; 10586 10587 /* reg_mcam_feature_group 10588 * Feature list mask index. 10589 * Access: Index 10590 */ 10591 MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8); 10592 10593 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits { 10594 /* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */ 10595 MLXSW_REG_MCAM_MCIA_128B = 34, 10596 }; 10597 10598 #define MLXSW_REG_BYTES_PER_DWORD 0x4 10599 10600 /* reg_mcam_mng_feature_cap_mask 10601 * Supported port's enhanced features. 10602 * Based on feature_group index. 10603 * When bit is set, the feature is supported in the device. 10604 * Access: RO 10605 */ 10606 #define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset) \ 10607 MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \ 10608 _offset, MLXSW_REG_BYTES_PER_DWORD, 1) 10609 10610 /* The access to the bits in the field 'mng_feature_cap_mask' is not same to 10611 * other mask fields in other registers. In most of the cases bit #0 is the 10612 * first one in the last dword. In MCAM register, the first dword contains bits 10613 * #0-#31 and so on, so the access to the bits is simpler using bit array per 10614 * dword. Declare each dword of 'mng_feature_cap_mask' field separately. 10615 */ 10616 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28); 10617 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C); 10618 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30); 10619 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34); 10620 10621 static inline void 10622 mlxsw_reg_mcam_pack(char *payload, enum mlxsw_reg_mcam_feature_group feat_group) 10623 { 10624 MLXSW_REG_ZERO(mcam, payload); 10625 mlxsw_reg_mcam_feature_group_set(payload, feat_group); 10626 } 10627 10628 static inline void 10629 mlxsw_reg_mcam_unpack(char *payload, 10630 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit, 10631 bool *p_mng_feature_cap_val) 10632 { 10633 int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); 10634 int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); 10635 u8 (*getters[])(const char *, u16) = { 10636 mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get, 10637 mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get, 10638 mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get, 10639 mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get, 10640 }; 10641 10642 if (!WARN_ON_ONCE(dword >= ARRAY_SIZE(getters))) 10643 *p_mng_feature_cap_val = getters[dword](payload, offset); 10644 } 10645 10646 /* MPSC - Monitoring Packet Sampling Configuration Register 10647 * -------------------------------------------------------- 10648 * MPSC Register is used to configure the Packet Sampling mechanism. 10649 */ 10650 #define MLXSW_REG_MPSC_ID 0x9080 10651 #define MLXSW_REG_MPSC_LEN 0x1C 10652 10653 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10654 10655 /* reg_mpsc_local_port 10656 * Local port number 10657 * Not supported for CPU port 10658 * Access: Index 10659 */ 10660 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10661 10662 /* reg_mpsc_e 10663 * Enable sampling on port local_port 10664 * Access: RW 10665 */ 10666 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10667 10668 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10669 10670 /* reg_mpsc_rate 10671 * Sampling rate = 1 out of rate packets (with randomization around 10672 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10673 * Access: RW 10674 */ 10675 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10676 10677 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10678 u32 rate) 10679 { 10680 MLXSW_REG_ZERO(mpsc, payload); 10681 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10682 mlxsw_reg_mpsc_e_set(payload, e); 10683 mlxsw_reg_mpsc_rate_set(payload, rate); 10684 } 10685 10686 /* MGPC - Monitoring General Purpose Counter Set Register 10687 * The MGPC register retrieves and sets the General Purpose Counter Set. 10688 */ 10689 #define MLXSW_REG_MGPC_ID 0x9081 10690 #define MLXSW_REG_MGPC_LEN 0x18 10691 10692 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10693 10694 /* reg_mgpc_counter_set_type 10695 * Counter set type. 10696 * Access: OP 10697 */ 10698 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10699 10700 /* reg_mgpc_counter_index 10701 * Counter index. 10702 * Access: Index 10703 */ 10704 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10705 10706 enum mlxsw_reg_mgpc_opcode { 10707 /* Nop */ 10708 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10709 /* Clear counters */ 10710 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10711 }; 10712 10713 /* reg_mgpc_opcode 10714 * Opcode. 10715 * Access: OP 10716 */ 10717 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10718 10719 /* reg_mgpc_byte_counter 10720 * Byte counter value. 10721 * Access: RW 10722 */ 10723 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10724 10725 /* reg_mgpc_packet_counter 10726 * Packet counter value. 10727 * Access: RW 10728 */ 10729 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10730 10731 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10732 enum mlxsw_reg_mgpc_opcode opcode, 10733 enum mlxsw_reg_flow_counter_set_type set_type) 10734 { 10735 MLXSW_REG_ZERO(mgpc, payload); 10736 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10737 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10738 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10739 } 10740 10741 /* MPRS - Monitoring Parsing State Register 10742 * ---------------------------------------- 10743 * The MPRS register is used for setting up the parsing for hash, 10744 * policy-engine and routing. 10745 */ 10746 #define MLXSW_REG_MPRS_ID 0x9083 10747 #define MLXSW_REG_MPRS_LEN 0x14 10748 10749 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10750 10751 /* reg_mprs_parsing_depth 10752 * Minimum parsing depth. 10753 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10754 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10755 * Access: RW 10756 */ 10757 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10758 10759 /* reg_mprs_parsing_en 10760 * Parsing enable. 10761 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10762 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10763 * Access: RW 10764 */ 10765 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10766 10767 /* reg_mprs_vxlan_udp_dport 10768 * VxLAN UDP destination port. 10769 * Used for identifying VxLAN packets and for dport field in 10770 * encapsulation. Default is 4789. 10771 * Access: RW 10772 */ 10773 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10774 10775 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10776 u16 vxlan_udp_dport) 10777 { 10778 MLXSW_REG_ZERO(mprs, payload); 10779 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10780 mlxsw_reg_mprs_parsing_en_set(payload, true); 10781 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10782 } 10783 10784 /* MOGCR - Monitoring Global Configuration Register 10785 * ------------------------------------------------ 10786 */ 10787 #define MLXSW_REG_MOGCR_ID 0x9086 10788 #define MLXSW_REG_MOGCR_LEN 0x20 10789 10790 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10791 10792 /* reg_mogcr_ptp_iftc 10793 * PTP Ingress FIFO Trap Clear 10794 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10795 * to this value. Default 0. 10796 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10797 * Access: RW 10798 */ 10799 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10800 10801 /* reg_mogcr_ptp_eftc 10802 * PTP Egress FIFO Trap Clear 10803 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10804 * to this value. Default 0. 10805 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10806 * Access: RW 10807 */ 10808 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10809 10810 /* reg_mogcr_mirroring_pid_base 10811 * Base policer id for mirroring policers. 10812 * Must have an even value (e.g. 1000, not 1001). 10813 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10814 * Access: RW 10815 */ 10816 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10817 10818 /* MPAGR - Monitoring Port Analyzer Global Register 10819 * ------------------------------------------------ 10820 * This register is used for global port analyzer configurations. 10821 * Note: This register is not supported by current FW versions for Spectrum-1. 10822 */ 10823 #define MLXSW_REG_MPAGR_ID 0x9089 10824 #define MLXSW_REG_MPAGR_LEN 0x0C 10825 10826 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10827 10828 enum mlxsw_reg_mpagr_trigger { 10829 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10830 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10831 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10832 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10833 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10834 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10835 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10836 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10837 }; 10838 10839 /* reg_mpagr_trigger 10840 * Mirror trigger. 10841 * Access: Index 10842 */ 10843 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10844 10845 /* reg_mpagr_pa_id 10846 * Port analyzer ID. 10847 * Access: RW 10848 */ 10849 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10850 10851 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10852 10853 /* reg_mpagr_probability_rate 10854 * Sampling rate. 10855 * Valid values are: 1 to 3.5*10^9 10856 * Value of 1 means "sample all". Default is 1. 10857 * Access: RW 10858 */ 10859 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10860 10861 static inline void mlxsw_reg_mpagr_pack(char *payload, 10862 enum mlxsw_reg_mpagr_trigger trigger, 10863 u8 pa_id, u32 probability_rate) 10864 { 10865 MLXSW_REG_ZERO(mpagr, payload); 10866 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10867 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10868 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10869 } 10870 10871 /* MOMTE - Monitoring Mirror Trigger Enable Register 10872 * ------------------------------------------------- 10873 * This register is used to configure the mirror enable for different mirror 10874 * reasons. 10875 */ 10876 #define MLXSW_REG_MOMTE_ID 0x908D 10877 #define MLXSW_REG_MOMTE_LEN 0x10 10878 10879 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10880 10881 /* reg_momte_local_port 10882 * Local port number. 10883 * Access: Index 10884 */ 10885 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10886 10887 enum mlxsw_reg_momte_type { 10888 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10889 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10890 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10891 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10892 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10893 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10894 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10895 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10896 }; 10897 10898 /* reg_momte_type 10899 * Type of mirroring. 10900 * Access: Index 10901 */ 10902 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10903 10904 /* reg_momte_tclass_en 10905 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10906 * 0: disable (default) 10907 * 1: enable 10908 * Access: RW 10909 */ 10910 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10911 10912 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10913 enum mlxsw_reg_momte_type type) 10914 { 10915 MLXSW_REG_ZERO(momte, payload); 10916 mlxsw_reg_momte_local_port_set(payload, local_port); 10917 mlxsw_reg_momte_type_set(payload, type); 10918 } 10919 10920 /* MTPPPC - Time Precision Packet Port Configuration 10921 * ------------------------------------------------- 10922 * This register serves for configuration of which PTP messages should be 10923 * timestamped. This is a global configuration, despite the register name. 10924 * 10925 * Reserved when Spectrum-2. 10926 */ 10927 #define MLXSW_REG_MTPPPC_ID 0x9090 10928 #define MLXSW_REG_MTPPPC_LEN 0x28 10929 10930 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10931 10932 /* reg_mtpppc_ing_timestamp_message_type 10933 * Bitwise vector of PTP message types to timestamp at ingress. 10934 * MessageType field as defined by IEEE 1588 10935 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10936 * Default all 0 10937 * Access: RW 10938 */ 10939 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10940 10941 /* reg_mtpppc_egr_timestamp_message_type 10942 * Bitwise vector of PTP message types to timestamp at egress. 10943 * MessageType field as defined by IEEE 1588 10944 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10945 * Default all 0 10946 * Access: RW 10947 */ 10948 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10949 10950 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10951 { 10952 MLXSW_REG_ZERO(mtpppc, payload); 10953 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10954 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10955 } 10956 10957 /* MTPPTR - Time Precision Packet Timestamping Reading 10958 * --------------------------------------------------- 10959 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10960 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10961 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10962 * trapped. The sequence number is used to synchronize the timestamp FIFO 10963 * entries and the trapped packets. 10964 * Reserved when Spectrum-2. 10965 */ 10966 10967 #define MLXSW_REG_MTPPTR_ID 0x9091 10968 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10969 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10970 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10971 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10972 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10973 10974 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10975 10976 /* reg_mtpptr_local_port 10977 * Not supported for CPU port. 10978 * Access: Index 10979 */ 10980 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10981 10982 enum mlxsw_reg_mtpptr_dir { 10983 MLXSW_REG_MTPPTR_DIR_INGRESS, 10984 MLXSW_REG_MTPPTR_DIR_EGRESS, 10985 }; 10986 10987 /* reg_mtpptr_dir 10988 * Direction. 10989 * Access: Index 10990 */ 10991 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10992 10993 /* reg_mtpptr_clr 10994 * Clear the records. 10995 * Access: OP 10996 */ 10997 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10998 10999 /* reg_mtpptr_num_rec 11000 * Number of valid records in the response 11001 * Range 0.. cap_ptp_timestamp_fifo 11002 * Access: RO 11003 */ 11004 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 11005 11006 /* reg_mtpptr_rec_message_type 11007 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11008 * (e.g. Bit0: Sync, Bit1: Delay_Req) 11009 * Access: RO 11010 */ 11011 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 11012 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 11013 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11014 11015 /* reg_mtpptr_rec_domain_number 11016 * DomainNumber field as defined by IEEE 1588 11017 * Access: RO 11018 */ 11019 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 11020 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 11021 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11022 11023 /* reg_mtpptr_rec_sequence_id 11024 * SequenceId field as defined by IEEE 1588 11025 * Access: RO 11026 */ 11027 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 11028 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 11029 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 11030 11031 /* reg_mtpptr_rec_timestamp_high 11032 * Timestamp of when the PTP packet has passed through the port Units of PLL 11033 * clock time. 11034 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 11035 * Access: RO 11036 */ 11037 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 11038 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11039 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 11040 11041 /* reg_mtpptr_rec_timestamp_low 11042 * See rec_timestamp_high. 11043 * Access: RO 11044 */ 11045 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 11046 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11047 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 11048 11049 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 11050 unsigned int rec, 11051 u8 *p_message_type, 11052 u8 *p_domain_number, 11053 u16 *p_sequence_id, 11054 u64 *p_timestamp) 11055 { 11056 u32 timestamp_high, timestamp_low; 11057 11058 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 11059 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 11060 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 11061 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11062 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11063 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11064 } 11065 11066 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11067 * --------------------------------------------------------- 11068 * This register is used for configuring under which trap to deliver PTP 11069 * packets depending on type of the packet. 11070 */ 11071 #define MLXSW_REG_MTPTPT_ID 0x9092 11072 #define MLXSW_REG_MTPTPT_LEN 0x08 11073 11074 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11075 11076 enum mlxsw_reg_mtptpt_trap_id { 11077 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11078 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11079 }; 11080 11081 /* reg_mtptpt_trap_id 11082 * Trap id. 11083 * Access: Index 11084 */ 11085 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11086 11087 /* reg_mtptpt_message_type 11088 * Bitwise vector of PTP message types to trap. This is a necessary but 11089 * non-sufficient condition since need to enable also per port. See MTPPPC. 11090 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11091 * Bit0: Sync, Bit1: Delay_Req) 11092 */ 11093 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11094 11095 static inline void mlxsw_reg_mtptpt_pack(char *payload, 11096 enum mlxsw_reg_mtptpt_trap_id trap_id, 11097 u16 message_type) 11098 { 11099 MLXSW_REG_ZERO(mtptpt, payload); 11100 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11101 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11102 } 11103 11104 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 11105 * ------------------------------------------------------------------------- 11106 */ 11107 #define MLXSW_REG_MTPCPC_ID 0x9093 11108 #define MLXSW_REG_MTPCPC_LEN 0x2C 11109 11110 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 11111 11112 /* reg_mtpcpc_pport 11113 * Per port: 11114 * 0: config is global. When reading - the local_port is 1. 11115 * 1: config is per port. 11116 * Access: Index 11117 */ 11118 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 11119 11120 /* reg_mtpcpc_local_port 11121 * Local port number. 11122 * Supported to/from CPU port. 11123 * Reserved when pport = 0. 11124 * Access: Index 11125 */ 11126 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 11127 11128 /* reg_mtpcpc_ptp_trap_en 11129 * Enable PTP traps. 11130 * The trap_id is configured by MTPTPT. 11131 * Access: RW 11132 */ 11133 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 11134 11135 /* reg_mtpcpc_ing_correction_message_type 11136 * Bitwise vector of PTP message types to update correction-field at ingress. 11137 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11138 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11139 * Default all 0 11140 * Access: RW 11141 */ 11142 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 11143 11144 /* reg_mtpcpc_egr_correction_message_type 11145 * Bitwise vector of PTP message types to update correction-field at egress. 11146 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11147 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11148 * Default all 0 11149 * Access: RW 11150 */ 11151 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 11152 11153 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 11154 u16 local_port, bool ptp_trap_en, 11155 u16 ing, u16 egr) 11156 { 11157 MLXSW_REG_ZERO(mtpcpc, payload); 11158 mlxsw_reg_mtpcpc_pport_set(payload, pport); 11159 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 11160 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 11161 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 11162 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 11163 } 11164 11165 /* MFGD - Monitoring FW General Debug Register 11166 * ------------------------------------------- 11167 */ 11168 #define MLXSW_REG_MFGD_ID 0x90F0 11169 #define MLXSW_REG_MFGD_LEN 0x0C 11170 11171 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11172 11173 /* reg_mfgd_fw_fatal_event_mode 11174 * 0 - don't check FW fatal (default) 11175 * 1 - check FW fatal - enable MFDE trap 11176 * Access: RW 11177 */ 11178 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11179 11180 /* reg_mfgd_trigger_test 11181 * Access: WO 11182 */ 11183 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11184 11185 /* MGPIR - Management General Peripheral Information Register 11186 * ---------------------------------------------------------- 11187 * MGPIR register allows software to query the hardware and 11188 * firmware general information of peripheral entities. 11189 */ 11190 #define MLXSW_REG_MGPIR_ID 0x9100 11191 #define MLXSW_REG_MGPIR_LEN 0xA0 11192 11193 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11194 11195 enum mlxsw_reg_mgpir_device_type { 11196 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11197 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11198 }; 11199 11200 /* mgpir_slot_index 11201 * Slot index (0: Main board). 11202 * Access: Index 11203 */ 11204 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11205 11206 /* mgpir_device_type 11207 * Access: RO 11208 */ 11209 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11210 11211 /* mgpir_devices_per_flash 11212 * Number of devices of device_type per flash (can be shared by few devices). 11213 * Access: RO 11214 */ 11215 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11216 11217 /* mgpir_num_of_devices 11218 * Number of devices of device_type. 11219 * Access: RO 11220 */ 11221 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11222 11223 /* max_modules_per_slot 11224 * Maximum number of modules that can be connected per slot. 11225 * Access: RO 11226 */ 11227 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11228 11229 /* mgpir_num_of_slots 11230 * Number of slots in the system. 11231 * Access: RO 11232 */ 11233 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11234 11235 /* mgpir_num_of_modules 11236 * Number of modules. 11237 * Access: RO 11238 */ 11239 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11240 11241 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11242 { 11243 MLXSW_REG_ZERO(mgpir, payload); 11244 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11245 } 11246 11247 static inline void 11248 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11249 enum mlxsw_reg_mgpir_device_type *device_type, 11250 u8 *devices_per_flash, u8 *num_of_modules, 11251 u8 *num_of_slots) 11252 { 11253 if (num_of_devices) 11254 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11255 if (device_type) 11256 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11257 if (devices_per_flash) 11258 *devices_per_flash = 11259 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11260 if (num_of_modules) 11261 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11262 if (num_of_slots) 11263 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11264 } 11265 11266 /* MBCT - Management Binary Code Transfer Register 11267 * ----------------------------------------------- 11268 * This register allows to transfer binary codes from the host to 11269 * the management FW by transferring it by chunks of maximum 1KB. 11270 */ 11271 #define MLXSW_REG_MBCT_ID 0x9120 11272 #define MLXSW_REG_MBCT_LEN 0x420 11273 11274 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11275 11276 /* reg_mbct_slot_index 11277 * Slot index. 0 is reserved. 11278 * Access: Index 11279 */ 11280 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11281 11282 /* reg_mbct_data_size 11283 * Actual data field size in bytes for the current data transfer. 11284 * Access: WO 11285 */ 11286 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11287 11288 enum mlxsw_reg_mbct_op { 11289 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11290 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11291 MLXSW_REG_MBCT_OP_ACTIVATE, 11292 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11293 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11294 }; 11295 11296 /* reg_mbct_op 11297 * Access: WO 11298 */ 11299 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11300 11301 /* reg_mbct_last 11302 * Indicates that the current data field is the last chunk of the INI. 11303 * Access: WO 11304 */ 11305 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11306 11307 /* reg_mbct_oee 11308 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11309 * was executed and the fsm_state has changed. 11310 * Access: WO 11311 */ 11312 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11313 11314 enum mlxsw_reg_mbct_status { 11315 /* Partial data transfer completed successfully and ready for next 11316 * data transfer. 11317 */ 11318 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11319 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11320 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11321 /* Error - trying to erase INI while it being used. */ 11322 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11323 /* Last data transfer completed, applying magic pattern. */ 11324 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11325 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11326 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11327 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11328 }; 11329 11330 /* reg_mbct_status 11331 * Status. 11332 * Access: RO 11333 */ 11334 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11335 11336 enum mlxsw_reg_mbct_fsm_state { 11337 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11338 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11339 }; 11340 11341 /* reg_mbct_fsm_state 11342 * FSM state. 11343 * Access: RO 11344 */ 11345 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11346 11347 #define MLXSW_REG_MBCT_DATA_LEN 1024 11348 11349 /* reg_mbct_data 11350 * Up to 1KB of data. 11351 * Access: WO 11352 */ 11353 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11354 11355 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11356 enum mlxsw_reg_mbct_op op, bool oee) 11357 { 11358 MLXSW_REG_ZERO(mbct, payload); 11359 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11360 mlxsw_reg_mbct_op_set(payload, op); 11361 mlxsw_reg_mbct_oee_set(payload, oee); 11362 } 11363 11364 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11365 u16 data_size, bool last, 11366 const char *data) 11367 { 11368 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11369 return; 11370 mlxsw_reg_mbct_data_size_set(payload, data_size); 11371 mlxsw_reg_mbct_last_set(payload, last); 11372 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11373 } 11374 11375 static inline void 11376 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11377 enum mlxsw_reg_mbct_status *p_status, 11378 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11379 { 11380 if (p_slot_index) 11381 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11382 *p_status = mlxsw_reg_mbct_status_get(payload); 11383 if (p_fsm_state) 11384 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11385 } 11386 11387 /* MDDT - Management DownStream Device Tunneling Register 11388 * ------------------------------------------------------ 11389 * This register allows to deliver query and request messages (PRM registers, 11390 * commands) to a DownStream device. 11391 */ 11392 #define MLXSW_REG_MDDT_ID 0x9160 11393 #define MLXSW_REG_MDDT_LEN 0x110 11394 11395 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11396 11397 /* reg_mddt_slot_index 11398 * Slot index. 11399 * Access: Index 11400 */ 11401 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11402 11403 /* reg_mddt_device_index 11404 * Device index. 11405 * Access: Index 11406 */ 11407 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11408 11409 /* reg_mddt_read_size 11410 * Read size in D-Words. 11411 * Access: OP 11412 */ 11413 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11414 11415 /* reg_mddt_write_size 11416 * Write size in D-Words. 11417 * Access: OP 11418 */ 11419 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11420 11421 enum mlxsw_reg_mddt_status { 11422 MLXSW_REG_MDDT_STATUS_OK, 11423 }; 11424 11425 /* reg_mddt_status 11426 * Return code of the Downstream Device to the register that was sent. 11427 * Access: RO 11428 */ 11429 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11430 11431 enum mlxsw_reg_mddt_method { 11432 MLXSW_REG_MDDT_METHOD_QUERY, 11433 MLXSW_REG_MDDT_METHOD_WRITE, 11434 }; 11435 11436 /* reg_mddt_method 11437 * Access: OP 11438 */ 11439 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11440 11441 /* reg_mddt_register_id 11442 * Access: Index 11443 */ 11444 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11445 11446 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11447 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11448 11449 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11450 { 11451 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11452 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11453 } 11454 11455 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11456 u8 device_index, 11457 enum mlxsw_reg_mddt_method method, 11458 const struct mlxsw_reg_info *reg, 11459 char **inner_payload) 11460 { 11461 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11462 11463 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11464 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11465 11466 MLXSW_REG_ZERO(mddt, payload); 11467 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11468 mlxsw_reg_mddt_device_index_set(payload, device_index); 11469 mlxsw_reg_mddt_method_set(payload, method); 11470 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11471 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11472 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11473 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11474 } 11475 11476 /* MDDQ - Management DownStream Device Query Register 11477 * -------------------------------------------------- 11478 * This register allows to query the DownStream device properties. The desired 11479 * information is chosen upon the query_type field and is delivered by 32B 11480 * of data blocks. 11481 */ 11482 #define MLXSW_REG_MDDQ_ID 0x9161 11483 #define MLXSW_REG_MDDQ_LEN 0x30 11484 11485 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11486 11487 /* reg_mddq_sie 11488 * Slot info event enable. 11489 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11490 * active / ready will generate a DSDSC event. 11491 * Access: RW 11492 */ 11493 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11494 11495 enum mlxsw_reg_mddq_query_type { 11496 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11497 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11498 * on the slot, data_valid 11499 * will be '0'. 11500 */ 11501 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11502 }; 11503 11504 /* reg_mddq_query_type 11505 * Access: Index 11506 */ 11507 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11508 11509 /* reg_mddq_slot_index 11510 * Slot index. 0 is reserved. 11511 * Access: Index 11512 */ 11513 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11514 11515 /* reg_mddq_response_msg_seq 11516 * Response message sequential number. For a specific request, the response 11517 * message sequential number is the following one. In addition, the last 11518 * message should be 0. 11519 * Access: RO 11520 */ 11521 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11522 11523 /* reg_mddq_request_msg_seq 11524 * Request message sequential number. 11525 * The first message number should be 0. 11526 * Access: Index 11527 */ 11528 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11529 11530 /* reg_mddq_data_valid 11531 * If set, the data in the data field is valid and contain the information 11532 * for the queried index. 11533 * Access: RO 11534 */ 11535 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11536 11537 /* reg_mddq_slot_info_provisioned 11538 * If set, the INI file is applied and the card is provisioned. 11539 * Access: RO 11540 */ 11541 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11542 11543 /* reg_mddq_slot_info_sr_valid 11544 * If set, Shift Register is valid (after being provisioned) and data 11545 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11546 * Access: RO 11547 */ 11548 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11549 11550 enum mlxsw_reg_mddq_slot_info_ready { 11551 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11552 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11553 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11554 }; 11555 11556 /* reg_mddq_slot_info_lc_ready 11557 * If set, the LC is powered on, matching the INI version and a new FW 11558 * version can be burnt (if necessary). 11559 * Access: RO 11560 */ 11561 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11562 11563 /* reg_mddq_slot_info_active 11564 * If set, the FW has completed the MDDC.device_enable command. 11565 * Access: RO 11566 */ 11567 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11568 11569 /* reg_mddq_slot_info_hw_revision 11570 * Major user-configured version number of the current INI file. 11571 * Valid only when active or ready are '1'. 11572 * Access: RO 11573 */ 11574 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11575 11576 /* reg_mddq_slot_info_ini_file_version 11577 * User-configured version number of the current INI file. 11578 * Valid only when active or lc_ready are '1'. 11579 * Access: RO 11580 */ 11581 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11582 11583 /* reg_mddq_slot_info_card_type 11584 * Access: RO 11585 */ 11586 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11587 11588 static inline void 11589 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11590 enum mlxsw_reg_mddq_query_type query_type) 11591 { 11592 MLXSW_REG_ZERO(mddq, payload); 11593 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11594 mlxsw_reg_mddq_query_type_set(payload, query_type); 11595 } 11596 11597 static inline void 11598 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11599 { 11600 __mlxsw_reg_mddq_pack(payload, slot_index, 11601 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11602 mlxsw_reg_mddq_sie_set(payload, sie); 11603 } 11604 11605 static inline void 11606 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11607 bool *p_provisioned, bool *p_sr_valid, 11608 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11609 bool *p_active, u16 *p_hw_revision, 11610 u16 *p_ini_file_version, 11611 u8 *p_card_type) 11612 { 11613 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11614 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11615 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11616 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11617 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11618 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11619 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11620 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11621 } 11622 11623 /* reg_mddq_device_info_flash_owner 11624 * If set, the device is the flash owner. Otherwise, a shared flash 11625 * is used by this device (another device is the flash owner). 11626 * Access: RO 11627 */ 11628 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11629 11630 /* reg_mddq_device_info_device_index 11631 * Device index. The first device should number 0. 11632 * Access: RO 11633 */ 11634 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11635 11636 /* reg_mddq_device_info_fw_major 11637 * Major FW version number. 11638 * Access: RO 11639 */ 11640 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11641 11642 /* reg_mddq_device_info_fw_minor 11643 * Minor FW version number. 11644 * Access: RO 11645 */ 11646 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11647 11648 /* reg_mddq_device_info_fw_sub_minor 11649 * Sub-minor FW version number. 11650 * Access: RO 11651 */ 11652 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11653 11654 static inline void 11655 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11656 u8 request_msg_seq) 11657 { 11658 __mlxsw_reg_mddq_pack(payload, slot_index, 11659 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11660 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11661 } 11662 11663 static inline void 11664 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11665 bool *p_data_valid, bool *p_flash_owner, 11666 u8 *p_device_index, u16 *p_fw_major, 11667 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11668 { 11669 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11670 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11671 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11672 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11673 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11674 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11675 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11676 } 11677 11678 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11679 11680 /* reg_mddq_slot_ascii_name 11681 * Slot's ASCII name. 11682 * Access: RO 11683 */ 11684 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11685 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11686 11687 static inline void 11688 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11689 { 11690 __mlxsw_reg_mddq_pack(payload, slot_index, 11691 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11692 } 11693 11694 static inline void 11695 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11696 { 11697 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11698 } 11699 11700 /* MDDC - Management DownStream Device Control Register 11701 * ---------------------------------------------------- 11702 * This register allows to control downstream devices and line cards. 11703 */ 11704 #define MLXSW_REG_MDDC_ID 0x9163 11705 #define MLXSW_REG_MDDC_LEN 0x30 11706 11707 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11708 11709 /* reg_mddc_slot_index 11710 * Slot index. 0 is reserved. 11711 * Access: Index 11712 */ 11713 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11714 11715 /* reg_mddc_rst 11716 * Reset request. 11717 * Access: OP 11718 */ 11719 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11720 11721 /* reg_mddc_device_enable 11722 * When set, FW is the manager and allowed to program the downstream device. 11723 * Access: RW 11724 */ 11725 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11726 11727 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11728 bool device_enable) 11729 { 11730 MLXSW_REG_ZERO(mddc, payload); 11731 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11732 mlxsw_reg_mddc_rst_set(payload, rst); 11733 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11734 } 11735 11736 /* MFDE - Monitoring FW Debug Register 11737 * ----------------------------------- 11738 */ 11739 #define MLXSW_REG_MFDE_ID 0x9200 11740 #define MLXSW_REG_MFDE_LEN 0x30 11741 11742 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11743 11744 /* reg_mfde_irisc_id 11745 * Which irisc triggered the event 11746 * Access: RO 11747 */ 11748 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11749 11750 enum mlxsw_reg_mfde_severity { 11751 /* Unrecoverable switch behavior */ 11752 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11753 /* Unexpected state with possible systemic failure */ 11754 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11755 /* Unexpected state without systemic failure */ 11756 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11757 }; 11758 11759 /* reg_mfde_severity 11760 * The severity of the event. 11761 * Access: RO 11762 */ 11763 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11764 11765 enum mlxsw_reg_mfde_event_id { 11766 /* CRspace timeout */ 11767 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11768 /* KVD insertion machine stopped */ 11769 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11770 /* Triggered by MFGD.trigger_test */ 11771 MLXSW_REG_MFDE_EVENT_ID_TEST, 11772 /* Triggered when firmware hits an assert */ 11773 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11774 /* Fatal error interrupt from hardware */ 11775 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11776 }; 11777 11778 /* reg_mfde_event_id 11779 * Access: RO 11780 */ 11781 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11782 11783 enum mlxsw_reg_mfde_method { 11784 MLXSW_REG_MFDE_METHOD_QUERY, 11785 MLXSW_REG_MFDE_METHOD_WRITE, 11786 }; 11787 11788 /* reg_mfde_method 11789 * Access: RO 11790 */ 11791 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11792 11793 /* reg_mfde_long_process 11794 * Indicates if the command is in long_process mode. 11795 * Access: RO 11796 */ 11797 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11798 11799 enum mlxsw_reg_mfde_command_type { 11800 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11801 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11802 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11803 }; 11804 11805 /* reg_mfde_command_type 11806 * Access: RO 11807 */ 11808 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11809 11810 /* reg_mfde_reg_attr_id 11811 * EMAD - register id, MAD - attibute id 11812 * Access: RO 11813 */ 11814 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11815 11816 /* reg_mfde_crspace_to_log_address 11817 * crspace address accessed, which resulted in timeout. 11818 * Access: RO 11819 */ 11820 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11821 11822 /* reg_mfde_crspace_to_oe 11823 * 0 - New event 11824 * 1 - Old event, occurred before MFGD activation. 11825 * Access: RO 11826 */ 11827 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11828 11829 /* reg_mfde_crspace_to_log_id 11830 * Which irisc triggered the timeout. 11831 * Access: RO 11832 */ 11833 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11834 11835 /* reg_mfde_crspace_to_log_ip 11836 * IP (instruction pointer) that triggered the timeout. 11837 * Access: RO 11838 */ 11839 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11840 11841 /* reg_mfde_kvd_im_stop_oe 11842 * 0 - New event 11843 * 1 - Old event, occurred before MFGD activation. 11844 * Access: RO 11845 */ 11846 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11847 11848 /* reg_mfde_kvd_im_stop_pipes_mask 11849 * Bit per kvh pipe. 11850 * Access: RO 11851 */ 11852 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11853 11854 /* reg_mfde_fw_assert_var0-4 11855 * Variables passed to assert. 11856 * Access: RO 11857 */ 11858 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11859 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11860 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11861 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11862 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11863 11864 /* reg_mfde_fw_assert_existptr 11865 * The instruction pointer when assert was triggered. 11866 * Access: RO 11867 */ 11868 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11869 11870 /* reg_mfde_fw_assert_callra 11871 * The return address after triggering assert. 11872 * Access: RO 11873 */ 11874 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11875 11876 /* reg_mfde_fw_assert_oe 11877 * 0 - New event 11878 * 1 - Old event, occurred before MFGD activation. 11879 * Access: RO 11880 */ 11881 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11882 11883 /* reg_mfde_fw_assert_tile_v 11884 * 0: The assert was from main 11885 * 1: The assert was from a tile 11886 * Access: RO 11887 */ 11888 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11889 11890 /* reg_mfde_fw_assert_tile_index 11891 * When tile_v=1, the tile_index that caused the assert. 11892 * Access: RO 11893 */ 11894 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11895 11896 /* reg_mfde_fw_assert_ext_synd 11897 * A generated one-to-one identifier which is specific per-assert. 11898 * Access: RO 11899 */ 11900 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11901 11902 /* reg_mfde_fatal_cause_id 11903 * HW interrupt cause id. 11904 * Access: RO 11905 */ 11906 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11907 11908 /* reg_mfde_fatal_cause_tile_v 11909 * 0: The assert was from main 11910 * 1: The assert was from a tile 11911 * Access: RO 11912 */ 11913 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11914 11915 /* reg_mfde_fatal_cause_tile_index 11916 * When tile_v=1, the tile_index that caused the assert. 11917 * Access: RO 11918 */ 11919 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11920 11921 /* TNGCR - Tunneling NVE General Configuration Register 11922 * ---------------------------------------------------- 11923 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11924 */ 11925 #define MLXSW_REG_TNGCR_ID 0xA001 11926 #define MLXSW_REG_TNGCR_LEN 0x44 11927 11928 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11929 11930 enum mlxsw_reg_tngcr_type { 11931 MLXSW_REG_TNGCR_TYPE_VXLAN, 11932 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11933 MLXSW_REG_TNGCR_TYPE_GENEVE, 11934 MLXSW_REG_TNGCR_TYPE_NVGRE, 11935 }; 11936 11937 /* reg_tngcr_type 11938 * Tunnel type for encapsulation and decapsulation. The types are mutually 11939 * exclusive. 11940 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11941 * Access: RW 11942 */ 11943 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11944 11945 /* reg_tngcr_nve_valid 11946 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11947 * Access: RW 11948 */ 11949 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11950 11951 /* reg_tngcr_nve_ttl_uc 11952 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11953 * Access: RW 11954 */ 11955 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11956 11957 /* reg_tngcr_nve_ttl_mc 11958 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11959 * Access: RW 11960 */ 11961 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11962 11963 enum { 11964 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11965 MLXSW_REG_TNGCR_FL_NO_COPY, 11966 /* Copy flow label from inner packet if packet is IPv6 and 11967 * encapsulation is by IPv6. Otherwise, calculate flow label using 11968 * nve_flh. 11969 */ 11970 MLXSW_REG_TNGCR_FL_COPY, 11971 }; 11972 11973 /* reg_tngcr_nve_flc 11974 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11975 * Access: RW 11976 */ 11977 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11978 11979 enum { 11980 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11981 * uses {nve_fl_prefix, nve_fl_suffix}. 11982 */ 11983 MLXSW_REG_TNGCR_FL_NO_HASH, 11984 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11985 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11986 */ 11987 MLXSW_REG_TNGCR_FL_HASH, 11988 }; 11989 11990 /* reg_tngcr_nve_flh 11991 * NVE flow label hash. 11992 * Access: RW 11993 */ 11994 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11995 11996 /* reg_tngcr_nve_fl_prefix 11997 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11998 * Access: RW 11999 */ 12000 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 12001 12002 /* reg_tngcr_nve_fl_suffix 12003 * NVE flow label suffix. Constant 8 LSBs of the flow label. 12004 * Reserved when nve_flh=1 and for Spectrum. 12005 * Access: RW 12006 */ 12007 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 12008 12009 enum { 12010 /* Source UDP port is fixed (default '0') */ 12011 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 12012 /* Source UDP port is calculated based on hash */ 12013 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 12014 }; 12015 12016 /* reg_tngcr_nve_udp_sport_type 12017 * NVE UDP source port type. 12018 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 12019 * When the source UDP port is calculated based on hash, then the 8 LSBs 12020 * are calculated from hash the 8 MSBs are configured by 12021 * nve_udp_sport_prefix. 12022 * Access: RW 12023 */ 12024 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 12025 12026 /* reg_tngcr_nve_udp_sport_prefix 12027 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 12028 * Reserved when NVE type is NVGRE. 12029 * Access: RW 12030 */ 12031 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 12032 12033 /* reg_tngcr_nve_group_size_mc 12034 * The amount of sequential linked lists of MC entries. The first linked 12035 * list is configured by SFD.underlay_mc_ptr. 12036 * Valid values: 1, 2, 4, 8, 16, 32, 64 12037 * The linked list are configured by TNUMT. 12038 * The hash is set by LAG hash. 12039 * Access: RW 12040 */ 12041 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 12042 12043 /* reg_tngcr_nve_group_size_flood 12044 * The amount of sequential linked lists of flooding entries. The first 12045 * linked list is configured by SFMR.nve_tunnel_flood_ptr 12046 * Valid values: 1, 2, 4, 8, 16, 32, 64 12047 * The linked list are configured by TNUMT. 12048 * The hash is set by LAG hash. 12049 * Access: RW 12050 */ 12051 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 12052 12053 /* reg_tngcr_learn_enable 12054 * During decapsulation, whether to learn from NVE port. 12055 * Reserved when Spectrum-2. See TNPC. 12056 * Access: RW 12057 */ 12058 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 12059 12060 /* reg_tngcr_underlay_virtual_router 12061 * Underlay virtual router. 12062 * Reserved when Spectrum-2. 12063 * Access: RW 12064 */ 12065 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 12066 12067 /* reg_tngcr_underlay_rif 12068 * Underlay ingress router interface. RIF type should be loopback generic. 12069 * Reserved when Spectrum. 12070 * Access: RW 12071 */ 12072 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 12073 12074 /* reg_tngcr_usipv4 12075 * Underlay source IPv4 address of the NVE. 12076 * Access: RW 12077 */ 12078 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 12079 12080 /* reg_tngcr_usipv6 12081 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 12082 * modified under traffic of NVE tunneling encapsulation. 12083 * Access: RW 12084 */ 12085 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 12086 12087 static inline void mlxsw_reg_tngcr_pack(char *payload, 12088 enum mlxsw_reg_tngcr_type type, 12089 bool valid, u8 ttl) 12090 { 12091 MLXSW_REG_ZERO(tngcr, payload); 12092 mlxsw_reg_tngcr_type_set(payload, type); 12093 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 12094 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 12095 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 12096 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 12097 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 12098 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 12099 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 12100 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 12101 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 12102 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 12103 } 12104 12105 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 12106 * ------------------------------------------------------- 12107 * The TNUMT register is for building the underlay MC table. It is used 12108 * for MC, flooding and BC traffic into the NVE tunnel. 12109 */ 12110 #define MLXSW_REG_TNUMT_ID 0xA003 12111 #define MLXSW_REG_TNUMT_LEN 0x20 12112 12113 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 12114 12115 enum mlxsw_reg_tnumt_record_type { 12116 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 12117 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 12118 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 12119 }; 12120 12121 /* reg_tnumt_record_type 12122 * Record type. 12123 * Access: RW 12124 */ 12125 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 12126 12127 /* reg_tnumt_tunnel_port 12128 * Tunnel port. 12129 * Access: RW 12130 */ 12131 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 12132 12133 /* reg_tnumt_underlay_mc_ptr 12134 * Index to the underlay multicast table. 12135 * For Spectrum the index is to the KVD linear. 12136 * Access: Index 12137 */ 12138 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 12139 12140 /* reg_tnumt_vnext 12141 * The next_underlay_mc_ptr is valid. 12142 * Access: RW 12143 */ 12144 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 12145 12146 /* reg_tnumt_next_underlay_mc_ptr 12147 * The next index to the underlay multicast table. 12148 * Access: RW 12149 */ 12150 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 12151 12152 /* reg_tnumt_record_size 12153 * Number of IP addresses in the record. 12154 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 12155 * Access: RW 12156 */ 12157 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 12158 12159 /* reg_tnumt_udip 12160 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 12161 * Access: RW 12162 */ 12163 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 12164 12165 /* reg_tnumt_udip_ptr 12166 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 12167 * i >= size. The IPv6 addresses are configured by RIPS. 12168 * Access: RW 12169 */ 12170 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 12171 12172 static inline void mlxsw_reg_tnumt_pack(char *payload, 12173 enum mlxsw_reg_tnumt_record_type type, 12174 enum mlxsw_reg_tunnel_port tport, 12175 u32 underlay_mc_ptr, bool vnext, 12176 u32 next_underlay_mc_ptr, 12177 u8 record_size) 12178 { 12179 MLXSW_REG_ZERO(tnumt, payload); 12180 mlxsw_reg_tnumt_record_type_set(payload, type); 12181 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12182 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12183 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12184 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12185 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12186 } 12187 12188 /* TNQCR - Tunneling NVE QoS Configuration Register 12189 * ------------------------------------------------ 12190 * The TNQCR register configures how QoS is set in encapsulation into the 12191 * underlay network. 12192 */ 12193 #define MLXSW_REG_TNQCR_ID 0xA010 12194 #define MLXSW_REG_TNQCR_LEN 0x0C 12195 12196 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12197 12198 /* reg_tnqcr_enc_set_dscp 12199 * For encapsulation: How to set DSCP field: 12200 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12201 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12202 * 1 - Set the DSCP field as TNQDR.dscp 12203 * Access: RW 12204 */ 12205 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12206 12207 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12208 { 12209 MLXSW_REG_ZERO(tnqcr, payload); 12210 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12211 } 12212 12213 /* TNQDR - Tunneling NVE QoS Default Register 12214 * ------------------------------------------ 12215 * The TNQDR register configures the default QoS settings for NVE 12216 * encapsulation. 12217 */ 12218 #define MLXSW_REG_TNQDR_ID 0xA011 12219 #define MLXSW_REG_TNQDR_LEN 0x08 12220 12221 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12222 12223 /* reg_tnqdr_local_port 12224 * Local port number (receive port). CPU port is supported. 12225 * Access: Index 12226 */ 12227 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12228 12229 /* reg_tnqdr_dscp 12230 * For encapsulation, the default DSCP. 12231 * Access: RW 12232 */ 12233 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12234 12235 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12236 { 12237 MLXSW_REG_ZERO(tnqdr, payload); 12238 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12239 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12240 } 12241 12242 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12243 * -------------------------------------------------------- 12244 * The TNEEM register maps ECN of the IP header at the ingress to the 12245 * encapsulation to the ECN of the underlay network. 12246 */ 12247 #define MLXSW_REG_TNEEM_ID 0xA012 12248 #define MLXSW_REG_TNEEM_LEN 0x0C 12249 12250 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12251 12252 /* reg_tneem_overlay_ecn 12253 * ECN of the IP header in the overlay network. 12254 * Access: Index 12255 */ 12256 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12257 12258 /* reg_tneem_underlay_ecn 12259 * ECN of the IP header in the underlay network. 12260 * Access: RW 12261 */ 12262 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12263 12264 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12265 u8 underlay_ecn) 12266 { 12267 MLXSW_REG_ZERO(tneem, payload); 12268 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12269 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12270 } 12271 12272 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12273 * -------------------------------------------------------- 12274 * The TNDEM register configures the actions that are done in the 12275 * decapsulation. 12276 */ 12277 #define MLXSW_REG_TNDEM_ID 0xA013 12278 #define MLXSW_REG_TNDEM_LEN 0x0C 12279 12280 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12281 12282 /* reg_tndem_underlay_ecn 12283 * ECN field of the IP header in the underlay network. 12284 * Access: Index 12285 */ 12286 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12287 12288 /* reg_tndem_overlay_ecn 12289 * ECN field of the IP header in the overlay network. 12290 * Access: Index 12291 */ 12292 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12293 12294 /* reg_tndem_eip_ecn 12295 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12296 * from the decapsulation. 12297 * Access: RW 12298 */ 12299 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12300 12301 /* reg_tndem_trap_en 12302 * Trap enable: 12303 * 0 - No trap due to decap ECN 12304 * 1 - Trap enable with trap_id 12305 * Access: RW 12306 */ 12307 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12308 12309 /* reg_tndem_trap_id 12310 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12311 * Reserved when trap_en is '0'. 12312 * Access: RW 12313 */ 12314 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12315 12316 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12317 u8 overlay_ecn, u8 ecn, bool trap_en, 12318 u16 trap_id) 12319 { 12320 MLXSW_REG_ZERO(tndem, payload); 12321 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12322 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12323 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12324 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12325 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12326 } 12327 12328 /* TNPC - Tunnel Port Configuration Register 12329 * ----------------------------------------- 12330 * The TNPC register is used for tunnel port configuration. 12331 * Reserved when Spectrum. 12332 */ 12333 #define MLXSW_REG_TNPC_ID 0xA020 12334 #define MLXSW_REG_TNPC_LEN 0x18 12335 12336 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12337 12338 /* reg_tnpc_tunnel_port 12339 * Tunnel port. 12340 * Access: Index 12341 */ 12342 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12343 12344 /* reg_tnpc_learn_enable_v6 12345 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12346 * Access: RW 12347 */ 12348 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12349 12350 /* reg_tnpc_learn_enable_v4 12351 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12352 * Access: RW 12353 */ 12354 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12355 12356 static inline void mlxsw_reg_tnpc_pack(char *payload, 12357 enum mlxsw_reg_tunnel_port tport, 12358 bool learn_enable) 12359 { 12360 MLXSW_REG_ZERO(tnpc, payload); 12361 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12362 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12363 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12364 } 12365 12366 /* TIGCR - Tunneling IPinIP General Configuration Register 12367 * ------------------------------------------------------- 12368 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12369 */ 12370 #define MLXSW_REG_TIGCR_ID 0xA801 12371 #define MLXSW_REG_TIGCR_LEN 0x10 12372 12373 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12374 12375 /* reg_tigcr_ipip_ttlc 12376 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12377 * header. 12378 * Access: RW 12379 */ 12380 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12381 12382 /* reg_tigcr_ipip_ttl_uc 12383 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12384 * reg_tigcr_ipip_ttlc is unset. 12385 * Access: RW 12386 */ 12387 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12388 12389 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12390 { 12391 MLXSW_REG_ZERO(tigcr, payload); 12392 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12393 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12394 } 12395 12396 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12397 * ----------------------------------------------------------- 12398 * The TIEEM register maps ECN of the IP header at the ingress to the 12399 * encapsulation to the ECN of the underlay network. 12400 */ 12401 #define MLXSW_REG_TIEEM_ID 0xA812 12402 #define MLXSW_REG_TIEEM_LEN 0x0C 12403 12404 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12405 12406 /* reg_tieem_overlay_ecn 12407 * ECN of the IP header in the overlay network. 12408 * Access: Index 12409 */ 12410 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12411 12412 /* reg_tineem_underlay_ecn 12413 * ECN of the IP header in the underlay network. 12414 * Access: RW 12415 */ 12416 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12417 12418 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12419 u8 underlay_ecn) 12420 { 12421 MLXSW_REG_ZERO(tieem, payload); 12422 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12423 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12424 } 12425 12426 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12427 * ----------------------------------------------------------- 12428 * The TIDEM register configures the actions that are done in the 12429 * decapsulation. 12430 */ 12431 #define MLXSW_REG_TIDEM_ID 0xA813 12432 #define MLXSW_REG_TIDEM_LEN 0x0C 12433 12434 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12435 12436 /* reg_tidem_underlay_ecn 12437 * ECN field of the IP header in the underlay network. 12438 * Access: Index 12439 */ 12440 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12441 12442 /* reg_tidem_overlay_ecn 12443 * ECN field of the IP header in the overlay network. 12444 * Access: Index 12445 */ 12446 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12447 12448 /* reg_tidem_eip_ecn 12449 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12450 * from the decapsulation. 12451 * Access: RW 12452 */ 12453 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12454 12455 /* reg_tidem_trap_en 12456 * Trap enable: 12457 * 0 - No trap due to decap ECN 12458 * 1 - Trap enable with trap_id 12459 * Access: RW 12460 */ 12461 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12462 12463 /* reg_tidem_trap_id 12464 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12465 * Reserved when trap_en is '0'. 12466 * Access: RW 12467 */ 12468 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12469 12470 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12471 u8 overlay_ecn, u8 eip_ecn, 12472 bool trap_en, u16 trap_id) 12473 { 12474 MLXSW_REG_ZERO(tidem, payload); 12475 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12476 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12477 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12478 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12479 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12480 } 12481 12482 /* SBPR - Shared Buffer Pools Register 12483 * ----------------------------------- 12484 * The SBPR configures and retrieves the shared buffer pools and configuration. 12485 */ 12486 #define MLXSW_REG_SBPR_ID 0xB001 12487 #define MLXSW_REG_SBPR_LEN 0x14 12488 12489 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12490 12491 /* reg_sbpr_desc 12492 * When set, configures descriptor buffer. 12493 * Access: Index 12494 */ 12495 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12496 12497 /* shared direstion enum for SBPR, SBCM, SBPM */ 12498 enum mlxsw_reg_sbxx_dir { 12499 MLXSW_REG_SBXX_DIR_INGRESS, 12500 MLXSW_REG_SBXX_DIR_EGRESS, 12501 }; 12502 12503 /* reg_sbpr_dir 12504 * Direction. 12505 * Access: Index 12506 */ 12507 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12508 12509 /* reg_sbpr_pool 12510 * Pool index. 12511 * Access: Index 12512 */ 12513 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12514 12515 /* reg_sbpr_infi_size 12516 * Size is infinite. 12517 * Access: RW 12518 */ 12519 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12520 12521 /* reg_sbpr_size 12522 * Pool size in buffer cells. 12523 * Reserved when infi_size = 1. 12524 * Access: RW 12525 */ 12526 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12527 12528 enum mlxsw_reg_sbpr_mode { 12529 MLXSW_REG_SBPR_MODE_STATIC, 12530 MLXSW_REG_SBPR_MODE_DYNAMIC, 12531 }; 12532 12533 /* reg_sbpr_mode 12534 * Pool quota calculation mode. 12535 * Access: RW 12536 */ 12537 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12538 12539 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12540 enum mlxsw_reg_sbxx_dir dir, 12541 enum mlxsw_reg_sbpr_mode mode, u32 size, 12542 bool infi_size) 12543 { 12544 MLXSW_REG_ZERO(sbpr, payload); 12545 mlxsw_reg_sbpr_pool_set(payload, pool); 12546 mlxsw_reg_sbpr_dir_set(payload, dir); 12547 mlxsw_reg_sbpr_mode_set(payload, mode); 12548 mlxsw_reg_sbpr_size_set(payload, size); 12549 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12550 } 12551 12552 /* SBCM - Shared Buffer Class Management Register 12553 * ---------------------------------------------- 12554 * The SBCM register configures and retrieves the shared buffer allocation 12555 * and configuration according to Port-PG, including the binding to pool 12556 * and definition of the associated quota. 12557 */ 12558 #define MLXSW_REG_SBCM_ID 0xB002 12559 #define MLXSW_REG_SBCM_LEN 0x28 12560 12561 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12562 12563 /* reg_sbcm_local_port 12564 * Local port number. 12565 * For Ingress: excludes CPU port and Router port 12566 * For Egress: excludes IP Router 12567 * Access: Index 12568 */ 12569 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12570 12571 /* reg_sbcm_pg_buff 12572 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12573 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12574 * For traffic class: range is 0..cap_max_tclass - 1 12575 * Note that when traffic class is in MC aware mode then the traffic 12576 * classes which are MC aware cannot be configured. 12577 * Access: Index 12578 */ 12579 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12580 12581 /* reg_sbcm_dir 12582 * Direction. 12583 * Access: Index 12584 */ 12585 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12586 12587 /* reg_sbcm_min_buff 12588 * Minimum buffer size for the limiter, in cells. 12589 * Access: RW 12590 */ 12591 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12592 12593 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12594 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12595 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12596 12597 /* reg_sbcm_infi_max 12598 * Max buffer is infinite. 12599 * Access: RW 12600 */ 12601 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12602 12603 /* reg_sbcm_max_buff 12604 * When the pool associated to the port-pg/tclass is configured to 12605 * static, Maximum buffer size for the limiter configured in cells. 12606 * When the pool associated to the port-pg/tclass is configured to 12607 * dynamic, the max_buff holds the "alpha" parameter, supporting 12608 * the following values: 12609 * 0: 0 12610 * i: (1/128)*2^(i-1), for i=1..14 12611 * 0xFF: Infinity 12612 * Reserved when infi_max = 1. 12613 * Access: RW 12614 */ 12615 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12616 12617 /* reg_sbcm_pool 12618 * Association of the port-priority to a pool. 12619 * Access: RW 12620 */ 12621 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12622 12623 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12624 enum mlxsw_reg_sbxx_dir dir, 12625 u32 min_buff, u32 max_buff, 12626 bool infi_max, u8 pool) 12627 { 12628 MLXSW_REG_ZERO(sbcm, payload); 12629 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12630 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12631 mlxsw_reg_sbcm_dir_set(payload, dir); 12632 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12633 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12634 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12635 mlxsw_reg_sbcm_pool_set(payload, pool); 12636 } 12637 12638 /* SBPM - Shared Buffer Port Management Register 12639 * --------------------------------------------- 12640 * The SBPM register configures and retrieves the shared buffer allocation 12641 * and configuration according to Port-Pool, including the definition 12642 * of the associated quota. 12643 */ 12644 #define MLXSW_REG_SBPM_ID 0xB003 12645 #define MLXSW_REG_SBPM_LEN 0x28 12646 12647 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12648 12649 /* reg_sbpm_local_port 12650 * Local port number. 12651 * For Ingress: excludes CPU port and Router port 12652 * For Egress: excludes IP Router 12653 * Access: Index 12654 */ 12655 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12656 12657 /* reg_sbpm_pool 12658 * The pool associated to quota counting on the local_port. 12659 * Access: Index 12660 */ 12661 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12662 12663 /* reg_sbpm_dir 12664 * Direction. 12665 * Access: Index 12666 */ 12667 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12668 12669 /* reg_sbpm_buff_occupancy 12670 * Current buffer occupancy in cells. 12671 * Access: RO 12672 */ 12673 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12674 12675 /* reg_sbpm_clr 12676 * Clear Max Buffer Occupancy 12677 * When this bit is set, max_buff_occupancy field is cleared (and a 12678 * new max value is tracked from the time the clear was performed). 12679 * Access: OP 12680 */ 12681 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12682 12683 /* reg_sbpm_max_buff_occupancy 12684 * Maximum value of buffer occupancy in cells monitored. Cleared by 12685 * writing to the clr field. 12686 * Access: RO 12687 */ 12688 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12689 12690 /* reg_sbpm_min_buff 12691 * Minimum buffer size for the limiter, in cells. 12692 * Access: RW 12693 */ 12694 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12695 12696 /* reg_sbpm_max_buff 12697 * When the pool associated to the port-pg/tclass is configured to 12698 * static, Maximum buffer size for the limiter configured in cells. 12699 * When the pool associated to the port-pg/tclass is configured to 12700 * dynamic, the max_buff holds the "alpha" parameter, supporting 12701 * the following values: 12702 * 0: 0 12703 * i: (1/128)*2^(i-1), for i=1..14 12704 * 0xFF: Infinity 12705 * Access: RW 12706 */ 12707 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12708 12709 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12710 enum mlxsw_reg_sbxx_dir dir, bool clr, 12711 u32 min_buff, u32 max_buff) 12712 { 12713 MLXSW_REG_ZERO(sbpm, payload); 12714 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12715 mlxsw_reg_sbpm_pool_set(payload, pool); 12716 mlxsw_reg_sbpm_dir_set(payload, dir); 12717 mlxsw_reg_sbpm_clr_set(payload, clr); 12718 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12719 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12720 } 12721 12722 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12723 u32 *p_max_buff_occupancy) 12724 { 12725 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12726 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12727 } 12728 12729 /* SBMM - Shared Buffer Multicast Management Register 12730 * -------------------------------------------------- 12731 * The SBMM register configures and retrieves the shared buffer allocation 12732 * and configuration for MC packets according to Switch-Priority, including 12733 * the binding to pool and definition of the associated quota. 12734 */ 12735 #define MLXSW_REG_SBMM_ID 0xB004 12736 #define MLXSW_REG_SBMM_LEN 0x28 12737 12738 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12739 12740 /* reg_sbmm_prio 12741 * Switch Priority. 12742 * Access: Index 12743 */ 12744 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12745 12746 /* reg_sbmm_min_buff 12747 * Minimum buffer size for the limiter, in cells. 12748 * Access: RW 12749 */ 12750 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12751 12752 /* reg_sbmm_max_buff 12753 * When the pool associated to the port-pg/tclass is configured to 12754 * static, Maximum buffer size for the limiter configured in cells. 12755 * When the pool associated to the port-pg/tclass is configured to 12756 * dynamic, the max_buff holds the "alpha" parameter, supporting 12757 * the following values: 12758 * 0: 0 12759 * i: (1/128)*2^(i-1), for i=1..14 12760 * 0xFF: Infinity 12761 * Access: RW 12762 */ 12763 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12764 12765 /* reg_sbmm_pool 12766 * Association of the port-priority to a pool. 12767 * Access: RW 12768 */ 12769 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12770 12771 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12772 u32 max_buff, u8 pool) 12773 { 12774 MLXSW_REG_ZERO(sbmm, payload); 12775 mlxsw_reg_sbmm_prio_set(payload, prio); 12776 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12777 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12778 mlxsw_reg_sbmm_pool_set(payload, pool); 12779 } 12780 12781 /* SBSR - Shared Buffer Status Register 12782 * ------------------------------------ 12783 * The SBSR register retrieves the shared buffer occupancy according to 12784 * Port-Pool. Note that this register enables reading a large amount of data. 12785 * It is the user's responsibility to limit the amount of data to ensure the 12786 * response can match the maximum transfer unit. In case the response exceeds 12787 * the maximum transport unit, it will be truncated with no special notice. 12788 */ 12789 #define MLXSW_REG_SBSR_ID 0xB005 12790 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12791 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12792 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12793 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12794 MLXSW_REG_SBSR_REC_LEN * \ 12795 MLXSW_REG_SBSR_REC_MAX_COUNT) 12796 12797 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12798 12799 /* reg_sbsr_clr 12800 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12801 * field is cleared (and a new max value is tracked from the time the clear 12802 * was performed). 12803 * Access: OP 12804 */ 12805 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12806 12807 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12808 12809 /* reg_sbsr_port_page 12810 * Determines the range of the ports specified in the 'ingress_port_mask' 12811 * and 'egress_port_mask' bit masks. 12812 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12813 * Access: Index 12814 */ 12815 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12816 12817 /* reg_sbsr_ingress_port_mask 12818 * Bit vector for all ingress network ports. 12819 * Indicates which of the ports (for which the relevant bit is set) 12820 * are affected by the set operation. Configuration of any other port 12821 * does not change. 12822 * Access: Index 12823 */ 12824 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12825 12826 /* reg_sbsr_pg_buff_mask 12827 * Bit vector for all switch priority groups. 12828 * Indicates which of the priorities (for which the relevant bit is set) 12829 * are affected by the set operation. Configuration of any other priority 12830 * does not change. 12831 * Range is 0..cap_max_pg_buffers - 1 12832 * Access: Index 12833 */ 12834 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12835 12836 /* reg_sbsr_egress_port_mask 12837 * Bit vector for all egress network ports. 12838 * Indicates which of the ports (for which the relevant bit is set) 12839 * are affected by the set operation. Configuration of any other port 12840 * does not change. 12841 * Access: Index 12842 */ 12843 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12844 12845 /* reg_sbsr_tclass_mask 12846 * Bit vector for all traffic classes. 12847 * Indicates which of the traffic classes (for which the relevant bit is 12848 * set) are affected by the set operation. Configuration of any other 12849 * traffic class does not change. 12850 * Range is 0..cap_max_tclass - 1 12851 * Access: Index 12852 */ 12853 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12854 12855 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12856 { 12857 MLXSW_REG_ZERO(sbsr, payload); 12858 mlxsw_reg_sbsr_clr_set(payload, clr); 12859 } 12860 12861 /* reg_sbsr_rec_buff_occupancy 12862 * Current buffer occupancy in cells. 12863 * Access: RO 12864 */ 12865 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12866 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12867 12868 /* reg_sbsr_rec_max_buff_occupancy 12869 * Maximum value of buffer occupancy in cells monitored. Cleared by 12870 * writing to the clr field. 12871 * Access: RO 12872 */ 12873 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12874 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12875 12876 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12877 u32 *p_buff_occupancy, 12878 u32 *p_max_buff_occupancy) 12879 { 12880 *p_buff_occupancy = 12881 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12882 *p_max_buff_occupancy = 12883 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12884 } 12885 12886 /* SBIB - Shared Buffer Internal Buffer Register 12887 * --------------------------------------------- 12888 * The SBIB register configures per port buffers for internal use. The internal 12889 * buffers consume memory on the port buffers (note that the port buffers are 12890 * used also by PBMC). 12891 * 12892 * For Spectrum this is used for egress mirroring. 12893 */ 12894 #define MLXSW_REG_SBIB_ID 0xB006 12895 #define MLXSW_REG_SBIB_LEN 0x10 12896 12897 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12898 12899 /* reg_sbib_local_port 12900 * Local port number 12901 * Not supported for CPU port and router port 12902 * Access: Index 12903 */ 12904 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12905 12906 /* reg_sbib_buff_size 12907 * Units represented in cells 12908 * Allowed range is 0 to (cap_max_headroom_size - 1) 12909 * Default is 0 12910 * Access: RW 12911 */ 12912 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12913 12914 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12915 u32 buff_size) 12916 { 12917 MLXSW_REG_ZERO(sbib, payload); 12918 mlxsw_reg_sbib_local_port_set(payload, local_port); 12919 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12920 } 12921 12922 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12923 MLXSW_REG(sgcr), 12924 MLXSW_REG(spad), 12925 MLXSW_REG(sspr), 12926 MLXSW_REG(sfdat), 12927 MLXSW_REG(sfd), 12928 MLXSW_REG(sfn), 12929 MLXSW_REG(spms), 12930 MLXSW_REG(spvid), 12931 MLXSW_REG(spvm), 12932 MLXSW_REG(spaft), 12933 MLXSW_REG(sfgc), 12934 MLXSW_REG(sfdf), 12935 MLXSW_REG(sldr), 12936 MLXSW_REG(slcr), 12937 MLXSW_REG(slcor), 12938 MLXSW_REG(spmlr), 12939 MLXSW_REG(svfa), 12940 MLXSW_REG(spvtr), 12941 MLXSW_REG(svpe), 12942 MLXSW_REG(sfmr), 12943 MLXSW_REG(spvmlr), 12944 MLXSW_REG(spfsr), 12945 MLXSW_REG(spvc), 12946 MLXSW_REG(spevet), 12947 MLXSW_REG(smpe), 12948 MLXSW_REG(smid2), 12949 MLXSW_REG(cwtp), 12950 MLXSW_REG(cwtpm), 12951 MLXSW_REG(pgcr), 12952 MLXSW_REG(ppbt), 12953 MLXSW_REG(pacl), 12954 MLXSW_REG(pagt), 12955 MLXSW_REG(ptar), 12956 MLXSW_REG(pprr), 12957 MLXSW_REG(ppbs), 12958 MLXSW_REG(prcr), 12959 MLXSW_REG(pefa), 12960 MLXSW_REG(pemrbt), 12961 MLXSW_REG(ptce2), 12962 MLXSW_REG(perpt), 12963 MLXSW_REG(peabfe), 12964 MLXSW_REG(perar), 12965 MLXSW_REG(ptce3), 12966 MLXSW_REG(percr), 12967 MLXSW_REG(pererp), 12968 MLXSW_REG(iedr), 12969 MLXSW_REG(qpts), 12970 MLXSW_REG(qpcr), 12971 MLXSW_REG(qtct), 12972 MLXSW_REG(qeec), 12973 MLXSW_REG(qrwe), 12974 MLXSW_REG(qpdsm), 12975 MLXSW_REG(qpdp), 12976 MLXSW_REG(qpdpm), 12977 MLXSW_REG(qtctm), 12978 MLXSW_REG(qpsc), 12979 MLXSW_REG(pmlp), 12980 MLXSW_REG(pmtu), 12981 MLXSW_REG(ptys), 12982 MLXSW_REG(ppad), 12983 MLXSW_REG(paos), 12984 MLXSW_REG(pfcc), 12985 MLXSW_REG(ppcnt), 12986 MLXSW_REG(pptb), 12987 MLXSW_REG(pbmc), 12988 MLXSW_REG(pspa), 12989 MLXSW_REG(pmaos), 12990 MLXSW_REG(pplr), 12991 MLXSW_REG(pmtdb), 12992 MLXSW_REG(pmecr), 12993 MLXSW_REG(pmpe), 12994 MLXSW_REG(pddr), 12995 MLXSW_REG(pmmp), 12996 MLXSW_REG(pllp), 12997 MLXSW_REG(pmtm), 12998 MLXSW_REG(htgt), 12999 MLXSW_REG(hpkt), 13000 MLXSW_REG(rgcr), 13001 MLXSW_REG(ritr), 13002 MLXSW_REG(rtar), 13003 MLXSW_REG(ratr), 13004 MLXSW_REG(rtdp), 13005 MLXSW_REG(rips), 13006 MLXSW_REG(ratrad), 13007 MLXSW_REG(rdpm), 13008 MLXSW_REG(ricnt), 13009 MLXSW_REG(rrcr), 13010 MLXSW_REG(ralta), 13011 MLXSW_REG(ralst), 13012 MLXSW_REG(raltb), 13013 MLXSW_REG(ralue), 13014 MLXSW_REG(rauht), 13015 MLXSW_REG(raleu), 13016 MLXSW_REG(rauhtd), 13017 MLXSW_REG(rigr2), 13018 MLXSW_REG(recr2), 13019 MLXSW_REG(rmft2), 13020 MLXSW_REG(reiv), 13021 MLXSW_REG(mfcr), 13022 MLXSW_REG(mfsc), 13023 MLXSW_REG(mfsm), 13024 MLXSW_REG(mfsl), 13025 MLXSW_REG(fore), 13026 MLXSW_REG(mtcap), 13027 MLXSW_REG(mtmp), 13028 MLXSW_REG(mtwe), 13029 MLXSW_REG(mtbr), 13030 MLXSW_REG(mcia), 13031 MLXSW_REG(mpat), 13032 MLXSW_REG(mpar), 13033 MLXSW_REG(mgir), 13034 MLXSW_REG(mrsr), 13035 MLXSW_REG(mlcr), 13036 MLXSW_REG(mcion), 13037 MLXSW_REG(mtpps), 13038 MLXSW_REG(mtutc), 13039 MLXSW_REG(mcqi), 13040 MLXSW_REG(mcc), 13041 MLXSW_REG(mcda), 13042 MLXSW_REG(mcam), 13043 MLXSW_REG(mpsc), 13044 MLXSW_REG(mgpc), 13045 MLXSW_REG(mprs), 13046 MLXSW_REG(mogcr), 13047 MLXSW_REG(mpagr), 13048 MLXSW_REG(momte), 13049 MLXSW_REG(mtpppc), 13050 MLXSW_REG(mtpptr), 13051 MLXSW_REG(mtptpt), 13052 MLXSW_REG(mtpcpc), 13053 MLXSW_REG(mfgd), 13054 MLXSW_REG(mgpir), 13055 MLXSW_REG(mbct), 13056 MLXSW_REG(mddt), 13057 MLXSW_REG(mddq), 13058 MLXSW_REG(mddc), 13059 MLXSW_REG(mfde), 13060 MLXSW_REG(tngcr), 13061 MLXSW_REG(tnumt), 13062 MLXSW_REG(tnqcr), 13063 MLXSW_REG(tnqdr), 13064 MLXSW_REG(tneem), 13065 MLXSW_REG(tndem), 13066 MLXSW_REG(tnpc), 13067 MLXSW_REG(tigcr), 13068 MLXSW_REG(tieem), 13069 MLXSW_REG(tidem), 13070 MLXSW_REG(sbpr), 13071 MLXSW_REG(sbcm), 13072 MLXSW_REG(sbpm), 13073 MLXSW_REG(sbmm), 13074 MLXSW_REG(sbsr), 13075 MLXSW_REG(sbib), 13076 }; 13077 13078 static inline const char *mlxsw_reg_id_str(u16 reg_id) 13079 { 13080 const struct mlxsw_reg_info *reg_info; 13081 int i; 13082 13083 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 13084 reg_info = mlxsw_reg_infos[i]; 13085 if (reg_info->id == reg_id) 13086 return reg_info->name; 13087 } 13088 return "*UNKNOWN*"; 13089 } 13090 13091 /* PUDE - Port Up / Down Event 13092 * --------------------------- 13093 * Reports the operational state change of a port. 13094 */ 13095 #define MLXSW_REG_PUDE_LEN 0x10 13096 13097 /* reg_pude_swid 13098 * Switch partition ID with which to associate the port. 13099 * Access: Index 13100 */ 13101 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 13102 13103 /* reg_pude_local_port 13104 * Local port number. 13105 * Access: Index 13106 */ 13107 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 13108 13109 /* reg_pude_admin_status 13110 * Port administrative state (the desired state). 13111 * 1 - Up. 13112 * 2 - Down. 13113 * 3 - Up once. This means that in case of link failure, the port won't go 13114 * into polling mode, but will wait to be re-enabled by software. 13115 * 4 - Disabled by system. Can only be set by hardware. 13116 * Access: RO 13117 */ 13118 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 13119 13120 /* reg_pude_oper_status 13121 * Port operatioanl state. 13122 * 1 - Up. 13123 * 2 - Down. 13124 * 3 - Down by port failure. This means that the device will not let the 13125 * port up again until explicitly specified by software. 13126 * Access: RO 13127 */ 13128 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 13129 13130 #endif 13131