1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 }; 645 646 /* reg_sfn_rec_type 647 * Notification record type. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 651 MLXSW_REG_SFN_REC_LEN, 0x00, false); 652 653 /* reg_sfn_rec_mac 654 * MAC address. 655 * Access: RO 656 */ 657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 658 MLXSW_REG_SFN_REC_LEN, 0x02); 659 660 /* reg_sfn_mac_sub_port 661 * VEPA channel on the local port. 662 * 0 if multichannel VEPA is not enabled. 663 * Access: RO 664 */ 665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 666 MLXSW_REG_SFN_REC_LEN, 0x08, false); 667 668 /* reg_sfn_mac_fid 669 * Filtering identifier. 670 * Access: RO 671 */ 672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 673 MLXSW_REG_SFN_REC_LEN, 0x08, false); 674 675 /* reg_sfn_mac_system_port 676 * Unique port identifier for the final destination of the packet. 677 * Access: RO 678 */ 679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 680 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 681 682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 683 char *mac, u16 *p_vid, 684 u8 *p_local_port) 685 { 686 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 687 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 689 } 690 691 /* reg_sfn_mac_lag_lag_id 692 * LAG ID (pointer into the LAG descriptor table). 693 * Access: RO 694 */ 695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 696 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 697 698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 699 char *mac, u16 *p_vid, 700 u16 *p_lag_id) 701 { 702 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 703 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 705 } 706 707 /* SPMS - Switch Port MSTP/RSTP State Register 708 * ------------------------------------------- 709 * Configures the spanning tree state of a physical port. 710 */ 711 #define MLXSW_REG_SPMS_ID 0x200D 712 #define MLXSW_REG_SPMS_LEN 0x404 713 714 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 715 716 /* reg_spms_local_port 717 * Local port number. 718 * Access: Index 719 */ 720 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 721 722 enum mlxsw_reg_spms_state { 723 MLXSW_REG_SPMS_STATE_NO_CHANGE, 724 MLXSW_REG_SPMS_STATE_DISCARDING, 725 MLXSW_REG_SPMS_STATE_LEARNING, 726 MLXSW_REG_SPMS_STATE_FORWARDING, 727 }; 728 729 /* reg_spms_state 730 * Spanning tree state of each VLAN ID (VID) of the local port. 731 * 0 - Do not change spanning tree state (used only when writing). 732 * 1 - Discarding. No learning or forwarding to/from this port (default). 733 * 2 - Learning. Port is learning, but not forwarding. 734 * 3 - Forwarding. Port is learning and forwarding. 735 * Access: RW 736 */ 737 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 738 739 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 740 { 741 MLXSW_REG_ZERO(spms, payload); 742 mlxsw_reg_spms_local_port_set(payload, local_port); 743 } 744 745 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 746 enum mlxsw_reg_spms_state state) 747 { 748 mlxsw_reg_spms_state_set(payload, vid, state); 749 } 750 751 /* SPVID - Switch Port VID 752 * ----------------------- 753 * The switch port VID configures the default VID for a port. 754 */ 755 #define MLXSW_REG_SPVID_ID 0x200E 756 #define MLXSW_REG_SPVID_LEN 0x08 757 758 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 759 760 /* reg_spvid_local_port 761 * Local port number. 762 * Access: Index 763 */ 764 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 765 766 /* reg_spvid_sub_port 767 * Virtual port within the physical port. 768 * Should be set to 0 when virtual ports are not enabled on the port. 769 * Access: Index 770 */ 771 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 772 773 /* reg_spvid_pvid 774 * Port default VID 775 * Access: RW 776 */ 777 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 778 779 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 780 { 781 MLXSW_REG_ZERO(spvid, payload); 782 mlxsw_reg_spvid_local_port_set(payload, local_port); 783 mlxsw_reg_spvid_pvid_set(payload, pvid); 784 } 785 786 /* SPVM - Switch Port VLAN Membership 787 * ---------------------------------- 788 * The Switch Port VLAN Membership register configures the VLAN membership 789 * of a port in a VLAN denoted by VID. VLAN membership is managed per 790 * virtual port. The register can be used to add and remove VID(s) from a port. 791 */ 792 #define MLXSW_REG_SPVM_ID 0x200F 793 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 794 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 795 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 796 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 797 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 798 799 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 800 801 /* reg_spvm_pt 802 * Priority tagged. If this bit is set, packets forwarded to the port with 803 * untagged VLAN membership (u bit is set) will be tagged with priority tag 804 * (VID=0) 805 * Access: RW 806 */ 807 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 808 809 /* reg_spvm_pte 810 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 811 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 812 * Access: WO 813 */ 814 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 815 816 /* reg_spvm_local_port 817 * Local port number. 818 * Access: Index 819 */ 820 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 821 822 /* reg_spvm_sub_port 823 * Virtual port within the physical port. 824 * Should be set to 0 when virtual ports are not enabled on the port. 825 * Access: Index 826 */ 827 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 828 829 /* reg_spvm_num_rec 830 * Number of records to update. Each record contains: i, e, u, vid. 831 * Access: OP 832 */ 833 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 834 835 /* reg_spvm_rec_i 836 * Ingress membership in VLAN ID. 837 * Access: Index 838 */ 839 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 840 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 841 MLXSW_REG_SPVM_REC_LEN, 0, false); 842 843 /* reg_spvm_rec_e 844 * Egress membership in VLAN ID. 845 * Access: Index 846 */ 847 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 848 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 849 MLXSW_REG_SPVM_REC_LEN, 0, false); 850 851 /* reg_spvm_rec_u 852 * Untagged - port is an untagged member - egress transmission uses untagged 853 * frames on VID<n> 854 * Access: Index 855 */ 856 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 857 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 858 MLXSW_REG_SPVM_REC_LEN, 0, false); 859 860 /* reg_spvm_rec_vid 861 * Egress membership in VLAN ID. 862 * Access: Index 863 */ 864 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 865 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 866 MLXSW_REG_SPVM_REC_LEN, 0, false); 867 868 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 869 u16 vid_begin, u16 vid_end, 870 bool is_member, bool untagged) 871 { 872 int size = vid_end - vid_begin + 1; 873 int i; 874 875 MLXSW_REG_ZERO(spvm, payload); 876 mlxsw_reg_spvm_local_port_set(payload, local_port); 877 mlxsw_reg_spvm_num_rec_set(payload, size); 878 879 for (i = 0; i < size; i++) { 880 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 881 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 882 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 883 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 884 } 885 } 886 887 /* SPAFT - Switch Port Acceptable Frame Types 888 * ------------------------------------------ 889 * The Switch Port Acceptable Frame Types register configures the frame 890 * admittance of the port. 891 */ 892 #define MLXSW_REG_SPAFT_ID 0x2010 893 #define MLXSW_REG_SPAFT_LEN 0x08 894 895 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 896 897 /* reg_spaft_local_port 898 * Local port number. 899 * Access: Index 900 * 901 * Note: CPU port is not supported (all tag types are allowed). 902 */ 903 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 904 905 /* reg_spaft_sub_port 906 * Virtual port within the physical port. 907 * Should be set to 0 when virtual ports are not enabled on the port. 908 * Access: RW 909 */ 910 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 911 912 /* reg_spaft_allow_untagged 913 * When set, untagged frames on the ingress are allowed (default). 914 * Access: RW 915 */ 916 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 917 918 /* reg_spaft_allow_prio_tagged 919 * When set, priority tagged frames on the ingress are allowed (default). 920 * Access: RW 921 */ 922 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 923 924 /* reg_spaft_allow_tagged 925 * When set, tagged frames on the ingress are allowed (default). 926 * Access: RW 927 */ 928 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 929 930 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 931 bool allow_untagged) 932 { 933 MLXSW_REG_ZERO(spaft, payload); 934 mlxsw_reg_spaft_local_port_set(payload, local_port); 935 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 936 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 937 mlxsw_reg_spaft_allow_tagged_set(payload, true); 938 } 939 940 /* SFGC - Switch Flooding Group Configuration 941 * ------------------------------------------ 942 * The following register controls the association of flooding tables and MIDs 943 * to packet types used for flooding. 944 */ 945 #define MLXSW_REG_SFGC_ID 0x2011 946 #define MLXSW_REG_SFGC_LEN 0x10 947 948 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 949 950 enum mlxsw_reg_sfgc_type { 951 MLXSW_REG_SFGC_TYPE_BROADCAST, 952 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 953 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 954 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 955 MLXSW_REG_SFGC_TYPE_RESERVED, 956 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 957 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 958 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 959 MLXSW_REG_SFGC_TYPE_MAX, 960 }; 961 962 /* reg_sfgc_type 963 * The traffic type to reach the flooding table. 964 * Access: Index 965 */ 966 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 967 968 enum mlxsw_reg_sfgc_bridge_type { 969 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 970 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 971 }; 972 973 /* reg_sfgc_bridge_type 974 * Access: Index 975 * 976 * Note: SwitchX-2 only supports 802.1Q mode. 977 */ 978 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 979 980 enum mlxsw_flood_table_type { 981 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 982 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 983 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 984 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 985 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 986 }; 987 988 /* reg_sfgc_table_type 989 * See mlxsw_flood_table_type 990 * Access: RW 991 * 992 * Note: FID offset and FID types are not supported in SwitchX-2. 993 */ 994 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 995 996 /* reg_sfgc_flood_table 997 * Flooding table index to associate with the specific type on the specific 998 * switch partition. 999 * Access: RW 1000 */ 1001 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1002 1003 /* reg_sfgc_mid 1004 * The multicast ID for the swid. Not supported for Spectrum 1005 * Access: RW 1006 */ 1007 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1008 1009 /* reg_sfgc_counter_set_type 1010 * Counter Set Type for flow counters. 1011 * Access: RW 1012 */ 1013 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1014 1015 /* reg_sfgc_counter_index 1016 * Counter Index for flow counters. 1017 * Access: RW 1018 */ 1019 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1020 1021 static inline void 1022 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1023 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1024 enum mlxsw_flood_table_type table_type, 1025 unsigned int flood_table) 1026 { 1027 MLXSW_REG_ZERO(sfgc, payload); 1028 mlxsw_reg_sfgc_type_set(payload, type); 1029 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1030 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1031 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1032 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1033 } 1034 1035 /* SFTR - Switch Flooding Table Register 1036 * ------------------------------------- 1037 * The switch flooding table is used for flooding packet replication. The table 1038 * defines a bit mask of ports for packet replication. 1039 */ 1040 #define MLXSW_REG_SFTR_ID 0x2012 1041 #define MLXSW_REG_SFTR_LEN 0x420 1042 1043 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1044 1045 /* reg_sftr_swid 1046 * Switch partition ID with which to associate the port. 1047 * Access: Index 1048 */ 1049 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1050 1051 /* reg_sftr_flood_table 1052 * Flooding table index to associate with the specific type on the specific 1053 * switch partition. 1054 * Access: Index 1055 */ 1056 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1057 1058 /* reg_sftr_index 1059 * Index. Used as an index into the Flooding Table in case the table is 1060 * configured to use VID / FID or FID Offset. 1061 * Access: Index 1062 */ 1063 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1064 1065 /* reg_sftr_table_type 1066 * See mlxsw_flood_table_type 1067 * Access: RW 1068 */ 1069 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1070 1071 /* reg_sftr_range 1072 * Range of entries to update 1073 * Access: Index 1074 */ 1075 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1076 1077 /* reg_sftr_port 1078 * Local port membership (1 bit per port). 1079 * Access: RW 1080 */ 1081 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1082 1083 /* reg_sftr_cpu_port_mask 1084 * CPU port mask (1 bit per port). 1085 * Access: W 1086 */ 1087 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1088 1089 static inline void mlxsw_reg_sftr_pack(char *payload, 1090 unsigned int flood_table, 1091 unsigned int index, 1092 enum mlxsw_flood_table_type table_type, 1093 unsigned int range, u8 port, bool set) 1094 { 1095 MLXSW_REG_ZERO(sftr, payload); 1096 mlxsw_reg_sftr_swid_set(payload, 0); 1097 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1098 mlxsw_reg_sftr_index_set(payload, index); 1099 mlxsw_reg_sftr_table_type_set(payload, table_type); 1100 mlxsw_reg_sftr_range_set(payload, range); 1101 mlxsw_reg_sftr_port_set(payload, port, set); 1102 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1103 } 1104 1105 /* SFDF - Switch Filtering DB Flush 1106 * -------------------------------- 1107 * The switch filtering DB flush register is used to flush the FDB. 1108 * Note that FDB notifications are flushed as well. 1109 */ 1110 #define MLXSW_REG_SFDF_ID 0x2013 1111 #define MLXSW_REG_SFDF_LEN 0x14 1112 1113 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1114 1115 /* reg_sfdf_swid 1116 * Switch partition ID. 1117 * Access: Index 1118 */ 1119 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1120 1121 enum mlxsw_reg_sfdf_flush_type { 1122 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1123 MLXSW_REG_SFDF_FLUSH_PER_FID, 1124 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1125 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1126 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1127 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1128 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1129 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1130 }; 1131 1132 /* reg_sfdf_flush_type 1133 * Flush type. 1134 * 0 - All SWID dynamic entries are flushed. 1135 * 1 - All FID dynamic entries are flushed. 1136 * 2 - All dynamic entries pointing to port are flushed. 1137 * 3 - All FID dynamic entries pointing to port are flushed. 1138 * 4 - All dynamic entries pointing to LAG are flushed. 1139 * 5 - All FID dynamic entries pointing to LAG are flushed. 1140 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1141 * flushed. 1142 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1143 * flushed, per FID. 1144 * Access: RW 1145 */ 1146 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1147 1148 /* reg_sfdf_flush_static 1149 * Static. 1150 * 0 - Flush only dynamic entries. 1151 * 1 - Flush both dynamic and static entries. 1152 * Access: RW 1153 */ 1154 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1155 1156 static inline void mlxsw_reg_sfdf_pack(char *payload, 1157 enum mlxsw_reg_sfdf_flush_type type) 1158 { 1159 MLXSW_REG_ZERO(sfdf, payload); 1160 mlxsw_reg_sfdf_flush_type_set(payload, type); 1161 mlxsw_reg_sfdf_flush_static_set(payload, true); 1162 } 1163 1164 /* reg_sfdf_fid 1165 * FID to flush. 1166 * Access: RW 1167 */ 1168 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1169 1170 /* reg_sfdf_system_port 1171 * Port to flush. 1172 * Access: RW 1173 */ 1174 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1175 1176 /* reg_sfdf_port_fid_system_port 1177 * Port to flush, pointed to by FID. 1178 * Access: RW 1179 */ 1180 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1181 1182 /* reg_sfdf_lag_id 1183 * LAG ID to flush. 1184 * Access: RW 1185 */ 1186 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1187 1188 /* reg_sfdf_lag_fid_lag_id 1189 * LAG ID to flush, pointed to by FID. 1190 * Access: RW 1191 */ 1192 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1193 1194 /* SLDR - Switch LAG Descriptor Register 1195 * ----------------------------------------- 1196 * The switch LAG descriptor register is populated by LAG descriptors. 1197 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1198 * max_lag-1. 1199 */ 1200 #define MLXSW_REG_SLDR_ID 0x2014 1201 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1202 1203 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1204 1205 enum mlxsw_reg_sldr_op { 1206 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1207 MLXSW_REG_SLDR_OP_LAG_CREATE, 1208 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1209 /* Ports that appear in the list have the Distributor enabled */ 1210 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1211 /* Removes ports from the disributor list */ 1212 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1213 }; 1214 1215 /* reg_sldr_op 1216 * Operation. 1217 * Access: RW 1218 */ 1219 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1220 1221 /* reg_sldr_lag_id 1222 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1223 * Access: Index 1224 */ 1225 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1226 1227 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1228 { 1229 MLXSW_REG_ZERO(sldr, payload); 1230 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1231 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1232 } 1233 1234 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1235 { 1236 MLXSW_REG_ZERO(sldr, payload); 1237 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1238 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1239 } 1240 1241 /* reg_sldr_num_ports 1242 * The number of member ports of the LAG. 1243 * Reserved for Create / Destroy operations 1244 * For Add / Remove operations - indicates the number of ports in the list. 1245 * Access: RW 1246 */ 1247 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1248 1249 /* reg_sldr_system_port 1250 * System port. 1251 * Access: RW 1252 */ 1253 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1254 1255 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1256 u8 local_port) 1257 { 1258 MLXSW_REG_ZERO(sldr, payload); 1259 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1260 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1261 mlxsw_reg_sldr_num_ports_set(payload, 1); 1262 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1263 } 1264 1265 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1266 u8 local_port) 1267 { 1268 MLXSW_REG_ZERO(sldr, payload); 1269 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1270 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1271 mlxsw_reg_sldr_num_ports_set(payload, 1); 1272 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1273 } 1274 1275 /* SLCR - Switch LAG Configuration 2 Register 1276 * ------------------------------------------- 1277 * The Switch LAG Configuration register is used for configuring the 1278 * LAG properties of the switch. 1279 */ 1280 #define MLXSW_REG_SLCR_ID 0x2015 1281 #define MLXSW_REG_SLCR_LEN 0x10 1282 1283 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1284 1285 enum mlxsw_reg_slcr_pp { 1286 /* Global Configuration (for all ports) */ 1287 MLXSW_REG_SLCR_PP_GLOBAL, 1288 /* Per port configuration, based on local_port field */ 1289 MLXSW_REG_SLCR_PP_PER_PORT, 1290 }; 1291 1292 /* reg_slcr_pp 1293 * Per Port Configuration 1294 * Note: Reading at Global mode results in reading port 1 configuration. 1295 * Access: Index 1296 */ 1297 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1298 1299 /* reg_slcr_local_port 1300 * Local port number 1301 * Supported from CPU port 1302 * Not supported from router port 1303 * Reserved when pp = Global Configuration 1304 * Access: Index 1305 */ 1306 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1307 1308 enum mlxsw_reg_slcr_type { 1309 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1310 MLXSW_REG_SLCR_TYPE_XOR, 1311 MLXSW_REG_SLCR_TYPE_RANDOM, 1312 }; 1313 1314 /* reg_slcr_type 1315 * Hash type 1316 * Access: RW 1317 */ 1318 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1319 1320 /* Ingress port */ 1321 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1322 /* SMAC - for IPv4 and IPv6 packets */ 1323 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1324 /* SMAC - for non-IP packets */ 1325 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1326 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1327 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1328 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1329 /* DMAC - for IPv4 and IPv6 packets */ 1330 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1331 /* DMAC - for non-IP packets */ 1332 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1333 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1334 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1335 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1336 /* Ethertype - for IPv4 and IPv6 packets */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1338 /* Ethertype - for non-IP packets */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1340 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1341 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1342 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1343 /* VLAN ID - for IPv4 and IPv6 packets */ 1344 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1345 /* VLAN ID - for non-IP packets */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1347 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1348 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1349 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1350 /* Source IP address (can be IPv4 or IPv6) */ 1351 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1352 /* Destination IP address (can be IPv4 or IPv6) */ 1353 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1354 /* TCP/UDP source port */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1356 /* TCP/UDP destination port*/ 1357 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1358 /* IPv4 Protocol/IPv6 Next Header */ 1359 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1360 /* IPv6 Flow label */ 1361 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1362 /* SID - FCoE source ID */ 1363 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1364 /* DID - FCoE destination ID */ 1365 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1366 /* OXID - FCoE originator exchange ID */ 1367 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1368 /* Destination QP number - for RoCE packets */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1370 1371 /* reg_slcr_lag_hash 1372 * LAG hashing configuration. This is a bitmask, in which each set 1373 * bit includes the corresponding item in the LAG hash calculation. 1374 * The default lag_hash contains SMAC, DMAC, VLANID and 1375 * Ethertype (for all packet types). 1376 * Access: RW 1377 */ 1378 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1379 1380 /* reg_slcr_seed 1381 * LAG seed value. The seed is the same for all ports. 1382 * Access: RW 1383 */ 1384 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1385 1386 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1387 { 1388 MLXSW_REG_ZERO(slcr, payload); 1389 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1390 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1391 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1392 mlxsw_reg_slcr_seed_set(payload, seed); 1393 } 1394 1395 /* SLCOR - Switch LAG Collector Register 1396 * ------------------------------------- 1397 * The Switch LAG Collector register controls the Local Port membership 1398 * in a LAG and enablement of the collector. 1399 */ 1400 #define MLXSW_REG_SLCOR_ID 0x2016 1401 #define MLXSW_REG_SLCOR_LEN 0x10 1402 1403 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1404 1405 enum mlxsw_reg_slcor_col { 1406 /* Port is added with collector disabled */ 1407 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1408 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1409 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1410 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1411 }; 1412 1413 /* reg_slcor_col 1414 * Collector configuration 1415 * Access: RW 1416 */ 1417 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1418 1419 /* reg_slcor_local_port 1420 * Local port number 1421 * Not supported for CPU port 1422 * Access: Index 1423 */ 1424 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1425 1426 /* reg_slcor_lag_id 1427 * LAG Identifier. Index into the LAG descriptor table. 1428 * Access: Index 1429 */ 1430 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1431 1432 /* reg_slcor_port_index 1433 * Port index in the LAG list. Only valid on Add Port to LAG col. 1434 * Valid range is from 0 to cap_max_lag_members-1 1435 * Access: RW 1436 */ 1437 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1438 1439 static inline void mlxsw_reg_slcor_pack(char *payload, 1440 u8 local_port, u16 lag_id, 1441 enum mlxsw_reg_slcor_col col) 1442 { 1443 MLXSW_REG_ZERO(slcor, payload); 1444 mlxsw_reg_slcor_col_set(payload, col); 1445 mlxsw_reg_slcor_local_port_set(payload, local_port); 1446 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1447 } 1448 1449 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1450 u8 local_port, u16 lag_id, 1451 u8 port_index) 1452 { 1453 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1454 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1455 mlxsw_reg_slcor_port_index_set(payload, port_index); 1456 } 1457 1458 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1459 u8 local_port, u16 lag_id) 1460 { 1461 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1462 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1463 } 1464 1465 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1466 u8 local_port, u16 lag_id) 1467 { 1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1469 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1470 } 1471 1472 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1473 u8 local_port, u16 lag_id) 1474 { 1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1477 } 1478 1479 /* SPMLR - Switch Port MAC Learning Register 1480 * ----------------------------------------- 1481 * Controls the Switch MAC learning policy per port. 1482 */ 1483 #define MLXSW_REG_SPMLR_ID 0x2018 1484 #define MLXSW_REG_SPMLR_LEN 0x8 1485 1486 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1487 1488 /* reg_spmlr_local_port 1489 * Local port number. 1490 * Access: Index 1491 */ 1492 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1493 1494 /* reg_spmlr_sub_port 1495 * Virtual port within the physical port. 1496 * Should be set to 0 when virtual ports are not enabled on the port. 1497 * Access: Index 1498 */ 1499 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1500 1501 enum mlxsw_reg_spmlr_learn_mode { 1502 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1503 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1504 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1505 }; 1506 1507 /* reg_spmlr_learn_mode 1508 * Learning mode on the port. 1509 * 0 - Learning disabled. 1510 * 2 - Learning enabled. 1511 * 3 - Security mode. 1512 * 1513 * In security mode the switch does not learn MACs on the port, but uses the 1514 * SMAC to see if it exists on another ingress port. If so, the packet is 1515 * classified as a bad packet and is discarded unless the software registers 1516 * to receive port security error packets usign HPKT. 1517 */ 1518 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1519 1520 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1521 enum mlxsw_reg_spmlr_learn_mode mode) 1522 { 1523 MLXSW_REG_ZERO(spmlr, payload); 1524 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1525 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1526 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1527 } 1528 1529 /* SVFA - Switch VID to FID Allocation Register 1530 * -------------------------------------------- 1531 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1532 * virtualized ports. 1533 */ 1534 #define MLXSW_REG_SVFA_ID 0x201C 1535 #define MLXSW_REG_SVFA_LEN 0x10 1536 1537 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1538 1539 /* reg_svfa_swid 1540 * Switch partition ID. 1541 * Access: Index 1542 */ 1543 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1544 1545 /* reg_svfa_local_port 1546 * Local port number. 1547 * Access: Index 1548 * 1549 * Note: Reserved for 802.1Q FIDs. 1550 */ 1551 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1552 1553 enum mlxsw_reg_svfa_mt { 1554 MLXSW_REG_SVFA_MT_VID_TO_FID, 1555 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1556 }; 1557 1558 /* reg_svfa_mapping_table 1559 * Mapping table: 1560 * 0 - VID to FID 1561 * 1 - {Port, VID} to FID 1562 * Access: Index 1563 * 1564 * Note: Reserved for SwitchX-2. 1565 */ 1566 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1567 1568 /* reg_svfa_v 1569 * Valid. 1570 * Valid if set. 1571 * Access: RW 1572 * 1573 * Note: Reserved for SwitchX-2. 1574 */ 1575 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1576 1577 /* reg_svfa_fid 1578 * Filtering ID. 1579 * Access: RW 1580 */ 1581 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1582 1583 /* reg_svfa_vid 1584 * VLAN ID. 1585 * Access: Index 1586 */ 1587 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1588 1589 /* reg_svfa_counter_set_type 1590 * Counter set type for flow counters. 1591 * Access: RW 1592 * 1593 * Note: Reserved for SwitchX-2. 1594 */ 1595 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1596 1597 /* reg_svfa_counter_index 1598 * Counter index for flow counters. 1599 * Access: RW 1600 * 1601 * Note: Reserved for SwitchX-2. 1602 */ 1603 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1604 1605 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1606 enum mlxsw_reg_svfa_mt mt, bool valid, 1607 u16 fid, u16 vid) 1608 { 1609 MLXSW_REG_ZERO(svfa, payload); 1610 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1611 mlxsw_reg_svfa_swid_set(payload, 0); 1612 mlxsw_reg_svfa_local_port_set(payload, local_port); 1613 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1614 mlxsw_reg_svfa_v_set(payload, valid); 1615 mlxsw_reg_svfa_fid_set(payload, fid); 1616 mlxsw_reg_svfa_vid_set(payload, vid); 1617 } 1618 1619 /* SVPE - Switch Virtual-Port Enabling Register 1620 * -------------------------------------------- 1621 * Enables port virtualization. 1622 */ 1623 #define MLXSW_REG_SVPE_ID 0x201E 1624 #define MLXSW_REG_SVPE_LEN 0x4 1625 1626 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1627 1628 /* reg_svpe_local_port 1629 * Local port number 1630 * Access: Index 1631 * 1632 * Note: CPU port is not supported (uses VLAN mode only). 1633 */ 1634 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1635 1636 /* reg_svpe_vp_en 1637 * Virtual port enable. 1638 * 0 - Disable, VLAN mode (VID to FID). 1639 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1640 * Access: RW 1641 */ 1642 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1643 1644 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1645 bool enable) 1646 { 1647 MLXSW_REG_ZERO(svpe, payload); 1648 mlxsw_reg_svpe_local_port_set(payload, local_port); 1649 mlxsw_reg_svpe_vp_en_set(payload, enable); 1650 } 1651 1652 /* SFMR - Switch FID Management Register 1653 * ------------------------------------- 1654 * Creates and configures FIDs. 1655 */ 1656 #define MLXSW_REG_SFMR_ID 0x201F 1657 #define MLXSW_REG_SFMR_LEN 0x18 1658 1659 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1660 1661 enum mlxsw_reg_sfmr_op { 1662 MLXSW_REG_SFMR_OP_CREATE_FID, 1663 MLXSW_REG_SFMR_OP_DESTROY_FID, 1664 }; 1665 1666 /* reg_sfmr_op 1667 * Operation. 1668 * 0 - Create or edit FID. 1669 * 1 - Destroy FID. 1670 * Access: WO 1671 */ 1672 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1673 1674 /* reg_sfmr_fid 1675 * Filtering ID. 1676 * Access: Index 1677 */ 1678 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1679 1680 /* reg_sfmr_fid_offset 1681 * FID offset. 1682 * Used to point into the flooding table selected by SFGC register if 1683 * the table is of type FID-Offset. Otherwise, this field is reserved. 1684 * Access: RW 1685 */ 1686 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1687 1688 /* reg_sfmr_vtfp 1689 * Valid Tunnel Flood Pointer. 1690 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1691 * Access: RW 1692 * 1693 * Note: Reserved for 802.1Q FIDs. 1694 */ 1695 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1696 1697 /* reg_sfmr_nve_tunnel_flood_ptr 1698 * Underlay Flooding and BC Pointer. 1699 * Used as a pointer to the first entry of the group based link lists of 1700 * flooding or BC entries (for NVE tunnels). 1701 * Access: RW 1702 */ 1703 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1704 1705 /* reg_sfmr_vv 1706 * VNI Valid. 1707 * If not set, then vni is reserved. 1708 * Access: RW 1709 * 1710 * Note: Reserved for 802.1Q FIDs. 1711 */ 1712 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1713 1714 /* reg_sfmr_vni 1715 * Virtual Network Identifier. 1716 * Access: RW 1717 * 1718 * Note: A given VNI can only be assigned to one FID. 1719 */ 1720 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1721 1722 static inline void mlxsw_reg_sfmr_pack(char *payload, 1723 enum mlxsw_reg_sfmr_op op, u16 fid, 1724 u16 fid_offset) 1725 { 1726 MLXSW_REG_ZERO(sfmr, payload); 1727 mlxsw_reg_sfmr_op_set(payload, op); 1728 mlxsw_reg_sfmr_fid_set(payload, fid); 1729 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1730 mlxsw_reg_sfmr_vtfp_set(payload, false); 1731 mlxsw_reg_sfmr_vv_set(payload, false); 1732 } 1733 1734 /* SPVMLR - Switch Port VLAN MAC Learning Register 1735 * ----------------------------------------------- 1736 * Controls the switch MAC learning policy per {Port, VID}. 1737 */ 1738 #define MLXSW_REG_SPVMLR_ID 0x2020 1739 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1740 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1741 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1742 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1743 MLXSW_REG_SPVMLR_REC_LEN * \ 1744 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1745 1746 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1747 1748 /* reg_spvmlr_local_port 1749 * Local ingress port. 1750 * Access: Index 1751 * 1752 * Note: CPU port is not supported. 1753 */ 1754 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1755 1756 /* reg_spvmlr_num_rec 1757 * Number of records to update. 1758 * Access: OP 1759 */ 1760 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1761 1762 /* reg_spvmlr_rec_learn_enable 1763 * 0 - Disable learning for {Port, VID}. 1764 * 1 - Enable learning for {Port, VID}. 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1768 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1769 1770 /* reg_spvmlr_rec_vid 1771 * VLAN ID to be added/removed from port or for querying. 1772 * Access: Index 1773 */ 1774 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1775 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1776 1777 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1778 u16 vid_begin, u16 vid_end, 1779 bool learn_enable) 1780 { 1781 int num_rec = vid_end - vid_begin + 1; 1782 int i; 1783 1784 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1785 1786 MLXSW_REG_ZERO(spvmlr, payload); 1787 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1788 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1789 1790 for (i = 0; i < num_rec; i++) { 1791 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1792 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1793 } 1794 } 1795 1796 /* CWTP - Congetion WRED ECN TClass Profile 1797 * ---------------------------------------- 1798 * Configures the profiles for queues of egress port and traffic class 1799 */ 1800 #define MLXSW_REG_CWTP_ID 0x2802 1801 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1802 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1803 #define MLXSW_REG_CWTP_LEN 0x40 1804 1805 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1806 1807 /* reg_cwtp_local_port 1808 * Local port number 1809 * Not supported for CPU port 1810 * Access: Index 1811 */ 1812 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1813 1814 /* reg_cwtp_traffic_class 1815 * Traffic Class to configure 1816 * Access: Index 1817 */ 1818 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1819 1820 /* reg_cwtp_profile_min 1821 * Minimum Average Queue Size of the profile in cells. 1822 * Access: RW 1823 */ 1824 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1825 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1826 1827 /* reg_cwtp_profile_percent 1828 * Percentage of WRED and ECN marking for maximum Average Queue size 1829 * Range is 0 to 100, units of integer percentage 1830 * Access: RW 1831 */ 1832 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1833 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1834 1835 /* reg_cwtp_profile_max 1836 * Maximum Average Queue size of the profile in cells 1837 * Access: RW 1838 */ 1839 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1840 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1841 1842 #define MLXSW_REG_CWTP_MIN_VALUE 64 1843 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1844 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1845 1846 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1847 u8 traffic_class) 1848 { 1849 int i; 1850 1851 MLXSW_REG_ZERO(cwtp, payload); 1852 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1853 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1854 1855 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1856 mlxsw_reg_cwtp_profile_min_set(payload, i, 1857 MLXSW_REG_CWTP_MIN_VALUE); 1858 mlxsw_reg_cwtp_profile_max_set(payload, i, 1859 MLXSW_REG_CWTP_MIN_VALUE); 1860 } 1861 } 1862 1863 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1864 1865 static inline void 1866 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1867 u32 probability) 1868 { 1869 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1870 1871 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1872 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1873 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1874 } 1875 1876 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1877 * --------------------------------------------------- 1878 * The CWTPM register maps each egress port and traffic class to profile num. 1879 */ 1880 #define MLXSW_REG_CWTPM_ID 0x2803 1881 #define MLXSW_REG_CWTPM_LEN 0x44 1882 1883 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1884 1885 /* reg_cwtpm_local_port 1886 * Local port number 1887 * Not supported for CPU port 1888 * Access: Index 1889 */ 1890 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1891 1892 /* reg_cwtpm_traffic_class 1893 * Traffic Class to configure 1894 * Access: Index 1895 */ 1896 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1897 1898 /* reg_cwtpm_ew 1899 * Control enablement of WRED for traffic class: 1900 * 0 - Disable 1901 * 1 - Enable 1902 * Access: RW 1903 */ 1904 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1905 1906 /* reg_cwtpm_ee 1907 * Control enablement of ECN for traffic class: 1908 * 0 - Disable 1909 * 1 - Enable 1910 * Access: RW 1911 */ 1912 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1913 1914 /* reg_cwtpm_tcp_g 1915 * TCP Green Profile. 1916 * Index of the profile within {port, traffic class} to use. 1917 * 0 for disabling both WRED and ECN for this type of traffic. 1918 * Access: RW 1919 */ 1920 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1921 1922 /* reg_cwtpm_tcp_y 1923 * TCP Yellow Profile. 1924 * Index of the profile within {port, traffic class} to use. 1925 * 0 for disabling both WRED and ECN for this type of traffic. 1926 * Access: RW 1927 */ 1928 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1929 1930 /* reg_cwtpm_tcp_r 1931 * TCP Red Profile. 1932 * Index of the profile within {port, traffic class} to use. 1933 * 0 for disabling both WRED and ECN for this type of traffic. 1934 * Access: RW 1935 */ 1936 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 1937 1938 /* reg_cwtpm_ntcp_g 1939 * Non-TCP Green Profile. 1940 * Index of the profile within {port, traffic class} to use. 1941 * 0 for disabling both WRED and ECN for this type of traffic. 1942 * Access: RW 1943 */ 1944 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 1945 1946 /* reg_cwtpm_ntcp_y 1947 * Non-TCP Yellow Profile. 1948 * Index of the profile within {port, traffic class} to use. 1949 * 0 for disabling both WRED and ECN for this type of traffic. 1950 * Access: RW 1951 */ 1952 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 1953 1954 /* reg_cwtpm_ntcp_r 1955 * Non-TCP Red Profile. 1956 * Index of the profile within {port, traffic class} to use. 1957 * 0 for disabling both WRED and ECN for this type of traffic. 1958 * Access: RW 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 1961 1962 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 1963 1964 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 1965 u8 traffic_class, u8 profile, 1966 bool wred, bool ecn) 1967 { 1968 MLXSW_REG_ZERO(cwtpm, payload); 1969 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 1970 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 1971 mlxsw_reg_cwtpm_ew_set(payload, wred); 1972 mlxsw_reg_cwtpm_ee_set(payload, ecn); 1973 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 1974 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 1975 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 1976 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 1977 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 1978 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 1979 } 1980 1981 /* PGCR - Policy-Engine General Configuration Register 1982 * --------------------------------------------------- 1983 * This register configures general Policy-Engine settings. 1984 */ 1985 #define MLXSW_REG_PGCR_ID 0x3001 1986 #define MLXSW_REG_PGCR_LEN 0x20 1987 1988 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 1989 1990 /* reg_pgcr_default_action_pointer_base 1991 * Default action pointer base. Each region has a default action pointer 1992 * which is equal to default_action_pointer_base + region_id. 1993 * Access: RW 1994 */ 1995 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 1996 1997 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 1998 { 1999 MLXSW_REG_ZERO(pgcr, payload); 2000 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2001 } 2002 2003 /* PPBT - Policy-Engine Port Binding Table 2004 * --------------------------------------- 2005 * This register is used for configuration of the Port Binding Table. 2006 */ 2007 #define MLXSW_REG_PPBT_ID 0x3002 2008 #define MLXSW_REG_PPBT_LEN 0x14 2009 2010 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2011 2012 enum mlxsw_reg_pxbt_e { 2013 MLXSW_REG_PXBT_E_IACL, 2014 MLXSW_REG_PXBT_E_EACL, 2015 }; 2016 2017 /* reg_ppbt_e 2018 * Access: Index 2019 */ 2020 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2021 2022 enum mlxsw_reg_pxbt_op { 2023 MLXSW_REG_PXBT_OP_BIND, 2024 MLXSW_REG_PXBT_OP_UNBIND, 2025 }; 2026 2027 /* reg_ppbt_op 2028 * Access: RW 2029 */ 2030 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2031 2032 /* reg_ppbt_local_port 2033 * Local port. Not including CPU port. 2034 * Access: Index 2035 */ 2036 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2037 2038 /* reg_ppbt_g 2039 * group - When set, the binding is of an ACL group. When cleared, 2040 * the binding is of an ACL. 2041 * Must be set to 1 for Spectrum. 2042 * Access: RW 2043 */ 2044 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2045 2046 /* reg_ppbt_acl_info 2047 * ACL/ACL group identifier. If the g bit is set, this field should hold 2048 * the acl_group_id, else it should hold the acl_id. 2049 * Access: RW 2050 */ 2051 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2052 2053 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2054 enum mlxsw_reg_pxbt_op op, 2055 u8 local_port, u16 acl_info) 2056 { 2057 MLXSW_REG_ZERO(ppbt, payload); 2058 mlxsw_reg_ppbt_e_set(payload, e); 2059 mlxsw_reg_ppbt_op_set(payload, op); 2060 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2061 mlxsw_reg_ppbt_g_set(payload, true); 2062 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2063 } 2064 2065 /* PACL - Policy-Engine ACL Register 2066 * --------------------------------- 2067 * This register is used for configuration of the ACL. 2068 */ 2069 #define MLXSW_REG_PACL_ID 0x3004 2070 #define MLXSW_REG_PACL_LEN 0x70 2071 2072 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2073 2074 /* reg_pacl_v 2075 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2076 * while the ACL is bounded to either a port, VLAN or ACL rule. 2077 * Access: RW 2078 */ 2079 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2080 2081 /* reg_pacl_acl_id 2082 * An identifier representing the ACL (managed by software) 2083 * Range 0 .. cap_max_acl_regions - 1 2084 * Access: Index 2085 */ 2086 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2087 2088 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2089 2090 /* reg_pacl_tcam_region_info 2091 * Opaque object that represents a TCAM region. 2092 * Obtained through PTAR register. 2093 * Access: RW 2094 */ 2095 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2096 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2097 2098 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2099 bool valid, const char *tcam_region_info) 2100 { 2101 MLXSW_REG_ZERO(pacl, payload); 2102 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2103 mlxsw_reg_pacl_v_set(payload, valid); 2104 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2105 } 2106 2107 /* PAGT - Policy-Engine ACL Group Table 2108 * ------------------------------------ 2109 * This register is used for configuration of the ACL Group Table. 2110 */ 2111 #define MLXSW_REG_PAGT_ID 0x3005 2112 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2113 #define MLXSW_REG_PAGT_ACL_LEN 4 2114 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2115 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2116 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2117 2118 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2119 2120 /* reg_pagt_size 2121 * Number of ACLs in the group. 2122 * Size 0 invalidates a group. 2123 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2124 * Total number of ACLs in all groups must be lower or equal 2125 * to cap_max_acl_tot_groups 2126 * Note: a group which is binded must not be invalidated 2127 * Access: Index 2128 */ 2129 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2130 2131 /* reg_pagt_acl_group_id 2132 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2133 * the ACL Group identifier (managed by software). 2134 * Access: Index 2135 */ 2136 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2137 2138 /* reg_pagt_acl_id 2139 * ACL identifier 2140 * Access: RW 2141 */ 2142 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2143 2144 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2145 { 2146 MLXSW_REG_ZERO(pagt, payload); 2147 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2148 } 2149 2150 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2151 u16 acl_id) 2152 { 2153 u8 size = mlxsw_reg_pagt_size_get(payload); 2154 2155 if (index >= size) 2156 mlxsw_reg_pagt_size_set(payload, index + 1); 2157 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2158 } 2159 2160 /* PTAR - Policy-Engine TCAM Allocation Register 2161 * --------------------------------------------- 2162 * This register is used for allocation of regions in the TCAM. 2163 * Note: Query method is not supported on this register. 2164 */ 2165 #define MLXSW_REG_PTAR_ID 0x3006 2166 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2167 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2168 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2169 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2170 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2171 2172 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2173 2174 enum mlxsw_reg_ptar_op { 2175 /* allocate a TCAM region */ 2176 MLXSW_REG_PTAR_OP_ALLOC, 2177 /* resize a TCAM region */ 2178 MLXSW_REG_PTAR_OP_RESIZE, 2179 /* deallocate TCAM region */ 2180 MLXSW_REG_PTAR_OP_FREE, 2181 /* test allocation */ 2182 MLXSW_REG_PTAR_OP_TEST, 2183 }; 2184 2185 /* reg_ptar_op 2186 * Access: OP 2187 */ 2188 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2189 2190 /* reg_ptar_action_set_type 2191 * Type of action set to be used on this region. 2192 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2193 * Access: WO 2194 */ 2195 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2196 2197 enum mlxsw_reg_ptar_key_type { 2198 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2199 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2200 }; 2201 2202 /* reg_ptar_key_type 2203 * TCAM key type for the region. 2204 * Access: WO 2205 */ 2206 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2207 2208 /* reg_ptar_region_size 2209 * TCAM region size. When allocating/resizing this is the requested size, 2210 * the response is the actual size. Note that actual size may be 2211 * larger than requested. 2212 * Allowed range 1 .. cap_max_rules-1 2213 * Reserved during op deallocate. 2214 * Access: WO 2215 */ 2216 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2217 2218 /* reg_ptar_region_id 2219 * Region identifier 2220 * Range 0 .. cap_max_regions-1 2221 * Access: Index 2222 */ 2223 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2224 2225 /* reg_ptar_tcam_region_info 2226 * Opaque object that represents the TCAM region. 2227 * Returned when allocating a region. 2228 * Provided by software for ACL generation and region deallocation and resize. 2229 * Access: RW 2230 */ 2231 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2232 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2233 2234 /* reg_ptar_flexible_key_id 2235 * Identifier of the Flexible Key. 2236 * Only valid if key_type == "FLEX_KEY" 2237 * The key size will be rounded up to one of the following values: 2238 * 9B, 18B, 36B, 54B. 2239 * This field is reserved for in resize operation. 2240 * Access: WO 2241 */ 2242 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2243 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2244 2245 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2246 enum mlxsw_reg_ptar_key_type key_type, 2247 u16 region_size, u16 region_id, 2248 const char *tcam_region_info) 2249 { 2250 MLXSW_REG_ZERO(ptar, payload); 2251 mlxsw_reg_ptar_op_set(payload, op); 2252 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2253 mlxsw_reg_ptar_key_type_set(payload, key_type); 2254 mlxsw_reg_ptar_region_size_set(payload, region_size); 2255 mlxsw_reg_ptar_region_id_set(payload, region_id); 2256 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2257 } 2258 2259 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2260 u16 key_id) 2261 { 2262 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2263 } 2264 2265 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2266 { 2267 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2268 } 2269 2270 /* PPBS - Policy-Engine Policy Based Switching Register 2271 * ---------------------------------------------------- 2272 * This register retrieves and sets Policy Based Switching Table entries. 2273 */ 2274 #define MLXSW_REG_PPBS_ID 0x300C 2275 #define MLXSW_REG_PPBS_LEN 0x14 2276 2277 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2278 2279 /* reg_ppbs_pbs_ptr 2280 * Index into the PBS table. 2281 * For Spectrum, the index points to the KVD Linear. 2282 * Access: Index 2283 */ 2284 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2285 2286 /* reg_ppbs_system_port 2287 * Unique port identifier for the final destination of the packet. 2288 * Access: RW 2289 */ 2290 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2291 2292 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2293 u16 system_port) 2294 { 2295 MLXSW_REG_ZERO(ppbs, payload); 2296 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2297 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2298 } 2299 2300 /* PRCR - Policy-Engine Rules Copy Register 2301 * ---------------------------------------- 2302 * This register is used for accessing rules within a TCAM region. 2303 */ 2304 #define MLXSW_REG_PRCR_ID 0x300D 2305 #define MLXSW_REG_PRCR_LEN 0x40 2306 2307 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2308 2309 enum mlxsw_reg_prcr_op { 2310 /* Move rules. Moves the rules from "tcam_region_info" starting 2311 * at offset "offset" to "dest_tcam_region_info" 2312 * at offset "dest_offset." 2313 */ 2314 MLXSW_REG_PRCR_OP_MOVE, 2315 /* Copy rules. Copies the rules from "tcam_region_info" starting 2316 * at offset "offset" to "dest_tcam_region_info" 2317 * at offset "dest_offset." 2318 */ 2319 MLXSW_REG_PRCR_OP_COPY, 2320 }; 2321 2322 /* reg_prcr_op 2323 * Access: OP 2324 */ 2325 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2326 2327 /* reg_prcr_offset 2328 * Offset within the source region to copy/move from. 2329 * Access: Index 2330 */ 2331 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2332 2333 /* reg_prcr_size 2334 * The number of rules to copy/move. 2335 * Access: WO 2336 */ 2337 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2338 2339 /* reg_prcr_tcam_region_info 2340 * Opaque object that represents the source TCAM region. 2341 * Access: Index 2342 */ 2343 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2344 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2345 2346 /* reg_prcr_dest_offset 2347 * Offset within the source region to copy/move to. 2348 * Access: Index 2349 */ 2350 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2351 2352 /* reg_prcr_dest_tcam_region_info 2353 * Opaque object that represents the destination TCAM region. 2354 * Access: Index 2355 */ 2356 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2357 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2358 2359 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2360 const char *src_tcam_region_info, 2361 u16 src_offset, 2362 const char *dest_tcam_region_info, 2363 u16 dest_offset, u16 size) 2364 { 2365 MLXSW_REG_ZERO(prcr, payload); 2366 mlxsw_reg_prcr_op_set(payload, op); 2367 mlxsw_reg_prcr_offset_set(payload, src_offset); 2368 mlxsw_reg_prcr_size_set(payload, size); 2369 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2370 src_tcam_region_info); 2371 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2372 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2373 dest_tcam_region_info); 2374 } 2375 2376 /* PEFA - Policy-Engine Extended Flexible Action Register 2377 * ------------------------------------------------------ 2378 * This register is used for accessing an extended flexible action entry 2379 * in the central KVD Linear Database. 2380 */ 2381 #define MLXSW_REG_PEFA_ID 0x300F 2382 #define MLXSW_REG_PEFA_LEN 0xB0 2383 2384 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2385 2386 /* reg_pefa_index 2387 * Index in the KVD Linear Centralized Database. 2388 * Access: Index 2389 */ 2390 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2391 2392 /* reg_pefa_a 2393 * Index in the KVD Linear Centralized Database. 2394 * Activity 2395 * For a new entry: set if ca=0, clear if ca=1 2396 * Set if a packet lookup has hit on the specific entry 2397 * Access: RO 2398 */ 2399 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2400 2401 /* reg_pefa_ca 2402 * Clear activity 2403 * When write: activity is according to this field 2404 * When read: after reading the activity is cleared according to ca 2405 * Access: OP 2406 */ 2407 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2408 2409 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2410 2411 /* reg_pefa_flex_action_set 2412 * Action-set to perform when rule is matched. 2413 * Must be zero padded if action set is shorter. 2414 * Access: RW 2415 */ 2416 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2417 2418 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2419 const char *flex_action_set) 2420 { 2421 MLXSW_REG_ZERO(pefa, payload); 2422 mlxsw_reg_pefa_index_set(payload, index); 2423 mlxsw_reg_pefa_ca_set(payload, ca); 2424 if (flex_action_set) 2425 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2426 flex_action_set); 2427 } 2428 2429 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2430 { 2431 *p_a = mlxsw_reg_pefa_a_get(payload); 2432 } 2433 2434 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2435 * ----------------------------------------------------- 2436 * This register is used for accessing rules within a TCAM region. 2437 * It is a new version of PTCE in order to support wider key, 2438 * mask and action within a TCAM region. This register is not supported 2439 * by SwitchX and SwitchX-2. 2440 */ 2441 #define MLXSW_REG_PTCE2_ID 0x3017 2442 #define MLXSW_REG_PTCE2_LEN 0x1D8 2443 2444 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2445 2446 /* reg_ptce2_v 2447 * Valid. 2448 * Access: RW 2449 */ 2450 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2451 2452 /* reg_ptce2_a 2453 * Activity. Set if a packet lookup has hit on the specific entry. 2454 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2455 * Access: RO 2456 */ 2457 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2458 2459 enum mlxsw_reg_ptce2_op { 2460 /* Read operation. */ 2461 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2462 /* clear on read operation. Used to read entry 2463 * and clear Activity bit. 2464 */ 2465 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2466 /* Write operation. Used to write a new entry to the table. 2467 * All R/W fields are relevant for new entry. Activity bit is set 2468 * for new entries - Note write with v = 0 will delete the entry. 2469 */ 2470 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2471 /* Update action. Only action set will be updated. */ 2472 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2473 /* Clear activity. A bit is cleared for the entry. */ 2474 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2475 }; 2476 2477 /* reg_ptce2_op 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2481 2482 /* reg_ptce2_offset 2483 * Access: Index 2484 */ 2485 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2486 2487 /* reg_ptce2_priority 2488 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2489 * Note: priority does not have to be unique per rule. 2490 * Within a region, higher priority should have lower offset (no limitation 2491 * between regions in a multi-region). 2492 * Access: RW 2493 */ 2494 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2495 2496 /* reg_ptce2_tcam_region_info 2497 * Opaque object that represents the TCAM region. 2498 * Access: Index 2499 */ 2500 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2501 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2502 2503 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2504 2505 /* reg_ptce2_flex_key_blocks 2506 * ACL Key. 2507 * Access: RW 2508 */ 2509 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2510 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2511 2512 /* reg_ptce2_mask 2513 * mask- in the same size as key. A bit that is set directs the TCAM 2514 * to compare the corresponding bit in key. A bit that is clear directs 2515 * the TCAM to ignore the corresponding bit in key. 2516 * Access: RW 2517 */ 2518 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2519 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2520 2521 /* reg_ptce2_flex_action_set 2522 * ACL action set. 2523 * Access: RW 2524 */ 2525 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2526 MLXSW_REG_FLEX_ACTION_SET_LEN); 2527 2528 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2529 enum mlxsw_reg_ptce2_op op, 2530 const char *tcam_region_info, 2531 u16 offset, u32 priority) 2532 { 2533 MLXSW_REG_ZERO(ptce2, payload); 2534 mlxsw_reg_ptce2_v_set(payload, valid); 2535 mlxsw_reg_ptce2_op_set(payload, op); 2536 mlxsw_reg_ptce2_offset_set(payload, offset); 2537 mlxsw_reg_ptce2_priority_set(payload, priority); 2538 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2539 } 2540 2541 /* PERPT - Policy-Engine ERP Table Register 2542 * ---------------------------------------- 2543 * This register adds and removes eRPs from the eRP table. 2544 */ 2545 #define MLXSW_REG_PERPT_ID 0x3021 2546 #define MLXSW_REG_PERPT_LEN 0x80 2547 2548 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2549 2550 /* reg_perpt_erpt_bank 2551 * eRP table bank. 2552 * Range 0 .. cap_max_erp_table_banks - 1 2553 * Access: Index 2554 */ 2555 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2556 2557 /* reg_perpt_erpt_index 2558 * Index to eRP table within the eRP bank. 2559 * Range is 0 .. cap_max_erp_table_bank_size - 1 2560 * Access: Index 2561 */ 2562 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2563 2564 enum mlxsw_reg_perpt_key_size { 2565 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2566 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2567 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2568 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2569 }; 2570 2571 /* reg_perpt_key_size 2572 * Access: OP 2573 */ 2574 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2575 2576 /* reg_perpt_bf_bypass 2577 * 0 - The eRP is used only if bloom filter state is set for the given 2578 * rule. 2579 * 1 - The eRP is used regardless of bloom filter state. 2580 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2581 * Access: RW 2582 */ 2583 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2584 2585 /* reg_perpt_erp_id 2586 * eRP ID for use by the rules. 2587 * Access: RW 2588 */ 2589 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2590 2591 /* reg_perpt_erpt_base_bank 2592 * Base eRP table bank, points to head of erp_vector 2593 * Range is 0 .. cap_max_erp_table_banks - 1 2594 * Access: OP 2595 */ 2596 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2597 2598 /* reg_perpt_erpt_base_index 2599 * Base index to eRP table within the eRP bank 2600 * Range is 0 .. cap_max_erp_table_bank_size - 1 2601 * Access: OP 2602 */ 2603 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2604 2605 /* reg_perpt_erp_index_in_vector 2606 * eRP index in the vector. 2607 * Access: OP 2608 */ 2609 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2610 2611 /* reg_perpt_erp_vector 2612 * eRP vector. 2613 * Access: OP 2614 */ 2615 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2616 2617 /* reg_perpt_mask 2618 * Mask 2619 * 0 - A-TCAM will ignore the bit in key 2620 * 1 - A-TCAM will compare the bit in key 2621 * Access: RW 2622 */ 2623 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2624 2625 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2626 unsigned long *erp_vector, 2627 unsigned long size) 2628 { 2629 unsigned long bit; 2630 2631 for_each_set_bit(bit, erp_vector, size) 2632 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2633 } 2634 2635 static inline void 2636 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2637 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2638 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2639 char *mask) 2640 { 2641 MLXSW_REG_ZERO(perpt, payload); 2642 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2643 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2644 mlxsw_reg_perpt_key_size_set(payload, key_size); 2645 mlxsw_reg_perpt_bf_bypass_set(payload, true); 2646 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2647 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2648 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2649 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2650 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2651 } 2652 2653 /* PERAR - Policy-Engine Region Association Register 2654 * ------------------------------------------------- 2655 * This register associates a hw region for region_id's. Changing on the fly 2656 * is supported by the device. 2657 */ 2658 #define MLXSW_REG_PERAR_ID 0x3026 2659 #define MLXSW_REG_PERAR_LEN 0x08 2660 2661 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2662 2663 /* reg_perar_region_id 2664 * Region identifier 2665 * Range 0 .. cap_max_regions-1 2666 * Access: Index 2667 */ 2668 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2669 2670 static inline unsigned int 2671 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2672 { 2673 return DIV_ROUND_UP(block_num, 4); 2674 } 2675 2676 /* reg_perar_hw_region 2677 * HW Region 2678 * Range 0 .. cap_max_regions-1 2679 * Default: hw_region = region_id 2680 * For a 8 key block region, 2 consecutive regions are used 2681 * For a 12 key block region, 3 consecutive regions are used 2682 * Access: RW 2683 */ 2684 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2685 2686 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2687 u16 hw_region) 2688 { 2689 MLXSW_REG_ZERO(perar, payload); 2690 mlxsw_reg_perar_region_id_set(payload, region_id); 2691 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2692 } 2693 2694 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2695 * ----------------------------------------------------- 2696 * This register is a new version of PTCE-V2 in order to support the 2697 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2698 */ 2699 #define MLXSW_REG_PTCE3_ID 0x3027 2700 #define MLXSW_REG_PTCE3_LEN 0xF0 2701 2702 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2703 2704 /* reg_ptce3_v 2705 * Valid. 2706 * Access: RW 2707 */ 2708 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2709 2710 enum mlxsw_reg_ptce3_op { 2711 /* Write operation. Used to write a new entry to the table. 2712 * All R/W fields are relevant for new entry. Activity bit is set 2713 * for new entries. Write with v = 0 will delete the entry. Must 2714 * not be used if an entry exists. 2715 */ 2716 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2717 /* Update operation */ 2718 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2719 /* Read operation */ 2720 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2721 }; 2722 2723 /* reg_ptce3_op 2724 * Access: OP 2725 */ 2726 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2727 2728 /* reg_ptce3_priority 2729 * Priority of the rule. Higher values win. 2730 * For Spectrum-2 range is 1..cap_kvd_size - 1 2731 * Note: Priority does not have to be unique per rule. 2732 * Access: RW 2733 */ 2734 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2735 2736 /* reg_ptce3_tcam_region_info 2737 * Opaque object that represents the TCAM region. 2738 * Access: Index 2739 */ 2740 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2741 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2742 2743 /* reg_ptce3_flex2_key_blocks 2744 * ACL key. The key must be masked according to eRP (if exists) or 2745 * according to master mask. 2746 * Access: Index 2747 */ 2748 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2749 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2750 2751 /* reg_ptce3_erp_id 2752 * eRP ID. 2753 * Access: Index 2754 */ 2755 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2756 2757 /* reg_ptce3_delta_start 2758 * Start point of delta_value and delta_mask, in bits. Must not exceed 2759 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2760 * Access: Index 2761 */ 2762 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2763 2764 /* reg_ptce3_delta_mask 2765 * Delta mask. 2766 * 0 - Ignore relevant bit in delta_value 2767 * 1 - Compare relevant bit in delta_value 2768 * Delta mask must not be set for reserved fields in the key blocks. 2769 * Note: No delta when no eRPs. Thus, for regions with 2770 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2771 * Access: Index 2772 */ 2773 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2774 2775 /* reg_ptce3_delta_value 2776 * Delta value. 2777 * Bits which are masked by delta_mask must be 0. 2778 * Access: Index 2779 */ 2780 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2781 2782 /* reg_ptce3_prune_vector 2783 * Pruning vector relative to the PERPT.erp_id. 2784 * Used for reducing lookups. 2785 * 0 - NEED: Do a lookup using the eRP. 2786 * 1 - PRUNE: Do not perform a lookup using the eRP. 2787 * Maybe be modified by PEAPBL and PEAPBM. 2788 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2789 * all 1's or all 0's. 2790 * Access: RW 2791 */ 2792 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2793 2794 /* reg_ptce3_prune_ctcam 2795 * Pruning on C-TCAM. Used for reducing lookups. 2796 * 0 - NEED: Do a lookup in the C-TCAM. 2797 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2798 * Access: RW 2799 */ 2800 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2801 2802 /* reg_ptce3_large_exists 2803 * Large entry key ID exists. 2804 * Within the region: 2805 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2806 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2807 * For rule delete: The MSB of the key will be removed. 2808 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2809 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2810 * For rule delete: The MSB of the key will not be removed. 2811 * Access: WO 2812 */ 2813 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2814 2815 /* reg_ptce3_large_entry_key_id 2816 * Large entry key ID. 2817 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2818 * blocks. Must be different for different keys which have the same common 2819 * 6 key blocks (MSB, blocks 6..11) key within a region. 2820 * Range is 0..cap_max_pe_large_key_id - 1 2821 * Access: RW 2822 */ 2823 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2824 2825 /* reg_ptce3_action_pointer 2826 * Pointer to action. 2827 * Range is 0..cap_max_kvd_action_sets - 1 2828 * Access: RW 2829 */ 2830 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2831 2832 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2833 enum mlxsw_reg_ptce3_op op, 2834 u32 priority, 2835 const char *tcam_region_info, 2836 const char *key, u8 erp_id, 2837 bool large_exists, u32 lkey_id, 2838 u32 action_pointer) 2839 { 2840 MLXSW_REG_ZERO(ptce3, payload); 2841 mlxsw_reg_ptce3_v_set(payload, valid); 2842 mlxsw_reg_ptce3_op_set(payload, op); 2843 mlxsw_reg_ptce3_priority_set(payload, priority); 2844 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2845 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2846 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2847 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2848 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2849 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2850 } 2851 2852 /* PERCR - Policy-Engine Region Configuration Register 2853 * --------------------------------------------------- 2854 * This register configures the region parameters. The region_id must be 2855 * allocated. 2856 */ 2857 #define MLXSW_REG_PERCR_ID 0x302A 2858 #define MLXSW_REG_PERCR_LEN 0x80 2859 2860 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2861 2862 /* reg_percr_region_id 2863 * Region identifier. 2864 * Range 0..cap_max_regions-1 2865 * Access: Index 2866 */ 2867 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2868 2869 /* reg_percr_atcam_ignore_prune 2870 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2871 * Access: RW 2872 */ 2873 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2874 2875 /* reg_percr_ctcam_ignore_prune 2876 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2877 * Access: RW 2878 */ 2879 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2880 2881 /* reg_percr_bf_bypass 2882 * Bloom filter bypass. 2883 * 0 - Bloom filter is used (default) 2884 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2885 * region_id or eRP. See PERPT.bf_bypass 2886 * Access: RW 2887 */ 2888 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 2889 2890 /* reg_percr_master_mask 2891 * Master mask. Logical OR mask of all masks of all rules of a region 2892 * (both A-TCAM and C-TCAM). When there are no eRPs 2893 * (erpt_pointer_valid = 0), then this provides the mask. 2894 * Access: RW 2895 */ 2896 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 2897 2898 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 2899 { 2900 MLXSW_REG_ZERO(percr, payload); 2901 mlxsw_reg_percr_region_id_set(payload, region_id); 2902 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 2903 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 2904 mlxsw_reg_percr_bf_bypass_set(payload, true); 2905 } 2906 2907 /* PERERP - Policy-Engine Region eRP Register 2908 * ------------------------------------------ 2909 * This register configures the region eRP. The region_id must be 2910 * allocated. 2911 */ 2912 #define MLXSW_REG_PERERP_ID 0x302B 2913 #define MLXSW_REG_PERERP_LEN 0x1C 2914 2915 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 2916 2917 /* reg_pererp_region_id 2918 * Region identifier. 2919 * Range 0..cap_max_regions-1 2920 * Access: Index 2921 */ 2922 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 2923 2924 /* reg_pererp_ctcam_le 2925 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 2926 * Access: RW 2927 */ 2928 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 2929 2930 /* reg_pererp_erpt_pointer_valid 2931 * erpt_pointer is valid. 2932 * Access: RW 2933 */ 2934 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 2935 2936 /* reg_pererp_erpt_bank_pointer 2937 * Pointer to eRP table bank. May be modified at any time. 2938 * Range 0..cap_max_erp_table_banks-1 2939 * Reserved when erpt_pointer_valid = 0 2940 */ 2941 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 2942 2943 /* reg_pererp_erpt_pointer 2944 * Pointer to eRP table within the eRP bank. Can be changed for an 2945 * existing region. 2946 * Range 0..cap_max_erp_table_size-1 2947 * Reserved when erpt_pointer_valid = 0 2948 * Access: RW 2949 */ 2950 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 2951 2952 /* reg_pererp_erpt_vector 2953 * Vector of allowed eRP indexes starting from erpt_pointer within the 2954 * erpt_bank_pointer. Next entries will be in next bank. 2955 * Note that eRP index is used and not eRP ID. 2956 * Reserved when erpt_pointer_valid = 0 2957 * Access: RW 2958 */ 2959 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 2960 2961 /* reg_pererp_master_rp_id 2962 * Master RP ID. When there are no eRPs, then this provides the eRP ID 2963 * for the lookup. Can be changed for an existing region. 2964 * Reserved when erpt_pointer_valid = 1 2965 * Access: RW 2966 */ 2967 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 2968 2969 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 2970 unsigned long *erp_vector, 2971 unsigned long size) 2972 { 2973 unsigned long bit; 2974 2975 for_each_set_bit(bit, erp_vector, size) 2976 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 2977 } 2978 2979 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 2980 bool ctcam_le, bool erpt_pointer_valid, 2981 u8 erpt_bank_pointer, u8 erpt_pointer, 2982 u8 master_rp_id) 2983 { 2984 MLXSW_REG_ZERO(pererp, payload); 2985 mlxsw_reg_pererp_region_id_set(payload, region_id); 2986 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 2987 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 2988 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 2989 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 2990 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 2991 } 2992 2993 /* IEDR - Infrastructure Entry Delete Register 2994 * ---------------------------------------------------- 2995 * This register is used for deleting entries from the entry tables. 2996 * It is legitimate to attempt to delete a nonexisting entry (the device will 2997 * respond as a good flow). 2998 */ 2999 #define MLXSW_REG_IEDR_ID 0x3804 3000 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3001 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3002 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3003 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3004 MLXSW_REG_IEDR_REC_LEN * \ 3005 MLXSW_REG_IEDR_REC_MAX_COUNT) 3006 3007 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3008 3009 /* reg_iedr_num_rec 3010 * Number of records. 3011 * Access: OP 3012 */ 3013 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3014 3015 /* reg_iedr_rec_type 3016 * Resource type. 3017 * Access: OP 3018 */ 3019 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3020 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3021 3022 /* reg_iedr_rec_size 3023 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3024 * Access: OP 3025 */ 3026 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3027 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3028 3029 /* reg_iedr_rec_index_start 3030 * Resource index start. 3031 * Access: OP 3032 */ 3033 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3034 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3035 3036 static inline void mlxsw_reg_iedr_pack(char *payload) 3037 { 3038 MLXSW_REG_ZERO(iedr, payload); 3039 } 3040 3041 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3042 u8 rec_type, u16 rec_size, 3043 u32 rec_index_start) 3044 { 3045 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3046 3047 if (rec_index >= num_rec) 3048 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3049 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3050 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3051 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3052 } 3053 3054 /* QPTS - QoS Priority Trust State Register 3055 * ---------------------------------------- 3056 * This register controls the port policy to calculate the switch priority and 3057 * packet color based on incoming packet fields. 3058 */ 3059 #define MLXSW_REG_QPTS_ID 0x4002 3060 #define MLXSW_REG_QPTS_LEN 0x8 3061 3062 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3063 3064 /* reg_qpts_local_port 3065 * Local port number. 3066 * Access: Index 3067 * 3068 * Note: CPU port is supported. 3069 */ 3070 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3071 3072 enum mlxsw_reg_qpts_trust_state { 3073 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3074 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3075 }; 3076 3077 /* reg_qpts_trust_state 3078 * Trust state for a given port. 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3082 3083 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3084 enum mlxsw_reg_qpts_trust_state ts) 3085 { 3086 MLXSW_REG_ZERO(qpts, payload); 3087 3088 mlxsw_reg_qpts_local_port_set(payload, local_port); 3089 mlxsw_reg_qpts_trust_state_set(payload, ts); 3090 } 3091 3092 /* QPCR - QoS Policer Configuration Register 3093 * ----------------------------------------- 3094 * The QPCR register is used to create policers - that limit 3095 * the rate of bytes or packets via some trap group. 3096 */ 3097 #define MLXSW_REG_QPCR_ID 0x4004 3098 #define MLXSW_REG_QPCR_LEN 0x28 3099 3100 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3101 3102 enum mlxsw_reg_qpcr_g { 3103 MLXSW_REG_QPCR_G_GLOBAL = 2, 3104 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3105 }; 3106 3107 /* reg_qpcr_g 3108 * The policer type. 3109 * Access: Index 3110 */ 3111 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3112 3113 /* reg_qpcr_pid 3114 * Policer ID. 3115 * Access: Index 3116 */ 3117 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3118 3119 /* reg_qpcr_color_aware 3120 * Is the policer aware of colors. 3121 * Must be 0 (unaware) for cpu port. 3122 * Access: RW for unbounded policer. RO for bounded policer. 3123 */ 3124 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3125 3126 /* reg_qpcr_bytes 3127 * Is policer limit is for bytes per sec or packets per sec. 3128 * 0 - packets 3129 * 1 - bytes 3130 * Access: RW for unbounded policer. RO for bounded policer. 3131 */ 3132 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3133 3134 enum mlxsw_reg_qpcr_ir_units { 3135 MLXSW_REG_QPCR_IR_UNITS_M, 3136 MLXSW_REG_QPCR_IR_UNITS_K, 3137 }; 3138 3139 /* reg_qpcr_ir_units 3140 * Policer's units for cir and eir fields (for bytes limits only) 3141 * 1 - 10^3 3142 * 0 - 10^6 3143 * Access: OP 3144 */ 3145 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3146 3147 enum mlxsw_reg_qpcr_rate_type { 3148 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3149 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3150 }; 3151 3152 /* reg_qpcr_rate_type 3153 * Policer can have one limit (single rate) or 2 limits with specific operation 3154 * for packets that exceed the lower rate but not the upper one. 3155 * (For cpu port must be single rate) 3156 * Access: RW for unbounded policer. RO for bounded policer. 3157 */ 3158 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3159 3160 /* reg_qpc_cbs 3161 * Policer's committed burst size. 3162 * The policer is working with time slices of 50 nano sec. By default every 3163 * slice is granted the proportionate share of the committed rate. If we want to 3164 * allow a slice to exceed that share (while still keeping the rate per sec) we 3165 * can allow burst. The burst size is between the default proportionate share 3166 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3167 * committed rate will result in exceeding the rate). The burst size must be a 3168 * log of 2 and will be determined by 2^cbs. 3169 * Access: RW 3170 */ 3171 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3172 3173 /* reg_qpcr_cir 3174 * Policer's committed rate. 3175 * The rate used for sungle rate, the lower rate for double rate. 3176 * For bytes limits, the rate will be this value * the unit from ir_units. 3177 * (Resolution error is up to 1%). 3178 * Access: RW 3179 */ 3180 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3181 3182 /* reg_qpcr_eir 3183 * Policer's exceed rate. 3184 * The higher rate for double rate, reserved for single rate. 3185 * Lower rate for double rate policer. 3186 * For bytes limits, the rate will be this value * the unit from ir_units. 3187 * (Resolution error is up to 1%). 3188 * Access: RW 3189 */ 3190 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3191 3192 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3193 3194 /* reg_qpcr_exceed_action. 3195 * What to do with packets between the 2 limits for double rate. 3196 * Access: RW for unbounded policer. RO for bounded policer. 3197 */ 3198 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3199 3200 enum mlxsw_reg_qpcr_action { 3201 /* Discard */ 3202 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3203 /* Forward and set color to red. 3204 * If the packet is intended to cpu port, it will be dropped. 3205 */ 3206 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3207 }; 3208 3209 /* reg_qpcr_violate_action 3210 * What to do with packets that cross the cir limit (for single rate) or the eir 3211 * limit (for double rate). 3212 * Access: RW for unbounded policer. RO for bounded policer. 3213 */ 3214 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3215 3216 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3217 enum mlxsw_reg_qpcr_ir_units ir_units, 3218 bool bytes, u32 cir, u16 cbs) 3219 { 3220 MLXSW_REG_ZERO(qpcr, payload); 3221 mlxsw_reg_qpcr_pid_set(payload, pid); 3222 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3223 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3224 mlxsw_reg_qpcr_violate_action_set(payload, 3225 MLXSW_REG_QPCR_ACTION_DISCARD); 3226 mlxsw_reg_qpcr_cir_set(payload, cir); 3227 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3228 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3229 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3230 } 3231 3232 /* QTCT - QoS Switch Traffic Class Table 3233 * ------------------------------------- 3234 * Configures the mapping between the packet switch priority and the 3235 * traffic class on the transmit port. 3236 */ 3237 #define MLXSW_REG_QTCT_ID 0x400A 3238 #define MLXSW_REG_QTCT_LEN 0x08 3239 3240 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3241 3242 /* reg_qtct_local_port 3243 * Local port number. 3244 * Access: Index 3245 * 3246 * Note: CPU port is not supported. 3247 */ 3248 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3249 3250 /* reg_qtct_sub_port 3251 * Virtual port within the physical port. 3252 * Should be set to 0 when virtual ports are not enabled on the port. 3253 * Access: Index 3254 */ 3255 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3256 3257 /* reg_qtct_switch_prio 3258 * Switch priority. 3259 * Access: Index 3260 */ 3261 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3262 3263 /* reg_qtct_tclass 3264 * Traffic class. 3265 * Default values: 3266 * switch_prio 0 : tclass 1 3267 * switch_prio 1 : tclass 0 3268 * switch_prio i : tclass i, for i > 1 3269 * Access: RW 3270 */ 3271 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3272 3273 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3274 u8 switch_prio, u8 tclass) 3275 { 3276 MLXSW_REG_ZERO(qtct, payload); 3277 mlxsw_reg_qtct_local_port_set(payload, local_port); 3278 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3279 mlxsw_reg_qtct_tclass_set(payload, tclass); 3280 } 3281 3282 /* QEEC - QoS ETS Element Configuration Register 3283 * --------------------------------------------- 3284 * Configures the ETS elements. 3285 */ 3286 #define MLXSW_REG_QEEC_ID 0x400D 3287 #define MLXSW_REG_QEEC_LEN 0x20 3288 3289 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3290 3291 /* reg_qeec_local_port 3292 * Local port number. 3293 * Access: Index 3294 * 3295 * Note: CPU port is supported. 3296 */ 3297 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3298 3299 enum mlxsw_reg_qeec_hr { 3300 MLXSW_REG_QEEC_HIERARCY_PORT, 3301 MLXSW_REG_QEEC_HIERARCY_GROUP, 3302 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3303 MLXSW_REG_QEEC_HIERARCY_TC, 3304 }; 3305 3306 /* reg_qeec_element_hierarchy 3307 * 0 - Port 3308 * 1 - Group 3309 * 2 - Subgroup 3310 * 3 - Traffic Class 3311 * Access: Index 3312 */ 3313 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3314 3315 /* reg_qeec_element_index 3316 * The index of the element in the hierarchy. 3317 * Access: Index 3318 */ 3319 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3320 3321 /* reg_qeec_next_element_index 3322 * The index of the next (lower) element in the hierarchy. 3323 * Access: RW 3324 * 3325 * Note: Reserved for element_hierarchy 0. 3326 */ 3327 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3328 3329 /* reg_qeec_mise 3330 * Min shaper configuration enable. Enables configuration of the min 3331 * shaper on this ETS element 3332 * 0 - Disable 3333 * 1 - Enable 3334 * Access: RW 3335 */ 3336 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3337 3338 enum { 3339 MLXSW_REG_QEEC_BYTES_MODE, 3340 MLXSW_REG_QEEC_PACKETS_MODE, 3341 }; 3342 3343 /* reg_qeec_pb 3344 * Packets or bytes mode. 3345 * 0 - Bytes mode 3346 * 1 - Packets mode 3347 * Access: RW 3348 * 3349 * Note: Used for max shaper configuration. For Spectrum, packets mode 3350 * is supported only for traffic classes of CPU port. 3351 */ 3352 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3353 3354 /* The smallest permitted min shaper rate. */ 3355 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3356 3357 /* reg_qeec_min_shaper_rate 3358 * Min shaper information rate. 3359 * For CPU port, can only be configured for port hierarchy. 3360 * When in bytes mode, value is specified in units of 1000bps. 3361 * Access: RW 3362 */ 3363 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3364 3365 /* reg_qeec_mase 3366 * Max shaper configuration enable. Enables configuration of the max 3367 * shaper on this ETS element. 3368 * 0 - Disable 3369 * 1 - Enable 3370 * Access: RW 3371 */ 3372 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3373 3374 /* A large max rate will disable the max shaper. */ 3375 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3376 3377 /* reg_qeec_max_shaper_rate 3378 * Max shaper information rate. 3379 * For CPU port, can only be configured for port hierarchy. 3380 * When in bytes mode, value is specified in units of 1000bps. 3381 * Access: RW 3382 */ 3383 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3384 3385 /* reg_qeec_de 3386 * DWRR configuration enable. Enables configuration of the dwrr and 3387 * dwrr_weight. 3388 * 0 - Disable 3389 * 1 - Enable 3390 * Access: RW 3391 */ 3392 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3393 3394 /* reg_qeec_dwrr 3395 * Transmission selection algorithm to use on the link going down from 3396 * the ETS element. 3397 * 0 - Strict priority 3398 * 1 - DWRR 3399 * Access: RW 3400 */ 3401 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3402 3403 /* reg_qeec_dwrr_weight 3404 * DWRR weight on the link going down from the ETS element. The 3405 * percentage of bandwidth guaranteed to an ETS element within 3406 * its hierarchy. The sum of all weights across all ETS elements 3407 * within one hierarchy should be equal to 100. Reserved when 3408 * transmission selection algorithm is strict priority. 3409 * Access: RW 3410 */ 3411 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3412 3413 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3414 enum mlxsw_reg_qeec_hr hr, u8 index, 3415 u8 next_index) 3416 { 3417 MLXSW_REG_ZERO(qeec, payload); 3418 mlxsw_reg_qeec_local_port_set(payload, local_port); 3419 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3420 mlxsw_reg_qeec_element_index_set(payload, index); 3421 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3422 } 3423 3424 /* QRWE - QoS ReWrite Enable 3425 * ------------------------- 3426 * This register configures the rewrite enable per receive port. 3427 */ 3428 #define MLXSW_REG_QRWE_ID 0x400F 3429 #define MLXSW_REG_QRWE_LEN 0x08 3430 3431 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3432 3433 /* reg_qrwe_local_port 3434 * Local port number. 3435 * Access: Index 3436 * 3437 * Note: CPU port is supported. No support for router port. 3438 */ 3439 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3440 3441 /* reg_qrwe_dscp 3442 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3443 * Access: RW 3444 */ 3445 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3446 3447 /* reg_qrwe_pcp 3448 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3449 * Access: RW 3450 */ 3451 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3452 3453 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3454 bool rewrite_pcp, bool rewrite_dscp) 3455 { 3456 MLXSW_REG_ZERO(qrwe, payload); 3457 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3458 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3459 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3460 } 3461 3462 /* QPDSM - QoS Priority to DSCP Mapping 3463 * ------------------------------------ 3464 * QoS Priority to DSCP Mapping Register 3465 */ 3466 #define MLXSW_REG_QPDSM_ID 0x4011 3467 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3468 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3469 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3470 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3471 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3472 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3473 3474 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3475 3476 /* reg_qpdsm_local_port 3477 * Local Port. Supported for data packets from CPU port. 3478 * Access: Index 3479 */ 3480 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3481 3482 /* reg_qpdsm_prio_entry_color0_e 3483 * Enable update of the entry for color 0 and a given port. 3484 * Access: WO 3485 */ 3486 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3487 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3488 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3489 3490 /* reg_qpdsm_prio_entry_color0_dscp 3491 * DSCP field in the outer label of the packet for color 0 and a given port. 3492 * Reserved when e=0. 3493 * Access: RW 3494 */ 3495 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3496 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3497 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3498 3499 /* reg_qpdsm_prio_entry_color1_e 3500 * Enable update of the entry for color 1 and a given port. 3501 * Access: WO 3502 */ 3503 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3504 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3505 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3506 3507 /* reg_qpdsm_prio_entry_color1_dscp 3508 * DSCP field in the outer label of the packet for color 1 and a given port. 3509 * Reserved when e=0. 3510 * Access: RW 3511 */ 3512 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3513 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3514 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3515 3516 /* reg_qpdsm_prio_entry_color2_e 3517 * Enable update of the entry for color 2 and a given port. 3518 * Access: WO 3519 */ 3520 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3521 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3522 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3523 3524 /* reg_qpdsm_prio_entry_color2_dscp 3525 * DSCP field in the outer label of the packet for color 2 and a given port. 3526 * Reserved when e=0. 3527 * Access: RW 3528 */ 3529 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3530 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3531 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3532 3533 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3534 { 3535 MLXSW_REG_ZERO(qpdsm, payload); 3536 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3537 } 3538 3539 static inline void 3540 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3541 { 3542 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3543 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3544 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3545 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3546 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3547 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3548 } 3549 3550 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3551 * -------------------------------------------------- 3552 * This register controls the mapping from DSCP field to 3553 * Switch Priority for IP packets. 3554 */ 3555 #define MLXSW_REG_QPDPM_ID 0x4013 3556 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3557 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3558 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3559 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3560 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3561 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3562 3563 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3564 3565 /* reg_qpdpm_local_port 3566 * Local Port. Supported for data packets from CPU port. 3567 * Access: Index 3568 */ 3569 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3570 3571 /* reg_qpdpm_dscp_e 3572 * Enable update of the specific entry. When cleared, the switch_prio and color 3573 * fields are ignored and the previous switch_prio and color values are 3574 * preserved. 3575 * Access: WO 3576 */ 3577 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3578 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3579 3580 /* reg_qpdpm_dscp_prio 3581 * The new Switch Priority value for the relevant DSCP value. 3582 * Access: RW 3583 */ 3584 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3585 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3586 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3587 3588 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3589 { 3590 MLXSW_REG_ZERO(qpdpm, payload); 3591 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3592 } 3593 3594 static inline void 3595 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3596 { 3597 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3598 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3599 } 3600 3601 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3602 * ------------------------------------------------------------------ 3603 * This register configures if the Switch Priority to Traffic Class mapping is 3604 * based on Multicast packet indication. If so, then multicast packets will get 3605 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3606 * QTCT. 3607 * By default, Switch Priority to Traffic Class mapping is not based on 3608 * Multicast packet indication. 3609 */ 3610 #define MLXSW_REG_QTCTM_ID 0x401A 3611 #define MLXSW_REG_QTCTM_LEN 0x08 3612 3613 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3614 3615 /* reg_qtctm_local_port 3616 * Local port number. 3617 * No support for CPU port. 3618 * Access: Index 3619 */ 3620 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3621 3622 /* reg_qtctm_mc 3623 * Multicast Mode 3624 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3625 * indication (default is 0, not based on Multicast packet indication). 3626 */ 3627 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3628 3629 static inline void 3630 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3631 { 3632 MLXSW_REG_ZERO(qtctm, payload); 3633 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3634 mlxsw_reg_qtctm_mc_set(payload, mc); 3635 } 3636 3637 /* PMLP - Ports Module to Local Port Register 3638 * ------------------------------------------ 3639 * Configures the assignment of modules to local ports. 3640 */ 3641 #define MLXSW_REG_PMLP_ID 0x5002 3642 #define MLXSW_REG_PMLP_LEN 0x40 3643 3644 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3645 3646 /* reg_pmlp_rxtx 3647 * 0 - Tx value is used for both Tx and Rx. 3648 * 1 - Rx value is taken from a separte field. 3649 * Access: RW 3650 */ 3651 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3652 3653 /* reg_pmlp_local_port 3654 * Local port number. 3655 * Access: Index 3656 */ 3657 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3658 3659 /* reg_pmlp_width 3660 * 0 - Unmap local port. 3661 * 1 - Lane 0 is used. 3662 * 2 - Lanes 0 and 1 are used. 3663 * 4 - Lanes 0, 1, 2 and 3 are used. 3664 * Access: RW 3665 */ 3666 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3667 3668 /* reg_pmlp_module 3669 * Module number. 3670 * Access: RW 3671 */ 3672 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3673 3674 /* reg_pmlp_tx_lane 3675 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3676 * Access: RW 3677 */ 3678 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3679 3680 /* reg_pmlp_rx_lane 3681 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3682 * equal to Tx lane. 3683 * Access: RW 3684 */ 3685 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3686 3687 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3688 { 3689 MLXSW_REG_ZERO(pmlp, payload); 3690 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3691 } 3692 3693 /* PMTU - Port MTU Register 3694 * ------------------------ 3695 * Configures and reports the port MTU. 3696 */ 3697 #define MLXSW_REG_PMTU_ID 0x5003 3698 #define MLXSW_REG_PMTU_LEN 0x10 3699 3700 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3701 3702 /* reg_pmtu_local_port 3703 * Local port number. 3704 * Access: Index 3705 */ 3706 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3707 3708 /* reg_pmtu_max_mtu 3709 * Maximum MTU. 3710 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3711 * reported, otherwise the minimum between the max_mtu of the different 3712 * types is reported. 3713 * Access: RO 3714 */ 3715 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3716 3717 /* reg_pmtu_admin_mtu 3718 * MTU value to set port to. Must be smaller or equal to max_mtu. 3719 * Note: If port type is Infiniband, then port must be disabled, when its 3720 * MTU is set. 3721 * Access: RW 3722 */ 3723 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3724 3725 /* reg_pmtu_oper_mtu 3726 * The actual MTU configured on the port. Packets exceeding this size 3727 * will be dropped. 3728 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3729 * oper_mtu might be smaller than admin_mtu. 3730 * Access: RO 3731 */ 3732 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3733 3734 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3735 u16 new_mtu) 3736 { 3737 MLXSW_REG_ZERO(pmtu, payload); 3738 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3739 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3740 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3741 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3742 } 3743 3744 /* PTYS - Port Type and Speed Register 3745 * ----------------------------------- 3746 * Configures and reports the port speed type. 3747 * 3748 * Note: When set while the link is up, the changes will not take effect 3749 * until the port transitions from down to up state. 3750 */ 3751 #define MLXSW_REG_PTYS_ID 0x5004 3752 #define MLXSW_REG_PTYS_LEN 0x40 3753 3754 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3755 3756 /* an_disable_admin 3757 * Auto negotiation disable administrative configuration 3758 * 0 - Device doesn't support AN disable. 3759 * 1 - Device supports AN disable. 3760 * Access: RW 3761 */ 3762 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3763 3764 /* reg_ptys_local_port 3765 * Local port number. 3766 * Access: Index 3767 */ 3768 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3769 3770 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3771 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3772 3773 /* reg_ptys_proto_mask 3774 * Protocol mask. Indicates which protocol is used. 3775 * 0 - Infiniband. 3776 * 1 - Fibre Channel. 3777 * 2 - Ethernet. 3778 * Access: Index 3779 */ 3780 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3781 3782 enum { 3783 MLXSW_REG_PTYS_AN_STATUS_NA, 3784 MLXSW_REG_PTYS_AN_STATUS_OK, 3785 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3786 }; 3787 3788 /* reg_ptys_an_status 3789 * Autonegotiation status. 3790 * Access: RO 3791 */ 3792 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3793 3794 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3795 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3796 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3797 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3798 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3799 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3800 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3801 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3802 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3803 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3804 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3805 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3806 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3807 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3808 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3809 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3810 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3811 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3812 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3813 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3814 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3815 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3816 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3817 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3818 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3819 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 3820 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 3821 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 3822 3823 /* reg_ptys_eth_proto_cap 3824 * Ethernet port supported speeds and protocols. 3825 * Access: RO 3826 */ 3827 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 3828 3829 /* reg_ptys_ib_link_width_cap 3830 * IB port supported widths. 3831 * Access: RO 3832 */ 3833 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 3834 3835 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 3836 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 3837 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 3838 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 3839 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 3840 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 3841 3842 /* reg_ptys_ib_proto_cap 3843 * IB port supported speeds and protocols. 3844 * Access: RO 3845 */ 3846 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 3847 3848 /* reg_ptys_eth_proto_admin 3849 * Speed and protocol to set port to. 3850 * Access: RW 3851 */ 3852 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 3853 3854 /* reg_ptys_ib_link_width_admin 3855 * IB width to set port to. 3856 * Access: RW 3857 */ 3858 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 3859 3860 /* reg_ptys_ib_proto_admin 3861 * IB speeds and protocols to set port to. 3862 * Access: RW 3863 */ 3864 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 3865 3866 /* reg_ptys_eth_proto_oper 3867 * The current speed and protocol configured for the port. 3868 * Access: RO 3869 */ 3870 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 3871 3872 /* reg_ptys_ib_link_width_oper 3873 * The current IB width to set port to. 3874 * Access: RO 3875 */ 3876 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 3877 3878 /* reg_ptys_ib_proto_oper 3879 * The current IB speed and protocol. 3880 * Access: RO 3881 */ 3882 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3883 3884 /* reg_ptys_eth_proto_lp_advertise 3885 * The protocols that were advertised by the link partner during 3886 * autonegotiation. 3887 * Access: RO 3888 */ 3889 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3890 3891 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3892 u32 proto_admin, bool autoneg) 3893 { 3894 MLXSW_REG_ZERO(ptys, payload); 3895 mlxsw_reg_ptys_local_port_set(payload, local_port); 3896 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 3897 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 3898 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 3899 } 3900 3901 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 3902 u32 *p_eth_proto_cap, 3903 u32 *p_eth_proto_adm, 3904 u32 *p_eth_proto_oper) 3905 { 3906 if (p_eth_proto_cap) 3907 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 3908 if (p_eth_proto_adm) 3909 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 3910 if (p_eth_proto_oper) 3911 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 3912 } 3913 3914 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 3915 u16 proto_admin, u16 link_width) 3916 { 3917 MLXSW_REG_ZERO(ptys, payload); 3918 mlxsw_reg_ptys_local_port_set(payload, local_port); 3919 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 3920 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 3921 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 3922 } 3923 3924 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 3925 u16 *p_ib_link_width_cap, 3926 u16 *p_ib_proto_oper, 3927 u16 *p_ib_link_width_oper) 3928 { 3929 if (p_ib_proto_cap) 3930 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 3931 if (p_ib_link_width_cap) 3932 *p_ib_link_width_cap = 3933 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 3934 if (p_ib_proto_oper) 3935 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 3936 if (p_ib_link_width_oper) 3937 *p_ib_link_width_oper = 3938 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 3939 } 3940 3941 /* PPAD - Port Physical Address Register 3942 * ------------------------------------- 3943 * The PPAD register configures the per port physical MAC address. 3944 */ 3945 #define MLXSW_REG_PPAD_ID 0x5005 3946 #define MLXSW_REG_PPAD_LEN 0x10 3947 3948 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 3949 3950 /* reg_ppad_single_base_mac 3951 * 0: base_mac, local port should be 0 and mac[7:0] is 3952 * reserved. HW will set incremental 3953 * 1: single_mac - mac of the local_port 3954 * Access: RW 3955 */ 3956 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 3957 3958 /* reg_ppad_local_port 3959 * port number, if single_base_mac = 0 then local_port is reserved 3960 * Access: RW 3961 */ 3962 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 3963 3964 /* reg_ppad_mac 3965 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 3966 * If single_base_mac = 1 - the per port MAC address 3967 * Access: RW 3968 */ 3969 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 3970 3971 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 3972 u8 local_port) 3973 { 3974 MLXSW_REG_ZERO(ppad, payload); 3975 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 3976 mlxsw_reg_ppad_local_port_set(payload, local_port); 3977 } 3978 3979 /* PAOS - Ports Administrative and Operational Status Register 3980 * ----------------------------------------------------------- 3981 * Configures and retrieves per port administrative and operational status. 3982 */ 3983 #define MLXSW_REG_PAOS_ID 0x5006 3984 #define MLXSW_REG_PAOS_LEN 0x10 3985 3986 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 3987 3988 /* reg_paos_swid 3989 * Switch partition ID with which to associate the port. 3990 * Note: while external ports uses unique local port numbers (and thus swid is 3991 * redundant), router ports use the same local port number where swid is the 3992 * only indication for the relevant port. 3993 * Access: Index 3994 */ 3995 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 3996 3997 /* reg_paos_local_port 3998 * Local port number. 3999 * Access: Index 4000 */ 4001 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4002 4003 /* reg_paos_admin_status 4004 * Port administrative state (the desired state of the port): 4005 * 1 - Up. 4006 * 2 - Down. 4007 * 3 - Up once. This means that in case of link failure, the port won't go 4008 * into polling mode, but will wait to be re-enabled by software. 4009 * 4 - Disabled by system. Can only be set by hardware. 4010 * Access: RW 4011 */ 4012 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4013 4014 /* reg_paos_oper_status 4015 * Port operational state (the current state): 4016 * 1 - Up. 4017 * 2 - Down. 4018 * 3 - Down by port failure. This means that the device will not let the 4019 * port up again until explicitly specified by software. 4020 * Access: RO 4021 */ 4022 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4023 4024 /* reg_paos_ase 4025 * Admin state update enabled. 4026 * Access: WO 4027 */ 4028 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4029 4030 /* reg_paos_ee 4031 * Event update enable. If this bit is set, event generation will be 4032 * updated based on the e field. 4033 * Access: WO 4034 */ 4035 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4036 4037 /* reg_paos_e 4038 * Event generation on operational state change: 4039 * 0 - Do not generate event. 4040 * 1 - Generate Event. 4041 * 2 - Generate Single Event. 4042 * Access: RW 4043 */ 4044 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4045 4046 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4047 enum mlxsw_port_admin_status status) 4048 { 4049 MLXSW_REG_ZERO(paos, payload); 4050 mlxsw_reg_paos_swid_set(payload, 0); 4051 mlxsw_reg_paos_local_port_set(payload, local_port); 4052 mlxsw_reg_paos_admin_status_set(payload, status); 4053 mlxsw_reg_paos_oper_status_set(payload, 0); 4054 mlxsw_reg_paos_ase_set(payload, 1); 4055 mlxsw_reg_paos_ee_set(payload, 1); 4056 mlxsw_reg_paos_e_set(payload, 1); 4057 } 4058 4059 /* PFCC - Ports Flow Control Configuration Register 4060 * ------------------------------------------------ 4061 * Configures and retrieves the per port flow control configuration. 4062 */ 4063 #define MLXSW_REG_PFCC_ID 0x5007 4064 #define MLXSW_REG_PFCC_LEN 0x20 4065 4066 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4067 4068 /* reg_pfcc_local_port 4069 * Local port number. 4070 * Access: Index 4071 */ 4072 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4073 4074 /* reg_pfcc_pnat 4075 * Port number access type. Determines the way local_port is interpreted: 4076 * 0 - Local port number. 4077 * 1 - IB / label port number. 4078 * Access: Index 4079 */ 4080 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4081 4082 /* reg_pfcc_shl_cap 4083 * Send to higher layers capabilities: 4084 * 0 - No capability of sending Pause and PFC frames to higher layers. 4085 * 1 - Device has capability of sending Pause and PFC frames to higher 4086 * layers. 4087 * Access: RO 4088 */ 4089 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4090 4091 /* reg_pfcc_shl_opr 4092 * Send to higher layers operation: 4093 * 0 - Pause and PFC frames are handled by the port (default). 4094 * 1 - Pause and PFC frames are handled by the port and also sent to 4095 * higher layers. Only valid if shl_cap = 1. 4096 * Access: RW 4097 */ 4098 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4099 4100 /* reg_pfcc_ppan 4101 * Pause policy auto negotiation. 4102 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4103 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4104 * based on the auto-negotiation resolution. 4105 * Access: RW 4106 * 4107 * Note: The auto-negotiation advertisement is set according to pptx and 4108 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4109 */ 4110 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4111 4112 /* reg_pfcc_prio_mask_tx 4113 * Bit per priority indicating if Tx flow control policy should be 4114 * updated based on bit pfctx. 4115 * Access: WO 4116 */ 4117 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4118 4119 /* reg_pfcc_prio_mask_rx 4120 * Bit per priority indicating if Rx flow control policy should be 4121 * updated based on bit pfcrx. 4122 * Access: WO 4123 */ 4124 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4125 4126 /* reg_pfcc_pptx 4127 * Admin Pause policy on Tx. 4128 * 0 - Never generate Pause frames (default). 4129 * 1 - Generate Pause frames according to Rx buffer threshold. 4130 * Access: RW 4131 */ 4132 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4133 4134 /* reg_pfcc_aptx 4135 * Active (operational) Pause policy on Tx. 4136 * 0 - Never generate Pause frames. 4137 * 1 - Generate Pause frames according to Rx buffer threshold. 4138 * Access: RO 4139 */ 4140 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4141 4142 /* reg_pfcc_pfctx 4143 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4144 * 0 - Never generate priority Pause frames on the specified priority 4145 * (default). 4146 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4147 * the specified priority. 4148 * Access: RW 4149 * 4150 * Note: pfctx and pptx must be mutually exclusive. 4151 */ 4152 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4153 4154 /* reg_pfcc_pprx 4155 * Admin Pause policy on Rx. 4156 * 0 - Ignore received Pause frames (default). 4157 * 1 - Respect received Pause frames. 4158 * Access: RW 4159 */ 4160 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4161 4162 /* reg_pfcc_aprx 4163 * Active (operational) Pause policy on Rx. 4164 * 0 - Ignore received Pause frames. 4165 * 1 - Respect received Pause frames. 4166 * Access: RO 4167 */ 4168 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4169 4170 /* reg_pfcc_pfcrx 4171 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4172 * 0 - Ignore incoming priority Pause frames on the specified priority 4173 * (default). 4174 * 1 - Respect incoming priority Pause frames on the specified priority. 4175 * Access: RW 4176 */ 4177 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4178 4179 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4180 4181 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4182 { 4183 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4184 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4185 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4186 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4187 } 4188 4189 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4190 { 4191 MLXSW_REG_ZERO(pfcc, payload); 4192 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4193 } 4194 4195 /* PPCNT - Ports Performance Counters Register 4196 * ------------------------------------------- 4197 * The PPCNT register retrieves per port performance counters. 4198 */ 4199 #define MLXSW_REG_PPCNT_ID 0x5008 4200 #define MLXSW_REG_PPCNT_LEN 0x100 4201 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4202 4203 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4204 4205 /* reg_ppcnt_swid 4206 * For HCA: must be always 0. 4207 * Switch partition ID to associate port with. 4208 * Switch partitions are numbered from 0 to 7 inclusively. 4209 * Switch partition 254 indicates stacking ports. 4210 * Switch partition 255 indicates all switch partitions. 4211 * Only valid on Set() operation with local_port=255. 4212 * Access: Index 4213 */ 4214 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4215 4216 /* reg_ppcnt_local_port 4217 * Local port number. 4218 * 255 indicates all ports on the device, and is only allowed 4219 * for Set() operation. 4220 * Access: Index 4221 */ 4222 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4223 4224 /* reg_ppcnt_pnat 4225 * Port number access type: 4226 * 0 - Local port number 4227 * 1 - IB port number 4228 * Access: Index 4229 */ 4230 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4231 4232 enum mlxsw_reg_ppcnt_grp { 4233 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4234 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4235 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4236 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4237 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4238 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4239 }; 4240 4241 /* reg_ppcnt_grp 4242 * Performance counter group. 4243 * Group 63 indicates all groups. Only valid on Set() operation with 4244 * clr bit set. 4245 * 0x0: IEEE 802.3 Counters 4246 * 0x1: RFC 2863 Counters 4247 * 0x2: RFC 2819 Counters 4248 * 0x3: RFC 3635 Counters 4249 * 0x5: Ethernet Extended Counters 4250 * 0x8: Link Level Retransmission Counters 4251 * 0x10: Per Priority Counters 4252 * 0x11: Per Traffic Class Counters 4253 * 0x12: Physical Layer Counters 4254 * 0x13: Per Traffic Class Congestion Counters 4255 * Access: Index 4256 */ 4257 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4258 4259 /* reg_ppcnt_clr 4260 * Clear counters. Setting the clr bit will reset the counter value 4261 * for all counters in the counter group. This bit can be set 4262 * for both Set() and Get() operation. 4263 * Access: OP 4264 */ 4265 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4266 4267 /* reg_ppcnt_prio_tc 4268 * Priority for counter set that support per priority, valid values: 0-7. 4269 * Traffic class for counter set that support per traffic class, 4270 * valid values: 0- cap_max_tclass-1 . 4271 * For HCA: cap_max_tclass is always 8. 4272 * Otherwise must be 0. 4273 * Access: Index 4274 */ 4275 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4276 4277 /* Ethernet IEEE 802.3 Counter Group */ 4278 4279 /* reg_ppcnt_a_frames_transmitted_ok 4280 * Access: RO 4281 */ 4282 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4283 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4284 4285 /* reg_ppcnt_a_frames_received_ok 4286 * Access: RO 4287 */ 4288 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4289 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4290 4291 /* reg_ppcnt_a_frame_check_sequence_errors 4292 * Access: RO 4293 */ 4294 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4295 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4296 4297 /* reg_ppcnt_a_alignment_errors 4298 * Access: RO 4299 */ 4300 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4301 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4302 4303 /* reg_ppcnt_a_octets_transmitted_ok 4304 * Access: RO 4305 */ 4306 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4307 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4308 4309 /* reg_ppcnt_a_octets_received_ok 4310 * Access: RO 4311 */ 4312 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4313 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4314 4315 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4316 * Access: RO 4317 */ 4318 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4319 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4320 4321 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4322 * Access: RO 4323 */ 4324 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4325 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4326 4327 /* reg_ppcnt_a_multicast_frames_received_ok 4328 * Access: RO 4329 */ 4330 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4331 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4332 4333 /* reg_ppcnt_a_broadcast_frames_received_ok 4334 * Access: RO 4335 */ 4336 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4337 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4338 4339 /* reg_ppcnt_a_in_range_length_errors 4340 * Access: RO 4341 */ 4342 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4343 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4344 4345 /* reg_ppcnt_a_out_of_range_length_field 4346 * Access: RO 4347 */ 4348 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4349 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4350 4351 /* reg_ppcnt_a_frame_too_long_errors 4352 * Access: RO 4353 */ 4354 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4356 4357 /* reg_ppcnt_a_symbol_error_during_carrier 4358 * Access: RO 4359 */ 4360 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4362 4363 /* reg_ppcnt_a_mac_control_frames_transmitted 4364 * Access: RO 4365 */ 4366 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4368 4369 /* reg_ppcnt_a_mac_control_frames_received 4370 * Access: RO 4371 */ 4372 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4373 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4374 4375 /* reg_ppcnt_a_unsupported_opcodes_received 4376 * Access: RO 4377 */ 4378 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4379 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4380 4381 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4382 * Access: RO 4383 */ 4384 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4385 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4386 4387 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4388 * Access: RO 4389 */ 4390 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4391 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4392 4393 /* Ethernet RFC 2819 Counter Group */ 4394 4395 /* reg_ppcnt_ether_stats_pkts64octets 4396 * Access: RO 4397 */ 4398 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4399 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4400 4401 /* reg_ppcnt_ether_stats_pkts65to127octets 4402 * Access: RO 4403 */ 4404 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4405 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4406 4407 /* reg_ppcnt_ether_stats_pkts128to255octets 4408 * Access: RO 4409 */ 4410 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4411 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4412 4413 /* reg_ppcnt_ether_stats_pkts256to511octets 4414 * Access: RO 4415 */ 4416 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4417 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4418 4419 /* reg_ppcnt_ether_stats_pkts512to1023octets 4420 * Access: RO 4421 */ 4422 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4423 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4424 4425 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4426 * Access: RO 4427 */ 4428 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4429 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4430 4431 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4432 * Access: RO 4433 */ 4434 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4435 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4436 4437 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4438 * Access: RO 4439 */ 4440 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4441 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4442 4443 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4444 * Access: RO 4445 */ 4446 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4447 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4448 4449 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4450 * Access: RO 4451 */ 4452 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4453 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4454 4455 /* Ethernet Extended Counter Group Counters */ 4456 4457 /* reg_ppcnt_ecn_marked 4458 * Access: RO 4459 */ 4460 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4462 4463 /* Ethernet Per Priority Group Counters */ 4464 4465 /* reg_ppcnt_rx_octets 4466 * Access: RO 4467 */ 4468 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4469 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4470 4471 /* reg_ppcnt_rx_frames 4472 * Access: RO 4473 */ 4474 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4475 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4476 4477 /* reg_ppcnt_tx_octets 4478 * Access: RO 4479 */ 4480 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4481 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4482 4483 /* reg_ppcnt_tx_frames 4484 * Access: RO 4485 */ 4486 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4487 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4488 4489 /* reg_ppcnt_rx_pause 4490 * Access: RO 4491 */ 4492 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4493 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4494 4495 /* reg_ppcnt_rx_pause_duration 4496 * Access: RO 4497 */ 4498 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4499 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4500 4501 /* reg_ppcnt_tx_pause 4502 * Access: RO 4503 */ 4504 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4505 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4506 4507 /* reg_ppcnt_tx_pause_duration 4508 * Access: RO 4509 */ 4510 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4511 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4512 4513 /* reg_ppcnt_rx_pause_transition 4514 * Access: RO 4515 */ 4516 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4517 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4518 4519 /* Ethernet Per Traffic Group Counters */ 4520 4521 /* reg_ppcnt_tc_transmit_queue 4522 * Contains the transmit queue depth in cells of traffic class 4523 * selected by prio_tc and the port selected by local_port. 4524 * The field cannot be cleared. 4525 * Access: RO 4526 */ 4527 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4528 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4529 4530 /* reg_ppcnt_tc_no_buffer_discard_uc 4531 * The number of unicast packets dropped due to lack of shared 4532 * buffer resources. 4533 * Access: RO 4534 */ 4535 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4536 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4537 4538 /* Ethernet Per Traffic Class Congestion Group Counters */ 4539 4540 /* reg_ppcnt_wred_discard 4541 * Access: RO 4542 */ 4543 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4544 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4545 4546 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4547 enum mlxsw_reg_ppcnt_grp grp, 4548 u8 prio_tc) 4549 { 4550 MLXSW_REG_ZERO(ppcnt, payload); 4551 mlxsw_reg_ppcnt_swid_set(payload, 0); 4552 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4553 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4554 mlxsw_reg_ppcnt_grp_set(payload, grp); 4555 mlxsw_reg_ppcnt_clr_set(payload, 0); 4556 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4557 } 4558 4559 /* PLIB - Port Local to InfiniBand Port 4560 * ------------------------------------ 4561 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4562 */ 4563 #define MLXSW_REG_PLIB_ID 0x500A 4564 #define MLXSW_REG_PLIB_LEN 0x10 4565 4566 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4567 4568 /* reg_plib_local_port 4569 * Local port number. 4570 * Access: Index 4571 */ 4572 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4573 4574 /* reg_plib_ib_port 4575 * InfiniBand port remapping for local_port. 4576 * Access: RW 4577 */ 4578 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4579 4580 /* PPTB - Port Prio To Buffer Register 4581 * ----------------------------------- 4582 * Configures the switch priority to buffer table. 4583 */ 4584 #define MLXSW_REG_PPTB_ID 0x500B 4585 #define MLXSW_REG_PPTB_LEN 0x10 4586 4587 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4588 4589 enum { 4590 MLXSW_REG_PPTB_MM_UM, 4591 MLXSW_REG_PPTB_MM_UNICAST, 4592 MLXSW_REG_PPTB_MM_MULTICAST, 4593 }; 4594 4595 /* reg_pptb_mm 4596 * Mapping mode. 4597 * 0 - Map both unicast and multicast packets to the same buffer. 4598 * 1 - Map only unicast packets. 4599 * 2 - Map only multicast packets. 4600 * Access: Index 4601 * 4602 * Note: SwitchX-2 only supports the first option. 4603 */ 4604 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4605 4606 /* reg_pptb_local_port 4607 * Local port number. 4608 * Access: Index 4609 */ 4610 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4611 4612 /* reg_pptb_um 4613 * Enables the update of the untagged_buf field. 4614 * Access: RW 4615 */ 4616 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4617 4618 /* reg_pptb_pm 4619 * Enables the update of the prio_to_buff field. 4620 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4621 * Access: RW 4622 */ 4623 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4624 4625 /* reg_pptb_prio_to_buff 4626 * Mapping of switch priority <i> to one of the allocated receive port 4627 * buffers. 4628 * Access: RW 4629 */ 4630 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4631 4632 /* reg_pptb_pm_msb 4633 * Enables the update of the prio_to_buff field. 4634 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4635 * Access: RW 4636 */ 4637 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4638 4639 /* reg_pptb_untagged_buff 4640 * Mapping of untagged frames to one of the allocated receive port buffers. 4641 * Access: RW 4642 * 4643 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4644 * Spectrum, as it maps untagged packets based on the default switch priority. 4645 */ 4646 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4647 4648 /* reg_pptb_prio_to_buff_msb 4649 * Mapping of switch priority <i+8> to one of the allocated receive port 4650 * buffers. 4651 * Access: RW 4652 */ 4653 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4654 4655 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4656 4657 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4658 { 4659 MLXSW_REG_ZERO(pptb, payload); 4660 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4661 mlxsw_reg_pptb_local_port_set(payload, local_port); 4662 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4663 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4664 } 4665 4666 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4667 u8 buff) 4668 { 4669 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4670 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4671 } 4672 4673 /* PBMC - Port Buffer Management Control Register 4674 * ---------------------------------------------- 4675 * The PBMC register configures and retrieves the port packet buffer 4676 * allocation for different Prios, and the Pause threshold management. 4677 */ 4678 #define MLXSW_REG_PBMC_ID 0x500C 4679 #define MLXSW_REG_PBMC_LEN 0x6C 4680 4681 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 4682 4683 /* reg_pbmc_local_port 4684 * Local port number. 4685 * Access: Index 4686 */ 4687 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 4688 4689 /* reg_pbmc_xoff_timer_value 4690 * When device generates a pause frame, it uses this value as the pause 4691 * timer (time for the peer port to pause in quota-512 bit time). 4692 * Access: RW 4693 */ 4694 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 4695 4696 /* reg_pbmc_xoff_refresh 4697 * The time before a new pause frame should be sent to refresh the pause RW 4698 * state. Using the same units as xoff_timer_value above (in quota-512 bit 4699 * time). 4700 * Access: RW 4701 */ 4702 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 4703 4704 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 4705 4706 /* reg_pbmc_buf_lossy 4707 * The field indicates if the buffer is lossy. 4708 * 0 - Lossless 4709 * 1 - Lossy 4710 * Access: RW 4711 */ 4712 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 4713 4714 /* reg_pbmc_buf_epsb 4715 * Eligible for Port Shared buffer. 4716 * If epsb is set, packets assigned to buffer are allowed to insert the port 4717 * shared buffer. 4718 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 4719 * Access: RW 4720 */ 4721 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 4722 4723 /* reg_pbmc_buf_size 4724 * The part of the packet buffer array is allocated for the specific buffer. 4725 * Units are represented in cells. 4726 * Access: RW 4727 */ 4728 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 4729 4730 /* reg_pbmc_buf_xoff_threshold 4731 * Once the amount of data in the buffer goes above this value, device 4732 * starts sending PFC frames for all priorities associated with the 4733 * buffer. Units are represented in cells. Reserved in case of lossy 4734 * buffer. 4735 * Access: RW 4736 * 4737 * Note: In Spectrum, reserved for buffer[9]. 4738 */ 4739 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 4740 0x08, 0x04, false); 4741 4742 /* reg_pbmc_buf_xon_threshold 4743 * When the amount of data in the buffer goes below this value, device 4744 * stops sending PFC frames for the priorities associated with the 4745 * buffer. Units are represented in cells. Reserved in case of lossy 4746 * buffer. 4747 * Access: RW 4748 * 4749 * Note: In Spectrum, reserved for buffer[9]. 4750 */ 4751 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 4752 0x08, 0x04, false); 4753 4754 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 4755 u16 xoff_timer_value, u16 xoff_refresh) 4756 { 4757 MLXSW_REG_ZERO(pbmc, payload); 4758 mlxsw_reg_pbmc_local_port_set(payload, local_port); 4759 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 4760 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 4761 } 4762 4763 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 4764 int buf_index, 4765 u16 size) 4766 { 4767 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 4768 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4769 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4770 } 4771 4772 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 4773 int buf_index, u16 size, 4774 u16 threshold) 4775 { 4776 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 4777 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 4778 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 4779 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 4780 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 4781 } 4782 4783 /* PSPA - Port Switch Partition Allocation 4784 * --------------------------------------- 4785 * Controls the association of a port with a switch partition and enables 4786 * configuring ports as stacking ports. 4787 */ 4788 #define MLXSW_REG_PSPA_ID 0x500D 4789 #define MLXSW_REG_PSPA_LEN 0x8 4790 4791 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 4792 4793 /* reg_pspa_swid 4794 * Switch partition ID. 4795 * Access: RW 4796 */ 4797 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 4798 4799 /* reg_pspa_local_port 4800 * Local port number. 4801 * Access: Index 4802 */ 4803 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 4804 4805 /* reg_pspa_sub_port 4806 * Virtual port within the local port. Set to 0 when virtual ports are 4807 * disabled on the local port. 4808 * Access: Index 4809 */ 4810 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 4811 4812 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 4813 { 4814 MLXSW_REG_ZERO(pspa, payload); 4815 mlxsw_reg_pspa_swid_set(payload, swid); 4816 mlxsw_reg_pspa_local_port_set(payload, local_port); 4817 mlxsw_reg_pspa_sub_port_set(payload, 0); 4818 } 4819 4820 /* HTGT - Host Trap Group Table 4821 * ---------------------------- 4822 * Configures the properties for forwarding to CPU. 4823 */ 4824 #define MLXSW_REG_HTGT_ID 0x7002 4825 #define MLXSW_REG_HTGT_LEN 0x20 4826 4827 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 4828 4829 /* reg_htgt_swid 4830 * Switch partition ID. 4831 * Access: Index 4832 */ 4833 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 4834 4835 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 4836 4837 /* reg_htgt_type 4838 * CPU path type. 4839 * Access: RW 4840 */ 4841 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 4842 4843 enum mlxsw_reg_htgt_trap_group { 4844 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 4845 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 4846 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 4847 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 4848 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 4849 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 4850 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 4851 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 4852 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 4853 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 4854 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 4855 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 4856 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 4857 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 4858 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 4859 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 4860 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 4861 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 4862 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 4863 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 4864 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 4865 }; 4866 4867 /* reg_htgt_trap_group 4868 * Trap group number. User defined number specifying which trap groups 4869 * should be forwarded to the CPU. The mapping between trap IDs and trap 4870 * groups is configured using HPKT register. 4871 * Access: Index 4872 */ 4873 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 4874 4875 enum { 4876 MLXSW_REG_HTGT_POLICER_DISABLE, 4877 MLXSW_REG_HTGT_POLICER_ENABLE, 4878 }; 4879 4880 /* reg_htgt_pide 4881 * Enable policer ID specified using 'pid' field. 4882 * Access: RW 4883 */ 4884 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 4885 4886 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 4887 4888 /* reg_htgt_pid 4889 * Policer ID for the trap group. 4890 * Access: RW 4891 */ 4892 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 4893 4894 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 4895 4896 /* reg_htgt_mirror_action 4897 * Mirror action to use. 4898 * 0 - Trap to CPU. 4899 * 1 - Trap to CPU and mirror to a mirroring agent. 4900 * 2 - Mirror to a mirroring agent and do not trap to CPU. 4901 * Access: RW 4902 * 4903 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 4904 */ 4905 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 4906 4907 /* reg_htgt_mirroring_agent 4908 * Mirroring agent. 4909 * Access: RW 4910 */ 4911 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 4912 4913 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 4914 4915 /* reg_htgt_priority 4916 * Trap group priority. 4917 * In case a packet matches multiple classification rules, the packet will 4918 * only be trapped once, based on the trap ID associated with the group (via 4919 * register HPKT) with the highest priority. 4920 * Supported values are 0-7, with 7 represnting the highest priority. 4921 * Access: RW 4922 * 4923 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 4924 * by the 'trap_group' field. 4925 */ 4926 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 4927 4928 #define MLXSW_REG_HTGT_DEFAULT_TC 7 4929 4930 /* reg_htgt_local_path_cpu_tclass 4931 * CPU ingress traffic class for the trap group. 4932 * Access: RW 4933 */ 4934 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 4935 4936 enum mlxsw_reg_htgt_local_path_rdq { 4937 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 4938 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 4939 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 4940 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 4941 }; 4942 /* reg_htgt_local_path_rdq 4943 * Receive descriptor queue (RDQ) to use for the trap group. 4944 * Access: RW 4945 */ 4946 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 4947 4948 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 4949 u8 priority, u8 tc) 4950 { 4951 MLXSW_REG_ZERO(htgt, payload); 4952 4953 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 4954 mlxsw_reg_htgt_pide_set(payload, 4955 MLXSW_REG_HTGT_POLICER_DISABLE); 4956 } else { 4957 mlxsw_reg_htgt_pide_set(payload, 4958 MLXSW_REG_HTGT_POLICER_ENABLE); 4959 mlxsw_reg_htgt_pid_set(payload, policer_id); 4960 } 4961 4962 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 4963 mlxsw_reg_htgt_trap_group_set(payload, group); 4964 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 4965 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 4966 mlxsw_reg_htgt_priority_set(payload, priority); 4967 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 4968 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 4969 } 4970 4971 /* HPKT - Host Packet Trap 4972 * ----------------------- 4973 * Configures trap IDs inside trap groups. 4974 */ 4975 #define MLXSW_REG_HPKT_ID 0x7003 4976 #define MLXSW_REG_HPKT_LEN 0x10 4977 4978 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 4979 4980 enum { 4981 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 4982 MLXSW_REG_HPKT_ACK_REQUIRED, 4983 }; 4984 4985 /* reg_hpkt_ack 4986 * Require acknowledgements from the host for events. 4987 * If set, then the device will wait for the event it sent to be acknowledged 4988 * by the host. This option is only relevant for event trap IDs. 4989 * Access: RW 4990 * 4991 * Note: Currently not supported by firmware. 4992 */ 4993 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 4994 4995 enum mlxsw_reg_hpkt_action { 4996 MLXSW_REG_HPKT_ACTION_FORWARD, 4997 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 4998 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 4999 MLXSW_REG_HPKT_ACTION_DISCARD, 5000 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5001 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5002 }; 5003 5004 /* reg_hpkt_action 5005 * Action to perform on packet when trapped. 5006 * 0 - No action. Forward to CPU based on switching rules. 5007 * 1 - Trap to CPU (CPU receives sole copy). 5008 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5009 * 3 - Discard. 5010 * 4 - Soft discard (allow other traps to act on the packet). 5011 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5012 * Access: RW 5013 * 5014 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5015 * addressed to the CPU. 5016 */ 5017 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5018 5019 /* reg_hpkt_trap_group 5020 * Trap group to associate the trap with. 5021 * Access: RW 5022 */ 5023 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5024 5025 /* reg_hpkt_trap_id 5026 * Trap ID. 5027 * Access: Index 5028 * 5029 * Note: A trap ID can only be associated with a single trap group. The device 5030 * will associate the trap ID with the last trap group configured. 5031 */ 5032 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5033 5034 enum { 5035 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5036 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5037 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5038 }; 5039 5040 /* reg_hpkt_ctrl 5041 * Configure dedicated buffer resources for control packets. 5042 * Ignored by SwitchX-2. 5043 * 0 - Keep factory defaults. 5044 * 1 - Do not use control buffer for this trap ID. 5045 * 2 - Use control buffer for this trap ID. 5046 * Access: RW 5047 */ 5048 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5049 5050 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5051 enum mlxsw_reg_htgt_trap_group trap_group, 5052 bool is_ctrl) 5053 { 5054 MLXSW_REG_ZERO(hpkt, payload); 5055 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5056 mlxsw_reg_hpkt_action_set(payload, action); 5057 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5058 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5059 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5060 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5061 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5062 } 5063 5064 /* RGCR - Router General Configuration Register 5065 * -------------------------------------------- 5066 * The register is used for setting up the router configuration. 5067 */ 5068 #define MLXSW_REG_RGCR_ID 0x8001 5069 #define MLXSW_REG_RGCR_LEN 0x28 5070 5071 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5072 5073 /* reg_rgcr_ipv4_en 5074 * IPv4 router enable. 5075 * Access: RW 5076 */ 5077 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5078 5079 /* reg_rgcr_ipv6_en 5080 * IPv6 router enable. 5081 * Access: RW 5082 */ 5083 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5084 5085 /* reg_rgcr_max_router_interfaces 5086 * Defines the maximum number of active router interfaces for all virtual 5087 * routers. 5088 * Access: RW 5089 */ 5090 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5091 5092 /* reg_rgcr_usp 5093 * Update switch priority and packet color. 5094 * 0 - Preserve the value of Switch Priority and packet color. 5095 * 1 - Recalculate the value of Switch Priority and packet color. 5096 * Access: RW 5097 * 5098 * Note: Not supported by SwitchX and SwitchX-2. 5099 */ 5100 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5101 5102 /* reg_rgcr_pcp_rw 5103 * Indicates how to handle the pcp_rewrite_en value: 5104 * 0 - Preserve the value of pcp_rewrite_en. 5105 * 2 - Disable PCP rewrite. 5106 * 3 - Enable PCP rewrite. 5107 * Access: RW 5108 * 5109 * Note: Not supported by SwitchX and SwitchX-2. 5110 */ 5111 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5112 5113 /* reg_rgcr_activity_dis 5114 * Activity disable: 5115 * 0 - Activity will be set when an entry is hit (default). 5116 * 1 - Activity will not be set when an entry is hit. 5117 * 5118 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5119 * (RALUE). 5120 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5121 * Entry (RAUHT). 5122 * Bits 2:7 are reserved. 5123 * Access: RW 5124 * 5125 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5126 */ 5127 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5128 5129 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5130 bool ipv6_en) 5131 { 5132 MLXSW_REG_ZERO(rgcr, payload); 5133 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5134 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5135 } 5136 5137 /* RITR - Router Interface Table Register 5138 * -------------------------------------- 5139 * The register is used to configure the router interface table. 5140 */ 5141 #define MLXSW_REG_RITR_ID 0x8002 5142 #define MLXSW_REG_RITR_LEN 0x40 5143 5144 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5145 5146 /* reg_ritr_enable 5147 * Enables routing on the router interface. 5148 * Access: RW 5149 */ 5150 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5151 5152 /* reg_ritr_ipv4 5153 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5154 * interface. 5155 * Access: RW 5156 */ 5157 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5158 5159 /* reg_ritr_ipv6 5160 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5161 * interface. 5162 * Access: RW 5163 */ 5164 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5165 5166 /* reg_ritr_ipv4_mc 5167 * IPv4 multicast routing enable. 5168 * Access: RW 5169 */ 5170 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5171 5172 /* reg_ritr_ipv6_mc 5173 * IPv6 multicast routing enable. 5174 * Access: RW 5175 */ 5176 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5177 5178 enum mlxsw_reg_ritr_if_type { 5179 /* VLAN interface. */ 5180 MLXSW_REG_RITR_VLAN_IF, 5181 /* FID interface. */ 5182 MLXSW_REG_RITR_FID_IF, 5183 /* Sub-port interface. */ 5184 MLXSW_REG_RITR_SP_IF, 5185 /* Loopback Interface. */ 5186 MLXSW_REG_RITR_LOOPBACK_IF, 5187 }; 5188 5189 /* reg_ritr_type 5190 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5191 * Access: RW 5192 */ 5193 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5194 5195 enum { 5196 MLXSW_REG_RITR_RIF_CREATE, 5197 MLXSW_REG_RITR_RIF_DEL, 5198 }; 5199 5200 /* reg_ritr_op 5201 * Opcode: 5202 * 0 - Create or edit RIF. 5203 * 1 - Delete RIF. 5204 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5205 * is not supported. An interface must be deleted and re-created in order 5206 * to update properties. 5207 * Access: WO 5208 */ 5209 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5210 5211 /* reg_ritr_rif 5212 * Router interface index. A pointer to the Router Interface Table. 5213 * Access: Index 5214 */ 5215 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5216 5217 /* reg_ritr_ipv4_fe 5218 * IPv4 Forwarding Enable. 5219 * Enables routing of IPv4 traffic on the router interface. When disabled, 5220 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5221 * Not supported in SwitchX-2. 5222 * Access: RW 5223 */ 5224 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5225 5226 /* reg_ritr_ipv6_fe 5227 * IPv6 Forwarding Enable. 5228 * Enables routing of IPv6 traffic on the router interface. When disabled, 5229 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5230 * Not supported in SwitchX-2. 5231 * Access: RW 5232 */ 5233 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5234 5235 /* reg_ritr_ipv4_mc_fe 5236 * IPv4 Multicast Forwarding Enable. 5237 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5238 * will be enabled. 5239 * Access: RW 5240 */ 5241 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5242 5243 /* reg_ritr_ipv6_mc_fe 5244 * IPv6 Multicast Forwarding Enable. 5245 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5246 * will be enabled. 5247 * Access: RW 5248 */ 5249 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5250 5251 /* reg_ritr_lb_en 5252 * Loop-back filter enable for unicast packets. 5253 * If the flag is set then loop-back filter for unicast packets is 5254 * implemented on the RIF. Multicast packets are always subject to 5255 * loop-back filtering. 5256 * Access: RW 5257 */ 5258 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5259 5260 /* reg_ritr_virtual_router 5261 * Virtual router ID associated with the router interface. 5262 * Access: RW 5263 */ 5264 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5265 5266 /* reg_ritr_mtu 5267 * Router interface MTU. 5268 * Access: RW 5269 */ 5270 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5271 5272 /* reg_ritr_if_swid 5273 * Switch partition ID. 5274 * Access: RW 5275 */ 5276 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5277 5278 /* reg_ritr_if_mac 5279 * Router interface MAC address. 5280 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5281 * Access: RW 5282 */ 5283 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5284 5285 /* reg_ritr_if_vrrp_id_ipv6 5286 * VRRP ID for IPv6 5287 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5288 * Access: RW 5289 */ 5290 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5291 5292 /* reg_ritr_if_vrrp_id_ipv4 5293 * VRRP ID for IPv4 5294 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5295 * Access: RW 5296 */ 5297 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5298 5299 /* VLAN Interface */ 5300 5301 /* reg_ritr_vlan_if_vid 5302 * VLAN ID. 5303 * Access: RW 5304 */ 5305 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5306 5307 /* FID Interface */ 5308 5309 /* reg_ritr_fid_if_fid 5310 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5311 * the vFID range are supported. 5312 * Access: RW 5313 */ 5314 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5315 5316 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5317 enum mlxsw_reg_ritr_if_type rif_type, 5318 u16 fid) 5319 { 5320 if (rif_type == MLXSW_REG_RITR_FID_IF) 5321 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5322 else 5323 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5324 } 5325 5326 /* Sub-port Interface */ 5327 5328 /* reg_ritr_sp_if_lag 5329 * LAG indication. When this bit is set the system_port field holds the 5330 * LAG identifier. 5331 * Access: RW 5332 */ 5333 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5334 5335 /* reg_ritr_sp_system_port 5336 * Port unique indentifier. When lag bit is set, this field holds the 5337 * lag_id in bits 0:9. 5338 * Access: RW 5339 */ 5340 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5341 5342 /* reg_ritr_sp_if_vid 5343 * VLAN ID. 5344 * Access: RW 5345 */ 5346 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5347 5348 /* Loopback Interface */ 5349 5350 enum mlxsw_reg_ritr_loopback_protocol { 5351 /* IPinIP IPv4 underlay Unicast */ 5352 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5353 /* IPinIP IPv6 underlay Unicast */ 5354 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5355 }; 5356 5357 /* reg_ritr_loopback_protocol 5358 * Access: RW 5359 */ 5360 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5361 5362 enum mlxsw_reg_ritr_loopback_ipip_type { 5363 /* Tunnel is IPinIP. */ 5364 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5365 /* Tunnel is GRE, no key. */ 5366 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5367 /* Tunnel is GRE, with a key. */ 5368 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5369 }; 5370 5371 /* reg_ritr_loopback_ipip_type 5372 * Encapsulation type. 5373 * Access: RW 5374 */ 5375 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5376 5377 enum mlxsw_reg_ritr_loopback_ipip_options { 5378 /* The key is defined by gre_key. */ 5379 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5380 }; 5381 5382 /* reg_ritr_loopback_ipip_options 5383 * Access: RW 5384 */ 5385 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5386 5387 /* reg_ritr_loopback_ipip_uvr 5388 * Underlay Virtual Router ID. 5389 * Range is 0..cap_max_virtual_routers-1. 5390 * Reserved for Spectrum-2. 5391 * Access: RW 5392 */ 5393 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5394 5395 /* reg_ritr_loopback_ipip_usip* 5396 * Encapsulation Underlay source IP. 5397 * Access: RW 5398 */ 5399 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5400 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5401 5402 /* reg_ritr_loopback_ipip_gre_key 5403 * GRE Key. 5404 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5405 * Access: RW 5406 */ 5407 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5408 5409 /* Shared between ingress/egress */ 5410 enum mlxsw_reg_ritr_counter_set_type { 5411 /* No Count. */ 5412 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5413 /* Basic. Used for router interfaces, counting the following: 5414 * - Error and Discard counters. 5415 * - Unicast, Multicast and Broadcast counters. Sharing the 5416 * same set of counters for the different type of traffic 5417 * (IPv4, IPv6 and mpls). 5418 */ 5419 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5420 }; 5421 5422 /* reg_ritr_ingress_counter_index 5423 * Counter Index for flow counter. 5424 * Access: RW 5425 */ 5426 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5427 5428 /* reg_ritr_ingress_counter_set_type 5429 * Igress Counter Set Type for router interface counter. 5430 * Access: RW 5431 */ 5432 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5433 5434 /* reg_ritr_egress_counter_index 5435 * Counter Index for flow counter. 5436 * Access: RW 5437 */ 5438 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5439 5440 /* reg_ritr_egress_counter_set_type 5441 * Egress Counter Set Type for router interface counter. 5442 * Access: RW 5443 */ 5444 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5445 5446 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5447 bool enable, bool egress) 5448 { 5449 enum mlxsw_reg_ritr_counter_set_type set_type; 5450 5451 if (enable) 5452 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5453 else 5454 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5455 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5456 5457 if (egress) 5458 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5459 else 5460 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5461 } 5462 5463 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5464 { 5465 MLXSW_REG_ZERO(ritr, payload); 5466 mlxsw_reg_ritr_rif_set(payload, rif); 5467 } 5468 5469 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5470 u16 system_port, u16 vid) 5471 { 5472 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5473 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5474 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5475 } 5476 5477 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5478 enum mlxsw_reg_ritr_if_type type, 5479 u16 rif, u16 vr_id, u16 mtu) 5480 { 5481 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5482 5483 MLXSW_REG_ZERO(ritr, payload); 5484 mlxsw_reg_ritr_enable_set(payload, enable); 5485 mlxsw_reg_ritr_ipv4_set(payload, 1); 5486 mlxsw_reg_ritr_ipv6_set(payload, 1); 5487 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5488 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5489 mlxsw_reg_ritr_type_set(payload, type); 5490 mlxsw_reg_ritr_op_set(payload, op); 5491 mlxsw_reg_ritr_rif_set(payload, rif); 5492 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5493 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5494 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5495 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5496 mlxsw_reg_ritr_lb_en_set(payload, 1); 5497 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5498 mlxsw_reg_ritr_mtu_set(payload, mtu); 5499 } 5500 5501 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5502 { 5503 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5504 } 5505 5506 static inline void 5507 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5508 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5509 enum mlxsw_reg_ritr_loopback_ipip_options options, 5510 u16 uvr_id, u32 gre_key) 5511 { 5512 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5513 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5514 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5515 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5516 } 5517 5518 static inline void 5519 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5520 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5521 enum mlxsw_reg_ritr_loopback_ipip_options options, 5522 u16 uvr_id, u32 usip, u32 gre_key) 5523 { 5524 mlxsw_reg_ritr_loopback_protocol_set(payload, 5525 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5526 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5527 uvr_id, gre_key); 5528 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5529 } 5530 5531 /* RTAR - Router TCAM Allocation Register 5532 * -------------------------------------- 5533 * This register is used for allocation of regions in the TCAM table. 5534 */ 5535 #define MLXSW_REG_RTAR_ID 0x8004 5536 #define MLXSW_REG_RTAR_LEN 0x20 5537 5538 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5539 5540 enum mlxsw_reg_rtar_op { 5541 MLXSW_REG_RTAR_OP_ALLOCATE, 5542 MLXSW_REG_RTAR_OP_RESIZE, 5543 MLXSW_REG_RTAR_OP_DEALLOCATE, 5544 }; 5545 5546 /* reg_rtar_op 5547 * Access: WO 5548 */ 5549 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5550 5551 enum mlxsw_reg_rtar_key_type { 5552 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5553 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5554 }; 5555 5556 /* reg_rtar_key_type 5557 * TCAM key type for the region. 5558 * Access: WO 5559 */ 5560 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5561 5562 /* reg_rtar_region_size 5563 * TCAM region size. When allocating/resizing this is the requested 5564 * size, the response is the actual size. 5565 * Note: Actual size may be larger than requested. 5566 * Reserved for op = Deallocate 5567 * Access: WO 5568 */ 5569 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5570 5571 static inline void mlxsw_reg_rtar_pack(char *payload, 5572 enum mlxsw_reg_rtar_op op, 5573 enum mlxsw_reg_rtar_key_type key_type, 5574 u16 region_size) 5575 { 5576 MLXSW_REG_ZERO(rtar, payload); 5577 mlxsw_reg_rtar_op_set(payload, op); 5578 mlxsw_reg_rtar_key_type_set(payload, key_type); 5579 mlxsw_reg_rtar_region_size_set(payload, region_size); 5580 } 5581 5582 /* RATR - Router Adjacency Table Register 5583 * -------------------------------------- 5584 * The RATR register is used to configure the Router Adjacency (next-hop) 5585 * Table. 5586 */ 5587 #define MLXSW_REG_RATR_ID 0x8008 5588 #define MLXSW_REG_RATR_LEN 0x2C 5589 5590 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5591 5592 enum mlxsw_reg_ratr_op { 5593 /* Read */ 5594 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5595 /* Read and clear activity */ 5596 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5597 /* Write Adjacency entry */ 5598 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5599 /* Write Adjacency entry only if the activity is cleared. 5600 * The write may not succeed if the activity is set. There is not 5601 * direct feedback if the write has succeeded or not, however 5602 * the get will reveal the actual entry (SW can compare the get 5603 * response to the set command). 5604 */ 5605 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5606 }; 5607 5608 /* reg_ratr_op 5609 * Note that Write operation may also be used for updating 5610 * counter_set_type and counter_index. In this case all other 5611 * fields must not be updated. 5612 * Access: OP 5613 */ 5614 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5615 5616 /* reg_ratr_v 5617 * Valid bit. Indicates if the adjacency entry is valid. 5618 * Note: the device may need some time before reusing an invalidated 5619 * entry. During this time the entry can not be reused. It is 5620 * recommended to use another entry before reusing an invalidated 5621 * entry (e.g. software can put it at the end of the list for 5622 * reusing). Trying to access an invalidated entry not yet cleared 5623 * by the device results with failure indicating "Try Again" status. 5624 * When valid is '0' then egress_router_interface,trap_action, 5625 * adjacency_parameters and counters are reserved 5626 * Access: RW 5627 */ 5628 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5629 5630 /* reg_ratr_a 5631 * Activity. Set for new entries. Set if a packet lookup has hit on 5632 * the specific entry. To clear the a bit, use "clear activity". 5633 * Access: RO 5634 */ 5635 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5636 5637 enum mlxsw_reg_ratr_type { 5638 /* Ethernet */ 5639 MLXSW_REG_RATR_TYPE_ETHERNET, 5640 /* IPoIB Unicast without GRH. 5641 * Reserved for Spectrum. 5642 */ 5643 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5644 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5645 * adjacency). 5646 * Reserved for Spectrum. 5647 */ 5648 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5649 /* IPoIB Multicast. 5650 * Reserved for Spectrum. 5651 */ 5652 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5653 /* MPLS. 5654 * Reserved for SwitchX/-2. 5655 */ 5656 MLXSW_REG_RATR_TYPE_MPLS, 5657 /* IPinIP Encap. 5658 * Reserved for SwitchX/-2. 5659 */ 5660 MLXSW_REG_RATR_TYPE_IPIP, 5661 }; 5662 5663 /* reg_ratr_type 5664 * Adjacency entry type. 5665 * Access: RW 5666 */ 5667 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 5668 5669 /* reg_ratr_adjacency_index_low 5670 * Bits 15:0 of index into the adjacency table. 5671 * For SwitchX and SwitchX-2, the adjacency table is linear and 5672 * used for adjacency entries only. 5673 * For Spectrum, the index is to the KVD linear. 5674 * Access: Index 5675 */ 5676 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 5677 5678 /* reg_ratr_egress_router_interface 5679 * Range is 0 .. cap_max_router_interfaces - 1 5680 * Access: RW 5681 */ 5682 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 5683 5684 enum mlxsw_reg_ratr_trap_action { 5685 MLXSW_REG_RATR_TRAP_ACTION_NOP, 5686 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 5687 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 5688 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 5689 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 5690 }; 5691 5692 /* reg_ratr_trap_action 5693 * see mlxsw_reg_ratr_trap_action 5694 * Access: RW 5695 */ 5696 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 5697 5698 /* reg_ratr_adjacency_index_high 5699 * Bits 23:16 of the adjacency_index. 5700 * Access: Index 5701 */ 5702 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 5703 5704 enum mlxsw_reg_ratr_trap_id { 5705 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 5706 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 5707 }; 5708 5709 /* reg_ratr_trap_id 5710 * Trap ID to be reported to CPU. 5711 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5712 * For trap_action of NOP, MIRROR and DISCARD_ERROR 5713 * Access: RW 5714 */ 5715 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 5716 5717 /* reg_ratr_eth_destination_mac 5718 * MAC address of the destination next-hop. 5719 * Access: RW 5720 */ 5721 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 5722 5723 enum mlxsw_reg_ratr_ipip_type { 5724 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 5725 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 5726 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 5727 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 5728 }; 5729 5730 /* reg_ratr_ipip_type 5731 * Underlay destination ip type. 5732 * Note: the type field must match the protocol of the router interface. 5733 * Access: RW 5734 */ 5735 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 5736 5737 /* reg_ratr_ipip_ipv4_udip 5738 * Underlay ipv4 dip. 5739 * Reserved when ipip_type is IPv6. 5740 * Access: RW 5741 */ 5742 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 5743 5744 /* reg_ratr_ipip_ipv6_ptr 5745 * Pointer to IPv6 underlay destination ip address. 5746 * For Spectrum: Pointer to KVD linear space. 5747 * Access: RW 5748 */ 5749 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 5750 5751 enum mlxsw_reg_flow_counter_set_type { 5752 /* No count */ 5753 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5754 /* Count packets and bytes */ 5755 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 5756 /* Count only packets */ 5757 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 5758 }; 5759 5760 /* reg_ratr_counter_set_type 5761 * Counter set type for flow counters 5762 * Access: RW 5763 */ 5764 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 5765 5766 /* reg_ratr_counter_index 5767 * Counter index for flow counters 5768 * Access: RW 5769 */ 5770 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 5771 5772 static inline void 5773 mlxsw_reg_ratr_pack(char *payload, 5774 enum mlxsw_reg_ratr_op op, bool valid, 5775 enum mlxsw_reg_ratr_type type, 5776 u32 adjacency_index, u16 egress_rif) 5777 { 5778 MLXSW_REG_ZERO(ratr, payload); 5779 mlxsw_reg_ratr_op_set(payload, op); 5780 mlxsw_reg_ratr_v_set(payload, valid); 5781 mlxsw_reg_ratr_type_set(payload, type); 5782 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 5783 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 5784 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 5785 } 5786 5787 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 5788 const char *dest_mac) 5789 { 5790 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 5791 } 5792 5793 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 5794 { 5795 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 5796 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 5797 } 5798 5799 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 5800 bool counter_enable) 5801 { 5802 enum mlxsw_reg_flow_counter_set_type set_type; 5803 5804 if (counter_enable) 5805 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 5806 else 5807 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 5808 5809 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 5810 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 5811 } 5812 5813 /* RDPM - Router DSCP to Priority Mapping 5814 * -------------------------------------- 5815 * Controls the mapping from DSCP field to switch priority on routed packets 5816 */ 5817 #define MLXSW_REG_RDPM_ID 0x8009 5818 #define MLXSW_REG_RDPM_BASE_LEN 0x00 5819 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 5820 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 5821 #define MLXSW_REG_RDPM_LEN 0x40 5822 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 5823 MLXSW_REG_RDPM_LEN - \ 5824 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 5825 5826 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 5827 5828 /* reg_dscp_entry_e 5829 * Enable update of the specific entry 5830 * Access: Index 5831 */ 5832 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 5833 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 5834 5835 /* reg_dscp_entry_prio 5836 * Switch Priority 5837 * Access: RW 5838 */ 5839 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 5840 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 5841 5842 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 5843 u8 prio) 5844 { 5845 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 5846 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 5847 } 5848 5849 /* RICNT - Router Interface Counter Register 5850 * ----------------------------------------- 5851 * The RICNT register retrieves per port performance counters 5852 */ 5853 #define MLXSW_REG_RICNT_ID 0x800B 5854 #define MLXSW_REG_RICNT_LEN 0x100 5855 5856 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 5857 5858 /* reg_ricnt_counter_index 5859 * Counter index 5860 * Access: RW 5861 */ 5862 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 5863 5864 enum mlxsw_reg_ricnt_counter_set_type { 5865 /* No Count. */ 5866 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 5867 /* Basic. Used for router interfaces, counting the following: 5868 * - Error and Discard counters. 5869 * - Unicast, Multicast and Broadcast counters. Sharing the 5870 * same set of counters for the different type of traffic 5871 * (IPv4, IPv6 and mpls). 5872 */ 5873 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 5874 }; 5875 5876 /* reg_ricnt_counter_set_type 5877 * Counter Set Type for router interface counter 5878 * Access: RW 5879 */ 5880 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 5881 5882 enum mlxsw_reg_ricnt_opcode { 5883 /* Nop. Supported only for read access*/ 5884 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 5885 /* Clear. Setting the clr bit will reset the counter value for 5886 * all counters of the specified Router Interface. 5887 */ 5888 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 5889 }; 5890 5891 /* reg_ricnt_opcode 5892 * Opcode 5893 * Access: RW 5894 */ 5895 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 5896 5897 /* reg_ricnt_good_unicast_packets 5898 * good unicast packets. 5899 * Access: RW 5900 */ 5901 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 5902 5903 /* reg_ricnt_good_multicast_packets 5904 * good multicast packets. 5905 * Access: RW 5906 */ 5907 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 5908 5909 /* reg_ricnt_good_broadcast_packets 5910 * good broadcast packets 5911 * Access: RW 5912 */ 5913 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 5914 5915 /* reg_ricnt_good_unicast_bytes 5916 * A count of L3 data and padding octets not including L2 headers 5917 * for good unicast frames. 5918 * Access: RW 5919 */ 5920 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 5921 5922 /* reg_ricnt_good_multicast_bytes 5923 * A count of L3 data and padding octets not including L2 headers 5924 * for good multicast frames. 5925 * Access: RW 5926 */ 5927 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 5928 5929 /* reg_ritr_good_broadcast_bytes 5930 * A count of L3 data and padding octets not including L2 headers 5931 * for good broadcast frames. 5932 * Access: RW 5933 */ 5934 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 5935 5936 /* reg_ricnt_error_packets 5937 * A count of errored frames that do not pass the router checks. 5938 * Access: RW 5939 */ 5940 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 5941 5942 /* reg_ricnt_discrad_packets 5943 * A count of non-errored frames that do not pass the router checks. 5944 * Access: RW 5945 */ 5946 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 5947 5948 /* reg_ricnt_error_bytes 5949 * A count of L3 data and padding octets not including L2 headers 5950 * for errored frames. 5951 * Access: RW 5952 */ 5953 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 5954 5955 /* reg_ricnt_discard_bytes 5956 * A count of L3 data and padding octets not including L2 headers 5957 * for non-errored frames that do not pass the router checks. 5958 * Access: RW 5959 */ 5960 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 5961 5962 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 5963 enum mlxsw_reg_ricnt_opcode op) 5964 { 5965 MLXSW_REG_ZERO(ricnt, payload); 5966 mlxsw_reg_ricnt_op_set(payload, op); 5967 mlxsw_reg_ricnt_counter_index_set(payload, index); 5968 mlxsw_reg_ricnt_counter_set_type_set(payload, 5969 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 5970 } 5971 5972 /* RRCR - Router Rules Copy Register Layout 5973 * ---------------------------------------- 5974 * This register is used for moving and copying route entry rules. 5975 */ 5976 #define MLXSW_REG_RRCR_ID 0x800F 5977 #define MLXSW_REG_RRCR_LEN 0x24 5978 5979 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 5980 5981 enum mlxsw_reg_rrcr_op { 5982 /* Move rules */ 5983 MLXSW_REG_RRCR_OP_MOVE, 5984 /* Copy rules */ 5985 MLXSW_REG_RRCR_OP_COPY, 5986 }; 5987 5988 /* reg_rrcr_op 5989 * Access: WO 5990 */ 5991 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 5992 5993 /* reg_rrcr_offset 5994 * Offset within the region from which to copy/move. 5995 * Access: Index 5996 */ 5997 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 5998 5999 /* reg_rrcr_size 6000 * The number of rules to copy/move. 6001 * Access: WO 6002 */ 6003 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6004 6005 /* reg_rrcr_table_id 6006 * Identifier of the table on which to perform the operation. Encoding is the 6007 * same as in RTAR.key_type 6008 * Access: Index 6009 */ 6010 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6011 6012 /* reg_rrcr_dest_offset 6013 * Offset within the region to which to copy/move 6014 * Access: Index 6015 */ 6016 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6017 6018 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6019 u16 offset, u16 size, 6020 enum mlxsw_reg_rtar_key_type table_id, 6021 u16 dest_offset) 6022 { 6023 MLXSW_REG_ZERO(rrcr, payload); 6024 mlxsw_reg_rrcr_op_set(payload, op); 6025 mlxsw_reg_rrcr_offset_set(payload, offset); 6026 mlxsw_reg_rrcr_size_set(payload, size); 6027 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6028 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6029 } 6030 6031 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6032 * ------------------------------------------------------- 6033 * RALTA is used to allocate the LPM trees of the SHSPM method. 6034 */ 6035 #define MLXSW_REG_RALTA_ID 0x8010 6036 #define MLXSW_REG_RALTA_LEN 0x04 6037 6038 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6039 6040 /* reg_ralta_op 6041 * opcode (valid for Write, must be 0 on Read) 6042 * 0 - allocate a tree 6043 * 1 - deallocate a tree 6044 * Access: OP 6045 */ 6046 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6047 6048 enum mlxsw_reg_ralxx_protocol { 6049 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6050 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6051 }; 6052 6053 /* reg_ralta_protocol 6054 * Protocol. 6055 * Deallocation opcode: Reserved. 6056 * Access: RW 6057 */ 6058 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6059 6060 /* reg_ralta_tree_id 6061 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6062 * the tree identifier (managed by software). 6063 * Note that tree_id 0 is allocated for a default-route tree. 6064 * Access: Index 6065 */ 6066 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6067 6068 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6069 enum mlxsw_reg_ralxx_protocol protocol, 6070 u8 tree_id) 6071 { 6072 MLXSW_REG_ZERO(ralta, payload); 6073 mlxsw_reg_ralta_op_set(payload, !alloc); 6074 mlxsw_reg_ralta_protocol_set(payload, protocol); 6075 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6076 } 6077 6078 /* RALST - Router Algorithmic LPM Structure Tree Register 6079 * ------------------------------------------------------ 6080 * RALST is used to set and query the structure of an LPM tree. 6081 * The structure of the tree must be sorted as a sorted binary tree, while 6082 * each node is a bin that is tagged as the length of the prefixes the lookup 6083 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6084 * of X bits to match with the destination address. The bin 0 indicates 6085 * the default action, when there is no match of any prefix. 6086 */ 6087 #define MLXSW_REG_RALST_ID 0x8011 6088 #define MLXSW_REG_RALST_LEN 0x104 6089 6090 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6091 6092 /* reg_ralst_root_bin 6093 * The bin number of the root bin. 6094 * 0<root_bin=<(length of IP address) 6095 * For a default-route tree configure 0xff 6096 * Access: RW 6097 */ 6098 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6099 6100 /* reg_ralst_tree_id 6101 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6102 * Access: Index 6103 */ 6104 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6105 6106 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6107 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6108 #define MLXSW_REG_RALST_BIN_COUNT 128 6109 6110 /* reg_ralst_left_child_bin 6111 * Holding the children of the bin according to the stored tree's structure. 6112 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6113 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6114 * Access: RW 6115 */ 6116 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6117 6118 /* reg_ralst_right_child_bin 6119 * Holding the children of the bin according to the stored tree's structure. 6120 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6121 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6122 * Access: RW 6123 */ 6124 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6125 false); 6126 6127 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6128 { 6129 MLXSW_REG_ZERO(ralst, payload); 6130 6131 /* Initialize all bins to have no left or right child */ 6132 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6133 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6134 6135 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6136 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6137 } 6138 6139 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6140 u8 left_child_bin, 6141 u8 right_child_bin) 6142 { 6143 int bin_index = bin_number - 1; 6144 6145 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6146 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6147 right_child_bin); 6148 } 6149 6150 /* RALTB - Router Algorithmic LPM Tree Binding Register 6151 * ---------------------------------------------------- 6152 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6153 */ 6154 #define MLXSW_REG_RALTB_ID 0x8012 6155 #define MLXSW_REG_RALTB_LEN 0x04 6156 6157 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6158 6159 /* reg_raltb_virtual_router 6160 * Virtual Router ID 6161 * Range is 0..cap_max_virtual_routers-1 6162 * Access: Index 6163 */ 6164 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6165 6166 /* reg_raltb_protocol 6167 * Protocol. 6168 * Access: Index 6169 */ 6170 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6171 6172 /* reg_raltb_tree_id 6173 * Tree to be used for the {virtual_router, protocol} 6174 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6175 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6176 * Access: RW 6177 */ 6178 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6179 6180 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6181 enum mlxsw_reg_ralxx_protocol protocol, 6182 u8 tree_id) 6183 { 6184 MLXSW_REG_ZERO(raltb, payload); 6185 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6186 mlxsw_reg_raltb_protocol_set(payload, protocol); 6187 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6188 } 6189 6190 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6191 * ----------------------------------------------------- 6192 * RALUE is used to configure and query LPM entries that serve 6193 * the Unicast protocols. 6194 */ 6195 #define MLXSW_REG_RALUE_ID 0x8013 6196 #define MLXSW_REG_RALUE_LEN 0x38 6197 6198 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6199 6200 /* reg_ralue_protocol 6201 * Protocol. 6202 * Access: Index 6203 */ 6204 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6205 6206 enum mlxsw_reg_ralue_op { 6207 /* Read operation. If entry doesn't exist, the operation fails. */ 6208 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6209 /* Clear on read operation. Used to read entry and 6210 * clear Activity bit. 6211 */ 6212 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6213 /* Write operation. Used to write a new entry to the table. All RW 6214 * fields are written for new entry. Activity bit is set 6215 * for new entries. 6216 */ 6217 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6218 /* Update operation. Used to update an existing route entry and 6219 * only update the RW fields that are detailed in the field 6220 * op_u_mask. If entry doesn't exist, the operation fails. 6221 */ 6222 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6223 /* Clear activity. The Activity bit (the field a) is cleared 6224 * for the entry. 6225 */ 6226 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6227 /* Delete operation. Used to delete an existing entry. If entry 6228 * doesn't exist, the operation fails. 6229 */ 6230 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6231 }; 6232 6233 /* reg_ralue_op 6234 * Operation. 6235 * Access: OP 6236 */ 6237 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6238 6239 /* reg_ralue_a 6240 * Activity. Set for new entries. Set if a packet lookup has hit on the 6241 * specific entry, only if the entry is a route. To clear the a bit, use 6242 * "clear activity" op. 6243 * Enabled by activity_dis in RGCR 6244 * Access: RO 6245 */ 6246 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6247 6248 /* reg_ralue_virtual_router 6249 * Virtual Router ID 6250 * Range is 0..cap_max_virtual_routers-1 6251 * Access: Index 6252 */ 6253 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6254 6255 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6256 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6257 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6258 6259 /* reg_ralue_op_u_mask 6260 * opcode update mask. 6261 * On read operation, this field is reserved. 6262 * This field is valid for update opcode, otherwise - reserved. 6263 * This field is a bitmask of the fields that should be updated. 6264 * Access: WO 6265 */ 6266 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6267 6268 /* reg_ralue_prefix_len 6269 * Number of bits in the prefix of the LPM route. 6270 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6271 * two entries in the physical HW table. 6272 * Access: Index 6273 */ 6274 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6275 6276 /* reg_ralue_dip* 6277 * The prefix of the route or of the marker that the object of the LPM 6278 * is compared with. The most significant bits of the dip are the prefix. 6279 * The least significant bits must be '0' if the prefix_len is smaller 6280 * than 128 for IPv6 or smaller than 32 for IPv4. 6281 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6282 * Access: Index 6283 */ 6284 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6285 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6286 6287 enum mlxsw_reg_ralue_entry_type { 6288 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6289 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6290 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6291 }; 6292 6293 /* reg_ralue_entry_type 6294 * Entry type. 6295 * Note - for Marker entries, the action_type and action fields are reserved. 6296 * Access: RW 6297 */ 6298 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6299 6300 /* reg_ralue_bmp_len 6301 * The best match prefix length in the case that there is no match for 6302 * longer prefixes. 6303 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6304 * Note for any update operation with entry_type modification this 6305 * field must be set. 6306 * Access: RW 6307 */ 6308 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6309 6310 enum mlxsw_reg_ralue_action_type { 6311 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6312 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6313 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6314 }; 6315 6316 /* reg_ralue_action_type 6317 * Action Type 6318 * Indicates how the IP address is connected. 6319 * It can be connected to a local subnet through local_erif or can be 6320 * on a remote subnet connected through a next-hop router, 6321 * or transmitted to the CPU. 6322 * Reserved when entry_type = MARKER_ENTRY 6323 * Access: RW 6324 */ 6325 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6326 6327 enum mlxsw_reg_ralue_trap_action { 6328 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6329 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6330 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6331 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6332 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6333 }; 6334 6335 /* reg_ralue_trap_action 6336 * Trap action. 6337 * For IP2ME action, only NOP and MIRROR are possible. 6338 * Access: RW 6339 */ 6340 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6341 6342 /* reg_ralue_trap_id 6343 * Trap ID to be reported to CPU. 6344 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6345 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6346 * Access: RW 6347 */ 6348 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6349 6350 /* reg_ralue_adjacency_index 6351 * Points to the first entry of the group-based ECMP. 6352 * Only relevant in case of REMOTE action. 6353 * Access: RW 6354 */ 6355 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6356 6357 /* reg_ralue_ecmp_size 6358 * Amount of sequential entries starting 6359 * from the adjacency_index (the number of ECMPs). 6360 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6361 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6362 * Only relevant in case of REMOTE action. 6363 * Access: RW 6364 */ 6365 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6366 6367 /* reg_ralue_local_erif 6368 * Egress Router Interface. 6369 * Only relevant in case of LOCAL action. 6370 * Access: RW 6371 */ 6372 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6373 6374 /* reg_ralue_ip2me_v 6375 * Valid bit for the tunnel_ptr field. 6376 * If valid = 0 then trap to CPU as IP2ME trap ID. 6377 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6378 * decapsulation then tunnel decapsulation is done. 6379 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6380 * decapsulation then trap as IP2ME trap ID. 6381 * Only relevant in case of IP2ME action. 6382 * Access: RW 6383 */ 6384 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6385 6386 /* reg_ralue_ip2me_tunnel_ptr 6387 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6388 * For Spectrum, pointer to KVD Linear. 6389 * Only relevant in case of IP2ME action. 6390 * Access: RW 6391 */ 6392 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6393 6394 static inline void mlxsw_reg_ralue_pack(char *payload, 6395 enum mlxsw_reg_ralxx_protocol protocol, 6396 enum mlxsw_reg_ralue_op op, 6397 u16 virtual_router, u8 prefix_len) 6398 { 6399 MLXSW_REG_ZERO(ralue, payload); 6400 mlxsw_reg_ralue_protocol_set(payload, protocol); 6401 mlxsw_reg_ralue_op_set(payload, op); 6402 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6403 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6404 mlxsw_reg_ralue_entry_type_set(payload, 6405 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6406 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6407 } 6408 6409 static inline void mlxsw_reg_ralue_pack4(char *payload, 6410 enum mlxsw_reg_ralxx_protocol protocol, 6411 enum mlxsw_reg_ralue_op op, 6412 u16 virtual_router, u8 prefix_len, 6413 u32 dip) 6414 { 6415 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6416 mlxsw_reg_ralue_dip4_set(payload, dip); 6417 } 6418 6419 static inline void mlxsw_reg_ralue_pack6(char *payload, 6420 enum mlxsw_reg_ralxx_protocol protocol, 6421 enum mlxsw_reg_ralue_op op, 6422 u16 virtual_router, u8 prefix_len, 6423 const void *dip) 6424 { 6425 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6426 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6427 } 6428 6429 static inline void 6430 mlxsw_reg_ralue_act_remote_pack(char *payload, 6431 enum mlxsw_reg_ralue_trap_action trap_action, 6432 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6433 { 6434 mlxsw_reg_ralue_action_type_set(payload, 6435 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6436 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6437 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6438 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6439 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6440 } 6441 6442 static inline void 6443 mlxsw_reg_ralue_act_local_pack(char *payload, 6444 enum mlxsw_reg_ralue_trap_action trap_action, 6445 u16 trap_id, u16 local_erif) 6446 { 6447 mlxsw_reg_ralue_action_type_set(payload, 6448 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6449 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6450 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6451 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6452 } 6453 6454 static inline void 6455 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6456 { 6457 mlxsw_reg_ralue_action_type_set(payload, 6458 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6459 } 6460 6461 static inline void 6462 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6463 { 6464 mlxsw_reg_ralue_action_type_set(payload, 6465 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6466 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6467 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6468 } 6469 6470 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6471 * ---------------------------------------------------------- 6472 * The RAUHT register is used to configure and query the Unicast Host table in 6473 * devices that implement the Algorithmic LPM. 6474 */ 6475 #define MLXSW_REG_RAUHT_ID 0x8014 6476 #define MLXSW_REG_RAUHT_LEN 0x74 6477 6478 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6479 6480 enum mlxsw_reg_rauht_type { 6481 MLXSW_REG_RAUHT_TYPE_IPV4, 6482 MLXSW_REG_RAUHT_TYPE_IPV6, 6483 }; 6484 6485 /* reg_rauht_type 6486 * Access: Index 6487 */ 6488 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6489 6490 enum mlxsw_reg_rauht_op { 6491 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6492 /* Read operation */ 6493 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6494 /* Clear on read operation. Used to read entry and clear 6495 * activity bit. 6496 */ 6497 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6498 /* Add. Used to write a new entry to the table. All R/W fields are 6499 * relevant for new entry. Activity bit is set for new entries. 6500 */ 6501 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6502 /* Update action. Used to update an existing route entry and 6503 * only update the following fields: 6504 * trap_action, trap_id, mac, counter_set_type, counter_index 6505 */ 6506 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6507 /* Clear activity. A bit is cleared for the entry. */ 6508 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6509 /* Delete entry */ 6510 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6511 /* Delete all host entries on a RIF. In this command, dip 6512 * field is reserved. 6513 */ 6514 }; 6515 6516 /* reg_rauht_op 6517 * Access: OP 6518 */ 6519 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6520 6521 /* reg_rauht_a 6522 * Activity. Set for new entries. Set if a packet lookup has hit on 6523 * the specific entry. 6524 * To clear the a bit, use "clear activity" op. 6525 * Enabled by activity_dis in RGCR 6526 * Access: RO 6527 */ 6528 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6529 6530 /* reg_rauht_rif 6531 * Router Interface 6532 * Access: Index 6533 */ 6534 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6535 6536 /* reg_rauht_dip* 6537 * Destination address. 6538 * Access: Index 6539 */ 6540 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6541 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6542 6543 enum mlxsw_reg_rauht_trap_action { 6544 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6545 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6546 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6547 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6548 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6549 }; 6550 6551 /* reg_rauht_trap_action 6552 * Access: RW 6553 */ 6554 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6555 6556 enum mlxsw_reg_rauht_trap_id { 6557 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6558 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6559 }; 6560 6561 /* reg_rauht_trap_id 6562 * Trap ID to be reported to CPU. 6563 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6564 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6565 * trap_id is reserved. 6566 * Access: RW 6567 */ 6568 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6569 6570 /* reg_rauht_counter_set_type 6571 * Counter set type for flow counters 6572 * Access: RW 6573 */ 6574 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6575 6576 /* reg_rauht_counter_index 6577 * Counter index for flow counters 6578 * Access: RW 6579 */ 6580 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6581 6582 /* reg_rauht_mac 6583 * MAC address. 6584 * Access: RW 6585 */ 6586 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6587 6588 static inline void mlxsw_reg_rauht_pack(char *payload, 6589 enum mlxsw_reg_rauht_op op, u16 rif, 6590 const char *mac) 6591 { 6592 MLXSW_REG_ZERO(rauht, payload); 6593 mlxsw_reg_rauht_op_set(payload, op); 6594 mlxsw_reg_rauht_rif_set(payload, rif); 6595 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6596 } 6597 6598 static inline void mlxsw_reg_rauht_pack4(char *payload, 6599 enum mlxsw_reg_rauht_op op, u16 rif, 6600 const char *mac, u32 dip) 6601 { 6602 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6603 mlxsw_reg_rauht_dip4_set(payload, dip); 6604 } 6605 6606 static inline void mlxsw_reg_rauht_pack6(char *payload, 6607 enum mlxsw_reg_rauht_op op, u16 rif, 6608 const char *mac, const char *dip) 6609 { 6610 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6611 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6612 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6613 } 6614 6615 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6616 u64 counter_index) 6617 { 6618 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6619 mlxsw_reg_rauht_counter_set_type_set(payload, 6620 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6621 } 6622 6623 /* RALEU - Router Algorithmic LPM ECMP Update Register 6624 * --------------------------------------------------- 6625 * The register enables updating the ECMP section in the action for multiple 6626 * LPM Unicast entries in a single operation. The update is executed to 6627 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6628 */ 6629 #define MLXSW_REG_RALEU_ID 0x8015 6630 #define MLXSW_REG_RALEU_LEN 0x28 6631 6632 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6633 6634 /* reg_raleu_protocol 6635 * Protocol. 6636 * Access: Index 6637 */ 6638 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6639 6640 /* reg_raleu_virtual_router 6641 * Virtual Router ID 6642 * Range is 0..cap_max_virtual_routers-1 6643 * Access: Index 6644 */ 6645 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6646 6647 /* reg_raleu_adjacency_index 6648 * Adjacency Index used for matching on the existing entries. 6649 * Access: Index 6650 */ 6651 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6652 6653 /* reg_raleu_ecmp_size 6654 * ECMP Size used for matching on the existing entries. 6655 * Access: Index 6656 */ 6657 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6658 6659 /* reg_raleu_new_adjacency_index 6660 * New Adjacency Index. 6661 * Access: WO 6662 */ 6663 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6664 6665 /* reg_raleu_new_ecmp_size 6666 * New ECMP Size. 6667 * Access: WO 6668 */ 6669 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 6670 6671 static inline void mlxsw_reg_raleu_pack(char *payload, 6672 enum mlxsw_reg_ralxx_protocol protocol, 6673 u16 virtual_router, 6674 u32 adjacency_index, u16 ecmp_size, 6675 u32 new_adjacency_index, 6676 u16 new_ecmp_size) 6677 { 6678 MLXSW_REG_ZERO(raleu, payload); 6679 mlxsw_reg_raleu_protocol_set(payload, protocol); 6680 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 6681 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 6682 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 6683 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 6684 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 6685 } 6686 6687 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 6688 * ---------------------------------------------------------------- 6689 * The RAUHTD register allows dumping entries from the Router Unicast Host 6690 * Table. For a given session an entry is dumped no more than one time. The 6691 * first RAUHTD access after reset is a new session. A session ends when the 6692 * num_rec response is smaller than num_rec request or for IPv4 when the 6693 * num_entries is smaller than 4. The clear activity affect the current session 6694 * or the last session if a new session has not started. 6695 */ 6696 #define MLXSW_REG_RAUHTD_ID 0x8018 6697 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 6698 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 6699 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 6700 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 6701 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 6702 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 6703 6704 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 6705 6706 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 6707 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 6708 6709 /* reg_rauhtd_filter_fields 6710 * if a bit is '0' then the relevant field is ignored and dump is done 6711 * regardless of the field value 6712 * Bit0 - filter by activity: entry_a 6713 * Bit3 - filter by entry rip: entry_rif 6714 * Access: Index 6715 */ 6716 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 6717 6718 enum mlxsw_reg_rauhtd_op { 6719 MLXSW_REG_RAUHTD_OP_DUMP, 6720 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 6721 }; 6722 6723 /* reg_rauhtd_op 6724 * Access: OP 6725 */ 6726 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 6727 6728 /* reg_rauhtd_num_rec 6729 * At request: number of records requested 6730 * At response: number of records dumped 6731 * For IPv4, each record has 4 entries at request and up to 4 entries 6732 * at response 6733 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 6734 * Access: Index 6735 */ 6736 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 6737 6738 /* reg_rauhtd_entry_a 6739 * Dump only if activity has value of entry_a 6740 * Reserved if filter_fields bit0 is '0' 6741 * Access: Index 6742 */ 6743 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 6744 6745 enum mlxsw_reg_rauhtd_type { 6746 MLXSW_REG_RAUHTD_TYPE_IPV4, 6747 MLXSW_REG_RAUHTD_TYPE_IPV6, 6748 }; 6749 6750 /* reg_rauhtd_type 6751 * Dump only if record type is: 6752 * 0 - IPv4 6753 * 1 - IPv6 6754 * Access: Index 6755 */ 6756 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 6757 6758 /* reg_rauhtd_entry_rif 6759 * Dump only if RIF has value of entry_rif 6760 * Reserved if filter_fields bit3 is '0' 6761 * Access: Index 6762 */ 6763 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 6764 6765 static inline void mlxsw_reg_rauhtd_pack(char *payload, 6766 enum mlxsw_reg_rauhtd_type type) 6767 { 6768 MLXSW_REG_ZERO(rauhtd, payload); 6769 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 6770 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 6771 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 6772 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 6773 mlxsw_reg_rauhtd_type_set(payload, type); 6774 } 6775 6776 /* reg_rauhtd_ipv4_rec_num_entries 6777 * Number of valid entries in this record: 6778 * 0 - 1 valid entry 6779 * 1 - 2 valid entries 6780 * 2 - 3 valid entries 6781 * 3 - 4 valid entries 6782 * Access: RO 6783 */ 6784 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 6785 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 6786 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6787 6788 /* reg_rauhtd_rec_type 6789 * Record type. 6790 * 0 - IPv4 6791 * 1 - IPv6 6792 * Access: RO 6793 */ 6794 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 6795 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 6796 6797 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 6798 6799 /* reg_rauhtd_ipv4_ent_a 6800 * Activity. Set for new entries. Set if a packet lookup has hit on the 6801 * specific entry. 6802 * Access: RO 6803 */ 6804 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 6805 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 6806 6807 /* reg_rauhtd_ipv4_ent_rif 6808 * Router interface. 6809 * Access: RO 6810 */ 6811 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6812 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 6813 6814 /* reg_rauhtd_ipv4_ent_dip 6815 * Destination IPv4 address. 6816 * Access: RO 6817 */ 6818 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6819 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 6820 6821 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 6822 6823 /* reg_rauhtd_ipv6_ent_a 6824 * Activity. Set for new entries. Set if a packet lookup has hit on the 6825 * specific entry. 6826 * Access: RO 6827 */ 6828 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 6829 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 6830 6831 /* reg_rauhtd_ipv6_ent_rif 6832 * Router interface. 6833 * Access: RO 6834 */ 6835 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 6836 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 6837 6838 /* reg_rauhtd_ipv6_ent_dip 6839 * Destination IPv6 address. 6840 * Access: RO 6841 */ 6842 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 6843 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 6844 6845 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 6846 int ent_index, u16 *p_rif, 6847 u32 *p_dip) 6848 { 6849 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 6850 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 6851 } 6852 6853 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 6854 int rec_index, u16 *p_rif, 6855 char *p_dip) 6856 { 6857 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 6858 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 6859 } 6860 6861 /* RTDP - Routing Tunnel Decap Properties Register 6862 * ----------------------------------------------- 6863 * The RTDP register is used for configuring the tunnel decap properties of NVE 6864 * and IPinIP. 6865 */ 6866 #define MLXSW_REG_RTDP_ID 0x8020 6867 #define MLXSW_REG_RTDP_LEN 0x44 6868 6869 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 6870 6871 enum mlxsw_reg_rtdp_type { 6872 MLXSW_REG_RTDP_TYPE_NVE, 6873 MLXSW_REG_RTDP_TYPE_IPIP, 6874 }; 6875 6876 /* reg_rtdp_type 6877 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 6878 * Access: RW 6879 */ 6880 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 6881 6882 /* reg_rtdp_tunnel_index 6883 * Index to the Decap entry. 6884 * For Spectrum, Index to KVD Linear. 6885 * Access: Index 6886 */ 6887 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 6888 6889 /* IPinIP */ 6890 6891 /* reg_rtdp_ipip_irif 6892 * Ingress Router Interface for the overlay router 6893 * Access: RW 6894 */ 6895 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 6896 6897 enum mlxsw_reg_rtdp_ipip_sip_check { 6898 /* No sip checks. */ 6899 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 6900 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 6901 * equal ipv4_usip. 6902 */ 6903 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 6904 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 6905 * equal ipv6_usip. 6906 */ 6907 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 6908 }; 6909 6910 /* reg_rtdp_ipip_sip_check 6911 * SIP check to perform. If decapsulation failed due to these configurations 6912 * then trap_id is IPIP_DECAP_ERROR. 6913 * Access: RW 6914 */ 6915 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 6916 6917 /* If set, allow decapsulation of IPinIP (without GRE). */ 6918 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 6919 /* If set, allow decapsulation of IPinGREinIP without a key. */ 6920 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 6921 /* If set, allow decapsulation of IPinGREinIP with a key. */ 6922 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 6923 6924 /* reg_rtdp_ipip_type_check 6925 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 6926 * these configurations then trap_id is IPIP_DECAP_ERROR. 6927 * Access: RW 6928 */ 6929 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 6930 6931 /* reg_rtdp_ipip_gre_key_check 6932 * Whether GRE key should be checked. When check is enabled: 6933 * - A packet received as IPinIP (without GRE) will always pass. 6934 * - A packet received as IPinGREinIP without a key will not pass the check. 6935 * - A packet received as IPinGREinIP with a key will pass the check only if the 6936 * key in the packet is equal to expected_gre_key. 6937 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 6938 * Access: RW 6939 */ 6940 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 6941 6942 /* reg_rtdp_ipip_ipv4_usip 6943 * Underlay IPv4 address for ipv4 source address check. 6944 * Reserved when sip_check is not '1'. 6945 * Access: RW 6946 */ 6947 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 6948 6949 /* reg_rtdp_ipip_ipv6_usip_ptr 6950 * This field is valid when sip_check is "sipv6 check explicitly". This is a 6951 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 6952 * is to the KVD linear. 6953 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 6954 * Access: RW 6955 */ 6956 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 6957 6958 /* reg_rtdp_ipip_expected_gre_key 6959 * GRE key for checking. 6960 * Reserved when gre_key_check is '0'. 6961 * Access: RW 6962 */ 6963 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 6964 6965 static inline void mlxsw_reg_rtdp_pack(char *payload, 6966 enum mlxsw_reg_rtdp_type type, 6967 u32 tunnel_index) 6968 { 6969 MLXSW_REG_ZERO(rtdp, payload); 6970 mlxsw_reg_rtdp_type_set(payload, type); 6971 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 6972 } 6973 6974 static inline void 6975 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 6976 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 6977 unsigned int type_check, bool gre_key_check, 6978 u32 ipv4_usip, u32 expected_gre_key) 6979 { 6980 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 6981 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 6982 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 6983 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 6984 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 6985 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 6986 } 6987 6988 /* RIGR-V2 - Router Interface Group Register Version 2 6989 * --------------------------------------------------- 6990 * The RIGR_V2 register is used to add, remove and query egress interface list 6991 * of a multicast forwarding entry. 6992 */ 6993 #define MLXSW_REG_RIGR2_ID 0x8023 6994 #define MLXSW_REG_RIGR2_LEN 0xB0 6995 6996 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 6997 6998 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 6999 7000 /* reg_rigr2_rigr_index 7001 * KVD Linear index. 7002 * Access: Index 7003 */ 7004 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7005 7006 /* reg_rigr2_vnext 7007 * Next RIGR Index is valid. 7008 * Access: RW 7009 */ 7010 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7011 7012 /* reg_rigr2_next_rigr_index 7013 * Next RIGR Index. The index is to the KVD linear. 7014 * Reserved when vnxet = '0'. 7015 * Access: RW 7016 */ 7017 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7018 7019 /* reg_rigr2_vrmid 7020 * RMID Index is valid. 7021 * Access: RW 7022 */ 7023 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7024 7025 /* reg_rigr2_rmid_index 7026 * RMID Index. 7027 * Range 0 .. max_mid - 1 7028 * Reserved when vrmid = '0'. 7029 * The index is to the Port Group Table (PGT) 7030 * Access: RW 7031 */ 7032 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7033 7034 /* reg_rigr2_erif_entry_v 7035 * Egress Router Interface is valid. 7036 * Note that low-entries must be set if high-entries are set. For 7037 * example: if erif_entry[2].v is set then erif_entry[1].v and 7038 * erif_entry[0].v must be set. 7039 * Index can be from 0 to cap_mc_erif_list_entries-1 7040 * Access: RW 7041 */ 7042 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7043 7044 /* reg_rigr2_erif_entry_erif 7045 * Egress Router Interface. 7046 * Valid range is from 0 to cap_max_router_interfaces - 1 7047 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7048 * Access: RW 7049 */ 7050 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7051 7052 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7053 bool vnext, u32 next_rigr_index) 7054 { 7055 MLXSW_REG_ZERO(rigr2, payload); 7056 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7057 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7058 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7059 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7060 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7061 } 7062 7063 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7064 bool v, u16 erif) 7065 { 7066 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7067 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7068 } 7069 7070 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7071 * ------------------------------------------------------ 7072 */ 7073 #define MLXSW_REG_RECR2_ID 0x8025 7074 #define MLXSW_REG_RECR2_LEN 0x38 7075 7076 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7077 7078 /* reg_recr2_pp 7079 * Per-port configuration 7080 * Access: Index 7081 */ 7082 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7083 7084 /* reg_recr2_sh 7085 * Symmetric hash 7086 * Access: RW 7087 */ 7088 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7089 7090 /* reg_recr2_seed 7091 * Seed 7092 * Access: RW 7093 */ 7094 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7095 7096 enum { 7097 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7098 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7099 /* Enable IPv4 fields if packet is TCP or UDP */ 7100 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7101 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7102 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7103 /* Enable IPv6 fields if packet is TCP or UDP */ 7104 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7105 /* Enable TCP/UDP header fields if packet is IPv4 */ 7106 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7107 /* Enable TCP/UDP header fields if packet is IPv6 */ 7108 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7109 }; 7110 7111 /* reg_recr2_outer_header_enables 7112 * Bit mask where each bit enables a specific layer to be included in 7113 * the hash calculation. 7114 * Access: RW 7115 */ 7116 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7117 7118 enum { 7119 /* IPv4 Source IP */ 7120 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7121 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7122 /* IPv4 Destination IP */ 7123 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7124 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7125 /* IP Protocol */ 7126 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7127 /* IPv6 Source IP */ 7128 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7129 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7130 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7131 /* IPv6 Destination IP */ 7132 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7133 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7134 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7135 /* IPv6 Next Header */ 7136 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7137 /* IPv6 Flow Label */ 7138 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7139 /* TCP/UDP Source Port */ 7140 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7141 /* TCP/UDP Destination Port */ 7142 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7143 }; 7144 7145 /* reg_recr2_outer_header_fields_enable 7146 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7147 * Access: RW 7148 */ 7149 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7150 7151 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7152 { 7153 int i; 7154 7155 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7156 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7157 true); 7158 } 7159 7160 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7161 { 7162 int i; 7163 7164 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7165 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7166 true); 7167 } 7168 7169 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7170 { 7171 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7172 7173 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7174 7175 i = MLXSW_REG_RECR2_IPV6_SIP8; 7176 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7177 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7178 true); 7179 } 7180 7181 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7182 { 7183 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7184 7185 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7186 7187 i = MLXSW_REG_RECR2_IPV6_DIP8; 7188 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7189 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7190 true); 7191 } 7192 7193 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7194 { 7195 MLXSW_REG_ZERO(recr2, payload); 7196 mlxsw_reg_recr2_pp_set(payload, false); 7197 mlxsw_reg_recr2_sh_set(payload, true); 7198 mlxsw_reg_recr2_seed_set(payload, seed); 7199 } 7200 7201 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7202 * -------------------------------------------------------------- 7203 * The RMFT_V2 register is used to configure and query the multicast table. 7204 */ 7205 #define MLXSW_REG_RMFT2_ID 0x8027 7206 #define MLXSW_REG_RMFT2_LEN 0x174 7207 7208 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7209 7210 /* reg_rmft2_v 7211 * Valid 7212 * Access: RW 7213 */ 7214 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7215 7216 enum mlxsw_reg_rmft2_type { 7217 MLXSW_REG_RMFT2_TYPE_IPV4, 7218 MLXSW_REG_RMFT2_TYPE_IPV6 7219 }; 7220 7221 /* reg_rmft2_type 7222 * Access: Index 7223 */ 7224 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7225 7226 enum mlxsw_sp_reg_rmft2_op { 7227 /* For Write: 7228 * Write operation. Used to write a new entry to the table. All RW 7229 * fields are relevant for new entry. Activity bit is set for new 7230 * entries - Note write with v (Valid) 0 will delete the entry. 7231 * For Query: 7232 * Read operation 7233 */ 7234 MLXSW_REG_RMFT2_OP_READ_WRITE, 7235 }; 7236 7237 /* reg_rmft2_op 7238 * Operation. 7239 * Access: OP 7240 */ 7241 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7242 7243 /* reg_rmft2_a 7244 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7245 * entry. 7246 * Access: RO 7247 */ 7248 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7249 7250 /* reg_rmft2_offset 7251 * Offset within the multicast forwarding table to write to. 7252 * Access: Index 7253 */ 7254 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7255 7256 /* reg_rmft2_virtual_router 7257 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7258 * Access: RW 7259 */ 7260 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7261 7262 enum mlxsw_reg_rmft2_irif_mask { 7263 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7264 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7265 }; 7266 7267 /* reg_rmft2_irif_mask 7268 * Ingress RIF mask. 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7272 7273 /* reg_rmft2_irif 7274 * Ingress RIF index. 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7278 7279 /* reg_rmft2_dip{4,6} 7280 * Destination IPv4/6 address 7281 * Access: RW 7282 */ 7283 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7284 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7285 7286 /* reg_rmft2_dip{4,6}_mask 7287 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7288 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7289 * Access: RW 7290 */ 7291 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7292 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7293 7294 /* reg_rmft2_sip{4,6} 7295 * Source IPv4/6 address 7296 * Access: RW 7297 */ 7298 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7299 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7300 7301 /* reg_rmft2_sip{4,6}_mask 7302 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7303 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7304 * Access: RW 7305 */ 7306 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7307 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7308 7309 /* reg_rmft2_flexible_action_set 7310 * ACL action set. The only supported action types in this field and in any 7311 * action-set pointed from here are as follows: 7312 * 00h: ACTION_NULL 7313 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7314 * 03h: ACTION_TRAP 7315 * 06h: ACTION_QOS 7316 * 08h: ACTION_POLICING_MONITORING 7317 * 10h: ACTION_ROUTER_MC 7318 * Access: RW 7319 */ 7320 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7321 MLXSW_REG_FLEX_ACTION_SET_LEN); 7322 7323 static inline void 7324 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7325 u16 virtual_router, 7326 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7327 const char *flex_action_set) 7328 { 7329 MLXSW_REG_ZERO(rmft2, payload); 7330 mlxsw_reg_rmft2_v_set(payload, v); 7331 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7332 mlxsw_reg_rmft2_offset_set(payload, offset); 7333 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7334 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7335 mlxsw_reg_rmft2_irif_set(payload, irif); 7336 if (flex_action_set) 7337 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7338 flex_action_set); 7339 } 7340 7341 static inline void 7342 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7343 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7344 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7345 const char *flexible_action_set) 7346 { 7347 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7348 irif_mask, irif, flexible_action_set); 7349 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7350 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7351 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7352 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7353 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7354 } 7355 7356 static inline void 7357 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7358 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7359 struct in6_addr dip6, struct in6_addr dip6_mask, 7360 struct in6_addr sip6, struct in6_addr sip6_mask, 7361 const char *flexible_action_set) 7362 { 7363 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7364 irif_mask, irif, flexible_action_set); 7365 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7366 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7367 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7368 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7369 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7370 } 7371 7372 /* MFCR - Management Fan Control Register 7373 * -------------------------------------- 7374 * This register controls the settings of the Fan Speed PWM mechanism. 7375 */ 7376 #define MLXSW_REG_MFCR_ID 0x9001 7377 #define MLXSW_REG_MFCR_LEN 0x08 7378 7379 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7380 7381 enum mlxsw_reg_mfcr_pwm_frequency { 7382 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7383 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7384 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7385 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7386 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7387 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7388 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7389 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7390 }; 7391 7392 /* reg_mfcr_pwm_frequency 7393 * Controls the frequency of the PWM signal. 7394 * Access: RW 7395 */ 7396 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7397 7398 #define MLXSW_MFCR_TACHOS_MAX 10 7399 7400 /* reg_mfcr_tacho_active 7401 * Indicates which of the tachometer is active (bit per tachometer). 7402 * Access: RO 7403 */ 7404 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7405 7406 #define MLXSW_MFCR_PWMS_MAX 5 7407 7408 /* reg_mfcr_pwm_active 7409 * Indicates which of the PWM control is active (bit per PWM). 7410 * Access: RO 7411 */ 7412 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7413 7414 static inline void 7415 mlxsw_reg_mfcr_pack(char *payload, 7416 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7417 { 7418 MLXSW_REG_ZERO(mfcr, payload); 7419 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7420 } 7421 7422 static inline void 7423 mlxsw_reg_mfcr_unpack(char *payload, 7424 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7425 u16 *p_tacho_active, u8 *p_pwm_active) 7426 { 7427 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7428 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7429 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7430 } 7431 7432 /* MFSC - Management Fan Speed Control Register 7433 * -------------------------------------------- 7434 * This register controls the settings of the Fan Speed PWM mechanism. 7435 */ 7436 #define MLXSW_REG_MFSC_ID 0x9002 7437 #define MLXSW_REG_MFSC_LEN 0x08 7438 7439 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7440 7441 /* reg_mfsc_pwm 7442 * Fan pwm to control / monitor. 7443 * Access: Index 7444 */ 7445 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7446 7447 /* reg_mfsc_pwm_duty_cycle 7448 * Controls the duty cycle of the PWM. Value range from 0..255 to 7449 * represent duty cycle of 0%...100%. 7450 * Access: RW 7451 */ 7452 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7453 7454 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7455 u8 pwm_duty_cycle) 7456 { 7457 MLXSW_REG_ZERO(mfsc, payload); 7458 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7459 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7460 } 7461 7462 /* MFSM - Management Fan Speed Measurement 7463 * --------------------------------------- 7464 * This register controls the settings of the Tacho measurements and 7465 * enables reading the Tachometer measurements. 7466 */ 7467 #define MLXSW_REG_MFSM_ID 0x9003 7468 #define MLXSW_REG_MFSM_LEN 0x08 7469 7470 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7471 7472 /* reg_mfsm_tacho 7473 * Fan tachometer index. 7474 * Access: Index 7475 */ 7476 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7477 7478 /* reg_mfsm_rpm 7479 * Fan speed (round per minute). 7480 * Access: RO 7481 */ 7482 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7483 7484 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7485 { 7486 MLXSW_REG_ZERO(mfsm, payload); 7487 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7488 } 7489 7490 /* MFSL - Management Fan Speed Limit Register 7491 * ------------------------------------------ 7492 * The Fan Speed Limit register is used to configure the fan speed 7493 * event / interrupt notification mechanism. Fan speed threshold are 7494 * defined for both under-speed and over-speed. 7495 */ 7496 #define MLXSW_REG_MFSL_ID 0x9004 7497 #define MLXSW_REG_MFSL_LEN 0x0C 7498 7499 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7500 7501 /* reg_mfsl_tacho 7502 * Fan tachometer index. 7503 * Access: Index 7504 */ 7505 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7506 7507 /* reg_mfsl_tach_min 7508 * Tachometer minimum value (minimum RPM). 7509 * Access: RW 7510 */ 7511 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7512 7513 /* reg_mfsl_tach_max 7514 * Tachometer maximum value (maximum RPM). 7515 * Access: RW 7516 */ 7517 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7518 7519 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7520 u16 tach_min, u16 tach_max) 7521 { 7522 MLXSW_REG_ZERO(mfsl, payload); 7523 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7524 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7525 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7526 } 7527 7528 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7529 u16 *p_tach_min, u16 *p_tach_max) 7530 { 7531 if (p_tach_min) 7532 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7533 7534 if (p_tach_max) 7535 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7536 } 7537 7538 /* MTCAP - Management Temperature Capabilities 7539 * ------------------------------------------- 7540 * This register exposes the capabilities of the device and 7541 * system temperature sensing. 7542 */ 7543 #define MLXSW_REG_MTCAP_ID 0x9009 7544 #define MLXSW_REG_MTCAP_LEN 0x08 7545 7546 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7547 7548 /* reg_mtcap_sensor_count 7549 * Number of sensors supported by the device. 7550 * This includes the QSFP module sensors (if exists in the QSFP module). 7551 * Access: RO 7552 */ 7553 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7554 7555 /* MTMP - Management Temperature 7556 * ----------------------------- 7557 * This register controls the settings of the temperature measurements 7558 * and enables reading the temperature measurements. Note that temperature 7559 * is in 0.125 degrees Celsius. 7560 */ 7561 #define MLXSW_REG_MTMP_ID 0x900A 7562 #define MLXSW_REG_MTMP_LEN 0x20 7563 7564 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 7565 7566 /* reg_mtmp_sensor_index 7567 * Sensors index to access. 7568 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 7569 * (module 0 is mapped to sensor_index 64). 7570 * Access: Index 7571 */ 7572 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 7573 7574 /* Convert to milli degrees Celsius */ 7575 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 7576 7577 /* reg_mtmp_temperature 7578 * Temperature reading from the sensor. Reading is in 0.125 Celsius 7579 * degrees units. 7580 * Access: RO 7581 */ 7582 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 7583 7584 /* reg_mtmp_mte 7585 * Max Temperature Enable - enables measuring the max temperature on a sensor. 7586 * Access: RW 7587 */ 7588 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 7589 7590 /* reg_mtmp_mtr 7591 * Max Temperature Reset - clears the value of the max temperature register. 7592 * Access: WO 7593 */ 7594 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7595 7596 /* reg_mtmp_max_temperature 7597 * The highest measured temperature from the sensor. 7598 * When the bit mte is cleared, the field max_temperature is reserved. 7599 * Access: RO 7600 */ 7601 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7602 7603 /* reg_mtmp_tee 7604 * Temperature Event Enable. 7605 * 0 - Do not generate event 7606 * 1 - Generate event 7607 * 2 - Generate single event 7608 * Access: RW 7609 */ 7610 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7611 7612 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7613 7614 /* reg_mtmp_temperature_threshold_hi 7615 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7616 * Access: RW 7617 */ 7618 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7619 7620 /* reg_mtmp_temperature_threshold_lo 7621 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7622 * Access: RW 7623 */ 7624 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7625 7626 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7627 7628 /* reg_mtmp_sensor_name 7629 * Sensor Name 7630 * Access: RO 7631 */ 7632 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 7633 7634 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 7635 bool max_temp_enable, 7636 bool max_temp_reset) 7637 { 7638 MLXSW_REG_ZERO(mtmp, payload); 7639 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 7640 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 7641 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 7642 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 7643 MLXSW_REG_MTMP_THRESH_HI); 7644 } 7645 7646 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 7647 unsigned int *p_max_temp, 7648 char *sensor_name) 7649 { 7650 u16 temp; 7651 7652 if (p_temp) { 7653 temp = mlxsw_reg_mtmp_temperature_get(payload); 7654 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7655 } 7656 if (p_max_temp) { 7657 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 7658 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7659 } 7660 if (sensor_name) 7661 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 7662 } 7663 7664 /* MCIA - Management Cable Info Access 7665 * ----------------------------------- 7666 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 7667 */ 7668 7669 #define MLXSW_REG_MCIA_ID 0x9014 7670 #define MLXSW_REG_MCIA_LEN 0x40 7671 7672 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 7673 7674 /* reg_mcia_l 7675 * Lock bit. Setting this bit will lock the access to the specific 7676 * cable. Used for updating a full page in a cable EPROM. Any access 7677 * other then subsequence writes will fail while the port is locked. 7678 * Access: RW 7679 */ 7680 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 7681 7682 /* reg_mcia_module 7683 * Module number. 7684 * Access: Index 7685 */ 7686 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 7687 7688 /* reg_mcia_status 7689 * Module status. 7690 * Access: RO 7691 */ 7692 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 7693 7694 /* reg_mcia_i2c_device_address 7695 * I2C device address. 7696 * Access: RW 7697 */ 7698 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 7699 7700 /* reg_mcia_page_number 7701 * Page number. 7702 * Access: RW 7703 */ 7704 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 7705 7706 /* reg_mcia_device_address 7707 * Device address. 7708 * Access: RW 7709 */ 7710 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 7711 7712 /* reg_mcia_size 7713 * Number of bytes to read/write (up to 48 bytes). 7714 * Access: RW 7715 */ 7716 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 7717 7718 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 7719 7720 /* reg_mcia_eeprom 7721 * Bytes to read/write. 7722 * Access: RW 7723 */ 7724 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 7725 7726 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 7727 u8 page_number, u16 device_addr, 7728 u8 size, u8 i2c_device_addr) 7729 { 7730 MLXSW_REG_ZERO(mcia, payload); 7731 mlxsw_reg_mcia_module_set(payload, module); 7732 mlxsw_reg_mcia_l_set(payload, lock); 7733 mlxsw_reg_mcia_page_number_set(payload, page_number); 7734 mlxsw_reg_mcia_device_address_set(payload, device_addr); 7735 mlxsw_reg_mcia_size_set(payload, size); 7736 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 7737 } 7738 7739 /* MPAT - Monitoring Port Analyzer Table 7740 * ------------------------------------- 7741 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 7742 * For an enabled analyzer, all fields except e (enable) cannot be modified. 7743 */ 7744 #define MLXSW_REG_MPAT_ID 0x901A 7745 #define MLXSW_REG_MPAT_LEN 0x78 7746 7747 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 7748 7749 /* reg_mpat_pa_id 7750 * Port Analyzer ID. 7751 * Access: Index 7752 */ 7753 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 7754 7755 /* reg_mpat_system_port 7756 * A unique port identifier for the final destination of the packet. 7757 * Access: RW 7758 */ 7759 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 7760 7761 /* reg_mpat_e 7762 * Enable. Indicating the Port Analyzer is enabled. 7763 * Access: RW 7764 */ 7765 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 7766 7767 /* reg_mpat_qos 7768 * Quality Of Service Mode. 7769 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 7770 * PCP, DEI, DSCP or VL) are configured. 7771 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 7772 * same as in the original packet that has triggered the mirroring. For 7773 * SPAN also the pcp,dei are maintained. 7774 * Access: RW 7775 */ 7776 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 7777 7778 /* reg_mpat_be 7779 * Best effort mode. Indicates mirroring traffic should not cause packet 7780 * drop or back pressure, but will discard the mirrored packets. Mirrored 7781 * packets will be forwarded on a best effort manner. 7782 * 0: Do not discard mirrored packets 7783 * 1: Discard mirrored packets if causing congestion 7784 * Access: RW 7785 */ 7786 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 7787 7788 enum mlxsw_reg_mpat_span_type { 7789 /* Local SPAN Ethernet. 7790 * The original packet is not encapsulated. 7791 */ 7792 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 7793 7794 /* Remote SPAN Ethernet VLAN. 7795 * The packet is forwarded to the monitoring port on the monitoring 7796 * VLAN. 7797 */ 7798 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 7799 7800 /* Encapsulated Remote SPAN Ethernet L3 GRE. 7801 * The packet is encapsulated with GRE header. 7802 */ 7803 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 7804 }; 7805 7806 /* reg_mpat_span_type 7807 * SPAN type. 7808 * Access: RW 7809 */ 7810 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 7811 7812 /* Remote SPAN - Ethernet VLAN 7813 * - - - - - - - - - - - - - - 7814 */ 7815 7816 /* reg_mpat_eth_rspan_vid 7817 * Encapsulation header VLAN ID. 7818 * Access: RW 7819 */ 7820 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 7821 7822 /* Encapsulated Remote SPAN - Ethernet L2 7823 * - - - - - - - - - - - - - - - - - - - 7824 */ 7825 7826 enum mlxsw_reg_mpat_eth_rspan_version { 7827 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 7828 }; 7829 7830 /* reg_mpat_eth_rspan_version 7831 * RSPAN mirror header version. 7832 * Access: RW 7833 */ 7834 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 7835 7836 /* reg_mpat_eth_rspan_mac 7837 * Destination MAC address. 7838 * Access: RW 7839 */ 7840 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 7841 7842 /* reg_mpat_eth_rspan_tp 7843 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 7844 * Access: RW 7845 */ 7846 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 7847 7848 /* Encapsulated Remote SPAN - Ethernet L3 7849 * - - - - - - - - - - - - - - - - - - - 7850 */ 7851 7852 enum mlxsw_reg_mpat_eth_rspan_protocol { 7853 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 7854 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 7855 }; 7856 7857 /* reg_mpat_eth_rspan_protocol 7858 * SPAN encapsulation protocol. 7859 * Access: RW 7860 */ 7861 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 7862 7863 /* reg_mpat_eth_rspan_ttl 7864 * Encapsulation header Time-to-Live/HopLimit. 7865 * Access: RW 7866 */ 7867 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 7868 7869 /* reg_mpat_eth_rspan_smac 7870 * Source MAC address 7871 * Access: RW 7872 */ 7873 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 7874 7875 /* reg_mpat_eth_rspan_dip* 7876 * Destination IP address. The IP version is configured by protocol. 7877 * Access: RW 7878 */ 7879 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 7880 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 7881 7882 /* reg_mpat_eth_rspan_sip* 7883 * Source IP address. The IP version is configured by protocol. 7884 * Access: RW 7885 */ 7886 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 7887 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 7888 7889 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 7890 u16 system_port, bool e, 7891 enum mlxsw_reg_mpat_span_type span_type) 7892 { 7893 MLXSW_REG_ZERO(mpat, payload); 7894 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 7895 mlxsw_reg_mpat_system_port_set(payload, system_port); 7896 mlxsw_reg_mpat_e_set(payload, e); 7897 mlxsw_reg_mpat_qos_set(payload, 1); 7898 mlxsw_reg_mpat_be_set(payload, 1); 7899 mlxsw_reg_mpat_span_type_set(payload, span_type); 7900 } 7901 7902 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 7903 { 7904 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 7905 } 7906 7907 static inline void 7908 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 7909 enum mlxsw_reg_mpat_eth_rspan_version version, 7910 const char *mac, 7911 bool tp) 7912 { 7913 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 7914 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 7915 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 7916 } 7917 7918 static inline void 7919 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 7920 const char *smac, 7921 u32 sip, u32 dip) 7922 { 7923 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7924 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7925 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7926 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 7927 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 7928 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 7929 } 7930 7931 static inline void 7932 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 7933 const char *smac, 7934 struct in6_addr sip, struct in6_addr dip) 7935 { 7936 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 7937 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 7938 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 7939 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 7940 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 7941 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 7942 } 7943 7944 /* MPAR - Monitoring Port Analyzer Register 7945 * ---------------------------------------- 7946 * MPAR register is used to query and configure the port analyzer port mirroring 7947 * properties. 7948 */ 7949 #define MLXSW_REG_MPAR_ID 0x901B 7950 #define MLXSW_REG_MPAR_LEN 0x08 7951 7952 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 7953 7954 /* reg_mpar_local_port 7955 * The local port to mirror the packets from. 7956 * Access: Index 7957 */ 7958 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 7959 7960 enum mlxsw_reg_mpar_i_e { 7961 MLXSW_REG_MPAR_TYPE_EGRESS, 7962 MLXSW_REG_MPAR_TYPE_INGRESS, 7963 }; 7964 7965 /* reg_mpar_i_e 7966 * Ingress/Egress 7967 * Access: Index 7968 */ 7969 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 7970 7971 /* reg_mpar_enable 7972 * Enable mirroring 7973 * By default, port mirroring is disabled for all ports. 7974 * Access: RW 7975 */ 7976 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 7977 7978 /* reg_mpar_pa_id 7979 * Port Analyzer ID. 7980 * Access: RW 7981 */ 7982 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 7983 7984 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 7985 enum mlxsw_reg_mpar_i_e i_e, 7986 bool enable, u8 pa_id) 7987 { 7988 MLXSW_REG_ZERO(mpar, payload); 7989 mlxsw_reg_mpar_local_port_set(payload, local_port); 7990 mlxsw_reg_mpar_enable_set(payload, enable); 7991 mlxsw_reg_mpar_i_e_set(payload, i_e); 7992 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 7993 } 7994 7995 /* MRSR - Management Reset and Shutdown Register 7996 * --------------------------------------------- 7997 * MRSR register is used to reset or shutdown the switch or 7998 * the entire system (when applicable). 7999 */ 8000 #define MLXSW_REG_MRSR_ID 0x9023 8001 #define MLXSW_REG_MRSR_LEN 0x08 8002 8003 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8004 8005 /* reg_mrsr_command 8006 * Reset/shutdown command 8007 * 0 - do nothing 8008 * 1 - software reset 8009 * Access: WO 8010 */ 8011 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8012 8013 static inline void mlxsw_reg_mrsr_pack(char *payload) 8014 { 8015 MLXSW_REG_ZERO(mrsr, payload); 8016 mlxsw_reg_mrsr_command_set(payload, 1); 8017 } 8018 8019 /* MLCR - Management LED Control Register 8020 * -------------------------------------- 8021 * Controls the system LEDs. 8022 */ 8023 #define MLXSW_REG_MLCR_ID 0x902B 8024 #define MLXSW_REG_MLCR_LEN 0x0C 8025 8026 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8027 8028 /* reg_mlcr_local_port 8029 * Local port number. 8030 * Access: RW 8031 */ 8032 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8033 8034 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8035 8036 /* reg_mlcr_beacon_duration 8037 * Duration of the beacon to be active, in seconds. 8038 * 0x0 - Will turn off the beacon. 8039 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8040 * Access: RW 8041 */ 8042 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8043 8044 /* reg_mlcr_beacon_remain 8045 * Remaining duration of the beacon, in seconds. 8046 * 0xFFFF indicates an infinite amount of time. 8047 * Access: RO 8048 */ 8049 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8050 8051 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8052 bool active) 8053 { 8054 MLXSW_REG_ZERO(mlcr, payload); 8055 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8056 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8057 MLXSW_REG_MLCR_DURATION_MAX : 0); 8058 } 8059 8060 /* MCQI - Management Component Query Information 8061 * --------------------------------------------- 8062 * This register allows querying information about firmware components. 8063 */ 8064 #define MLXSW_REG_MCQI_ID 0x9061 8065 #define MLXSW_REG_MCQI_BASE_LEN 0x18 8066 #define MLXSW_REG_MCQI_CAP_LEN 0x14 8067 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 8068 8069 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 8070 8071 /* reg_mcqi_component_index 8072 * Index of the accessed component. 8073 * Access: Index 8074 */ 8075 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 8076 8077 enum mlxfw_reg_mcqi_info_type { 8078 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 8079 }; 8080 8081 /* reg_mcqi_info_type 8082 * Component properties set. 8083 * Access: RW 8084 */ 8085 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 8086 8087 /* reg_mcqi_offset 8088 * The requested/returned data offset from the section start, given in bytes. 8089 * Must be DWORD aligned. 8090 * Access: RW 8091 */ 8092 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8093 8094 /* reg_mcqi_data_size 8095 * The requested/returned data size, given in bytes. If data_size is not DWORD 8096 * aligned, the last bytes are zero padded. 8097 * Access: RW 8098 */ 8099 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8100 8101 /* reg_mcqi_cap_max_component_size 8102 * Maximum size for this component, given in bytes. 8103 * Access: RO 8104 */ 8105 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8106 8107 /* reg_mcqi_cap_log_mcda_word_size 8108 * Log 2 of the access word size in bytes. Read and write access must be aligned 8109 * to the word size. Write access must be done for an integer number of words. 8110 * Access: RO 8111 */ 8112 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8113 8114 /* reg_mcqi_cap_mcda_max_write_size 8115 * Maximal write size for MCDA register 8116 * Access: RO 8117 */ 8118 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8119 8120 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8121 { 8122 MLXSW_REG_ZERO(mcqi, payload); 8123 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8124 mlxsw_reg_mcqi_info_type_set(payload, 8125 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8126 mlxsw_reg_mcqi_offset_set(payload, 0); 8127 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8128 } 8129 8130 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8131 u32 *p_cap_max_component_size, 8132 u8 *p_cap_log_mcda_word_size, 8133 u16 *p_cap_mcda_max_write_size) 8134 { 8135 *p_cap_max_component_size = 8136 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8137 *p_cap_log_mcda_word_size = 8138 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8139 *p_cap_mcda_max_write_size = 8140 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8141 } 8142 8143 /* MCC - Management Component Control 8144 * ---------------------------------- 8145 * Controls the firmware component and updates the FSM. 8146 */ 8147 #define MLXSW_REG_MCC_ID 0x9062 8148 #define MLXSW_REG_MCC_LEN 0x1C 8149 8150 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8151 8152 enum mlxsw_reg_mcc_instruction { 8153 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8154 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8155 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8156 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8157 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8158 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8159 }; 8160 8161 /* reg_mcc_instruction 8162 * Command to be executed by the FSM. 8163 * Applicable for write operation only. 8164 * Access: RW 8165 */ 8166 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8167 8168 /* reg_mcc_component_index 8169 * Index of the accessed component. Applicable only for commands that 8170 * refer to components. Otherwise, this field is reserved. 8171 * Access: Index 8172 */ 8173 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8174 8175 /* reg_mcc_update_handle 8176 * Token representing the current flow executed by the FSM. 8177 * Access: WO 8178 */ 8179 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8180 8181 /* reg_mcc_error_code 8182 * Indicates the successful completion of the instruction, or the reason it 8183 * failed 8184 * Access: RO 8185 */ 8186 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8187 8188 /* reg_mcc_control_state 8189 * Current FSM state 8190 * Access: RO 8191 */ 8192 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8193 8194 /* reg_mcc_component_size 8195 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8196 * the size may shorten the update time. Value 0x0 means that size is 8197 * unspecified. 8198 * Access: WO 8199 */ 8200 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8201 8202 static inline void mlxsw_reg_mcc_pack(char *payload, 8203 enum mlxsw_reg_mcc_instruction instr, 8204 u16 component_index, u32 update_handle, 8205 u32 component_size) 8206 { 8207 MLXSW_REG_ZERO(mcc, payload); 8208 mlxsw_reg_mcc_instruction_set(payload, instr); 8209 mlxsw_reg_mcc_component_index_set(payload, component_index); 8210 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8211 mlxsw_reg_mcc_component_size_set(payload, component_size); 8212 } 8213 8214 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8215 u8 *p_error_code, u8 *p_control_state) 8216 { 8217 if (p_update_handle) 8218 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8219 if (p_error_code) 8220 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8221 if (p_control_state) 8222 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8223 } 8224 8225 /* MCDA - Management Component Data Access 8226 * --------------------------------------- 8227 * This register allows reading and writing a firmware component. 8228 */ 8229 #define MLXSW_REG_MCDA_ID 0x9063 8230 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8231 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8232 #define MLXSW_REG_MCDA_LEN \ 8233 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8234 8235 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8236 8237 /* reg_mcda_update_handle 8238 * Token representing the current flow executed by the FSM. 8239 * Access: RW 8240 */ 8241 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8242 8243 /* reg_mcda_offset 8244 * Offset of accessed address relative to component start. Accesses must be in 8245 * accordance to log_mcda_word_size in MCQI reg. 8246 * Access: RW 8247 */ 8248 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8249 8250 /* reg_mcda_size 8251 * Size of the data accessed, given in bytes. 8252 * Access: RW 8253 */ 8254 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8255 8256 /* reg_mcda_data 8257 * Data block accessed. 8258 * Access: RW 8259 */ 8260 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8261 8262 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8263 u32 offset, u16 size, u8 *data) 8264 { 8265 int i; 8266 8267 MLXSW_REG_ZERO(mcda, payload); 8268 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8269 mlxsw_reg_mcda_offset_set(payload, offset); 8270 mlxsw_reg_mcda_size_set(payload, size); 8271 8272 for (i = 0; i < size / 4; i++) 8273 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8274 } 8275 8276 /* MPSC - Monitoring Packet Sampling Configuration Register 8277 * -------------------------------------------------------- 8278 * MPSC Register is used to configure the Packet Sampling mechanism. 8279 */ 8280 #define MLXSW_REG_MPSC_ID 0x9080 8281 #define MLXSW_REG_MPSC_LEN 0x1C 8282 8283 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8284 8285 /* reg_mpsc_local_port 8286 * Local port number 8287 * Not supported for CPU port 8288 * Access: Index 8289 */ 8290 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8291 8292 /* reg_mpsc_e 8293 * Enable sampling on port local_port 8294 * Access: RW 8295 */ 8296 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8297 8298 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8299 8300 /* reg_mpsc_rate 8301 * Sampling rate = 1 out of rate packets (with randomization around 8302 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8303 * Access: RW 8304 */ 8305 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8306 8307 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8308 u32 rate) 8309 { 8310 MLXSW_REG_ZERO(mpsc, payload); 8311 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8312 mlxsw_reg_mpsc_e_set(payload, e); 8313 mlxsw_reg_mpsc_rate_set(payload, rate); 8314 } 8315 8316 /* MGPC - Monitoring General Purpose Counter Set Register 8317 * The MGPC register retrieves and sets the General Purpose Counter Set. 8318 */ 8319 #define MLXSW_REG_MGPC_ID 0x9081 8320 #define MLXSW_REG_MGPC_LEN 0x18 8321 8322 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8323 8324 /* reg_mgpc_counter_set_type 8325 * Counter set type. 8326 * Access: OP 8327 */ 8328 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8329 8330 /* reg_mgpc_counter_index 8331 * Counter index. 8332 * Access: Index 8333 */ 8334 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8335 8336 enum mlxsw_reg_mgpc_opcode { 8337 /* Nop */ 8338 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8339 /* Clear counters */ 8340 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8341 }; 8342 8343 /* reg_mgpc_opcode 8344 * Opcode. 8345 * Access: OP 8346 */ 8347 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8348 8349 /* reg_mgpc_byte_counter 8350 * Byte counter value. 8351 * Access: RW 8352 */ 8353 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8354 8355 /* reg_mgpc_packet_counter 8356 * Packet counter value. 8357 * Access: RW 8358 */ 8359 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8360 8361 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8362 enum mlxsw_reg_mgpc_opcode opcode, 8363 enum mlxsw_reg_flow_counter_set_type set_type) 8364 { 8365 MLXSW_REG_ZERO(mgpc, payload); 8366 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8367 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8368 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8369 } 8370 8371 /* MPRS - Monitoring Parsing State Register 8372 * ---------------------------------------- 8373 * The MPRS register is used for setting up the parsing for hash, 8374 * policy-engine and routing. 8375 */ 8376 #define MLXSW_REG_MPRS_ID 0x9083 8377 #define MLXSW_REG_MPRS_LEN 0x14 8378 8379 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 8380 8381 /* reg_mprs_parsing_depth 8382 * Minimum parsing depth. 8383 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 8384 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 8385 * Access: RW 8386 */ 8387 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 8388 8389 /* reg_mprs_parsing_en 8390 * Parsing enable. 8391 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 8392 * NVGRE. Default is enabled. Reserved when SwitchX-2. 8393 * Access: RW 8394 */ 8395 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 8396 8397 /* reg_mprs_vxlan_udp_dport 8398 * VxLAN UDP destination port. 8399 * Used for identifying VxLAN packets and for dport field in 8400 * encapsulation. Default is 4789. 8401 * Access: RW 8402 */ 8403 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 8404 8405 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 8406 u16 vxlan_udp_dport) 8407 { 8408 MLXSW_REG_ZERO(mprs, payload); 8409 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 8410 mlxsw_reg_mprs_parsing_en_set(payload, true); 8411 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 8412 } 8413 8414 /* TNGCR - Tunneling NVE General Configuration Register 8415 * ---------------------------------------------------- 8416 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8417 */ 8418 #define MLXSW_REG_TNGCR_ID 0xA001 8419 #define MLXSW_REG_TNGCR_LEN 0x44 8420 8421 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 8422 8423 enum mlxsw_reg_tngcr_type { 8424 MLXSW_REG_TNGCR_TYPE_VXLAN, 8425 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 8426 MLXSW_REG_TNGCR_TYPE_GENEVE, 8427 MLXSW_REG_TNGCR_TYPE_NVGRE, 8428 }; 8429 8430 /* reg_tngcr_type 8431 * Tunnel type for encapsulation and decapsulation. The types are mutually 8432 * exclusive. 8433 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 8434 * Access: RW 8435 */ 8436 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 8437 8438 /* reg_tngcr_nve_valid 8439 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 8440 * Access: RW 8441 */ 8442 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 8443 8444 /* reg_tngcr_nve_ttl_uc 8445 * The TTL for NVE tunnel encapsulation underlay unicast packets. 8446 * Access: RW 8447 */ 8448 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 8449 8450 /* reg_tngcr_nve_ttl_mc 8451 * The TTL for NVE tunnel encapsulation underlay multicast packets. 8452 * Access: RW 8453 */ 8454 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 8455 8456 enum { 8457 /* Do not copy flow label. Calculate flow label using nve_flh. */ 8458 MLXSW_REG_TNGCR_FL_NO_COPY, 8459 /* Copy flow label from inner packet if packet is IPv6 and 8460 * encapsulation is by IPv6. Otherwise, calculate flow label using 8461 * nve_flh. 8462 */ 8463 MLXSW_REG_TNGCR_FL_COPY, 8464 }; 8465 8466 /* reg_tngcr_nve_flc 8467 * For NVE tunnel encapsulation: Flow label copy from inner packet. 8468 * Access: RW 8469 */ 8470 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 8471 8472 enum { 8473 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 8474 * uses {nve_fl_prefix, nve_fl_suffix}. 8475 */ 8476 MLXSW_REG_TNGCR_FL_NO_HASH, 8477 /* 8 LSBs of the flow label are calculated from ECMP hash of the 8478 * inner packet. 12 MSBs are configured by nve_fl_prefix. 8479 */ 8480 MLXSW_REG_TNGCR_FL_HASH, 8481 }; 8482 8483 /* reg_tngcr_nve_flh 8484 * NVE flow label hash. 8485 * Access: RW 8486 */ 8487 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 8488 8489 /* reg_tngcr_nve_fl_prefix 8490 * NVE flow label prefix. Constant 12 MSBs of the flow label. 8491 * Access: RW 8492 */ 8493 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 8494 8495 /* reg_tngcr_nve_fl_suffix 8496 * NVE flow label suffix. Constant 8 LSBs of the flow label. 8497 * Reserved when nve_flh=1 and for Spectrum. 8498 * Access: RW 8499 */ 8500 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 8501 8502 enum { 8503 /* Source UDP port is fixed (default '0') */ 8504 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 8505 /* Source UDP port is calculated based on hash */ 8506 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 8507 }; 8508 8509 /* reg_tngcr_nve_udp_sport_type 8510 * NVE UDP source port type. 8511 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 8512 * When the source UDP port is calculated based on hash, then the 8 LSBs 8513 * are calculated from hash the 8 MSBs are configured by 8514 * nve_udp_sport_prefix. 8515 * Access: RW 8516 */ 8517 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 8518 8519 /* reg_tngcr_nve_udp_sport_prefix 8520 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 8521 * Reserved when NVE type is NVGRE. 8522 * Access: RW 8523 */ 8524 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 8525 8526 /* reg_tngcr_nve_group_size_mc 8527 * The amount of sequential linked lists of MC entries. The first linked 8528 * list is configured by SFD.underlay_mc_ptr. 8529 * Valid values: 1, 2, 4, 8, 16, 32, 64 8530 * The linked list are configured by TNUMT. 8531 * The hash is set by LAG hash. 8532 * Access: RW 8533 */ 8534 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 8535 8536 /* reg_tngcr_nve_group_size_flood 8537 * The amount of sequential linked lists of flooding entries. The first 8538 * linked list is configured by SFMR.nve_tunnel_flood_ptr 8539 * Valid values: 1, 2, 4, 8, 16, 32, 64 8540 * The linked list are configured by TNUMT. 8541 * The hash is set by LAG hash. 8542 * Access: RW 8543 */ 8544 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 8545 8546 /* reg_tngcr_learn_enable 8547 * During decapsulation, whether to learn from NVE port. 8548 * Reserved when Spectrum-2. See TNPC. 8549 * Access: RW 8550 */ 8551 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 8552 8553 /* reg_tngcr_underlay_virtual_router 8554 * Underlay virtual router. 8555 * Reserved when Spectrum-2. 8556 * Access: RW 8557 */ 8558 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 8559 8560 /* reg_tngcr_underlay_rif 8561 * Underlay ingress router interface. RIF type should be loopback generic. 8562 * Reserved when Spectrum. 8563 * Access: RW 8564 */ 8565 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 8566 8567 /* reg_tngcr_usipv4 8568 * Underlay source IPv4 address of the NVE. 8569 * Access: RW 8570 */ 8571 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 8572 8573 /* reg_tngcr_usipv6 8574 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 8575 * modified under traffic of NVE tunneling encapsulation. 8576 * Access: RW 8577 */ 8578 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 8579 8580 static inline void mlxsw_reg_tngcr_pack(char *payload, 8581 enum mlxsw_reg_tngcr_type type, 8582 bool valid, u8 ttl) 8583 { 8584 MLXSW_REG_ZERO(tngcr, payload); 8585 mlxsw_reg_tngcr_type_set(payload, type); 8586 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 8587 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 8588 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 8589 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 8590 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 8591 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 8592 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 8593 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 8594 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 8595 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 8596 } 8597 8598 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 8599 * ------------------------------------------------------- 8600 * The TNUMT register is for building the underlay MC table. It is used 8601 * for MC, flooding and BC traffic into the NVE tunnel. 8602 */ 8603 #define MLXSW_REG_TNUMT_ID 0xA003 8604 #define MLXSW_REG_TNUMT_LEN 0x20 8605 8606 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 8607 8608 enum mlxsw_reg_tnumt_record_type { 8609 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 8610 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 8611 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 8612 }; 8613 8614 /* reg_tnumt_record_type 8615 * Record type. 8616 * Access: RW 8617 */ 8618 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 8619 8620 enum mlxsw_reg_tnumt_tunnel_port { 8621 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 8622 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 8623 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 8624 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 8625 }; 8626 8627 /* reg_tnumt_tunnel_port 8628 * Tunnel port. 8629 * Access: RW 8630 */ 8631 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 8632 8633 /* reg_tnumt_underlay_mc_ptr 8634 * Index to the underlay multicast table. 8635 * For Spectrum the index is to the KVD linear. 8636 * Access: Index 8637 */ 8638 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 8639 8640 /* reg_tnumt_vnext 8641 * The next_underlay_mc_ptr is valid. 8642 * Access: RW 8643 */ 8644 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 8645 8646 /* reg_tnumt_next_underlay_mc_ptr 8647 * The next index to the underlay multicast table. 8648 * Access: RW 8649 */ 8650 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 8651 8652 /* reg_tnumt_record_size 8653 * Number of IP addresses in the record. 8654 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 8655 * Access: RW 8656 */ 8657 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 8658 8659 /* reg_tnumt_udip 8660 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 8661 * Access: RW 8662 */ 8663 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 8664 8665 /* reg_tnumt_udip_ptr 8666 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 8667 * i >= size. The IPv6 addresses are configured by RIPS. 8668 * Access: RW 8669 */ 8670 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 8671 8672 static inline void mlxsw_reg_tnumt_pack(char *payload, 8673 enum mlxsw_reg_tnumt_record_type type, 8674 enum mlxsw_reg_tnumt_tunnel_port tport, 8675 u32 underlay_mc_ptr, bool vnext, 8676 u32 next_underlay_mc_ptr, 8677 u8 record_size) 8678 { 8679 MLXSW_REG_ZERO(tnumt, payload); 8680 mlxsw_reg_tnumt_record_type_set(payload, type); 8681 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 8682 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 8683 mlxsw_reg_tnumt_vnext_set(payload, vnext); 8684 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 8685 mlxsw_reg_tnumt_record_size_set(payload, record_size); 8686 } 8687 8688 /* TNQCR - Tunneling NVE QoS Configuration Register 8689 * ------------------------------------------------ 8690 * The TNQCR register configures how QoS is set in encapsulation into the 8691 * underlay network. 8692 */ 8693 #define MLXSW_REG_TNQCR_ID 0xA010 8694 #define MLXSW_REG_TNQCR_LEN 0x0C 8695 8696 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 8697 8698 /* reg_tnqcr_enc_set_dscp 8699 * For encapsulation: How to set DSCP field: 8700 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 8701 * (outer) IP header. If there is no IP header, use TNQDR.dscp 8702 * 1 - Set the DSCP field as TNQDR.dscp 8703 * Access: RW 8704 */ 8705 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 8706 8707 static inline void mlxsw_reg_tnqcr_pack(char *payload) 8708 { 8709 MLXSW_REG_ZERO(tnqcr, payload); 8710 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 8711 } 8712 8713 /* TNQDR - Tunneling NVE QoS Default Register 8714 * ------------------------------------------ 8715 * The TNQDR register configures the default QoS settings for NVE 8716 * encapsulation. 8717 */ 8718 #define MLXSW_REG_TNQDR_ID 0xA011 8719 #define MLXSW_REG_TNQDR_LEN 0x08 8720 8721 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 8722 8723 /* reg_tnqdr_local_port 8724 * Local port number (receive port). CPU port is supported. 8725 * Access: Index 8726 */ 8727 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 8728 8729 /* reg_tnqdr_dscp 8730 * For encapsulation, the default DSCP. 8731 * Access: RW 8732 */ 8733 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 8734 8735 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 8736 { 8737 MLXSW_REG_ZERO(tnqdr, payload); 8738 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 8739 mlxsw_reg_tnqdr_dscp_set(payload, 0); 8740 } 8741 8742 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 8743 * -------------------------------------------------------- 8744 * The TNEEM register maps ECN of the IP header at the ingress to the 8745 * encapsulation to the ECN of the underlay network. 8746 */ 8747 #define MLXSW_REG_TNEEM_ID 0xA012 8748 #define MLXSW_REG_TNEEM_LEN 0x0C 8749 8750 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 8751 8752 /* reg_tneem_overlay_ecn 8753 * ECN of the IP header in the overlay network. 8754 * Access: Index 8755 */ 8756 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 8757 8758 /* reg_tneem_underlay_ecn 8759 * ECN of the IP header in the underlay network. 8760 * Access: RW 8761 */ 8762 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 8763 8764 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 8765 u8 underlay_ecn) 8766 { 8767 MLXSW_REG_ZERO(tneem, payload); 8768 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 8769 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 8770 } 8771 8772 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 8773 * -------------------------------------------------------- 8774 * The TNDEM register configures the actions that are done in the 8775 * decapsulation. 8776 */ 8777 #define MLXSW_REG_TNDEM_ID 0xA013 8778 #define MLXSW_REG_TNDEM_LEN 0x0C 8779 8780 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 8781 8782 /* reg_tndem_underlay_ecn 8783 * ECN field of the IP header in the underlay network. 8784 * Access: Index 8785 */ 8786 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 8787 8788 /* reg_tndem_overlay_ecn 8789 * ECN field of the IP header in the overlay network. 8790 * Access: Index 8791 */ 8792 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 8793 8794 /* reg_tndem_eip_ecn 8795 * Egress IP ECN. ECN field of the IP header of the packet which goes out 8796 * from the decapsulation. 8797 * Access: RW 8798 */ 8799 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 8800 8801 /* reg_tndem_trap_en 8802 * Trap enable: 8803 * 0 - No trap due to decap ECN 8804 * 1 - Trap enable with trap_id 8805 * Access: RW 8806 */ 8807 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 8808 8809 /* reg_tndem_trap_id 8810 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 8811 * Reserved when trap_en is '0'. 8812 * Access: RW 8813 */ 8814 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 8815 8816 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 8817 u8 overlay_ecn, u8 ecn, bool trap_en, 8818 u16 trap_id) 8819 { 8820 MLXSW_REG_ZERO(tndem, payload); 8821 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 8822 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 8823 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 8824 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 8825 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 8826 } 8827 8828 /* TNPC - Tunnel Port Configuration Register 8829 * ----------------------------------------- 8830 * The TNPC register is used for tunnel port configuration. 8831 * Reserved when Spectrum. 8832 */ 8833 #define MLXSW_REG_TNPC_ID 0xA020 8834 #define MLXSW_REG_TNPC_LEN 0x18 8835 8836 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 8837 8838 enum mlxsw_reg_tnpc_tunnel_port { 8839 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 8840 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 8841 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 8842 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 8843 }; 8844 8845 /* reg_tnpc_tunnel_port 8846 * Tunnel port. 8847 * Access: Index 8848 */ 8849 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 8850 8851 /* reg_tnpc_learn_enable_v6 8852 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 8853 * Access: RW 8854 */ 8855 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 8856 8857 /* reg_tnpc_learn_enable_v4 8858 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 8859 * Access: RW 8860 */ 8861 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 8862 8863 static inline void mlxsw_reg_tnpc_pack(char *payload, 8864 enum mlxsw_reg_tnpc_tunnel_port tport, 8865 bool learn_enable) 8866 { 8867 MLXSW_REG_ZERO(tnpc, payload); 8868 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 8869 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 8870 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 8871 } 8872 8873 /* TIGCR - Tunneling IPinIP General Configuration Register 8874 * ------------------------------------------------------- 8875 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 8876 */ 8877 #define MLXSW_REG_TIGCR_ID 0xA801 8878 #define MLXSW_REG_TIGCR_LEN 0x10 8879 8880 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 8881 8882 /* reg_tigcr_ipip_ttlc 8883 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 8884 * header. 8885 * Access: RW 8886 */ 8887 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 8888 8889 /* reg_tigcr_ipip_ttl_uc 8890 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 8891 * reg_tigcr_ipip_ttlc is unset. 8892 * Access: RW 8893 */ 8894 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 8895 8896 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 8897 { 8898 MLXSW_REG_ZERO(tigcr, payload); 8899 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 8900 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 8901 } 8902 8903 /* SBPR - Shared Buffer Pools Register 8904 * ----------------------------------- 8905 * The SBPR configures and retrieves the shared buffer pools and configuration. 8906 */ 8907 #define MLXSW_REG_SBPR_ID 0xB001 8908 #define MLXSW_REG_SBPR_LEN 0x14 8909 8910 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 8911 8912 /* shared direstion enum for SBPR, SBCM, SBPM */ 8913 enum mlxsw_reg_sbxx_dir { 8914 MLXSW_REG_SBXX_DIR_INGRESS, 8915 MLXSW_REG_SBXX_DIR_EGRESS, 8916 }; 8917 8918 /* reg_sbpr_dir 8919 * Direction. 8920 * Access: Index 8921 */ 8922 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 8923 8924 /* reg_sbpr_pool 8925 * Pool index. 8926 * Access: Index 8927 */ 8928 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 8929 8930 /* reg_sbpr_infi_size 8931 * Size is infinite. 8932 * Access: RW 8933 */ 8934 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 8935 8936 /* reg_sbpr_size 8937 * Pool size in buffer cells. 8938 * Reserved when infi_size = 1. 8939 * Access: RW 8940 */ 8941 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 8942 8943 enum mlxsw_reg_sbpr_mode { 8944 MLXSW_REG_SBPR_MODE_STATIC, 8945 MLXSW_REG_SBPR_MODE_DYNAMIC, 8946 }; 8947 8948 /* reg_sbpr_mode 8949 * Pool quota calculation mode. 8950 * Access: RW 8951 */ 8952 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 8953 8954 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 8955 enum mlxsw_reg_sbxx_dir dir, 8956 enum mlxsw_reg_sbpr_mode mode, u32 size, 8957 bool infi_size) 8958 { 8959 MLXSW_REG_ZERO(sbpr, payload); 8960 mlxsw_reg_sbpr_pool_set(payload, pool); 8961 mlxsw_reg_sbpr_dir_set(payload, dir); 8962 mlxsw_reg_sbpr_mode_set(payload, mode); 8963 mlxsw_reg_sbpr_size_set(payload, size); 8964 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 8965 } 8966 8967 /* SBCM - Shared Buffer Class Management Register 8968 * ---------------------------------------------- 8969 * The SBCM register configures and retrieves the shared buffer allocation 8970 * and configuration according to Port-PG, including the binding to pool 8971 * and definition of the associated quota. 8972 */ 8973 #define MLXSW_REG_SBCM_ID 0xB002 8974 #define MLXSW_REG_SBCM_LEN 0x28 8975 8976 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 8977 8978 /* reg_sbcm_local_port 8979 * Local port number. 8980 * For Ingress: excludes CPU port and Router port 8981 * For Egress: excludes IP Router 8982 * Access: Index 8983 */ 8984 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 8985 8986 /* reg_sbcm_pg_buff 8987 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 8988 * For PG buffer: range is 0..cap_max_pg_buffers - 1 8989 * For traffic class: range is 0..cap_max_tclass - 1 8990 * Note that when traffic class is in MC aware mode then the traffic 8991 * classes which are MC aware cannot be configured. 8992 * Access: Index 8993 */ 8994 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 8995 8996 /* reg_sbcm_dir 8997 * Direction. 8998 * Access: Index 8999 */ 9000 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 9001 9002 /* reg_sbcm_min_buff 9003 * Minimum buffer size for the limiter, in cells. 9004 * Access: RW 9005 */ 9006 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 9007 9008 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 9009 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 9010 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 9011 9012 /* reg_sbcm_infi_max 9013 * Max buffer is infinite. 9014 * Access: RW 9015 */ 9016 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 9017 9018 /* reg_sbcm_max_buff 9019 * When the pool associated to the port-pg/tclass is configured to 9020 * static, Maximum buffer size for the limiter configured in cells. 9021 * When the pool associated to the port-pg/tclass is configured to 9022 * dynamic, the max_buff holds the "alpha" parameter, supporting 9023 * the following values: 9024 * 0: 0 9025 * i: (1/128)*2^(i-1), for i=1..14 9026 * 0xFF: Infinity 9027 * Reserved when infi_max = 1. 9028 * Access: RW 9029 */ 9030 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 9031 9032 /* reg_sbcm_pool 9033 * Association of the port-priority to a pool. 9034 * Access: RW 9035 */ 9036 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 9037 9038 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 9039 enum mlxsw_reg_sbxx_dir dir, 9040 u32 min_buff, u32 max_buff, 9041 bool infi_max, u8 pool) 9042 { 9043 MLXSW_REG_ZERO(sbcm, payload); 9044 mlxsw_reg_sbcm_local_port_set(payload, local_port); 9045 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 9046 mlxsw_reg_sbcm_dir_set(payload, dir); 9047 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 9048 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 9049 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 9050 mlxsw_reg_sbcm_pool_set(payload, pool); 9051 } 9052 9053 /* SBPM - Shared Buffer Port Management Register 9054 * --------------------------------------------- 9055 * The SBPM register configures and retrieves the shared buffer allocation 9056 * and configuration according to Port-Pool, including the definition 9057 * of the associated quota. 9058 */ 9059 #define MLXSW_REG_SBPM_ID 0xB003 9060 #define MLXSW_REG_SBPM_LEN 0x28 9061 9062 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 9063 9064 /* reg_sbpm_local_port 9065 * Local port number. 9066 * For Ingress: excludes CPU port and Router port 9067 * For Egress: excludes IP Router 9068 * Access: Index 9069 */ 9070 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 9071 9072 /* reg_sbpm_pool 9073 * The pool associated to quota counting on the local_port. 9074 * Access: Index 9075 */ 9076 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 9077 9078 /* reg_sbpm_dir 9079 * Direction. 9080 * Access: Index 9081 */ 9082 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 9083 9084 /* reg_sbpm_buff_occupancy 9085 * Current buffer occupancy in cells. 9086 * Access: RO 9087 */ 9088 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 9089 9090 /* reg_sbpm_clr 9091 * Clear Max Buffer Occupancy 9092 * When this bit is set, max_buff_occupancy field is cleared (and a 9093 * new max value is tracked from the time the clear was performed). 9094 * Access: OP 9095 */ 9096 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 9097 9098 /* reg_sbpm_max_buff_occupancy 9099 * Maximum value of buffer occupancy in cells monitored. Cleared by 9100 * writing to the clr field. 9101 * Access: RO 9102 */ 9103 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 9104 9105 /* reg_sbpm_min_buff 9106 * Minimum buffer size for the limiter, in cells. 9107 * Access: RW 9108 */ 9109 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 9110 9111 /* reg_sbpm_max_buff 9112 * When the pool associated to the port-pg/tclass is configured to 9113 * static, Maximum buffer size for the limiter configured in cells. 9114 * When the pool associated to the port-pg/tclass is configured to 9115 * dynamic, the max_buff holds the "alpha" parameter, supporting 9116 * the following values: 9117 * 0: 0 9118 * i: (1/128)*2^(i-1), for i=1..14 9119 * 0xFF: Infinity 9120 * Access: RW 9121 */ 9122 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 9123 9124 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 9125 enum mlxsw_reg_sbxx_dir dir, bool clr, 9126 u32 min_buff, u32 max_buff) 9127 { 9128 MLXSW_REG_ZERO(sbpm, payload); 9129 mlxsw_reg_sbpm_local_port_set(payload, local_port); 9130 mlxsw_reg_sbpm_pool_set(payload, pool); 9131 mlxsw_reg_sbpm_dir_set(payload, dir); 9132 mlxsw_reg_sbpm_clr_set(payload, clr); 9133 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 9134 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 9135 } 9136 9137 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 9138 u32 *p_max_buff_occupancy) 9139 { 9140 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 9141 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 9142 } 9143 9144 /* SBMM - Shared Buffer Multicast Management Register 9145 * -------------------------------------------------- 9146 * The SBMM register configures and retrieves the shared buffer allocation 9147 * and configuration for MC packets according to Switch-Priority, including 9148 * the binding to pool and definition of the associated quota. 9149 */ 9150 #define MLXSW_REG_SBMM_ID 0xB004 9151 #define MLXSW_REG_SBMM_LEN 0x28 9152 9153 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 9154 9155 /* reg_sbmm_prio 9156 * Switch Priority. 9157 * Access: Index 9158 */ 9159 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 9160 9161 /* reg_sbmm_min_buff 9162 * Minimum buffer size for the limiter, in cells. 9163 * Access: RW 9164 */ 9165 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 9166 9167 /* reg_sbmm_max_buff 9168 * When the pool associated to the port-pg/tclass is configured to 9169 * static, Maximum buffer size for the limiter configured in cells. 9170 * When the pool associated to the port-pg/tclass is configured to 9171 * dynamic, the max_buff holds the "alpha" parameter, supporting 9172 * the following values: 9173 * 0: 0 9174 * i: (1/128)*2^(i-1), for i=1..14 9175 * 0xFF: Infinity 9176 * Access: RW 9177 */ 9178 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 9179 9180 /* reg_sbmm_pool 9181 * Association of the port-priority to a pool. 9182 * Access: RW 9183 */ 9184 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 9185 9186 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 9187 u32 max_buff, u8 pool) 9188 { 9189 MLXSW_REG_ZERO(sbmm, payload); 9190 mlxsw_reg_sbmm_prio_set(payload, prio); 9191 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 9192 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 9193 mlxsw_reg_sbmm_pool_set(payload, pool); 9194 } 9195 9196 /* SBSR - Shared Buffer Status Register 9197 * ------------------------------------ 9198 * The SBSR register retrieves the shared buffer occupancy according to 9199 * Port-Pool. Note that this register enables reading a large amount of data. 9200 * It is the user's responsibility to limit the amount of data to ensure the 9201 * response can match the maximum transfer unit. In case the response exceeds 9202 * the maximum transport unit, it will be truncated with no special notice. 9203 */ 9204 #define MLXSW_REG_SBSR_ID 0xB005 9205 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 9206 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 9207 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 9208 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 9209 MLXSW_REG_SBSR_REC_LEN * \ 9210 MLXSW_REG_SBSR_REC_MAX_COUNT) 9211 9212 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 9213 9214 /* reg_sbsr_clr 9215 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 9216 * field is cleared (and a new max value is tracked from the time the clear 9217 * was performed). 9218 * Access: OP 9219 */ 9220 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 9221 9222 /* reg_sbsr_ingress_port_mask 9223 * Bit vector for all ingress network ports. 9224 * Indicates which of the ports (for which the relevant bit is set) 9225 * are affected by the set operation. Configuration of any other port 9226 * does not change. 9227 * Access: Index 9228 */ 9229 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 9230 9231 /* reg_sbsr_pg_buff_mask 9232 * Bit vector for all switch priority groups. 9233 * Indicates which of the priorities (for which the relevant bit is set) 9234 * are affected by the set operation. Configuration of any other priority 9235 * does not change. 9236 * Range is 0..cap_max_pg_buffers - 1 9237 * Access: Index 9238 */ 9239 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 9240 9241 /* reg_sbsr_egress_port_mask 9242 * Bit vector for all egress network ports. 9243 * Indicates which of the ports (for which the relevant bit is set) 9244 * are affected by the set operation. Configuration of any other port 9245 * does not change. 9246 * Access: Index 9247 */ 9248 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 9249 9250 /* reg_sbsr_tclass_mask 9251 * Bit vector for all traffic classes. 9252 * Indicates which of the traffic classes (for which the relevant bit is 9253 * set) are affected by the set operation. Configuration of any other 9254 * traffic class does not change. 9255 * Range is 0..cap_max_tclass - 1 9256 * Access: Index 9257 */ 9258 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 9259 9260 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 9261 { 9262 MLXSW_REG_ZERO(sbsr, payload); 9263 mlxsw_reg_sbsr_clr_set(payload, clr); 9264 } 9265 9266 /* reg_sbsr_rec_buff_occupancy 9267 * Current buffer occupancy in cells. 9268 * Access: RO 9269 */ 9270 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9271 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 9272 9273 /* reg_sbsr_rec_max_buff_occupancy 9274 * Maximum value of buffer occupancy in cells monitored. Cleared by 9275 * writing to the clr field. 9276 * Access: RO 9277 */ 9278 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9279 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 9280 9281 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 9282 u32 *p_buff_occupancy, 9283 u32 *p_max_buff_occupancy) 9284 { 9285 *p_buff_occupancy = 9286 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 9287 *p_max_buff_occupancy = 9288 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 9289 } 9290 9291 /* SBIB - Shared Buffer Internal Buffer Register 9292 * --------------------------------------------- 9293 * The SBIB register configures per port buffers for internal use. The internal 9294 * buffers consume memory on the port buffers (note that the port buffers are 9295 * used also by PBMC). 9296 * 9297 * For Spectrum this is used for egress mirroring. 9298 */ 9299 #define MLXSW_REG_SBIB_ID 0xB006 9300 #define MLXSW_REG_SBIB_LEN 0x10 9301 9302 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 9303 9304 /* reg_sbib_local_port 9305 * Local port number 9306 * Not supported for CPU port and router port 9307 * Access: Index 9308 */ 9309 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 9310 9311 /* reg_sbib_buff_size 9312 * Units represented in cells 9313 * Allowed range is 0 to (cap_max_headroom_size - 1) 9314 * Default is 0 9315 * Access: RW 9316 */ 9317 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 9318 9319 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 9320 u32 buff_size) 9321 { 9322 MLXSW_REG_ZERO(sbib, payload); 9323 mlxsw_reg_sbib_local_port_set(payload, local_port); 9324 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 9325 } 9326 9327 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 9328 MLXSW_REG(sgcr), 9329 MLXSW_REG(spad), 9330 MLXSW_REG(smid), 9331 MLXSW_REG(sspr), 9332 MLXSW_REG(sfdat), 9333 MLXSW_REG(sfd), 9334 MLXSW_REG(sfn), 9335 MLXSW_REG(spms), 9336 MLXSW_REG(spvid), 9337 MLXSW_REG(spvm), 9338 MLXSW_REG(spaft), 9339 MLXSW_REG(sfgc), 9340 MLXSW_REG(sftr), 9341 MLXSW_REG(sfdf), 9342 MLXSW_REG(sldr), 9343 MLXSW_REG(slcr), 9344 MLXSW_REG(slcor), 9345 MLXSW_REG(spmlr), 9346 MLXSW_REG(svfa), 9347 MLXSW_REG(svpe), 9348 MLXSW_REG(sfmr), 9349 MLXSW_REG(spvmlr), 9350 MLXSW_REG(cwtp), 9351 MLXSW_REG(cwtpm), 9352 MLXSW_REG(pgcr), 9353 MLXSW_REG(ppbt), 9354 MLXSW_REG(pacl), 9355 MLXSW_REG(pagt), 9356 MLXSW_REG(ptar), 9357 MLXSW_REG(ppbs), 9358 MLXSW_REG(prcr), 9359 MLXSW_REG(pefa), 9360 MLXSW_REG(ptce2), 9361 MLXSW_REG(perpt), 9362 MLXSW_REG(perar), 9363 MLXSW_REG(ptce3), 9364 MLXSW_REG(percr), 9365 MLXSW_REG(pererp), 9366 MLXSW_REG(iedr), 9367 MLXSW_REG(qpts), 9368 MLXSW_REG(qpcr), 9369 MLXSW_REG(qtct), 9370 MLXSW_REG(qeec), 9371 MLXSW_REG(qrwe), 9372 MLXSW_REG(qpdsm), 9373 MLXSW_REG(qpdpm), 9374 MLXSW_REG(qtctm), 9375 MLXSW_REG(pmlp), 9376 MLXSW_REG(pmtu), 9377 MLXSW_REG(ptys), 9378 MLXSW_REG(ppad), 9379 MLXSW_REG(paos), 9380 MLXSW_REG(pfcc), 9381 MLXSW_REG(ppcnt), 9382 MLXSW_REG(plib), 9383 MLXSW_REG(pptb), 9384 MLXSW_REG(pbmc), 9385 MLXSW_REG(pspa), 9386 MLXSW_REG(htgt), 9387 MLXSW_REG(hpkt), 9388 MLXSW_REG(rgcr), 9389 MLXSW_REG(ritr), 9390 MLXSW_REG(rtar), 9391 MLXSW_REG(ratr), 9392 MLXSW_REG(rtdp), 9393 MLXSW_REG(rdpm), 9394 MLXSW_REG(ricnt), 9395 MLXSW_REG(rrcr), 9396 MLXSW_REG(ralta), 9397 MLXSW_REG(ralst), 9398 MLXSW_REG(raltb), 9399 MLXSW_REG(ralue), 9400 MLXSW_REG(rauht), 9401 MLXSW_REG(raleu), 9402 MLXSW_REG(rauhtd), 9403 MLXSW_REG(rigr2), 9404 MLXSW_REG(recr2), 9405 MLXSW_REG(rmft2), 9406 MLXSW_REG(mfcr), 9407 MLXSW_REG(mfsc), 9408 MLXSW_REG(mfsm), 9409 MLXSW_REG(mfsl), 9410 MLXSW_REG(mtcap), 9411 MLXSW_REG(mtmp), 9412 MLXSW_REG(mcia), 9413 MLXSW_REG(mpat), 9414 MLXSW_REG(mpar), 9415 MLXSW_REG(mrsr), 9416 MLXSW_REG(mlcr), 9417 MLXSW_REG(mpsc), 9418 MLXSW_REG(mcqi), 9419 MLXSW_REG(mcc), 9420 MLXSW_REG(mcda), 9421 MLXSW_REG(mgpc), 9422 MLXSW_REG(mprs), 9423 MLXSW_REG(tngcr), 9424 MLXSW_REG(tnumt), 9425 MLXSW_REG(tnqcr), 9426 MLXSW_REG(tnqdr), 9427 MLXSW_REG(tneem), 9428 MLXSW_REG(tndem), 9429 MLXSW_REG(tnpc), 9430 MLXSW_REG(tigcr), 9431 MLXSW_REG(sbpr), 9432 MLXSW_REG(sbcm), 9433 MLXSW_REG(sbpm), 9434 MLXSW_REG(sbmm), 9435 MLXSW_REG(sbsr), 9436 MLXSW_REG(sbib), 9437 }; 9438 9439 static inline const char *mlxsw_reg_id_str(u16 reg_id) 9440 { 9441 const struct mlxsw_reg_info *reg_info; 9442 int i; 9443 9444 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 9445 reg_info = mlxsw_reg_infos[i]; 9446 if (reg_info->id == reg_id) 9447 return reg_info->name; 9448 } 9449 return "*UNKNOWN*"; 9450 } 9451 9452 /* PUDE - Port Up / Down Event 9453 * --------------------------- 9454 * Reports the operational state change of a port. 9455 */ 9456 #define MLXSW_REG_PUDE_LEN 0x10 9457 9458 /* reg_pude_swid 9459 * Switch partition ID with which to associate the port. 9460 * Access: Index 9461 */ 9462 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 9463 9464 /* reg_pude_local_port 9465 * Local port number. 9466 * Access: Index 9467 */ 9468 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 9469 9470 /* reg_pude_admin_status 9471 * Port administrative state (the desired state). 9472 * 1 - Up. 9473 * 2 - Down. 9474 * 3 - Up once. This means that in case of link failure, the port won't go 9475 * into polling mode, but will wait to be re-enabled by software. 9476 * 4 - Disabled by system. Can only be set by hardware. 9477 * Access: RO 9478 */ 9479 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 9480 9481 /* reg_pude_oper_status 9482 * Port operatioanl state. 9483 * 1 - Up. 9484 * 2 - Down. 9485 * 3 - Down by port failure. This means that the device will not let the 9486 * port up again until explicitly specified by software. 9487 * Access: RO 9488 */ 9489 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 9490 9491 #endif 9492