1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_acl_id 2203 * ACL identifier 2204 * Access: RW 2205 */ 2206 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2207 2208 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2209 { 2210 MLXSW_REG_ZERO(pagt, payload); 2211 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2212 } 2213 2214 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2215 u16 acl_id) 2216 { 2217 u8 size = mlxsw_reg_pagt_size_get(payload); 2218 2219 if (index >= size) 2220 mlxsw_reg_pagt_size_set(payload, index + 1); 2221 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2222 } 2223 2224 /* PTAR - Policy-Engine TCAM Allocation Register 2225 * --------------------------------------------- 2226 * This register is used for allocation of regions in the TCAM. 2227 * Note: Query method is not supported on this register. 2228 */ 2229 #define MLXSW_REG_PTAR_ID 0x3006 2230 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2231 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2232 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2233 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2234 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2235 2236 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2237 2238 enum mlxsw_reg_ptar_op { 2239 /* allocate a TCAM region */ 2240 MLXSW_REG_PTAR_OP_ALLOC, 2241 /* resize a TCAM region */ 2242 MLXSW_REG_PTAR_OP_RESIZE, 2243 /* deallocate TCAM region */ 2244 MLXSW_REG_PTAR_OP_FREE, 2245 /* test allocation */ 2246 MLXSW_REG_PTAR_OP_TEST, 2247 }; 2248 2249 /* reg_ptar_op 2250 * Access: OP 2251 */ 2252 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2253 2254 /* reg_ptar_action_set_type 2255 * Type of action set to be used on this region. 2256 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2257 * Access: WO 2258 */ 2259 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2260 2261 enum mlxsw_reg_ptar_key_type { 2262 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2263 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2264 }; 2265 2266 /* reg_ptar_key_type 2267 * TCAM key type for the region. 2268 * Access: WO 2269 */ 2270 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2271 2272 /* reg_ptar_region_size 2273 * TCAM region size. When allocating/resizing this is the requested size, 2274 * the response is the actual size. Note that actual size may be 2275 * larger than requested. 2276 * Allowed range 1 .. cap_max_rules-1 2277 * Reserved during op deallocate. 2278 * Access: WO 2279 */ 2280 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2281 2282 /* reg_ptar_region_id 2283 * Region identifier 2284 * Range 0 .. cap_max_regions-1 2285 * Access: Index 2286 */ 2287 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2288 2289 /* reg_ptar_tcam_region_info 2290 * Opaque object that represents the TCAM region. 2291 * Returned when allocating a region. 2292 * Provided by software for ACL generation and region deallocation and resize. 2293 * Access: RW 2294 */ 2295 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2296 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2297 2298 /* reg_ptar_flexible_key_id 2299 * Identifier of the Flexible Key. 2300 * Only valid if key_type == "FLEX_KEY" 2301 * The key size will be rounded up to one of the following values: 2302 * 9B, 18B, 36B, 54B. 2303 * This field is reserved for in resize operation. 2304 * Access: WO 2305 */ 2306 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2307 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2308 2309 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2310 enum mlxsw_reg_ptar_key_type key_type, 2311 u16 region_size, u16 region_id, 2312 const char *tcam_region_info) 2313 { 2314 MLXSW_REG_ZERO(ptar, payload); 2315 mlxsw_reg_ptar_op_set(payload, op); 2316 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2317 mlxsw_reg_ptar_key_type_set(payload, key_type); 2318 mlxsw_reg_ptar_region_size_set(payload, region_size); 2319 mlxsw_reg_ptar_region_id_set(payload, region_id); 2320 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2321 } 2322 2323 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2324 u16 key_id) 2325 { 2326 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2327 } 2328 2329 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2330 { 2331 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2332 } 2333 2334 /* PPBS - Policy-Engine Policy Based Switching Register 2335 * ---------------------------------------------------- 2336 * This register retrieves and sets Policy Based Switching Table entries. 2337 */ 2338 #define MLXSW_REG_PPBS_ID 0x300C 2339 #define MLXSW_REG_PPBS_LEN 0x14 2340 2341 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2342 2343 /* reg_ppbs_pbs_ptr 2344 * Index into the PBS table. 2345 * For Spectrum, the index points to the KVD Linear. 2346 * Access: Index 2347 */ 2348 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2349 2350 /* reg_ppbs_system_port 2351 * Unique port identifier for the final destination of the packet. 2352 * Access: RW 2353 */ 2354 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2355 2356 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2357 u16 system_port) 2358 { 2359 MLXSW_REG_ZERO(ppbs, payload); 2360 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2361 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2362 } 2363 2364 /* PRCR - Policy-Engine Rules Copy Register 2365 * ---------------------------------------- 2366 * This register is used for accessing rules within a TCAM region. 2367 */ 2368 #define MLXSW_REG_PRCR_ID 0x300D 2369 #define MLXSW_REG_PRCR_LEN 0x40 2370 2371 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2372 2373 enum mlxsw_reg_prcr_op { 2374 /* Move rules. Moves the rules from "tcam_region_info" starting 2375 * at offset "offset" to "dest_tcam_region_info" 2376 * at offset "dest_offset." 2377 */ 2378 MLXSW_REG_PRCR_OP_MOVE, 2379 /* Copy rules. Copies the rules from "tcam_region_info" starting 2380 * at offset "offset" to "dest_tcam_region_info" 2381 * at offset "dest_offset." 2382 */ 2383 MLXSW_REG_PRCR_OP_COPY, 2384 }; 2385 2386 /* reg_prcr_op 2387 * Access: OP 2388 */ 2389 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2390 2391 /* reg_prcr_offset 2392 * Offset within the source region to copy/move from. 2393 * Access: Index 2394 */ 2395 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2396 2397 /* reg_prcr_size 2398 * The number of rules to copy/move. 2399 * Access: WO 2400 */ 2401 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2402 2403 /* reg_prcr_tcam_region_info 2404 * Opaque object that represents the source TCAM region. 2405 * Access: Index 2406 */ 2407 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2408 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2409 2410 /* reg_prcr_dest_offset 2411 * Offset within the source region to copy/move to. 2412 * Access: Index 2413 */ 2414 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2415 2416 /* reg_prcr_dest_tcam_region_info 2417 * Opaque object that represents the destination TCAM region. 2418 * Access: Index 2419 */ 2420 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2421 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2422 2423 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2424 const char *src_tcam_region_info, 2425 u16 src_offset, 2426 const char *dest_tcam_region_info, 2427 u16 dest_offset, u16 size) 2428 { 2429 MLXSW_REG_ZERO(prcr, payload); 2430 mlxsw_reg_prcr_op_set(payload, op); 2431 mlxsw_reg_prcr_offset_set(payload, src_offset); 2432 mlxsw_reg_prcr_size_set(payload, size); 2433 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2434 src_tcam_region_info); 2435 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2436 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2437 dest_tcam_region_info); 2438 } 2439 2440 /* PEFA - Policy-Engine Extended Flexible Action Register 2441 * ------------------------------------------------------ 2442 * This register is used for accessing an extended flexible action entry 2443 * in the central KVD Linear Database. 2444 */ 2445 #define MLXSW_REG_PEFA_ID 0x300F 2446 #define MLXSW_REG_PEFA_LEN 0xB0 2447 2448 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2449 2450 /* reg_pefa_index 2451 * Index in the KVD Linear Centralized Database. 2452 * Access: Index 2453 */ 2454 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2455 2456 /* reg_pefa_a 2457 * Index in the KVD Linear Centralized Database. 2458 * Activity 2459 * For a new entry: set if ca=0, clear if ca=1 2460 * Set if a packet lookup has hit on the specific entry 2461 * Access: RO 2462 */ 2463 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2464 2465 /* reg_pefa_ca 2466 * Clear activity 2467 * When write: activity is according to this field 2468 * When read: after reading the activity is cleared according to ca 2469 * Access: OP 2470 */ 2471 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2472 2473 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2474 2475 /* reg_pefa_flex_action_set 2476 * Action-set to perform when rule is matched. 2477 * Must be zero padded if action set is shorter. 2478 * Access: RW 2479 */ 2480 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2481 2482 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2483 const char *flex_action_set) 2484 { 2485 MLXSW_REG_ZERO(pefa, payload); 2486 mlxsw_reg_pefa_index_set(payload, index); 2487 mlxsw_reg_pefa_ca_set(payload, ca); 2488 if (flex_action_set) 2489 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2490 flex_action_set); 2491 } 2492 2493 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2494 { 2495 *p_a = mlxsw_reg_pefa_a_get(payload); 2496 } 2497 2498 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2499 * -------------------------------------------------------------- 2500 * This register is used for binding Multicast router to an ACL group 2501 * that serves the MC router. 2502 * This register is not supported by SwitchX/-2 and Spectrum. 2503 */ 2504 #define MLXSW_REG_PEMRBT_ID 0x3014 2505 #define MLXSW_REG_PEMRBT_LEN 0x14 2506 2507 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2508 2509 enum mlxsw_reg_pemrbt_protocol { 2510 MLXSW_REG_PEMRBT_PROTO_IPV4, 2511 MLXSW_REG_PEMRBT_PROTO_IPV6, 2512 }; 2513 2514 /* reg_pemrbt_protocol 2515 * Access: Index 2516 */ 2517 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2518 2519 /* reg_pemrbt_group_id 2520 * ACL group identifier. 2521 * Range 0..cap_max_acl_groups-1 2522 * Access: RW 2523 */ 2524 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2525 2526 static inline void 2527 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2528 u16 group_id) 2529 { 2530 MLXSW_REG_ZERO(pemrbt, payload); 2531 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2532 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2533 } 2534 2535 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2536 * ----------------------------------------------------- 2537 * This register is used for accessing rules within a TCAM region. 2538 * It is a new version of PTCE in order to support wider key, 2539 * mask and action within a TCAM region. This register is not supported 2540 * by SwitchX and SwitchX-2. 2541 */ 2542 #define MLXSW_REG_PTCE2_ID 0x3017 2543 #define MLXSW_REG_PTCE2_LEN 0x1D8 2544 2545 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2546 2547 /* reg_ptce2_v 2548 * Valid. 2549 * Access: RW 2550 */ 2551 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2552 2553 /* reg_ptce2_a 2554 * Activity. Set if a packet lookup has hit on the specific entry. 2555 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2556 * Access: RO 2557 */ 2558 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2559 2560 enum mlxsw_reg_ptce2_op { 2561 /* Read operation. */ 2562 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2563 /* clear on read operation. Used to read entry 2564 * and clear Activity bit. 2565 */ 2566 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2567 /* Write operation. Used to write a new entry to the table. 2568 * All R/W fields are relevant for new entry. Activity bit is set 2569 * for new entries - Note write with v = 0 will delete the entry. 2570 */ 2571 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2572 /* Update action. Only action set will be updated. */ 2573 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2574 /* Clear activity. A bit is cleared for the entry. */ 2575 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2576 }; 2577 2578 /* reg_ptce2_op 2579 * Access: OP 2580 */ 2581 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2582 2583 /* reg_ptce2_offset 2584 * Access: Index 2585 */ 2586 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2587 2588 /* reg_ptce2_priority 2589 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2590 * Note: priority does not have to be unique per rule. 2591 * Within a region, higher priority should have lower offset (no limitation 2592 * between regions in a multi-region). 2593 * Access: RW 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2596 2597 /* reg_ptce2_tcam_region_info 2598 * Opaque object that represents the TCAM region. 2599 * Access: Index 2600 */ 2601 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2602 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2603 2604 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2605 2606 /* reg_ptce2_flex_key_blocks 2607 * ACL Key. 2608 * Access: RW 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2611 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2612 2613 /* reg_ptce2_mask 2614 * mask- in the same size as key. A bit that is set directs the TCAM 2615 * to compare the corresponding bit in key. A bit that is clear directs 2616 * the TCAM to ignore the corresponding bit in key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_flex_action_set 2623 * ACL action set. 2624 * Access: RW 2625 */ 2626 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2627 MLXSW_REG_FLEX_ACTION_SET_LEN); 2628 2629 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2630 enum mlxsw_reg_ptce2_op op, 2631 const char *tcam_region_info, 2632 u16 offset, u32 priority) 2633 { 2634 MLXSW_REG_ZERO(ptce2, payload); 2635 mlxsw_reg_ptce2_v_set(payload, valid); 2636 mlxsw_reg_ptce2_op_set(payload, op); 2637 mlxsw_reg_ptce2_offset_set(payload, offset); 2638 mlxsw_reg_ptce2_priority_set(payload, priority); 2639 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2640 } 2641 2642 /* PERPT - Policy-Engine ERP Table Register 2643 * ---------------------------------------- 2644 * This register adds and removes eRPs from the eRP table. 2645 */ 2646 #define MLXSW_REG_PERPT_ID 0x3021 2647 #define MLXSW_REG_PERPT_LEN 0x80 2648 2649 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2650 2651 /* reg_perpt_erpt_bank 2652 * eRP table bank. 2653 * Range 0 .. cap_max_erp_table_banks - 1 2654 * Access: Index 2655 */ 2656 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2657 2658 /* reg_perpt_erpt_index 2659 * Index to eRP table within the eRP bank. 2660 * Range is 0 .. cap_max_erp_table_bank_size - 1 2661 * Access: Index 2662 */ 2663 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2664 2665 enum mlxsw_reg_perpt_key_size { 2666 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2667 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2668 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2669 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2670 }; 2671 2672 /* reg_perpt_key_size 2673 * Access: OP 2674 */ 2675 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2676 2677 /* reg_perpt_bf_bypass 2678 * 0 - The eRP is used only if bloom filter state is set for the given 2679 * rule. 2680 * 1 - The eRP is used regardless of bloom filter state. 2681 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2682 * Access: RW 2683 */ 2684 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2685 2686 /* reg_perpt_erp_id 2687 * eRP ID for use by the rules. 2688 * Access: RW 2689 */ 2690 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2691 2692 /* reg_perpt_erpt_base_bank 2693 * Base eRP table bank, points to head of erp_vector 2694 * Range is 0 .. cap_max_erp_table_banks - 1 2695 * Access: OP 2696 */ 2697 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2698 2699 /* reg_perpt_erpt_base_index 2700 * Base index to eRP table within the eRP bank 2701 * Range is 0 .. cap_max_erp_table_bank_size - 1 2702 * Access: OP 2703 */ 2704 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2705 2706 /* reg_perpt_erp_index_in_vector 2707 * eRP index in the vector. 2708 * Access: OP 2709 */ 2710 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2711 2712 /* reg_perpt_erp_vector 2713 * eRP vector. 2714 * Access: OP 2715 */ 2716 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2717 2718 /* reg_perpt_mask 2719 * Mask 2720 * 0 - A-TCAM will ignore the bit in key 2721 * 1 - A-TCAM will compare the bit in key 2722 * Access: RW 2723 */ 2724 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2725 2726 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2727 unsigned long *erp_vector, 2728 unsigned long size) 2729 { 2730 unsigned long bit; 2731 2732 for_each_set_bit(bit, erp_vector, size) 2733 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2734 } 2735 2736 static inline void 2737 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2738 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2739 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2740 char *mask) 2741 { 2742 MLXSW_REG_ZERO(perpt, payload); 2743 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2744 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2745 mlxsw_reg_perpt_key_size_set(payload, key_size); 2746 mlxsw_reg_perpt_bf_bypass_set(payload, true); 2747 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2748 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2749 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2750 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2751 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2752 } 2753 2754 /* PERAR - Policy-Engine Region Association Register 2755 * ------------------------------------------------- 2756 * This register associates a hw region for region_id's. Changing on the fly 2757 * is supported by the device. 2758 */ 2759 #define MLXSW_REG_PERAR_ID 0x3026 2760 #define MLXSW_REG_PERAR_LEN 0x08 2761 2762 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2763 2764 /* reg_perar_region_id 2765 * Region identifier 2766 * Range 0 .. cap_max_regions-1 2767 * Access: Index 2768 */ 2769 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2770 2771 static inline unsigned int 2772 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2773 { 2774 return DIV_ROUND_UP(block_num, 4); 2775 } 2776 2777 /* reg_perar_hw_region 2778 * HW Region 2779 * Range 0 .. cap_max_regions-1 2780 * Default: hw_region = region_id 2781 * For a 8 key block region, 2 consecutive regions are used 2782 * For a 12 key block region, 3 consecutive regions are used 2783 * Access: RW 2784 */ 2785 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2786 2787 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2788 u16 hw_region) 2789 { 2790 MLXSW_REG_ZERO(perar, payload); 2791 mlxsw_reg_perar_region_id_set(payload, region_id); 2792 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2793 } 2794 2795 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2796 * ----------------------------------------------------- 2797 * This register is a new version of PTCE-V2 in order to support the 2798 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2799 */ 2800 #define MLXSW_REG_PTCE3_ID 0x3027 2801 #define MLXSW_REG_PTCE3_LEN 0xF0 2802 2803 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2804 2805 /* reg_ptce3_v 2806 * Valid. 2807 * Access: RW 2808 */ 2809 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2810 2811 enum mlxsw_reg_ptce3_op { 2812 /* Write operation. Used to write a new entry to the table. 2813 * All R/W fields are relevant for new entry. Activity bit is set 2814 * for new entries. Write with v = 0 will delete the entry. Must 2815 * not be used if an entry exists. 2816 */ 2817 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2818 /* Update operation */ 2819 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2820 /* Read operation */ 2821 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2822 }; 2823 2824 /* reg_ptce3_op 2825 * Access: OP 2826 */ 2827 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2828 2829 /* reg_ptce3_priority 2830 * Priority of the rule. Higher values win. 2831 * For Spectrum-2 range is 1..cap_kvd_size - 1 2832 * Note: Priority does not have to be unique per rule. 2833 * Access: RW 2834 */ 2835 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2836 2837 /* reg_ptce3_tcam_region_info 2838 * Opaque object that represents the TCAM region. 2839 * Access: Index 2840 */ 2841 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2842 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2843 2844 /* reg_ptce3_flex2_key_blocks 2845 * ACL key. The key must be masked according to eRP (if exists) or 2846 * according to master mask. 2847 * Access: Index 2848 */ 2849 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2850 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2851 2852 /* reg_ptce3_erp_id 2853 * eRP ID. 2854 * Access: Index 2855 */ 2856 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2857 2858 /* reg_ptce3_delta_start 2859 * Start point of delta_value and delta_mask, in bits. Must not exceed 2860 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2861 * Access: Index 2862 */ 2863 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2864 2865 /* reg_ptce3_delta_mask 2866 * Delta mask. 2867 * 0 - Ignore relevant bit in delta_value 2868 * 1 - Compare relevant bit in delta_value 2869 * Delta mask must not be set for reserved fields in the key blocks. 2870 * Note: No delta when no eRPs. Thus, for regions with 2871 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2872 * Access: Index 2873 */ 2874 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2875 2876 /* reg_ptce3_delta_value 2877 * Delta value. 2878 * Bits which are masked by delta_mask must be 0. 2879 * Access: Index 2880 */ 2881 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2882 2883 /* reg_ptce3_prune_vector 2884 * Pruning vector relative to the PERPT.erp_id. 2885 * Used for reducing lookups. 2886 * 0 - NEED: Do a lookup using the eRP. 2887 * 1 - PRUNE: Do not perform a lookup using the eRP. 2888 * Maybe be modified by PEAPBL and PEAPBM. 2889 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2890 * all 1's or all 0's. 2891 * Access: RW 2892 */ 2893 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2894 2895 /* reg_ptce3_prune_ctcam 2896 * Pruning on C-TCAM. Used for reducing lookups. 2897 * 0 - NEED: Do a lookup in the C-TCAM. 2898 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2899 * Access: RW 2900 */ 2901 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2902 2903 /* reg_ptce3_large_exists 2904 * Large entry key ID exists. 2905 * Within the region: 2906 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2907 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2908 * For rule delete: The MSB of the key will be removed. 2909 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2910 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2911 * For rule delete: The MSB of the key will not be removed. 2912 * Access: WO 2913 */ 2914 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2915 2916 /* reg_ptce3_large_entry_key_id 2917 * Large entry key ID. 2918 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2919 * blocks. Must be different for different keys which have the same common 2920 * 6 key blocks (MSB, blocks 6..11) key within a region. 2921 * Range is 0..cap_max_pe_large_key_id - 1 2922 * Access: RW 2923 */ 2924 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2925 2926 /* reg_ptce3_action_pointer 2927 * Pointer to action. 2928 * Range is 0..cap_max_kvd_action_sets - 1 2929 * Access: RW 2930 */ 2931 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2932 2933 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2934 enum mlxsw_reg_ptce3_op op, 2935 u32 priority, 2936 const char *tcam_region_info, 2937 const char *key, u8 erp_id, 2938 u16 delta_start, u8 delta_mask, 2939 u8 delta_value, bool large_exists, 2940 u32 lkey_id, u32 action_pointer) 2941 { 2942 MLXSW_REG_ZERO(ptce3, payload); 2943 mlxsw_reg_ptce3_v_set(payload, valid); 2944 mlxsw_reg_ptce3_op_set(payload, op); 2945 mlxsw_reg_ptce3_priority_set(payload, priority); 2946 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2947 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2948 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2949 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2950 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2951 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2952 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2953 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2954 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2955 } 2956 2957 /* PERCR - Policy-Engine Region Configuration Register 2958 * --------------------------------------------------- 2959 * This register configures the region parameters. The region_id must be 2960 * allocated. 2961 */ 2962 #define MLXSW_REG_PERCR_ID 0x302A 2963 #define MLXSW_REG_PERCR_LEN 0x80 2964 2965 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2966 2967 /* reg_percr_region_id 2968 * Region identifier. 2969 * Range 0..cap_max_regions-1 2970 * Access: Index 2971 */ 2972 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2973 2974 /* reg_percr_atcam_ignore_prune 2975 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2976 * Access: RW 2977 */ 2978 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2979 2980 /* reg_percr_ctcam_ignore_prune 2981 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2982 * Access: RW 2983 */ 2984 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2985 2986 /* reg_percr_bf_bypass 2987 * Bloom filter bypass. 2988 * 0 - Bloom filter is used (default) 2989 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2990 * region_id or eRP. See PERPT.bf_bypass 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 2994 2995 /* reg_percr_master_mask 2996 * Master mask. Logical OR mask of all masks of all rules of a region 2997 * (both A-TCAM and C-TCAM). When there are no eRPs 2998 * (erpt_pointer_valid = 0), then this provides the mask. 2999 * Access: RW 3000 */ 3001 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3002 3003 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3004 { 3005 MLXSW_REG_ZERO(percr, payload); 3006 mlxsw_reg_percr_region_id_set(payload, region_id); 3007 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3008 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3009 mlxsw_reg_percr_bf_bypass_set(payload, true); 3010 } 3011 3012 /* PERERP - Policy-Engine Region eRP Register 3013 * ------------------------------------------ 3014 * This register configures the region eRP. The region_id must be 3015 * allocated. 3016 */ 3017 #define MLXSW_REG_PERERP_ID 0x302B 3018 #define MLXSW_REG_PERERP_LEN 0x1C 3019 3020 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3021 3022 /* reg_pererp_region_id 3023 * Region identifier. 3024 * Range 0..cap_max_regions-1 3025 * Access: Index 3026 */ 3027 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3028 3029 /* reg_pererp_ctcam_le 3030 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3031 * Access: RW 3032 */ 3033 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3034 3035 /* reg_pererp_erpt_pointer_valid 3036 * erpt_pointer is valid. 3037 * Access: RW 3038 */ 3039 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3040 3041 /* reg_pererp_erpt_bank_pointer 3042 * Pointer to eRP table bank. May be modified at any time. 3043 * Range 0..cap_max_erp_table_banks-1 3044 * Reserved when erpt_pointer_valid = 0 3045 */ 3046 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3047 3048 /* reg_pererp_erpt_pointer 3049 * Pointer to eRP table within the eRP bank. Can be changed for an 3050 * existing region. 3051 * Range 0..cap_max_erp_table_size-1 3052 * Reserved when erpt_pointer_valid = 0 3053 * Access: RW 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3056 3057 /* reg_pererp_erpt_vector 3058 * Vector of allowed eRP indexes starting from erpt_pointer within the 3059 * erpt_bank_pointer. Next entries will be in next bank. 3060 * Note that eRP index is used and not eRP ID. 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3065 3066 /* reg_pererp_master_rp_id 3067 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3068 * for the lookup. Can be changed for an existing region. 3069 * Reserved when erpt_pointer_valid = 1 3070 * Access: RW 3071 */ 3072 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3073 3074 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3075 unsigned long *erp_vector, 3076 unsigned long size) 3077 { 3078 unsigned long bit; 3079 3080 for_each_set_bit(bit, erp_vector, size) 3081 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3082 } 3083 3084 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3085 bool ctcam_le, bool erpt_pointer_valid, 3086 u8 erpt_bank_pointer, u8 erpt_pointer, 3087 u8 master_rp_id) 3088 { 3089 MLXSW_REG_ZERO(pererp, payload); 3090 mlxsw_reg_pererp_region_id_set(payload, region_id); 3091 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3092 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3093 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3094 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3095 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3096 } 3097 3098 /* IEDR - Infrastructure Entry Delete Register 3099 * ---------------------------------------------------- 3100 * This register is used for deleting entries from the entry tables. 3101 * It is legitimate to attempt to delete a nonexisting entry (the device will 3102 * respond as a good flow). 3103 */ 3104 #define MLXSW_REG_IEDR_ID 0x3804 3105 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3106 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3107 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3108 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3109 MLXSW_REG_IEDR_REC_LEN * \ 3110 MLXSW_REG_IEDR_REC_MAX_COUNT) 3111 3112 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3113 3114 /* reg_iedr_num_rec 3115 * Number of records. 3116 * Access: OP 3117 */ 3118 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3119 3120 /* reg_iedr_rec_type 3121 * Resource type. 3122 * Access: OP 3123 */ 3124 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3125 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3126 3127 /* reg_iedr_rec_size 3128 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3129 * Access: OP 3130 */ 3131 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3132 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3133 3134 /* reg_iedr_rec_index_start 3135 * Resource index start. 3136 * Access: OP 3137 */ 3138 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3139 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3140 3141 static inline void mlxsw_reg_iedr_pack(char *payload) 3142 { 3143 MLXSW_REG_ZERO(iedr, payload); 3144 } 3145 3146 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3147 u8 rec_type, u16 rec_size, 3148 u32 rec_index_start) 3149 { 3150 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3151 3152 if (rec_index >= num_rec) 3153 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3154 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3155 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3156 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3157 } 3158 3159 /* QPTS - QoS Priority Trust State Register 3160 * ---------------------------------------- 3161 * This register controls the port policy to calculate the switch priority and 3162 * packet color based on incoming packet fields. 3163 */ 3164 #define MLXSW_REG_QPTS_ID 0x4002 3165 #define MLXSW_REG_QPTS_LEN 0x8 3166 3167 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3168 3169 /* reg_qpts_local_port 3170 * Local port number. 3171 * Access: Index 3172 * 3173 * Note: CPU port is supported. 3174 */ 3175 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3176 3177 enum mlxsw_reg_qpts_trust_state { 3178 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3179 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3180 }; 3181 3182 /* reg_qpts_trust_state 3183 * Trust state for a given port. 3184 * Access: RW 3185 */ 3186 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3187 3188 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3189 enum mlxsw_reg_qpts_trust_state ts) 3190 { 3191 MLXSW_REG_ZERO(qpts, payload); 3192 3193 mlxsw_reg_qpts_local_port_set(payload, local_port); 3194 mlxsw_reg_qpts_trust_state_set(payload, ts); 3195 } 3196 3197 /* QPCR - QoS Policer Configuration Register 3198 * ----------------------------------------- 3199 * The QPCR register is used to create policers - that limit 3200 * the rate of bytes or packets via some trap group. 3201 */ 3202 #define MLXSW_REG_QPCR_ID 0x4004 3203 #define MLXSW_REG_QPCR_LEN 0x28 3204 3205 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3206 3207 enum mlxsw_reg_qpcr_g { 3208 MLXSW_REG_QPCR_G_GLOBAL = 2, 3209 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3210 }; 3211 3212 /* reg_qpcr_g 3213 * The policer type. 3214 * Access: Index 3215 */ 3216 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3217 3218 /* reg_qpcr_pid 3219 * Policer ID. 3220 * Access: Index 3221 */ 3222 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3223 3224 /* reg_qpcr_color_aware 3225 * Is the policer aware of colors. 3226 * Must be 0 (unaware) for cpu port. 3227 * Access: RW for unbounded policer. RO for bounded policer. 3228 */ 3229 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3230 3231 /* reg_qpcr_bytes 3232 * Is policer limit is for bytes per sec or packets per sec. 3233 * 0 - packets 3234 * 1 - bytes 3235 * Access: RW for unbounded policer. RO for bounded policer. 3236 */ 3237 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3238 3239 enum mlxsw_reg_qpcr_ir_units { 3240 MLXSW_REG_QPCR_IR_UNITS_M, 3241 MLXSW_REG_QPCR_IR_UNITS_K, 3242 }; 3243 3244 /* reg_qpcr_ir_units 3245 * Policer's units for cir and eir fields (for bytes limits only) 3246 * 1 - 10^3 3247 * 0 - 10^6 3248 * Access: OP 3249 */ 3250 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3251 3252 enum mlxsw_reg_qpcr_rate_type { 3253 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3254 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3255 }; 3256 3257 /* reg_qpcr_rate_type 3258 * Policer can have one limit (single rate) or 2 limits with specific operation 3259 * for packets that exceed the lower rate but not the upper one. 3260 * (For cpu port must be single rate) 3261 * Access: RW for unbounded policer. RO for bounded policer. 3262 */ 3263 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3264 3265 /* reg_qpc_cbs 3266 * Policer's committed burst size. 3267 * The policer is working with time slices of 50 nano sec. By default every 3268 * slice is granted the proportionate share of the committed rate. If we want to 3269 * allow a slice to exceed that share (while still keeping the rate per sec) we 3270 * can allow burst. The burst size is between the default proportionate share 3271 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3272 * committed rate will result in exceeding the rate). The burst size must be a 3273 * log of 2 and will be determined by 2^cbs. 3274 * Access: RW 3275 */ 3276 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3277 3278 /* reg_qpcr_cir 3279 * Policer's committed rate. 3280 * The rate used for sungle rate, the lower rate for double rate. 3281 * For bytes limits, the rate will be this value * the unit from ir_units. 3282 * (Resolution error is up to 1%). 3283 * Access: RW 3284 */ 3285 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3286 3287 /* reg_qpcr_eir 3288 * Policer's exceed rate. 3289 * The higher rate for double rate, reserved for single rate. 3290 * Lower rate for double rate policer. 3291 * For bytes limits, the rate will be this value * the unit from ir_units. 3292 * (Resolution error is up to 1%). 3293 * Access: RW 3294 */ 3295 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3296 3297 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3298 3299 /* reg_qpcr_exceed_action. 3300 * What to do with packets between the 2 limits for double rate. 3301 * Access: RW for unbounded policer. RO for bounded policer. 3302 */ 3303 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3304 3305 enum mlxsw_reg_qpcr_action { 3306 /* Discard */ 3307 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3308 /* Forward and set color to red. 3309 * If the packet is intended to cpu port, it will be dropped. 3310 */ 3311 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3312 }; 3313 3314 /* reg_qpcr_violate_action 3315 * What to do with packets that cross the cir limit (for single rate) or the eir 3316 * limit (for double rate). 3317 * Access: RW for unbounded policer. RO for bounded policer. 3318 */ 3319 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3320 3321 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3322 enum mlxsw_reg_qpcr_ir_units ir_units, 3323 bool bytes, u32 cir, u16 cbs) 3324 { 3325 MLXSW_REG_ZERO(qpcr, payload); 3326 mlxsw_reg_qpcr_pid_set(payload, pid); 3327 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3328 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3329 mlxsw_reg_qpcr_violate_action_set(payload, 3330 MLXSW_REG_QPCR_ACTION_DISCARD); 3331 mlxsw_reg_qpcr_cir_set(payload, cir); 3332 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3333 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3334 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3335 } 3336 3337 /* QTCT - QoS Switch Traffic Class Table 3338 * ------------------------------------- 3339 * Configures the mapping between the packet switch priority and the 3340 * traffic class on the transmit port. 3341 */ 3342 #define MLXSW_REG_QTCT_ID 0x400A 3343 #define MLXSW_REG_QTCT_LEN 0x08 3344 3345 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3346 3347 /* reg_qtct_local_port 3348 * Local port number. 3349 * Access: Index 3350 * 3351 * Note: CPU port is not supported. 3352 */ 3353 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3354 3355 /* reg_qtct_sub_port 3356 * Virtual port within the physical port. 3357 * Should be set to 0 when virtual ports are not enabled on the port. 3358 * Access: Index 3359 */ 3360 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3361 3362 /* reg_qtct_switch_prio 3363 * Switch priority. 3364 * Access: Index 3365 */ 3366 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3367 3368 /* reg_qtct_tclass 3369 * Traffic class. 3370 * Default values: 3371 * switch_prio 0 : tclass 1 3372 * switch_prio 1 : tclass 0 3373 * switch_prio i : tclass i, for i > 1 3374 * Access: RW 3375 */ 3376 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3377 3378 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3379 u8 switch_prio, u8 tclass) 3380 { 3381 MLXSW_REG_ZERO(qtct, payload); 3382 mlxsw_reg_qtct_local_port_set(payload, local_port); 3383 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3384 mlxsw_reg_qtct_tclass_set(payload, tclass); 3385 } 3386 3387 /* QEEC - QoS ETS Element Configuration Register 3388 * --------------------------------------------- 3389 * Configures the ETS elements. 3390 */ 3391 #define MLXSW_REG_QEEC_ID 0x400D 3392 #define MLXSW_REG_QEEC_LEN 0x20 3393 3394 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3395 3396 /* reg_qeec_local_port 3397 * Local port number. 3398 * Access: Index 3399 * 3400 * Note: CPU port is supported. 3401 */ 3402 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3403 3404 enum mlxsw_reg_qeec_hr { 3405 MLXSW_REG_QEEC_HIERARCY_PORT, 3406 MLXSW_REG_QEEC_HIERARCY_GROUP, 3407 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3408 MLXSW_REG_QEEC_HIERARCY_TC, 3409 }; 3410 3411 /* reg_qeec_element_hierarchy 3412 * 0 - Port 3413 * 1 - Group 3414 * 2 - Subgroup 3415 * 3 - Traffic Class 3416 * Access: Index 3417 */ 3418 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3419 3420 /* reg_qeec_element_index 3421 * The index of the element in the hierarchy. 3422 * Access: Index 3423 */ 3424 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3425 3426 /* reg_qeec_next_element_index 3427 * The index of the next (lower) element in the hierarchy. 3428 * Access: RW 3429 * 3430 * Note: Reserved for element_hierarchy 0. 3431 */ 3432 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3433 3434 /* reg_qeec_mise 3435 * Min shaper configuration enable. Enables configuration of the min 3436 * shaper on this ETS element 3437 * 0 - Disable 3438 * 1 - Enable 3439 * Access: RW 3440 */ 3441 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3442 3443 enum { 3444 MLXSW_REG_QEEC_BYTES_MODE, 3445 MLXSW_REG_QEEC_PACKETS_MODE, 3446 }; 3447 3448 /* reg_qeec_pb 3449 * Packets or bytes mode. 3450 * 0 - Bytes mode 3451 * 1 - Packets mode 3452 * Access: RW 3453 * 3454 * Note: Used for max shaper configuration. For Spectrum, packets mode 3455 * is supported only for traffic classes of CPU port. 3456 */ 3457 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3458 3459 /* The smallest permitted min shaper rate. */ 3460 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3461 3462 /* reg_qeec_min_shaper_rate 3463 * Min shaper information rate. 3464 * For CPU port, can only be configured for port hierarchy. 3465 * When in bytes mode, value is specified in units of 1000bps. 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3469 3470 /* reg_qeec_mase 3471 * Max shaper configuration enable. Enables configuration of the max 3472 * shaper on this ETS element. 3473 * 0 - Disable 3474 * 1 - Enable 3475 * Access: RW 3476 */ 3477 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3478 3479 /* A large max rate will disable the max shaper. */ 3480 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3481 3482 /* reg_qeec_max_shaper_rate 3483 * Max shaper information rate. 3484 * For CPU port, can only be configured for port hierarchy. 3485 * When in bytes mode, value is specified in units of 1000bps. 3486 * Access: RW 3487 */ 3488 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3489 3490 /* reg_qeec_de 3491 * DWRR configuration enable. Enables configuration of the dwrr and 3492 * dwrr_weight. 3493 * 0 - Disable 3494 * 1 - Enable 3495 * Access: RW 3496 */ 3497 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3498 3499 /* reg_qeec_dwrr 3500 * Transmission selection algorithm to use on the link going down from 3501 * the ETS element. 3502 * 0 - Strict priority 3503 * 1 - DWRR 3504 * Access: RW 3505 */ 3506 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3507 3508 /* reg_qeec_dwrr_weight 3509 * DWRR weight on the link going down from the ETS element. The 3510 * percentage of bandwidth guaranteed to an ETS element within 3511 * its hierarchy. The sum of all weights across all ETS elements 3512 * within one hierarchy should be equal to 100. Reserved when 3513 * transmission selection algorithm is strict priority. 3514 * Access: RW 3515 */ 3516 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3517 3518 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3519 enum mlxsw_reg_qeec_hr hr, u8 index, 3520 u8 next_index) 3521 { 3522 MLXSW_REG_ZERO(qeec, payload); 3523 mlxsw_reg_qeec_local_port_set(payload, local_port); 3524 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3525 mlxsw_reg_qeec_element_index_set(payload, index); 3526 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3527 } 3528 3529 /* QRWE - QoS ReWrite Enable 3530 * ------------------------- 3531 * This register configures the rewrite enable per receive port. 3532 */ 3533 #define MLXSW_REG_QRWE_ID 0x400F 3534 #define MLXSW_REG_QRWE_LEN 0x08 3535 3536 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3537 3538 /* reg_qrwe_local_port 3539 * Local port number. 3540 * Access: Index 3541 * 3542 * Note: CPU port is supported. No support for router port. 3543 */ 3544 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3545 3546 /* reg_qrwe_dscp 3547 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3548 * Access: RW 3549 */ 3550 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3551 3552 /* reg_qrwe_pcp 3553 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3554 * Access: RW 3555 */ 3556 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3557 3558 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3559 bool rewrite_pcp, bool rewrite_dscp) 3560 { 3561 MLXSW_REG_ZERO(qrwe, payload); 3562 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3563 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3564 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3565 } 3566 3567 /* QPDSM - QoS Priority to DSCP Mapping 3568 * ------------------------------------ 3569 * QoS Priority to DSCP Mapping Register 3570 */ 3571 #define MLXSW_REG_QPDSM_ID 0x4011 3572 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3573 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3574 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3575 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3576 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3577 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3578 3579 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3580 3581 /* reg_qpdsm_local_port 3582 * Local Port. Supported for data packets from CPU port. 3583 * Access: Index 3584 */ 3585 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3586 3587 /* reg_qpdsm_prio_entry_color0_e 3588 * Enable update of the entry for color 0 and a given port. 3589 * Access: WO 3590 */ 3591 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3592 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3593 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3594 3595 /* reg_qpdsm_prio_entry_color0_dscp 3596 * DSCP field in the outer label of the packet for color 0 and a given port. 3597 * Reserved when e=0. 3598 * Access: RW 3599 */ 3600 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3601 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3602 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3603 3604 /* reg_qpdsm_prio_entry_color1_e 3605 * Enable update of the entry for color 1 and a given port. 3606 * Access: WO 3607 */ 3608 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3609 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3610 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3611 3612 /* reg_qpdsm_prio_entry_color1_dscp 3613 * DSCP field in the outer label of the packet for color 1 and a given port. 3614 * Reserved when e=0. 3615 * Access: RW 3616 */ 3617 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3618 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3619 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3620 3621 /* reg_qpdsm_prio_entry_color2_e 3622 * Enable update of the entry for color 2 and a given port. 3623 * Access: WO 3624 */ 3625 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3626 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3627 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3628 3629 /* reg_qpdsm_prio_entry_color2_dscp 3630 * DSCP field in the outer label of the packet for color 2 and a given port. 3631 * Reserved when e=0. 3632 * Access: RW 3633 */ 3634 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3635 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3636 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3637 3638 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3639 { 3640 MLXSW_REG_ZERO(qpdsm, payload); 3641 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3642 } 3643 3644 static inline void 3645 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3646 { 3647 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3648 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3649 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3650 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3651 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3652 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3653 } 3654 3655 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3656 * -------------------------------------------------- 3657 * This register controls the mapping from DSCP field to 3658 * Switch Priority for IP packets. 3659 */ 3660 #define MLXSW_REG_QPDPM_ID 0x4013 3661 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3662 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3663 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3664 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3665 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3666 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3667 3668 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3669 3670 /* reg_qpdpm_local_port 3671 * Local Port. Supported for data packets from CPU port. 3672 * Access: Index 3673 */ 3674 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3675 3676 /* reg_qpdpm_dscp_e 3677 * Enable update of the specific entry. When cleared, the switch_prio and color 3678 * fields are ignored and the previous switch_prio and color values are 3679 * preserved. 3680 * Access: WO 3681 */ 3682 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3683 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3684 3685 /* reg_qpdpm_dscp_prio 3686 * The new Switch Priority value for the relevant DSCP value. 3687 * Access: RW 3688 */ 3689 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3690 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3691 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3692 3693 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3694 { 3695 MLXSW_REG_ZERO(qpdpm, payload); 3696 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3697 } 3698 3699 static inline void 3700 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3701 { 3702 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3703 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3704 } 3705 3706 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3707 * ------------------------------------------------------------------ 3708 * This register configures if the Switch Priority to Traffic Class mapping is 3709 * based on Multicast packet indication. If so, then multicast packets will get 3710 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3711 * QTCT. 3712 * By default, Switch Priority to Traffic Class mapping is not based on 3713 * Multicast packet indication. 3714 */ 3715 #define MLXSW_REG_QTCTM_ID 0x401A 3716 #define MLXSW_REG_QTCTM_LEN 0x08 3717 3718 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3719 3720 /* reg_qtctm_local_port 3721 * Local port number. 3722 * No support for CPU port. 3723 * Access: Index 3724 */ 3725 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3726 3727 /* reg_qtctm_mc 3728 * Multicast Mode 3729 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3730 * indication (default is 0, not based on Multicast packet indication). 3731 */ 3732 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3733 3734 static inline void 3735 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3736 { 3737 MLXSW_REG_ZERO(qtctm, payload); 3738 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3739 mlxsw_reg_qtctm_mc_set(payload, mc); 3740 } 3741 3742 /* PMLP - Ports Module to Local Port Register 3743 * ------------------------------------------ 3744 * Configures the assignment of modules to local ports. 3745 */ 3746 #define MLXSW_REG_PMLP_ID 0x5002 3747 #define MLXSW_REG_PMLP_LEN 0x40 3748 3749 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3750 3751 /* reg_pmlp_rxtx 3752 * 0 - Tx value is used for both Tx and Rx. 3753 * 1 - Rx value is taken from a separte field. 3754 * Access: RW 3755 */ 3756 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3757 3758 /* reg_pmlp_local_port 3759 * Local port number. 3760 * Access: Index 3761 */ 3762 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3763 3764 /* reg_pmlp_width 3765 * 0 - Unmap local port. 3766 * 1 - Lane 0 is used. 3767 * 2 - Lanes 0 and 1 are used. 3768 * 4 - Lanes 0, 1, 2 and 3 are used. 3769 * Access: RW 3770 */ 3771 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3772 3773 /* reg_pmlp_module 3774 * Module number. 3775 * Access: RW 3776 */ 3777 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3778 3779 /* reg_pmlp_tx_lane 3780 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3781 * Access: RW 3782 */ 3783 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3784 3785 /* reg_pmlp_rx_lane 3786 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3787 * equal to Tx lane. 3788 * Access: RW 3789 */ 3790 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3791 3792 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3793 { 3794 MLXSW_REG_ZERO(pmlp, payload); 3795 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3796 } 3797 3798 /* PMTU - Port MTU Register 3799 * ------------------------ 3800 * Configures and reports the port MTU. 3801 */ 3802 #define MLXSW_REG_PMTU_ID 0x5003 3803 #define MLXSW_REG_PMTU_LEN 0x10 3804 3805 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3806 3807 /* reg_pmtu_local_port 3808 * Local port number. 3809 * Access: Index 3810 */ 3811 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3812 3813 /* reg_pmtu_max_mtu 3814 * Maximum MTU. 3815 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3816 * reported, otherwise the minimum between the max_mtu of the different 3817 * types is reported. 3818 * Access: RO 3819 */ 3820 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3821 3822 /* reg_pmtu_admin_mtu 3823 * MTU value to set port to. Must be smaller or equal to max_mtu. 3824 * Note: If port type is Infiniband, then port must be disabled, when its 3825 * MTU is set. 3826 * Access: RW 3827 */ 3828 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3829 3830 /* reg_pmtu_oper_mtu 3831 * The actual MTU configured on the port. Packets exceeding this size 3832 * will be dropped. 3833 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3834 * oper_mtu might be smaller than admin_mtu. 3835 * Access: RO 3836 */ 3837 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3838 3839 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3840 u16 new_mtu) 3841 { 3842 MLXSW_REG_ZERO(pmtu, payload); 3843 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3844 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3845 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3846 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3847 } 3848 3849 /* PTYS - Port Type and Speed Register 3850 * ----------------------------------- 3851 * Configures and reports the port speed type. 3852 * 3853 * Note: When set while the link is up, the changes will not take effect 3854 * until the port transitions from down to up state. 3855 */ 3856 #define MLXSW_REG_PTYS_ID 0x5004 3857 #define MLXSW_REG_PTYS_LEN 0x40 3858 3859 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3860 3861 /* an_disable_admin 3862 * Auto negotiation disable administrative configuration 3863 * 0 - Device doesn't support AN disable. 3864 * 1 - Device supports AN disable. 3865 * Access: RW 3866 */ 3867 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3868 3869 /* reg_ptys_local_port 3870 * Local port number. 3871 * Access: Index 3872 */ 3873 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3874 3875 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3876 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3877 3878 /* reg_ptys_proto_mask 3879 * Protocol mask. Indicates which protocol is used. 3880 * 0 - Infiniband. 3881 * 1 - Fibre Channel. 3882 * 2 - Ethernet. 3883 * Access: Index 3884 */ 3885 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3886 3887 enum { 3888 MLXSW_REG_PTYS_AN_STATUS_NA, 3889 MLXSW_REG_PTYS_AN_STATUS_OK, 3890 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3891 }; 3892 3893 /* reg_ptys_an_status 3894 * Autonegotiation status. 3895 * Access: RO 3896 */ 3897 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3898 3899 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3900 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3901 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3902 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3903 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3904 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3905 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3906 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3907 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3908 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3909 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3910 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3911 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3912 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3913 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3914 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3915 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3916 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3917 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3918 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3919 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3920 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3921 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3922 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3923 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3924 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 3925 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 3926 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 3927 3928 /* reg_ptys_eth_proto_cap 3929 * Ethernet port supported speeds and protocols. 3930 * Access: RO 3931 */ 3932 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 3933 3934 /* reg_ptys_ib_link_width_cap 3935 * IB port supported widths. 3936 * Access: RO 3937 */ 3938 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 3939 3940 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 3941 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 3942 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 3943 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 3944 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 3945 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 3946 3947 /* reg_ptys_ib_proto_cap 3948 * IB port supported speeds and protocols. 3949 * Access: RO 3950 */ 3951 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 3952 3953 /* reg_ptys_eth_proto_admin 3954 * Speed and protocol to set port to. 3955 * Access: RW 3956 */ 3957 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 3958 3959 /* reg_ptys_ib_link_width_admin 3960 * IB width to set port to. 3961 * Access: RW 3962 */ 3963 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 3964 3965 /* reg_ptys_ib_proto_admin 3966 * IB speeds and protocols to set port to. 3967 * Access: RW 3968 */ 3969 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 3970 3971 /* reg_ptys_eth_proto_oper 3972 * The current speed and protocol configured for the port. 3973 * Access: RO 3974 */ 3975 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 3976 3977 /* reg_ptys_ib_link_width_oper 3978 * The current IB width to set port to. 3979 * Access: RO 3980 */ 3981 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 3982 3983 /* reg_ptys_ib_proto_oper 3984 * The current IB speed and protocol. 3985 * Access: RO 3986 */ 3987 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 3988 3989 /* reg_ptys_eth_proto_lp_advertise 3990 * The protocols that were advertised by the link partner during 3991 * autonegotiation. 3992 * Access: RO 3993 */ 3994 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 3995 3996 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 3997 u32 proto_admin, bool autoneg) 3998 { 3999 MLXSW_REG_ZERO(ptys, payload); 4000 mlxsw_reg_ptys_local_port_set(payload, local_port); 4001 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4002 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4003 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4004 } 4005 4006 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4007 u32 *p_eth_proto_cap, 4008 u32 *p_eth_proto_adm, 4009 u32 *p_eth_proto_oper) 4010 { 4011 if (p_eth_proto_cap) 4012 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 4013 if (p_eth_proto_adm) 4014 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 4015 if (p_eth_proto_oper) 4016 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 4017 } 4018 4019 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4020 u16 proto_admin, u16 link_width) 4021 { 4022 MLXSW_REG_ZERO(ptys, payload); 4023 mlxsw_reg_ptys_local_port_set(payload, local_port); 4024 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4025 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4026 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4027 } 4028 4029 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4030 u16 *p_ib_link_width_cap, 4031 u16 *p_ib_proto_oper, 4032 u16 *p_ib_link_width_oper) 4033 { 4034 if (p_ib_proto_cap) 4035 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4036 if (p_ib_link_width_cap) 4037 *p_ib_link_width_cap = 4038 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4039 if (p_ib_proto_oper) 4040 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4041 if (p_ib_link_width_oper) 4042 *p_ib_link_width_oper = 4043 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4044 } 4045 4046 /* PPAD - Port Physical Address Register 4047 * ------------------------------------- 4048 * The PPAD register configures the per port physical MAC address. 4049 */ 4050 #define MLXSW_REG_PPAD_ID 0x5005 4051 #define MLXSW_REG_PPAD_LEN 0x10 4052 4053 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4054 4055 /* reg_ppad_single_base_mac 4056 * 0: base_mac, local port should be 0 and mac[7:0] is 4057 * reserved. HW will set incremental 4058 * 1: single_mac - mac of the local_port 4059 * Access: RW 4060 */ 4061 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4062 4063 /* reg_ppad_local_port 4064 * port number, if single_base_mac = 0 then local_port is reserved 4065 * Access: RW 4066 */ 4067 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4068 4069 /* reg_ppad_mac 4070 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4071 * If single_base_mac = 1 - the per port MAC address 4072 * Access: RW 4073 */ 4074 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4075 4076 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4077 u8 local_port) 4078 { 4079 MLXSW_REG_ZERO(ppad, payload); 4080 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4081 mlxsw_reg_ppad_local_port_set(payload, local_port); 4082 } 4083 4084 /* PAOS - Ports Administrative and Operational Status Register 4085 * ----------------------------------------------------------- 4086 * Configures and retrieves per port administrative and operational status. 4087 */ 4088 #define MLXSW_REG_PAOS_ID 0x5006 4089 #define MLXSW_REG_PAOS_LEN 0x10 4090 4091 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4092 4093 /* reg_paos_swid 4094 * Switch partition ID with which to associate the port. 4095 * Note: while external ports uses unique local port numbers (and thus swid is 4096 * redundant), router ports use the same local port number where swid is the 4097 * only indication for the relevant port. 4098 * Access: Index 4099 */ 4100 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4101 4102 /* reg_paos_local_port 4103 * Local port number. 4104 * Access: Index 4105 */ 4106 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4107 4108 /* reg_paos_admin_status 4109 * Port administrative state (the desired state of the port): 4110 * 1 - Up. 4111 * 2 - Down. 4112 * 3 - Up once. This means that in case of link failure, the port won't go 4113 * into polling mode, but will wait to be re-enabled by software. 4114 * 4 - Disabled by system. Can only be set by hardware. 4115 * Access: RW 4116 */ 4117 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4118 4119 /* reg_paos_oper_status 4120 * Port operational state (the current state): 4121 * 1 - Up. 4122 * 2 - Down. 4123 * 3 - Down by port failure. This means that the device will not let the 4124 * port up again until explicitly specified by software. 4125 * Access: RO 4126 */ 4127 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4128 4129 /* reg_paos_ase 4130 * Admin state update enabled. 4131 * Access: WO 4132 */ 4133 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4134 4135 /* reg_paos_ee 4136 * Event update enable. If this bit is set, event generation will be 4137 * updated based on the e field. 4138 * Access: WO 4139 */ 4140 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4141 4142 /* reg_paos_e 4143 * Event generation on operational state change: 4144 * 0 - Do not generate event. 4145 * 1 - Generate Event. 4146 * 2 - Generate Single Event. 4147 * Access: RW 4148 */ 4149 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4150 4151 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4152 enum mlxsw_port_admin_status status) 4153 { 4154 MLXSW_REG_ZERO(paos, payload); 4155 mlxsw_reg_paos_swid_set(payload, 0); 4156 mlxsw_reg_paos_local_port_set(payload, local_port); 4157 mlxsw_reg_paos_admin_status_set(payload, status); 4158 mlxsw_reg_paos_oper_status_set(payload, 0); 4159 mlxsw_reg_paos_ase_set(payload, 1); 4160 mlxsw_reg_paos_ee_set(payload, 1); 4161 mlxsw_reg_paos_e_set(payload, 1); 4162 } 4163 4164 /* PFCC - Ports Flow Control Configuration Register 4165 * ------------------------------------------------ 4166 * Configures and retrieves the per port flow control configuration. 4167 */ 4168 #define MLXSW_REG_PFCC_ID 0x5007 4169 #define MLXSW_REG_PFCC_LEN 0x20 4170 4171 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4172 4173 /* reg_pfcc_local_port 4174 * Local port number. 4175 * Access: Index 4176 */ 4177 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4178 4179 /* reg_pfcc_pnat 4180 * Port number access type. Determines the way local_port is interpreted: 4181 * 0 - Local port number. 4182 * 1 - IB / label port number. 4183 * Access: Index 4184 */ 4185 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4186 4187 /* reg_pfcc_shl_cap 4188 * Send to higher layers capabilities: 4189 * 0 - No capability of sending Pause and PFC frames to higher layers. 4190 * 1 - Device has capability of sending Pause and PFC frames to higher 4191 * layers. 4192 * Access: RO 4193 */ 4194 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4195 4196 /* reg_pfcc_shl_opr 4197 * Send to higher layers operation: 4198 * 0 - Pause and PFC frames are handled by the port (default). 4199 * 1 - Pause and PFC frames are handled by the port and also sent to 4200 * higher layers. Only valid if shl_cap = 1. 4201 * Access: RW 4202 */ 4203 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4204 4205 /* reg_pfcc_ppan 4206 * Pause policy auto negotiation. 4207 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4208 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4209 * based on the auto-negotiation resolution. 4210 * Access: RW 4211 * 4212 * Note: The auto-negotiation advertisement is set according to pptx and 4213 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4214 */ 4215 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4216 4217 /* reg_pfcc_prio_mask_tx 4218 * Bit per priority indicating if Tx flow control policy should be 4219 * updated based on bit pfctx. 4220 * Access: WO 4221 */ 4222 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4223 4224 /* reg_pfcc_prio_mask_rx 4225 * Bit per priority indicating if Rx flow control policy should be 4226 * updated based on bit pfcrx. 4227 * Access: WO 4228 */ 4229 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4230 4231 /* reg_pfcc_pptx 4232 * Admin Pause policy on Tx. 4233 * 0 - Never generate Pause frames (default). 4234 * 1 - Generate Pause frames according to Rx buffer threshold. 4235 * Access: RW 4236 */ 4237 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4238 4239 /* reg_pfcc_aptx 4240 * Active (operational) Pause policy on Tx. 4241 * 0 - Never generate Pause frames. 4242 * 1 - Generate Pause frames according to Rx buffer threshold. 4243 * Access: RO 4244 */ 4245 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4246 4247 /* reg_pfcc_pfctx 4248 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4249 * 0 - Never generate priority Pause frames on the specified priority 4250 * (default). 4251 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4252 * the specified priority. 4253 * Access: RW 4254 * 4255 * Note: pfctx and pptx must be mutually exclusive. 4256 */ 4257 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4258 4259 /* reg_pfcc_pprx 4260 * Admin Pause policy on Rx. 4261 * 0 - Ignore received Pause frames (default). 4262 * 1 - Respect received Pause frames. 4263 * Access: RW 4264 */ 4265 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4266 4267 /* reg_pfcc_aprx 4268 * Active (operational) Pause policy on Rx. 4269 * 0 - Ignore received Pause frames. 4270 * 1 - Respect received Pause frames. 4271 * Access: RO 4272 */ 4273 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4274 4275 /* reg_pfcc_pfcrx 4276 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4277 * 0 - Ignore incoming priority Pause frames on the specified priority 4278 * (default). 4279 * 1 - Respect incoming priority Pause frames on the specified priority. 4280 * Access: RW 4281 */ 4282 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4283 4284 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4285 4286 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4287 { 4288 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4289 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4290 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4291 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4292 } 4293 4294 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4295 { 4296 MLXSW_REG_ZERO(pfcc, payload); 4297 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4298 } 4299 4300 /* PPCNT - Ports Performance Counters Register 4301 * ------------------------------------------- 4302 * The PPCNT register retrieves per port performance counters. 4303 */ 4304 #define MLXSW_REG_PPCNT_ID 0x5008 4305 #define MLXSW_REG_PPCNT_LEN 0x100 4306 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4307 4308 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4309 4310 /* reg_ppcnt_swid 4311 * For HCA: must be always 0. 4312 * Switch partition ID to associate port with. 4313 * Switch partitions are numbered from 0 to 7 inclusively. 4314 * Switch partition 254 indicates stacking ports. 4315 * Switch partition 255 indicates all switch partitions. 4316 * Only valid on Set() operation with local_port=255. 4317 * Access: Index 4318 */ 4319 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4320 4321 /* reg_ppcnt_local_port 4322 * Local port number. 4323 * 255 indicates all ports on the device, and is only allowed 4324 * for Set() operation. 4325 * Access: Index 4326 */ 4327 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4328 4329 /* reg_ppcnt_pnat 4330 * Port number access type: 4331 * 0 - Local port number 4332 * 1 - IB port number 4333 * Access: Index 4334 */ 4335 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4336 4337 enum mlxsw_reg_ppcnt_grp { 4338 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4339 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4340 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4341 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4342 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4343 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4344 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4345 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4346 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4347 }; 4348 4349 /* reg_ppcnt_grp 4350 * Performance counter group. 4351 * Group 63 indicates all groups. Only valid on Set() operation with 4352 * clr bit set. 4353 * 0x0: IEEE 802.3 Counters 4354 * 0x1: RFC 2863 Counters 4355 * 0x2: RFC 2819 Counters 4356 * 0x3: RFC 3635 Counters 4357 * 0x5: Ethernet Extended Counters 4358 * 0x6: Ethernet Discard Counters 4359 * 0x8: Link Level Retransmission Counters 4360 * 0x10: Per Priority Counters 4361 * 0x11: Per Traffic Class Counters 4362 * 0x12: Physical Layer Counters 4363 * 0x13: Per Traffic Class Congestion Counters 4364 * Access: Index 4365 */ 4366 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4367 4368 /* reg_ppcnt_clr 4369 * Clear counters. Setting the clr bit will reset the counter value 4370 * for all counters in the counter group. This bit can be set 4371 * for both Set() and Get() operation. 4372 * Access: OP 4373 */ 4374 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4375 4376 /* reg_ppcnt_prio_tc 4377 * Priority for counter set that support per priority, valid values: 0-7. 4378 * Traffic class for counter set that support per traffic class, 4379 * valid values: 0- cap_max_tclass-1 . 4380 * For HCA: cap_max_tclass is always 8. 4381 * Otherwise must be 0. 4382 * Access: Index 4383 */ 4384 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4385 4386 /* Ethernet IEEE 802.3 Counter Group */ 4387 4388 /* reg_ppcnt_a_frames_transmitted_ok 4389 * Access: RO 4390 */ 4391 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4392 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4393 4394 /* reg_ppcnt_a_frames_received_ok 4395 * Access: RO 4396 */ 4397 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4398 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4399 4400 /* reg_ppcnt_a_frame_check_sequence_errors 4401 * Access: RO 4402 */ 4403 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4404 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4405 4406 /* reg_ppcnt_a_alignment_errors 4407 * Access: RO 4408 */ 4409 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4410 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4411 4412 /* reg_ppcnt_a_octets_transmitted_ok 4413 * Access: RO 4414 */ 4415 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4416 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4417 4418 /* reg_ppcnt_a_octets_received_ok 4419 * Access: RO 4420 */ 4421 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4422 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4423 4424 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4425 * Access: RO 4426 */ 4427 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4428 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4429 4430 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4431 * Access: RO 4432 */ 4433 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4434 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4435 4436 /* reg_ppcnt_a_multicast_frames_received_ok 4437 * Access: RO 4438 */ 4439 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4440 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4441 4442 /* reg_ppcnt_a_broadcast_frames_received_ok 4443 * Access: RO 4444 */ 4445 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4446 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4447 4448 /* reg_ppcnt_a_in_range_length_errors 4449 * Access: RO 4450 */ 4451 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4452 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4453 4454 /* reg_ppcnt_a_out_of_range_length_field 4455 * Access: RO 4456 */ 4457 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4458 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4459 4460 /* reg_ppcnt_a_frame_too_long_errors 4461 * Access: RO 4462 */ 4463 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4464 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4465 4466 /* reg_ppcnt_a_symbol_error_during_carrier 4467 * Access: RO 4468 */ 4469 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4470 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4471 4472 /* reg_ppcnt_a_mac_control_frames_transmitted 4473 * Access: RO 4474 */ 4475 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4477 4478 /* reg_ppcnt_a_mac_control_frames_received 4479 * Access: RO 4480 */ 4481 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4482 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4483 4484 /* reg_ppcnt_a_unsupported_opcodes_received 4485 * Access: RO 4486 */ 4487 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4488 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4489 4490 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4491 * Access: RO 4492 */ 4493 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4494 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4495 4496 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4497 * Access: RO 4498 */ 4499 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4500 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4501 4502 /* Ethernet RFC 2863 Counter Group */ 4503 4504 /* reg_ppcnt_if_in_discards 4505 * Access: RO 4506 */ 4507 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4508 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4509 4510 /* reg_ppcnt_if_out_discards 4511 * Access: RO 4512 */ 4513 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4514 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4515 4516 /* reg_ppcnt_if_out_errors 4517 * Access: RO 4518 */ 4519 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4520 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4521 4522 /* Ethernet RFC 2819 Counter Group */ 4523 4524 /* reg_ppcnt_ether_stats_undersize_pkts 4525 * Access: RO 4526 */ 4527 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4528 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4529 4530 /* reg_ppcnt_ether_stats_oversize_pkts 4531 * Access: RO 4532 */ 4533 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4534 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4535 4536 /* reg_ppcnt_ether_stats_fragments 4537 * Access: RO 4538 */ 4539 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4540 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4541 4542 /* reg_ppcnt_ether_stats_pkts64octets 4543 * Access: RO 4544 */ 4545 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4546 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4547 4548 /* reg_ppcnt_ether_stats_pkts65to127octets 4549 * Access: RO 4550 */ 4551 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4552 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4553 4554 /* reg_ppcnt_ether_stats_pkts128to255octets 4555 * Access: RO 4556 */ 4557 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4558 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4559 4560 /* reg_ppcnt_ether_stats_pkts256to511octets 4561 * Access: RO 4562 */ 4563 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4564 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4565 4566 /* reg_ppcnt_ether_stats_pkts512to1023octets 4567 * Access: RO 4568 */ 4569 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4570 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4571 4572 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4573 * Access: RO 4574 */ 4575 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4576 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4577 4578 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4579 * Access: RO 4580 */ 4581 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4582 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4583 4584 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4585 * Access: RO 4586 */ 4587 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4588 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4589 4590 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4591 * Access: RO 4592 */ 4593 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4594 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4595 4596 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4597 * Access: RO 4598 */ 4599 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4600 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4601 4602 /* Ethernet RFC 3635 Counter Group */ 4603 4604 /* reg_ppcnt_dot3stats_fcs_errors 4605 * Access: RO 4606 */ 4607 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4608 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4609 4610 /* reg_ppcnt_dot3stats_symbol_errors 4611 * Access: RO 4612 */ 4613 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4614 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4615 4616 /* reg_ppcnt_dot3control_in_unknown_opcodes 4617 * Access: RO 4618 */ 4619 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4620 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4621 4622 /* reg_ppcnt_dot3in_pause_frames 4623 * Access: RO 4624 */ 4625 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4626 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4627 4628 /* Ethernet Extended Counter Group Counters */ 4629 4630 /* reg_ppcnt_ecn_marked 4631 * Access: RO 4632 */ 4633 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4634 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4635 4636 /* Ethernet Discard Counter Group Counters */ 4637 4638 /* reg_ppcnt_ingress_general 4639 * Access: RO 4640 */ 4641 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4642 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4643 4644 /* reg_ppcnt_ingress_policy_engine 4645 * Access: RO 4646 */ 4647 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4648 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4649 4650 /* reg_ppcnt_ingress_vlan_membership 4651 * Access: RO 4652 */ 4653 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4654 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4655 4656 /* reg_ppcnt_ingress_tag_frame_type 4657 * Access: RO 4658 */ 4659 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4660 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4661 4662 /* reg_ppcnt_egress_vlan_membership 4663 * Access: RO 4664 */ 4665 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4667 4668 /* reg_ppcnt_loopback_filter 4669 * Access: RO 4670 */ 4671 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4672 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4673 4674 /* reg_ppcnt_egress_general 4675 * Access: RO 4676 */ 4677 MLXSW_ITEM64(reg, ppcnt, egress_general, 4678 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4679 4680 /* reg_ppcnt_egress_hoq 4681 * Access: RO 4682 */ 4683 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 4684 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4685 4686 /* reg_ppcnt_egress_policy_engine 4687 * Access: RO 4688 */ 4689 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 4690 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4691 4692 /* reg_ppcnt_ingress_tx_link_down 4693 * Access: RO 4694 */ 4695 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 4696 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4697 4698 /* reg_ppcnt_egress_stp_filter 4699 * Access: RO 4700 */ 4701 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 4702 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4703 4704 /* reg_ppcnt_egress_sll 4705 * Access: RO 4706 */ 4707 MLXSW_ITEM64(reg, ppcnt, egress_sll, 4708 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4709 4710 /* Ethernet Per Priority Group Counters */ 4711 4712 /* reg_ppcnt_rx_octets 4713 * Access: RO 4714 */ 4715 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4716 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4717 4718 /* reg_ppcnt_rx_frames 4719 * Access: RO 4720 */ 4721 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4722 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4723 4724 /* reg_ppcnt_tx_octets 4725 * Access: RO 4726 */ 4727 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4728 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4729 4730 /* reg_ppcnt_tx_frames 4731 * Access: RO 4732 */ 4733 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4734 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4735 4736 /* reg_ppcnt_rx_pause 4737 * Access: RO 4738 */ 4739 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4740 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4741 4742 /* reg_ppcnt_rx_pause_duration 4743 * Access: RO 4744 */ 4745 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4746 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4747 4748 /* reg_ppcnt_tx_pause 4749 * Access: RO 4750 */ 4751 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4752 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4753 4754 /* reg_ppcnt_tx_pause_duration 4755 * Access: RO 4756 */ 4757 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4758 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4759 4760 /* reg_ppcnt_rx_pause_transition 4761 * Access: RO 4762 */ 4763 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4764 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4765 4766 /* Ethernet Per Traffic Group Counters */ 4767 4768 /* reg_ppcnt_tc_transmit_queue 4769 * Contains the transmit queue depth in cells of traffic class 4770 * selected by prio_tc and the port selected by local_port. 4771 * The field cannot be cleared. 4772 * Access: RO 4773 */ 4774 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4775 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4776 4777 /* reg_ppcnt_tc_no_buffer_discard_uc 4778 * The number of unicast packets dropped due to lack of shared 4779 * buffer resources. 4780 * Access: RO 4781 */ 4782 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4783 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4784 4785 /* Ethernet Per Traffic Class Congestion Group Counters */ 4786 4787 /* reg_ppcnt_wred_discard 4788 * Access: RO 4789 */ 4790 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4791 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4792 4793 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4794 enum mlxsw_reg_ppcnt_grp grp, 4795 u8 prio_tc) 4796 { 4797 MLXSW_REG_ZERO(ppcnt, payload); 4798 mlxsw_reg_ppcnt_swid_set(payload, 0); 4799 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4800 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4801 mlxsw_reg_ppcnt_grp_set(payload, grp); 4802 mlxsw_reg_ppcnt_clr_set(payload, 0); 4803 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4804 } 4805 4806 /* PLIB - Port Local to InfiniBand Port 4807 * ------------------------------------ 4808 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4809 */ 4810 #define MLXSW_REG_PLIB_ID 0x500A 4811 #define MLXSW_REG_PLIB_LEN 0x10 4812 4813 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4814 4815 /* reg_plib_local_port 4816 * Local port number. 4817 * Access: Index 4818 */ 4819 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4820 4821 /* reg_plib_ib_port 4822 * InfiniBand port remapping for local_port. 4823 * Access: RW 4824 */ 4825 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4826 4827 /* PPTB - Port Prio To Buffer Register 4828 * ----------------------------------- 4829 * Configures the switch priority to buffer table. 4830 */ 4831 #define MLXSW_REG_PPTB_ID 0x500B 4832 #define MLXSW_REG_PPTB_LEN 0x10 4833 4834 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4835 4836 enum { 4837 MLXSW_REG_PPTB_MM_UM, 4838 MLXSW_REG_PPTB_MM_UNICAST, 4839 MLXSW_REG_PPTB_MM_MULTICAST, 4840 }; 4841 4842 /* reg_pptb_mm 4843 * Mapping mode. 4844 * 0 - Map both unicast and multicast packets to the same buffer. 4845 * 1 - Map only unicast packets. 4846 * 2 - Map only multicast packets. 4847 * Access: Index 4848 * 4849 * Note: SwitchX-2 only supports the first option. 4850 */ 4851 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4852 4853 /* reg_pptb_local_port 4854 * Local port number. 4855 * Access: Index 4856 */ 4857 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4858 4859 /* reg_pptb_um 4860 * Enables the update of the untagged_buf field. 4861 * Access: RW 4862 */ 4863 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4864 4865 /* reg_pptb_pm 4866 * Enables the update of the prio_to_buff field. 4867 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4868 * Access: RW 4869 */ 4870 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4871 4872 /* reg_pptb_prio_to_buff 4873 * Mapping of switch priority <i> to one of the allocated receive port 4874 * buffers. 4875 * Access: RW 4876 */ 4877 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4878 4879 /* reg_pptb_pm_msb 4880 * Enables the update of the prio_to_buff field. 4881 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4882 * Access: RW 4883 */ 4884 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4885 4886 /* reg_pptb_untagged_buff 4887 * Mapping of untagged frames to one of the allocated receive port buffers. 4888 * Access: RW 4889 * 4890 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4891 * Spectrum, as it maps untagged packets based on the default switch priority. 4892 */ 4893 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4894 4895 /* reg_pptb_prio_to_buff_msb 4896 * Mapping of switch priority <i+8> to one of the allocated receive port 4897 * buffers. 4898 * Access: RW 4899 */ 4900 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4901 4902 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4903 4904 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4905 { 4906 MLXSW_REG_ZERO(pptb, payload); 4907 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4908 mlxsw_reg_pptb_local_port_set(payload, local_port); 4909 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4910 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4911 } 4912 4913 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4914 u8 buff) 4915 { 4916 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4917 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4918 } 4919 4920 /* PBMC - Port Buffer Management Control Register 4921 * ---------------------------------------------- 4922 * The PBMC register configures and retrieves the port packet buffer 4923 * allocation for different Prios, and the Pause threshold management. 4924 */ 4925 #define MLXSW_REG_PBMC_ID 0x500C 4926 #define MLXSW_REG_PBMC_LEN 0x6C 4927 4928 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 4929 4930 /* reg_pbmc_local_port 4931 * Local port number. 4932 * Access: Index 4933 */ 4934 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 4935 4936 /* reg_pbmc_xoff_timer_value 4937 * When device generates a pause frame, it uses this value as the pause 4938 * timer (time for the peer port to pause in quota-512 bit time). 4939 * Access: RW 4940 */ 4941 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 4942 4943 /* reg_pbmc_xoff_refresh 4944 * The time before a new pause frame should be sent to refresh the pause RW 4945 * state. Using the same units as xoff_timer_value above (in quota-512 bit 4946 * time). 4947 * Access: RW 4948 */ 4949 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 4950 4951 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 4952 4953 /* reg_pbmc_buf_lossy 4954 * The field indicates if the buffer is lossy. 4955 * 0 - Lossless 4956 * 1 - Lossy 4957 * Access: RW 4958 */ 4959 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 4960 4961 /* reg_pbmc_buf_epsb 4962 * Eligible for Port Shared buffer. 4963 * If epsb is set, packets assigned to buffer are allowed to insert the port 4964 * shared buffer. 4965 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 4966 * Access: RW 4967 */ 4968 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 4969 4970 /* reg_pbmc_buf_size 4971 * The part of the packet buffer array is allocated for the specific buffer. 4972 * Units are represented in cells. 4973 * Access: RW 4974 */ 4975 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 4976 4977 /* reg_pbmc_buf_xoff_threshold 4978 * Once the amount of data in the buffer goes above this value, device 4979 * starts sending PFC frames for all priorities associated with the 4980 * buffer. Units are represented in cells. Reserved in case of lossy 4981 * buffer. 4982 * Access: RW 4983 * 4984 * Note: In Spectrum, reserved for buffer[9]. 4985 */ 4986 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 4987 0x08, 0x04, false); 4988 4989 /* reg_pbmc_buf_xon_threshold 4990 * When the amount of data in the buffer goes below this value, device 4991 * stops sending PFC frames for the priorities associated with the 4992 * buffer. Units are represented in cells. Reserved in case of lossy 4993 * buffer. 4994 * Access: RW 4995 * 4996 * Note: In Spectrum, reserved for buffer[9]. 4997 */ 4998 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 4999 0x08, 0x04, false); 5000 5001 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5002 u16 xoff_timer_value, u16 xoff_refresh) 5003 { 5004 MLXSW_REG_ZERO(pbmc, payload); 5005 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5006 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5007 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5008 } 5009 5010 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5011 int buf_index, 5012 u16 size) 5013 { 5014 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5015 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5016 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5017 } 5018 5019 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5020 int buf_index, u16 size, 5021 u16 threshold) 5022 { 5023 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5024 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5025 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5026 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5027 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5028 } 5029 5030 /* PSPA - Port Switch Partition Allocation 5031 * --------------------------------------- 5032 * Controls the association of a port with a switch partition and enables 5033 * configuring ports as stacking ports. 5034 */ 5035 #define MLXSW_REG_PSPA_ID 0x500D 5036 #define MLXSW_REG_PSPA_LEN 0x8 5037 5038 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5039 5040 /* reg_pspa_swid 5041 * Switch partition ID. 5042 * Access: RW 5043 */ 5044 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5045 5046 /* reg_pspa_local_port 5047 * Local port number. 5048 * Access: Index 5049 */ 5050 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5051 5052 /* reg_pspa_sub_port 5053 * Virtual port within the local port. Set to 0 when virtual ports are 5054 * disabled on the local port. 5055 * Access: Index 5056 */ 5057 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5058 5059 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5060 { 5061 MLXSW_REG_ZERO(pspa, payload); 5062 mlxsw_reg_pspa_swid_set(payload, swid); 5063 mlxsw_reg_pspa_local_port_set(payload, local_port); 5064 mlxsw_reg_pspa_sub_port_set(payload, 0); 5065 } 5066 5067 /* HTGT - Host Trap Group Table 5068 * ---------------------------- 5069 * Configures the properties for forwarding to CPU. 5070 */ 5071 #define MLXSW_REG_HTGT_ID 0x7002 5072 #define MLXSW_REG_HTGT_LEN 0x20 5073 5074 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5075 5076 /* reg_htgt_swid 5077 * Switch partition ID. 5078 * Access: Index 5079 */ 5080 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5081 5082 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5083 5084 /* reg_htgt_type 5085 * CPU path type. 5086 * Access: RW 5087 */ 5088 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5089 5090 enum mlxsw_reg_htgt_trap_group { 5091 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5092 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5093 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5094 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5095 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5096 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5097 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5098 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5099 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5100 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5101 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5102 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5103 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5104 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5105 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5106 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5107 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5108 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5109 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5110 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5111 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5112 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5113 }; 5114 5115 /* reg_htgt_trap_group 5116 * Trap group number. User defined number specifying which trap groups 5117 * should be forwarded to the CPU. The mapping between trap IDs and trap 5118 * groups is configured using HPKT register. 5119 * Access: Index 5120 */ 5121 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5122 5123 enum { 5124 MLXSW_REG_HTGT_POLICER_DISABLE, 5125 MLXSW_REG_HTGT_POLICER_ENABLE, 5126 }; 5127 5128 /* reg_htgt_pide 5129 * Enable policer ID specified using 'pid' field. 5130 * Access: RW 5131 */ 5132 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5133 5134 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5135 5136 /* reg_htgt_pid 5137 * Policer ID for the trap group. 5138 * Access: RW 5139 */ 5140 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5141 5142 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5143 5144 /* reg_htgt_mirror_action 5145 * Mirror action to use. 5146 * 0 - Trap to CPU. 5147 * 1 - Trap to CPU and mirror to a mirroring agent. 5148 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5149 * Access: RW 5150 * 5151 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5152 */ 5153 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5154 5155 /* reg_htgt_mirroring_agent 5156 * Mirroring agent. 5157 * Access: RW 5158 */ 5159 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5160 5161 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5162 5163 /* reg_htgt_priority 5164 * Trap group priority. 5165 * In case a packet matches multiple classification rules, the packet will 5166 * only be trapped once, based on the trap ID associated with the group (via 5167 * register HPKT) with the highest priority. 5168 * Supported values are 0-7, with 7 represnting the highest priority. 5169 * Access: RW 5170 * 5171 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5172 * by the 'trap_group' field. 5173 */ 5174 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5175 5176 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5177 5178 /* reg_htgt_local_path_cpu_tclass 5179 * CPU ingress traffic class for the trap group. 5180 * Access: RW 5181 */ 5182 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5183 5184 enum mlxsw_reg_htgt_local_path_rdq { 5185 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5186 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5187 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5188 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5189 }; 5190 /* reg_htgt_local_path_rdq 5191 * Receive descriptor queue (RDQ) to use for the trap group. 5192 * Access: RW 5193 */ 5194 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5195 5196 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5197 u8 priority, u8 tc) 5198 { 5199 MLXSW_REG_ZERO(htgt, payload); 5200 5201 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5202 mlxsw_reg_htgt_pide_set(payload, 5203 MLXSW_REG_HTGT_POLICER_DISABLE); 5204 } else { 5205 mlxsw_reg_htgt_pide_set(payload, 5206 MLXSW_REG_HTGT_POLICER_ENABLE); 5207 mlxsw_reg_htgt_pid_set(payload, policer_id); 5208 } 5209 5210 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5211 mlxsw_reg_htgt_trap_group_set(payload, group); 5212 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5213 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5214 mlxsw_reg_htgt_priority_set(payload, priority); 5215 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5216 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5217 } 5218 5219 /* HPKT - Host Packet Trap 5220 * ----------------------- 5221 * Configures trap IDs inside trap groups. 5222 */ 5223 #define MLXSW_REG_HPKT_ID 0x7003 5224 #define MLXSW_REG_HPKT_LEN 0x10 5225 5226 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5227 5228 enum { 5229 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5230 MLXSW_REG_HPKT_ACK_REQUIRED, 5231 }; 5232 5233 /* reg_hpkt_ack 5234 * Require acknowledgements from the host for events. 5235 * If set, then the device will wait for the event it sent to be acknowledged 5236 * by the host. This option is only relevant for event trap IDs. 5237 * Access: RW 5238 * 5239 * Note: Currently not supported by firmware. 5240 */ 5241 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5242 5243 enum mlxsw_reg_hpkt_action { 5244 MLXSW_REG_HPKT_ACTION_FORWARD, 5245 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5246 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5247 MLXSW_REG_HPKT_ACTION_DISCARD, 5248 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5249 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5250 }; 5251 5252 /* reg_hpkt_action 5253 * Action to perform on packet when trapped. 5254 * 0 - No action. Forward to CPU based on switching rules. 5255 * 1 - Trap to CPU (CPU receives sole copy). 5256 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5257 * 3 - Discard. 5258 * 4 - Soft discard (allow other traps to act on the packet). 5259 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5260 * Access: RW 5261 * 5262 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5263 * addressed to the CPU. 5264 */ 5265 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5266 5267 /* reg_hpkt_trap_group 5268 * Trap group to associate the trap with. 5269 * Access: RW 5270 */ 5271 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5272 5273 /* reg_hpkt_trap_id 5274 * Trap ID. 5275 * Access: Index 5276 * 5277 * Note: A trap ID can only be associated with a single trap group. The device 5278 * will associate the trap ID with the last trap group configured. 5279 */ 5280 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5281 5282 enum { 5283 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5284 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5285 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5286 }; 5287 5288 /* reg_hpkt_ctrl 5289 * Configure dedicated buffer resources for control packets. 5290 * Ignored by SwitchX-2. 5291 * 0 - Keep factory defaults. 5292 * 1 - Do not use control buffer for this trap ID. 5293 * 2 - Use control buffer for this trap ID. 5294 * Access: RW 5295 */ 5296 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5297 5298 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5299 enum mlxsw_reg_htgt_trap_group trap_group, 5300 bool is_ctrl) 5301 { 5302 MLXSW_REG_ZERO(hpkt, payload); 5303 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5304 mlxsw_reg_hpkt_action_set(payload, action); 5305 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5306 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5307 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5308 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5309 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5310 } 5311 5312 /* RGCR - Router General Configuration Register 5313 * -------------------------------------------- 5314 * The register is used for setting up the router configuration. 5315 */ 5316 #define MLXSW_REG_RGCR_ID 0x8001 5317 #define MLXSW_REG_RGCR_LEN 0x28 5318 5319 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5320 5321 /* reg_rgcr_ipv4_en 5322 * IPv4 router enable. 5323 * Access: RW 5324 */ 5325 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5326 5327 /* reg_rgcr_ipv6_en 5328 * IPv6 router enable. 5329 * Access: RW 5330 */ 5331 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5332 5333 /* reg_rgcr_max_router_interfaces 5334 * Defines the maximum number of active router interfaces for all virtual 5335 * routers. 5336 * Access: RW 5337 */ 5338 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5339 5340 /* reg_rgcr_usp 5341 * Update switch priority and packet color. 5342 * 0 - Preserve the value of Switch Priority and packet color. 5343 * 1 - Recalculate the value of Switch Priority and packet color. 5344 * Access: RW 5345 * 5346 * Note: Not supported by SwitchX and SwitchX-2. 5347 */ 5348 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5349 5350 /* reg_rgcr_pcp_rw 5351 * Indicates how to handle the pcp_rewrite_en value: 5352 * 0 - Preserve the value of pcp_rewrite_en. 5353 * 2 - Disable PCP rewrite. 5354 * 3 - Enable PCP rewrite. 5355 * Access: RW 5356 * 5357 * Note: Not supported by SwitchX and SwitchX-2. 5358 */ 5359 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5360 5361 /* reg_rgcr_activity_dis 5362 * Activity disable: 5363 * 0 - Activity will be set when an entry is hit (default). 5364 * 1 - Activity will not be set when an entry is hit. 5365 * 5366 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5367 * (RALUE). 5368 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5369 * Entry (RAUHT). 5370 * Bits 2:7 are reserved. 5371 * Access: RW 5372 * 5373 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5374 */ 5375 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5376 5377 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5378 bool ipv6_en) 5379 { 5380 MLXSW_REG_ZERO(rgcr, payload); 5381 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5382 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5383 } 5384 5385 /* RITR - Router Interface Table Register 5386 * -------------------------------------- 5387 * The register is used to configure the router interface table. 5388 */ 5389 #define MLXSW_REG_RITR_ID 0x8002 5390 #define MLXSW_REG_RITR_LEN 0x40 5391 5392 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5393 5394 /* reg_ritr_enable 5395 * Enables routing on the router interface. 5396 * Access: RW 5397 */ 5398 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5399 5400 /* reg_ritr_ipv4 5401 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5402 * interface. 5403 * Access: RW 5404 */ 5405 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5406 5407 /* reg_ritr_ipv6 5408 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5409 * interface. 5410 * Access: RW 5411 */ 5412 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5413 5414 /* reg_ritr_ipv4_mc 5415 * IPv4 multicast routing enable. 5416 * Access: RW 5417 */ 5418 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5419 5420 /* reg_ritr_ipv6_mc 5421 * IPv6 multicast routing enable. 5422 * Access: RW 5423 */ 5424 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5425 5426 enum mlxsw_reg_ritr_if_type { 5427 /* VLAN interface. */ 5428 MLXSW_REG_RITR_VLAN_IF, 5429 /* FID interface. */ 5430 MLXSW_REG_RITR_FID_IF, 5431 /* Sub-port interface. */ 5432 MLXSW_REG_RITR_SP_IF, 5433 /* Loopback Interface. */ 5434 MLXSW_REG_RITR_LOOPBACK_IF, 5435 }; 5436 5437 /* reg_ritr_type 5438 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5439 * Access: RW 5440 */ 5441 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5442 5443 enum { 5444 MLXSW_REG_RITR_RIF_CREATE, 5445 MLXSW_REG_RITR_RIF_DEL, 5446 }; 5447 5448 /* reg_ritr_op 5449 * Opcode: 5450 * 0 - Create or edit RIF. 5451 * 1 - Delete RIF. 5452 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5453 * is not supported. An interface must be deleted and re-created in order 5454 * to update properties. 5455 * Access: WO 5456 */ 5457 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5458 5459 /* reg_ritr_rif 5460 * Router interface index. A pointer to the Router Interface Table. 5461 * Access: Index 5462 */ 5463 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5464 5465 /* reg_ritr_ipv4_fe 5466 * IPv4 Forwarding Enable. 5467 * Enables routing of IPv4 traffic on the router interface. When disabled, 5468 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5469 * Not supported in SwitchX-2. 5470 * Access: RW 5471 */ 5472 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5473 5474 /* reg_ritr_ipv6_fe 5475 * IPv6 Forwarding Enable. 5476 * Enables routing of IPv6 traffic on the router interface. When disabled, 5477 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5478 * Not supported in SwitchX-2. 5479 * Access: RW 5480 */ 5481 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5482 5483 /* reg_ritr_ipv4_mc_fe 5484 * IPv4 Multicast Forwarding Enable. 5485 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5486 * will be enabled. 5487 * Access: RW 5488 */ 5489 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5490 5491 /* reg_ritr_ipv6_mc_fe 5492 * IPv6 Multicast Forwarding Enable. 5493 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5494 * will be enabled. 5495 * Access: RW 5496 */ 5497 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5498 5499 /* reg_ritr_lb_en 5500 * Loop-back filter enable for unicast packets. 5501 * If the flag is set then loop-back filter for unicast packets is 5502 * implemented on the RIF. Multicast packets are always subject to 5503 * loop-back filtering. 5504 * Access: RW 5505 */ 5506 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5507 5508 /* reg_ritr_virtual_router 5509 * Virtual router ID associated with the router interface. 5510 * Access: RW 5511 */ 5512 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5513 5514 /* reg_ritr_mtu 5515 * Router interface MTU. 5516 * Access: RW 5517 */ 5518 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5519 5520 /* reg_ritr_if_swid 5521 * Switch partition ID. 5522 * Access: RW 5523 */ 5524 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5525 5526 /* reg_ritr_if_mac 5527 * Router interface MAC address. 5528 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5529 * Access: RW 5530 */ 5531 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5532 5533 /* reg_ritr_if_vrrp_id_ipv6 5534 * VRRP ID for IPv6 5535 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5536 * Access: RW 5537 */ 5538 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5539 5540 /* reg_ritr_if_vrrp_id_ipv4 5541 * VRRP ID for IPv4 5542 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5543 * Access: RW 5544 */ 5545 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5546 5547 /* VLAN Interface */ 5548 5549 /* reg_ritr_vlan_if_vid 5550 * VLAN ID. 5551 * Access: RW 5552 */ 5553 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5554 5555 /* FID Interface */ 5556 5557 /* reg_ritr_fid_if_fid 5558 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5559 * the vFID range are supported. 5560 * Access: RW 5561 */ 5562 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5563 5564 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5565 enum mlxsw_reg_ritr_if_type rif_type, 5566 u16 fid) 5567 { 5568 if (rif_type == MLXSW_REG_RITR_FID_IF) 5569 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5570 else 5571 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5572 } 5573 5574 /* Sub-port Interface */ 5575 5576 /* reg_ritr_sp_if_lag 5577 * LAG indication. When this bit is set the system_port field holds the 5578 * LAG identifier. 5579 * Access: RW 5580 */ 5581 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5582 5583 /* reg_ritr_sp_system_port 5584 * Port unique indentifier. When lag bit is set, this field holds the 5585 * lag_id in bits 0:9. 5586 * Access: RW 5587 */ 5588 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5589 5590 /* reg_ritr_sp_if_vid 5591 * VLAN ID. 5592 * Access: RW 5593 */ 5594 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5595 5596 /* Loopback Interface */ 5597 5598 enum mlxsw_reg_ritr_loopback_protocol { 5599 /* IPinIP IPv4 underlay Unicast */ 5600 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5601 /* IPinIP IPv6 underlay Unicast */ 5602 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5603 }; 5604 5605 /* reg_ritr_loopback_protocol 5606 * Access: RW 5607 */ 5608 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5609 5610 enum mlxsw_reg_ritr_loopback_ipip_type { 5611 /* Tunnel is IPinIP. */ 5612 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5613 /* Tunnel is GRE, no key. */ 5614 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5615 /* Tunnel is GRE, with a key. */ 5616 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5617 }; 5618 5619 /* reg_ritr_loopback_ipip_type 5620 * Encapsulation type. 5621 * Access: RW 5622 */ 5623 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5624 5625 enum mlxsw_reg_ritr_loopback_ipip_options { 5626 /* The key is defined by gre_key. */ 5627 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5628 }; 5629 5630 /* reg_ritr_loopback_ipip_options 5631 * Access: RW 5632 */ 5633 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5634 5635 /* reg_ritr_loopback_ipip_uvr 5636 * Underlay Virtual Router ID. 5637 * Range is 0..cap_max_virtual_routers-1. 5638 * Reserved for Spectrum-2. 5639 * Access: RW 5640 */ 5641 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5642 5643 /* reg_ritr_loopback_ipip_usip* 5644 * Encapsulation Underlay source IP. 5645 * Access: RW 5646 */ 5647 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5648 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5649 5650 /* reg_ritr_loopback_ipip_gre_key 5651 * GRE Key. 5652 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5653 * Access: RW 5654 */ 5655 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5656 5657 /* Shared between ingress/egress */ 5658 enum mlxsw_reg_ritr_counter_set_type { 5659 /* No Count. */ 5660 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5661 /* Basic. Used for router interfaces, counting the following: 5662 * - Error and Discard counters. 5663 * - Unicast, Multicast and Broadcast counters. Sharing the 5664 * same set of counters for the different type of traffic 5665 * (IPv4, IPv6 and mpls). 5666 */ 5667 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5668 }; 5669 5670 /* reg_ritr_ingress_counter_index 5671 * Counter Index for flow counter. 5672 * Access: RW 5673 */ 5674 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5675 5676 /* reg_ritr_ingress_counter_set_type 5677 * Igress Counter Set Type for router interface counter. 5678 * Access: RW 5679 */ 5680 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5681 5682 /* reg_ritr_egress_counter_index 5683 * Counter Index for flow counter. 5684 * Access: RW 5685 */ 5686 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5687 5688 /* reg_ritr_egress_counter_set_type 5689 * Egress Counter Set Type for router interface counter. 5690 * Access: RW 5691 */ 5692 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5693 5694 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5695 bool enable, bool egress) 5696 { 5697 enum mlxsw_reg_ritr_counter_set_type set_type; 5698 5699 if (enable) 5700 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5701 else 5702 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5703 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5704 5705 if (egress) 5706 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5707 else 5708 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5709 } 5710 5711 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5712 { 5713 MLXSW_REG_ZERO(ritr, payload); 5714 mlxsw_reg_ritr_rif_set(payload, rif); 5715 } 5716 5717 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5718 u16 system_port, u16 vid) 5719 { 5720 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5721 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5722 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5723 } 5724 5725 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5726 enum mlxsw_reg_ritr_if_type type, 5727 u16 rif, u16 vr_id, u16 mtu) 5728 { 5729 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5730 5731 MLXSW_REG_ZERO(ritr, payload); 5732 mlxsw_reg_ritr_enable_set(payload, enable); 5733 mlxsw_reg_ritr_ipv4_set(payload, 1); 5734 mlxsw_reg_ritr_ipv6_set(payload, 1); 5735 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5736 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5737 mlxsw_reg_ritr_type_set(payload, type); 5738 mlxsw_reg_ritr_op_set(payload, op); 5739 mlxsw_reg_ritr_rif_set(payload, rif); 5740 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5741 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5742 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5743 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5744 mlxsw_reg_ritr_lb_en_set(payload, 1); 5745 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5746 mlxsw_reg_ritr_mtu_set(payload, mtu); 5747 } 5748 5749 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5750 { 5751 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5752 } 5753 5754 static inline void 5755 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5756 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5757 enum mlxsw_reg_ritr_loopback_ipip_options options, 5758 u16 uvr_id, u32 gre_key) 5759 { 5760 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5761 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5762 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5763 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5764 } 5765 5766 static inline void 5767 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5768 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5769 enum mlxsw_reg_ritr_loopback_ipip_options options, 5770 u16 uvr_id, u32 usip, u32 gre_key) 5771 { 5772 mlxsw_reg_ritr_loopback_protocol_set(payload, 5773 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5774 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5775 uvr_id, gre_key); 5776 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5777 } 5778 5779 /* RTAR - Router TCAM Allocation Register 5780 * -------------------------------------- 5781 * This register is used for allocation of regions in the TCAM table. 5782 */ 5783 #define MLXSW_REG_RTAR_ID 0x8004 5784 #define MLXSW_REG_RTAR_LEN 0x20 5785 5786 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5787 5788 enum mlxsw_reg_rtar_op { 5789 MLXSW_REG_RTAR_OP_ALLOCATE, 5790 MLXSW_REG_RTAR_OP_RESIZE, 5791 MLXSW_REG_RTAR_OP_DEALLOCATE, 5792 }; 5793 5794 /* reg_rtar_op 5795 * Access: WO 5796 */ 5797 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5798 5799 enum mlxsw_reg_rtar_key_type { 5800 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5801 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5802 }; 5803 5804 /* reg_rtar_key_type 5805 * TCAM key type for the region. 5806 * Access: WO 5807 */ 5808 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5809 5810 /* reg_rtar_region_size 5811 * TCAM region size. When allocating/resizing this is the requested 5812 * size, the response is the actual size. 5813 * Note: Actual size may be larger than requested. 5814 * Reserved for op = Deallocate 5815 * Access: WO 5816 */ 5817 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5818 5819 static inline void mlxsw_reg_rtar_pack(char *payload, 5820 enum mlxsw_reg_rtar_op op, 5821 enum mlxsw_reg_rtar_key_type key_type, 5822 u16 region_size) 5823 { 5824 MLXSW_REG_ZERO(rtar, payload); 5825 mlxsw_reg_rtar_op_set(payload, op); 5826 mlxsw_reg_rtar_key_type_set(payload, key_type); 5827 mlxsw_reg_rtar_region_size_set(payload, region_size); 5828 } 5829 5830 /* RATR - Router Adjacency Table Register 5831 * -------------------------------------- 5832 * The RATR register is used to configure the Router Adjacency (next-hop) 5833 * Table. 5834 */ 5835 #define MLXSW_REG_RATR_ID 0x8008 5836 #define MLXSW_REG_RATR_LEN 0x2C 5837 5838 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5839 5840 enum mlxsw_reg_ratr_op { 5841 /* Read */ 5842 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5843 /* Read and clear activity */ 5844 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5845 /* Write Adjacency entry */ 5846 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5847 /* Write Adjacency entry only if the activity is cleared. 5848 * The write may not succeed if the activity is set. There is not 5849 * direct feedback if the write has succeeded or not, however 5850 * the get will reveal the actual entry (SW can compare the get 5851 * response to the set command). 5852 */ 5853 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5854 }; 5855 5856 /* reg_ratr_op 5857 * Note that Write operation may also be used for updating 5858 * counter_set_type and counter_index. In this case all other 5859 * fields must not be updated. 5860 * Access: OP 5861 */ 5862 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5863 5864 /* reg_ratr_v 5865 * Valid bit. Indicates if the adjacency entry is valid. 5866 * Note: the device may need some time before reusing an invalidated 5867 * entry. During this time the entry can not be reused. It is 5868 * recommended to use another entry before reusing an invalidated 5869 * entry (e.g. software can put it at the end of the list for 5870 * reusing). Trying to access an invalidated entry not yet cleared 5871 * by the device results with failure indicating "Try Again" status. 5872 * When valid is '0' then egress_router_interface,trap_action, 5873 * adjacency_parameters and counters are reserved 5874 * Access: RW 5875 */ 5876 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5877 5878 /* reg_ratr_a 5879 * Activity. Set for new entries. Set if a packet lookup has hit on 5880 * the specific entry. To clear the a bit, use "clear activity". 5881 * Access: RO 5882 */ 5883 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5884 5885 enum mlxsw_reg_ratr_type { 5886 /* Ethernet */ 5887 MLXSW_REG_RATR_TYPE_ETHERNET, 5888 /* IPoIB Unicast without GRH. 5889 * Reserved for Spectrum. 5890 */ 5891 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5892 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5893 * adjacency). 5894 * Reserved for Spectrum. 5895 */ 5896 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5897 /* IPoIB Multicast. 5898 * Reserved for Spectrum. 5899 */ 5900 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5901 /* MPLS. 5902 * Reserved for SwitchX/-2. 5903 */ 5904 MLXSW_REG_RATR_TYPE_MPLS, 5905 /* IPinIP Encap. 5906 * Reserved for SwitchX/-2. 5907 */ 5908 MLXSW_REG_RATR_TYPE_IPIP, 5909 }; 5910 5911 /* reg_ratr_type 5912 * Adjacency entry type. 5913 * Access: RW 5914 */ 5915 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 5916 5917 /* reg_ratr_adjacency_index_low 5918 * Bits 15:0 of index into the adjacency table. 5919 * For SwitchX and SwitchX-2, the adjacency table is linear and 5920 * used for adjacency entries only. 5921 * For Spectrum, the index is to the KVD linear. 5922 * Access: Index 5923 */ 5924 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 5925 5926 /* reg_ratr_egress_router_interface 5927 * Range is 0 .. cap_max_router_interfaces - 1 5928 * Access: RW 5929 */ 5930 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 5931 5932 enum mlxsw_reg_ratr_trap_action { 5933 MLXSW_REG_RATR_TRAP_ACTION_NOP, 5934 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 5935 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 5936 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 5937 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 5938 }; 5939 5940 /* reg_ratr_trap_action 5941 * see mlxsw_reg_ratr_trap_action 5942 * Access: RW 5943 */ 5944 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 5945 5946 /* reg_ratr_adjacency_index_high 5947 * Bits 23:16 of the adjacency_index. 5948 * Access: Index 5949 */ 5950 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 5951 5952 enum mlxsw_reg_ratr_trap_id { 5953 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 5954 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 5955 }; 5956 5957 /* reg_ratr_trap_id 5958 * Trap ID to be reported to CPU. 5959 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5960 * For trap_action of NOP, MIRROR and DISCARD_ERROR 5961 * Access: RW 5962 */ 5963 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 5964 5965 /* reg_ratr_eth_destination_mac 5966 * MAC address of the destination next-hop. 5967 * Access: RW 5968 */ 5969 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 5970 5971 enum mlxsw_reg_ratr_ipip_type { 5972 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 5973 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 5974 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 5975 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 5976 }; 5977 5978 /* reg_ratr_ipip_type 5979 * Underlay destination ip type. 5980 * Note: the type field must match the protocol of the router interface. 5981 * Access: RW 5982 */ 5983 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 5984 5985 /* reg_ratr_ipip_ipv4_udip 5986 * Underlay ipv4 dip. 5987 * Reserved when ipip_type is IPv6. 5988 * Access: RW 5989 */ 5990 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 5991 5992 /* reg_ratr_ipip_ipv6_ptr 5993 * Pointer to IPv6 underlay destination ip address. 5994 * For Spectrum: Pointer to KVD linear space. 5995 * Access: RW 5996 */ 5997 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 5998 5999 enum mlxsw_reg_flow_counter_set_type { 6000 /* No count */ 6001 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6002 /* Count packets and bytes */ 6003 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6004 /* Count only packets */ 6005 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6006 }; 6007 6008 /* reg_ratr_counter_set_type 6009 * Counter set type for flow counters 6010 * Access: RW 6011 */ 6012 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6013 6014 /* reg_ratr_counter_index 6015 * Counter index for flow counters 6016 * Access: RW 6017 */ 6018 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6019 6020 static inline void 6021 mlxsw_reg_ratr_pack(char *payload, 6022 enum mlxsw_reg_ratr_op op, bool valid, 6023 enum mlxsw_reg_ratr_type type, 6024 u32 adjacency_index, u16 egress_rif) 6025 { 6026 MLXSW_REG_ZERO(ratr, payload); 6027 mlxsw_reg_ratr_op_set(payload, op); 6028 mlxsw_reg_ratr_v_set(payload, valid); 6029 mlxsw_reg_ratr_type_set(payload, type); 6030 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6031 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6032 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6033 } 6034 6035 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6036 const char *dest_mac) 6037 { 6038 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6039 } 6040 6041 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6042 { 6043 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6044 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6045 } 6046 6047 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6048 bool counter_enable) 6049 { 6050 enum mlxsw_reg_flow_counter_set_type set_type; 6051 6052 if (counter_enable) 6053 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6054 else 6055 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6056 6057 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6058 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6059 } 6060 6061 /* RDPM - Router DSCP to Priority Mapping 6062 * -------------------------------------- 6063 * Controls the mapping from DSCP field to switch priority on routed packets 6064 */ 6065 #define MLXSW_REG_RDPM_ID 0x8009 6066 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6067 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6068 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6069 #define MLXSW_REG_RDPM_LEN 0x40 6070 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6071 MLXSW_REG_RDPM_LEN - \ 6072 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6073 6074 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6075 6076 /* reg_dscp_entry_e 6077 * Enable update of the specific entry 6078 * Access: Index 6079 */ 6080 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6081 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6082 6083 /* reg_dscp_entry_prio 6084 * Switch Priority 6085 * Access: RW 6086 */ 6087 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6088 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6089 6090 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6091 u8 prio) 6092 { 6093 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6094 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6095 } 6096 6097 /* RICNT - Router Interface Counter Register 6098 * ----------------------------------------- 6099 * The RICNT register retrieves per port performance counters 6100 */ 6101 #define MLXSW_REG_RICNT_ID 0x800B 6102 #define MLXSW_REG_RICNT_LEN 0x100 6103 6104 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6105 6106 /* reg_ricnt_counter_index 6107 * Counter index 6108 * Access: RW 6109 */ 6110 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6111 6112 enum mlxsw_reg_ricnt_counter_set_type { 6113 /* No Count. */ 6114 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6115 /* Basic. Used for router interfaces, counting the following: 6116 * - Error and Discard counters. 6117 * - Unicast, Multicast and Broadcast counters. Sharing the 6118 * same set of counters for the different type of traffic 6119 * (IPv4, IPv6 and mpls). 6120 */ 6121 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6122 }; 6123 6124 /* reg_ricnt_counter_set_type 6125 * Counter Set Type for router interface counter 6126 * Access: RW 6127 */ 6128 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6129 6130 enum mlxsw_reg_ricnt_opcode { 6131 /* Nop. Supported only for read access*/ 6132 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6133 /* Clear. Setting the clr bit will reset the counter value for 6134 * all counters of the specified Router Interface. 6135 */ 6136 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6137 }; 6138 6139 /* reg_ricnt_opcode 6140 * Opcode 6141 * Access: RW 6142 */ 6143 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6144 6145 /* reg_ricnt_good_unicast_packets 6146 * good unicast packets. 6147 * Access: RW 6148 */ 6149 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6150 6151 /* reg_ricnt_good_multicast_packets 6152 * good multicast packets. 6153 * Access: RW 6154 */ 6155 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6156 6157 /* reg_ricnt_good_broadcast_packets 6158 * good broadcast packets 6159 * Access: RW 6160 */ 6161 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6162 6163 /* reg_ricnt_good_unicast_bytes 6164 * A count of L3 data and padding octets not including L2 headers 6165 * for good unicast frames. 6166 * Access: RW 6167 */ 6168 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6169 6170 /* reg_ricnt_good_multicast_bytes 6171 * A count of L3 data and padding octets not including L2 headers 6172 * for good multicast frames. 6173 * Access: RW 6174 */ 6175 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6176 6177 /* reg_ritr_good_broadcast_bytes 6178 * A count of L3 data and padding octets not including L2 headers 6179 * for good broadcast frames. 6180 * Access: RW 6181 */ 6182 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6183 6184 /* reg_ricnt_error_packets 6185 * A count of errored frames that do not pass the router checks. 6186 * Access: RW 6187 */ 6188 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6189 6190 /* reg_ricnt_discrad_packets 6191 * A count of non-errored frames that do not pass the router checks. 6192 * Access: RW 6193 */ 6194 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6195 6196 /* reg_ricnt_error_bytes 6197 * A count of L3 data and padding octets not including L2 headers 6198 * for errored frames. 6199 * Access: RW 6200 */ 6201 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6202 6203 /* reg_ricnt_discard_bytes 6204 * A count of L3 data and padding octets not including L2 headers 6205 * for non-errored frames that do not pass the router checks. 6206 * Access: RW 6207 */ 6208 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6209 6210 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6211 enum mlxsw_reg_ricnt_opcode op) 6212 { 6213 MLXSW_REG_ZERO(ricnt, payload); 6214 mlxsw_reg_ricnt_op_set(payload, op); 6215 mlxsw_reg_ricnt_counter_index_set(payload, index); 6216 mlxsw_reg_ricnt_counter_set_type_set(payload, 6217 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6218 } 6219 6220 /* RRCR - Router Rules Copy Register Layout 6221 * ---------------------------------------- 6222 * This register is used for moving and copying route entry rules. 6223 */ 6224 #define MLXSW_REG_RRCR_ID 0x800F 6225 #define MLXSW_REG_RRCR_LEN 0x24 6226 6227 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6228 6229 enum mlxsw_reg_rrcr_op { 6230 /* Move rules */ 6231 MLXSW_REG_RRCR_OP_MOVE, 6232 /* Copy rules */ 6233 MLXSW_REG_RRCR_OP_COPY, 6234 }; 6235 6236 /* reg_rrcr_op 6237 * Access: WO 6238 */ 6239 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6240 6241 /* reg_rrcr_offset 6242 * Offset within the region from which to copy/move. 6243 * Access: Index 6244 */ 6245 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6246 6247 /* reg_rrcr_size 6248 * The number of rules to copy/move. 6249 * Access: WO 6250 */ 6251 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6252 6253 /* reg_rrcr_table_id 6254 * Identifier of the table on which to perform the operation. Encoding is the 6255 * same as in RTAR.key_type 6256 * Access: Index 6257 */ 6258 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6259 6260 /* reg_rrcr_dest_offset 6261 * Offset within the region to which to copy/move 6262 * Access: Index 6263 */ 6264 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6265 6266 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6267 u16 offset, u16 size, 6268 enum mlxsw_reg_rtar_key_type table_id, 6269 u16 dest_offset) 6270 { 6271 MLXSW_REG_ZERO(rrcr, payload); 6272 mlxsw_reg_rrcr_op_set(payload, op); 6273 mlxsw_reg_rrcr_offset_set(payload, offset); 6274 mlxsw_reg_rrcr_size_set(payload, size); 6275 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6276 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6277 } 6278 6279 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6280 * ------------------------------------------------------- 6281 * RALTA is used to allocate the LPM trees of the SHSPM method. 6282 */ 6283 #define MLXSW_REG_RALTA_ID 0x8010 6284 #define MLXSW_REG_RALTA_LEN 0x04 6285 6286 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6287 6288 /* reg_ralta_op 6289 * opcode (valid for Write, must be 0 on Read) 6290 * 0 - allocate a tree 6291 * 1 - deallocate a tree 6292 * Access: OP 6293 */ 6294 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6295 6296 enum mlxsw_reg_ralxx_protocol { 6297 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6298 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6299 }; 6300 6301 /* reg_ralta_protocol 6302 * Protocol. 6303 * Deallocation opcode: Reserved. 6304 * Access: RW 6305 */ 6306 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6307 6308 /* reg_ralta_tree_id 6309 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6310 * the tree identifier (managed by software). 6311 * Note that tree_id 0 is allocated for a default-route tree. 6312 * Access: Index 6313 */ 6314 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6315 6316 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6317 enum mlxsw_reg_ralxx_protocol protocol, 6318 u8 tree_id) 6319 { 6320 MLXSW_REG_ZERO(ralta, payload); 6321 mlxsw_reg_ralta_op_set(payload, !alloc); 6322 mlxsw_reg_ralta_protocol_set(payload, protocol); 6323 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6324 } 6325 6326 /* RALST - Router Algorithmic LPM Structure Tree Register 6327 * ------------------------------------------------------ 6328 * RALST is used to set and query the structure of an LPM tree. 6329 * The structure of the tree must be sorted as a sorted binary tree, while 6330 * each node is a bin that is tagged as the length of the prefixes the lookup 6331 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6332 * of X bits to match with the destination address. The bin 0 indicates 6333 * the default action, when there is no match of any prefix. 6334 */ 6335 #define MLXSW_REG_RALST_ID 0x8011 6336 #define MLXSW_REG_RALST_LEN 0x104 6337 6338 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6339 6340 /* reg_ralst_root_bin 6341 * The bin number of the root bin. 6342 * 0<root_bin=<(length of IP address) 6343 * For a default-route tree configure 0xff 6344 * Access: RW 6345 */ 6346 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6347 6348 /* reg_ralst_tree_id 6349 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6350 * Access: Index 6351 */ 6352 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6353 6354 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6355 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6356 #define MLXSW_REG_RALST_BIN_COUNT 128 6357 6358 /* reg_ralst_left_child_bin 6359 * Holding the children of the bin according to the stored tree's structure. 6360 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6361 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6362 * Access: RW 6363 */ 6364 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6365 6366 /* reg_ralst_right_child_bin 6367 * Holding the children of the bin according to the stored tree's structure. 6368 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6369 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6370 * Access: RW 6371 */ 6372 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6373 false); 6374 6375 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6376 { 6377 MLXSW_REG_ZERO(ralst, payload); 6378 6379 /* Initialize all bins to have no left or right child */ 6380 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6381 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6382 6383 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6384 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6385 } 6386 6387 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6388 u8 left_child_bin, 6389 u8 right_child_bin) 6390 { 6391 int bin_index = bin_number - 1; 6392 6393 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6394 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6395 right_child_bin); 6396 } 6397 6398 /* RALTB - Router Algorithmic LPM Tree Binding Register 6399 * ---------------------------------------------------- 6400 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6401 */ 6402 #define MLXSW_REG_RALTB_ID 0x8012 6403 #define MLXSW_REG_RALTB_LEN 0x04 6404 6405 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6406 6407 /* reg_raltb_virtual_router 6408 * Virtual Router ID 6409 * Range is 0..cap_max_virtual_routers-1 6410 * Access: Index 6411 */ 6412 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6413 6414 /* reg_raltb_protocol 6415 * Protocol. 6416 * Access: Index 6417 */ 6418 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6419 6420 /* reg_raltb_tree_id 6421 * Tree to be used for the {virtual_router, protocol} 6422 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6423 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6424 * Access: RW 6425 */ 6426 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6427 6428 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6429 enum mlxsw_reg_ralxx_protocol protocol, 6430 u8 tree_id) 6431 { 6432 MLXSW_REG_ZERO(raltb, payload); 6433 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6434 mlxsw_reg_raltb_protocol_set(payload, protocol); 6435 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6436 } 6437 6438 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6439 * ----------------------------------------------------- 6440 * RALUE is used to configure and query LPM entries that serve 6441 * the Unicast protocols. 6442 */ 6443 #define MLXSW_REG_RALUE_ID 0x8013 6444 #define MLXSW_REG_RALUE_LEN 0x38 6445 6446 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6447 6448 /* reg_ralue_protocol 6449 * Protocol. 6450 * Access: Index 6451 */ 6452 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6453 6454 enum mlxsw_reg_ralue_op { 6455 /* Read operation. If entry doesn't exist, the operation fails. */ 6456 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6457 /* Clear on read operation. Used to read entry and 6458 * clear Activity bit. 6459 */ 6460 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6461 /* Write operation. Used to write a new entry to the table. All RW 6462 * fields are written for new entry. Activity bit is set 6463 * for new entries. 6464 */ 6465 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6466 /* Update operation. Used to update an existing route entry and 6467 * only update the RW fields that are detailed in the field 6468 * op_u_mask. If entry doesn't exist, the operation fails. 6469 */ 6470 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6471 /* Clear activity. The Activity bit (the field a) is cleared 6472 * for the entry. 6473 */ 6474 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6475 /* Delete operation. Used to delete an existing entry. If entry 6476 * doesn't exist, the operation fails. 6477 */ 6478 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6479 }; 6480 6481 /* reg_ralue_op 6482 * Operation. 6483 * Access: OP 6484 */ 6485 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6486 6487 /* reg_ralue_a 6488 * Activity. Set for new entries. Set if a packet lookup has hit on the 6489 * specific entry, only if the entry is a route. To clear the a bit, use 6490 * "clear activity" op. 6491 * Enabled by activity_dis in RGCR 6492 * Access: RO 6493 */ 6494 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6495 6496 /* reg_ralue_virtual_router 6497 * Virtual Router ID 6498 * Range is 0..cap_max_virtual_routers-1 6499 * Access: Index 6500 */ 6501 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6502 6503 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6504 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6505 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6506 6507 /* reg_ralue_op_u_mask 6508 * opcode update mask. 6509 * On read operation, this field is reserved. 6510 * This field is valid for update opcode, otherwise - reserved. 6511 * This field is a bitmask of the fields that should be updated. 6512 * Access: WO 6513 */ 6514 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6515 6516 /* reg_ralue_prefix_len 6517 * Number of bits in the prefix of the LPM route. 6518 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6519 * two entries in the physical HW table. 6520 * Access: Index 6521 */ 6522 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6523 6524 /* reg_ralue_dip* 6525 * The prefix of the route or of the marker that the object of the LPM 6526 * is compared with. The most significant bits of the dip are the prefix. 6527 * The least significant bits must be '0' if the prefix_len is smaller 6528 * than 128 for IPv6 or smaller than 32 for IPv4. 6529 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6530 * Access: Index 6531 */ 6532 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6533 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6534 6535 enum mlxsw_reg_ralue_entry_type { 6536 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6537 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6538 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6539 }; 6540 6541 /* reg_ralue_entry_type 6542 * Entry type. 6543 * Note - for Marker entries, the action_type and action fields are reserved. 6544 * Access: RW 6545 */ 6546 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6547 6548 /* reg_ralue_bmp_len 6549 * The best match prefix length in the case that there is no match for 6550 * longer prefixes. 6551 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6552 * Note for any update operation with entry_type modification this 6553 * field must be set. 6554 * Access: RW 6555 */ 6556 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6557 6558 enum mlxsw_reg_ralue_action_type { 6559 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6560 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6561 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6562 }; 6563 6564 /* reg_ralue_action_type 6565 * Action Type 6566 * Indicates how the IP address is connected. 6567 * It can be connected to a local subnet through local_erif or can be 6568 * on a remote subnet connected through a next-hop router, 6569 * or transmitted to the CPU. 6570 * Reserved when entry_type = MARKER_ENTRY 6571 * Access: RW 6572 */ 6573 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6574 6575 enum mlxsw_reg_ralue_trap_action { 6576 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6577 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6578 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6579 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6580 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6581 }; 6582 6583 /* reg_ralue_trap_action 6584 * Trap action. 6585 * For IP2ME action, only NOP and MIRROR are possible. 6586 * Access: RW 6587 */ 6588 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6589 6590 /* reg_ralue_trap_id 6591 * Trap ID to be reported to CPU. 6592 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6593 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6594 * Access: RW 6595 */ 6596 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6597 6598 /* reg_ralue_adjacency_index 6599 * Points to the first entry of the group-based ECMP. 6600 * Only relevant in case of REMOTE action. 6601 * Access: RW 6602 */ 6603 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6604 6605 /* reg_ralue_ecmp_size 6606 * Amount of sequential entries starting 6607 * from the adjacency_index (the number of ECMPs). 6608 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6609 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6610 * Only relevant in case of REMOTE action. 6611 * Access: RW 6612 */ 6613 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6614 6615 /* reg_ralue_local_erif 6616 * Egress Router Interface. 6617 * Only relevant in case of LOCAL action. 6618 * Access: RW 6619 */ 6620 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6621 6622 /* reg_ralue_ip2me_v 6623 * Valid bit for the tunnel_ptr field. 6624 * If valid = 0 then trap to CPU as IP2ME trap ID. 6625 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6626 * decapsulation then tunnel decapsulation is done. 6627 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6628 * decapsulation then trap as IP2ME trap ID. 6629 * Only relevant in case of IP2ME action. 6630 * Access: RW 6631 */ 6632 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6633 6634 /* reg_ralue_ip2me_tunnel_ptr 6635 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6636 * For Spectrum, pointer to KVD Linear. 6637 * Only relevant in case of IP2ME action. 6638 * Access: RW 6639 */ 6640 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6641 6642 static inline void mlxsw_reg_ralue_pack(char *payload, 6643 enum mlxsw_reg_ralxx_protocol protocol, 6644 enum mlxsw_reg_ralue_op op, 6645 u16 virtual_router, u8 prefix_len) 6646 { 6647 MLXSW_REG_ZERO(ralue, payload); 6648 mlxsw_reg_ralue_protocol_set(payload, protocol); 6649 mlxsw_reg_ralue_op_set(payload, op); 6650 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6651 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6652 mlxsw_reg_ralue_entry_type_set(payload, 6653 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6654 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6655 } 6656 6657 static inline void mlxsw_reg_ralue_pack4(char *payload, 6658 enum mlxsw_reg_ralxx_protocol protocol, 6659 enum mlxsw_reg_ralue_op op, 6660 u16 virtual_router, u8 prefix_len, 6661 u32 dip) 6662 { 6663 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6664 mlxsw_reg_ralue_dip4_set(payload, dip); 6665 } 6666 6667 static inline void mlxsw_reg_ralue_pack6(char *payload, 6668 enum mlxsw_reg_ralxx_protocol protocol, 6669 enum mlxsw_reg_ralue_op op, 6670 u16 virtual_router, u8 prefix_len, 6671 const void *dip) 6672 { 6673 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6674 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6675 } 6676 6677 static inline void 6678 mlxsw_reg_ralue_act_remote_pack(char *payload, 6679 enum mlxsw_reg_ralue_trap_action trap_action, 6680 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6681 { 6682 mlxsw_reg_ralue_action_type_set(payload, 6683 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6684 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6685 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6686 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6687 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6688 } 6689 6690 static inline void 6691 mlxsw_reg_ralue_act_local_pack(char *payload, 6692 enum mlxsw_reg_ralue_trap_action trap_action, 6693 u16 trap_id, u16 local_erif) 6694 { 6695 mlxsw_reg_ralue_action_type_set(payload, 6696 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6697 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6698 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6699 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6700 } 6701 6702 static inline void 6703 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6704 { 6705 mlxsw_reg_ralue_action_type_set(payload, 6706 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6707 } 6708 6709 static inline void 6710 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6711 { 6712 mlxsw_reg_ralue_action_type_set(payload, 6713 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6714 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6715 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6716 } 6717 6718 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6719 * ---------------------------------------------------------- 6720 * The RAUHT register is used to configure and query the Unicast Host table in 6721 * devices that implement the Algorithmic LPM. 6722 */ 6723 #define MLXSW_REG_RAUHT_ID 0x8014 6724 #define MLXSW_REG_RAUHT_LEN 0x74 6725 6726 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6727 6728 enum mlxsw_reg_rauht_type { 6729 MLXSW_REG_RAUHT_TYPE_IPV4, 6730 MLXSW_REG_RAUHT_TYPE_IPV6, 6731 }; 6732 6733 /* reg_rauht_type 6734 * Access: Index 6735 */ 6736 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6737 6738 enum mlxsw_reg_rauht_op { 6739 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6740 /* Read operation */ 6741 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6742 /* Clear on read operation. Used to read entry and clear 6743 * activity bit. 6744 */ 6745 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6746 /* Add. Used to write a new entry to the table. All R/W fields are 6747 * relevant for new entry. Activity bit is set for new entries. 6748 */ 6749 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6750 /* Update action. Used to update an existing route entry and 6751 * only update the following fields: 6752 * trap_action, trap_id, mac, counter_set_type, counter_index 6753 */ 6754 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6755 /* Clear activity. A bit is cleared for the entry. */ 6756 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6757 /* Delete entry */ 6758 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6759 /* Delete all host entries on a RIF. In this command, dip 6760 * field is reserved. 6761 */ 6762 }; 6763 6764 /* reg_rauht_op 6765 * Access: OP 6766 */ 6767 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6768 6769 /* reg_rauht_a 6770 * Activity. Set for new entries. Set if a packet lookup has hit on 6771 * the specific entry. 6772 * To clear the a bit, use "clear activity" op. 6773 * Enabled by activity_dis in RGCR 6774 * Access: RO 6775 */ 6776 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6777 6778 /* reg_rauht_rif 6779 * Router Interface 6780 * Access: Index 6781 */ 6782 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6783 6784 /* reg_rauht_dip* 6785 * Destination address. 6786 * Access: Index 6787 */ 6788 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6789 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6790 6791 enum mlxsw_reg_rauht_trap_action { 6792 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6793 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6794 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6795 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6796 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6797 }; 6798 6799 /* reg_rauht_trap_action 6800 * Access: RW 6801 */ 6802 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6803 6804 enum mlxsw_reg_rauht_trap_id { 6805 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6806 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6807 }; 6808 6809 /* reg_rauht_trap_id 6810 * Trap ID to be reported to CPU. 6811 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6812 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6813 * trap_id is reserved. 6814 * Access: RW 6815 */ 6816 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6817 6818 /* reg_rauht_counter_set_type 6819 * Counter set type for flow counters 6820 * Access: RW 6821 */ 6822 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6823 6824 /* reg_rauht_counter_index 6825 * Counter index for flow counters 6826 * Access: RW 6827 */ 6828 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6829 6830 /* reg_rauht_mac 6831 * MAC address. 6832 * Access: RW 6833 */ 6834 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6835 6836 static inline void mlxsw_reg_rauht_pack(char *payload, 6837 enum mlxsw_reg_rauht_op op, u16 rif, 6838 const char *mac) 6839 { 6840 MLXSW_REG_ZERO(rauht, payload); 6841 mlxsw_reg_rauht_op_set(payload, op); 6842 mlxsw_reg_rauht_rif_set(payload, rif); 6843 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6844 } 6845 6846 static inline void mlxsw_reg_rauht_pack4(char *payload, 6847 enum mlxsw_reg_rauht_op op, u16 rif, 6848 const char *mac, u32 dip) 6849 { 6850 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6851 mlxsw_reg_rauht_dip4_set(payload, dip); 6852 } 6853 6854 static inline void mlxsw_reg_rauht_pack6(char *payload, 6855 enum mlxsw_reg_rauht_op op, u16 rif, 6856 const char *mac, const char *dip) 6857 { 6858 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6859 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6860 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6861 } 6862 6863 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6864 u64 counter_index) 6865 { 6866 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6867 mlxsw_reg_rauht_counter_set_type_set(payload, 6868 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6869 } 6870 6871 /* RALEU - Router Algorithmic LPM ECMP Update Register 6872 * --------------------------------------------------- 6873 * The register enables updating the ECMP section in the action for multiple 6874 * LPM Unicast entries in a single operation. The update is executed to 6875 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6876 */ 6877 #define MLXSW_REG_RALEU_ID 0x8015 6878 #define MLXSW_REG_RALEU_LEN 0x28 6879 6880 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6881 6882 /* reg_raleu_protocol 6883 * Protocol. 6884 * Access: Index 6885 */ 6886 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6887 6888 /* reg_raleu_virtual_router 6889 * Virtual Router ID 6890 * Range is 0..cap_max_virtual_routers-1 6891 * Access: Index 6892 */ 6893 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6894 6895 /* reg_raleu_adjacency_index 6896 * Adjacency Index used for matching on the existing entries. 6897 * Access: Index 6898 */ 6899 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6900 6901 /* reg_raleu_ecmp_size 6902 * ECMP Size used for matching on the existing entries. 6903 * Access: Index 6904 */ 6905 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6906 6907 /* reg_raleu_new_adjacency_index 6908 * New Adjacency Index. 6909 * Access: WO 6910 */ 6911 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6912 6913 /* reg_raleu_new_ecmp_size 6914 * New ECMP Size. 6915 * Access: WO 6916 */ 6917 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 6918 6919 static inline void mlxsw_reg_raleu_pack(char *payload, 6920 enum mlxsw_reg_ralxx_protocol protocol, 6921 u16 virtual_router, 6922 u32 adjacency_index, u16 ecmp_size, 6923 u32 new_adjacency_index, 6924 u16 new_ecmp_size) 6925 { 6926 MLXSW_REG_ZERO(raleu, payload); 6927 mlxsw_reg_raleu_protocol_set(payload, protocol); 6928 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 6929 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 6930 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 6931 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 6932 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 6933 } 6934 6935 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 6936 * ---------------------------------------------------------------- 6937 * The RAUHTD register allows dumping entries from the Router Unicast Host 6938 * Table. For a given session an entry is dumped no more than one time. The 6939 * first RAUHTD access after reset is a new session. A session ends when the 6940 * num_rec response is smaller than num_rec request or for IPv4 when the 6941 * num_entries is smaller than 4. The clear activity affect the current session 6942 * or the last session if a new session has not started. 6943 */ 6944 #define MLXSW_REG_RAUHTD_ID 0x8018 6945 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 6946 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 6947 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 6948 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 6949 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 6950 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 6951 6952 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 6953 6954 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 6955 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 6956 6957 /* reg_rauhtd_filter_fields 6958 * if a bit is '0' then the relevant field is ignored and dump is done 6959 * regardless of the field value 6960 * Bit0 - filter by activity: entry_a 6961 * Bit3 - filter by entry rip: entry_rif 6962 * Access: Index 6963 */ 6964 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 6965 6966 enum mlxsw_reg_rauhtd_op { 6967 MLXSW_REG_RAUHTD_OP_DUMP, 6968 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 6969 }; 6970 6971 /* reg_rauhtd_op 6972 * Access: OP 6973 */ 6974 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 6975 6976 /* reg_rauhtd_num_rec 6977 * At request: number of records requested 6978 * At response: number of records dumped 6979 * For IPv4, each record has 4 entries at request and up to 4 entries 6980 * at response 6981 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 6982 * Access: Index 6983 */ 6984 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 6985 6986 /* reg_rauhtd_entry_a 6987 * Dump only if activity has value of entry_a 6988 * Reserved if filter_fields bit0 is '0' 6989 * Access: Index 6990 */ 6991 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 6992 6993 enum mlxsw_reg_rauhtd_type { 6994 MLXSW_REG_RAUHTD_TYPE_IPV4, 6995 MLXSW_REG_RAUHTD_TYPE_IPV6, 6996 }; 6997 6998 /* reg_rauhtd_type 6999 * Dump only if record type is: 7000 * 0 - IPv4 7001 * 1 - IPv6 7002 * Access: Index 7003 */ 7004 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7005 7006 /* reg_rauhtd_entry_rif 7007 * Dump only if RIF has value of entry_rif 7008 * Reserved if filter_fields bit3 is '0' 7009 * Access: Index 7010 */ 7011 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7012 7013 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7014 enum mlxsw_reg_rauhtd_type type) 7015 { 7016 MLXSW_REG_ZERO(rauhtd, payload); 7017 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7018 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7019 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7020 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7021 mlxsw_reg_rauhtd_type_set(payload, type); 7022 } 7023 7024 /* reg_rauhtd_ipv4_rec_num_entries 7025 * Number of valid entries in this record: 7026 * 0 - 1 valid entry 7027 * 1 - 2 valid entries 7028 * 2 - 3 valid entries 7029 * 3 - 4 valid entries 7030 * Access: RO 7031 */ 7032 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7033 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7034 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7035 7036 /* reg_rauhtd_rec_type 7037 * Record type. 7038 * 0 - IPv4 7039 * 1 - IPv6 7040 * Access: RO 7041 */ 7042 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7043 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7044 7045 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7046 7047 /* reg_rauhtd_ipv4_ent_a 7048 * Activity. Set for new entries. Set if a packet lookup has hit on the 7049 * specific entry. 7050 * Access: RO 7051 */ 7052 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7053 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7054 7055 /* reg_rauhtd_ipv4_ent_rif 7056 * Router interface. 7057 * Access: RO 7058 */ 7059 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7060 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7061 7062 /* reg_rauhtd_ipv4_ent_dip 7063 * Destination IPv4 address. 7064 * Access: RO 7065 */ 7066 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7067 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7068 7069 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7070 7071 /* reg_rauhtd_ipv6_ent_a 7072 * Activity. Set for new entries. Set if a packet lookup has hit on the 7073 * specific entry. 7074 * Access: RO 7075 */ 7076 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7077 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7078 7079 /* reg_rauhtd_ipv6_ent_rif 7080 * Router interface. 7081 * Access: RO 7082 */ 7083 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7084 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7085 7086 /* reg_rauhtd_ipv6_ent_dip 7087 * Destination IPv6 address. 7088 * Access: RO 7089 */ 7090 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7091 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7092 7093 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7094 int ent_index, u16 *p_rif, 7095 u32 *p_dip) 7096 { 7097 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7098 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7099 } 7100 7101 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7102 int rec_index, u16 *p_rif, 7103 char *p_dip) 7104 { 7105 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7106 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7107 } 7108 7109 /* RTDP - Routing Tunnel Decap Properties Register 7110 * ----------------------------------------------- 7111 * The RTDP register is used for configuring the tunnel decap properties of NVE 7112 * and IPinIP. 7113 */ 7114 #define MLXSW_REG_RTDP_ID 0x8020 7115 #define MLXSW_REG_RTDP_LEN 0x44 7116 7117 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7118 7119 enum mlxsw_reg_rtdp_type { 7120 MLXSW_REG_RTDP_TYPE_NVE, 7121 MLXSW_REG_RTDP_TYPE_IPIP, 7122 }; 7123 7124 /* reg_rtdp_type 7125 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7126 * Access: RW 7127 */ 7128 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7129 7130 /* reg_rtdp_tunnel_index 7131 * Index to the Decap entry. 7132 * For Spectrum, Index to KVD Linear. 7133 * Access: Index 7134 */ 7135 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7136 7137 /* IPinIP */ 7138 7139 /* reg_rtdp_ipip_irif 7140 * Ingress Router Interface for the overlay router 7141 * Access: RW 7142 */ 7143 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7144 7145 enum mlxsw_reg_rtdp_ipip_sip_check { 7146 /* No sip checks. */ 7147 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7148 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7149 * equal ipv4_usip. 7150 */ 7151 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7152 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7153 * equal ipv6_usip. 7154 */ 7155 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7156 }; 7157 7158 /* reg_rtdp_ipip_sip_check 7159 * SIP check to perform. If decapsulation failed due to these configurations 7160 * then trap_id is IPIP_DECAP_ERROR. 7161 * Access: RW 7162 */ 7163 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7164 7165 /* If set, allow decapsulation of IPinIP (without GRE). */ 7166 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7167 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7168 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7169 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7170 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7171 7172 /* reg_rtdp_ipip_type_check 7173 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7174 * these configurations then trap_id is IPIP_DECAP_ERROR. 7175 * Access: RW 7176 */ 7177 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7178 7179 /* reg_rtdp_ipip_gre_key_check 7180 * Whether GRE key should be checked. When check is enabled: 7181 * - A packet received as IPinIP (without GRE) will always pass. 7182 * - A packet received as IPinGREinIP without a key will not pass the check. 7183 * - A packet received as IPinGREinIP with a key will pass the check only if the 7184 * key in the packet is equal to expected_gre_key. 7185 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7186 * Access: RW 7187 */ 7188 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7189 7190 /* reg_rtdp_ipip_ipv4_usip 7191 * Underlay IPv4 address for ipv4 source address check. 7192 * Reserved when sip_check is not '1'. 7193 * Access: RW 7194 */ 7195 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7196 7197 /* reg_rtdp_ipip_ipv6_usip_ptr 7198 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7199 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7200 * is to the KVD linear. 7201 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7202 * Access: RW 7203 */ 7204 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7205 7206 /* reg_rtdp_ipip_expected_gre_key 7207 * GRE key for checking. 7208 * Reserved when gre_key_check is '0'. 7209 * Access: RW 7210 */ 7211 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7212 7213 static inline void mlxsw_reg_rtdp_pack(char *payload, 7214 enum mlxsw_reg_rtdp_type type, 7215 u32 tunnel_index) 7216 { 7217 MLXSW_REG_ZERO(rtdp, payload); 7218 mlxsw_reg_rtdp_type_set(payload, type); 7219 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7220 } 7221 7222 static inline void 7223 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7224 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7225 unsigned int type_check, bool gre_key_check, 7226 u32 ipv4_usip, u32 expected_gre_key) 7227 { 7228 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7229 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7230 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7231 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7232 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7233 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7234 } 7235 7236 /* RIGR-V2 - Router Interface Group Register Version 2 7237 * --------------------------------------------------- 7238 * The RIGR_V2 register is used to add, remove and query egress interface list 7239 * of a multicast forwarding entry. 7240 */ 7241 #define MLXSW_REG_RIGR2_ID 0x8023 7242 #define MLXSW_REG_RIGR2_LEN 0xB0 7243 7244 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7245 7246 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7247 7248 /* reg_rigr2_rigr_index 7249 * KVD Linear index. 7250 * Access: Index 7251 */ 7252 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7253 7254 /* reg_rigr2_vnext 7255 * Next RIGR Index is valid. 7256 * Access: RW 7257 */ 7258 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7259 7260 /* reg_rigr2_next_rigr_index 7261 * Next RIGR Index. The index is to the KVD linear. 7262 * Reserved when vnxet = '0'. 7263 * Access: RW 7264 */ 7265 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7266 7267 /* reg_rigr2_vrmid 7268 * RMID Index is valid. 7269 * Access: RW 7270 */ 7271 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7272 7273 /* reg_rigr2_rmid_index 7274 * RMID Index. 7275 * Range 0 .. max_mid - 1 7276 * Reserved when vrmid = '0'. 7277 * The index is to the Port Group Table (PGT) 7278 * Access: RW 7279 */ 7280 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7281 7282 /* reg_rigr2_erif_entry_v 7283 * Egress Router Interface is valid. 7284 * Note that low-entries must be set if high-entries are set. For 7285 * example: if erif_entry[2].v is set then erif_entry[1].v and 7286 * erif_entry[0].v must be set. 7287 * Index can be from 0 to cap_mc_erif_list_entries-1 7288 * Access: RW 7289 */ 7290 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7291 7292 /* reg_rigr2_erif_entry_erif 7293 * Egress Router Interface. 7294 * Valid range is from 0 to cap_max_router_interfaces - 1 7295 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7296 * Access: RW 7297 */ 7298 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7299 7300 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7301 bool vnext, u32 next_rigr_index) 7302 { 7303 MLXSW_REG_ZERO(rigr2, payload); 7304 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7305 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7306 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7307 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7308 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7309 } 7310 7311 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7312 bool v, u16 erif) 7313 { 7314 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7315 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7316 } 7317 7318 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7319 * ------------------------------------------------------ 7320 */ 7321 #define MLXSW_REG_RECR2_ID 0x8025 7322 #define MLXSW_REG_RECR2_LEN 0x38 7323 7324 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7325 7326 /* reg_recr2_pp 7327 * Per-port configuration 7328 * Access: Index 7329 */ 7330 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7331 7332 /* reg_recr2_sh 7333 * Symmetric hash 7334 * Access: RW 7335 */ 7336 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7337 7338 /* reg_recr2_seed 7339 * Seed 7340 * Access: RW 7341 */ 7342 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7343 7344 enum { 7345 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7346 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7347 /* Enable IPv4 fields if packet is TCP or UDP */ 7348 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7349 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7350 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7351 /* Enable IPv6 fields if packet is TCP or UDP */ 7352 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7353 /* Enable TCP/UDP header fields if packet is IPv4 */ 7354 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7355 /* Enable TCP/UDP header fields if packet is IPv6 */ 7356 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7357 }; 7358 7359 /* reg_recr2_outer_header_enables 7360 * Bit mask where each bit enables a specific layer to be included in 7361 * the hash calculation. 7362 * Access: RW 7363 */ 7364 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7365 7366 enum { 7367 /* IPv4 Source IP */ 7368 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7369 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7370 /* IPv4 Destination IP */ 7371 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7372 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7373 /* IP Protocol */ 7374 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7375 /* IPv6 Source IP */ 7376 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7377 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7378 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7379 /* IPv6 Destination IP */ 7380 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7381 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7382 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7383 /* IPv6 Next Header */ 7384 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7385 /* IPv6 Flow Label */ 7386 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7387 /* TCP/UDP Source Port */ 7388 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7389 /* TCP/UDP Destination Port */ 7390 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7391 }; 7392 7393 /* reg_recr2_outer_header_fields_enable 7394 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7395 * Access: RW 7396 */ 7397 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7398 7399 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7400 { 7401 int i; 7402 7403 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7404 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7405 true); 7406 } 7407 7408 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7409 { 7410 int i; 7411 7412 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7413 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7414 true); 7415 } 7416 7417 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7418 { 7419 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7420 7421 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7422 7423 i = MLXSW_REG_RECR2_IPV6_SIP8; 7424 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7425 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7426 true); 7427 } 7428 7429 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7430 { 7431 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7432 7433 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7434 7435 i = MLXSW_REG_RECR2_IPV6_DIP8; 7436 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7437 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7438 true); 7439 } 7440 7441 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7442 { 7443 MLXSW_REG_ZERO(recr2, payload); 7444 mlxsw_reg_recr2_pp_set(payload, false); 7445 mlxsw_reg_recr2_sh_set(payload, true); 7446 mlxsw_reg_recr2_seed_set(payload, seed); 7447 } 7448 7449 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7450 * -------------------------------------------------------------- 7451 * The RMFT_V2 register is used to configure and query the multicast table. 7452 */ 7453 #define MLXSW_REG_RMFT2_ID 0x8027 7454 #define MLXSW_REG_RMFT2_LEN 0x174 7455 7456 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7457 7458 /* reg_rmft2_v 7459 * Valid 7460 * Access: RW 7461 */ 7462 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7463 7464 enum mlxsw_reg_rmft2_type { 7465 MLXSW_REG_RMFT2_TYPE_IPV4, 7466 MLXSW_REG_RMFT2_TYPE_IPV6 7467 }; 7468 7469 /* reg_rmft2_type 7470 * Access: Index 7471 */ 7472 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7473 7474 enum mlxsw_sp_reg_rmft2_op { 7475 /* For Write: 7476 * Write operation. Used to write a new entry to the table. All RW 7477 * fields are relevant for new entry. Activity bit is set for new 7478 * entries - Note write with v (Valid) 0 will delete the entry. 7479 * For Query: 7480 * Read operation 7481 */ 7482 MLXSW_REG_RMFT2_OP_READ_WRITE, 7483 }; 7484 7485 /* reg_rmft2_op 7486 * Operation. 7487 * Access: OP 7488 */ 7489 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7490 7491 /* reg_rmft2_a 7492 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7493 * entry. 7494 * Access: RO 7495 */ 7496 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7497 7498 /* reg_rmft2_offset 7499 * Offset within the multicast forwarding table to write to. 7500 * Access: Index 7501 */ 7502 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7503 7504 /* reg_rmft2_virtual_router 7505 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7506 * Access: RW 7507 */ 7508 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7509 7510 enum mlxsw_reg_rmft2_irif_mask { 7511 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7512 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7513 }; 7514 7515 /* reg_rmft2_irif_mask 7516 * Ingress RIF mask. 7517 * Access: RW 7518 */ 7519 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7520 7521 /* reg_rmft2_irif 7522 * Ingress RIF index. 7523 * Access: RW 7524 */ 7525 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7526 7527 /* reg_rmft2_dip{4,6} 7528 * Destination IPv4/6 address 7529 * Access: RW 7530 */ 7531 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7532 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7533 7534 /* reg_rmft2_dip{4,6}_mask 7535 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7536 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7537 * Access: RW 7538 */ 7539 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7540 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7541 7542 /* reg_rmft2_sip{4,6} 7543 * Source IPv4/6 address 7544 * Access: RW 7545 */ 7546 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7547 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7548 7549 /* reg_rmft2_sip{4,6}_mask 7550 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7551 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7552 * Access: RW 7553 */ 7554 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7555 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7556 7557 /* reg_rmft2_flexible_action_set 7558 * ACL action set. The only supported action types in this field and in any 7559 * action-set pointed from here are as follows: 7560 * 00h: ACTION_NULL 7561 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7562 * 03h: ACTION_TRAP 7563 * 06h: ACTION_QOS 7564 * 08h: ACTION_POLICING_MONITORING 7565 * 10h: ACTION_ROUTER_MC 7566 * Access: RW 7567 */ 7568 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7569 MLXSW_REG_FLEX_ACTION_SET_LEN); 7570 7571 static inline void 7572 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7573 u16 virtual_router, 7574 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7575 const char *flex_action_set) 7576 { 7577 MLXSW_REG_ZERO(rmft2, payload); 7578 mlxsw_reg_rmft2_v_set(payload, v); 7579 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7580 mlxsw_reg_rmft2_offset_set(payload, offset); 7581 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7582 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7583 mlxsw_reg_rmft2_irif_set(payload, irif); 7584 if (flex_action_set) 7585 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7586 flex_action_set); 7587 } 7588 7589 static inline void 7590 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7591 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7592 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7593 const char *flexible_action_set) 7594 { 7595 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7596 irif_mask, irif, flexible_action_set); 7597 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7598 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7599 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7600 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7601 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7602 } 7603 7604 static inline void 7605 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7606 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7607 struct in6_addr dip6, struct in6_addr dip6_mask, 7608 struct in6_addr sip6, struct in6_addr sip6_mask, 7609 const char *flexible_action_set) 7610 { 7611 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7612 irif_mask, irif, flexible_action_set); 7613 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7614 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7615 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7616 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7617 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7618 } 7619 7620 /* MFCR - Management Fan Control Register 7621 * -------------------------------------- 7622 * This register controls the settings of the Fan Speed PWM mechanism. 7623 */ 7624 #define MLXSW_REG_MFCR_ID 0x9001 7625 #define MLXSW_REG_MFCR_LEN 0x08 7626 7627 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7628 7629 enum mlxsw_reg_mfcr_pwm_frequency { 7630 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7631 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7632 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7633 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7634 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7635 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7636 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7637 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7638 }; 7639 7640 /* reg_mfcr_pwm_frequency 7641 * Controls the frequency of the PWM signal. 7642 * Access: RW 7643 */ 7644 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7645 7646 #define MLXSW_MFCR_TACHOS_MAX 10 7647 7648 /* reg_mfcr_tacho_active 7649 * Indicates which of the tachometer is active (bit per tachometer). 7650 * Access: RO 7651 */ 7652 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7653 7654 #define MLXSW_MFCR_PWMS_MAX 5 7655 7656 /* reg_mfcr_pwm_active 7657 * Indicates which of the PWM control is active (bit per PWM). 7658 * Access: RO 7659 */ 7660 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7661 7662 static inline void 7663 mlxsw_reg_mfcr_pack(char *payload, 7664 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7665 { 7666 MLXSW_REG_ZERO(mfcr, payload); 7667 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7668 } 7669 7670 static inline void 7671 mlxsw_reg_mfcr_unpack(char *payload, 7672 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7673 u16 *p_tacho_active, u8 *p_pwm_active) 7674 { 7675 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7676 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7677 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7678 } 7679 7680 /* MFSC - Management Fan Speed Control Register 7681 * -------------------------------------------- 7682 * This register controls the settings of the Fan Speed PWM mechanism. 7683 */ 7684 #define MLXSW_REG_MFSC_ID 0x9002 7685 #define MLXSW_REG_MFSC_LEN 0x08 7686 7687 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7688 7689 /* reg_mfsc_pwm 7690 * Fan pwm to control / monitor. 7691 * Access: Index 7692 */ 7693 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7694 7695 /* reg_mfsc_pwm_duty_cycle 7696 * Controls the duty cycle of the PWM. Value range from 0..255 to 7697 * represent duty cycle of 0%...100%. 7698 * Access: RW 7699 */ 7700 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7701 7702 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7703 u8 pwm_duty_cycle) 7704 { 7705 MLXSW_REG_ZERO(mfsc, payload); 7706 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7707 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7708 } 7709 7710 /* MFSM - Management Fan Speed Measurement 7711 * --------------------------------------- 7712 * This register controls the settings of the Tacho measurements and 7713 * enables reading the Tachometer measurements. 7714 */ 7715 #define MLXSW_REG_MFSM_ID 0x9003 7716 #define MLXSW_REG_MFSM_LEN 0x08 7717 7718 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7719 7720 /* reg_mfsm_tacho 7721 * Fan tachometer index. 7722 * Access: Index 7723 */ 7724 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7725 7726 /* reg_mfsm_rpm 7727 * Fan speed (round per minute). 7728 * Access: RO 7729 */ 7730 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7731 7732 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7733 { 7734 MLXSW_REG_ZERO(mfsm, payload); 7735 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7736 } 7737 7738 /* MFSL - Management Fan Speed Limit Register 7739 * ------------------------------------------ 7740 * The Fan Speed Limit register is used to configure the fan speed 7741 * event / interrupt notification mechanism. Fan speed threshold are 7742 * defined for both under-speed and over-speed. 7743 */ 7744 #define MLXSW_REG_MFSL_ID 0x9004 7745 #define MLXSW_REG_MFSL_LEN 0x0C 7746 7747 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7748 7749 /* reg_mfsl_tacho 7750 * Fan tachometer index. 7751 * Access: Index 7752 */ 7753 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7754 7755 /* reg_mfsl_tach_min 7756 * Tachometer minimum value (minimum RPM). 7757 * Access: RW 7758 */ 7759 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7760 7761 /* reg_mfsl_tach_max 7762 * Tachometer maximum value (maximum RPM). 7763 * Access: RW 7764 */ 7765 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7766 7767 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7768 u16 tach_min, u16 tach_max) 7769 { 7770 MLXSW_REG_ZERO(mfsl, payload); 7771 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7772 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7773 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7774 } 7775 7776 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7777 u16 *p_tach_min, u16 *p_tach_max) 7778 { 7779 if (p_tach_min) 7780 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7781 7782 if (p_tach_max) 7783 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7784 } 7785 7786 /* MTCAP - Management Temperature Capabilities 7787 * ------------------------------------------- 7788 * This register exposes the capabilities of the device and 7789 * system temperature sensing. 7790 */ 7791 #define MLXSW_REG_MTCAP_ID 0x9009 7792 #define MLXSW_REG_MTCAP_LEN 0x08 7793 7794 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7795 7796 /* reg_mtcap_sensor_count 7797 * Number of sensors supported by the device. 7798 * This includes the QSFP module sensors (if exists in the QSFP module). 7799 * Access: RO 7800 */ 7801 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7802 7803 /* MTMP - Management Temperature 7804 * ----------------------------- 7805 * This register controls the settings of the temperature measurements 7806 * and enables reading the temperature measurements. Note that temperature 7807 * is in 0.125 degrees Celsius. 7808 */ 7809 #define MLXSW_REG_MTMP_ID 0x900A 7810 #define MLXSW_REG_MTMP_LEN 0x20 7811 7812 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 7813 7814 /* reg_mtmp_sensor_index 7815 * Sensors index to access. 7816 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 7817 * (module 0 is mapped to sensor_index 64). 7818 * Access: Index 7819 */ 7820 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 7821 7822 /* Convert to milli degrees Celsius */ 7823 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 7824 7825 /* reg_mtmp_temperature 7826 * Temperature reading from the sensor. Reading is in 0.125 Celsius 7827 * degrees units. 7828 * Access: RO 7829 */ 7830 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 7831 7832 /* reg_mtmp_mte 7833 * Max Temperature Enable - enables measuring the max temperature on a sensor. 7834 * Access: RW 7835 */ 7836 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 7837 7838 /* reg_mtmp_mtr 7839 * Max Temperature Reset - clears the value of the max temperature register. 7840 * Access: WO 7841 */ 7842 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7843 7844 /* reg_mtmp_max_temperature 7845 * The highest measured temperature from the sensor. 7846 * When the bit mte is cleared, the field max_temperature is reserved. 7847 * Access: RO 7848 */ 7849 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7850 7851 /* reg_mtmp_tee 7852 * Temperature Event Enable. 7853 * 0 - Do not generate event 7854 * 1 - Generate event 7855 * 2 - Generate single event 7856 * Access: RW 7857 */ 7858 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7859 7860 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7861 7862 /* reg_mtmp_temperature_threshold_hi 7863 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7864 * Access: RW 7865 */ 7866 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7867 7868 /* reg_mtmp_temperature_threshold_lo 7869 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7870 * Access: RW 7871 */ 7872 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7873 7874 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7875 7876 /* reg_mtmp_sensor_name 7877 * Sensor Name 7878 * Access: RO 7879 */ 7880 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 7881 7882 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 7883 bool max_temp_enable, 7884 bool max_temp_reset) 7885 { 7886 MLXSW_REG_ZERO(mtmp, payload); 7887 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 7888 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 7889 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 7890 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 7891 MLXSW_REG_MTMP_THRESH_HI); 7892 } 7893 7894 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 7895 unsigned int *p_max_temp, 7896 char *sensor_name) 7897 { 7898 u16 temp; 7899 7900 if (p_temp) { 7901 temp = mlxsw_reg_mtmp_temperature_get(payload); 7902 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7903 } 7904 if (p_max_temp) { 7905 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 7906 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 7907 } 7908 if (sensor_name) 7909 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 7910 } 7911 7912 /* MCIA - Management Cable Info Access 7913 * ----------------------------------- 7914 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 7915 */ 7916 7917 #define MLXSW_REG_MCIA_ID 0x9014 7918 #define MLXSW_REG_MCIA_LEN 0x40 7919 7920 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 7921 7922 /* reg_mcia_l 7923 * Lock bit. Setting this bit will lock the access to the specific 7924 * cable. Used for updating a full page in a cable EPROM. Any access 7925 * other then subsequence writes will fail while the port is locked. 7926 * Access: RW 7927 */ 7928 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 7929 7930 /* reg_mcia_module 7931 * Module number. 7932 * Access: Index 7933 */ 7934 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 7935 7936 /* reg_mcia_status 7937 * Module status. 7938 * Access: RO 7939 */ 7940 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 7941 7942 /* reg_mcia_i2c_device_address 7943 * I2C device address. 7944 * Access: RW 7945 */ 7946 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 7947 7948 /* reg_mcia_page_number 7949 * Page number. 7950 * Access: RW 7951 */ 7952 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 7953 7954 /* reg_mcia_device_address 7955 * Device address. 7956 * Access: RW 7957 */ 7958 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 7959 7960 /* reg_mcia_size 7961 * Number of bytes to read/write (up to 48 bytes). 7962 * Access: RW 7963 */ 7964 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 7965 7966 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 7967 7968 /* reg_mcia_eeprom 7969 * Bytes to read/write. 7970 * Access: RW 7971 */ 7972 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 7973 7974 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 7975 u8 page_number, u16 device_addr, 7976 u8 size, u8 i2c_device_addr) 7977 { 7978 MLXSW_REG_ZERO(mcia, payload); 7979 mlxsw_reg_mcia_module_set(payload, module); 7980 mlxsw_reg_mcia_l_set(payload, lock); 7981 mlxsw_reg_mcia_page_number_set(payload, page_number); 7982 mlxsw_reg_mcia_device_address_set(payload, device_addr); 7983 mlxsw_reg_mcia_size_set(payload, size); 7984 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 7985 } 7986 7987 /* MPAT - Monitoring Port Analyzer Table 7988 * ------------------------------------- 7989 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 7990 * For an enabled analyzer, all fields except e (enable) cannot be modified. 7991 */ 7992 #define MLXSW_REG_MPAT_ID 0x901A 7993 #define MLXSW_REG_MPAT_LEN 0x78 7994 7995 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 7996 7997 /* reg_mpat_pa_id 7998 * Port Analyzer ID. 7999 * Access: Index 8000 */ 8001 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8002 8003 /* reg_mpat_system_port 8004 * A unique port identifier for the final destination of the packet. 8005 * Access: RW 8006 */ 8007 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8008 8009 /* reg_mpat_e 8010 * Enable. Indicating the Port Analyzer is enabled. 8011 * Access: RW 8012 */ 8013 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8014 8015 /* reg_mpat_qos 8016 * Quality Of Service Mode. 8017 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8018 * PCP, DEI, DSCP or VL) are configured. 8019 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8020 * same as in the original packet that has triggered the mirroring. For 8021 * SPAN also the pcp,dei are maintained. 8022 * Access: RW 8023 */ 8024 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8025 8026 /* reg_mpat_be 8027 * Best effort mode. Indicates mirroring traffic should not cause packet 8028 * drop or back pressure, but will discard the mirrored packets. Mirrored 8029 * packets will be forwarded on a best effort manner. 8030 * 0: Do not discard mirrored packets 8031 * 1: Discard mirrored packets if causing congestion 8032 * Access: RW 8033 */ 8034 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8035 8036 enum mlxsw_reg_mpat_span_type { 8037 /* Local SPAN Ethernet. 8038 * The original packet is not encapsulated. 8039 */ 8040 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8041 8042 /* Remote SPAN Ethernet VLAN. 8043 * The packet is forwarded to the monitoring port on the monitoring 8044 * VLAN. 8045 */ 8046 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8047 8048 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8049 * The packet is encapsulated with GRE header. 8050 */ 8051 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8052 }; 8053 8054 /* reg_mpat_span_type 8055 * SPAN type. 8056 * Access: RW 8057 */ 8058 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8059 8060 /* Remote SPAN - Ethernet VLAN 8061 * - - - - - - - - - - - - - - 8062 */ 8063 8064 /* reg_mpat_eth_rspan_vid 8065 * Encapsulation header VLAN ID. 8066 * Access: RW 8067 */ 8068 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8069 8070 /* Encapsulated Remote SPAN - Ethernet L2 8071 * - - - - - - - - - - - - - - - - - - - 8072 */ 8073 8074 enum mlxsw_reg_mpat_eth_rspan_version { 8075 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8076 }; 8077 8078 /* reg_mpat_eth_rspan_version 8079 * RSPAN mirror header version. 8080 * Access: RW 8081 */ 8082 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8083 8084 /* reg_mpat_eth_rspan_mac 8085 * Destination MAC address. 8086 * Access: RW 8087 */ 8088 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8089 8090 /* reg_mpat_eth_rspan_tp 8091 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8092 * Access: RW 8093 */ 8094 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8095 8096 /* Encapsulated Remote SPAN - Ethernet L3 8097 * - - - - - - - - - - - - - - - - - - - 8098 */ 8099 8100 enum mlxsw_reg_mpat_eth_rspan_protocol { 8101 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8102 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8103 }; 8104 8105 /* reg_mpat_eth_rspan_protocol 8106 * SPAN encapsulation protocol. 8107 * Access: RW 8108 */ 8109 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8110 8111 /* reg_mpat_eth_rspan_ttl 8112 * Encapsulation header Time-to-Live/HopLimit. 8113 * Access: RW 8114 */ 8115 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8116 8117 /* reg_mpat_eth_rspan_smac 8118 * Source MAC address 8119 * Access: RW 8120 */ 8121 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8122 8123 /* reg_mpat_eth_rspan_dip* 8124 * Destination IP address. The IP version is configured by protocol. 8125 * Access: RW 8126 */ 8127 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8128 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8129 8130 /* reg_mpat_eth_rspan_sip* 8131 * Source IP address. The IP version is configured by protocol. 8132 * Access: RW 8133 */ 8134 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8135 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8136 8137 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8138 u16 system_port, bool e, 8139 enum mlxsw_reg_mpat_span_type span_type) 8140 { 8141 MLXSW_REG_ZERO(mpat, payload); 8142 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8143 mlxsw_reg_mpat_system_port_set(payload, system_port); 8144 mlxsw_reg_mpat_e_set(payload, e); 8145 mlxsw_reg_mpat_qos_set(payload, 1); 8146 mlxsw_reg_mpat_be_set(payload, 1); 8147 mlxsw_reg_mpat_span_type_set(payload, span_type); 8148 } 8149 8150 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8151 { 8152 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8153 } 8154 8155 static inline void 8156 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8157 enum mlxsw_reg_mpat_eth_rspan_version version, 8158 const char *mac, 8159 bool tp) 8160 { 8161 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8162 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8163 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8164 } 8165 8166 static inline void 8167 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8168 const char *smac, 8169 u32 sip, u32 dip) 8170 { 8171 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8172 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8173 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8174 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8175 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8176 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8177 } 8178 8179 static inline void 8180 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8181 const char *smac, 8182 struct in6_addr sip, struct in6_addr dip) 8183 { 8184 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8185 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8186 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8187 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8188 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8189 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8190 } 8191 8192 /* MPAR - Monitoring Port Analyzer Register 8193 * ---------------------------------------- 8194 * MPAR register is used to query and configure the port analyzer port mirroring 8195 * properties. 8196 */ 8197 #define MLXSW_REG_MPAR_ID 0x901B 8198 #define MLXSW_REG_MPAR_LEN 0x08 8199 8200 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8201 8202 /* reg_mpar_local_port 8203 * The local port to mirror the packets from. 8204 * Access: Index 8205 */ 8206 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8207 8208 enum mlxsw_reg_mpar_i_e { 8209 MLXSW_REG_MPAR_TYPE_EGRESS, 8210 MLXSW_REG_MPAR_TYPE_INGRESS, 8211 }; 8212 8213 /* reg_mpar_i_e 8214 * Ingress/Egress 8215 * Access: Index 8216 */ 8217 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8218 8219 /* reg_mpar_enable 8220 * Enable mirroring 8221 * By default, port mirroring is disabled for all ports. 8222 * Access: RW 8223 */ 8224 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8225 8226 /* reg_mpar_pa_id 8227 * Port Analyzer ID. 8228 * Access: RW 8229 */ 8230 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8231 8232 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8233 enum mlxsw_reg_mpar_i_e i_e, 8234 bool enable, u8 pa_id) 8235 { 8236 MLXSW_REG_ZERO(mpar, payload); 8237 mlxsw_reg_mpar_local_port_set(payload, local_port); 8238 mlxsw_reg_mpar_enable_set(payload, enable); 8239 mlxsw_reg_mpar_i_e_set(payload, i_e); 8240 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8241 } 8242 8243 /* MRSR - Management Reset and Shutdown Register 8244 * --------------------------------------------- 8245 * MRSR register is used to reset or shutdown the switch or 8246 * the entire system (when applicable). 8247 */ 8248 #define MLXSW_REG_MRSR_ID 0x9023 8249 #define MLXSW_REG_MRSR_LEN 0x08 8250 8251 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8252 8253 /* reg_mrsr_command 8254 * Reset/shutdown command 8255 * 0 - do nothing 8256 * 1 - software reset 8257 * Access: WO 8258 */ 8259 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8260 8261 static inline void mlxsw_reg_mrsr_pack(char *payload) 8262 { 8263 MLXSW_REG_ZERO(mrsr, payload); 8264 mlxsw_reg_mrsr_command_set(payload, 1); 8265 } 8266 8267 /* MLCR - Management LED Control Register 8268 * -------------------------------------- 8269 * Controls the system LEDs. 8270 */ 8271 #define MLXSW_REG_MLCR_ID 0x902B 8272 #define MLXSW_REG_MLCR_LEN 0x0C 8273 8274 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8275 8276 /* reg_mlcr_local_port 8277 * Local port number. 8278 * Access: RW 8279 */ 8280 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8281 8282 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8283 8284 /* reg_mlcr_beacon_duration 8285 * Duration of the beacon to be active, in seconds. 8286 * 0x0 - Will turn off the beacon. 8287 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8288 * Access: RW 8289 */ 8290 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8291 8292 /* reg_mlcr_beacon_remain 8293 * Remaining duration of the beacon, in seconds. 8294 * 0xFFFF indicates an infinite amount of time. 8295 * Access: RO 8296 */ 8297 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8298 8299 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8300 bool active) 8301 { 8302 MLXSW_REG_ZERO(mlcr, payload); 8303 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8304 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8305 MLXSW_REG_MLCR_DURATION_MAX : 0); 8306 } 8307 8308 /* MCQI - Management Component Query Information 8309 * --------------------------------------------- 8310 * This register allows querying information about firmware components. 8311 */ 8312 #define MLXSW_REG_MCQI_ID 0x9061 8313 #define MLXSW_REG_MCQI_BASE_LEN 0x18 8314 #define MLXSW_REG_MCQI_CAP_LEN 0x14 8315 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 8316 8317 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 8318 8319 /* reg_mcqi_component_index 8320 * Index of the accessed component. 8321 * Access: Index 8322 */ 8323 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 8324 8325 enum mlxfw_reg_mcqi_info_type { 8326 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 8327 }; 8328 8329 /* reg_mcqi_info_type 8330 * Component properties set. 8331 * Access: RW 8332 */ 8333 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 8334 8335 /* reg_mcqi_offset 8336 * The requested/returned data offset from the section start, given in bytes. 8337 * Must be DWORD aligned. 8338 * Access: RW 8339 */ 8340 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8341 8342 /* reg_mcqi_data_size 8343 * The requested/returned data size, given in bytes. If data_size is not DWORD 8344 * aligned, the last bytes are zero padded. 8345 * Access: RW 8346 */ 8347 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8348 8349 /* reg_mcqi_cap_max_component_size 8350 * Maximum size for this component, given in bytes. 8351 * Access: RO 8352 */ 8353 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8354 8355 /* reg_mcqi_cap_log_mcda_word_size 8356 * Log 2 of the access word size in bytes. Read and write access must be aligned 8357 * to the word size. Write access must be done for an integer number of words. 8358 * Access: RO 8359 */ 8360 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8361 8362 /* reg_mcqi_cap_mcda_max_write_size 8363 * Maximal write size for MCDA register 8364 * Access: RO 8365 */ 8366 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8367 8368 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8369 { 8370 MLXSW_REG_ZERO(mcqi, payload); 8371 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8372 mlxsw_reg_mcqi_info_type_set(payload, 8373 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8374 mlxsw_reg_mcqi_offset_set(payload, 0); 8375 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8376 } 8377 8378 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8379 u32 *p_cap_max_component_size, 8380 u8 *p_cap_log_mcda_word_size, 8381 u16 *p_cap_mcda_max_write_size) 8382 { 8383 *p_cap_max_component_size = 8384 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8385 *p_cap_log_mcda_word_size = 8386 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8387 *p_cap_mcda_max_write_size = 8388 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8389 } 8390 8391 /* MCC - Management Component Control 8392 * ---------------------------------- 8393 * Controls the firmware component and updates the FSM. 8394 */ 8395 #define MLXSW_REG_MCC_ID 0x9062 8396 #define MLXSW_REG_MCC_LEN 0x1C 8397 8398 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8399 8400 enum mlxsw_reg_mcc_instruction { 8401 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8402 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8403 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8404 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8405 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8406 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8407 }; 8408 8409 /* reg_mcc_instruction 8410 * Command to be executed by the FSM. 8411 * Applicable for write operation only. 8412 * Access: RW 8413 */ 8414 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8415 8416 /* reg_mcc_component_index 8417 * Index of the accessed component. Applicable only for commands that 8418 * refer to components. Otherwise, this field is reserved. 8419 * Access: Index 8420 */ 8421 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8422 8423 /* reg_mcc_update_handle 8424 * Token representing the current flow executed by the FSM. 8425 * Access: WO 8426 */ 8427 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8428 8429 /* reg_mcc_error_code 8430 * Indicates the successful completion of the instruction, or the reason it 8431 * failed 8432 * Access: RO 8433 */ 8434 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8435 8436 /* reg_mcc_control_state 8437 * Current FSM state 8438 * Access: RO 8439 */ 8440 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8441 8442 /* reg_mcc_component_size 8443 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8444 * the size may shorten the update time. Value 0x0 means that size is 8445 * unspecified. 8446 * Access: WO 8447 */ 8448 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8449 8450 static inline void mlxsw_reg_mcc_pack(char *payload, 8451 enum mlxsw_reg_mcc_instruction instr, 8452 u16 component_index, u32 update_handle, 8453 u32 component_size) 8454 { 8455 MLXSW_REG_ZERO(mcc, payload); 8456 mlxsw_reg_mcc_instruction_set(payload, instr); 8457 mlxsw_reg_mcc_component_index_set(payload, component_index); 8458 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8459 mlxsw_reg_mcc_component_size_set(payload, component_size); 8460 } 8461 8462 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8463 u8 *p_error_code, u8 *p_control_state) 8464 { 8465 if (p_update_handle) 8466 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8467 if (p_error_code) 8468 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8469 if (p_control_state) 8470 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8471 } 8472 8473 /* MCDA - Management Component Data Access 8474 * --------------------------------------- 8475 * This register allows reading and writing a firmware component. 8476 */ 8477 #define MLXSW_REG_MCDA_ID 0x9063 8478 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8479 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8480 #define MLXSW_REG_MCDA_LEN \ 8481 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8482 8483 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8484 8485 /* reg_mcda_update_handle 8486 * Token representing the current flow executed by the FSM. 8487 * Access: RW 8488 */ 8489 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8490 8491 /* reg_mcda_offset 8492 * Offset of accessed address relative to component start. Accesses must be in 8493 * accordance to log_mcda_word_size in MCQI reg. 8494 * Access: RW 8495 */ 8496 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8497 8498 /* reg_mcda_size 8499 * Size of the data accessed, given in bytes. 8500 * Access: RW 8501 */ 8502 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8503 8504 /* reg_mcda_data 8505 * Data block accessed. 8506 * Access: RW 8507 */ 8508 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8509 8510 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8511 u32 offset, u16 size, u8 *data) 8512 { 8513 int i; 8514 8515 MLXSW_REG_ZERO(mcda, payload); 8516 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8517 mlxsw_reg_mcda_offset_set(payload, offset); 8518 mlxsw_reg_mcda_size_set(payload, size); 8519 8520 for (i = 0; i < size / 4; i++) 8521 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8522 } 8523 8524 /* MPSC - Monitoring Packet Sampling Configuration Register 8525 * -------------------------------------------------------- 8526 * MPSC Register is used to configure the Packet Sampling mechanism. 8527 */ 8528 #define MLXSW_REG_MPSC_ID 0x9080 8529 #define MLXSW_REG_MPSC_LEN 0x1C 8530 8531 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8532 8533 /* reg_mpsc_local_port 8534 * Local port number 8535 * Not supported for CPU port 8536 * Access: Index 8537 */ 8538 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8539 8540 /* reg_mpsc_e 8541 * Enable sampling on port local_port 8542 * Access: RW 8543 */ 8544 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8545 8546 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8547 8548 /* reg_mpsc_rate 8549 * Sampling rate = 1 out of rate packets (with randomization around 8550 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8551 * Access: RW 8552 */ 8553 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8554 8555 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8556 u32 rate) 8557 { 8558 MLXSW_REG_ZERO(mpsc, payload); 8559 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8560 mlxsw_reg_mpsc_e_set(payload, e); 8561 mlxsw_reg_mpsc_rate_set(payload, rate); 8562 } 8563 8564 /* MGPC - Monitoring General Purpose Counter Set Register 8565 * The MGPC register retrieves and sets the General Purpose Counter Set. 8566 */ 8567 #define MLXSW_REG_MGPC_ID 0x9081 8568 #define MLXSW_REG_MGPC_LEN 0x18 8569 8570 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8571 8572 /* reg_mgpc_counter_set_type 8573 * Counter set type. 8574 * Access: OP 8575 */ 8576 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8577 8578 /* reg_mgpc_counter_index 8579 * Counter index. 8580 * Access: Index 8581 */ 8582 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8583 8584 enum mlxsw_reg_mgpc_opcode { 8585 /* Nop */ 8586 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8587 /* Clear counters */ 8588 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8589 }; 8590 8591 /* reg_mgpc_opcode 8592 * Opcode. 8593 * Access: OP 8594 */ 8595 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8596 8597 /* reg_mgpc_byte_counter 8598 * Byte counter value. 8599 * Access: RW 8600 */ 8601 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8602 8603 /* reg_mgpc_packet_counter 8604 * Packet counter value. 8605 * Access: RW 8606 */ 8607 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8608 8609 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8610 enum mlxsw_reg_mgpc_opcode opcode, 8611 enum mlxsw_reg_flow_counter_set_type set_type) 8612 { 8613 MLXSW_REG_ZERO(mgpc, payload); 8614 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8615 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8616 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8617 } 8618 8619 /* MPRS - Monitoring Parsing State Register 8620 * ---------------------------------------- 8621 * The MPRS register is used for setting up the parsing for hash, 8622 * policy-engine and routing. 8623 */ 8624 #define MLXSW_REG_MPRS_ID 0x9083 8625 #define MLXSW_REG_MPRS_LEN 0x14 8626 8627 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 8628 8629 /* reg_mprs_parsing_depth 8630 * Minimum parsing depth. 8631 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 8632 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 8633 * Access: RW 8634 */ 8635 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 8636 8637 /* reg_mprs_parsing_en 8638 * Parsing enable. 8639 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 8640 * NVGRE. Default is enabled. Reserved when SwitchX-2. 8641 * Access: RW 8642 */ 8643 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 8644 8645 /* reg_mprs_vxlan_udp_dport 8646 * VxLAN UDP destination port. 8647 * Used for identifying VxLAN packets and for dport field in 8648 * encapsulation. Default is 4789. 8649 * Access: RW 8650 */ 8651 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 8652 8653 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 8654 u16 vxlan_udp_dport) 8655 { 8656 MLXSW_REG_ZERO(mprs, payload); 8657 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 8658 mlxsw_reg_mprs_parsing_en_set(payload, true); 8659 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 8660 } 8661 8662 /* TNGCR - Tunneling NVE General Configuration Register 8663 * ---------------------------------------------------- 8664 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8665 */ 8666 #define MLXSW_REG_TNGCR_ID 0xA001 8667 #define MLXSW_REG_TNGCR_LEN 0x44 8668 8669 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 8670 8671 enum mlxsw_reg_tngcr_type { 8672 MLXSW_REG_TNGCR_TYPE_VXLAN, 8673 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 8674 MLXSW_REG_TNGCR_TYPE_GENEVE, 8675 MLXSW_REG_TNGCR_TYPE_NVGRE, 8676 }; 8677 8678 /* reg_tngcr_type 8679 * Tunnel type for encapsulation and decapsulation. The types are mutually 8680 * exclusive. 8681 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 8682 * Access: RW 8683 */ 8684 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 8685 8686 /* reg_tngcr_nve_valid 8687 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 8688 * Access: RW 8689 */ 8690 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 8691 8692 /* reg_tngcr_nve_ttl_uc 8693 * The TTL for NVE tunnel encapsulation underlay unicast packets. 8694 * Access: RW 8695 */ 8696 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 8697 8698 /* reg_tngcr_nve_ttl_mc 8699 * The TTL for NVE tunnel encapsulation underlay multicast packets. 8700 * Access: RW 8701 */ 8702 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 8703 8704 enum { 8705 /* Do not copy flow label. Calculate flow label using nve_flh. */ 8706 MLXSW_REG_TNGCR_FL_NO_COPY, 8707 /* Copy flow label from inner packet if packet is IPv6 and 8708 * encapsulation is by IPv6. Otherwise, calculate flow label using 8709 * nve_flh. 8710 */ 8711 MLXSW_REG_TNGCR_FL_COPY, 8712 }; 8713 8714 /* reg_tngcr_nve_flc 8715 * For NVE tunnel encapsulation: Flow label copy from inner packet. 8716 * Access: RW 8717 */ 8718 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 8719 8720 enum { 8721 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 8722 * uses {nve_fl_prefix, nve_fl_suffix}. 8723 */ 8724 MLXSW_REG_TNGCR_FL_NO_HASH, 8725 /* 8 LSBs of the flow label are calculated from ECMP hash of the 8726 * inner packet. 12 MSBs are configured by nve_fl_prefix. 8727 */ 8728 MLXSW_REG_TNGCR_FL_HASH, 8729 }; 8730 8731 /* reg_tngcr_nve_flh 8732 * NVE flow label hash. 8733 * Access: RW 8734 */ 8735 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 8736 8737 /* reg_tngcr_nve_fl_prefix 8738 * NVE flow label prefix. Constant 12 MSBs of the flow label. 8739 * Access: RW 8740 */ 8741 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 8742 8743 /* reg_tngcr_nve_fl_suffix 8744 * NVE flow label suffix. Constant 8 LSBs of the flow label. 8745 * Reserved when nve_flh=1 and for Spectrum. 8746 * Access: RW 8747 */ 8748 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 8749 8750 enum { 8751 /* Source UDP port is fixed (default '0') */ 8752 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 8753 /* Source UDP port is calculated based on hash */ 8754 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 8755 }; 8756 8757 /* reg_tngcr_nve_udp_sport_type 8758 * NVE UDP source port type. 8759 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 8760 * When the source UDP port is calculated based on hash, then the 8 LSBs 8761 * are calculated from hash the 8 MSBs are configured by 8762 * nve_udp_sport_prefix. 8763 * Access: RW 8764 */ 8765 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 8766 8767 /* reg_tngcr_nve_udp_sport_prefix 8768 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 8769 * Reserved when NVE type is NVGRE. 8770 * Access: RW 8771 */ 8772 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 8773 8774 /* reg_tngcr_nve_group_size_mc 8775 * The amount of sequential linked lists of MC entries. The first linked 8776 * list is configured by SFD.underlay_mc_ptr. 8777 * Valid values: 1, 2, 4, 8, 16, 32, 64 8778 * The linked list are configured by TNUMT. 8779 * The hash is set by LAG hash. 8780 * Access: RW 8781 */ 8782 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 8783 8784 /* reg_tngcr_nve_group_size_flood 8785 * The amount of sequential linked lists of flooding entries. The first 8786 * linked list is configured by SFMR.nve_tunnel_flood_ptr 8787 * Valid values: 1, 2, 4, 8, 16, 32, 64 8788 * The linked list are configured by TNUMT. 8789 * The hash is set by LAG hash. 8790 * Access: RW 8791 */ 8792 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 8793 8794 /* reg_tngcr_learn_enable 8795 * During decapsulation, whether to learn from NVE port. 8796 * Reserved when Spectrum-2. See TNPC. 8797 * Access: RW 8798 */ 8799 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 8800 8801 /* reg_tngcr_underlay_virtual_router 8802 * Underlay virtual router. 8803 * Reserved when Spectrum-2. 8804 * Access: RW 8805 */ 8806 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 8807 8808 /* reg_tngcr_underlay_rif 8809 * Underlay ingress router interface. RIF type should be loopback generic. 8810 * Reserved when Spectrum. 8811 * Access: RW 8812 */ 8813 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 8814 8815 /* reg_tngcr_usipv4 8816 * Underlay source IPv4 address of the NVE. 8817 * Access: RW 8818 */ 8819 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 8820 8821 /* reg_tngcr_usipv6 8822 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 8823 * modified under traffic of NVE tunneling encapsulation. 8824 * Access: RW 8825 */ 8826 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 8827 8828 static inline void mlxsw_reg_tngcr_pack(char *payload, 8829 enum mlxsw_reg_tngcr_type type, 8830 bool valid, u8 ttl) 8831 { 8832 MLXSW_REG_ZERO(tngcr, payload); 8833 mlxsw_reg_tngcr_type_set(payload, type); 8834 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 8835 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 8836 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 8837 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 8838 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 8839 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 8840 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 8841 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 8842 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 8843 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 8844 } 8845 8846 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 8847 * ------------------------------------------------------- 8848 * The TNUMT register is for building the underlay MC table. It is used 8849 * for MC, flooding and BC traffic into the NVE tunnel. 8850 */ 8851 #define MLXSW_REG_TNUMT_ID 0xA003 8852 #define MLXSW_REG_TNUMT_LEN 0x20 8853 8854 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 8855 8856 enum mlxsw_reg_tnumt_record_type { 8857 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 8858 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 8859 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 8860 }; 8861 8862 /* reg_tnumt_record_type 8863 * Record type. 8864 * Access: RW 8865 */ 8866 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 8867 8868 enum mlxsw_reg_tnumt_tunnel_port { 8869 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 8870 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 8871 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 8872 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 8873 }; 8874 8875 /* reg_tnumt_tunnel_port 8876 * Tunnel port. 8877 * Access: RW 8878 */ 8879 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 8880 8881 /* reg_tnumt_underlay_mc_ptr 8882 * Index to the underlay multicast table. 8883 * For Spectrum the index is to the KVD linear. 8884 * Access: Index 8885 */ 8886 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 8887 8888 /* reg_tnumt_vnext 8889 * The next_underlay_mc_ptr is valid. 8890 * Access: RW 8891 */ 8892 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 8893 8894 /* reg_tnumt_next_underlay_mc_ptr 8895 * The next index to the underlay multicast table. 8896 * Access: RW 8897 */ 8898 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 8899 8900 /* reg_tnumt_record_size 8901 * Number of IP addresses in the record. 8902 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 8903 * Access: RW 8904 */ 8905 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 8906 8907 /* reg_tnumt_udip 8908 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 8909 * Access: RW 8910 */ 8911 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 8912 8913 /* reg_tnumt_udip_ptr 8914 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 8915 * i >= size. The IPv6 addresses are configured by RIPS. 8916 * Access: RW 8917 */ 8918 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 8919 8920 static inline void mlxsw_reg_tnumt_pack(char *payload, 8921 enum mlxsw_reg_tnumt_record_type type, 8922 enum mlxsw_reg_tnumt_tunnel_port tport, 8923 u32 underlay_mc_ptr, bool vnext, 8924 u32 next_underlay_mc_ptr, 8925 u8 record_size) 8926 { 8927 MLXSW_REG_ZERO(tnumt, payload); 8928 mlxsw_reg_tnumt_record_type_set(payload, type); 8929 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 8930 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 8931 mlxsw_reg_tnumt_vnext_set(payload, vnext); 8932 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 8933 mlxsw_reg_tnumt_record_size_set(payload, record_size); 8934 } 8935 8936 /* TNQCR - Tunneling NVE QoS Configuration Register 8937 * ------------------------------------------------ 8938 * The TNQCR register configures how QoS is set in encapsulation into the 8939 * underlay network. 8940 */ 8941 #define MLXSW_REG_TNQCR_ID 0xA010 8942 #define MLXSW_REG_TNQCR_LEN 0x0C 8943 8944 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 8945 8946 /* reg_tnqcr_enc_set_dscp 8947 * For encapsulation: How to set DSCP field: 8948 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 8949 * (outer) IP header. If there is no IP header, use TNQDR.dscp 8950 * 1 - Set the DSCP field as TNQDR.dscp 8951 * Access: RW 8952 */ 8953 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 8954 8955 static inline void mlxsw_reg_tnqcr_pack(char *payload) 8956 { 8957 MLXSW_REG_ZERO(tnqcr, payload); 8958 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 8959 } 8960 8961 /* TNQDR - Tunneling NVE QoS Default Register 8962 * ------------------------------------------ 8963 * The TNQDR register configures the default QoS settings for NVE 8964 * encapsulation. 8965 */ 8966 #define MLXSW_REG_TNQDR_ID 0xA011 8967 #define MLXSW_REG_TNQDR_LEN 0x08 8968 8969 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 8970 8971 /* reg_tnqdr_local_port 8972 * Local port number (receive port). CPU port is supported. 8973 * Access: Index 8974 */ 8975 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 8976 8977 /* reg_tnqdr_dscp 8978 * For encapsulation, the default DSCP. 8979 * Access: RW 8980 */ 8981 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 8982 8983 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 8984 { 8985 MLXSW_REG_ZERO(tnqdr, payload); 8986 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 8987 mlxsw_reg_tnqdr_dscp_set(payload, 0); 8988 } 8989 8990 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 8991 * -------------------------------------------------------- 8992 * The TNEEM register maps ECN of the IP header at the ingress to the 8993 * encapsulation to the ECN of the underlay network. 8994 */ 8995 #define MLXSW_REG_TNEEM_ID 0xA012 8996 #define MLXSW_REG_TNEEM_LEN 0x0C 8997 8998 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 8999 9000 /* reg_tneem_overlay_ecn 9001 * ECN of the IP header in the overlay network. 9002 * Access: Index 9003 */ 9004 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 9005 9006 /* reg_tneem_underlay_ecn 9007 * ECN of the IP header in the underlay network. 9008 * Access: RW 9009 */ 9010 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 9011 9012 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 9013 u8 underlay_ecn) 9014 { 9015 MLXSW_REG_ZERO(tneem, payload); 9016 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 9017 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 9018 } 9019 9020 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 9021 * -------------------------------------------------------- 9022 * The TNDEM register configures the actions that are done in the 9023 * decapsulation. 9024 */ 9025 #define MLXSW_REG_TNDEM_ID 0xA013 9026 #define MLXSW_REG_TNDEM_LEN 0x0C 9027 9028 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 9029 9030 /* reg_tndem_underlay_ecn 9031 * ECN field of the IP header in the underlay network. 9032 * Access: Index 9033 */ 9034 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 9035 9036 /* reg_tndem_overlay_ecn 9037 * ECN field of the IP header in the overlay network. 9038 * Access: Index 9039 */ 9040 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 9041 9042 /* reg_tndem_eip_ecn 9043 * Egress IP ECN. ECN field of the IP header of the packet which goes out 9044 * from the decapsulation. 9045 * Access: RW 9046 */ 9047 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 9048 9049 /* reg_tndem_trap_en 9050 * Trap enable: 9051 * 0 - No trap due to decap ECN 9052 * 1 - Trap enable with trap_id 9053 * Access: RW 9054 */ 9055 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 9056 9057 /* reg_tndem_trap_id 9058 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 9059 * Reserved when trap_en is '0'. 9060 * Access: RW 9061 */ 9062 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 9063 9064 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 9065 u8 overlay_ecn, u8 ecn, bool trap_en, 9066 u16 trap_id) 9067 { 9068 MLXSW_REG_ZERO(tndem, payload); 9069 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 9070 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 9071 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 9072 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 9073 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 9074 } 9075 9076 /* TNPC - Tunnel Port Configuration Register 9077 * ----------------------------------------- 9078 * The TNPC register is used for tunnel port configuration. 9079 * Reserved when Spectrum. 9080 */ 9081 #define MLXSW_REG_TNPC_ID 0xA020 9082 #define MLXSW_REG_TNPC_LEN 0x18 9083 9084 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 9085 9086 enum mlxsw_reg_tnpc_tunnel_port { 9087 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 9088 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 9089 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 9090 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 9091 }; 9092 9093 /* reg_tnpc_tunnel_port 9094 * Tunnel port. 9095 * Access: Index 9096 */ 9097 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 9098 9099 /* reg_tnpc_learn_enable_v6 9100 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 9101 * Access: RW 9102 */ 9103 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 9104 9105 /* reg_tnpc_learn_enable_v4 9106 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 9107 * Access: RW 9108 */ 9109 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 9110 9111 static inline void mlxsw_reg_tnpc_pack(char *payload, 9112 enum mlxsw_reg_tnpc_tunnel_port tport, 9113 bool learn_enable) 9114 { 9115 MLXSW_REG_ZERO(tnpc, payload); 9116 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 9117 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 9118 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 9119 } 9120 9121 /* TIGCR - Tunneling IPinIP General Configuration Register 9122 * ------------------------------------------------------- 9123 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 9124 */ 9125 #define MLXSW_REG_TIGCR_ID 0xA801 9126 #define MLXSW_REG_TIGCR_LEN 0x10 9127 9128 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 9129 9130 /* reg_tigcr_ipip_ttlc 9131 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 9132 * header. 9133 * Access: RW 9134 */ 9135 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 9136 9137 /* reg_tigcr_ipip_ttl_uc 9138 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 9139 * reg_tigcr_ipip_ttlc is unset. 9140 * Access: RW 9141 */ 9142 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 9143 9144 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 9145 { 9146 MLXSW_REG_ZERO(tigcr, payload); 9147 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 9148 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 9149 } 9150 9151 /* SBPR - Shared Buffer Pools Register 9152 * ----------------------------------- 9153 * The SBPR configures and retrieves the shared buffer pools and configuration. 9154 */ 9155 #define MLXSW_REG_SBPR_ID 0xB001 9156 #define MLXSW_REG_SBPR_LEN 0x14 9157 9158 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 9159 9160 /* shared direstion enum for SBPR, SBCM, SBPM */ 9161 enum mlxsw_reg_sbxx_dir { 9162 MLXSW_REG_SBXX_DIR_INGRESS, 9163 MLXSW_REG_SBXX_DIR_EGRESS, 9164 }; 9165 9166 /* reg_sbpr_dir 9167 * Direction. 9168 * Access: Index 9169 */ 9170 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 9171 9172 /* reg_sbpr_pool 9173 * Pool index. 9174 * Access: Index 9175 */ 9176 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 9177 9178 /* reg_sbpr_infi_size 9179 * Size is infinite. 9180 * Access: RW 9181 */ 9182 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 9183 9184 /* reg_sbpr_size 9185 * Pool size in buffer cells. 9186 * Reserved when infi_size = 1. 9187 * Access: RW 9188 */ 9189 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 9190 9191 enum mlxsw_reg_sbpr_mode { 9192 MLXSW_REG_SBPR_MODE_STATIC, 9193 MLXSW_REG_SBPR_MODE_DYNAMIC, 9194 }; 9195 9196 /* reg_sbpr_mode 9197 * Pool quota calculation mode. 9198 * Access: RW 9199 */ 9200 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 9201 9202 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 9203 enum mlxsw_reg_sbxx_dir dir, 9204 enum mlxsw_reg_sbpr_mode mode, u32 size, 9205 bool infi_size) 9206 { 9207 MLXSW_REG_ZERO(sbpr, payload); 9208 mlxsw_reg_sbpr_pool_set(payload, pool); 9209 mlxsw_reg_sbpr_dir_set(payload, dir); 9210 mlxsw_reg_sbpr_mode_set(payload, mode); 9211 mlxsw_reg_sbpr_size_set(payload, size); 9212 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 9213 } 9214 9215 /* SBCM - Shared Buffer Class Management Register 9216 * ---------------------------------------------- 9217 * The SBCM register configures and retrieves the shared buffer allocation 9218 * and configuration according to Port-PG, including the binding to pool 9219 * and definition of the associated quota. 9220 */ 9221 #define MLXSW_REG_SBCM_ID 0xB002 9222 #define MLXSW_REG_SBCM_LEN 0x28 9223 9224 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 9225 9226 /* reg_sbcm_local_port 9227 * Local port number. 9228 * For Ingress: excludes CPU port and Router port 9229 * For Egress: excludes IP Router 9230 * Access: Index 9231 */ 9232 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 9233 9234 /* reg_sbcm_pg_buff 9235 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 9236 * For PG buffer: range is 0..cap_max_pg_buffers - 1 9237 * For traffic class: range is 0..cap_max_tclass - 1 9238 * Note that when traffic class is in MC aware mode then the traffic 9239 * classes which are MC aware cannot be configured. 9240 * Access: Index 9241 */ 9242 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 9243 9244 /* reg_sbcm_dir 9245 * Direction. 9246 * Access: Index 9247 */ 9248 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 9249 9250 /* reg_sbcm_min_buff 9251 * Minimum buffer size for the limiter, in cells. 9252 * Access: RW 9253 */ 9254 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 9255 9256 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 9257 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 9258 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 9259 9260 /* reg_sbcm_infi_max 9261 * Max buffer is infinite. 9262 * Access: RW 9263 */ 9264 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 9265 9266 /* reg_sbcm_max_buff 9267 * When the pool associated to the port-pg/tclass is configured to 9268 * static, Maximum buffer size for the limiter configured in cells. 9269 * When the pool associated to the port-pg/tclass is configured to 9270 * dynamic, the max_buff holds the "alpha" parameter, supporting 9271 * the following values: 9272 * 0: 0 9273 * i: (1/128)*2^(i-1), for i=1..14 9274 * 0xFF: Infinity 9275 * Reserved when infi_max = 1. 9276 * Access: RW 9277 */ 9278 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 9279 9280 /* reg_sbcm_pool 9281 * Association of the port-priority to a pool. 9282 * Access: RW 9283 */ 9284 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 9285 9286 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 9287 enum mlxsw_reg_sbxx_dir dir, 9288 u32 min_buff, u32 max_buff, 9289 bool infi_max, u8 pool) 9290 { 9291 MLXSW_REG_ZERO(sbcm, payload); 9292 mlxsw_reg_sbcm_local_port_set(payload, local_port); 9293 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 9294 mlxsw_reg_sbcm_dir_set(payload, dir); 9295 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 9296 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 9297 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 9298 mlxsw_reg_sbcm_pool_set(payload, pool); 9299 } 9300 9301 /* SBPM - Shared Buffer Port Management Register 9302 * --------------------------------------------- 9303 * The SBPM register configures and retrieves the shared buffer allocation 9304 * and configuration according to Port-Pool, including the definition 9305 * of the associated quota. 9306 */ 9307 #define MLXSW_REG_SBPM_ID 0xB003 9308 #define MLXSW_REG_SBPM_LEN 0x28 9309 9310 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 9311 9312 /* reg_sbpm_local_port 9313 * Local port number. 9314 * For Ingress: excludes CPU port and Router port 9315 * For Egress: excludes IP Router 9316 * Access: Index 9317 */ 9318 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 9319 9320 /* reg_sbpm_pool 9321 * The pool associated to quota counting on the local_port. 9322 * Access: Index 9323 */ 9324 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 9325 9326 /* reg_sbpm_dir 9327 * Direction. 9328 * Access: Index 9329 */ 9330 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 9331 9332 /* reg_sbpm_buff_occupancy 9333 * Current buffer occupancy in cells. 9334 * Access: RO 9335 */ 9336 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 9337 9338 /* reg_sbpm_clr 9339 * Clear Max Buffer Occupancy 9340 * When this bit is set, max_buff_occupancy field is cleared (and a 9341 * new max value is tracked from the time the clear was performed). 9342 * Access: OP 9343 */ 9344 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 9345 9346 /* reg_sbpm_max_buff_occupancy 9347 * Maximum value of buffer occupancy in cells monitored. Cleared by 9348 * writing to the clr field. 9349 * Access: RO 9350 */ 9351 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 9352 9353 /* reg_sbpm_min_buff 9354 * Minimum buffer size for the limiter, in cells. 9355 * Access: RW 9356 */ 9357 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 9358 9359 /* reg_sbpm_max_buff 9360 * When the pool associated to the port-pg/tclass is configured to 9361 * static, Maximum buffer size for the limiter configured in cells. 9362 * When the pool associated to the port-pg/tclass is configured to 9363 * dynamic, the max_buff holds the "alpha" parameter, supporting 9364 * the following values: 9365 * 0: 0 9366 * i: (1/128)*2^(i-1), for i=1..14 9367 * 0xFF: Infinity 9368 * Access: RW 9369 */ 9370 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 9371 9372 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 9373 enum mlxsw_reg_sbxx_dir dir, bool clr, 9374 u32 min_buff, u32 max_buff) 9375 { 9376 MLXSW_REG_ZERO(sbpm, payload); 9377 mlxsw_reg_sbpm_local_port_set(payload, local_port); 9378 mlxsw_reg_sbpm_pool_set(payload, pool); 9379 mlxsw_reg_sbpm_dir_set(payload, dir); 9380 mlxsw_reg_sbpm_clr_set(payload, clr); 9381 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 9382 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 9383 } 9384 9385 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 9386 u32 *p_max_buff_occupancy) 9387 { 9388 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 9389 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 9390 } 9391 9392 /* SBMM - Shared Buffer Multicast Management Register 9393 * -------------------------------------------------- 9394 * The SBMM register configures and retrieves the shared buffer allocation 9395 * and configuration for MC packets according to Switch-Priority, including 9396 * the binding to pool and definition of the associated quota. 9397 */ 9398 #define MLXSW_REG_SBMM_ID 0xB004 9399 #define MLXSW_REG_SBMM_LEN 0x28 9400 9401 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 9402 9403 /* reg_sbmm_prio 9404 * Switch Priority. 9405 * Access: Index 9406 */ 9407 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 9408 9409 /* reg_sbmm_min_buff 9410 * Minimum buffer size for the limiter, in cells. 9411 * Access: RW 9412 */ 9413 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 9414 9415 /* reg_sbmm_max_buff 9416 * When the pool associated to the port-pg/tclass is configured to 9417 * static, Maximum buffer size for the limiter configured in cells. 9418 * When the pool associated to the port-pg/tclass is configured to 9419 * dynamic, the max_buff holds the "alpha" parameter, supporting 9420 * the following values: 9421 * 0: 0 9422 * i: (1/128)*2^(i-1), for i=1..14 9423 * 0xFF: Infinity 9424 * Access: RW 9425 */ 9426 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 9427 9428 /* reg_sbmm_pool 9429 * Association of the port-priority to a pool. 9430 * Access: RW 9431 */ 9432 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 9433 9434 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 9435 u32 max_buff, u8 pool) 9436 { 9437 MLXSW_REG_ZERO(sbmm, payload); 9438 mlxsw_reg_sbmm_prio_set(payload, prio); 9439 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 9440 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 9441 mlxsw_reg_sbmm_pool_set(payload, pool); 9442 } 9443 9444 /* SBSR - Shared Buffer Status Register 9445 * ------------------------------------ 9446 * The SBSR register retrieves the shared buffer occupancy according to 9447 * Port-Pool. Note that this register enables reading a large amount of data. 9448 * It is the user's responsibility to limit the amount of data to ensure the 9449 * response can match the maximum transfer unit. In case the response exceeds 9450 * the maximum transport unit, it will be truncated with no special notice. 9451 */ 9452 #define MLXSW_REG_SBSR_ID 0xB005 9453 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 9454 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 9455 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 9456 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 9457 MLXSW_REG_SBSR_REC_LEN * \ 9458 MLXSW_REG_SBSR_REC_MAX_COUNT) 9459 9460 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 9461 9462 /* reg_sbsr_clr 9463 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 9464 * field is cleared (and a new max value is tracked from the time the clear 9465 * was performed). 9466 * Access: OP 9467 */ 9468 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 9469 9470 /* reg_sbsr_ingress_port_mask 9471 * Bit vector for all ingress network ports. 9472 * Indicates which of the ports (for which the relevant bit is set) 9473 * are affected by the set operation. Configuration of any other port 9474 * does not change. 9475 * Access: Index 9476 */ 9477 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 9478 9479 /* reg_sbsr_pg_buff_mask 9480 * Bit vector for all switch priority groups. 9481 * Indicates which of the priorities (for which the relevant bit is set) 9482 * are affected by the set operation. Configuration of any other priority 9483 * does not change. 9484 * Range is 0..cap_max_pg_buffers - 1 9485 * Access: Index 9486 */ 9487 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 9488 9489 /* reg_sbsr_egress_port_mask 9490 * Bit vector for all egress network ports. 9491 * Indicates which of the ports (for which the relevant bit is set) 9492 * are affected by the set operation. Configuration of any other port 9493 * does not change. 9494 * Access: Index 9495 */ 9496 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 9497 9498 /* reg_sbsr_tclass_mask 9499 * Bit vector for all traffic classes. 9500 * Indicates which of the traffic classes (for which the relevant bit is 9501 * set) are affected by the set operation. Configuration of any other 9502 * traffic class does not change. 9503 * Range is 0..cap_max_tclass - 1 9504 * Access: Index 9505 */ 9506 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 9507 9508 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 9509 { 9510 MLXSW_REG_ZERO(sbsr, payload); 9511 mlxsw_reg_sbsr_clr_set(payload, clr); 9512 } 9513 9514 /* reg_sbsr_rec_buff_occupancy 9515 * Current buffer occupancy in cells. 9516 * Access: RO 9517 */ 9518 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9519 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 9520 9521 /* reg_sbsr_rec_max_buff_occupancy 9522 * Maximum value of buffer occupancy in cells monitored. Cleared by 9523 * writing to the clr field. 9524 * Access: RO 9525 */ 9526 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9527 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 9528 9529 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 9530 u32 *p_buff_occupancy, 9531 u32 *p_max_buff_occupancy) 9532 { 9533 *p_buff_occupancy = 9534 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 9535 *p_max_buff_occupancy = 9536 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 9537 } 9538 9539 /* SBIB - Shared Buffer Internal Buffer Register 9540 * --------------------------------------------- 9541 * The SBIB register configures per port buffers for internal use. The internal 9542 * buffers consume memory on the port buffers (note that the port buffers are 9543 * used also by PBMC). 9544 * 9545 * For Spectrum this is used for egress mirroring. 9546 */ 9547 #define MLXSW_REG_SBIB_ID 0xB006 9548 #define MLXSW_REG_SBIB_LEN 0x10 9549 9550 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 9551 9552 /* reg_sbib_local_port 9553 * Local port number 9554 * Not supported for CPU port and router port 9555 * Access: Index 9556 */ 9557 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 9558 9559 /* reg_sbib_buff_size 9560 * Units represented in cells 9561 * Allowed range is 0 to (cap_max_headroom_size - 1) 9562 * Default is 0 9563 * Access: RW 9564 */ 9565 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 9566 9567 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 9568 u32 buff_size) 9569 { 9570 MLXSW_REG_ZERO(sbib, payload); 9571 mlxsw_reg_sbib_local_port_set(payload, local_port); 9572 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 9573 } 9574 9575 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 9576 MLXSW_REG(sgcr), 9577 MLXSW_REG(spad), 9578 MLXSW_REG(smid), 9579 MLXSW_REG(sspr), 9580 MLXSW_REG(sfdat), 9581 MLXSW_REG(sfd), 9582 MLXSW_REG(sfn), 9583 MLXSW_REG(spms), 9584 MLXSW_REG(spvid), 9585 MLXSW_REG(spvm), 9586 MLXSW_REG(spaft), 9587 MLXSW_REG(sfgc), 9588 MLXSW_REG(sftr), 9589 MLXSW_REG(sfdf), 9590 MLXSW_REG(sldr), 9591 MLXSW_REG(slcr), 9592 MLXSW_REG(slcor), 9593 MLXSW_REG(spmlr), 9594 MLXSW_REG(svfa), 9595 MLXSW_REG(svpe), 9596 MLXSW_REG(sfmr), 9597 MLXSW_REG(spvmlr), 9598 MLXSW_REG(cwtp), 9599 MLXSW_REG(cwtpm), 9600 MLXSW_REG(pgcr), 9601 MLXSW_REG(ppbt), 9602 MLXSW_REG(pacl), 9603 MLXSW_REG(pagt), 9604 MLXSW_REG(ptar), 9605 MLXSW_REG(ppbs), 9606 MLXSW_REG(prcr), 9607 MLXSW_REG(pefa), 9608 MLXSW_REG(pemrbt), 9609 MLXSW_REG(ptce2), 9610 MLXSW_REG(perpt), 9611 MLXSW_REG(perar), 9612 MLXSW_REG(ptce3), 9613 MLXSW_REG(percr), 9614 MLXSW_REG(pererp), 9615 MLXSW_REG(iedr), 9616 MLXSW_REG(qpts), 9617 MLXSW_REG(qpcr), 9618 MLXSW_REG(qtct), 9619 MLXSW_REG(qeec), 9620 MLXSW_REG(qrwe), 9621 MLXSW_REG(qpdsm), 9622 MLXSW_REG(qpdpm), 9623 MLXSW_REG(qtctm), 9624 MLXSW_REG(pmlp), 9625 MLXSW_REG(pmtu), 9626 MLXSW_REG(ptys), 9627 MLXSW_REG(ppad), 9628 MLXSW_REG(paos), 9629 MLXSW_REG(pfcc), 9630 MLXSW_REG(ppcnt), 9631 MLXSW_REG(plib), 9632 MLXSW_REG(pptb), 9633 MLXSW_REG(pbmc), 9634 MLXSW_REG(pspa), 9635 MLXSW_REG(htgt), 9636 MLXSW_REG(hpkt), 9637 MLXSW_REG(rgcr), 9638 MLXSW_REG(ritr), 9639 MLXSW_REG(rtar), 9640 MLXSW_REG(ratr), 9641 MLXSW_REG(rtdp), 9642 MLXSW_REG(rdpm), 9643 MLXSW_REG(ricnt), 9644 MLXSW_REG(rrcr), 9645 MLXSW_REG(ralta), 9646 MLXSW_REG(ralst), 9647 MLXSW_REG(raltb), 9648 MLXSW_REG(ralue), 9649 MLXSW_REG(rauht), 9650 MLXSW_REG(raleu), 9651 MLXSW_REG(rauhtd), 9652 MLXSW_REG(rigr2), 9653 MLXSW_REG(recr2), 9654 MLXSW_REG(rmft2), 9655 MLXSW_REG(mfcr), 9656 MLXSW_REG(mfsc), 9657 MLXSW_REG(mfsm), 9658 MLXSW_REG(mfsl), 9659 MLXSW_REG(mtcap), 9660 MLXSW_REG(mtmp), 9661 MLXSW_REG(mcia), 9662 MLXSW_REG(mpat), 9663 MLXSW_REG(mpar), 9664 MLXSW_REG(mrsr), 9665 MLXSW_REG(mlcr), 9666 MLXSW_REG(mpsc), 9667 MLXSW_REG(mcqi), 9668 MLXSW_REG(mcc), 9669 MLXSW_REG(mcda), 9670 MLXSW_REG(mgpc), 9671 MLXSW_REG(mprs), 9672 MLXSW_REG(tngcr), 9673 MLXSW_REG(tnumt), 9674 MLXSW_REG(tnqcr), 9675 MLXSW_REG(tnqdr), 9676 MLXSW_REG(tneem), 9677 MLXSW_REG(tndem), 9678 MLXSW_REG(tnpc), 9679 MLXSW_REG(tigcr), 9680 MLXSW_REG(sbpr), 9681 MLXSW_REG(sbcm), 9682 MLXSW_REG(sbpm), 9683 MLXSW_REG(sbmm), 9684 MLXSW_REG(sbsr), 9685 MLXSW_REG(sbib), 9686 }; 9687 9688 static inline const char *mlxsw_reg_id_str(u16 reg_id) 9689 { 9690 const struct mlxsw_reg_info *reg_info; 9691 int i; 9692 9693 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 9694 reg_info = mlxsw_reg_infos[i]; 9695 if (reg_info->id == reg_id) 9696 return reg_info->name; 9697 } 9698 return "*UNKNOWN*"; 9699 } 9700 9701 /* PUDE - Port Up / Down Event 9702 * --------------------------- 9703 * Reports the operational state change of a port. 9704 */ 9705 #define MLXSW_REG_PUDE_LEN 0x10 9706 9707 /* reg_pude_swid 9708 * Switch partition ID with which to associate the port. 9709 * Access: Index 9710 */ 9711 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 9712 9713 /* reg_pude_local_port 9714 * Local port number. 9715 * Access: Index 9716 */ 9717 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 9718 9719 /* reg_pude_admin_status 9720 * Port administrative state (the desired state). 9721 * 1 - Up. 9722 * 2 - Down. 9723 * 3 - Up once. This means that in case of link failure, the port won't go 9724 * into polling mode, but will wait to be re-enabled by software. 9725 * 4 - Disabled by system. Can only be set by hardware. 9726 * Access: RO 9727 */ 9728 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 9729 9730 /* reg_pude_oper_status 9731 * Port operatioanl state. 9732 * 1 - Up. 9733 * 2 - Down. 9734 * 3 - Down by port failure. This means that the device will not let the 9735 * port up again until explicitly specified by software. 9736 * Access: RO 9737 */ 9738 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 9739 9740 #endif 9741