1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_system_port 101 * Unique identifier within the stacking domain that represents all the ports 102 * that are available in the system (external ports). 103 * 104 * Currently, only single-ASIC configurations are supported, so we default to 105 * 1:1 mapping between system ports and local ports. 106 * Access: Index 107 */ 108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 109 110 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 111 { 112 MLXSW_REG_ZERO(sspr, payload); 113 mlxsw_reg_sspr_m_set(payload, 1); 114 mlxsw_reg_sspr_local_port_set(payload, local_port); 115 mlxsw_reg_sspr_system_port_set(payload, local_port); 116 } 117 118 /* SFDAT - Switch Filtering Database Aging Time 119 * -------------------------------------------- 120 * Controls the Switch aging time. Aging time is able to be set per Switch 121 * Partition. 122 */ 123 #define MLXSW_REG_SFDAT_ID 0x2009 124 #define MLXSW_REG_SFDAT_LEN 0x8 125 126 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 127 128 /* reg_sfdat_swid 129 * Switch partition ID. 130 * Access: Index 131 */ 132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 133 134 /* reg_sfdat_age_time 135 * Aging time in seconds 136 * Min - 10 seconds 137 * Max - 1,000,000 seconds 138 * Default is 300 seconds. 139 * Access: RW 140 */ 141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 142 143 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 144 { 145 MLXSW_REG_ZERO(sfdat, payload); 146 mlxsw_reg_sfdat_swid_set(payload, 0); 147 mlxsw_reg_sfdat_age_time_set(payload, age_time); 148 } 149 150 /* SFD - Switch Filtering Database 151 * ------------------------------- 152 * The following register defines the access to the filtering database. 153 * The register supports querying, adding, removing and modifying the database. 154 * The access is optimized for bulk updates in which case more than one 155 * FDB record is present in the same command. 156 */ 157 #define MLXSW_REG_SFD_ID 0x200A 158 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 159 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 160 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 161 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 162 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 163 164 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 165 166 /* reg_sfd_swid 167 * Switch partition ID for queries. Reserved on Write. 168 * Access: Index 169 */ 170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 171 172 enum mlxsw_reg_sfd_op { 173 /* Dump entire FDB a (process according to record_locator) */ 174 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 175 /* Query records by {MAC, VID/FID} value */ 176 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 177 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 178 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 179 /* Test. Response indicates if each of the records could be 180 * added to the FDB. 181 */ 182 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 183 /* Add/modify. Aged-out records cannot be added. This command removes 184 * the learning notification of the {MAC, VID/FID}. Response includes 185 * the entries that were added to the FDB. 186 */ 187 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 188 /* Remove record by {MAC, VID/FID}. This command also removes 189 * the learning notification and aged-out notifications 190 * of the {MAC, VID/FID}. The response provides current (pre-removal) 191 * entries as non-aged-out. 192 */ 193 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 194 /* Remove learned notification by {MAC, VID/FID}. The response provides 195 * the removed learning notification. 196 */ 197 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 198 }; 199 200 /* reg_sfd_op 201 * Operation. 202 * Access: OP 203 */ 204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 205 206 /* reg_sfd_record_locator 207 * Used for querying the FDB. Use record_locator=0 to initiate the 208 * query. When a record is returned, a new record_locator is 209 * returned to be used in the subsequent query. 210 * Reserved for database update. 211 * Access: Index 212 */ 213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 214 215 /* reg_sfd_num_rec 216 * Request: Number of records to read/add/modify/remove 217 * Response: Number of records read/added/replaced/removed 218 * See above description for more details. 219 * Ranges 0..64 220 * Access: RW 221 */ 222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 223 224 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 225 u32 record_locator) 226 { 227 MLXSW_REG_ZERO(sfd, payload); 228 mlxsw_reg_sfd_op_set(payload, op); 229 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 230 } 231 232 /* reg_sfd_rec_swid 233 * Switch partition ID. 234 * Access: Index 235 */ 236 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 237 MLXSW_REG_SFD_REC_LEN, 0x00, false); 238 239 enum mlxsw_reg_sfd_rec_type { 240 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 241 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 242 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 243 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 244 }; 245 246 /* reg_sfd_rec_type 247 * FDB record type. 248 * Access: RW 249 */ 250 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 251 MLXSW_REG_SFD_REC_LEN, 0x00, false); 252 253 enum mlxsw_reg_sfd_rec_policy { 254 /* Replacement disabled, aging disabled. */ 255 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 256 /* (mlag remote): Replacement enabled, aging disabled, 257 * learning notification enabled on this port. 258 */ 259 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 260 /* (ingress device): Replacement enabled, aging enabled. */ 261 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 262 }; 263 264 /* reg_sfd_rec_policy 265 * Policy. 266 * Access: RW 267 */ 268 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 269 MLXSW_REG_SFD_REC_LEN, 0x00, false); 270 271 /* reg_sfd_rec_a 272 * Activity. Set for new static entries. Set for static entries if a frame SMAC 273 * lookup hits on the entry. 274 * To clear the a bit, use "query and clear activity" op. 275 * Access: RO 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_mac 281 * MAC address. 282 * Access: Index 283 */ 284 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 285 MLXSW_REG_SFD_REC_LEN, 0x02); 286 287 enum mlxsw_reg_sfd_rec_action { 288 /* forward */ 289 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 290 /* forward and trap, trap_id is FDB_TRAP */ 291 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 292 /* trap and do not forward, trap_id is FDB_TRAP */ 293 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 294 /* forward to IP router */ 295 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 296 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 297 }; 298 299 /* reg_sfd_rec_action 300 * Action to apply on the packet. 301 * Note: Dynamic entries can only be configured with NOP action. 302 * Access: RW 303 */ 304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 305 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 306 307 /* reg_sfd_uc_sub_port 308 * VEPA channel on local port. 309 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 310 * VEPA is not enabled. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 314 MLXSW_REG_SFD_REC_LEN, 0x08, false); 315 316 /* reg_sfd_uc_set_vid 317 * Set VID. 318 * 0 - Do not update VID. 319 * 1 - Set VID. 320 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 321 * Access: RW 322 * 323 * Note: Reserved when legacy bridge model is used. 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 326 MLXSW_REG_SFD_REC_LEN, 0x08, false); 327 328 /* reg_sfd_uc_fid_vid 329 * Filtering ID or VLAN ID 330 * For SwitchX and SwitchX-2: 331 * - Dynamic entries (policy 2,3) use FID 332 * - Static entries (policy 0) use VID 333 * - When independent learning is configured, VID=FID 334 * For Spectrum: use FID for both Dynamic and Static entries. 335 * VID should not be used. 336 * Access: Index 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 339 MLXSW_REG_SFD_REC_LEN, 0x08, false); 340 341 /* reg_sfd_uc_vid 342 * New VID when set_vid=1. 343 * Access: RW 344 * 345 * Note: Reserved when legacy bridge model is used and when set_vid=0. 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 348 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 349 350 /* reg_sfd_uc_system_port 351 * Unique port identifier for the final destination of the packet. 352 * Access: RW 353 */ 354 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 355 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 356 357 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 358 enum mlxsw_reg_sfd_rec_type rec_type, 359 const char *mac, 360 enum mlxsw_reg_sfd_rec_action action) 361 { 362 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 363 364 if (rec_index >= num_rec) 365 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 366 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 367 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 368 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 369 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 370 } 371 372 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 373 enum mlxsw_reg_sfd_rec_policy policy, 374 const char *mac, u16 fid_vid, u16 vid, 375 enum mlxsw_reg_sfd_rec_action action, 376 u16 local_port) 377 { 378 mlxsw_reg_sfd_rec_pack(payload, rec_index, 379 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 380 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 381 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 382 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 383 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 384 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 385 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 386 } 387 388 /* reg_sfd_uc_lag_sub_port 389 * LAG sub port. 390 * Must be 0 if multichannel VEPA is not enabled. 391 * Access: RW 392 */ 393 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 394 MLXSW_REG_SFD_REC_LEN, 0x08, false); 395 396 /* reg_sfd_uc_lag_set_vid 397 * Set VID. 398 * 0 - Do not update VID. 399 * 1 - Set VID. 400 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 401 * Access: RW 402 * 403 * Note: Reserved when legacy bridge model is used. 404 */ 405 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 406 MLXSW_REG_SFD_REC_LEN, 0x08, false); 407 408 /* reg_sfd_uc_lag_fid_vid 409 * Filtering ID or VLAN ID 410 * For SwitchX and SwitchX-2: 411 * - Dynamic entries (policy 2,3) use FID 412 * - Static entries (policy 0) use VID 413 * - When independent learning is configured, VID=FID 414 * For Spectrum: use FID for both Dynamic and Static entries. 415 * VID should not be used. 416 * Access: Index 417 */ 418 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 419 MLXSW_REG_SFD_REC_LEN, 0x08, false); 420 421 /* reg_sfd_uc_lag_lag_vid 422 * New vlan ID. 423 * Access: RW 424 * 425 * Note: Reserved when legacy bridge model is used and set_vid=0. 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 428 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 429 430 /* reg_sfd_uc_lag_lag_id 431 * LAG Identifier - pointer into the LAG descriptor table. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 435 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 436 437 static inline void 438 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 439 enum mlxsw_reg_sfd_rec_policy policy, 440 const char *mac, u16 fid_vid, 441 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 442 u16 lag_id) 443 { 444 mlxsw_reg_sfd_rec_pack(payload, rec_index, 445 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 446 mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 451 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 452 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 453 } 454 455 /* reg_sfd_mc_pgi 456 * 457 * Multicast port group index - index into the port group table. 458 * Value 0x1FFF indicates the pgi should point to the MID entry. 459 * For Spectrum this value must be set to 0x1FFF 460 * Access: RW 461 */ 462 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 463 MLXSW_REG_SFD_REC_LEN, 0x08, false); 464 465 /* reg_sfd_mc_fid_vid 466 * 467 * Filtering ID or VLAN ID 468 * Access: Index 469 */ 470 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 471 MLXSW_REG_SFD_REC_LEN, 0x08, false); 472 473 /* reg_sfd_mc_mid 474 * 475 * Multicast identifier - global identifier that represents the multicast 476 * group across all devices. 477 * Access: RW 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 481 482 static inline void 483 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 484 const char *mac, u16 fid_vid, 485 enum mlxsw_reg_sfd_rec_action action, u16 mid) 486 { 487 mlxsw_reg_sfd_rec_pack(payload, rec_index, 488 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 489 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 490 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 491 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 492 } 493 494 /* reg_sfd_uc_tunnel_uip_msb 495 * When protocol is IPv4, the most significant byte of the underlay IPv4 496 * destination IP. 497 * When protocol is IPv6, reserved. 498 * Access: RW 499 */ 500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 501 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 502 503 /* reg_sfd_uc_tunnel_fid 504 * Filtering ID. 505 * Access: Index 506 */ 507 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 508 MLXSW_REG_SFD_REC_LEN, 0x08, false); 509 510 enum mlxsw_reg_sfd_uc_tunnel_protocol { 511 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 512 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 513 }; 514 515 /* reg_sfd_uc_tunnel_protocol 516 * IP protocol. 517 * Access: RW 518 */ 519 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 520 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 521 522 /* reg_sfd_uc_tunnel_uip_lsb 523 * When protocol is IPv4, the least significant bytes of the underlay 524 * IPv4 destination IP. 525 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 526 * which is configured by RIPS. 527 * Access: RW 528 */ 529 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 530 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 531 532 static inline void 533 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 534 enum mlxsw_reg_sfd_rec_policy policy, 535 const char *mac, u16 fid, 536 enum mlxsw_reg_sfd_rec_action action, 537 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 538 { 539 mlxsw_reg_sfd_rec_pack(payload, rec_index, 540 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 541 action); 542 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 543 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 544 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 545 } 546 547 static inline void 548 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 549 enum mlxsw_reg_sfd_rec_policy policy, 550 const char *mac, u16 fid, 551 enum mlxsw_reg_sfd_rec_action action, u32 uip) 552 { 553 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 554 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 555 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 556 action, 557 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 558 } 559 560 static inline void 561 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 562 u16 fid, enum mlxsw_reg_sfd_rec_action action, 563 u32 uip_ptr) 564 { 565 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 566 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 567 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 568 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 569 mac, fid, action, 570 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 571 } 572 573 enum mlxsw_reg_tunnel_port { 574 MLXSW_REG_TUNNEL_PORT_NVE, 575 MLXSW_REG_TUNNEL_PORT_VPLS, 576 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 577 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 578 }; 579 580 /* SFN - Switch FDB Notification Register 581 * ------------------------------------------- 582 * The switch provides notifications on newly learned FDB entries and 583 * aged out entries. The notifications can be polled by software. 584 */ 585 #define MLXSW_REG_SFN_ID 0x200B 586 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 587 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 588 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 589 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 590 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 591 592 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 593 594 /* reg_sfn_swid 595 * Switch partition ID. 596 * Access: Index 597 */ 598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 599 600 /* reg_sfn_end 601 * Forces the current session to end. 602 * Access: OP 603 */ 604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 605 606 /* reg_sfn_num_rec 607 * Request: Number of learned notifications and aged-out notification 608 * records requested. 609 * Response: Number of notification records returned (must be smaller 610 * than or equal to the value requested) 611 * Ranges 0..64 612 * Access: OP 613 */ 614 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 615 616 static inline void mlxsw_reg_sfn_pack(char *payload) 617 { 618 MLXSW_REG_ZERO(sfn, payload); 619 mlxsw_reg_sfn_swid_set(payload, 0); 620 mlxsw_reg_sfn_end_set(payload, 0); 621 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 622 } 623 624 /* reg_sfn_rec_swid 625 * Switch partition ID. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 enum mlxsw_reg_sfn_rec_type { 632 /* MAC addresses learned on a regular port. */ 633 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 634 /* MAC addresses learned on a LAG port. */ 635 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 636 /* Aged-out MAC address on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 638 /* Aged-out MAC address on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 640 /* Learned unicast tunnel record. */ 641 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 642 /* Aged-out unicast tunnel record. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 644 }; 645 646 /* reg_sfn_rec_type 647 * Notification record type. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 651 MLXSW_REG_SFN_REC_LEN, 0x00, false); 652 653 /* reg_sfn_rec_mac 654 * MAC address. 655 * Access: RO 656 */ 657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 658 MLXSW_REG_SFN_REC_LEN, 0x02); 659 660 /* reg_sfn_mac_sub_port 661 * VEPA channel on the local port. 662 * 0 if multichannel VEPA is not enabled. 663 * Access: RO 664 */ 665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 666 MLXSW_REG_SFN_REC_LEN, 0x08, false); 667 668 /* reg_sfn_mac_fid 669 * Filtering identifier. 670 * Access: RO 671 */ 672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 673 MLXSW_REG_SFN_REC_LEN, 0x08, false); 674 675 /* reg_sfn_mac_system_port 676 * Unique port identifier for the final destination of the packet. 677 * Access: RO 678 */ 679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 680 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 681 682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 683 char *mac, u16 *p_vid, 684 u16 *p_local_port) 685 { 686 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 687 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 689 } 690 691 /* reg_sfn_mac_lag_lag_id 692 * LAG ID (pointer into the LAG descriptor table). 693 * Access: RO 694 */ 695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 696 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 697 698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 699 char *mac, u16 *p_vid, 700 u16 *p_lag_id) 701 { 702 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 703 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 705 } 706 707 /* reg_sfn_uc_tunnel_uip_msb 708 * When protocol is IPv4, the most significant byte of the underlay IPv4 709 * address of the remote VTEP. 710 * When protocol is IPv6, reserved. 711 * Access: RO 712 */ 713 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 714 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 715 716 enum mlxsw_reg_sfn_uc_tunnel_protocol { 717 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 718 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 719 }; 720 721 /* reg_sfn_uc_tunnel_protocol 722 * IP protocol. 723 * Access: RO 724 */ 725 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 726 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 727 728 /* reg_sfn_uc_tunnel_uip_lsb 729 * When protocol is IPv4, the least significant bytes of the underlay 730 * IPv4 address of the remote VTEP. 731 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 735 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_port 738 * Tunnel port. 739 * Reserved on Spectrum. 740 * Access: RO 741 */ 742 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 743 MLXSW_REG_SFN_REC_LEN, 0x10, false); 744 745 static inline void 746 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 747 u16 *p_fid, u32 *p_uip, 748 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 749 { 750 u32 uip_msb, uip_lsb; 751 752 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 753 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 754 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 755 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 756 *p_uip = uip_msb << 24 | uip_lsb; 757 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 758 } 759 760 /* SPMS - Switch Port MSTP/RSTP State Register 761 * ------------------------------------------- 762 * Configures the spanning tree state of a physical port. 763 */ 764 #define MLXSW_REG_SPMS_ID 0x200D 765 #define MLXSW_REG_SPMS_LEN 0x404 766 767 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 768 769 /* reg_spms_local_port 770 * Local port number. 771 * Access: Index 772 */ 773 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 774 775 enum mlxsw_reg_spms_state { 776 MLXSW_REG_SPMS_STATE_NO_CHANGE, 777 MLXSW_REG_SPMS_STATE_DISCARDING, 778 MLXSW_REG_SPMS_STATE_LEARNING, 779 MLXSW_REG_SPMS_STATE_FORWARDING, 780 }; 781 782 /* reg_spms_state 783 * Spanning tree state of each VLAN ID (VID) of the local port. 784 * 0 - Do not change spanning tree state (used only when writing). 785 * 1 - Discarding. No learning or forwarding to/from this port (default). 786 * 2 - Learning. Port is learning, but not forwarding. 787 * 3 - Forwarding. Port is learning and forwarding. 788 * Access: RW 789 */ 790 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 791 792 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 793 { 794 MLXSW_REG_ZERO(spms, payload); 795 mlxsw_reg_spms_local_port_set(payload, local_port); 796 } 797 798 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 799 enum mlxsw_reg_spms_state state) 800 { 801 mlxsw_reg_spms_state_set(payload, vid, state); 802 } 803 804 /* SPVID - Switch Port VID 805 * ----------------------- 806 * The switch port VID configures the default VID for a port. 807 */ 808 #define MLXSW_REG_SPVID_ID 0x200E 809 #define MLXSW_REG_SPVID_LEN 0x08 810 811 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 812 813 /* reg_spvid_tport 814 * Port is tunnel port. 815 * Reserved when SwitchX/-2 or Spectrum-1. 816 * Access: Index 817 */ 818 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 819 820 /* reg_spvid_local_port 821 * When tport = 0: Local port number. Not supported for CPU port. 822 * When tport = 1: Tunnel port. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 826 827 /* reg_spvid_sub_port 828 * Virtual port within the physical port. 829 * Should be set to 0 when virtual ports are not enabled on the port. 830 * Access: Index 831 */ 832 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 833 834 /* reg_spvid_egr_et_set 835 * When VLAN is pushed at ingress (for untagged packets or for 836 * QinQ push mode) then the EtherType is decided at the egress port. 837 * Reserved when Spectrum-1. 838 * Access: RW 839 */ 840 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 841 842 /* reg_spvid_et_vlan 843 * EtherType used for when VLAN is pushed at ingress (for untagged 844 * packets or for QinQ push mode). 845 * 0: ether_type0 - (default) 846 * 1: ether_type1 847 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 848 * Ethertype IDs are configured by SVER. 849 * Reserved when egr_et_set = 1. 850 * Access: RW 851 */ 852 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 853 854 /* reg_spvid_pvid 855 * Port default VID 856 * Access: RW 857 */ 858 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 859 860 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 861 u8 et_vlan) 862 { 863 MLXSW_REG_ZERO(spvid, payload); 864 mlxsw_reg_spvid_local_port_set(payload, local_port); 865 mlxsw_reg_spvid_pvid_set(payload, pvid); 866 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 867 } 868 869 /* SPVM - Switch Port VLAN Membership 870 * ---------------------------------- 871 * The Switch Port VLAN Membership register configures the VLAN membership 872 * of a port in a VLAN denoted by VID. VLAN membership is managed per 873 * virtual port. The register can be used to add and remove VID(s) from a port. 874 */ 875 #define MLXSW_REG_SPVM_ID 0x200F 876 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 877 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 878 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 879 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 880 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 881 882 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 883 884 /* reg_spvm_pt 885 * Priority tagged. If this bit is set, packets forwarded to the port with 886 * untagged VLAN membership (u bit is set) will be tagged with priority tag 887 * (VID=0) 888 * Access: RW 889 */ 890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 891 892 /* reg_spvm_pte 893 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 894 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 895 * Access: WO 896 */ 897 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 898 899 /* reg_spvm_local_port 900 * Local port number. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 904 905 /* reg_spvm_sub_port 906 * Virtual port within the physical port. 907 * Should be set to 0 when virtual ports are not enabled on the port. 908 * Access: Index 909 */ 910 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 911 912 /* reg_spvm_num_rec 913 * Number of records to update. Each record contains: i, e, u, vid. 914 * Access: OP 915 */ 916 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 917 918 /* reg_spvm_rec_i 919 * Ingress membership in VLAN ID. 920 * Access: Index 921 */ 922 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 923 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 924 MLXSW_REG_SPVM_REC_LEN, 0, false); 925 926 /* reg_spvm_rec_e 927 * Egress membership in VLAN ID. 928 * Access: Index 929 */ 930 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 931 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 932 MLXSW_REG_SPVM_REC_LEN, 0, false); 933 934 /* reg_spvm_rec_u 935 * Untagged - port is an untagged member - egress transmission uses untagged 936 * frames on VID<n> 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 940 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_vid 944 * Egress membership in VLAN ID. 945 * Access: Index 946 */ 947 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 948 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 949 MLXSW_REG_SPVM_REC_LEN, 0, false); 950 951 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 952 u16 vid_begin, u16 vid_end, 953 bool is_member, bool untagged) 954 { 955 int size = vid_end - vid_begin + 1; 956 int i; 957 958 MLXSW_REG_ZERO(spvm, payload); 959 mlxsw_reg_spvm_local_port_set(payload, local_port); 960 mlxsw_reg_spvm_num_rec_set(payload, size); 961 962 for (i = 0; i < size; i++) { 963 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 964 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 965 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 966 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 967 } 968 } 969 970 /* SPAFT - Switch Port Acceptable Frame Types 971 * ------------------------------------------ 972 * The Switch Port Acceptable Frame Types register configures the frame 973 * admittance of the port. 974 */ 975 #define MLXSW_REG_SPAFT_ID 0x2010 976 #define MLXSW_REG_SPAFT_LEN 0x08 977 978 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 979 980 /* reg_spaft_local_port 981 * Local port number. 982 * Access: Index 983 * 984 * Note: CPU port is not supported (all tag types are allowed). 985 */ 986 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 987 988 /* reg_spaft_sub_port 989 * Virtual port within the physical port. 990 * Should be set to 0 when virtual ports are not enabled on the port. 991 * Access: RW 992 */ 993 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 994 995 /* reg_spaft_allow_untagged 996 * When set, untagged frames on the ingress are allowed (default). 997 * Access: RW 998 */ 999 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1000 1001 /* reg_spaft_allow_prio_tagged 1002 * When set, priority tagged frames on the ingress are allowed (default). 1003 * Access: RW 1004 */ 1005 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1006 1007 /* reg_spaft_allow_tagged 1008 * When set, tagged frames on the ingress are allowed (default). 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1012 1013 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1014 bool allow_untagged) 1015 { 1016 MLXSW_REG_ZERO(spaft, payload); 1017 mlxsw_reg_spaft_local_port_set(payload, local_port); 1018 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1019 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1020 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1021 } 1022 1023 /* SFGC - Switch Flooding Group Configuration 1024 * ------------------------------------------ 1025 * The following register controls the association of flooding tables and MIDs 1026 * to packet types used for flooding. 1027 */ 1028 #define MLXSW_REG_SFGC_ID 0x2011 1029 #define MLXSW_REG_SFGC_LEN 0x14 1030 1031 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1032 1033 enum mlxsw_reg_sfgc_type { 1034 MLXSW_REG_SFGC_TYPE_BROADCAST, 1035 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1036 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1037 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1038 MLXSW_REG_SFGC_TYPE_RESERVED, 1039 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1040 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1041 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1042 MLXSW_REG_SFGC_TYPE_MAX, 1043 }; 1044 1045 /* reg_sfgc_type 1046 * The traffic type to reach the flooding table. 1047 * Access: Index 1048 */ 1049 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1050 1051 /* bridge_type is used in SFGC and SFMR. */ 1052 enum mlxsw_reg_bridge_type { 1053 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1054 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1055 }; 1056 1057 /* reg_sfgc_bridge_type 1058 * Access: Index 1059 * 1060 * Note: SwitchX-2 only supports 802.1Q mode. 1061 */ 1062 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1063 1064 enum mlxsw_flood_table_type { 1065 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1066 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1067 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1068 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1069 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1070 }; 1071 1072 /* reg_sfgc_table_type 1073 * See mlxsw_flood_table_type 1074 * Access: RW 1075 * 1076 * Note: FID offset and FID types are not supported in SwitchX-2. 1077 */ 1078 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1079 1080 /* reg_sfgc_flood_table 1081 * Flooding table index to associate with the specific type on the specific 1082 * switch partition. 1083 * Access: RW 1084 */ 1085 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1086 1087 /* reg_sfgc_counter_set_type 1088 * Counter Set Type for flow counters. 1089 * Access: RW 1090 */ 1091 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1092 1093 /* reg_sfgc_counter_index 1094 * Counter Index for flow counters. 1095 * Access: RW 1096 */ 1097 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1098 1099 /* reg_sfgc_mid_base 1100 * MID Base. 1101 * Access: RW 1102 * 1103 * Note: Reserved when legacy bridge model is used. 1104 */ 1105 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1106 1107 static inline void 1108 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1109 enum mlxsw_reg_bridge_type bridge_type, 1110 enum mlxsw_flood_table_type table_type, 1111 unsigned int flood_table, u16 mid_base) 1112 { 1113 MLXSW_REG_ZERO(sfgc, payload); 1114 mlxsw_reg_sfgc_type_set(payload, type); 1115 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1116 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1117 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1118 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1119 } 1120 1121 /* SFDF - Switch Filtering DB Flush 1122 * -------------------------------- 1123 * The switch filtering DB flush register is used to flush the FDB. 1124 * Note that FDB notifications are flushed as well. 1125 */ 1126 #define MLXSW_REG_SFDF_ID 0x2013 1127 #define MLXSW_REG_SFDF_LEN 0x14 1128 1129 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1130 1131 /* reg_sfdf_swid 1132 * Switch partition ID. 1133 * Access: Index 1134 */ 1135 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1136 1137 enum mlxsw_reg_sfdf_flush_type { 1138 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1139 MLXSW_REG_SFDF_FLUSH_PER_FID, 1140 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1141 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1142 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1143 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1144 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1145 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1146 }; 1147 1148 /* reg_sfdf_flush_type 1149 * Flush type. 1150 * 0 - All SWID dynamic entries are flushed. 1151 * 1 - All FID dynamic entries are flushed. 1152 * 2 - All dynamic entries pointing to port are flushed. 1153 * 3 - All FID dynamic entries pointing to port are flushed. 1154 * 4 - All dynamic entries pointing to LAG are flushed. 1155 * 5 - All FID dynamic entries pointing to LAG are flushed. 1156 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1157 * flushed. 1158 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1159 * flushed, per FID. 1160 * Access: RW 1161 */ 1162 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1163 1164 /* reg_sfdf_flush_static 1165 * Static. 1166 * 0 - Flush only dynamic entries. 1167 * 1 - Flush both dynamic and static entries. 1168 * Access: RW 1169 */ 1170 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1171 1172 static inline void mlxsw_reg_sfdf_pack(char *payload, 1173 enum mlxsw_reg_sfdf_flush_type type) 1174 { 1175 MLXSW_REG_ZERO(sfdf, payload); 1176 mlxsw_reg_sfdf_flush_type_set(payload, type); 1177 mlxsw_reg_sfdf_flush_static_set(payload, true); 1178 } 1179 1180 /* reg_sfdf_fid 1181 * FID to flush. 1182 * Access: RW 1183 */ 1184 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1185 1186 /* reg_sfdf_system_port 1187 * Port to flush. 1188 * Access: RW 1189 */ 1190 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1191 1192 /* reg_sfdf_port_fid_system_port 1193 * Port to flush, pointed to by FID. 1194 * Access: RW 1195 */ 1196 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1197 1198 /* reg_sfdf_lag_id 1199 * LAG ID to flush. 1200 * Access: RW 1201 */ 1202 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1203 1204 /* reg_sfdf_lag_fid_lag_id 1205 * LAG ID to flush, pointed to by FID. 1206 * Access: RW 1207 */ 1208 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1209 1210 /* SLDR - Switch LAG Descriptor Register 1211 * ----------------------------------------- 1212 * The switch LAG descriptor register is populated by LAG descriptors. 1213 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1214 * max_lag-1. 1215 */ 1216 #define MLXSW_REG_SLDR_ID 0x2014 1217 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1218 1219 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1220 1221 enum mlxsw_reg_sldr_op { 1222 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1223 MLXSW_REG_SLDR_OP_LAG_CREATE, 1224 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1225 /* Ports that appear in the list have the Distributor enabled */ 1226 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1227 /* Removes ports from the disributor list */ 1228 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1229 }; 1230 1231 /* reg_sldr_op 1232 * Operation. 1233 * Access: RW 1234 */ 1235 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1236 1237 /* reg_sldr_lag_id 1238 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1239 * Access: Index 1240 */ 1241 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1242 1243 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1244 { 1245 MLXSW_REG_ZERO(sldr, payload); 1246 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1247 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1248 } 1249 1250 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1251 { 1252 MLXSW_REG_ZERO(sldr, payload); 1253 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1254 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1255 } 1256 1257 /* reg_sldr_num_ports 1258 * The number of member ports of the LAG. 1259 * Reserved for Create / Destroy operations 1260 * For Add / Remove operations - indicates the number of ports in the list. 1261 * Access: RW 1262 */ 1263 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1264 1265 /* reg_sldr_system_port 1266 * System port. 1267 * Access: RW 1268 */ 1269 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1270 1271 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1272 u16 local_port) 1273 { 1274 MLXSW_REG_ZERO(sldr, payload); 1275 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1276 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1277 mlxsw_reg_sldr_num_ports_set(payload, 1); 1278 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1279 } 1280 1281 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1282 u16 local_port) 1283 { 1284 MLXSW_REG_ZERO(sldr, payload); 1285 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1286 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1287 mlxsw_reg_sldr_num_ports_set(payload, 1); 1288 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1289 } 1290 1291 /* SLCR - Switch LAG Configuration 2 Register 1292 * ------------------------------------------- 1293 * The Switch LAG Configuration register is used for configuring the 1294 * LAG properties of the switch. 1295 */ 1296 #define MLXSW_REG_SLCR_ID 0x2015 1297 #define MLXSW_REG_SLCR_LEN 0x10 1298 1299 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1300 1301 enum mlxsw_reg_slcr_pp { 1302 /* Global Configuration (for all ports) */ 1303 MLXSW_REG_SLCR_PP_GLOBAL, 1304 /* Per port configuration, based on local_port field */ 1305 MLXSW_REG_SLCR_PP_PER_PORT, 1306 }; 1307 1308 /* reg_slcr_pp 1309 * Per Port Configuration 1310 * Note: Reading at Global mode results in reading port 1 configuration. 1311 * Access: Index 1312 */ 1313 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1314 1315 /* reg_slcr_local_port 1316 * Local port number 1317 * Supported from CPU port 1318 * Not supported from router port 1319 * Reserved when pp = Global Configuration 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1323 1324 enum mlxsw_reg_slcr_type { 1325 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1326 MLXSW_REG_SLCR_TYPE_XOR, 1327 MLXSW_REG_SLCR_TYPE_RANDOM, 1328 }; 1329 1330 /* reg_slcr_type 1331 * Hash type 1332 * Access: RW 1333 */ 1334 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1335 1336 /* Ingress port */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1338 /* SMAC - for IPv4 and IPv6 packets */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1340 /* SMAC - for non-IP packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1342 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1343 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1344 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1345 /* DMAC - for IPv4 and IPv6 packets */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1347 /* DMAC - for non-IP packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1349 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1350 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1351 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1352 /* Ethertype - for IPv4 and IPv6 packets */ 1353 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1354 /* Ethertype - for non-IP packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1356 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1357 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1358 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1359 /* VLAN ID - for IPv4 and IPv6 packets */ 1360 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1361 /* VLAN ID - for non-IP packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1363 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1364 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1365 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1366 /* Source IP address (can be IPv4 or IPv6) */ 1367 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1368 /* Destination IP address (can be IPv4 or IPv6) */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1370 /* TCP/UDP source port */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1372 /* TCP/UDP destination port*/ 1373 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1374 /* IPv4 Protocol/IPv6 Next Header */ 1375 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1376 /* IPv6 Flow label */ 1377 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1378 /* SID - FCoE source ID */ 1379 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1380 /* DID - FCoE destination ID */ 1381 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1382 /* OXID - FCoE originator exchange ID */ 1383 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1384 /* Destination QP number - for RoCE packets */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1386 1387 /* reg_slcr_lag_hash 1388 * LAG hashing configuration. This is a bitmask, in which each set 1389 * bit includes the corresponding item in the LAG hash calculation. 1390 * The default lag_hash contains SMAC, DMAC, VLANID and 1391 * Ethertype (for all packet types). 1392 * Access: RW 1393 */ 1394 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1395 1396 /* reg_slcr_seed 1397 * LAG seed value. The seed is the same for all ports. 1398 * Access: RW 1399 */ 1400 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1401 1402 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1403 { 1404 MLXSW_REG_ZERO(slcr, payload); 1405 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1406 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1407 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1408 mlxsw_reg_slcr_seed_set(payload, seed); 1409 } 1410 1411 /* SLCOR - Switch LAG Collector Register 1412 * ------------------------------------- 1413 * The Switch LAG Collector register controls the Local Port membership 1414 * in a LAG and enablement of the collector. 1415 */ 1416 #define MLXSW_REG_SLCOR_ID 0x2016 1417 #define MLXSW_REG_SLCOR_LEN 0x10 1418 1419 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1420 1421 enum mlxsw_reg_slcor_col { 1422 /* Port is added with collector disabled */ 1423 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1424 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1425 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1426 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1427 }; 1428 1429 /* reg_slcor_col 1430 * Collector configuration 1431 * Access: RW 1432 */ 1433 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1434 1435 /* reg_slcor_local_port 1436 * Local port number 1437 * Not supported for CPU port 1438 * Access: Index 1439 */ 1440 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1441 1442 /* reg_slcor_lag_id 1443 * LAG Identifier. Index into the LAG descriptor table. 1444 * Access: Index 1445 */ 1446 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1447 1448 /* reg_slcor_port_index 1449 * Port index in the LAG list. Only valid on Add Port to LAG col. 1450 * Valid range is from 0 to cap_max_lag_members-1 1451 * Access: RW 1452 */ 1453 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1454 1455 static inline void mlxsw_reg_slcor_pack(char *payload, 1456 u16 local_port, u16 lag_id, 1457 enum mlxsw_reg_slcor_col col) 1458 { 1459 MLXSW_REG_ZERO(slcor, payload); 1460 mlxsw_reg_slcor_col_set(payload, col); 1461 mlxsw_reg_slcor_local_port_set(payload, local_port); 1462 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1463 } 1464 1465 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1466 u16 local_port, u16 lag_id, 1467 u8 port_index) 1468 { 1469 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1470 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1471 mlxsw_reg_slcor_port_index_set(payload, port_index); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1475 u16 local_port, u16 lag_id) 1476 { 1477 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1478 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1479 } 1480 1481 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1482 u16 local_port, u16 lag_id) 1483 { 1484 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1485 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1486 } 1487 1488 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1489 u16 local_port, u16 lag_id) 1490 { 1491 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1492 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1493 } 1494 1495 /* SPMLR - Switch Port MAC Learning Register 1496 * ----------------------------------------- 1497 * Controls the Switch MAC learning policy per port. 1498 */ 1499 #define MLXSW_REG_SPMLR_ID 0x2018 1500 #define MLXSW_REG_SPMLR_LEN 0x8 1501 1502 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1503 1504 /* reg_spmlr_local_port 1505 * Local port number. 1506 * Access: Index 1507 */ 1508 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1509 1510 /* reg_spmlr_sub_port 1511 * Virtual port within the physical port. 1512 * Should be set to 0 when virtual ports are not enabled on the port. 1513 * Access: Index 1514 */ 1515 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1516 1517 enum mlxsw_reg_spmlr_learn_mode { 1518 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1519 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1520 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1521 }; 1522 1523 /* reg_spmlr_learn_mode 1524 * Learning mode on the port. 1525 * 0 - Learning disabled. 1526 * 2 - Learning enabled. 1527 * 3 - Security mode. 1528 * 1529 * In security mode the switch does not learn MACs on the port, but uses the 1530 * SMAC to see if it exists on another ingress port. If so, the packet is 1531 * classified as a bad packet and is discarded unless the software registers 1532 * to receive port security error packets usign HPKT. 1533 */ 1534 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1535 1536 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1537 enum mlxsw_reg_spmlr_learn_mode mode) 1538 { 1539 MLXSW_REG_ZERO(spmlr, payload); 1540 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1541 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1542 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1543 } 1544 1545 /* SVFA - Switch VID to FID Allocation Register 1546 * -------------------------------------------- 1547 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1548 * virtualized ports. 1549 */ 1550 #define MLXSW_REG_SVFA_ID 0x201C 1551 #define MLXSW_REG_SVFA_LEN 0x18 1552 1553 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1554 1555 /* reg_svfa_swid 1556 * Switch partition ID. 1557 * Access: Index 1558 */ 1559 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1560 1561 /* reg_svfa_local_port 1562 * Local port number. 1563 * Access: Index 1564 * 1565 * Note: Reserved for 802.1Q FIDs. 1566 */ 1567 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1568 1569 enum mlxsw_reg_svfa_mt { 1570 MLXSW_REG_SVFA_MT_VID_TO_FID, 1571 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1572 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1573 }; 1574 1575 /* reg_svfa_mapping_table 1576 * Mapping table: 1577 * 0 - VID to FID 1578 * 1 - {Port, VID} to FID 1579 * Access: Index 1580 * 1581 * Note: Reserved for SwitchX-2. 1582 */ 1583 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1584 1585 /* reg_svfa_v 1586 * Valid. 1587 * Valid if set. 1588 * Access: RW 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1593 1594 /* reg_svfa_fid 1595 * Filtering ID. 1596 * Access: RW 1597 */ 1598 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1599 1600 /* reg_svfa_vid 1601 * VLAN ID. 1602 * Access: Index 1603 */ 1604 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1605 1606 /* reg_svfa_counter_set_type 1607 * Counter set type for flow counters. 1608 * Access: RW 1609 * 1610 * Note: Reserved for SwitchX-2. 1611 */ 1612 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1613 1614 /* reg_svfa_counter_index 1615 * Counter index for flow counters. 1616 * Access: RW 1617 * 1618 * Note: Reserved for SwitchX-2. 1619 */ 1620 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1621 1622 /* reg_svfa_vni 1623 * Virtual Network Identifier. 1624 * Access: Index 1625 * 1626 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1627 */ 1628 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1629 1630 /* reg_svfa_irif_v 1631 * Ingress RIF valid. 1632 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1633 * 1 - Ingress RIF valid. 1634 * Must not be set for a non enabled RIF. 1635 * Access: RW 1636 * 1637 * Note: Reserved when legacy bridge model is used. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1640 1641 /* reg_svfa_irif 1642 * Ingress RIF (Router Interface). 1643 * Range is 0..cap_max_router_interfaces-1. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1649 1650 static inline void __mlxsw_reg_svfa_pack(char *payload, 1651 enum mlxsw_reg_svfa_mt mt, bool valid, 1652 u16 fid, bool irif_v, u16 irif) 1653 { 1654 MLXSW_REG_ZERO(svfa, payload); 1655 mlxsw_reg_svfa_swid_set(payload, 0); 1656 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1657 mlxsw_reg_svfa_v_set(payload, valid); 1658 mlxsw_reg_svfa_fid_set(payload, fid); 1659 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1660 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1661 } 1662 1663 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1664 bool valid, u16 fid, u16 vid, 1665 bool irif_v, u16 irif) 1666 { 1667 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1668 1669 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1670 mlxsw_reg_svfa_local_port_set(payload, local_port); 1671 mlxsw_reg_svfa_vid_set(payload, vid); 1672 } 1673 1674 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1675 u16 vid, bool irif_v, u16 irif) 1676 { 1677 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1678 1679 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1684 u32 vni, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vni_set(payload, vni); 1690 } 1691 1692 /* SPVTR - Switch Port VLAN Stacking Register 1693 * ------------------------------------------ 1694 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1695 * to enable VLAN stacking. 1696 */ 1697 #define MLXSW_REG_SPVTR_ID 0x201D 1698 #define MLXSW_REG_SPVTR_LEN 0x10 1699 1700 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1701 1702 /* reg_spvtr_tport 1703 * Port is tunnel port. 1704 * Access: Index 1705 * 1706 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1707 */ 1708 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1709 1710 /* reg_spvtr_local_port 1711 * When tport = 0: local port number (Not supported from/to CPU). 1712 * When tport = 1: tunnel port. 1713 * Access: Index 1714 */ 1715 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1716 1717 /* reg_spvtr_ippe 1718 * Ingress Port Prio Mode Update Enable. 1719 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1720 * Reserved on Get operations. 1721 * Access: OP 1722 */ 1723 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1724 1725 /* reg_spvtr_ipve 1726 * Ingress Port VID Mode Update Enable. 1727 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1728 * field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1733 1734 /* reg_spvtr_epve 1735 * Egress Port VID Mode Update Enable. 1736 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1737 * field. 1738 * Access: OP 1739 */ 1740 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1741 1742 /* reg_spvtr_ipprio_mode 1743 * Ingress Port Priority Mode. 1744 * This controls the PCP and DEI of the new outer VLAN 1745 * Note: for SwitchX/-2 the DEI is not affected. 1746 * 0: use port default PCP and DEI (configured by QPDPC). 1747 * 1: use C-VLAN PCP and DEI. 1748 * Has no effect when ipvid_mode = 0. 1749 * Reserved when tport = 1. 1750 * Access: RW 1751 */ 1752 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1753 1754 enum mlxsw_reg_spvtr_ipvid_mode { 1755 /* IEEE Compliant PVID (default) */ 1756 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1757 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1758 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1759 /* Always push VLAN (also for prio tagged packets) */ 1760 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1761 }; 1762 1763 /* reg_spvtr_ipvid_mode 1764 * Ingress Port VLAN-ID Mode. 1765 * For Spectrum family, this affects the values of SPVM.i 1766 * Access: RW 1767 */ 1768 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1769 1770 enum mlxsw_reg_spvtr_epvid_mode { 1771 /* IEEE Compliant VLAN membership */ 1772 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1773 /* Pop VLAN (for VLAN stacking) */ 1774 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1775 }; 1776 1777 /* reg_spvtr_epvid_mode 1778 * Egress Port VLAN-ID Mode. 1779 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1780 * Access: WO 1781 */ 1782 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1783 1784 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1785 u16 local_port, 1786 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1787 { 1788 MLXSW_REG_ZERO(spvtr, payload); 1789 mlxsw_reg_spvtr_tport_set(payload, tport); 1790 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1791 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1792 mlxsw_reg_spvtr_ipve_set(payload, true); 1793 } 1794 1795 /* SVPE - Switch Virtual-Port Enabling Register 1796 * -------------------------------------------- 1797 * Enables port virtualization. 1798 */ 1799 #define MLXSW_REG_SVPE_ID 0x201E 1800 #define MLXSW_REG_SVPE_LEN 0x4 1801 1802 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1803 1804 /* reg_svpe_local_port 1805 * Local port number 1806 * Access: Index 1807 * 1808 * Note: CPU port is not supported (uses VLAN mode only). 1809 */ 1810 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1811 1812 /* reg_svpe_vp_en 1813 * Virtual port enable. 1814 * 0 - Disable, VLAN mode (VID to FID). 1815 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1816 * Access: RW 1817 */ 1818 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1819 1820 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1821 bool enable) 1822 { 1823 MLXSW_REG_ZERO(svpe, payload); 1824 mlxsw_reg_svpe_local_port_set(payload, local_port); 1825 mlxsw_reg_svpe_vp_en_set(payload, enable); 1826 } 1827 1828 /* SFMR - Switch FID Management Register 1829 * ------------------------------------- 1830 * Creates and configures FIDs. 1831 */ 1832 #define MLXSW_REG_SFMR_ID 0x201F 1833 #define MLXSW_REG_SFMR_LEN 0x30 1834 1835 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1836 1837 enum mlxsw_reg_sfmr_op { 1838 MLXSW_REG_SFMR_OP_CREATE_FID, 1839 MLXSW_REG_SFMR_OP_DESTROY_FID, 1840 }; 1841 1842 /* reg_sfmr_op 1843 * Operation. 1844 * 0 - Create or edit FID. 1845 * 1 - Destroy FID. 1846 * Access: WO 1847 */ 1848 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1849 1850 /* reg_sfmr_fid 1851 * Filtering ID. 1852 * Access: Index 1853 */ 1854 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1855 1856 /* reg_sfmr_flood_rsp 1857 * Router sub-port flooding table. 1858 * 0 - Regular flooding table. 1859 * 1 - Router sub-port flooding table. For this FID the flooding is per 1860 * router-sub-port local_port. Must not be set for a FID which is not a 1861 * router-sub-port and must be set prior to enabling the relevant RIF. 1862 * Access: RW 1863 * 1864 * Note: Reserved when legacy bridge model is used. 1865 */ 1866 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1867 1868 /* reg_sfmr_flood_bridge_type 1869 * Flood bridge type (see SFGC.bridge_type). 1870 * 0 - type_0. 1871 * 1 - type_1. 1872 * Access: RW 1873 * 1874 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1875 */ 1876 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1877 1878 /* reg_sfmr_fid_offset 1879 * FID offset. 1880 * Used to point into the flooding table selected by SFGC register if 1881 * the table is of type FID-Offset. Otherwise, this field is reserved. 1882 * Access: RW 1883 */ 1884 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1885 1886 /* reg_sfmr_vtfp 1887 * Valid Tunnel Flood Pointer. 1888 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1889 * Access: RW 1890 * 1891 * Note: Reserved for 802.1Q FIDs. 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1894 1895 /* reg_sfmr_nve_tunnel_flood_ptr 1896 * Underlay Flooding and BC Pointer. 1897 * Used as a pointer to the first entry of the group based link lists of 1898 * flooding or BC entries (for NVE tunnels). 1899 * Access: RW 1900 */ 1901 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1902 1903 /* reg_sfmr_vv 1904 * VNI Valid. 1905 * If not set, then vni is reserved. 1906 * Access: RW 1907 * 1908 * Note: Reserved for 802.1Q FIDs. 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1911 1912 /* reg_sfmr_vni 1913 * Virtual Network Identifier. 1914 * When legacy bridge model is used, a given VNI can only be assigned to one 1915 * FID. When unified bridge model is used, it configures only the FID->VNI, 1916 * the VNI->FID is done by SVFA. 1917 * Access: RW 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1920 1921 /* reg_sfmr_irif_v 1922 * Ingress RIF valid. 1923 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1924 * 1 - Ingress RIF valid. 1925 * Must not be set for a non valid RIF. 1926 * Access: RW 1927 * 1928 * Note: Reserved when legacy bridge model is used. 1929 */ 1930 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1931 1932 /* reg_sfmr_irif 1933 * Ingress RIF (Router Interface). 1934 * Range is 0..cap_max_router_interfaces-1. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1940 1941 /* reg_sfmr_smpe_valid 1942 * SMPE is valid. 1943 * Access: RW 1944 * 1945 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1946 * Spectrum-1. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1949 1950 /* reg_sfmr_smpe 1951 * Switch multicast port to egress VID. 1952 * Range is 0..cap_max_rmpe-1 1953 * Access: RW 1954 * 1955 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1956 * Spectrum-1. 1957 */ 1958 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1959 1960 static inline void mlxsw_reg_sfmr_pack(char *payload, 1961 enum mlxsw_reg_sfmr_op op, u16 fid, 1962 u16 fid_offset, bool flood_rsp, 1963 enum mlxsw_reg_bridge_type bridge_type, 1964 bool smpe_valid, u16 smpe) 1965 { 1966 MLXSW_REG_ZERO(sfmr, payload); 1967 mlxsw_reg_sfmr_op_set(payload, op); 1968 mlxsw_reg_sfmr_fid_set(payload, fid); 1969 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1970 mlxsw_reg_sfmr_vtfp_set(payload, false); 1971 mlxsw_reg_sfmr_vv_set(payload, false); 1972 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1973 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1974 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1975 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1976 } 1977 1978 /* SPVMLR - Switch Port VLAN MAC Learning Register 1979 * ----------------------------------------------- 1980 * Controls the switch MAC learning policy per {Port, VID}. 1981 */ 1982 #define MLXSW_REG_SPVMLR_ID 0x2020 1983 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1984 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1985 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1986 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1987 MLXSW_REG_SPVMLR_REC_LEN * \ 1988 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1989 1990 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1991 1992 /* reg_spvmlr_local_port 1993 * Local ingress port. 1994 * Access: Index 1995 * 1996 * Note: CPU port is not supported. 1997 */ 1998 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 1999 2000 /* reg_spvmlr_num_rec 2001 * Number of records to update. 2002 * Access: OP 2003 */ 2004 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2005 2006 /* reg_spvmlr_rec_learn_enable 2007 * 0 - Disable learning for {Port, VID}. 2008 * 1 - Enable learning for {Port, VID}. 2009 * Access: RW 2010 */ 2011 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2012 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2013 2014 /* reg_spvmlr_rec_vid 2015 * VLAN ID to be added/removed from port or for querying. 2016 * Access: Index 2017 */ 2018 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2019 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2020 2021 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2022 u16 vid_begin, u16 vid_end, 2023 bool learn_enable) 2024 { 2025 int num_rec = vid_end - vid_begin + 1; 2026 int i; 2027 2028 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2029 2030 MLXSW_REG_ZERO(spvmlr, payload); 2031 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2032 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2033 2034 for (i = 0; i < num_rec; i++) { 2035 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2036 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2037 } 2038 } 2039 2040 /* SPFSR - Switch Port FDB Security Register 2041 * ----------------------------------------- 2042 * Configures the security mode per port. 2043 */ 2044 #define MLXSW_REG_SPFSR_ID 0x2023 2045 #define MLXSW_REG_SPFSR_LEN 0x08 2046 2047 MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN); 2048 2049 /* reg_spfsr_local_port 2050 * Local port. 2051 * Access: Index 2052 * 2053 * Note: not supported for CPU port. 2054 */ 2055 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12); 2056 2057 /* reg_spfsr_security 2058 * Security checks. 2059 * 0: disabled (default) 2060 * 1: enabled 2061 * Access: RW 2062 */ 2063 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1); 2064 2065 static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port, 2066 bool security) 2067 { 2068 MLXSW_REG_ZERO(spfsr, payload); 2069 mlxsw_reg_spfsr_local_port_set(payload, local_port); 2070 mlxsw_reg_spfsr_security_set(payload, security); 2071 } 2072 2073 /* SPVC - Switch Port VLAN Classification Register 2074 * ----------------------------------------------- 2075 * Configures the port to identify packets as untagged / single tagged / 2076 * double packets based on the packet EtherTypes. 2077 * Ethertype IDs are configured by SVER. 2078 */ 2079 #define MLXSW_REG_SPVC_ID 0x2026 2080 #define MLXSW_REG_SPVC_LEN 0x0C 2081 2082 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2083 2084 /* reg_spvc_local_port 2085 * Local port. 2086 * Access: Index 2087 * 2088 * Note: applies both to Rx port and Tx port, so if a packet traverses 2089 * through Rx port i and a Tx port j then port i and port j must have the 2090 * same configuration. 2091 */ 2092 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2093 2094 /* reg_spvc_inner_et2 2095 * Vlan Tag1 EtherType2 enable. 2096 * Packet is initially classified as double VLAN Tag if in addition to 2097 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2098 * equal to ether_type2. 2099 * 0: disable (default) 2100 * 1: enable 2101 * Access: RW 2102 */ 2103 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2104 2105 /* reg_spvc_et2 2106 * Vlan Tag0 EtherType2 enable. 2107 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2108 * equal to ether_type2. 2109 * 0: disable (default) 2110 * 1: enable 2111 * Access: RW 2112 */ 2113 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2114 2115 /* reg_spvc_inner_et1 2116 * Vlan Tag1 EtherType1 enable. 2117 * Packet is initially classified as double VLAN Tag if in addition to 2118 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2119 * equal to ether_type1. 2120 * 0: disable 2121 * 1: enable (default) 2122 * Access: RW 2123 */ 2124 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2125 2126 /* reg_spvc_et1 2127 * Vlan Tag0 EtherType1 enable. 2128 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2129 * equal to ether_type1. 2130 * 0: disable 2131 * 1: enable (default) 2132 * Access: RW 2133 */ 2134 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2135 2136 /* reg_inner_et0 2137 * Vlan Tag1 EtherType0 enable. 2138 * Packet is initially classified as double VLAN Tag if in addition to 2139 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2140 * equal to ether_type0. 2141 * 0: disable 2142 * 1: enable (default) 2143 * Access: RW 2144 */ 2145 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2146 2147 /* reg_et0 2148 * Vlan Tag0 EtherType0 enable. 2149 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2150 * equal to ether_type0. 2151 * 0: disable 2152 * 1: enable (default) 2153 * Access: RW 2154 */ 2155 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2156 2157 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2158 bool et0) 2159 { 2160 MLXSW_REG_ZERO(spvc, payload); 2161 mlxsw_reg_spvc_local_port_set(payload, local_port); 2162 /* Enable inner_et1 and inner_et0 to enable identification of double 2163 * tagged packets. 2164 */ 2165 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2166 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2167 mlxsw_reg_spvc_et1_set(payload, et1); 2168 mlxsw_reg_spvc_et0_set(payload, et0); 2169 } 2170 2171 /* SPEVET - Switch Port Egress VLAN EtherType 2172 * ------------------------------------------ 2173 * The switch port egress VLAN EtherType configures which EtherType to push at 2174 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2175 * is set. 2176 */ 2177 #define MLXSW_REG_SPEVET_ID 0x202A 2178 #define MLXSW_REG_SPEVET_LEN 0x08 2179 2180 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2181 2182 /* reg_spevet_local_port 2183 * Egress Local port number. 2184 * Not supported to CPU port. 2185 * Access: Index 2186 */ 2187 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2188 2189 /* reg_spevet_et_vlan 2190 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2191 * 0: ether_type0 - (default) 2192 * 1: ether_type1 2193 * 2: ether_type2 2194 * Access: RW 2195 */ 2196 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2197 2198 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2199 u8 et_vlan) 2200 { 2201 MLXSW_REG_ZERO(spevet, payload); 2202 mlxsw_reg_spevet_local_port_set(payload, local_port); 2203 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2204 } 2205 2206 /* SMPE - Switch Multicast Port to Egress VID 2207 * ------------------------------------------ 2208 * The switch multicast port to egress VID maps 2209 * {egress_port, SMPE index} -> {VID}. 2210 */ 2211 #define MLXSW_REG_SMPE_ID 0x202B 2212 #define MLXSW_REG_SMPE_LEN 0x0C 2213 2214 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2215 2216 /* reg_smpe_local_port 2217 * Local port number. 2218 * CPU port is not supported. 2219 * Access: Index 2220 */ 2221 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2222 2223 /* reg_smpe_smpe_index 2224 * Switch multicast port to egress VID. 2225 * Range is 0..cap_max_rmpe-1. 2226 * Access: Index 2227 */ 2228 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2229 2230 /* reg_smpe_evid 2231 * Egress VID. 2232 * Access: RW 2233 */ 2234 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2235 2236 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2237 u16 smpe_index, u16 evid) 2238 { 2239 MLXSW_REG_ZERO(smpe, payload); 2240 mlxsw_reg_smpe_local_port_set(payload, local_port); 2241 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2242 mlxsw_reg_smpe_evid_set(payload, evid); 2243 } 2244 2245 /* SMID-V2 - Switch Multicast ID Version 2 Register 2246 * ------------------------------------------------ 2247 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2248 * of the multicast group within the stacking domain, into a list of local 2249 * ports into which the packet is replicated. 2250 */ 2251 #define MLXSW_REG_SMID2_ID 0x2034 2252 #define MLXSW_REG_SMID2_LEN 0x120 2253 2254 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2255 2256 /* reg_smid2_swid 2257 * Switch partition ID. 2258 * Access: Index 2259 */ 2260 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2261 2262 /* reg_smid2_mid 2263 * Multicast identifier - global identifier that represents the multicast group 2264 * across all devices. 2265 * Access: Index 2266 */ 2267 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2268 2269 /* reg_smid2_smpe_valid 2270 * SMPE is valid. 2271 * When not valid, the egress VID will not be modified by the SMPE table. 2272 * Access: RW 2273 * 2274 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2275 */ 2276 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2277 2278 /* reg_smid2_smpe 2279 * Switch multicast port to egress VID. 2280 * Access: RW 2281 * 2282 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2283 */ 2284 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2285 2286 /* reg_smid2_port 2287 * Local port memebership (1 bit per port). 2288 * Access: RW 2289 */ 2290 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2291 2292 /* reg_smid2_port_mask 2293 * Local port mask (1 bit per port). 2294 * Access: WO 2295 */ 2296 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2297 2298 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2299 bool set, bool smpe_valid, u16 smpe) 2300 { 2301 MLXSW_REG_ZERO(smid2, payload); 2302 mlxsw_reg_smid2_swid_set(payload, 0); 2303 mlxsw_reg_smid2_mid_set(payload, mid); 2304 mlxsw_reg_smid2_port_set(payload, port, set); 2305 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2306 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2307 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2308 } 2309 2310 /* CWTP - Congetion WRED ECN TClass Profile 2311 * ---------------------------------------- 2312 * Configures the profiles for queues of egress port and traffic class 2313 */ 2314 #define MLXSW_REG_CWTP_ID 0x2802 2315 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2316 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2317 #define MLXSW_REG_CWTP_LEN 0x40 2318 2319 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2320 2321 /* reg_cwtp_local_port 2322 * Local port number 2323 * Not supported for CPU port 2324 * Access: Index 2325 */ 2326 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2327 2328 /* reg_cwtp_traffic_class 2329 * Traffic Class to configure 2330 * Access: Index 2331 */ 2332 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2333 2334 /* reg_cwtp_profile_min 2335 * Minimum Average Queue Size of the profile in cells. 2336 * Access: RW 2337 */ 2338 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2339 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2340 2341 /* reg_cwtp_profile_percent 2342 * Percentage of WRED and ECN marking for maximum Average Queue size 2343 * Range is 0 to 100, units of integer percentage 2344 * Access: RW 2345 */ 2346 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2347 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2348 2349 /* reg_cwtp_profile_max 2350 * Maximum Average Queue size of the profile in cells 2351 * Access: RW 2352 */ 2353 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2354 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2355 2356 #define MLXSW_REG_CWTP_MIN_VALUE 64 2357 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2358 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2359 2360 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2361 u8 traffic_class) 2362 { 2363 int i; 2364 2365 MLXSW_REG_ZERO(cwtp, payload); 2366 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2367 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2368 2369 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2370 mlxsw_reg_cwtp_profile_min_set(payload, i, 2371 MLXSW_REG_CWTP_MIN_VALUE); 2372 mlxsw_reg_cwtp_profile_max_set(payload, i, 2373 MLXSW_REG_CWTP_MIN_VALUE); 2374 } 2375 } 2376 2377 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2378 2379 static inline void 2380 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2381 u32 probability) 2382 { 2383 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2384 2385 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2386 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2387 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2388 } 2389 2390 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2391 * --------------------------------------------------- 2392 * The CWTPM register maps each egress port and traffic class to profile num. 2393 */ 2394 #define MLXSW_REG_CWTPM_ID 0x2803 2395 #define MLXSW_REG_CWTPM_LEN 0x44 2396 2397 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2398 2399 /* reg_cwtpm_local_port 2400 * Local port number 2401 * Not supported for CPU port 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2405 2406 /* reg_cwtpm_traffic_class 2407 * Traffic Class to configure 2408 * Access: Index 2409 */ 2410 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2411 2412 /* reg_cwtpm_ew 2413 * Control enablement of WRED for traffic class: 2414 * 0 - Disable 2415 * 1 - Enable 2416 * Access: RW 2417 */ 2418 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2419 2420 /* reg_cwtpm_ee 2421 * Control enablement of ECN for traffic class: 2422 * 0 - Disable 2423 * 1 - Enable 2424 * Access: RW 2425 */ 2426 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2427 2428 /* reg_cwtpm_tcp_g 2429 * TCP Green Profile. 2430 * Index of the profile within {port, traffic class} to use. 2431 * 0 for disabling both WRED and ECN for this type of traffic. 2432 * Access: RW 2433 */ 2434 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2435 2436 /* reg_cwtpm_tcp_y 2437 * TCP Yellow Profile. 2438 * Index of the profile within {port, traffic class} to use. 2439 * 0 for disabling both WRED and ECN for this type of traffic. 2440 * Access: RW 2441 */ 2442 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2443 2444 /* reg_cwtpm_tcp_r 2445 * TCP Red Profile. 2446 * Index of the profile within {port, traffic class} to use. 2447 * 0 for disabling both WRED and ECN for this type of traffic. 2448 * Access: RW 2449 */ 2450 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2451 2452 /* reg_cwtpm_ntcp_g 2453 * Non-TCP Green Profile. 2454 * Index of the profile within {port, traffic class} to use. 2455 * 0 for disabling both WRED and ECN for this type of traffic. 2456 * Access: RW 2457 */ 2458 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2459 2460 /* reg_cwtpm_ntcp_y 2461 * Non-TCP Yellow Profile. 2462 * Index of the profile within {port, traffic class} to use. 2463 * 0 for disabling both WRED and ECN for this type of traffic. 2464 * Access: RW 2465 */ 2466 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2467 2468 /* reg_cwtpm_ntcp_r 2469 * Non-TCP Red Profile. 2470 * Index of the profile within {port, traffic class} to use. 2471 * 0 for disabling both WRED and ECN for this type of traffic. 2472 * Access: RW 2473 */ 2474 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2475 2476 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2477 2478 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2479 u8 traffic_class, u8 profile, 2480 bool wred, bool ecn) 2481 { 2482 MLXSW_REG_ZERO(cwtpm, payload); 2483 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2484 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2485 mlxsw_reg_cwtpm_ew_set(payload, wred); 2486 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2487 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2488 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2489 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2490 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2491 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2492 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2493 } 2494 2495 /* PGCR - Policy-Engine General Configuration Register 2496 * --------------------------------------------------- 2497 * This register configures general Policy-Engine settings. 2498 */ 2499 #define MLXSW_REG_PGCR_ID 0x3001 2500 #define MLXSW_REG_PGCR_LEN 0x20 2501 2502 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2503 2504 /* reg_pgcr_default_action_pointer_base 2505 * Default action pointer base. Each region has a default action pointer 2506 * which is equal to default_action_pointer_base + region_id. 2507 * Access: RW 2508 */ 2509 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2510 2511 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2512 { 2513 MLXSW_REG_ZERO(pgcr, payload); 2514 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2515 } 2516 2517 /* PPBT - Policy-Engine Port Binding Table 2518 * --------------------------------------- 2519 * This register is used for configuration of the Port Binding Table. 2520 */ 2521 #define MLXSW_REG_PPBT_ID 0x3002 2522 #define MLXSW_REG_PPBT_LEN 0x14 2523 2524 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2525 2526 enum mlxsw_reg_pxbt_e { 2527 MLXSW_REG_PXBT_E_IACL, 2528 MLXSW_REG_PXBT_E_EACL, 2529 }; 2530 2531 /* reg_ppbt_e 2532 * Access: Index 2533 */ 2534 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2535 2536 enum mlxsw_reg_pxbt_op { 2537 MLXSW_REG_PXBT_OP_BIND, 2538 MLXSW_REG_PXBT_OP_UNBIND, 2539 }; 2540 2541 /* reg_ppbt_op 2542 * Access: RW 2543 */ 2544 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2545 2546 /* reg_ppbt_local_port 2547 * Local port. Not including CPU port. 2548 * Access: Index 2549 */ 2550 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2551 2552 /* reg_ppbt_g 2553 * group - When set, the binding is of an ACL group. When cleared, 2554 * the binding is of an ACL. 2555 * Must be set to 1 for Spectrum. 2556 * Access: RW 2557 */ 2558 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2559 2560 /* reg_ppbt_acl_info 2561 * ACL/ACL group identifier. If the g bit is set, this field should hold 2562 * the acl_group_id, else it should hold the acl_id. 2563 * Access: RW 2564 */ 2565 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2566 2567 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2568 enum mlxsw_reg_pxbt_op op, 2569 u16 local_port, u16 acl_info) 2570 { 2571 MLXSW_REG_ZERO(ppbt, payload); 2572 mlxsw_reg_ppbt_e_set(payload, e); 2573 mlxsw_reg_ppbt_op_set(payload, op); 2574 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2575 mlxsw_reg_ppbt_g_set(payload, true); 2576 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2577 } 2578 2579 /* PACL - Policy-Engine ACL Register 2580 * --------------------------------- 2581 * This register is used for configuration of the ACL. 2582 */ 2583 #define MLXSW_REG_PACL_ID 0x3004 2584 #define MLXSW_REG_PACL_LEN 0x70 2585 2586 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2587 2588 /* reg_pacl_v 2589 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2590 * while the ACL is bounded to either a port, VLAN or ACL rule. 2591 * Access: RW 2592 */ 2593 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2594 2595 /* reg_pacl_acl_id 2596 * An identifier representing the ACL (managed by software) 2597 * Range 0 .. cap_max_acl_regions - 1 2598 * Access: Index 2599 */ 2600 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2601 2602 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2603 2604 /* reg_pacl_tcam_region_info 2605 * Opaque object that represents a TCAM region. 2606 * Obtained through PTAR register. 2607 * Access: RW 2608 */ 2609 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2610 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2611 2612 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2613 bool valid, const char *tcam_region_info) 2614 { 2615 MLXSW_REG_ZERO(pacl, payload); 2616 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2617 mlxsw_reg_pacl_v_set(payload, valid); 2618 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2619 } 2620 2621 /* PAGT - Policy-Engine ACL Group Table 2622 * ------------------------------------ 2623 * This register is used for configuration of the ACL Group Table. 2624 */ 2625 #define MLXSW_REG_PAGT_ID 0x3005 2626 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2627 #define MLXSW_REG_PAGT_ACL_LEN 4 2628 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2629 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2630 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2631 2632 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2633 2634 /* reg_pagt_size 2635 * Number of ACLs in the group. 2636 * Size 0 invalidates a group. 2637 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2638 * Total number of ACLs in all groups must be lower or equal 2639 * to cap_max_acl_tot_groups 2640 * Note: a group which is binded must not be invalidated 2641 * Access: Index 2642 */ 2643 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2644 2645 /* reg_pagt_acl_group_id 2646 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2647 * the ACL Group identifier (managed by software). 2648 * Access: Index 2649 */ 2650 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2651 2652 /* reg_pagt_multi 2653 * Multi-ACL 2654 * 0 - This ACL is the last ACL in the multi-ACL 2655 * 1 - This ACL is part of a multi-ACL 2656 * Access: RW 2657 */ 2658 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2659 2660 /* reg_pagt_acl_id 2661 * ACL identifier 2662 * Access: RW 2663 */ 2664 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2665 2666 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2667 { 2668 MLXSW_REG_ZERO(pagt, payload); 2669 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2670 } 2671 2672 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2673 u16 acl_id, bool multi) 2674 { 2675 u8 size = mlxsw_reg_pagt_size_get(payload); 2676 2677 if (index >= size) 2678 mlxsw_reg_pagt_size_set(payload, index + 1); 2679 mlxsw_reg_pagt_multi_set(payload, index, multi); 2680 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2681 } 2682 2683 /* PTAR - Policy-Engine TCAM Allocation Register 2684 * --------------------------------------------- 2685 * This register is used for allocation of regions in the TCAM. 2686 * Note: Query method is not supported on this register. 2687 */ 2688 #define MLXSW_REG_PTAR_ID 0x3006 2689 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2690 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2691 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2692 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2693 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2694 2695 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2696 2697 enum mlxsw_reg_ptar_op { 2698 /* allocate a TCAM region */ 2699 MLXSW_REG_PTAR_OP_ALLOC, 2700 /* resize a TCAM region */ 2701 MLXSW_REG_PTAR_OP_RESIZE, 2702 /* deallocate TCAM region */ 2703 MLXSW_REG_PTAR_OP_FREE, 2704 /* test allocation */ 2705 MLXSW_REG_PTAR_OP_TEST, 2706 }; 2707 2708 /* reg_ptar_op 2709 * Access: OP 2710 */ 2711 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2712 2713 /* reg_ptar_action_set_type 2714 * Type of action set to be used on this region. 2715 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2716 * Access: WO 2717 */ 2718 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2719 2720 enum mlxsw_reg_ptar_key_type { 2721 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2722 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2723 }; 2724 2725 /* reg_ptar_key_type 2726 * TCAM key type for the region. 2727 * Access: WO 2728 */ 2729 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2730 2731 /* reg_ptar_region_size 2732 * TCAM region size. When allocating/resizing this is the requested size, 2733 * the response is the actual size. Note that actual size may be 2734 * larger than requested. 2735 * Allowed range 1 .. cap_max_rules-1 2736 * Reserved during op deallocate. 2737 * Access: WO 2738 */ 2739 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2740 2741 /* reg_ptar_region_id 2742 * Region identifier 2743 * Range 0 .. cap_max_regions-1 2744 * Access: Index 2745 */ 2746 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2747 2748 /* reg_ptar_tcam_region_info 2749 * Opaque object that represents the TCAM region. 2750 * Returned when allocating a region. 2751 * Provided by software for ACL generation and region deallocation and resize. 2752 * Access: RW 2753 */ 2754 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2755 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2756 2757 /* reg_ptar_flexible_key_id 2758 * Identifier of the Flexible Key. 2759 * Only valid if key_type == "FLEX_KEY" 2760 * The key size will be rounded up to one of the following values: 2761 * 9B, 18B, 36B, 54B. 2762 * This field is reserved for in resize operation. 2763 * Access: WO 2764 */ 2765 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2766 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2767 2768 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2769 enum mlxsw_reg_ptar_key_type key_type, 2770 u16 region_size, u16 region_id, 2771 const char *tcam_region_info) 2772 { 2773 MLXSW_REG_ZERO(ptar, payload); 2774 mlxsw_reg_ptar_op_set(payload, op); 2775 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2776 mlxsw_reg_ptar_key_type_set(payload, key_type); 2777 mlxsw_reg_ptar_region_size_set(payload, region_size); 2778 mlxsw_reg_ptar_region_id_set(payload, region_id); 2779 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2780 } 2781 2782 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2783 u16 key_id) 2784 { 2785 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2786 } 2787 2788 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2789 { 2790 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2791 } 2792 2793 /* PPBS - Policy-Engine Policy Based Switching Register 2794 * ---------------------------------------------------- 2795 * This register retrieves and sets Policy Based Switching Table entries. 2796 */ 2797 #define MLXSW_REG_PPBS_ID 0x300C 2798 #define MLXSW_REG_PPBS_LEN 0x14 2799 2800 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2801 2802 /* reg_ppbs_pbs_ptr 2803 * Index into the PBS table. 2804 * For Spectrum, the index points to the KVD Linear. 2805 * Access: Index 2806 */ 2807 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2808 2809 /* reg_ppbs_system_port 2810 * Unique port identifier for the final destination of the packet. 2811 * Access: RW 2812 */ 2813 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2814 2815 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2816 u16 system_port) 2817 { 2818 MLXSW_REG_ZERO(ppbs, payload); 2819 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2820 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2821 } 2822 2823 /* PRCR - Policy-Engine Rules Copy Register 2824 * ---------------------------------------- 2825 * This register is used for accessing rules within a TCAM region. 2826 */ 2827 #define MLXSW_REG_PRCR_ID 0x300D 2828 #define MLXSW_REG_PRCR_LEN 0x40 2829 2830 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2831 2832 enum mlxsw_reg_prcr_op { 2833 /* Move rules. Moves the rules from "tcam_region_info" starting 2834 * at offset "offset" to "dest_tcam_region_info" 2835 * at offset "dest_offset." 2836 */ 2837 MLXSW_REG_PRCR_OP_MOVE, 2838 /* Copy rules. Copies the rules from "tcam_region_info" starting 2839 * at offset "offset" to "dest_tcam_region_info" 2840 * at offset "dest_offset." 2841 */ 2842 MLXSW_REG_PRCR_OP_COPY, 2843 }; 2844 2845 /* reg_prcr_op 2846 * Access: OP 2847 */ 2848 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2849 2850 /* reg_prcr_offset 2851 * Offset within the source region to copy/move from. 2852 * Access: Index 2853 */ 2854 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2855 2856 /* reg_prcr_size 2857 * The number of rules to copy/move. 2858 * Access: WO 2859 */ 2860 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2861 2862 /* reg_prcr_tcam_region_info 2863 * Opaque object that represents the source TCAM region. 2864 * Access: Index 2865 */ 2866 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2867 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2868 2869 /* reg_prcr_dest_offset 2870 * Offset within the source region to copy/move to. 2871 * Access: Index 2872 */ 2873 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2874 2875 /* reg_prcr_dest_tcam_region_info 2876 * Opaque object that represents the destination TCAM region. 2877 * Access: Index 2878 */ 2879 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2880 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2881 2882 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2883 const char *src_tcam_region_info, 2884 u16 src_offset, 2885 const char *dest_tcam_region_info, 2886 u16 dest_offset, u16 size) 2887 { 2888 MLXSW_REG_ZERO(prcr, payload); 2889 mlxsw_reg_prcr_op_set(payload, op); 2890 mlxsw_reg_prcr_offset_set(payload, src_offset); 2891 mlxsw_reg_prcr_size_set(payload, size); 2892 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2893 src_tcam_region_info); 2894 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2895 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2896 dest_tcam_region_info); 2897 } 2898 2899 /* PEFA - Policy-Engine Extended Flexible Action Register 2900 * ------------------------------------------------------ 2901 * This register is used for accessing an extended flexible action entry 2902 * in the central KVD Linear Database. 2903 */ 2904 #define MLXSW_REG_PEFA_ID 0x300F 2905 #define MLXSW_REG_PEFA_LEN 0xB0 2906 2907 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2908 2909 /* reg_pefa_index 2910 * Index in the KVD Linear Centralized Database. 2911 * Access: Index 2912 */ 2913 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2914 2915 /* reg_pefa_a 2916 * Index in the KVD Linear Centralized Database. 2917 * Activity 2918 * For a new entry: set if ca=0, clear if ca=1 2919 * Set if a packet lookup has hit on the specific entry 2920 * Access: RO 2921 */ 2922 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2923 2924 /* reg_pefa_ca 2925 * Clear activity 2926 * When write: activity is according to this field 2927 * When read: after reading the activity is cleared according to ca 2928 * Access: OP 2929 */ 2930 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2931 2932 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2933 2934 /* reg_pefa_flex_action_set 2935 * Action-set to perform when rule is matched. 2936 * Must be zero padded if action set is shorter. 2937 * Access: RW 2938 */ 2939 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2940 2941 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2942 const char *flex_action_set) 2943 { 2944 MLXSW_REG_ZERO(pefa, payload); 2945 mlxsw_reg_pefa_index_set(payload, index); 2946 mlxsw_reg_pefa_ca_set(payload, ca); 2947 if (flex_action_set) 2948 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2949 flex_action_set); 2950 } 2951 2952 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2953 { 2954 *p_a = mlxsw_reg_pefa_a_get(payload); 2955 } 2956 2957 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2958 * -------------------------------------------------------------- 2959 * This register is used for binding Multicast router to an ACL group 2960 * that serves the MC router. 2961 * This register is not supported by SwitchX/-2 and Spectrum. 2962 */ 2963 #define MLXSW_REG_PEMRBT_ID 0x3014 2964 #define MLXSW_REG_PEMRBT_LEN 0x14 2965 2966 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2967 2968 enum mlxsw_reg_pemrbt_protocol { 2969 MLXSW_REG_PEMRBT_PROTO_IPV4, 2970 MLXSW_REG_PEMRBT_PROTO_IPV6, 2971 }; 2972 2973 /* reg_pemrbt_protocol 2974 * Access: Index 2975 */ 2976 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2977 2978 /* reg_pemrbt_group_id 2979 * ACL group identifier. 2980 * Range 0..cap_max_acl_groups-1 2981 * Access: RW 2982 */ 2983 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2984 2985 static inline void 2986 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2987 u16 group_id) 2988 { 2989 MLXSW_REG_ZERO(pemrbt, payload); 2990 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2991 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2992 } 2993 2994 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2995 * ----------------------------------------------------- 2996 * This register is used for accessing rules within a TCAM region. 2997 * It is a new version of PTCE in order to support wider key, 2998 * mask and action within a TCAM region. This register is not supported 2999 * by SwitchX and SwitchX-2. 3000 */ 3001 #define MLXSW_REG_PTCE2_ID 0x3017 3002 #define MLXSW_REG_PTCE2_LEN 0x1D8 3003 3004 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3005 3006 /* reg_ptce2_v 3007 * Valid. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3011 3012 /* reg_ptce2_a 3013 * Activity. Set if a packet lookup has hit on the specific entry. 3014 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3015 * Access: RO 3016 */ 3017 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3018 3019 enum mlxsw_reg_ptce2_op { 3020 /* Read operation. */ 3021 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3022 /* clear on read operation. Used to read entry 3023 * and clear Activity bit. 3024 */ 3025 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3026 /* Write operation. Used to write a new entry to the table. 3027 * All R/W fields are relevant for new entry. Activity bit is set 3028 * for new entries - Note write with v = 0 will delete the entry. 3029 */ 3030 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3031 /* Update action. Only action set will be updated. */ 3032 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3033 /* Clear activity. A bit is cleared for the entry. */ 3034 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3035 }; 3036 3037 /* reg_ptce2_op 3038 * Access: OP 3039 */ 3040 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3041 3042 /* reg_ptce2_offset 3043 * Access: Index 3044 */ 3045 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3046 3047 /* reg_ptce2_priority 3048 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3049 * Note: priority does not have to be unique per rule. 3050 * Within a region, higher priority should have lower offset (no limitation 3051 * between regions in a multi-region). 3052 * Access: RW 3053 */ 3054 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3055 3056 /* reg_ptce2_tcam_region_info 3057 * Opaque object that represents the TCAM region. 3058 * Access: Index 3059 */ 3060 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3061 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3062 3063 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3064 3065 /* reg_ptce2_flex_key_blocks 3066 * ACL Key. 3067 * Access: RW 3068 */ 3069 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3070 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3071 3072 /* reg_ptce2_mask 3073 * mask- in the same size as key. A bit that is set directs the TCAM 3074 * to compare the corresponding bit in key. A bit that is clear directs 3075 * the TCAM to ignore the corresponding bit in key. 3076 * Access: RW 3077 */ 3078 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3079 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3080 3081 /* reg_ptce2_flex_action_set 3082 * ACL action set. 3083 * Access: RW 3084 */ 3085 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3086 MLXSW_REG_FLEX_ACTION_SET_LEN); 3087 3088 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3089 enum mlxsw_reg_ptce2_op op, 3090 const char *tcam_region_info, 3091 u16 offset, u32 priority) 3092 { 3093 MLXSW_REG_ZERO(ptce2, payload); 3094 mlxsw_reg_ptce2_v_set(payload, valid); 3095 mlxsw_reg_ptce2_op_set(payload, op); 3096 mlxsw_reg_ptce2_offset_set(payload, offset); 3097 mlxsw_reg_ptce2_priority_set(payload, priority); 3098 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3099 } 3100 3101 /* PERPT - Policy-Engine ERP Table Register 3102 * ---------------------------------------- 3103 * This register adds and removes eRPs from the eRP table. 3104 */ 3105 #define MLXSW_REG_PERPT_ID 0x3021 3106 #define MLXSW_REG_PERPT_LEN 0x80 3107 3108 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3109 3110 /* reg_perpt_erpt_bank 3111 * eRP table bank. 3112 * Range 0 .. cap_max_erp_table_banks - 1 3113 * Access: Index 3114 */ 3115 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3116 3117 /* reg_perpt_erpt_index 3118 * Index to eRP table within the eRP bank. 3119 * Range is 0 .. cap_max_erp_table_bank_size - 1 3120 * Access: Index 3121 */ 3122 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3123 3124 enum mlxsw_reg_perpt_key_size { 3125 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3126 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3127 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3128 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3129 }; 3130 3131 /* reg_perpt_key_size 3132 * Access: OP 3133 */ 3134 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3135 3136 /* reg_perpt_bf_bypass 3137 * 0 - The eRP is used only if bloom filter state is set for the given 3138 * rule. 3139 * 1 - The eRP is used regardless of bloom filter state. 3140 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3141 * Access: RW 3142 */ 3143 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3144 3145 /* reg_perpt_erp_id 3146 * eRP ID for use by the rules. 3147 * Access: RW 3148 */ 3149 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3150 3151 /* reg_perpt_erpt_base_bank 3152 * Base eRP table bank, points to head of erp_vector 3153 * Range is 0 .. cap_max_erp_table_banks - 1 3154 * Access: OP 3155 */ 3156 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3157 3158 /* reg_perpt_erpt_base_index 3159 * Base index to eRP table within the eRP bank 3160 * Range is 0 .. cap_max_erp_table_bank_size - 1 3161 * Access: OP 3162 */ 3163 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3164 3165 /* reg_perpt_erp_index_in_vector 3166 * eRP index in the vector. 3167 * Access: OP 3168 */ 3169 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3170 3171 /* reg_perpt_erp_vector 3172 * eRP vector. 3173 * Access: OP 3174 */ 3175 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3176 3177 /* reg_perpt_mask 3178 * Mask 3179 * 0 - A-TCAM will ignore the bit in key 3180 * 1 - A-TCAM will compare the bit in key 3181 * Access: RW 3182 */ 3183 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3184 3185 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3186 unsigned long *erp_vector, 3187 unsigned long size) 3188 { 3189 unsigned long bit; 3190 3191 for_each_set_bit(bit, erp_vector, size) 3192 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3193 } 3194 3195 static inline void 3196 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3197 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3198 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3199 char *mask) 3200 { 3201 MLXSW_REG_ZERO(perpt, payload); 3202 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3203 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3204 mlxsw_reg_perpt_key_size_set(payload, key_size); 3205 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3206 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3207 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3208 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3209 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3210 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3211 } 3212 3213 /* PERAR - Policy-Engine Region Association Register 3214 * ------------------------------------------------- 3215 * This register associates a hw region for region_id's. Changing on the fly 3216 * is supported by the device. 3217 */ 3218 #define MLXSW_REG_PERAR_ID 0x3026 3219 #define MLXSW_REG_PERAR_LEN 0x08 3220 3221 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3222 3223 /* reg_perar_region_id 3224 * Region identifier 3225 * Range 0 .. cap_max_regions-1 3226 * Access: Index 3227 */ 3228 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3229 3230 static inline unsigned int 3231 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3232 { 3233 return DIV_ROUND_UP(block_num, 4); 3234 } 3235 3236 /* reg_perar_hw_region 3237 * HW Region 3238 * Range 0 .. cap_max_regions-1 3239 * Default: hw_region = region_id 3240 * For a 8 key block region, 2 consecutive regions are used 3241 * For a 12 key block region, 3 consecutive regions are used 3242 * Access: RW 3243 */ 3244 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3245 3246 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3247 u16 hw_region) 3248 { 3249 MLXSW_REG_ZERO(perar, payload); 3250 mlxsw_reg_perar_region_id_set(payload, region_id); 3251 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3252 } 3253 3254 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3255 * ----------------------------------------------------- 3256 * This register is a new version of PTCE-V2 in order to support the 3257 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3258 */ 3259 #define MLXSW_REG_PTCE3_ID 0x3027 3260 #define MLXSW_REG_PTCE3_LEN 0xF0 3261 3262 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3263 3264 /* reg_ptce3_v 3265 * Valid. 3266 * Access: RW 3267 */ 3268 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3269 3270 enum mlxsw_reg_ptce3_op { 3271 /* Write operation. Used to write a new entry to the table. 3272 * All R/W fields are relevant for new entry. Activity bit is set 3273 * for new entries. Write with v = 0 will delete the entry. Must 3274 * not be used if an entry exists. 3275 */ 3276 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3277 /* Update operation */ 3278 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3279 /* Read operation */ 3280 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3281 }; 3282 3283 /* reg_ptce3_op 3284 * Access: OP 3285 */ 3286 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3287 3288 /* reg_ptce3_priority 3289 * Priority of the rule. Higher values win. 3290 * For Spectrum-2 range is 1..cap_kvd_size - 1 3291 * Note: Priority does not have to be unique per rule. 3292 * Access: RW 3293 */ 3294 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3295 3296 /* reg_ptce3_tcam_region_info 3297 * Opaque object that represents the TCAM region. 3298 * Access: Index 3299 */ 3300 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3301 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3302 3303 /* reg_ptce3_flex2_key_blocks 3304 * ACL key. The key must be masked according to eRP (if exists) or 3305 * according to master mask. 3306 * Access: Index 3307 */ 3308 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3309 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3310 3311 /* reg_ptce3_erp_id 3312 * eRP ID. 3313 * Access: Index 3314 */ 3315 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3316 3317 /* reg_ptce3_delta_start 3318 * Start point of delta_value and delta_mask, in bits. Must not exceed 3319 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3320 * Access: Index 3321 */ 3322 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3323 3324 /* reg_ptce3_delta_mask 3325 * Delta mask. 3326 * 0 - Ignore relevant bit in delta_value 3327 * 1 - Compare relevant bit in delta_value 3328 * Delta mask must not be set for reserved fields in the key blocks. 3329 * Note: No delta when no eRPs. Thus, for regions with 3330 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3331 * Access: Index 3332 */ 3333 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3334 3335 /* reg_ptce3_delta_value 3336 * Delta value. 3337 * Bits which are masked by delta_mask must be 0. 3338 * Access: Index 3339 */ 3340 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3341 3342 /* reg_ptce3_prune_vector 3343 * Pruning vector relative to the PERPT.erp_id. 3344 * Used for reducing lookups. 3345 * 0 - NEED: Do a lookup using the eRP. 3346 * 1 - PRUNE: Do not perform a lookup using the eRP. 3347 * Maybe be modified by PEAPBL and PEAPBM. 3348 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3349 * all 1's or all 0's. 3350 * Access: RW 3351 */ 3352 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3353 3354 /* reg_ptce3_prune_ctcam 3355 * Pruning on C-TCAM. Used for reducing lookups. 3356 * 0 - NEED: Do a lookup in the C-TCAM. 3357 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3358 * Access: RW 3359 */ 3360 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3361 3362 /* reg_ptce3_large_exists 3363 * Large entry key ID exists. 3364 * Within the region: 3365 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3366 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3367 * For rule delete: The MSB of the key will be removed. 3368 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3369 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3370 * For rule delete: The MSB of the key will not be removed. 3371 * Access: WO 3372 */ 3373 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3374 3375 /* reg_ptce3_large_entry_key_id 3376 * Large entry key ID. 3377 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3378 * blocks. Must be different for different keys which have the same common 3379 * 6 key blocks (MSB, blocks 6..11) key within a region. 3380 * Range is 0..cap_max_pe_large_key_id - 1 3381 * Access: RW 3382 */ 3383 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3384 3385 /* reg_ptce3_action_pointer 3386 * Pointer to action. 3387 * Range is 0..cap_max_kvd_action_sets - 1 3388 * Access: RW 3389 */ 3390 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3391 3392 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3393 enum mlxsw_reg_ptce3_op op, 3394 u32 priority, 3395 const char *tcam_region_info, 3396 const char *key, u8 erp_id, 3397 u16 delta_start, u8 delta_mask, 3398 u8 delta_value, bool large_exists, 3399 u32 lkey_id, u32 action_pointer) 3400 { 3401 MLXSW_REG_ZERO(ptce3, payload); 3402 mlxsw_reg_ptce3_v_set(payload, valid); 3403 mlxsw_reg_ptce3_op_set(payload, op); 3404 mlxsw_reg_ptce3_priority_set(payload, priority); 3405 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3406 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3407 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3408 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3409 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3410 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3411 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3412 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3413 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3414 } 3415 3416 /* PERCR - Policy-Engine Region Configuration Register 3417 * --------------------------------------------------- 3418 * This register configures the region parameters. The region_id must be 3419 * allocated. 3420 */ 3421 #define MLXSW_REG_PERCR_ID 0x302A 3422 #define MLXSW_REG_PERCR_LEN 0x80 3423 3424 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3425 3426 /* reg_percr_region_id 3427 * Region identifier. 3428 * Range 0..cap_max_regions-1 3429 * Access: Index 3430 */ 3431 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3432 3433 /* reg_percr_atcam_ignore_prune 3434 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3435 * Access: RW 3436 */ 3437 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3438 3439 /* reg_percr_ctcam_ignore_prune 3440 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3441 * Access: RW 3442 */ 3443 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3444 3445 /* reg_percr_bf_bypass 3446 * Bloom filter bypass. 3447 * 0 - Bloom filter is used (default) 3448 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3449 * region_id or eRP. See PERPT.bf_bypass 3450 * Access: RW 3451 */ 3452 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3453 3454 /* reg_percr_master_mask 3455 * Master mask. Logical OR mask of all masks of all rules of a region 3456 * (both A-TCAM and C-TCAM). When there are no eRPs 3457 * (erpt_pointer_valid = 0), then this provides the mask. 3458 * Access: RW 3459 */ 3460 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3461 3462 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3463 { 3464 MLXSW_REG_ZERO(percr, payload); 3465 mlxsw_reg_percr_region_id_set(payload, region_id); 3466 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3467 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3468 mlxsw_reg_percr_bf_bypass_set(payload, false); 3469 } 3470 3471 /* PERERP - Policy-Engine Region eRP Register 3472 * ------------------------------------------ 3473 * This register configures the region eRP. The region_id must be 3474 * allocated. 3475 */ 3476 #define MLXSW_REG_PERERP_ID 0x302B 3477 #define MLXSW_REG_PERERP_LEN 0x1C 3478 3479 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3480 3481 /* reg_pererp_region_id 3482 * Region identifier. 3483 * Range 0..cap_max_regions-1 3484 * Access: Index 3485 */ 3486 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3487 3488 /* reg_pererp_ctcam_le 3489 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3490 * Access: RW 3491 */ 3492 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3493 3494 /* reg_pererp_erpt_pointer_valid 3495 * erpt_pointer is valid. 3496 * Access: RW 3497 */ 3498 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3499 3500 /* reg_pererp_erpt_bank_pointer 3501 * Pointer to eRP table bank. May be modified at any time. 3502 * Range 0..cap_max_erp_table_banks-1 3503 * Reserved when erpt_pointer_valid = 0 3504 */ 3505 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3506 3507 /* reg_pererp_erpt_pointer 3508 * Pointer to eRP table within the eRP bank. Can be changed for an 3509 * existing region. 3510 * Range 0..cap_max_erp_table_size-1 3511 * Reserved when erpt_pointer_valid = 0 3512 * Access: RW 3513 */ 3514 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3515 3516 /* reg_pererp_erpt_vector 3517 * Vector of allowed eRP indexes starting from erpt_pointer within the 3518 * erpt_bank_pointer. Next entries will be in next bank. 3519 * Note that eRP index is used and not eRP ID. 3520 * Reserved when erpt_pointer_valid = 0 3521 * Access: RW 3522 */ 3523 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3524 3525 /* reg_pererp_master_rp_id 3526 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3527 * for the lookup. Can be changed for an existing region. 3528 * Reserved when erpt_pointer_valid = 1 3529 * Access: RW 3530 */ 3531 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3532 3533 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3534 unsigned long *erp_vector, 3535 unsigned long size) 3536 { 3537 unsigned long bit; 3538 3539 for_each_set_bit(bit, erp_vector, size) 3540 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3541 } 3542 3543 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3544 bool ctcam_le, bool erpt_pointer_valid, 3545 u8 erpt_bank_pointer, u8 erpt_pointer, 3546 u8 master_rp_id) 3547 { 3548 MLXSW_REG_ZERO(pererp, payload); 3549 mlxsw_reg_pererp_region_id_set(payload, region_id); 3550 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3551 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3552 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3553 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3554 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3555 } 3556 3557 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3558 * ---------------------------------------------------------------- 3559 * This register configures the Bloom filter entries. 3560 */ 3561 #define MLXSW_REG_PEABFE_ID 0x3022 3562 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3563 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3564 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3565 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3566 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3567 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3568 3569 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3570 3571 /* reg_peabfe_size 3572 * Number of BF entries to be updated. 3573 * Range 1..256 3574 * Access: Op 3575 */ 3576 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3577 3578 /* reg_peabfe_bf_entry_state 3579 * Bloom filter state 3580 * 0 - Clear 3581 * 1 - Set 3582 * Access: RW 3583 */ 3584 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3585 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3586 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3587 3588 /* reg_peabfe_bf_entry_bank 3589 * Bloom filter bank ID 3590 * Range 0..cap_max_erp_table_banks-1 3591 * Access: Index 3592 */ 3593 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3594 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3595 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3596 3597 /* reg_peabfe_bf_entry_index 3598 * Bloom filter entry index 3599 * Range 0..2^cap_max_bf_log-1 3600 * Access: Index 3601 */ 3602 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3603 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3604 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3605 3606 static inline void mlxsw_reg_peabfe_pack(char *payload) 3607 { 3608 MLXSW_REG_ZERO(peabfe, payload); 3609 } 3610 3611 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3612 u8 state, u8 bank, u32 bf_index) 3613 { 3614 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3615 3616 if (rec_index >= num_rec) 3617 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3618 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3619 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3620 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3621 } 3622 3623 /* IEDR - Infrastructure Entry Delete Register 3624 * ---------------------------------------------------- 3625 * This register is used for deleting entries from the entry tables. 3626 * It is legitimate to attempt to delete a nonexisting entry (the device will 3627 * respond as a good flow). 3628 */ 3629 #define MLXSW_REG_IEDR_ID 0x3804 3630 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3631 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3632 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3633 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3634 MLXSW_REG_IEDR_REC_LEN * \ 3635 MLXSW_REG_IEDR_REC_MAX_COUNT) 3636 3637 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3638 3639 /* reg_iedr_num_rec 3640 * Number of records. 3641 * Access: OP 3642 */ 3643 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3644 3645 /* reg_iedr_rec_type 3646 * Resource type. 3647 * Access: OP 3648 */ 3649 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3650 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3651 3652 /* reg_iedr_rec_size 3653 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3654 * Access: OP 3655 */ 3656 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3657 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3658 3659 /* reg_iedr_rec_index_start 3660 * Resource index start. 3661 * Access: OP 3662 */ 3663 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3664 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3665 3666 static inline void mlxsw_reg_iedr_pack(char *payload) 3667 { 3668 MLXSW_REG_ZERO(iedr, payload); 3669 } 3670 3671 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3672 u8 rec_type, u16 rec_size, 3673 u32 rec_index_start) 3674 { 3675 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3676 3677 if (rec_index >= num_rec) 3678 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3679 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3680 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3681 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3682 } 3683 3684 /* QPTS - QoS Priority Trust State Register 3685 * ---------------------------------------- 3686 * This register controls the port policy to calculate the switch priority and 3687 * packet color based on incoming packet fields. 3688 */ 3689 #define MLXSW_REG_QPTS_ID 0x4002 3690 #define MLXSW_REG_QPTS_LEN 0x8 3691 3692 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3693 3694 /* reg_qpts_local_port 3695 * Local port number. 3696 * Access: Index 3697 * 3698 * Note: CPU port is supported. 3699 */ 3700 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3701 3702 enum mlxsw_reg_qpts_trust_state { 3703 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3704 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3705 }; 3706 3707 /* reg_qpts_trust_state 3708 * Trust state for a given port. 3709 * Access: RW 3710 */ 3711 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3712 3713 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3714 enum mlxsw_reg_qpts_trust_state ts) 3715 { 3716 MLXSW_REG_ZERO(qpts, payload); 3717 3718 mlxsw_reg_qpts_local_port_set(payload, local_port); 3719 mlxsw_reg_qpts_trust_state_set(payload, ts); 3720 } 3721 3722 /* QPCR - QoS Policer Configuration Register 3723 * ----------------------------------------- 3724 * The QPCR register is used to create policers - that limit 3725 * the rate of bytes or packets via some trap group. 3726 */ 3727 #define MLXSW_REG_QPCR_ID 0x4004 3728 #define MLXSW_REG_QPCR_LEN 0x28 3729 3730 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3731 3732 enum mlxsw_reg_qpcr_g { 3733 MLXSW_REG_QPCR_G_GLOBAL = 2, 3734 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3735 }; 3736 3737 /* reg_qpcr_g 3738 * The policer type. 3739 * Access: Index 3740 */ 3741 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3742 3743 /* reg_qpcr_pid 3744 * Policer ID. 3745 * Access: Index 3746 */ 3747 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3748 3749 /* reg_qpcr_clear_counter 3750 * Clear counters. 3751 * Access: OP 3752 */ 3753 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3754 3755 /* reg_qpcr_color_aware 3756 * Is the policer aware of colors. 3757 * Must be 0 (unaware) for cpu port. 3758 * Access: RW for unbounded policer. RO for bounded policer. 3759 */ 3760 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3761 3762 /* reg_qpcr_bytes 3763 * Is policer limit is for bytes per sec or packets per sec. 3764 * 0 - packets 3765 * 1 - bytes 3766 * Access: RW for unbounded policer. RO for bounded policer. 3767 */ 3768 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3769 3770 enum mlxsw_reg_qpcr_ir_units { 3771 MLXSW_REG_QPCR_IR_UNITS_M, 3772 MLXSW_REG_QPCR_IR_UNITS_K, 3773 }; 3774 3775 /* reg_qpcr_ir_units 3776 * Policer's units for cir and eir fields (for bytes limits only) 3777 * 1 - 10^3 3778 * 0 - 10^6 3779 * Access: OP 3780 */ 3781 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3782 3783 enum mlxsw_reg_qpcr_rate_type { 3784 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3785 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3786 }; 3787 3788 /* reg_qpcr_rate_type 3789 * Policer can have one limit (single rate) or 2 limits with specific operation 3790 * for packets that exceed the lower rate but not the upper one. 3791 * (For cpu port must be single rate) 3792 * Access: RW for unbounded policer. RO for bounded policer. 3793 */ 3794 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3795 3796 /* reg_qpc_cbs 3797 * Policer's committed burst size. 3798 * The policer is working with time slices of 50 nano sec. By default every 3799 * slice is granted the proportionate share of the committed rate. If we want to 3800 * allow a slice to exceed that share (while still keeping the rate per sec) we 3801 * can allow burst. The burst size is between the default proportionate share 3802 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3803 * committed rate will result in exceeding the rate). The burst size must be a 3804 * log of 2 and will be determined by 2^cbs. 3805 * Access: RW 3806 */ 3807 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3808 3809 /* reg_qpcr_cir 3810 * Policer's committed rate. 3811 * The rate used for sungle rate, the lower rate for double rate. 3812 * For bytes limits, the rate will be this value * the unit from ir_units. 3813 * (Resolution error is up to 1%). 3814 * Access: RW 3815 */ 3816 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3817 3818 /* reg_qpcr_eir 3819 * Policer's exceed rate. 3820 * The higher rate for double rate, reserved for single rate. 3821 * Lower rate for double rate policer. 3822 * For bytes limits, the rate will be this value * the unit from ir_units. 3823 * (Resolution error is up to 1%). 3824 * Access: RW 3825 */ 3826 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3827 3828 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3829 3830 /* reg_qpcr_exceed_action. 3831 * What to do with packets between the 2 limits for double rate. 3832 * Access: RW for unbounded policer. RO for bounded policer. 3833 */ 3834 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3835 3836 enum mlxsw_reg_qpcr_action { 3837 /* Discard */ 3838 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3839 /* Forward and set color to red. 3840 * If the packet is intended to cpu port, it will be dropped. 3841 */ 3842 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3843 }; 3844 3845 /* reg_qpcr_violate_action 3846 * What to do with packets that cross the cir limit (for single rate) or the eir 3847 * limit (for double rate). 3848 * Access: RW for unbounded policer. RO for bounded policer. 3849 */ 3850 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3851 3852 /* reg_qpcr_violate_count 3853 * Counts the number of times violate_action happened on this PID. 3854 * Access: RW 3855 */ 3856 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3857 3858 /* Packets */ 3859 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3860 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3861 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3862 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3863 3864 /* Bandwidth */ 3865 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3866 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3867 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3868 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3869 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3870 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3871 3872 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3873 enum mlxsw_reg_qpcr_ir_units ir_units, 3874 bool bytes, u32 cir, u16 cbs) 3875 { 3876 MLXSW_REG_ZERO(qpcr, payload); 3877 mlxsw_reg_qpcr_pid_set(payload, pid); 3878 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3879 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3880 mlxsw_reg_qpcr_violate_action_set(payload, 3881 MLXSW_REG_QPCR_ACTION_DISCARD); 3882 mlxsw_reg_qpcr_cir_set(payload, cir); 3883 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3884 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3885 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3886 } 3887 3888 /* QTCT - QoS Switch Traffic Class Table 3889 * ------------------------------------- 3890 * Configures the mapping between the packet switch priority and the 3891 * traffic class on the transmit port. 3892 */ 3893 #define MLXSW_REG_QTCT_ID 0x400A 3894 #define MLXSW_REG_QTCT_LEN 0x08 3895 3896 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3897 3898 /* reg_qtct_local_port 3899 * Local port number. 3900 * Access: Index 3901 * 3902 * Note: CPU port is not supported. 3903 */ 3904 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3905 3906 /* reg_qtct_sub_port 3907 * Virtual port within the physical port. 3908 * Should be set to 0 when virtual ports are not enabled on the port. 3909 * Access: Index 3910 */ 3911 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3912 3913 /* reg_qtct_switch_prio 3914 * Switch priority. 3915 * Access: Index 3916 */ 3917 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3918 3919 /* reg_qtct_tclass 3920 * Traffic class. 3921 * Default values: 3922 * switch_prio 0 : tclass 1 3923 * switch_prio 1 : tclass 0 3924 * switch_prio i : tclass i, for i > 1 3925 * Access: RW 3926 */ 3927 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3928 3929 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3930 u8 switch_prio, u8 tclass) 3931 { 3932 MLXSW_REG_ZERO(qtct, payload); 3933 mlxsw_reg_qtct_local_port_set(payload, local_port); 3934 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3935 mlxsw_reg_qtct_tclass_set(payload, tclass); 3936 } 3937 3938 /* QEEC - QoS ETS Element Configuration Register 3939 * --------------------------------------------- 3940 * Configures the ETS elements. 3941 */ 3942 #define MLXSW_REG_QEEC_ID 0x400D 3943 #define MLXSW_REG_QEEC_LEN 0x20 3944 3945 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3946 3947 /* reg_qeec_local_port 3948 * Local port number. 3949 * Access: Index 3950 * 3951 * Note: CPU port is supported. 3952 */ 3953 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3954 3955 enum mlxsw_reg_qeec_hr { 3956 MLXSW_REG_QEEC_HR_PORT, 3957 MLXSW_REG_QEEC_HR_GROUP, 3958 MLXSW_REG_QEEC_HR_SUBGROUP, 3959 MLXSW_REG_QEEC_HR_TC, 3960 }; 3961 3962 /* reg_qeec_element_hierarchy 3963 * 0 - Port 3964 * 1 - Group 3965 * 2 - Subgroup 3966 * 3 - Traffic Class 3967 * Access: Index 3968 */ 3969 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3970 3971 /* reg_qeec_element_index 3972 * The index of the element in the hierarchy. 3973 * Access: Index 3974 */ 3975 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3976 3977 /* reg_qeec_next_element_index 3978 * The index of the next (lower) element in the hierarchy. 3979 * Access: RW 3980 * 3981 * Note: Reserved for element_hierarchy 0. 3982 */ 3983 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3984 3985 /* reg_qeec_mise 3986 * Min shaper configuration enable. Enables configuration of the min 3987 * shaper on this ETS element 3988 * 0 - Disable 3989 * 1 - Enable 3990 * Access: RW 3991 */ 3992 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3993 3994 /* reg_qeec_ptps 3995 * PTP shaper 3996 * 0: regular shaper mode 3997 * 1: PTP oriented shaper 3998 * Allowed only for hierarchy 0 3999 * Not supported for CPU port 4000 * Note that ptps mode may affect the shaper rates of all hierarchies 4001 * Supported only on Spectrum-1 4002 * Access: RW 4003 */ 4004 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4005 4006 enum { 4007 MLXSW_REG_QEEC_BYTES_MODE, 4008 MLXSW_REG_QEEC_PACKETS_MODE, 4009 }; 4010 4011 /* reg_qeec_pb 4012 * Packets or bytes mode. 4013 * 0 - Bytes mode 4014 * 1 - Packets mode 4015 * Access: RW 4016 * 4017 * Note: Used for max shaper configuration. For Spectrum, packets mode 4018 * is supported only for traffic classes of CPU port. 4019 */ 4020 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4021 4022 /* The smallest permitted min shaper rate. */ 4023 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4024 4025 /* reg_qeec_min_shaper_rate 4026 * Min shaper information rate. 4027 * For CPU port, can only be configured for port hierarchy. 4028 * When in bytes mode, value is specified in units of 1000bps. 4029 * Access: RW 4030 */ 4031 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4032 4033 /* reg_qeec_mase 4034 * Max shaper configuration enable. Enables configuration of the max 4035 * shaper on this ETS element. 4036 * 0 - Disable 4037 * 1 - Enable 4038 * Access: RW 4039 */ 4040 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4041 4042 /* The largest max shaper value possible to disable the shaper. */ 4043 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4044 4045 /* reg_qeec_max_shaper_rate 4046 * Max shaper information rate. 4047 * For CPU port, can only be configured for port hierarchy. 4048 * When in bytes mode, value is specified in units of 1000bps. 4049 * Access: RW 4050 */ 4051 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4052 4053 /* reg_qeec_de 4054 * DWRR configuration enable. Enables configuration of the dwrr and 4055 * dwrr_weight. 4056 * 0 - Disable 4057 * 1 - Enable 4058 * Access: RW 4059 */ 4060 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4061 4062 /* reg_qeec_dwrr 4063 * Transmission selection algorithm to use on the link going down from 4064 * the ETS element. 4065 * 0 - Strict priority 4066 * 1 - DWRR 4067 * Access: RW 4068 */ 4069 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4070 4071 /* reg_qeec_dwrr_weight 4072 * DWRR weight on the link going down from the ETS element. The 4073 * percentage of bandwidth guaranteed to an ETS element within 4074 * its hierarchy. The sum of all weights across all ETS elements 4075 * within one hierarchy should be equal to 100. Reserved when 4076 * transmission selection algorithm is strict priority. 4077 * Access: RW 4078 */ 4079 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4080 4081 /* reg_qeec_max_shaper_bs 4082 * Max shaper burst size 4083 * Burst size is 2^max_shaper_bs * 512 bits 4084 * For Spectrum-1: Range is: 5..25 4085 * For Spectrum-2: Range is: 11..25 4086 * Reserved when ptps = 1 4087 * Access: RW 4088 */ 4089 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4090 4091 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4092 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4093 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4094 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4095 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4096 4097 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4098 enum mlxsw_reg_qeec_hr hr, u8 index, 4099 u8 next_index) 4100 { 4101 MLXSW_REG_ZERO(qeec, payload); 4102 mlxsw_reg_qeec_local_port_set(payload, local_port); 4103 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4104 mlxsw_reg_qeec_element_index_set(payload, index); 4105 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4106 } 4107 4108 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4109 bool ptps) 4110 { 4111 MLXSW_REG_ZERO(qeec, payload); 4112 mlxsw_reg_qeec_local_port_set(payload, local_port); 4113 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4114 mlxsw_reg_qeec_ptps_set(payload, ptps); 4115 } 4116 4117 /* QRWE - QoS ReWrite Enable 4118 * ------------------------- 4119 * This register configures the rewrite enable per receive port. 4120 */ 4121 #define MLXSW_REG_QRWE_ID 0x400F 4122 #define MLXSW_REG_QRWE_LEN 0x08 4123 4124 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4125 4126 /* reg_qrwe_local_port 4127 * Local port number. 4128 * Access: Index 4129 * 4130 * Note: CPU port is supported. No support for router port. 4131 */ 4132 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4133 4134 /* reg_qrwe_dscp 4135 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4136 * Access: RW 4137 */ 4138 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4139 4140 /* reg_qrwe_pcp 4141 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4142 * Access: RW 4143 */ 4144 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4145 4146 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4147 bool rewrite_pcp, bool rewrite_dscp) 4148 { 4149 MLXSW_REG_ZERO(qrwe, payload); 4150 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4151 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4152 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4153 } 4154 4155 /* QPDSM - QoS Priority to DSCP Mapping 4156 * ------------------------------------ 4157 * QoS Priority to DSCP Mapping Register 4158 */ 4159 #define MLXSW_REG_QPDSM_ID 0x4011 4160 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4161 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4162 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4163 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4164 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4165 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4166 4167 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4168 4169 /* reg_qpdsm_local_port 4170 * Local Port. Supported for data packets from CPU port. 4171 * Access: Index 4172 */ 4173 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4174 4175 /* reg_qpdsm_prio_entry_color0_e 4176 * Enable update of the entry for color 0 and a given port. 4177 * Access: WO 4178 */ 4179 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4180 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4181 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4182 4183 /* reg_qpdsm_prio_entry_color0_dscp 4184 * DSCP field in the outer label of the packet for color 0 and a given port. 4185 * Reserved when e=0. 4186 * Access: RW 4187 */ 4188 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4189 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4190 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4191 4192 /* reg_qpdsm_prio_entry_color1_e 4193 * Enable update of the entry for color 1 and a given port. 4194 * Access: WO 4195 */ 4196 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4197 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4198 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4199 4200 /* reg_qpdsm_prio_entry_color1_dscp 4201 * DSCP field in the outer label of the packet for color 1 and a given port. 4202 * Reserved when e=0. 4203 * Access: RW 4204 */ 4205 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4206 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4207 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4208 4209 /* reg_qpdsm_prio_entry_color2_e 4210 * Enable update of the entry for color 2 and a given port. 4211 * Access: WO 4212 */ 4213 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4214 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4215 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4216 4217 /* reg_qpdsm_prio_entry_color2_dscp 4218 * DSCP field in the outer label of the packet for color 2 and a given port. 4219 * Reserved when e=0. 4220 * Access: RW 4221 */ 4222 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4223 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4224 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4225 4226 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4227 { 4228 MLXSW_REG_ZERO(qpdsm, payload); 4229 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4230 } 4231 4232 static inline void 4233 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4234 { 4235 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4236 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4237 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4238 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4239 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4240 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4241 } 4242 4243 /* QPDP - QoS Port DSCP to Priority Mapping Register 4244 * ------------------------------------------------- 4245 * This register controls the port default Switch Priority and Color. The 4246 * default Switch Priority and Color are used for frames where the trust state 4247 * uses default values. All member ports of a LAG should be configured with the 4248 * same default values. 4249 */ 4250 #define MLXSW_REG_QPDP_ID 0x4007 4251 #define MLXSW_REG_QPDP_LEN 0x8 4252 4253 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4254 4255 /* reg_qpdp_local_port 4256 * Local Port. Supported for data packets from CPU port. 4257 * Access: Index 4258 */ 4259 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4260 4261 /* reg_qpdp_switch_prio 4262 * Default port Switch Priority (default 0) 4263 * Access: RW 4264 */ 4265 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4266 4267 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4268 u8 switch_prio) 4269 { 4270 MLXSW_REG_ZERO(qpdp, payload); 4271 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4272 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4273 } 4274 4275 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4276 * -------------------------------------------------- 4277 * This register controls the mapping from DSCP field to 4278 * Switch Priority for IP packets. 4279 */ 4280 #define MLXSW_REG_QPDPM_ID 0x4013 4281 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4282 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4283 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4284 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4285 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4286 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4287 4288 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4289 4290 /* reg_qpdpm_local_port 4291 * Local Port. Supported for data packets from CPU port. 4292 * Access: Index 4293 */ 4294 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4295 4296 /* reg_qpdpm_dscp_e 4297 * Enable update of the specific entry. When cleared, the switch_prio and color 4298 * fields are ignored and the previous switch_prio and color values are 4299 * preserved. 4300 * Access: WO 4301 */ 4302 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4303 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4304 4305 /* reg_qpdpm_dscp_prio 4306 * The new Switch Priority value for the relevant DSCP value. 4307 * Access: RW 4308 */ 4309 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4310 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4311 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4312 4313 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4314 { 4315 MLXSW_REG_ZERO(qpdpm, payload); 4316 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4317 } 4318 4319 static inline void 4320 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4321 { 4322 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4323 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4324 } 4325 4326 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4327 * ------------------------------------------------------------------ 4328 * This register configures if the Switch Priority to Traffic Class mapping is 4329 * based on Multicast packet indication. If so, then multicast packets will get 4330 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4331 * QTCT. 4332 * By default, Switch Priority to Traffic Class mapping is not based on 4333 * Multicast packet indication. 4334 */ 4335 #define MLXSW_REG_QTCTM_ID 0x401A 4336 #define MLXSW_REG_QTCTM_LEN 0x08 4337 4338 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4339 4340 /* reg_qtctm_local_port 4341 * Local port number. 4342 * No support for CPU port. 4343 * Access: Index 4344 */ 4345 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4346 4347 /* reg_qtctm_mc 4348 * Multicast Mode 4349 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4350 * indication (default is 0, not based on Multicast packet indication). 4351 */ 4352 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4353 4354 static inline void 4355 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4356 { 4357 MLXSW_REG_ZERO(qtctm, payload); 4358 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4359 mlxsw_reg_qtctm_mc_set(payload, mc); 4360 } 4361 4362 /* QPSC - QoS PTP Shaper Configuration Register 4363 * -------------------------------------------- 4364 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4365 * Supported only on Spectrum-1. 4366 */ 4367 #define MLXSW_REG_QPSC_ID 0x401B 4368 #define MLXSW_REG_QPSC_LEN 0x28 4369 4370 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4371 4372 enum mlxsw_reg_qpsc_port_speed { 4373 MLXSW_REG_QPSC_PORT_SPEED_100M, 4374 MLXSW_REG_QPSC_PORT_SPEED_1G, 4375 MLXSW_REG_QPSC_PORT_SPEED_10G, 4376 MLXSW_REG_QPSC_PORT_SPEED_25G, 4377 }; 4378 4379 /* reg_qpsc_port_speed 4380 * Port speed. 4381 * Access: Index 4382 */ 4383 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4384 4385 /* reg_qpsc_shaper_time_exp 4386 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4387 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4388 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4389 * Access: RW 4390 */ 4391 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4392 4393 /* reg_qpsc_shaper_time_mantissa 4394 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4395 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4396 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4397 * Access: RW 4398 */ 4399 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4400 4401 /* reg_qpsc_shaper_inc 4402 * Number of tokens added to shaper on each update. 4403 * Units of 8B. 4404 * Access: RW 4405 */ 4406 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4407 4408 /* reg_qpsc_shaper_bs 4409 * Max shaper Burst size. 4410 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4411 * Range is: 5..25 (from 2KB..2GB) 4412 * Access: RW 4413 */ 4414 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4415 4416 /* reg_qpsc_ptsc_we 4417 * Write enable to port_to_shaper_credits. 4418 * Access: WO 4419 */ 4420 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4421 4422 /* reg_qpsc_port_to_shaper_credits 4423 * For split ports: range 1..57 4424 * For non-split ports: range 1..112 4425 * Written only when ptsc_we is set. 4426 * Access: RW 4427 */ 4428 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4429 4430 /* reg_qpsc_ing_timestamp_inc 4431 * Ingress timestamp increment. 4432 * 2's complement. 4433 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4434 * value for all ports. 4435 * Same units as used by MTPPTR. 4436 * Access: RW 4437 */ 4438 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4439 4440 /* reg_qpsc_egr_timestamp_inc 4441 * Egress timestamp increment. 4442 * 2's complement. 4443 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4444 * value for all ports. 4445 * Same units as used by MTPPTR. 4446 * Access: RW 4447 */ 4448 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4449 4450 static inline void 4451 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4452 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4453 u8 shaper_bs, u8 port_to_shaper_credits, 4454 int ing_timestamp_inc, int egr_timestamp_inc) 4455 { 4456 MLXSW_REG_ZERO(qpsc, payload); 4457 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4458 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4459 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4460 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4461 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4462 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4463 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4464 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4465 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4466 } 4467 4468 /* PMLP - Ports Module to Local Port Register 4469 * ------------------------------------------ 4470 * Configures the assignment of modules to local ports. 4471 */ 4472 #define MLXSW_REG_PMLP_ID 0x5002 4473 #define MLXSW_REG_PMLP_LEN 0x40 4474 4475 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4476 4477 /* reg_pmlp_rxtx 4478 * 0 - Tx value is used for both Tx and Rx. 4479 * 1 - Rx value is taken from a separte field. 4480 * Access: RW 4481 */ 4482 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4483 4484 /* reg_pmlp_local_port 4485 * Local port number. 4486 * Access: Index 4487 */ 4488 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4489 4490 /* reg_pmlp_width 4491 * 0 - Unmap local port. 4492 * 1 - Lane 0 is used. 4493 * 2 - Lanes 0 and 1 are used. 4494 * 4 - Lanes 0, 1, 2 and 3 are used. 4495 * 8 - Lanes 0-7 are used. 4496 * Access: RW 4497 */ 4498 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4499 4500 /* reg_pmlp_module 4501 * Module number. 4502 * Access: RW 4503 */ 4504 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4505 4506 /* reg_pmlp_slot_index 4507 * Module number. 4508 * Slot_index 4509 * Slot_index = 0 represent the onboard (motherboard). 4510 * In case of non-modular system only slot_index = 0 is available. 4511 * Access: RW 4512 */ 4513 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4514 4515 /* reg_pmlp_tx_lane 4516 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4517 * Access: RW 4518 */ 4519 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4520 4521 /* reg_pmlp_rx_lane 4522 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4523 * equal to Tx lane. 4524 * Access: RW 4525 */ 4526 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4527 4528 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4529 { 4530 MLXSW_REG_ZERO(pmlp, payload); 4531 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4532 } 4533 4534 /* PMTU - Port MTU Register 4535 * ------------------------ 4536 * Configures and reports the port MTU. 4537 */ 4538 #define MLXSW_REG_PMTU_ID 0x5003 4539 #define MLXSW_REG_PMTU_LEN 0x10 4540 4541 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4542 4543 /* reg_pmtu_local_port 4544 * Local port number. 4545 * Access: Index 4546 */ 4547 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4548 4549 /* reg_pmtu_max_mtu 4550 * Maximum MTU. 4551 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4552 * reported, otherwise the minimum between the max_mtu of the different 4553 * types is reported. 4554 * Access: RO 4555 */ 4556 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4557 4558 /* reg_pmtu_admin_mtu 4559 * MTU value to set port to. Must be smaller or equal to max_mtu. 4560 * Note: If port type is Infiniband, then port must be disabled, when its 4561 * MTU is set. 4562 * Access: RW 4563 */ 4564 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4565 4566 /* reg_pmtu_oper_mtu 4567 * The actual MTU configured on the port. Packets exceeding this size 4568 * will be dropped. 4569 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4570 * oper_mtu might be smaller than admin_mtu. 4571 * Access: RO 4572 */ 4573 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4574 4575 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4576 u16 new_mtu) 4577 { 4578 MLXSW_REG_ZERO(pmtu, payload); 4579 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4580 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4581 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4582 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4583 } 4584 4585 /* PTYS - Port Type and Speed Register 4586 * ----------------------------------- 4587 * Configures and reports the port speed type. 4588 * 4589 * Note: When set while the link is up, the changes will not take effect 4590 * until the port transitions from down to up state. 4591 */ 4592 #define MLXSW_REG_PTYS_ID 0x5004 4593 #define MLXSW_REG_PTYS_LEN 0x40 4594 4595 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4596 4597 /* an_disable_admin 4598 * Auto negotiation disable administrative configuration 4599 * 0 - Device doesn't support AN disable. 4600 * 1 - Device supports AN disable. 4601 * Access: RW 4602 */ 4603 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4604 4605 /* reg_ptys_local_port 4606 * Local port number. 4607 * Access: Index 4608 */ 4609 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4610 4611 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4612 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4613 4614 /* reg_ptys_proto_mask 4615 * Protocol mask. Indicates which protocol is used. 4616 * 0 - Infiniband. 4617 * 1 - Fibre Channel. 4618 * 2 - Ethernet. 4619 * Access: Index 4620 */ 4621 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4622 4623 enum { 4624 MLXSW_REG_PTYS_AN_STATUS_NA, 4625 MLXSW_REG_PTYS_AN_STATUS_OK, 4626 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4627 }; 4628 4629 /* reg_ptys_an_status 4630 * Autonegotiation status. 4631 * Access: RO 4632 */ 4633 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4634 4635 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4636 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4637 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4638 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4639 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4640 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4641 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4642 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4643 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4644 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4645 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4646 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4647 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19) 4648 4649 /* reg_ptys_ext_eth_proto_cap 4650 * Extended Ethernet port supported speeds and protocols. 4651 * Access: RO 4652 */ 4653 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4654 4655 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4656 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4657 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4658 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4659 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4660 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4661 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4662 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4663 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4664 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4665 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4666 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4667 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4668 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4669 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4670 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4671 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4672 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4673 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4674 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4675 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4676 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4677 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4678 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4679 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4680 4681 /* reg_ptys_eth_proto_cap 4682 * Ethernet port supported speeds and protocols. 4683 * Access: RO 4684 */ 4685 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4686 4687 /* reg_ptys_ext_eth_proto_admin 4688 * Extended speed and protocol to set port to. 4689 * Access: RW 4690 */ 4691 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4692 4693 /* reg_ptys_eth_proto_admin 4694 * Speed and protocol to set port to. 4695 * Access: RW 4696 */ 4697 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4698 4699 /* reg_ptys_ext_eth_proto_oper 4700 * The extended current speed and protocol configured for the port. 4701 * Access: RO 4702 */ 4703 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4704 4705 /* reg_ptys_eth_proto_oper 4706 * The current speed and protocol configured for the port. 4707 * Access: RO 4708 */ 4709 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4710 4711 enum mlxsw_reg_ptys_connector_type { 4712 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4713 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4714 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4715 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4716 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4717 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4718 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4719 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4720 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4721 }; 4722 4723 /* reg_ptys_connector_type 4724 * Connector type indication. 4725 * Access: RO 4726 */ 4727 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4728 4729 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4730 u32 proto_admin, bool autoneg) 4731 { 4732 MLXSW_REG_ZERO(ptys, payload); 4733 mlxsw_reg_ptys_local_port_set(payload, local_port); 4734 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4735 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4736 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4737 } 4738 4739 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4740 u32 proto_admin, bool autoneg) 4741 { 4742 MLXSW_REG_ZERO(ptys, payload); 4743 mlxsw_reg_ptys_local_port_set(payload, local_port); 4744 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4745 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4746 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4747 } 4748 4749 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4750 u32 *p_eth_proto_cap, 4751 u32 *p_eth_proto_admin, 4752 u32 *p_eth_proto_oper) 4753 { 4754 if (p_eth_proto_cap) 4755 *p_eth_proto_cap = 4756 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4757 if (p_eth_proto_admin) 4758 *p_eth_proto_admin = 4759 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4760 if (p_eth_proto_oper) 4761 *p_eth_proto_oper = 4762 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4763 } 4764 4765 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4766 u32 *p_eth_proto_cap, 4767 u32 *p_eth_proto_admin, 4768 u32 *p_eth_proto_oper) 4769 { 4770 if (p_eth_proto_cap) 4771 *p_eth_proto_cap = 4772 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4773 if (p_eth_proto_admin) 4774 *p_eth_proto_admin = 4775 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4776 if (p_eth_proto_oper) 4777 *p_eth_proto_oper = 4778 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4779 } 4780 4781 /* PPAD - Port Physical Address Register 4782 * ------------------------------------- 4783 * The PPAD register configures the per port physical MAC address. 4784 */ 4785 #define MLXSW_REG_PPAD_ID 0x5005 4786 #define MLXSW_REG_PPAD_LEN 0x10 4787 4788 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4789 4790 /* reg_ppad_single_base_mac 4791 * 0: base_mac, local port should be 0 and mac[7:0] is 4792 * reserved. HW will set incremental 4793 * 1: single_mac - mac of the local_port 4794 * Access: RW 4795 */ 4796 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4797 4798 /* reg_ppad_local_port 4799 * port number, if single_base_mac = 0 then local_port is reserved 4800 * Access: RW 4801 */ 4802 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4803 4804 /* reg_ppad_mac 4805 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4806 * If single_base_mac = 1 - the per port MAC address 4807 * Access: RW 4808 */ 4809 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4810 4811 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4812 u16 local_port) 4813 { 4814 MLXSW_REG_ZERO(ppad, payload); 4815 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4816 mlxsw_reg_ppad_local_port_set(payload, local_port); 4817 } 4818 4819 /* PAOS - Ports Administrative and Operational Status Register 4820 * ----------------------------------------------------------- 4821 * Configures and retrieves per port administrative and operational status. 4822 */ 4823 #define MLXSW_REG_PAOS_ID 0x5006 4824 #define MLXSW_REG_PAOS_LEN 0x10 4825 4826 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4827 4828 /* reg_paos_swid 4829 * Switch partition ID with which to associate the port. 4830 * Note: while external ports uses unique local port numbers (and thus swid is 4831 * redundant), router ports use the same local port number where swid is the 4832 * only indication for the relevant port. 4833 * Access: Index 4834 */ 4835 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4836 4837 /* reg_paos_local_port 4838 * Local port number. 4839 * Access: Index 4840 */ 4841 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4842 4843 /* reg_paos_admin_status 4844 * Port administrative state (the desired state of the port): 4845 * 1 - Up. 4846 * 2 - Down. 4847 * 3 - Up once. This means that in case of link failure, the port won't go 4848 * into polling mode, but will wait to be re-enabled by software. 4849 * 4 - Disabled by system. Can only be set by hardware. 4850 * Access: RW 4851 */ 4852 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4853 4854 /* reg_paos_oper_status 4855 * Port operational state (the current state): 4856 * 1 - Up. 4857 * 2 - Down. 4858 * 3 - Down by port failure. This means that the device will not let the 4859 * port up again until explicitly specified by software. 4860 * Access: RO 4861 */ 4862 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4863 4864 /* reg_paos_ase 4865 * Admin state update enabled. 4866 * Access: WO 4867 */ 4868 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4869 4870 /* reg_paos_ee 4871 * Event update enable. If this bit is set, event generation will be 4872 * updated based on the e field. 4873 * Access: WO 4874 */ 4875 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4876 4877 /* reg_paos_e 4878 * Event generation on operational state change: 4879 * 0 - Do not generate event. 4880 * 1 - Generate Event. 4881 * 2 - Generate Single Event. 4882 * Access: RW 4883 */ 4884 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4885 4886 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4887 enum mlxsw_port_admin_status status) 4888 { 4889 MLXSW_REG_ZERO(paos, payload); 4890 mlxsw_reg_paos_swid_set(payload, 0); 4891 mlxsw_reg_paos_local_port_set(payload, local_port); 4892 mlxsw_reg_paos_admin_status_set(payload, status); 4893 mlxsw_reg_paos_oper_status_set(payload, 0); 4894 mlxsw_reg_paos_ase_set(payload, 1); 4895 mlxsw_reg_paos_ee_set(payload, 1); 4896 mlxsw_reg_paos_e_set(payload, 1); 4897 } 4898 4899 /* PFCC - Ports Flow Control Configuration Register 4900 * ------------------------------------------------ 4901 * Configures and retrieves the per port flow control configuration. 4902 */ 4903 #define MLXSW_REG_PFCC_ID 0x5007 4904 #define MLXSW_REG_PFCC_LEN 0x20 4905 4906 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4907 4908 /* reg_pfcc_local_port 4909 * Local port number. 4910 * Access: Index 4911 */ 4912 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4913 4914 /* reg_pfcc_pnat 4915 * Port number access type. Determines the way local_port is interpreted: 4916 * 0 - Local port number. 4917 * 1 - IB / label port number. 4918 * Access: Index 4919 */ 4920 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4921 4922 /* reg_pfcc_shl_cap 4923 * Send to higher layers capabilities: 4924 * 0 - No capability of sending Pause and PFC frames to higher layers. 4925 * 1 - Device has capability of sending Pause and PFC frames to higher 4926 * layers. 4927 * Access: RO 4928 */ 4929 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4930 4931 /* reg_pfcc_shl_opr 4932 * Send to higher layers operation: 4933 * 0 - Pause and PFC frames are handled by the port (default). 4934 * 1 - Pause and PFC frames are handled by the port and also sent to 4935 * higher layers. Only valid if shl_cap = 1. 4936 * Access: RW 4937 */ 4938 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4939 4940 /* reg_pfcc_ppan 4941 * Pause policy auto negotiation. 4942 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4943 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4944 * based on the auto-negotiation resolution. 4945 * Access: RW 4946 * 4947 * Note: The auto-negotiation advertisement is set according to pptx and 4948 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4949 */ 4950 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4951 4952 /* reg_pfcc_prio_mask_tx 4953 * Bit per priority indicating if Tx flow control policy should be 4954 * updated based on bit pfctx. 4955 * Access: WO 4956 */ 4957 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4958 4959 /* reg_pfcc_prio_mask_rx 4960 * Bit per priority indicating if Rx flow control policy should be 4961 * updated based on bit pfcrx. 4962 * Access: WO 4963 */ 4964 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4965 4966 /* reg_pfcc_pptx 4967 * Admin Pause policy on Tx. 4968 * 0 - Never generate Pause frames (default). 4969 * 1 - Generate Pause frames according to Rx buffer threshold. 4970 * Access: RW 4971 */ 4972 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4973 4974 /* reg_pfcc_aptx 4975 * Active (operational) Pause policy on Tx. 4976 * 0 - Never generate Pause frames. 4977 * 1 - Generate Pause frames according to Rx buffer threshold. 4978 * Access: RO 4979 */ 4980 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4981 4982 /* reg_pfcc_pfctx 4983 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4984 * 0 - Never generate priority Pause frames on the specified priority 4985 * (default). 4986 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4987 * the specified priority. 4988 * Access: RW 4989 * 4990 * Note: pfctx and pptx must be mutually exclusive. 4991 */ 4992 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4993 4994 /* reg_pfcc_pprx 4995 * Admin Pause policy on Rx. 4996 * 0 - Ignore received Pause frames (default). 4997 * 1 - Respect received Pause frames. 4998 * Access: RW 4999 */ 5000 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5001 5002 /* reg_pfcc_aprx 5003 * Active (operational) Pause policy on Rx. 5004 * 0 - Ignore received Pause frames. 5005 * 1 - Respect received Pause frames. 5006 * Access: RO 5007 */ 5008 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5009 5010 /* reg_pfcc_pfcrx 5011 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5012 * 0 - Ignore incoming priority Pause frames on the specified priority 5013 * (default). 5014 * 1 - Respect incoming priority Pause frames on the specified priority. 5015 * Access: RW 5016 */ 5017 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5018 5019 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5020 5021 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5022 { 5023 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5024 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5025 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5026 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5027 } 5028 5029 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5030 { 5031 MLXSW_REG_ZERO(pfcc, payload); 5032 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5033 } 5034 5035 /* PPCNT - Ports Performance Counters Register 5036 * ------------------------------------------- 5037 * The PPCNT register retrieves per port performance counters. 5038 */ 5039 #define MLXSW_REG_PPCNT_ID 0x5008 5040 #define MLXSW_REG_PPCNT_LEN 0x100 5041 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5042 5043 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5044 5045 /* reg_ppcnt_swid 5046 * For HCA: must be always 0. 5047 * Switch partition ID to associate port with. 5048 * Switch partitions are numbered from 0 to 7 inclusively. 5049 * Switch partition 254 indicates stacking ports. 5050 * Switch partition 255 indicates all switch partitions. 5051 * Only valid on Set() operation with local_port=255. 5052 * Access: Index 5053 */ 5054 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5055 5056 /* reg_ppcnt_local_port 5057 * Local port number. 5058 * Access: Index 5059 */ 5060 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5061 5062 /* reg_ppcnt_pnat 5063 * Port number access type: 5064 * 0 - Local port number 5065 * 1 - IB port number 5066 * Access: Index 5067 */ 5068 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5069 5070 enum mlxsw_reg_ppcnt_grp { 5071 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5072 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5073 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5074 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5075 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5076 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5077 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5078 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5079 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5080 }; 5081 5082 /* reg_ppcnt_grp 5083 * Performance counter group. 5084 * Group 63 indicates all groups. Only valid on Set() operation with 5085 * clr bit set. 5086 * 0x0: IEEE 802.3 Counters 5087 * 0x1: RFC 2863 Counters 5088 * 0x2: RFC 2819 Counters 5089 * 0x3: RFC 3635 Counters 5090 * 0x5: Ethernet Extended Counters 5091 * 0x6: Ethernet Discard Counters 5092 * 0x8: Link Level Retransmission Counters 5093 * 0x10: Per Priority Counters 5094 * 0x11: Per Traffic Class Counters 5095 * 0x12: Physical Layer Counters 5096 * 0x13: Per Traffic Class Congestion Counters 5097 * Access: Index 5098 */ 5099 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5100 5101 /* reg_ppcnt_clr 5102 * Clear counters. Setting the clr bit will reset the counter value 5103 * for all counters in the counter group. This bit can be set 5104 * for both Set() and Get() operation. 5105 * Access: OP 5106 */ 5107 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5108 5109 /* reg_ppcnt_lp_gl 5110 * Local port global variable. 5111 * 0: local_port 255 = all ports of the device. 5112 * 1: local_port indicates local port number for all ports. 5113 * Access: OP 5114 */ 5115 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5116 5117 /* reg_ppcnt_prio_tc 5118 * Priority for counter set that support per priority, valid values: 0-7. 5119 * Traffic class for counter set that support per traffic class, 5120 * valid values: 0- cap_max_tclass-1 . 5121 * For HCA: cap_max_tclass is always 8. 5122 * Otherwise must be 0. 5123 * Access: Index 5124 */ 5125 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5126 5127 /* Ethernet IEEE 802.3 Counter Group */ 5128 5129 /* reg_ppcnt_a_frames_transmitted_ok 5130 * Access: RO 5131 */ 5132 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5133 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5134 5135 /* reg_ppcnt_a_frames_received_ok 5136 * Access: RO 5137 */ 5138 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5139 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5140 5141 /* reg_ppcnt_a_frame_check_sequence_errors 5142 * Access: RO 5143 */ 5144 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5145 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5146 5147 /* reg_ppcnt_a_alignment_errors 5148 * Access: RO 5149 */ 5150 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5151 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5152 5153 /* reg_ppcnt_a_octets_transmitted_ok 5154 * Access: RO 5155 */ 5156 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5157 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5158 5159 /* reg_ppcnt_a_octets_received_ok 5160 * Access: RO 5161 */ 5162 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5163 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5164 5165 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5166 * Access: RO 5167 */ 5168 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5169 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5170 5171 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5172 * Access: RO 5173 */ 5174 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5175 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5176 5177 /* reg_ppcnt_a_multicast_frames_received_ok 5178 * Access: RO 5179 */ 5180 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5181 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5182 5183 /* reg_ppcnt_a_broadcast_frames_received_ok 5184 * Access: RO 5185 */ 5186 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5187 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5188 5189 /* reg_ppcnt_a_in_range_length_errors 5190 * Access: RO 5191 */ 5192 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5193 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5194 5195 /* reg_ppcnt_a_out_of_range_length_field 5196 * Access: RO 5197 */ 5198 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5199 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5200 5201 /* reg_ppcnt_a_frame_too_long_errors 5202 * Access: RO 5203 */ 5204 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5205 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5206 5207 /* reg_ppcnt_a_symbol_error_during_carrier 5208 * Access: RO 5209 */ 5210 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5211 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5212 5213 /* reg_ppcnt_a_mac_control_frames_transmitted 5214 * Access: RO 5215 */ 5216 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5217 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5218 5219 /* reg_ppcnt_a_mac_control_frames_received 5220 * Access: RO 5221 */ 5222 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5223 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5224 5225 /* reg_ppcnt_a_unsupported_opcodes_received 5226 * Access: RO 5227 */ 5228 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5229 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5230 5231 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5232 * Access: RO 5233 */ 5234 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5235 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5236 5237 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5238 * Access: RO 5239 */ 5240 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5241 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5242 5243 /* Ethernet RFC 2863 Counter Group */ 5244 5245 /* reg_ppcnt_if_in_discards 5246 * Access: RO 5247 */ 5248 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5249 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5250 5251 /* reg_ppcnt_if_out_discards 5252 * Access: RO 5253 */ 5254 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5255 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5256 5257 /* reg_ppcnt_if_out_errors 5258 * Access: RO 5259 */ 5260 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5261 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5262 5263 /* Ethernet RFC 2819 Counter Group */ 5264 5265 /* reg_ppcnt_ether_stats_undersize_pkts 5266 * Access: RO 5267 */ 5268 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5269 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5270 5271 /* reg_ppcnt_ether_stats_oversize_pkts 5272 * Access: RO 5273 */ 5274 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5275 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5276 5277 /* reg_ppcnt_ether_stats_fragments 5278 * Access: RO 5279 */ 5280 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5281 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5282 5283 /* reg_ppcnt_ether_stats_pkts64octets 5284 * Access: RO 5285 */ 5286 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5287 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5288 5289 /* reg_ppcnt_ether_stats_pkts65to127octets 5290 * Access: RO 5291 */ 5292 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5293 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5294 5295 /* reg_ppcnt_ether_stats_pkts128to255octets 5296 * Access: RO 5297 */ 5298 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5299 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5300 5301 /* reg_ppcnt_ether_stats_pkts256to511octets 5302 * Access: RO 5303 */ 5304 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5305 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5306 5307 /* reg_ppcnt_ether_stats_pkts512to1023octets 5308 * Access: RO 5309 */ 5310 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5311 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5312 5313 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5314 * Access: RO 5315 */ 5316 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5317 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5318 5319 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5320 * Access: RO 5321 */ 5322 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5323 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5324 5325 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5326 * Access: RO 5327 */ 5328 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5329 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5330 5331 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5332 * Access: RO 5333 */ 5334 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5335 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5336 5337 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5338 * Access: RO 5339 */ 5340 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5341 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5342 5343 /* Ethernet RFC 3635 Counter Group */ 5344 5345 /* reg_ppcnt_dot3stats_fcs_errors 5346 * Access: RO 5347 */ 5348 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5349 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5350 5351 /* reg_ppcnt_dot3stats_symbol_errors 5352 * Access: RO 5353 */ 5354 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5356 5357 /* reg_ppcnt_dot3control_in_unknown_opcodes 5358 * Access: RO 5359 */ 5360 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5362 5363 /* reg_ppcnt_dot3in_pause_frames 5364 * Access: RO 5365 */ 5366 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5368 5369 /* Ethernet Extended Counter Group Counters */ 5370 5371 /* reg_ppcnt_ecn_marked 5372 * Access: RO 5373 */ 5374 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5375 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5376 5377 /* Ethernet Discard Counter Group Counters */ 5378 5379 /* reg_ppcnt_ingress_general 5380 * Access: RO 5381 */ 5382 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5383 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5384 5385 /* reg_ppcnt_ingress_policy_engine 5386 * Access: RO 5387 */ 5388 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5389 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5390 5391 /* reg_ppcnt_ingress_vlan_membership 5392 * Access: RO 5393 */ 5394 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5395 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5396 5397 /* reg_ppcnt_ingress_tag_frame_type 5398 * Access: RO 5399 */ 5400 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5401 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5402 5403 /* reg_ppcnt_egress_vlan_membership 5404 * Access: RO 5405 */ 5406 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5407 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5408 5409 /* reg_ppcnt_loopback_filter 5410 * Access: RO 5411 */ 5412 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5413 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5414 5415 /* reg_ppcnt_egress_general 5416 * Access: RO 5417 */ 5418 MLXSW_ITEM64(reg, ppcnt, egress_general, 5419 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5420 5421 /* reg_ppcnt_egress_hoq 5422 * Access: RO 5423 */ 5424 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5425 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5426 5427 /* reg_ppcnt_egress_policy_engine 5428 * Access: RO 5429 */ 5430 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5431 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5432 5433 /* reg_ppcnt_ingress_tx_link_down 5434 * Access: RO 5435 */ 5436 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5437 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5438 5439 /* reg_ppcnt_egress_stp_filter 5440 * Access: RO 5441 */ 5442 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5443 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5444 5445 /* reg_ppcnt_egress_sll 5446 * Access: RO 5447 */ 5448 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5449 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5450 5451 /* Ethernet Per Priority Group Counters */ 5452 5453 /* reg_ppcnt_rx_octets 5454 * Access: RO 5455 */ 5456 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5457 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5458 5459 /* reg_ppcnt_rx_frames 5460 * Access: RO 5461 */ 5462 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5463 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5464 5465 /* reg_ppcnt_tx_octets 5466 * Access: RO 5467 */ 5468 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5469 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5470 5471 /* reg_ppcnt_tx_frames 5472 * Access: RO 5473 */ 5474 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5475 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5476 5477 /* reg_ppcnt_rx_pause 5478 * Access: RO 5479 */ 5480 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5481 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5482 5483 /* reg_ppcnt_rx_pause_duration 5484 * Access: RO 5485 */ 5486 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5487 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5488 5489 /* reg_ppcnt_tx_pause 5490 * Access: RO 5491 */ 5492 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5493 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5494 5495 /* reg_ppcnt_tx_pause_duration 5496 * Access: RO 5497 */ 5498 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5499 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5500 5501 /* reg_ppcnt_rx_pause_transition 5502 * Access: RO 5503 */ 5504 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5505 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5506 5507 /* Ethernet Per Traffic Class Counters */ 5508 5509 /* reg_ppcnt_tc_transmit_queue 5510 * Contains the transmit queue depth in cells of traffic class 5511 * selected by prio_tc and the port selected by local_port. 5512 * The field cannot be cleared. 5513 * Access: RO 5514 */ 5515 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5516 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5517 5518 /* reg_ppcnt_tc_no_buffer_discard_uc 5519 * The number of unicast packets dropped due to lack of shared 5520 * buffer resources. 5521 * Access: RO 5522 */ 5523 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5524 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5525 5526 /* Ethernet Per Traffic Class Congestion Group Counters */ 5527 5528 /* reg_ppcnt_wred_discard 5529 * Access: RO 5530 */ 5531 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5532 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5533 5534 /* reg_ppcnt_ecn_marked_tc 5535 * Access: RO 5536 */ 5537 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5538 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5539 5540 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5541 enum mlxsw_reg_ppcnt_grp grp, 5542 u8 prio_tc) 5543 { 5544 MLXSW_REG_ZERO(ppcnt, payload); 5545 mlxsw_reg_ppcnt_swid_set(payload, 0); 5546 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5547 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5548 mlxsw_reg_ppcnt_grp_set(payload, grp); 5549 mlxsw_reg_ppcnt_clr_set(payload, 0); 5550 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5551 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5552 } 5553 5554 /* PPTB - Port Prio To Buffer Register 5555 * ----------------------------------- 5556 * Configures the switch priority to buffer table. 5557 */ 5558 #define MLXSW_REG_PPTB_ID 0x500B 5559 #define MLXSW_REG_PPTB_LEN 0x10 5560 5561 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5562 5563 enum { 5564 MLXSW_REG_PPTB_MM_UM, 5565 MLXSW_REG_PPTB_MM_UNICAST, 5566 MLXSW_REG_PPTB_MM_MULTICAST, 5567 }; 5568 5569 /* reg_pptb_mm 5570 * Mapping mode. 5571 * 0 - Map both unicast and multicast packets to the same buffer. 5572 * 1 - Map only unicast packets. 5573 * 2 - Map only multicast packets. 5574 * Access: Index 5575 * 5576 * Note: SwitchX-2 only supports the first option. 5577 */ 5578 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5579 5580 /* reg_pptb_local_port 5581 * Local port number. 5582 * Access: Index 5583 */ 5584 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5585 5586 /* reg_pptb_um 5587 * Enables the update of the untagged_buf field. 5588 * Access: RW 5589 */ 5590 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5591 5592 /* reg_pptb_pm 5593 * Enables the update of the prio_to_buff field. 5594 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5595 * Access: RW 5596 */ 5597 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5598 5599 /* reg_pptb_prio_to_buff 5600 * Mapping of switch priority <i> to one of the allocated receive port 5601 * buffers. 5602 * Access: RW 5603 */ 5604 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5605 5606 /* reg_pptb_pm_msb 5607 * Enables the update of the prio_to_buff field. 5608 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5609 * Access: RW 5610 */ 5611 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5612 5613 /* reg_pptb_untagged_buff 5614 * Mapping of untagged frames to one of the allocated receive port buffers. 5615 * Access: RW 5616 * 5617 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5618 * Spectrum, as it maps untagged packets based on the default switch priority. 5619 */ 5620 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5621 5622 /* reg_pptb_prio_to_buff_msb 5623 * Mapping of switch priority <i+8> to one of the allocated receive port 5624 * buffers. 5625 * Access: RW 5626 */ 5627 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5628 5629 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5630 5631 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5632 { 5633 MLXSW_REG_ZERO(pptb, payload); 5634 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5635 mlxsw_reg_pptb_local_port_set(payload, local_port); 5636 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5637 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5638 } 5639 5640 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5641 u8 buff) 5642 { 5643 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5644 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5645 } 5646 5647 /* PBMC - Port Buffer Management Control Register 5648 * ---------------------------------------------- 5649 * The PBMC register configures and retrieves the port packet buffer 5650 * allocation for different Prios, and the Pause threshold management. 5651 */ 5652 #define MLXSW_REG_PBMC_ID 0x500C 5653 #define MLXSW_REG_PBMC_LEN 0x6C 5654 5655 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5656 5657 /* reg_pbmc_local_port 5658 * Local port number. 5659 * Access: Index 5660 */ 5661 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5662 5663 /* reg_pbmc_xoff_timer_value 5664 * When device generates a pause frame, it uses this value as the pause 5665 * timer (time for the peer port to pause in quota-512 bit time). 5666 * Access: RW 5667 */ 5668 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5669 5670 /* reg_pbmc_xoff_refresh 5671 * The time before a new pause frame should be sent to refresh the pause RW 5672 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5673 * time). 5674 * Access: RW 5675 */ 5676 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5677 5678 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5679 5680 /* reg_pbmc_buf_lossy 5681 * The field indicates if the buffer is lossy. 5682 * 0 - Lossless 5683 * 1 - Lossy 5684 * Access: RW 5685 */ 5686 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5687 5688 /* reg_pbmc_buf_epsb 5689 * Eligible for Port Shared buffer. 5690 * If epsb is set, packets assigned to buffer are allowed to insert the port 5691 * shared buffer. 5692 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5693 * Access: RW 5694 */ 5695 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5696 5697 /* reg_pbmc_buf_size 5698 * The part of the packet buffer array is allocated for the specific buffer. 5699 * Units are represented in cells. 5700 * Access: RW 5701 */ 5702 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5703 5704 /* reg_pbmc_buf_xoff_threshold 5705 * Once the amount of data in the buffer goes above this value, device 5706 * starts sending PFC frames for all priorities associated with the 5707 * buffer. Units are represented in cells. Reserved in case of lossy 5708 * buffer. 5709 * Access: RW 5710 * 5711 * Note: In Spectrum, reserved for buffer[9]. 5712 */ 5713 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5714 0x08, 0x04, false); 5715 5716 /* reg_pbmc_buf_xon_threshold 5717 * When the amount of data in the buffer goes below this value, device 5718 * stops sending PFC frames for the priorities associated with the 5719 * buffer. Units are represented in cells. Reserved in case of lossy 5720 * buffer. 5721 * Access: RW 5722 * 5723 * Note: In Spectrum, reserved for buffer[9]. 5724 */ 5725 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5726 0x08, 0x04, false); 5727 5728 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5729 u16 xoff_timer_value, u16 xoff_refresh) 5730 { 5731 MLXSW_REG_ZERO(pbmc, payload); 5732 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5733 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5734 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5735 } 5736 5737 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5738 int buf_index, 5739 u16 size) 5740 { 5741 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5742 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5743 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5744 } 5745 5746 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5747 int buf_index, u16 size, 5748 u16 threshold) 5749 { 5750 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5751 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5752 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5753 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5754 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5755 } 5756 5757 /* PSPA - Port Switch Partition Allocation 5758 * --------------------------------------- 5759 * Controls the association of a port with a switch partition and enables 5760 * configuring ports as stacking ports. 5761 */ 5762 #define MLXSW_REG_PSPA_ID 0x500D 5763 #define MLXSW_REG_PSPA_LEN 0x8 5764 5765 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5766 5767 /* reg_pspa_swid 5768 * Switch partition ID. 5769 * Access: RW 5770 */ 5771 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5772 5773 /* reg_pspa_local_port 5774 * Local port number. 5775 * Access: Index 5776 */ 5777 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5778 5779 /* reg_pspa_sub_port 5780 * Virtual port within the local port. Set to 0 when virtual ports are 5781 * disabled on the local port. 5782 * Access: Index 5783 */ 5784 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5785 5786 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5787 { 5788 MLXSW_REG_ZERO(pspa, payload); 5789 mlxsw_reg_pspa_swid_set(payload, swid); 5790 mlxsw_reg_pspa_local_port_set(payload, local_port); 5791 mlxsw_reg_pspa_sub_port_set(payload, 0); 5792 } 5793 5794 /* PMAOS - Ports Module Administrative and Operational Status 5795 * ---------------------------------------------------------- 5796 * This register configures and retrieves the per module status. 5797 */ 5798 #define MLXSW_REG_PMAOS_ID 0x5012 5799 #define MLXSW_REG_PMAOS_LEN 0x10 5800 5801 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5802 5803 /* reg_pmaos_rst 5804 * Module reset toggle. 5805 * Note: Setting reset while module is plugged-in will result in transition to 5806 * "initializing" operational state. 5807 * Access: OP 5808 */ 5809 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5810 5811 /* reg_pmaos_slot_index 5812 * Slot index. 5813 * Access: Index 5814 */ 5815 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5816 5817 /* reg_pmaos_module 5818 * Module number. 5819 * Access: Index 5820 */ 5821 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5822 5823 enum mlxsw_reg_pmaos_admin_status { 5824 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5825 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5826 /* If the module is active and then unplugged, or experienced an error 5827 * event, the operational status should go to "disabled" and can only 5828 * be enabled upon explicit enable command. 5829 */ 5830 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5831 }; 5832 5833 /* reg_pmaos_admin_status 5834 * Module administrative state (the desired state of the module). 5835 * Note: To disable a module, all ports associated with the port must be 5836 * administatively down first. 5837 * Access: RW 5838 */ 5839 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5840 5841 /* reg_pmaos_ase 5842 * Admin state update enable. 5843 * If this bit is set, admin state will be updated based on admin_state field. 5844 * Only relevant on Set() operations. 5845 * Access: WO 5846 */ 5847 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5848 5849 /* reg_pmaos_ee 5850 * Event update enable. 5851 * If this bit is set, event generation will be updated based on the e field. 5852 * Only relevant on Set operations. 5853 * Access: WO 5854 */ 5855 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5856 5857 enum mlxsw_reg_pmaos_e { 5858 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5859 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5860 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5861 }; 5862 5863 /* reg_pmaos_e 5864 * Event Generation on operational state change. 5865 * Access: RW 5866 */ 5867 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5868 5869 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5870 { 5871 MLXSW_REG_ZERO(pmaos, payload); 5872 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5873 mlxsw_reg_pmaos_module_set(payload, module); 5874 } 5875 5876 /* PPLR - Port Physical Loopback Register 5877 * -------------------------------------- 5878 * This register allows configuration of the port's loopback mode. 5879 */ 5880 #define MLXSW_REG_PPLR_ID 0x5018 5881 #define MLXSW_REG_PPLR_LEN 0x8 5882 5883 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5884 5885 /* reg_pplr_local_port 5886 * Local port number. 5887 * Access: Index 5888 */ 5889 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5890 5891 /* Phy local loopback. When set the port's egress traffic is looped back 5892 * to the receiver and the port transmitter is disabled. 5893 */ 5894 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5895 5896 /* reg_pplr_lb_en 5897 * Loopback enable. 5898 * Access: RW 5899 */ 5900 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5901 5902 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5903 bool phy_local) 5904 { 5905 MLXSW_REG_ZERO(pplr, payload); 5906 mlxsw_reg_pplr_local_port_set(payload, local_port); 5907 mlxsw_reg_pplr_lb_en_set(payload, 5908 phy_local ? 5909 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5910 } 5911 5912 /* PMTDB - Port Module To local DataBase Register 5913 * ---------------------------------------------- 5914 * The PMTDB register allows to query the possible module<->local port 5915 * mapping than can be used in PMLP. It does not represent the actual/current 5916 * mapping of the local to module. Actual mapping is only defined by PMLP. 5917 */ 5918 #define MLXSW_REG_PMTDB_ID 0x501A 5919 #define MLXSW_REG_PMTDB_LEN 0x40 5920 5921 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 5922 5923 /* reg_pmtdb_slot_index 5924 * Slot index (0: Main board). 5925 * Access: Index 5926 */ 5927 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 5928 5929 /* reg_pmtdb_module 5930 * Module number. 5931 * Access: Index 5932 */ 5933 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 5934 5935 /* reg_pmtdb_ports_width 5936 * Port's width 5937 * Access: Index 5938 */ 5939 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 5940 5941 /* reg_pmtdb_num_ports 5942 * Number of ports in a single module (split/breakout) 5943 * Access: Index 5944 */ 5945 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 5946 5947 enum mlxsw_reg_pmtdb_status { 5948 MLXSW_REG_PMTDB_STATUS_SUCCESS, 5949 }; 5950 5951 /* reg_pmtdb_status 5952 * Status 5953 * Access: RO 5954 */ 5955 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 5956 5957 /* reg_pmtdb_port_num 5958 * The local_port value which can be assigned to the module. 5959 * In case of more than one port, port<x> represent the /<x> port of 5960 * the module. 5961 * Access: RO 5962 */ 5963 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 5964 5965 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 5966 u8 ports_width, u8 num_ports) 5967 { 5968 MLXSW_REG_ZERO(pmtdb, payload); 5969 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 5970 mlxsw_reg_pmtdb_module_set(payload, module); 5971 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 5972 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 5973 } 5974 5975 /* PMECR - Ports Mapping Event Configuration Register 5976 * -------------------------------------------------- 5977 * The PMECR register is used to enable/disable event triggering 5978 * in case of local port mapping change. 5979 */ 5980 #define MLXSW_REG_PMECR_ID 0x501B 5981 #define MLXSW_REG_PMECR_LEN 0x20 5982 5983 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 5984 5985 /* reg_pmecr_local_port 5986 * Local port number. 5987 * Access: Index 5988 */ 5989 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 5990 5991 /* reg_pmecr_ee 5992 * Event update enable. If this bit is set, event generation will be updated 5993 * based on the e field. Only relevant on Set operations. 5994 * Access: WO 5995 */ 5996 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 5997 5998 /* reg_pmecr_eswi 5999 * Software ignore enable bit. If this bit is set, the value of swi is used. 6000 * If this bit is clear, the value of swi is ignored. 6001 * Only relevant on Set operations. 6002 * Access: WO 6003 */ 6004 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6005 6006 /* reg_pmecr_swi 6007 * Software ignore. If this bit is set, the device shouldn't generate events 6008 * in case of PMLP SET operation but only upon self local port mapping change 6009 * (if applicable according to e configuration). This is supplementary 6010 * configuration on top of e value. 6011 * Access: RW 6012 */ 6013 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6014 6015 enum mlxsw_reg_pmecr_e { 6016 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6017 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6018 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6019 }; 6020 6021 /* reg_pmecr_e 6022 * Event generation on local port mapping change. 6023 * Access: RW 6024 */ 6025 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6026 6027 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6028 enum mlxsw_reg_pmecr_e e) 6029 { 6030 MLXSW_REG_ZERO(pmecr, payload); 6031 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6032 mlxsw_reg_pmecr_e_set(payload, e); 6033 mlxsw_reg_pmecr_ee_set(payload, true); 6034 mlxsw_reg_pmecr_swi_set(payload, true); 6035 mlxsw_reg_pmecr_eswi_set(payload, true); 6036 } 6037 6038 /* PMPE - Port Module Plug/Unplug Event Register 6039 * --------------------------------------------- 6040 * This register reports any operational status change of a module. 6041 * A change in the module’s state will generate an event only if the change 6042 * happens after arming the event mechanism. Any changes to the module state 6043 * while the event mechanism is not armed will not be reported. Software can 6044 * query the PMPE register for module status. 6045 */ 6046 #define MLXSW_REG_PMPE_ID 0x5024 6047 #define MLXSW_REG_PMPE_LEN 0x10 6048 6049 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6050 6051 /* reg_pmpe_slot_index 6052 * Slot index. 6053 * Access: Index 6054 */ 6055 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6056 6057 /* reg_pmpe_module 6058 * Module number. 6059 * Access: Index 6060 */ 6061 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6062 6063 enum mlxsw_reg_pmpe_module_status { 6064 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6065 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6066 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6067 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6068 }; 6069 6070 /* reg_pmpe_module_status 6071 * Module status. 6072 * Access: RO 6073 */ 6074 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6075 6076 /* reg_pmpe_error_type 6077 * Module error details. 6078 * Access: RO 6079 */ 6080 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6081 6082 /* PDDR - Port Diagnostics Database Register 6083 * ----------------------------------------- 6084 * The PDDR enables to read the Phy debug database 6085 */ 6086 #define MLXSW_REG_PDDR_ID 0x5031 6087 #define MLXSW_REG_PDDR_LEN 0x100 6088 6089 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6090 6091 /* reg_pddr_local_port 6092 * Local port number. 6093 * Access: Index 6094 */ 6095 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6096 6097 enum mlxsw_reg_pddr_page_select { 6098 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6099 }; 6100 6101 /* reg_pddr_page_select 6102 * Page select index. 6103 * Access: Index 6104 */ 6105 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6106 6107 enum mlxsw_reg_pddr_trblsh_group_opcode { 6108 /* Monitor opcodes */ 6109 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6110 }; 6111 6112 /* reg_pddr_group_opcode 6113 * Group selector. 6114 * Access: Index 6115 */ 6116 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6117 6118 /* reg_pddr_status_opcode 6119 * Group selector. 6120 * Access: RO 6121 */ 6122 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6123 6124 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6125 u8 page_select) 6126 { 6127 MLXSW_REG_ZERO(pddr, payload); 6128 mlxsw_reg_pddr_local_port_set(payload, local_port); 6129 mlxsw_reg_pddr_page_select_set(payload, page_select); 6130 } 6131 6132 /* PMMP - Port Module Memory Map Properties Register 6133 * ------------------------------------------------- 6134 * The PMMP register allows to override the module memory map advertisement. 6135 * The register can only be set when the module is disabled by PMAOS register. 6136 */ 6137 #define MLXSW_REG_PMMP_ID 0x5044 6138 #define MLXSW_REG_PMMP_LEN 0x2C 6139 6140 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6141 6142 /* reg_pmmp_module 6143 * Module number. 6144 * Access: Index 6145 */ 6146 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6147 6148 /* reg_pmmp_slot_index 6149 * Slot index. 6150 * Access: Index 6151 */ 6152 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6153 6154 /* reg_pmmp_sticky 6155 * When set, will keep eeprom_override values after plug-out event. 6156 * Access: OP 6157 */ 6158 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6159 6160 /* reg_pmmp_eeprom_override_mask 6161 * Write mask bit (negative polarity). 6162 * 0 - Allow write 6163 * 1 - Ignore write 6164 * On write, indicates which of the bits from eeprom_override field are 6165 * updated. 6166 * Access: WO 6167 */ 6168 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6169 6170 enum { 6171 /* Set module to low power mode */ 6172 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6173 }; 6174 6175 /* reg_pmmp_eeprom_override 6176 * Override / ignore EEPROM advertisement properties bitmask 6177 * Access: RW 6178 */ 6179 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6180 6181 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6182 { 6183 MLXSW_REG_ZERO(pmmp, payload); 6184 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6185 mlxsw_reg_pmmp_module_set(payload, module); 6186 } 6187 6188 /* PLLP - Port Local port to Label Port mapping Register 6189 * ----------------------------------------------------- 6190 * The PLLP register returns the mapping from Local Port into Label Port. 6191 */ 6192 #define MLXSW_REG_PLLP_ID 0x504A 6193 #define MLXSW_REG_PLLP_LEN 0x10 6194 6195 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6196 6197 /* reg_pllp_local_port 6198 * Local port number. 6199 * Access: Index 6200 */ 6201 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6202 6203 /* reg_pllp_label_port 6204 * Front panel label of the port. 6205 * Access: RO 6206 */ 6207 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6208 6209 /* reg_pllp_split_num 6210 * Label split mapping for local_port. 6211 * Access: RO 6212 */ 6213 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6214 6215 /* reg_pllp_slot_index 6216 * Slot index (0: Main board). 6217 * Access: RO 6218 */ 6219 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6220 6221 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6222 { 6223 MLXSW_REG_ZERO(pllp, payload); 6224 mlxsw_reg_pllp_local_port_set(payload, local_port); 6225 } 6226 6227 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6228 u8 *split_num, u8 *slot_index) 6229 { 6230 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6231 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6232 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6233 } 6234 6235 /* PMTM - Port Module Type Mapping Register 6236 * ---------------------------------------- 6237 * The PMTM register allows query or configuration of module types. 6238 * The register can only be set when the module is disabled by PMAOS register 6239 */ 6240 #define MLXSW_REG_PMTM_ID 0x5067 6241 #define MLXSW_REG_PMTM_LEN 0x10 6242 6243 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6244 6245 /* reg_pmtm_slot_index 6246 * Slot index. 6247 * Access: Index 6248 */ 6249 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6250 6251 /* reg_pmtm_module 6252 * Module number. 6253 * Access: Index 6254 */ 6255 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6256 6257 enum mlxsw_reg_pmtm_module_type { 6258 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6259 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6260 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6261 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6262 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6263 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6264 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6265 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6266 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6267 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6268 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6269 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6270 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6271 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6272 }; 6273 6274 /* reg_pmtm_module_type 6275 * Module type. 6276 * Access: RW 6277 */ 6278 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6279 6280 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6281 { 6282 MLXSW_REG_ZERO(pmtm, payload); 6283 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6284 mlxsw_reg_pmtm_module_set(payload, module); 6285 } 6286 6287 /* HTGT - Host Trap Group Table 6288 * ---------------------------- 6289 * Configures the properties for forwarding to CPU. 6290 */ 6291 #define MLXSW_REG_HTGT_ID 0x7002 6292 #define MLXSW_REG_HTGT_LEN 0x20 6293 6294 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6295 6296 /* reg_htgt_swid 6297 * Switch partition ID. 6298 * Access: Index 6299 */ 6300 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6301 6302 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6303 6304 /* reg_htgt_type 6305 * CPU path type. 6306 * Access: RW 6307 */ 6308 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6309 6310 enum mlxsw_reg_htgt_trap_group { 6311 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6312 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6313 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6314 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6315 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6316 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6317 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6318 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6319 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6320 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6321 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6322 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6323 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6324 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6325 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6326 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6327 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6328 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6329 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6330 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6331 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6332 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6333 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6334 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6335 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6336 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6337 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6338 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6339 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6340 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6341 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6342 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6343 MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL, 6344 6345 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6346 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6347 }; 6348 6349 /* reg_htgt_trap_group 6350 * Trap group number. User defined number specifying which trap groups 6351 * should be forwarded to the CPU. The mapping between trap IDs and trap 6352 * groups is configured using HPKT register. 6353 * Access: Index 6354 */ 6355 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6356 6357 enum { 6358 MLXSW_REG_HTGT_POLICER_DISABLE, 6359 MLXSW_REG_HTGT_POLICER_ENABLE, 6360 }; 6361 6362 /* reg_htgt_pide 6363 * Enable policer ID specified using 'pid' field. 6364 * Access: RW 6365 */ 6366 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6367 6368 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6369 6370 /* reg_htgt_pid 6371 * Policer ID for the trap group. 6372 * Access: RW 6373 */ 6374 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6375 6376 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6377 6378 /* reg_htgt_mirror_action 6379 * Mirror action to use. 6380 * 0 - Trap to CPU. 6381 * 1 - Trap to CPU and mirror to a mirroring agent. 6382 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6383 * Access: RW 6384 * 6385 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6386 */ 6387 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6388 6389 /* reg_htgt_mirroring_agent 6390 * Mirroring agent. 6391 * Access: RW 6392 */ 6393 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6394 6395 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6396 6397 /* reg_htgt_priority 6398 * Trap group priority. 6399 * In case a packet matches multiple classification rules, the packet will 6400 * only be trapped once, based on the trap ID associated with the group (via 6401 * register HPKT) with the highest priority. 6402 * Supported values are 0-7, with 7 represnting the highest priority. 6403 * Access: RW 6404 * 6405 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6406 * by the 'trap_group' field. 6407 */ 6408 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6409 6410 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6411 6412 /* reg_htgt_local_path_cpu_tclass 6413 * CPU ingress traffic class for the trap group. 6414 * Access: RW 6415 */ 6416 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6417 6418 enum mlxsw_reg_htgt_local_path_rdq { 6419 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6420 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6421 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6422 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6423 }; 6424 /* reg_htgt_local_path_rdq 6425 * Receive descriptor queue (RDQ) to use for the trap group. 6426 * Access: RW 6427 */ 6428 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6429 6430 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6431 u8 priority, u8 tc) 6432 { 6433 MLXSW_REG_ZERO(htgt, payload); 6434 6435 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6436 mlxsw_reg_htgt_pide_set(payload, 6437 MLXSW_REG_HTGT_POLICER_DISABLE); 6438 } else { 6439 mlxsw_reg_htgt_pide_set(payload, 6440 MLXSW_REG_HTGT_POLICER_ENABLE); 6441 mlxsw_reg_htgt_pid_set(payload, policer_id); 6442 } 6443 6444 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6445 mlxsw_reg_htgt_trap_group_set(payload, group); 6446 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6447 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6448 mlxsw_reg_htgt_priority_set(payload, priority); 6449 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6450 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6451 } 6452 6453 /* HPKT - Host Packet Trap 6454 * ----------------------- 6455 * Configures trap IDs inside trap groups. 6456 */ 6457 #define MLXSW_REG_HPKT_ID 0x7003 6458 #define MLXSW_REG_HPKT_LEN 0x10 6459 6460 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6461 6462 enum { 6463 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6464 MLXSW_REG_HPKT_ACK_REQUIRED, 6465 }; 6466 6467 /* reg_hpkt_ack 6468 * Require acknowledgements from the host for events. 6469 * If set, then the device will wait for the event it sent to be acknowledged 6470 * by the host. This option is only relevant for event trap IDs. 6471 * Access: RW 6472 * 6473 * Note: Currently not supported by firmware. 6474 */ 6475 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6476 6477 enum mlxsw_reg_hpkt_action { 6478 MLXSW_REG_HPKT_ACTION_FORWARD, 6479 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6480 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6481 MLXSW_REG_HPKT_ACTION_DISCARD, 6482 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6483 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6484 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6485 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6486 }; 6487 6488 /* reg_hpkt_action 6489 * Action to perform on packet when trapped. 6490 * 0 - No action. Forward to CPU based on switching rules. 6491 * 1 - Trap to CPU (CPU receives sole copy). 6492 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6493 * 3 - Discard. 6494 * 4 - Soft discard (allow other traps to act on the packet). 6495 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6496 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6497 * 15 - Restore the firmware's default action. 6498 * Access: RW 6499 * 6500 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6501 * addressed to the CPU. 6502 */ 6503 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6504 6505 /* reg_hpkt_trap_group 6506 * Trap group to associate the trap with. 6507 * Access: RW 6508 */ 6509 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6510 6511 /* reg_hpkt_trap_id 6512 * Trap ID. 6513 * Access: Index 6514 * 6515 * Note: A trap ID can only be associated with a single trap group. The device 6516 * will associate the trap ID with the last trap group configured. 6517 */ 6518 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6519 6520 enum { 6521 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6522 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6523 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6524 }; 6525 6526 /* reg_hpkt_ctrl 6527 * Configure dedicated buffer resources for control packets. 6528 * Ignored by SwitchX-2. 6529 * 0 - Keep factory defaults. 6530 * 1 - Do not use control buffer for this trap ID. 6531 * 2 - Use control buffer for this trap ID. 6532 * Access: RW 6533 */ 6534 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6535 6536 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6537 enum mlxsw_reg_htgt_trap_group trap_group, 6538 bool is_ctrl) 6539 { 6540 MLXSW_REG_ZERO(hpkt, payload); 6541 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6542 mlxsw_reg_hpkt_action_set(payload, action); 6543 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6544 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6545 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6546 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6547 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6548 } 6549 6550 /* RGCR - Router General Configuration Register 6551 * -------------------------------------------- 6552 * The register is used for setting up the router configuration. 6553 */ 6554 #define MLXSW_REG_RGCR_ID 0x8001 6555 #define MLXSW_REG_RGCR_LEN 0x28 6556 6557 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6558 6559 /* reg_rgcr_ipv4_en 6560 * IPv4 router enable. 6561 * Access: RW 6562 */ 6563 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6564 6565 /* reg_rgcr_ipv6_en 6566 * IPv6 router enable. 6567 * Access: RW 6568 */ 6569 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6570 6571 /* reg_rgcr_max_router_interfaces 6572 * Defines the maximum number of active router interfaces for all virtual 6573 * routers. 6574 * Access: RW 6575 */ 6576 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6577 6578 /* reg_rgcr_usp 6579 * Update switch priority and packet color. 6580 * 0 - Preserve the value of Switch Priority and packet color. 6581 * 1 - Recalculate the value of Switch Priority and packet color. 6582 * Access: RW 6583 * 6584 * Note: Not supported by SwitchX and SwitchX-2. 6585 */ 6586 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6587 6588 /* reg_rgcr_pcp_rw 6589 * Indicates how to handle the pcp_rewrite_en value: 6590 * 0 - Preserve the value of pcp_rewrite_en. 6591 * 2 - Disable PCP rewrite. 6592 * 3 - Enable PCP rewrite. 6593 * Access: RW 6594 * 6595 * Note: Not supported by SwitchX and SwitchX-2. 6596 */ 6597 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6598 6599 /* reg_rgcr_activity_dis 6600 * Activity disable: 6601 * 0 - Activity will be set when an entry is hit (default). 6602 * 1 - Activity will not be set when an entry is hit. 6603 * 6604 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6605 * (RALUE). 6606 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6607 * Entry (RAUHT). 6608 * Bits 2:7 are reserved. 6609 * Access: RW 6610 * 6611 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6612 */ 6613 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6614 6615 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6616 bool ipv6_en) 6617 { 6618 MLXSW_REG_ZERO(rgcr, payload); 6619 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6620 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6621 } 6622 6623 /* RITR - Router Interface Table Register 6624 * -------------------------------------- 6625 * The register is used to configure the router interface table. 6626 */ 6627 #define MLXSW_REG_RITR_ID 0x8002 6628 #define MLXSW_REG_RITR_LEN 0x40 6629 6630 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6631 6632 /* reg_ritr_enable 6633 * Enables routing on the router interface. 6634 * Access: RW 6635 */ 6636 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6637 6638 /* reg_ritr_ipv4 6639 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6640 * interface. 6641 * Access: RW 6642 */ 6643 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6644 6645 /* reg_ritr_ipv6 6646 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6647 * interface. 6648 * Access: RW 6649 */ 6650 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6651 6652 /* reg_ritr_ipv4_mc 6653 * IPv4 multicast routing enable. 6654 * Access: RW 6655 */ 6656 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6657 6658 /* reg_ritr_ipv6_mc 6659 * IPv6 multicast routing enable. 6660 * Access: RW 6661 */ 6662 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6663 6664 enum mlxsw_reg_ritr_if_type { 6665 /* VLAN interface. */ 6666 MLXSW_REG_RITR_VLAN_IF, 6667 /* FID interface. */ 6668 MLXSW_REG_RITR_FID_IF, 6669 /* Sub-port interface. */ 6670 MLXSW_REG_RITR_SP_IF, 6671 /* Loopback Interface. */ 6672 MLXSW_REG_RITR_LOOPBACK_IF, 6673 }; 6674 6675 /* reg_ritr_type 6676 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6677 * Access: RW 6678 */ 6679 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6680 6681 enum { 6682 MLXSW_REG_RITR_RIF_CREATE, 6683 MLXSW_REG_RITR_RIF_DEL, 6684 }; 6685 6686 /* reg_ritr_op 6687 * Opcode: 6688 * 0 - Create or edit RIF. 6689 * 1 - Delete RIF. 6690 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6691 * is not supported. An interface must be deleted and re-created in order 6692 * to update properties. 6693 * Access: WO 6694 */ 6695 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6696 6697 /* reg_ritr_rif 6698 * Router interface index. A pointer to the Router Interface Table. 6699 * Access: Index 6700 */ 6701 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6702 6703 /* reg_ritr_ipv4_fe 6704 * IPv4 Forwarding Enable. 6705 * Enables routing of IPv4 traffic on the router interface. When disabled, 6706 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6707 * Not supported in SwitchX-2. 6708 * Access: RW 6709 */ 6710 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6711 6712 /* reg_ritr_ipv6_fe 6713 * IPv6 Forwarding Enable. 6714 * Enables routing of IPv6 traffic on the router interface. When disabled, 6715 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6716 * Not supported in SwitchX-2. 6717 * Access: RW 6718 */ 6719 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6720 6721 /* reg_ritr_ipv4_mc_fe 6722 * IPv4 Multicast Forwarding Enable. 6723 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6724 * will be enabled. 6725 * Access: RW 6726 */ 6727 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6728 6729 /* reg_ritr_ipv6_mc_fe 6730 * IPv6 Multicast Forwarding Enable. 6731 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6732 * will be enabled. 6733 * Access: RW 6734 */ 6735 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6736 6737 /* reg_ritr_lb_en 6738 * Loop-back filter enable for unicast packets. 6739 * If the flag is set then loop-back filter for unicast packets is 6740 * implemented on the RIF. Multicast packets are always subject to 6741 * loop-back filtering. 6742 * Access: RW 6743 */ 6744 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6745 6746 /* reg_ritr_virtual_router 6747 * Virtual router ID associated with the router interface. 6748 * Access: RW 6749 */ 6750 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6751 6752 /* reg_ritr_mtu 6753 * Router interface MTU. 6754 * Access: RW 6755 */ 6756 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6757 6758 /* reg_ritr_if_swid 6759 * Switch partition ID. 6760 * Access: RW 6761 */ 6762 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6763 6764 /* reg_ritr_if_mac_profile_id 6765 * MAC msb profile ID. 6766 * Access: RW 6767 */ 6768 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6769 6770 /* reg_ritr_if_mac 6771 * Router interface MAC address. 6772 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6773 * Access: RW 6774 */ 6775 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6776 6777 /* reg_ritr_if_vrrp_id_ipv6 6778 * VRRP ID for IPv6 6779 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6780 * Access: RW 6781 */ 6782 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6783 6784 /* reg_ritr_if_vrrp_id_ipv4 6785 * VRRP ID for IPv4 6786 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6787 * Access: RW 6788 */ 6789 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6790 6791 /* VLAN Interface */ 6792 6793 /* reg_ritr_vlan_if_vlan_id 6794 * VLAN ID. 6795 * Access: RW 6796 */ 6797 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6798 6799 /* reg_ritr_vlan_if_efid 6800 * Egress FID. 6801 * Used to connect the RIF to a bridge. 6802 * Access: RW 6803 * 6804 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6805 */ 6806 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6807 6808 /* FID Interface */ 6809 6810 /* reg_ritr_fid_if_fid 6811 * Filtering ID. Used to connect a bridge to the router. 6812 * When legacy bridge model is used, only FIDs from the vFID range are 6813 * supported. When unified bridge model is used, this is the egress FID for 6814 * router to bridge. 6815 * Access: RW 6816 */ 6817 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6818 6819 /* Sub-port Interface */ 6820 6821 /* reg_ritr_sp_if_lag 6822 * LAG indication. When this bit is set the system_port field holds the 6823 * LAG identifier. 6824 * Access: RW 6825 */ 6826 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6827 6828 /* reg_ritr_sp_system_port 6829 * Port unique indentifier. When lag bit is set, this field holds the 6830 * lag_id in bits 0:9. 6831 * Access: RW 6832 */ 6833 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6834 6835 /* reg_ritr_sp_if_efid 6836 * Egress filtering ID. 6837 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6838 * the VID. 6839 * Access: RW 6840 * 6841 * Note: Reserved when legacy bridge model is used. 6842 */ 6843 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6844 6845 /* reg_ritr_sp_if_vid 6846 * VLAN ID. 6847 * Access: RW 6848 */ 6849 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6850 6851 /* Loopback Interface */ 6852 6853 enum mlxsw_reg_ritr_loopback_protocol { 6854 /* IPinIP IPv4 underlay Unicast */ 6855 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6856 /* IPinIP IPv6 underlay Unicast */ 6857 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6858 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6859 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6860 }; 6861 6862 /* reg_ritr_loopback_protocol 6863 * Access: RW 6864 */ 6865 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6866 6867 enum mlxsw_reg_ritr_loopback_ipip_type { 6868 /* Tunnel is IPinIP. */ 6869 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6870 /* Tunnel is GRE, no key. */ 6871 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6872 /* Tunnel is GRE, with a key. */ 6873 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6874 }; 6875 6876 /* reg_ritr_loopback_ipip_type 6877 * Encapsulation type. 6878 * Access: RW 6879 */ 6880 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6881 6882 enum mlxsw_reg_ritr_loopback_ipip_options { 6883 /* The key is defined by gre_key. */ 6884 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6885 }; 6886 6887 /* reg_ritr_loopback_ipip_options 6888 * Access: RW 6889 */ 6890 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6891 6892 /* reg_ritr_loopback_ipip_uvr 6893 * Underlay Virtual Router ID. 6894 * Range is 0..cap_max_virtual_routers-1. 6895 * Reserved for Spectrum-2. 6896 * Access: RW 6897 */ 6898 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6899 6900 /* reg_ritr_loopback_ipip_underlay_rif 6901 * Underlay ingress router interface. 6902 * Reserved for Spectrum. 6903 * Access: RW 6904 */ 6905 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6906 6907 /* reg_ritr_loopback_ipip_usip* 6908 * Encapsulation Underlay source IP. 6909 * Access: RW 6910 */ 6911 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6912 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6913 6914 /* reg_ritr_loopback_ipip_gre_key 6915 * GRE Key. 6916 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6917 * Access: RW 6918 */ 6919 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6920 6921 /* Shared between ingress/egress */ 6922 enum mlxsw_reg_ritr_counter_set_type { 6923 /* No Count. */ 6924 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6925 /* Basic. Used for router interfaces, counting the following: 6926 * - Error and Discard counters. 6927 * - Unicast, Multicast and Broadcast counters. Sharing the 6928 * same set of counters for the different type of traffic 6929 * (IPv4, IPv6 and mpls). 6930 */ 6931 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6932 }; 6933 6934 /* reg_ritr_ingress_counter_index 6935 * Counter Index for flow counter. 6936 * Access: RW 6937 */ 6938 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6939 6940 /* reg_ritr_ingress_counter_set_type 6941 * Igress Counter Set Type for router interface counter. 6942 * Access: RW 6943 */ 6944 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6945 6946 /* reg_ritr_egress_counter_index 6947 * Counter Index for flow counter. 6948 * Access: RW 6949 */ 6950 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6951 6952 /* reg_ritr_egress_counter_set_type 6953 * Egress Counter Set Type for router interface counter. 6954 * Access: RW 6955 */ 6956 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6957 6958 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6959 bool enable, bool egress) 6960 { 6961 enum mlxsw_reg_ritr_counter_set_type set_type; 6962 6963 if (enable) 6964 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6965 else 6966 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6967 6968 if (egress) { 6969 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6970 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6971 } else { 6972 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 6973 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6974 } 6975 } 6976 6977 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6978 { 6979 MLXSW_REG_ZERO(ritr, payload); 6980 mlxsw_reg_ritr_rif_set(payload, rif); 6981 } 6982 6983 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6984 u16 system_port, u16 efid, u16 vid) 6985 { 6986 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6987 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6988 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 6989 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6990 } 6991 6992 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6993 enum mlxsw_reg_ritr_if_type type, 6994 u16 rif, u16 vr_id, u16 mtu) 6995 { 6996 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6997 6998 MLXSW_REG_ZERO(ritr, payload); 6999 mlxsw_reg_ritr_enable_set(payload, enable); 7000 mlxsw_reg_ritr_ipv4_set(payload, 1); 7001 mlxsw_reg_ritr_ipv6_set(payload, 1); 7002 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7003 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7004 mlxsw_reg_ritr_type_set(payload, type); 7005 mlxsw_reg_ritr_op_set(payload, op); 7006 mlxsw_reg_ritr_rif_set(payload, rif); 7007 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7008 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7009 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7010 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7011 mlxsw_reg_ritr_lb_en_set(payload, 1); 7012 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7013 mlxsw_reg_ritr_mtu_set(payload, mtu); 7014 } 7015 7016 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7017 { 7018 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7019 } 7020 7021 static inline void 7022 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7023 u16 mtu, const char *mac, u8 mac_profile_id, 7024 u16 vlan_id, u16 efid) 7025 { 7026 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7027 7028 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7029 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7030 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7031 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7032 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7033 } 7034 7035 static inline void 7036 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7037 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7038 enum mlxsw_reg_ritr_loopback_ipip_options options, 7039 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7040 { 7041 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7042 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7043 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7044 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7045 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7046 } 7047 7048 static inline void 7049 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7050 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7051 enum mlxsw_reg_ritr_loopback_ipip_options options, 7052 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7053 { 7054 mlxsw_reg_ritr_loopback_protocol_set(payload, 7055 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7056 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7057 uvr_id, underlay_rif, gre_key); 7058 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7059 } 7060 7061 static inline void 7062 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7063 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7064 enum mlxsw_reg_ritr_loopback_ipip_options options, 7065 u16 uvr_id, u16 underlay_rif, 7066 const struct in6_addr *usip, u32 gre_key) 7067 { 7068 enum mlxsw_reg_ritr_loopback_protocol protocol = 7069 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7070 7071 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7072 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7073 uvr_id, underlay_rif, gre_key); 7074 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7075 (const char *)usip); 7076 } 7077 7078 /* RTAR - Router TCAM Allocation Register 7079 * -------------------------------------- 7080 * This register is used for allocation of regions in the TCAM table. 7081 */ 7082 #define MLXSW_REG_RTAR_ID 0x8004 7083 #define MLXSW_REG_RTAR_LEN 0x20 7084 7085 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7086 7087 enum mlxsw_reg_rtar_op { 7088 MLXSW_REG_RTAR_OP_ALLOCATE, 7089 MLXSW_REG_RTAR_OP_RESIZE, 7090 MLXSW_REG_RTAR_OP_DEALLOCATE, 7091 }; 7092 7093 /* reg_rtar_op 7094 * Access: WO 7095 */ 7096 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7097 7098 enum mlxsw_reg_rtar_key_type { 7099 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7100 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7101 }; 7102 7103 /* reg_rtar_key_type 7104 * TCAM key type for the region. 7105 * Access: WO 7106 */ 7107 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7108 7109 /* reg_rtar_region_size 7110 * TCAM region size. When allocating/resizing this is the requested 7111 * size, the response is the actual size. 7112 * Note: Actual size may be larger than requested. 7113 * Reserved for op = Deallocate 7114 * Access: WO 7115 */ 7116 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7117 7118 static inline void mlxsw_reg_rtar_pack(char *payload, 7119 enum mlxsw_reg_rtar_op op, 7120 enum mlxsw_reg_rtar_key_type key_type, 7121 u16 region_size) 7122 { 7123 MLXSW_REG_ZERO(rtar, payload); 7124 mlxsw_reg_rtar_op_set(payload, op); 7125 mlxsw_reg_rtar_key_type_set(payload, key_type); 7126 mlxsw_reg_rtar_region_size_set(payload, region_size); 7127 } 7128 7129 /* RATR - Router Adjacency Table Register 7130 * -------------------------------------- 7131 * The RATR register is used to configure the Router Adjacency (next-hop) 7132 * Table. 7133 */ 7134 #define MLXSW_REG_RATR_ID 0x8008 7135 #define MLXSW_REG_RATR_LEN 0x2C 7136 7137 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7138 7139 enum mlxsw_reg_ratr_op { 7140 /* Read */ 7141 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7142 /* Read and clear activity */ 7143 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7144 /* Write Adjacency entry */ 7145 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7146 /* Write Adjacency entry only if the activity is cleared. 7147 * The write may not succeed if the activity is set. There is not 7148 * direct feedback if the write has succeeded or not, however 7149 * the get will reveal the actual entry (SW can compare the get 7150 * response to the set command). 7151 */ 7152 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7153 }; 7154 7155 /* reg_ratr_op 7156 * Note that Write operation may also be used for updating 7157 * counter_set_type and counter_index. In this case all other 7158 * fields must not be updated. 7159 * Access: OP 7160 */ 7161 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7162 7163 /* reg_ratr_v 7164 * Valid bit. Indicates if the adjacency entry is valid. 7165 * Note: the device may need some time before reusing an invalidated 7166 * entry. During this time the entry can not be reused. It is 7167 * recommended to use another entry before reusing an invalidated 7168 * entry (e.g. software can put it at the end of the list for 7169 * reusing). Trying to access an invalidated entry not yet cleared 7170 * by the device results with failure indicating "Try Again" status. 7171 * When valid is '0' then egress_router_interface,trap_action, 7172 * adjacency_parameters and counters are reserved 7173 * Access: RW 7174 */ 7175 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7176 7177 /* reg_ratr_a 7178 * Activity. Set for new entries. Set if a packet lookup has hit on 7179 * the specific entry. To clear the a bit, use "clear activity". 7180 * Access: RO 7181 */ 7182 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7183 7184 enum mlxsw_reg_ratr_type { 7185 /* Ethernet */ 7186 MLXSW_REG_RATR_TYPE_ETHERNET, 7187 /* IPoIB Unicast without GRH. 7188 * Reserved for Spectrum. 7189 */ 7190 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7191 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7192 * adjacency). 7193 * Reserved for Spectrum. 7194 */ 7195 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7196 /* IPoIB Multicast. 7197 * Reserved for Spectrum. 7198 */ 7199 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7200 /* MPLS. 7201 * Reserved for SwitchX/-2. 7202 */ 7203 MLXSW_REG_RATR_TYPE_MPLS, 7204 /* IPinIP Encap. 7205 * Reserved for SwitchX/-2. 7206 */ 7207 MLXSW_REG_RATR_TYPE_IPIP, 7208 }; 7209 7210 /* reg_ratr_type 7211 * Adjacency entry type. 7212 * Access: RW 7213 */ 7214 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7215 7216 /* reg_ratr_adjacency_index_low 7217 * Bits 15:0 of index into the adjacency table. 7218 * For SwitchX and SwitchX-2, the adjacency table is linear and 7219 * used for adjacency entries only. 7220 * For Spectrum, the index is to the KVD linear. 7221 * Access: Index 7222 */ 7223 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7224 7225 /* reg_ratr_egress_router_interface 7226 * Range is 0 .. cap_max_router_interfaces - 1 7227 * Access: RW 7228 */ 7229 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7230 7231 enum mlxsw_reg_ratr_trap_action { 7232 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7233 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7234 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7235 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7236 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7237 }; 7238 7239 /* reg_ratr_trap_action 7240 * see mlxsw_reg_ratr_trap_action 7241 * Access: RW 7242 */ 7243 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7244 7245 /* reg_ratr_adjacency_index_high 7246 * Bits 23:16 of the adjacency_index. 7247 * Access: Index 7248 */ 7249 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7250 7251 enum mlxsw_reg_ratr_trap_id { 7252 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7253 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7254 }; 7255 7256 /* reg_ratr_trap_id 7257 * Trap ID to be reported to CPU. 7258 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7259 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7260 * Access: RW 7261 */ 7262 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7263 7264 /* reg_ratr_eth_destination_mac 7265 * MAC address of the destination next-hop. 7266 * Access: RW 7267 */ 7268 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7269 7270 enum mlxsw_reg_ratr_ipip_type { 7271 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7272 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7273 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7274 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7275 }; 7276 7277 /* reg_ratr_ipip_type 7278 * Underlay destination ip type. 7279 * Note: the type field must match the protocol of the router interface. 7280 * Access: RW 7281 */ 7282 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7283 7284 /* reg_ratr_ipip_ipv4_udip 7285 * Underlay ipv4 dip. 7286 * Reserved when ipip_type is IPv6. 7287 * Access: RW 7288 */ 7289 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7290 7291 /* reg_ratr_ipip_ipv6_ptr 7292 * Pointer to IPv6 underlay destination ip address. 7293 * For Spectrum: Pointer to KVD linear space. 7294 * Access: RW 7295 */ 7296 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7297 7298 enum mlxsw_reg_flow_counter_set_type { 7299 /* No count */ 7300 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7301 /* Count packets and bytes */ 7302 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7303 /* Count only packets */ 7304 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7305 }; 7306 7307 /* reg_ratr_counter_set_type 7308 * Counter set type for flow counters 7309 * Access: RW 7310 */ 7311 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7312 7313 /* reg_ratr_counter_index 7314 * Counter index for flow counters 7315 * Access: RW 7316 */ 7317 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7318 7319 static inline void 7320 mlxsw_reg_ratr_pack(char *payload, 7321 enum mlxsw_reg_ratr_op op, bool valid, 7322 enum mlxsw_reg_ratr_type type, 7323 u32 adjacency_index, u16 egress_rif) 7324 { 7325 MLXSW_REG_ZERO(ratr, payload); 7326 mlxsw_reg_ratr_op_set(payload, op); 7327 mlxsw_reg_ratr_v_set(payload, valid); 7328 mlxsw_reg_ratr_type_set(payload, type); 7329 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7330 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7331 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7332 } 7333 7334 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7335 const char *dest_mac) 7336 { 7337 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7338 } 7339 7340 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7341 { 7342 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7343 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7344 } 7345 7346 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7347 { 7348 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7349 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7350 } 7351 7352 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7353 bool counter_enable) 7354 { 7355 enum mlxsw_reg_flow_counter_set_type set_type; 7356 7357 if (counter_enable) 7358 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7359 else 7360 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7361 7362 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7363 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7364 } 7365 7366 /* RDPM - Router DSCP to Priority Mapping 7367 * -------------------------------------- 7368 * Controls the mapping from DSCP field to switch priority on routed packets 7369 */ 7370 #define MLXSW_REG_RDPM_ID 0x8009 7371 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7372 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7373 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7374 #define MLXSW_REG_RDPM_LEN 0x40 7375 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7376 MLXSW_REG_RDPM_LEN - \ 7377 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7378 7379 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7380 7381 /* reg_dscp_entry_e 7382 * Enable update of the specific entry 7383 * Access: Index 7384 */ 7385 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7386 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7387 7388 /* reg_dscp_entry_prio 7389 * Switch Priority 7390 * Access: RW 7391 */ 7392 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7393 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7394 7395 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7396 u8 prio) 7397 { 7398 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7399 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7400 } 7401 7402 /* RICNT - Router Interface Counter Register 7403 * ----------------------------------------- 7404 * The RICNT register retrieves per port performance counters 7405 */ 7406 #define MLXSW_REG_RICNT_ID 0x800B 7407 #define MLXSW_REG_RICNT_LEN 0x100 7408 7409 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7410 7411 /* reg_ricnt_counter_index 7412 * Counter index 7413 * Access: RW 7414 */ 7415 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7416 7417 enum mlxsw_reg_ricnt_counter_set_type { 7418 /* No Count. */ 7419 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7420 /* Basic. Used for router interfaces, counting the following: 7421 * - Error and Discard counters. 7422 * - Unicast, Multicast and Broadcast counters. Sharing the 7423 * same set of counters for the different type of traffic 7424 * (IPv4, IPv6 and mpls). 7425 */ 7426 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7427 }; 7428 7429 /* reg_ricnt_counter_set_type 7430 * Counter Set Type for router interface counter 7431 * Access: RW 7432 */ 7433 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7434 7435 enum mlxsw_reg_ricnt_opcode { 7436 /* Nop. Supported only for read access*/ 7437 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7438 /* Clear. Setting the clr bit will reset the counter value for 7439 * all counters of the specified Router Interface. 7440 */ 7441 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7442 }; 7443 7444 /* reg_ricnt_opcode 7445 * Opcode 7446 * Access: RW 7447 */ 7448 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7449 7450 /* reg_ricnt_good_unicast_packets 7451 * good unicast packets. 7452 * Access: RW 7453 */ 7454 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7455 7456 /* reg_ricnt_good_multicast_packets 7457 * good multicast packets. 7458 * Access: RW 7459 */ 7460 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7461 7462 /* reg_ricnt_good_broadcast_packets 7463 * good broadcast packets 7464 * Access: RW 7465 */ 7466 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7467 7468 /* reg_ricnt_good_unicast_bytes 7469 * A count of L3 data and padding octets not including L2 headers 7470 * for good unicast frames. 7471 * Access: RW 7472 */ 7473 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7474 7475 /* reg_ricnt_good_multicast_bytes 7476 * A count of L3 data and padding octets not including L2 headers 7477 * for good multicast frames. 7478 * Access: RW 7479 */ 7480 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7481 7482 /* reg_ritr_good_broadcast_bytes 7483 * A count of L3 data and padding octets not including L2 headers 7484 * for good broadcast frames. 7485 * Access: RW 7486 */ 7487 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7488 7489 /* reg_ricnt_error_packets 7490 * A count of errored frames that do not pass the router checks. 7491 * Access: RW 7492 */ 7493 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7494 7495 /* reg_ricnt_discrad_packets 7496 * A count of non-errored frames that do not pass the router checks. 7497 * Access: RW 7498 */ 7499 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7500 7501 /* reg_ricnt_error_bytes 7502 * A count of L3 data and padding octets not including L2 headers 7503 * for errored frames. 7504 * Access: RW 7505 */ 7506 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7507 7508 /* reg_ricnt_discard_bytes 7509 * A count of L3 data and padding octets not including L2 headers 7510 * for non-errored frames that do not pass the router checks. 7511 * Access: RW 7512 */ 7513 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7514 7515 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7516 enum mlxsw_reg_ricnt_opcode op) 7517 { 7518 MLXSW_REG_ZERO(ricnt, payload); 7519 mlxsw_reg_ricnt_op_set(payload, op); 7520 mlxsw_reg_ricnt_counter_index_set(payload, index); 7521 mlxsw_reg_ricnt_counter_set_type_set(payload, 7522 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7523 } 7524 7525 /* RRCR - Router Rules Copy Register Layout 7526 * ---------------------------------------- 7527 * This register is used for moving and copying route entry rules. 7528 */ 7529 #define MLXSW_REG_RRCR_ID 0x800F 7530 #define MLXSW_REG_RRCR_LEN 0x24 7531 7532 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7533 7534 enum mlxsw_reg_rrcr_op { 7535 /* Move rules */ 7536 MLXSW_REG_RRCR_OP_MOVE, 7537 /* Copy rules */ 7538 MLXSW_REG_RRCR_OP_COPY, 7539 }; 7540 7541 /* reg_rrcr_op 7542 * Access: WO 7543 */ 7544 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7545 7546 /* reg_rrcr_offset 7547 * Offset within the region from which to copy/move. 7548 * Access: Index 7549 */ 7550 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7551 7552 /* reg_rrcr_size 7553 * The number of rules to copy/move. 7554 * Access: WO 7555 */ 7556 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7557 7558 /* reg_rrcr_table_id 7559 * Identifier of the table on which to perform the operation. Encoding is the 7560 * same as in RTAR.key_type 7561 * Access: Index 7562 */ 7563 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7564 7565 /* reg_rrcr_dest_offset 7566 * Offset within the region to which to copy/move 7567 * Access: Index 7568 */ 7569 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7570 7571 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7572 u16 offset, u16 size, 7573 enum mlxsw_reg_rtar_key_type table_id, 7574 u16 dest_offset) 7575 { 7576 MLXSW_REG_ZERO(rrcr, payload); 7577 mlxsw_reg_rrcr_op_set(payload, op); 7578 mlxsw_reg_rrcr_offset_set(payload, offset); 7579 mlxsw_reg_rrcr_size_set(payload, size); 7580 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7581 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7582 } 7583 7584 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7585 * ------------------------------------------------------- 7586 * RALTA is used to allocate the LPM trees of the SHSPM method. 7587 */ 7588 #define MLXSW_REG_RALTA_ID 0x8010 7589 #define MLXSW_REG_RALTA_LEN 0x04 7590 7591 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7592 7593 /* reg_ralta_op 7594 * opcode (valid for Write, must be 0 on Read) 7595 * 0 - allocate a tree 7596 * 1 - deallocate a tree 7597 * Access: OP 7598 */ 7599 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7600 7601 enum mlxsw_reg_ralxx_protocol { 7602 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7603 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7604 }; 7605 7606 /* reg_ralta_protocol 7607 * Protocol. 7608 * Deallocation opcode: Reserved. 7609 * Access: RW 7610 */ 7611 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7612 7613 /* reg_ralta_tree_id 7614 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7615 * the tree identifier (managed by software). 7616 * Note that tree_id 0 is allocated for a default-route tree. 7617 * Access: Index 7618 */ 7619 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7620 7621 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7622 enum mlxsw_reg_ralxx_protocol protocol, 7623 u8 tree_id) 7624 { 7625 MLXSW_REG_ZERO(ralta, payload); 7626 mlxsw_reg_ralta_op_set(payload, !alloc); 7627 mlxsw_reg_ralta_protocol_set(payload, protocol); 7628 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7629 } 7630 7631 /* RALST - Router Algorithmic LPM Structure Tree Register 7632 * ------------------------------------------------------ 7633 * RALST is used to set and query the structure of an LPM tree. 7634 * The structure of the tree must be sorted as a sorted binary tree, while 7635 * each node is a bin that is tagged as the length of the prefixes the lookup 7636 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7637 * of X bits to match with the destination address. The bin 0 indicates 7638 * the default action, when there is no match of any prefix. 7639 */ 7640 #define MLXSW_REG_RALST_ID 0x8011 7641 #define MLXSW_REG_RALST_LEN 0x104 7642 7643 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7644 7645 /* reg_ralst_root_bin 7646 * The bin number of the root bin. 7647 * 0<root_bin=<(length of IP address) 7648 * For a default-route tree configure 0xff 7649 * Access: RW 7650 */ 7651 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7652 7653 /* reg_ralst_tree_id 7654 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7655 * Access: Index 7656 */ 7657 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7658 7659 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7660 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7661 #define MLXSW_REG_RALST_BIN_COUNT 128 7662 7663 /* reg_ralst_left_child_bin 7664 * Holding the children of the bin according to the stored tree's structure. 7665 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7666 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7667 * Access: RW 7668 */ 7669 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7670 7671 /* reg_ralst_right_child_bin 7672 * Holding the children of the bin according to the stored tree's structure. 7673 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7674 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7675 * Access: RW 7676 */ 7677 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7678 false); 7679 7680 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7681 { 7682 MLXSW_REG_ZERO(ralst, payload); 7683 7684 /* Initialize all bins to have no left or right child */ 7685 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7686 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7687 7688 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7689 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7690 } 7691 7692 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7693 u8 left_child_bin, 7694 u8 right_child_bin) 7695 { 7696 int bin_index = bin_number - 1; 7697 7698 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7699 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7700 right_child_bin); 7701 } 7702 7703 /* RALTB - Router Algorithmic LPM Tree Binding Register 7704 * ---------------------------------------------------- 7705 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7706 */ 7707 #define MLXSW_REG_RALTB_ID 0x8012 7708 #define MLXSW_REG_RALTB_LEN 0x04 7709 7710 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7711 7712 /* reg_raltb_virtual_router 7713 * Virtual Router ID 7714 * Range is 0..cap_max_virtual_routers-1 7715 * Access: Index 7716 */ 7717 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7718 7719 /* reg_raltb_protocol 7720 * Protocol. 7721 * Access: Index 7722 */ 7723 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7724 7725 /* reg_raltb_tree_id 7726 * Tree to be used for the {virtual_router, protocol} 7727 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7728 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7729 * Access: RW 7730 */ 7731 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7732 7733 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7734 enum mlxsw_reg_ralxx_protocol protocol, 7735 u8 tree_id) 7736 { 7737 MLXSW_REG_ZERO(raltb, payload); 7738 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7739 mlxsw_reg_raltb_protocol_set(payload, protocol); 7740 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7741 } 7742 7743 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7744 * ----------------------------------------------------- 7745 * RALUE is used to configure and query LPM entries that serve 7746 * the Unicast protocols. 7747 */ 7748 #define MLXSW_REG_RALUE_ID 0x8013 7749 #define MLXSW_REG_RALUE_LEN 0x38 7750 7751 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7752 7753 /* reg_ralue_protocol 7754 * Protocol. 7755 * Access: Index 7756 */ 7757 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7758 7759 enum mlxsw_reg_ralue_op { 7760 /* Read operation. If entry doesn't exist, the operation fails. */ 7761 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7762 /* Clear on read operation. Used to read entry and 7763 * clear Activity bit. 7764 */ 7765 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7766 /* Write operation. Used to write a new entry to the table. All RW 7767 * fields are written for new entry. Activity bit is set 7768 * for new entries. 7769 */ 7770 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7771 /* Update operation. Used to update an existing route entry and 7772 * only update the RW fields that are detailed in the field 7773 * op_u_mask. If entry doesn't exist, the operation fails. 7774 */ 7775 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7776 /* Clear activity. The Activity bit (the field a) is cleared 7777 * for the entry. 7778 */ 7779 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7780 /* Delete operation. Used to delete an existing entry. If entry 7781 * doesn't exist, the operation fails. 7782 */ 7783 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7784 }; 7785 7786 /* reg_ralue_op 7787 * Operation. 7788 * Access: OP 7789 */ 7790 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7791 7792 /* reg_ralue_a 7793 * Activity. Set for new entries. Set if a packet lookup has hit on the 7794 * specific entry, only if the entry is a route. To clear the a bit, use 7795 * "clear activity" op. 7796 * Enabled by activity_dis in RGCR 7797 * Access: RO 7798 */ 7799 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7800 7801 /* reg_ralue_virtual_router 7802 * Virtual Router ID 7803 * Range is 0..cap_max_virtual_routers-1 7804 * Access: Index 7805 */ 7806 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7807 7808 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7809 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7810 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7811 7812 /* reg_ralue_op_u_mask 7813 * opcode update mask. 7814 * On read operation, this field is reserved. 7815 * This field is valid for update opcode, otherwise - reserved. 7816 * This field is a bitmask of the fields that should be updated. 7817 * Access: WO 7818 */ 7819 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7820 7821 /* reg_ralue_prefix_len 7822 * Number of bits in the prefix of the LPM route. 7823 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7824 * two entries in the physical HW table. 7825 * Access: Index 7826 */ 7827 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7828 7829 /* reg_ralue_dip* 7830 * The prefix of the route or of the marker that the object of the LPM 7831 * is compared with. The most significant bits of the dip are the prefix. 7832 * The least significant bits must be '0' if the prefix_len is smaller 7833 * than 128 for IPv6 or smaller than 32 for IPv4. 7834 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7835 * Access: Index 7836 */ 7837 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7838 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7839 7840 enum mlxsw_reg_ralue_entry_type { 7841 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7842 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7843 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7844 }; 7845 7846 /* reg_ralue_entry_type 7847 * Entry type. 7848 * Note - for Marker entries, the action_type and action fields are reserved. 7849 * Access: RW 7850 */ 7851 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7852 7853 /* reg_ralue_bmp_len 7854 * The best match prefix length in the case that there is no match for 7855 * longer prefixes. 7856 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7857 * Note for any update operation with entry_type modification this 7858 * field must be set. 7859 * Access: RW 7860 */ 7861 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7862 7863 enum mlxsw_reg_ralue_action_type { 7864 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7865 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7866 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7867 }; 7868 7869 /* reg_ralue_action_type 7870 * Action Type 7871 * Indicates how the IP address is connected. 7872 * It can be connected to a local subnet through local_erif or can be 7873 * on a remote subnet connected through a next-hop router, 7874 * or transmitted to the CPU. 7875 * Reserved when entry_type = MARKER_ENTRY 7876 * Access: RW 7877 */ 7878 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7879 7880 enum mlxsw_reg_ralue_trap_action { 7881 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7882 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7883 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7884 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7885 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7886 }; 7887 7888 /* reg_ralue_trap_action 7889 * Trap action. 7890 * For IP2ME action, only NOP and MIRROR are possible. 7891 * Access: RW 7892 */ 7893 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7894 7895 /* reg_ralue_trap_id 7896 * Trap ID to be reported to CPU. 7897 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7898 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7899 * Access: RW 7900 */ 7901 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7902 7903 /* reg_ralue_adjacency_index 7904 * Points to the first entry of the group-based ECMP. 7905 * Only relevant in case of REMOTE action. 7906 * Access: RW 7907 */ 7908 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7909 7910 /* reg_ralue_ecmp_size 7911 * Amount of sequential entries starting 7912 * from the adjacency_index (the number of ECMPs). 7913 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7914 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7915 * Only relevant in case of REMOTE action. 7916 * Access: RW 7917 */ 7918 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7919 7920 /* reg_ralue_local_erif 7921 * Egress Router Interface. 7922 * Only relevant in case of LOCAL action. 7923 * Access: RW 7924 */ 7925 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7926 7927 /* reg_ralue_ip2me_v 7928 * Valid bit for the tunnel_ptr field. 7929 * If valid = 0 then trap to CPU as IP2ME trap ID. 7930 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7931 * decapsulation then tunnel decapsulation is done. 7932 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7933 * decapsulation then trap as IP2ME trap ID. 7934 * Only relevant in case of IP2ME action. 7935 * Access: RW 7936 */ 7937 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7938 7939 /* reg_ralue_ip2me_tunnel_ptr 7940 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7941 * For Spectrum, pointer to KVD Linear. 7942 * Only relevant in case of IP2ME action. 7943 * Access: RW 7944 */ 7945 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7946 7947 static inline void mlxsw_reg_ralue_pack(char *payload, 7948 enum mlxsw_reg_ralxx_protocol protocol, 7949 enum mlxsw_reg_ralue_op op, 7950 u16 virtual_router, u8 prefix_len) 7951 { 7952 MLXSW_REG_ZERO(ralue, payload); 7953 mlxsw_reg_ralue_protocol_set(payload, protocol); 7954 mlxsw_reg_ralue_op_set(payload, op); 7955 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7956 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7957 mlxsw_reg_ralue_entry_type_set(payload, 7958 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7959 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7960 } 7961 7962 static inline void mlxsw_reg_ralue_pack4(char *payload, 7963 enum mlxsw_reg_ralxx_protocol protocol, 7964 enum mlxsw_reg_ralue_op op, 7965 u16 virtual_router, u8 prefix_len, 7966 u32 dip) 7967 { 7968 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7969 mlxsw_reg_ralue_dip4_set(payload, dip); 7970 } 7971 7972 static inline void mlxsw_reg_ralue_pack6(char *payload, 7973 enum mlxsw_reg_ralxx_protocol protocol, 7974 enum mlxsw_reg_ralue_op op, 7975 u16 virtual_router, u8 prefix_len, 7976 const void *dip) 7977 { 7978 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7979 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7980 } 7981 7982 static inline void 7983 mlxsw_reg_ralue_act_remote_pack(char *payload, 7984 enum mlxsw_reg_ralue_trap_action trap_action, 7985 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7986 { 7987 mlxsw_reg_ralue_action_type_set(payload, 7988 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7989 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7990 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7991 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7992 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7993 } 7994 7995 static inline void 7996 mlxsw_reg_ralue_act_local_pack(char *payload, 7997 enum mlxsw_reg_ralue_trap_action trap_action, 7998 u16 trap_id, u16 local_erif) 7999 { 8000 mlxsw_reg_ralue_action_type_set(payload, 8001 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8002 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8003 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8004 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8005 } 8006 8007 static inline void 8008 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8009 { 8010 mlxsw_reg_ralue_action_type_set(payload, 8011 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8012 } 8013 8014 static inline void 8015 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8016 { 8017 mlxsw_reg_ralue_action_type_set(payload, 8018 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8019 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8020 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8021 } 8022 8023 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8024 * ---------------------------------------------------------- 8025 * The RAUHT register is used to configure and query the Unicast Host table in 8026 * devices that implement the Algorithmic LPM. 8027 */ 8028 #define MLXSW_REG_RAUHT_ID 0x8014 8029 #define MLXSW_REG_RAUHT_LEN 0x74 8030 8031 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8032 8033 enum mlxsw_reg_rauht_type { 8034 MLXSW_REG_RAUHT_TYPE_IPV4, 8035 MLXSW_REG_RAUHT_TYPE_IPV6, 8036 }; 8037 8038 /* reg_rauht_type 8039 * Access: Index 8040 */ 8041 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8042 8043 enum mlxsw_reg_rauht_op { 8044 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8045 /* Read operation */ 8046 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8047 /* Clear on read operation. Used to read entry and clear 8048 * activity bit. 8049 */ 8050 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8051 /* Add. Used to write a new entry to the table. All R/W fields are 8052 * relevant for new entry. Activity bit is set for new entries. 8053 */ 8054 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8055 /* Update action. Used to update an existing route entry and 8056 * only update the following fields: 8057 * trap_action, trap_id, mac, counter_set_type, counter_index 8058 */ 8059 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8060 /* Clear activity. A bit is cleared for the entry. */ 8061 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8062 /* Delete entry */ 8063 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8064 /* Delete all host entries on a RIF. In this command, dip 8065 * field is reserved. 8066 */ 8067 }; 8068 8069 /* reg_rauht_op 8070 * Access: OP 8071 */ 8072 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8073 8074 /* reg_rauht_a 8075 * Activity. Set for new entries. Set if a packet lookup has hit on 8076 * the specific entry. 8077 * To clear the a bit, use "clear activity" op. 8078 * Enabled by activity_dis in RGCR 8079 * Access: RO 8080 */ 8081 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8082 8083 /* reg_rauht_rif 8084 * Router Interface 8085 * Access: Index 8086 */ 8087 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8088 8089 /* reg_rauht_dip* 8090 * Destination address. 8091 * Access: Index 8092 */ 8093 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8094 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8095 8096 enum mlxsw_reg_rauht_trap_action { 8097 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8098 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8099 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8100 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8101 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8102 }; 8103 8104 /* reg_rauht_trap_action 8105 * Access: RW 8106 */ 8107 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8108 8109 enum mlxsw_reg_rauht_trap_id { 8110 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8111 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8112 }; 8113 8114 /* reg_rauht_trap_id 8115 * Trap ID to be reported to CPU. 8116 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8117 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8118 * trap_id is reserved. 8119 * Access: RW 8120 */ 8121 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8122 8123 /* reg_rauht_counter_set_type 8124 * Counter set type for flow counters 8125 * Access: RW 8126 */ 8127 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8128 8129 /* reg_rauht_counter_index 8130 * Counter index for flow counters 8131 * Access: RW 8132 */ 8133 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8134 8135 /* reg_rauht_mac 8136 * MAC address. 8137 * Access: RW 8138 */ 8139 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8140 8141 static inline void mlxsw_reg_rauht_pack(char *payload, 8142 enum mlxsw_reg_rauht_op op, u16 rif, 8143 const char *mac) 8144 { 8145 MLXSW_REG_ZERO(rauht, payload); 8146 mlxsw_reg_rauht_op_set(payload, op); 8147 mlxsw_reg_rauht_rif_set(payload, rif); 8148 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8149 } 8150 8151 static inline void mlxsw_reg_rauht_pack4(char *payload, 8152 enum mlxsw_reg_rauht_op op, u16 rif, 8153 const char *mac, u32 dip) 8154 { 8155 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8156 mlxsw_reg_rauht_dip4_set(payload, dip); 8157 } 8158 8159 static inline void mlxsw_reg_rauht_pack6(char *payload, 8160 enum mlxsw_reg_rauht_op op, u16 rif, 8161 const char *mac, const char *dip) 8162 { 8163 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8164 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8165 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8166 } 8167 8168 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8169 u64 counter_index) 8170 { 8171 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8172 mlxsw_reg_rauht_counter_set_type_set(payload, 8173 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8174 } 8175 8176 /* RALEU - Router Algorithmic LPM ECMP Update Register 8177 * --------------------------------------------------- 8178 * The register enables updating the ECMP section in the action for multiple 8179 * LPM Unicast entries in a single operation. The update is executed to 8180 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8181 */ 8182 #define MLXSW_REG_RALEU_ID 0x8015 8183 #define MLXSW_REG_RALEU_LEN 0x28 8184 8185 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8186 8187 /* reg_raleu_protocol 8188 * Protocol. 8189 * Access: Index 8190 */ 8191 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8192 8193 /* reg_raleu_virtual_router 8194 * Virtual Router ID 8195 * Range is 0..cap_max_virtual_routers-1 8196 * Access: Index 8197 */ 8198 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8199 8200 /* reg_raleu_adjacency_index 8201 * Adjacency Index used for matching on the existing entries. 8202 * Access: Index 8203 */ 8204 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8205 8206 /* reg_raleu_ecmp_size 8207 * ECMP Size used for matching on the existing entries. 8208 * Access: Index 8209 */ 8210 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8211 8212 /* reg_raleu_new_adjacency_index 8213 * New Adjacency Index. 8214 * Access: WO 8215 */ 8216 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8217 8218 /* reg_raleu_new_ecmp_size 8219 * New ECMP Size. 8220 * Access: WO 8221 */ 8222 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8223 8224 static inline void mlxsw_reg_raleu_pack(char *payload, 8225 enum mlxsw_reg_ralxx_protocol protocol, 8226 u16 virtual_router, 8227 u32 adjacency_index, u16 ecmp_size, 8228 u32 new_adjacency_index, 8229 u16 new_ecmp_size) 8230 { 8231 MLXSW_REG_ZERO(raleu, payload); 8232 mlxsw_reg_raleu_protocol_set(payload, protocol); 8233 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8234 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8235 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8236 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8237 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8238 } 8239 8240 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8241 * ---------------------------------------------------------------- 8242 * The RAUHTD register allows dumping entries from the Router Unicast Host 8243 * Table. For a given session an entry is dumped no more than one time. The 8244 * first RAUHTD access after reset is a new session. A session ends when the 8245 * num_rec response is smaller than num_rec request or for IPv4 when the 8246 * num_entries is smaller than 4. The clear activity affect the current session 8247 * or the last session if a new session has not started. 8248 */ 8249 #define MLXSW_REG_RAUHTD_ID 0x8018 8250 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8251 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8252 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8253 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8254 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8255 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8256 8257 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8258 8259 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8260 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8261 8262 /* reg_rauhtd_filter_fields 8263 * if a bit is '0' then the relevant field is ignored and dump is done 8264 * regardless of the field value 8265 * Bit0 - filter by activity: entry_a 8266 * Bit3 - filter by entry rip: entry_rif 8267 * Access: Index 8268 */ 8269 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8270 8271 enum mlxsw_reg_rauhtd_op { 8272 MLXSW_REG_RAUHTD_OP_DUMP, 8273 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8274 }; 8275 8276 /* reg_rauhtd_op 8277 * Access: OP 8278 */ 8279 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8280 8281 /* reg_rauhtd_num_rec 8282 * At request: number of records requested 8283 * At response: number of records dumped 8284 * For IPv4, each record has 4 entries at request and up to 4 entries 8285 * at response 8286 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8287 * Access: Index 8288 */ 8289 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8290 8291 /* reg_rauhtd_entry_a 8292 * Dump only if activity has value of entry_a 8293 * Reserved if filter_fields bit0 is '0' 8294 * Access: Index 8295 */ 8296 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8297 8298 enum mlxsw_reg_rauhtd_type { 8299 MLXSW_REG_RAUHTD_TYPE_IPV4, 8300 MLXSW_REG_RAUHTD_TYPE_IPV6, 8301 }; 8302 8303 /* reg_rauhtd_type 8304 * Dump only if record type is: 8305 * 0 - IPv4 8306 * 1 - IPv6 8307 * Access: Index 8308 */ 8309 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8310 8311 /* reg_rauhtd_entry_rif 8312 * Dump only if RIF has value of entry_rif 8313 * Reserved if filter_fields bit3 is '0' 8314 * Access: Index 8315 */ 8316 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8317 8318 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8319 enum mlxsw_reg_rauhtd_type type) 8320 { 8321 MLXSW_REG_ZERO(rauhtd, payload); 8322 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8323 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8324 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8325 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8326 mlxsw_reg_rauhtd_type_set(payload, type); 8327 } 8328 8329 /* reg_rauhtd_ipv4_rec_num_entries 8330 * Number of valid entries in this record: 8331 * 0 - 1 valid entry 8332 * 1 - 2 valid entries 8333 * 2 - 3 valid entries 8334 * 3 - 4 valid entries 8335 * Access: RO 8336 */ 8337 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8338 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8339 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8340 8341 /* reg_rauhtd_rec_type 8342 * Record type. 8343 * 0 - IPv4 8344 * 1 - IPv6 8345 * Access: RO 8346 */ 8347 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8348 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8349 8350 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8351 8352 /* reg_rauhtd_ipv4_ent_a 8353 * Activity. Set for new entries. Set if a packet lookup has hit on the 8354 * specific entry. 8355 * Access: RO 8356 */ 8357 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8358 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8359 8360 /* reg_rauhtd_ipv4_ent_rif 8361 * Router interface. 8362 * Access: RO 8363 */ 8364 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8365 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8366 8367 /* reg_rauhtd_ipv4_ent_dip 8368 * Destination IPv4 address. 8369 * Access: RO 8370 */ 8371 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8372 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8373 8374 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8375 8376 /* reg_rauhtd_ipv6_ent_a 8377 * Activity. Set for new entries. Set if a packet lookup has hit on the 8378 * specific entry. 8379 * Access: RO 8380 */ 8381 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8382 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8383 8384 /* reg_rauhtd_ipv6_ent_rif 8385 * Router interface. 8386 * Access: RO 8387 */ 8388 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8389 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8390 8391 /* reg_rauhtd_ipv6_ent_dip 8392 * Destination IPv6 address. 8393 * Access: RO 8394 */ 8395 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8396 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8397 8398 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8399 int ent_index, u16 *p_rif, 8400 u32 *p_dip) 8401 { 8402 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8403 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8404 } 8405 8406 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8407 int rec_index, u16 *p_rif, 8408 char *p_dip) 8409 { 8410 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8411 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8412 } 8413 8414 /* RTDP - Routing Tunnel Decap Properties Register 8415 * ----------------------------------------------- 8416 * The RTDP register is used for configuring the tunnel decap properties of NVE 8417 * and IPinIP. 8418 */ 8419 #define MLXSW_REG_RTDP_ID 0x8020 8420 #define MLXSW_REG_RTDP_LEN 0x44 8421 8422 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8423 8424 enum mlxsw_reg_rtdp_type { 8425 MLXSW_REG_RTDP_TYPE_NVE, 8426 MLXSW_REG_RTDP_TYPE_IPIP, 8427 }; 8428 8429 /* reg_rtdp_type 8430 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8431 * Access: RW 8432 */ 8433 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8434 8435 /* reg_rtdp_tunnel_index 8436 * Index to the Decap entry. 8437 * For Spectrum, Index to KVD Linear. 8438 * Access: Index 8439 */ 8440 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8441 8442 /* reg_rtdp_egress_router_interface 8443 * Underlay egress router interface. 8444 * Valid range is from 0 to cap_max_router_interfaces - 1 8445 * Access: RW 8446 */ 8447 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8448 8449 /* IPinIP */ 8450 8451 /* reg_rtdp_ipip_irif 8452 * Ingress Router Interface for the overlay router 8453 * Access: RW 8454 */ 8455 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8456 8457 enum mlxsw_reg_rtdp_ipip_sip_check { 8458 /* No sip checks. */ 8459 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8460 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8461 * equal ipv4_usip. 8462 */ 8463 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8464 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8465 * equal ipv6_usip. 8466 */ 8467 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8468 }; 8469 8470 /* reg_rtdp_ipip_sip_check 8471 * SIP check to perform. If decapsulation failed due to these configurations 8472 * then trap_id is IPIP_DECAP_ERROR. 8473 * Access: RW 8474 */ 8475 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8476 8477 /* If set, allow decapsulation of IPinIP (without GRE). */ 8478 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8479 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8480 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8481 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8482 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8483 8484 /* reg_rtdp_ipip_type_check 8485 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8486 * these configurations then trap_id is IPIP_DECAP_ERROR. 8487 * Access: RW 8488 */ 8489 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8490 8491 /* reg_rtdp_ipip_gre_key_check 8492 * Whether GRE key should be checked. When check is enabled: 8493 * - A packet received as IPinIP (without GRE) will always pass. 8494 * - A packet received as IPinGREinIP without a key will not pass the check. 8495 * - A packet received as IPinGREinIP with a key will pass the check only if the 8496 * key in the packet is equal to expected_gre_key. 8497 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8498 * Access: RW 8499 */ 8500 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8501 8502 /* reg_rtdp_ipip_ipv4_usip 8503 * Underlay IPv4 address for ipv4 source address check. 8504 * Reserved when sip_check is not '1'. 8505 * Access: RW 8506 */ 8507 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8508 8509 /* reg_rtdp_ipip_ipv6_usip_ptr 8510 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8511 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8512 * is to the KVD linear. 8513 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8514 * Access: RW 8515 */ 8516 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8517 8518 /* reg_rtdp_ipip_expected_gre_key 8519 * GRE key for checking. 8520 * Reserved when gre_key_check is '0'. 8521 * Access: RW 8522 */ 8523 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8524 8525 static inline void mlxsw_reg_rtdp_pack(char *payload, 8526 enum mlxsw_reg_rtdp_type type, 8527 u32 tunnel_index) 8528 { 8529 MLXSW_REG_ZERO(rtdp, payload); 8530 mlxsw_reg_rtdp_type_set(payload, type); 8531 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8532 } 8533 8534 static inline void 8535 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8536 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8537 unsigned int type_check, bool gre_key_check, 8538 u32 expected_gre_key) 8539 { 8540 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8541 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8542 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8543 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8544 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8545 } 8546 8547 static inline void 8548 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8549 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8550 unsigned int type_check, bool gre_key_check, 8551 u32 ipv4_usip, u32 expected_gre_key) 8552 { 8553 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8554 gre_key_check, expected_gre_key); 8555 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8556 } 8557 8558 static inline void 8559 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8560 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8561 unsigned int type_check, bool gre_key_check, 8562 u32 ipv6_usip_ptr, u32 expected_gre_key) 8563 { 8564 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8565 gre_key_check, expected_gre_key); 8566 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8567 } 8568 8569 /* RIPS - Router IP version Six Register 8570 * ------------------------------------- 8571 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8572 * IPinIP 8573 */ 8574 #define MLXSW_REG_RIPS_ID 0x8021 8575 #define MLXSW_REG_RIPS_LEN 0x14 8576 8577 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8578 8579 /* reg_rips_index 8580 * Index to IPv6 address. 8581 * For Spectrum, the index is to the KVD linear. 8582 * Access: Index 8583 */ 8584 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8585 8586 /* reg_rips_ipv6 8587 * IPv6 address 8588 * Access: RW 8589 */ 8590 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8591 8592 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8593 const struct in6_addr *ipv6) 8594 { 8595 MLXSW_REG_ZERO(rips, payload); 8596 mlxsw_reg_rips_index_set(payload, index); 8597 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8598 } 8599 8600 /* RATRAD - Router Adjacency Table Activity Dump Register 8601 * ------------------------------------------------------ 8602 * The RATRAD register is used to dump and optionally clear activity bits of 8603 * router adjacency table entries. 8604 */ 8605 #define MLXSW_REG_RATRAD_ID 0x8022 8606 #define MLXSW_REG_RATRAD_LEN 0x210 8607 8608 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8609 8610 enum { 8611 /* Read activity */ 8612 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8613 /* Read and clear activity */ 8614 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8615 }; 8616 8617 /* reg_ratrad_op 8618 * Access: Operation 8619 */ 8620 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8621 8622 /* reg_ratrad_ecmp_size 8623 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8624 * ranges: 8625 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8626 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8627 * Access: Index 8628 */ 8629 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8630 8631 /* reg_ratrad_adjacency_index 8632 * Index into the adjacency table. 8633 * Access: Index 8634 */ 8635 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8636 8637 /* reg_ratrad_activity_vector 8638 * Activity bit per adjacency index. 8639 * Bits higher than ecmp_size are reserved. 8640 * Access: RO 8641 */ 8642 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8643 8644 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8645 u16 ecmp_size) 8646 { 8647 MLXSW_REG_ZERO(ratrad, payload); 8648 mlxsw_reg_ratrad_op_set(payload, 8649 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8650 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8651 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8652 } 8653 8654 /* RIGR-V2 - Router Interface Group Register Version 2 8655 * --------------------------------------------------- 8656 * The RIGR_V2 register is used to add, remove and query egress interface list 8657 * of a multicast forwarding entry. 8658 */ 8659 #define MLXSW_REG_RIGR2_ID 0x8023 8660 #define MLXSW_REG_RIGR2_LEN 0xB0 8661 8662 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8663 8664 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8665 8666 /* reg_rigr2_rigr_index 8667 * KVD Linear index. 8668 * Access: Index 8669 */ 8670 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8671 8672 /* reg_rigr2_vnext 8673 * Next RIGR Index is valid. 8674 * Access: RW 8675 */ 8676 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8677 8678 /* reg_rigr2_next_rigr_index 8679 * Next RIGR Index. The index is to the KVD linear. 8680 * Reserved when vnxet = '0'. 8681 * Access: RW 8682 */ 8683 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8684 8685 /* reg_rigr2_vrmid 8686 * RMID Index is valid. 8687 * Access: RW 8688 */ 8689 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8690 8691 /* reg_rigr2_rmid_index 8692 * RMID Index. 8693 * Range 0 .. max_mid - 1 8694 * Reserved when vrmid = '0'. 8695 * The index is to the Port Group Table (PGT) 8696 * Access: RW 8697 */ 8698 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8699 8700 /* reg_rigr2_erif_entry_v 8701 * Egress Router Interface is valid. 8702 * Note that low-entries must be set if high-entries are set. For 8703 * example: if erif_entry[2].v is set then erif_entry[1].v and 8704 * erif_entry[0].v must be set. 8705 * Index can be from 0 to cap_mc_erif_list_entries-1 8706 * Access: RW 8707 */ 8708 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8709 8710 /* reg_rigr2_erif_entry_erif 8711 * Egress Router Interface. 8712 * Valid range is from 0 to cap_max_router_interfaces - 1 8713 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8714 * Access: RW 8715 */ 8716 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8717 8718 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8719 bool vnext, u32 next_rigr_index) 8720 { 8721 MLXSW_REG_ZERO(rigr2, payload); 8722 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8723 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8724 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8725 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8726 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8727 } 8728 8729 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8730 bool v, u16 erif) 8731 { 8732 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8733 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8734 } 8735 8736 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8737 * ------------------------------------------------------ 8738 */ 8739 #define MLXSW_REG_RECR2_ID 0x8025 8740 #define MLXSW_REG_RECR2_LEN 0x38 8741 8742 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8743 8744 /* reg_recr2_pp 8745 * Per-port configuration 8746 * Access: Index 8747 */ 8748 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8749 8750 /* reg_recr2_sh 8751 * Symmetric hash 8752 * Access: RW 8753 */ 8754 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8755 8756 /* reg_recr2_seed 8757 * Seed 8758 * Access: RW 8759 */ 8760 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8761 8762 enum { 8763 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8764 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8765 /* Enable IPv4 fields if packet is TCP or UDP */ 8766 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8767 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8768 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8769 /* Enable IPv6 fields if packet is TCP or UDP */ 8770 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8771 /* Enable TCP/UDP header fields if packet is IPv4 */ 8772 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8773 /* Enable TCP/UDP header fields if packet is IPv6 */ 8774 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8775 8776 __MLXSW_REG_RECR2_HEADER_CNT, 8777 }; 8778 8779 /* reg_recr2_outer_header_enables 8780 * Bit mask where each bit enables a specific layer to be included in 8781 * the hash calculation. 8782 * Access: RW 8783 */ 8784 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8785 8786 enum { 8787 /* IPv4 Source IP */ 8788 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8789 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8790 /* IPv4 Destination IP */ 8791 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8792 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8793 /* IP Protocol */ 8794 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8795 /* IPv6 Source IP */ 8796 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8797 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8798 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8799 /* IPv6 Destination IP */ 8800 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8801 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8802 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8803 /* IPv6 Next Header */ 8804 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8805 /* IPv6 Flow Label */ 8806 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8807 /* TCP/UDP Source Port */ 8808 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8809 /* TCP/UDP Destination Port */ 8810 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8811 8812 __MLXSW_REG_RECR2_FIELD_CNT, 8813 }; 8814 8815 /* reg_recr2_outer_header_fields_enable 8816 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8817 * Access: RW 8818 */ 8819 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8820 8821 /* reg_recr2_inner_header_enables 8822 * Bit mask where each bit enables a specific inner layer to be included in the 8823 * hash calculation. Same values as reg_recr2_outer_header_enables. 8824 * Access: RW 8825 */ 8826 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8827 8828 enum { 8829 /* Inner IPv4 Source IP */ 8830 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8831 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8832 /* Inner IPv4 Destination IP */ 8833 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8834 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8835 /* Inner IP Protocol */ 8836 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8837 /* Inner IPv6 Source IP */ 8838 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8839 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8840 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8841 /* Inner IPv6 Destination IP */ 8842 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8843 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8844 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8845 /* Inner IPv6 Next Header */ 8846 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8847 /* Inner IPv6 Flow Label */ 8848 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8849 /* Inner TCP/UDP Source Port */ 8850 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8851 /* Inner TCP/UDP Destination Port */ 8852 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8853 8854 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8855 }; 8856 8857 /* reg_recr2_inner_header_fields_enable 8858 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8859 * Access: RW 8860 */ 8861 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8862 8863 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8864 { 8865 MLXSW_REG_ZERO(recr2, payload); 8866 mlxsw_reg_recr2_pp_set(payload, false); 8867 mlxsw_reg_recr2_sh_set(payload, true); 8868 mlxsw_reg_recr2_seed_set(payload, seed); 8869 } 8870 8871 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8872 * -------------------------------------------------------------- 8873 * The RMFT_V2 register is used to configure and query the multicast table. 8874 */ 8875 #define MLXSW_REG_RMFT2_ID 0x8027 8876 #define MLXSW_REG_RMFT2_LEN 0x174 8877 8878 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8879 8880 /* reg_rmft2_v 8881 * Valid 8882 * Access: RW 8883 */ 8884 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8885 8886 enum mlxsw_reg_rmft2_type { 8887 MLXSW_REG_RMFT2_TYPE_IPV4, 8888 MLXSW_REG_RMFT2_TYPE_IPV6 8889 }; 8890 8891 /* reg_rmft2_type 8892 * Access: Index 8893 */ 8894 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8895 8896 enum mlxsw_sp_reg_rmft2_op { 8897 /* For Write: 8898 * Write operation. Used to write a new entry to the table. All RW 8899 * fields are relevant for new entry. Activity bit is set for new 8900 * entries - Note write with v (Valid) 0 will delete the entry. 8901 * For Query: 8902 * Read operation 8903 */ 8904 MLXSW_REG_RMFT2_OP_READ_WRITE, 8905 }; 8906 8907 /* reg_rmft2_op 8908 * Operation. 8909 * Access: OP 8910 */ 8911 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8912 8913 /* reg_rmft2_a 8914 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8915 * entry. 8916 * Access: RO 8917 */ 8918 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8919 8920 /* reg_rmft2_offset 8921 * Offset within the multicast forwarding table to write to. 8922 * Access: Index 8923 */ 8924 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8925 8926 /* reg_rmft2_virtual_router 8927 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8928 * Access: RW 8929 */ 8930 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8931 8932 enum mlxsw_reg_rmft2_irif_mask { 8933 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8934 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8935 }; 8936 8937 /* reg_rmft2_irif_mask 8938 * Ingress RIF mask. 8939 * Access: RW 8940 */ 8941 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8942 8943 /* reg_rmft2_irif 8944 * Ingress RIF index. 8945 * Access: RW 8946 */ 8947 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8948 8949 /* reg_rmft2_dip{4,6} 8950 * Destination IPv4/6 address 8951 * Access: RW 8952 */ 8953 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8954 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8955 8956 /* reg_rmft2_dip{4,6}_mask 8957 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8958 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8959 * Access: RW 8960 */ 8961 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8962 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8963 8964 /* reg_rmft2_sip{4,6} 8965 * Source IPv4/6 address 8966 * Access: RW 8967 */ 8968 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8969 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8970 8971 /* reg_rmft2_sip{4,6}_mask 8972 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8973 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8974 * Access: RW 8975 */ 8976 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8977 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8978 8979 /* reg_rmft2_flexible_action_set 8980 * ACL action set. The only supported action types in this field and in any 8981 * action-set pointed from here are as follows: 8982 * 00h: ACTION_NULL 8983 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8984 * 03h: ACTION_TRAP 8985 * 06h: ACTION_QOS 8986 * 08h: ACTION_POLICING_MONITORING 8987 * 10h: ACTION_ROUTER_MC 8988 * Access: RW 8989 */ 8990 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8991 MLXSW_REG_FLEX_ACTION_SET_LEN); 8992 8993 static inline void 8994 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8995 u16 virtual_router, 8996 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8997 const char *flex_action_set) 8998 { 8999 MLXSW_REG_ZERO(rmft2, payload); 9000 mlxsw_reg_rmft2_v_set(payload, v); 9001 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9002 mlxsw_reg_rmft2_offset_set(payload, offset); 9003 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9004 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9005 mlxsw_reg_rmft2_irif_set(payload, irif); 9006 if (flex_action_set) 9007 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9008 flex_action_set); 9009 } 9010 9011 static inline void 9012 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9013 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9014 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9015 const char *flexible_action_set) 9016 { 9017 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9018 irif_mask, irif, flexible_action_set); 9019 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9020 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9021 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9022 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9023 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9024 } 9025 9026 static inline void 9027 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9028 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9029 struct in6_addr dip6, struct in6_addr dip6_mask, 9030 struct in6_addr sip6, struct in6_addr sip6_mask, 9031 const char *flexible_action_set) 9032 { 9033 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9034 irif_mask, irif, flexible_action_set); 9035 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9036 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9037 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9038 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9039 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9040 } 9041 9042 /* REIV - Router Egress Interface to VID Register 9043 * ---------------------------------------------- 9044 * The REIV register maps {eRIF, egress_port} -> VID. 9045 * This mapping is done at the egress, after the ACLs. 9046 * This mapping always takes effect after router, regardless of cast 9047 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9048 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9049 * Reserved when the RIF is a loopback RIF. 9050 * 9051 * Note: Reserved when legacy bridge model is used. 9052 */ 9053 #define MLXSW_REG_REIV_ID 0x8034 9054 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9055 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9056 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9057 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9058 MLXSW_REG_REIV_REC_LEN * \ 9059 MLXSW_REG_REIV_REC_MAX_COUNT) 9060 9061 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9062 9063 /* reg_reiv_port_page 9064 * Port page - elport_record[0] is 256*port_page. 9065 * Access: Index 9066 */ 9067 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9068 9069 /* reg_reiv_erif 9070 * Egress RIF. 9071 * Range is 0..cap_max_router_interfaces-1. 9072 * Access: Index 9073 */ 9074 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9075 9076 /* reg_reiv_rec_update 9077 * Update enable (when write): 9078 * 0 - Do not update the entry. 9079 * 1 - Update the entry. 9080 * Access: OP 9081 */ 9082 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9083 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9084 9085 /* reg_reiv_rec_evid 9086 * Egress VID. 9087 * Range is 0..4095. 9088 * Access: RW 9089 */ 9090 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9091 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9092 9093 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9094 { 9095 MLXSW_REG_ZERO(reiv, payload); 9096 mlxsw_reg_reiv_port_page_set(payload, port_page); 9097 mlxsw_reg_reiv_erif_set(payload, erif); 9098 } 9099 9100 /* MFCR - Management Fan Control Register 9101 * -------------------------------------- 9102 * This register controls the settings of the Fan Speed PWM mechanism. 9103 */ 9104 #define MLXSW_REG_MFCR_ID 0x9001 9105 #define MLXSW_REG_MFCR_LEN 0x08 9106 9107 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9108 9109 enum mlxsw_reg_mfcr_pwm_frequency { 9110 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9111 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9112 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9113 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9114 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9115 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9116 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9117 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9118 }; 9119 9120 /* reg_mfcr_pwm_frequency 9121 * Controls the frequency of the PWM signal. 9122 * Access: RW 9123 */ 9124 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9125 9126 #define MLXSW_MFCR_TACHOS_MAX 10 9127 9128 /* reg_mfcr_tacho_active 9129 * Indicates which of the tachometer is active (bit per tachometer). 9130 * Access: RO 9131 */ 9132 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9133 9134 #define MLXSW_MFCR_PWMS_MAX 5 9135 9136 /* reg_mfcr_pwm_active 9137 * Indicates which of the PWM control is active (bit per PWM). 9138 * Access: RO 9139 */ 9140 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9141 9142 static inline void 9143 mlxsw_reg_mfcr_pack(char *payload, 9144 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9145 { 9146 MLXSW_REG_ZERO(mfcr, payload); 9147 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9148 } 9149 9150 static inline void 9151 mlxsw_reg_mfcr_unpack(char *payload, 9152 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9153 u16 *p_tacho_active, u8 *p_pwm_active) 9154 { 9155 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9156 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9157 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9158 } 9159 9160 /* MFSC - Management Fan Speed Control Register 9161 * -------------------------------------------- 9162 * This register controls the settings of the Fan Speed PWM mechanism. 9163 */ 9164 #define MLXSW_REG_MFSC_ID 0x9002 9165 #define MLXSW_REG_MFSC_LEN 0x08 9166 9167 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9168 9169 /* reg_mfsc_pwm 9170 * Fan pwm to control / monitor. 9171 * Access: Index 9172 */ 9173 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9174 9175 /* reg_mfsc_pwm_duty_cycle 9176 * Controls the duty cycle of the PWM. Value range from 0..255 to 9177 * represent duty cycle of 0%...100%. 9178 * Access: RW 9179 */ 9180 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9181 9182 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9183 u8 pwm_duty_cycle) 9184 { 9185 MLXSW_REG_ZERO(mfsc, payload); 9186 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9187 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9188 } 9189 9190 /* MFSM - Management Fan Speed Measurement 9191 * --------------------------------------- 9192 * This register controls the settings of the Tacho measurements and 9193 * enables reading the Tachometer measurements. 9194 */ 9195 #define MLXSW_REG_MFSM_ID 0x9003 9196 #define MLXSW_REG_MFSM_LEN 0x08 9197 9198 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9199 9200 /* reg_mfsm_tacho 9201 * Fan tachometer index. 9202 * Access: Index 9203 */ 9204 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9205 9206 /* reg_mfsm_rpm 9207 * Fan speed (round per minute). 9208 * Access: RO 9209 */ 9210 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9211 9212 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9213 { 9214 MLXSW_REG_ZERO(mfsm, payload); 9215 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9216 } 9217 9218 /* MFSL - Management Fan Speed Limit Register 9219 * ------------------------------------------ 9220 * The Fan Speed Limit register is used to configure the fan speed 9221 * event / interrupt notification mechanism. Fan speed threshold are 9222 * defined for both under-speed and over-speed. 9223 */ 9224 #define MLXSW_REG_MFSL_ID 0x9004 9225 #define MLXSW_REG_MFSL_LEN 0x0C 9226 9227 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9228 9229 /* reg_mfsl_tacho 9230 * Fan tachometer index. 9231 * Access: Index 9232 */ 9233 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9234 9235 /* reg_mfsl_tach_min 9236 * Tachometer minimum value (minimum RPM). 9237 * Access: RW 9238 */ 9239 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9240 9241 /* reg_mfsl_tach_max 9242 * Tachometer maximum value (maximum RPM). 9243 * Access: RW 9244 */ 9245 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9246 9247 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9248 u16 tach_min, u16 tach_max) 9249 { 9250 MLXSW_REG_ZERO(mfsl, payload); 9251 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9252 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9253 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9254 } 9255 9256 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9257 u16 *p_tach_min, u16 *p_tach_max) 9258 { 9259 if (p_tach_min) 9260 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9261 9262 if (p_tach_max) 9263 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9264 } 9265 9266 /* FORE - Fan Out of Range Event Register 9267 * -------------------------------------- 9268 * This register reports the status of the controlled fans compared to the 9269 * range defined by the MFSL register. 9270 */ 9271 #define MLXSW_REG_FORE_ID 0x9007 9272 #define MLXSW_REG_FORE_LEN 0x0C 9273 9274 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9275 9276 /* fan_under_limit 9277 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9278 * to a single tachometer and indicates the specific tachometer reading is 9279 * below the threshold. 9280 * Access: RO 9281 */ 9282 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9283 9284 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9285 bool *fault) 9286 { 9287 u16 limit; 9288 9289 if (fault) { 9290 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9291 *fault = limit & BIT(tacho); 9292 } 9293 } 9294 9295 /* MTCAP - Management Temperature Capabilities 9296 * ------------------------------------------- 9297 * This register exposes the capabilities of the device and 9298 * system temperature sensing. 9299 */ 9300 #define MLXSW_REG_MTCAP_ID 0x9009 9301 #define MLXSW_REG_MTCAP_LEN 0x08 9302 9303 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9304 9305 /* reg_mtcap_sensor_count 9306 * Number of sensors supported by the device. 9307 * This includes the QSFP module sensors (if exists in the QSFP module). 9308 * Access: RO 9309 */ 9310 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9311 9312 /* MTMP - Management Temperature 9313 * ----------------------------- 9314 * This register controls the settings of the temperature measurements 9315 * and enables reading the temperature measurements. Note that temperature 9316 * is in 0.125 degrees Celsius. 9317 */ 9318 #define MLXSW_REG_MTMP_ID 0x900A 9319 #define MLXSW_REG_MTMP_LEN 0x20 9320 9321 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9322 9323 /* reg_mtmp_slot_index 9324 * Slot index (0: Main board). 9325 * Access: Index 9326 */ 9327 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9328 9329 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9330 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9331 /* reg_mtmp_sensor_index 9332 * Sensors index to access. 9333 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9334 * (module 0 is mapped to sensor_index 64). 9335 * Access: Index 9336 */ 9337 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9338 9339 /* Convert to milli degrees Celsius */ 9340 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9341 ((v_) >= 0) ? ((v_) * 125) : \ 9342 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9343 * 125)); }) 9344 9345 /* reg_mtmp_max_operational_temperature 9346 * The highest temperature in the nominal operational range. Reading is in 9347 * 0.125 Celsius degrees units. 9348 * In case of module this is SFF critical temperature threshold. 9349 * Access: RO 9350 */ 9351 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9352 9353 /* reg_mtmp_temperature 9354 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9355 * degrees units. 9356 * Access: RO 9357 */ 9358 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9359 9360 /* reg_mtmp_mte 9361 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9362 * Access: RW 9363 */ 9364 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9365 9366 /* reg_mtmp_mtr 9367 * Max Temperature Reset - clears the value of the max temperature register. 9368 * Access: WO 9369 */ 9370 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9371 9372 /* reg_mtmp_max_temperature 9373 * The highest measured temperature from the sensor. 9374 * When the bit mte is cleared, the field max_temperature is reserved. 9375 * Access: RO 9376 */ 9377 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9378 9379 /* reg_mtmp_tee 9380 * Temperature Event Enable. 9381 * 0 - Do not generate event 9382 * 1 - Generate event 9383 * 2 - Generate single event 9384 * Access: RW 9385 */ 9386 9387 enum mlxsw_reg_mtmp_tee { 9388 MLXSW_REG_MTMP_TEE_NO_EVENT, 9389 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9390 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9391 }; 9392 9393 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9394 9395 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9396 9397 /* reg_mtmp_temperature_threshold_hi 9398 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9399 * Access: RW 9400 */ 9401 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9402 9403 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9404 /* reg_mtmp_temperature_threshold_lo 9405 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9406 * Access: RW 9407 */ 9408 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9409 9410 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9411 9412 /* reg_mtmp_sensor_name 9413 * Sensor Name 9414 * Access: RO 9415 */ 9416 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9417 9418 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9419 u16 sensor_index, bool max_temp_enable, 9420 bool max_temp_reset) 9421 { 9422 MLXSW_REG_ZERO(mtmp, payload); 9423 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9424 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9425 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9426 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9427 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9428 MLXSW_REG_MTMP_THRESH_HI); 9429 } 9430 9431 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9432 int *p_max_temp, int *p_temp_hi, 9433 int *p_max_oper_temp, 9434 char *sensor_name) 9435 { 9436 s16 temp; 9437 9438 if (p_temp) { 9439 temp = mlxsw_reg_mtmp_temperature_get(payload); 9440 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9441 } 9442 if (p_max_temp) { 9443 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9444 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9445 } 9446 if (p_temp_hi) { 9447 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9448 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9449 } 9450 if (p_max_oper_temp) { 9451 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9452 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9453 } 9454 if (sensor_name) 9455 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9456 } 9457 9458 /* MTWE - Management Temperature Warning Event 9459 * ------------------------------------------- 9460 * This register is used for over temperature warning. 9461 */ 9462 #define MLXSW_REG_MTWE_ID 0x900B 9463 #define MLXSW_REG_MTWE_LEN 0x10 9464 9465 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9466 9467 /* reg_mtwe_sensor_warning 9468 * Bit vector indicating which of the sensor reading is above threshold. 9469 * Address 00h bit31 is sensor_warning[127]. 9470 * Address 0Ch bit0 is sensor_warning[0]. 9471 * Access: RO 9472 */ 9473 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9474 9475 /* MTBR - Management Temperature Bulk Register 9476 * ------------------------------------------- 9477 * This register is used for bulk temperature reading. 9478 */ 9479 #define MLXSW_REG_MTBR_ID 0x900F 9480 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9481 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9482 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9483 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9484 MLXSW_REG_MTBR_REC_LEN * \ 9485 MLXSW_REG_MTBR_REC_MAX_COUNT) 9486 9487 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9488 9489 /* reg_mtbr_slot_index 9490 * Slot index (0: Main board). 9491 * Access: Index 9492 */ 9493 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9494 9495 /* reg_mtbr_base_sensor_index 9496 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9497 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9498 * Access: Index 9499 */ 9500 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9501 9502 /* reg_mtbr_num_rec 9503 * Request: Number of records to read 9504 * Response: Number of records read 9505 * See above description for more details. 9506 * Range 1..255 9507 * Access: RW 9508 */ 9509 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9510 9511 /* reg_mtbr_rec_max_temp 9512 * The highest measured temperature from the sensor. 9513 * When the bit mte is cleared, the field max_temperature is reserved. 9514 * Access: RO 9515 */ 9516 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9517 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9518 9519 /* reg_mtbr_rec_temp 9520 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9521 * degrees units. 9522 * Access: RO 9523 */ 9524 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9525 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9526 9527 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9528 u16 base_sensor_index, u8 num_rec) 9529 { 9530 MLXSW_REG_ZERO(mtbr, payload); 9531 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9532 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9533 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9534 } 9535 9536 /* Error codes from temperatute reading */ 9537 enum mlxsw_reg_mtbr_temp_status { 9538 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9539 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9540 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9541 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9542 }; 9543 9544 /* Base index for reading modules temperature */ 9545 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9546 9547 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9548 u16 *p_temp, u16 *p_max_temp) 9549 { 9550 if (p_temp) 9551 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9552 if (p_max_temp) 9553 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9554 } 9555 9556 /* MCIA - Management Cable Info Access 9557 * ----------------------------------- 9558 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9559 */ 9560 9561 #define MLXSW_REG_MCIA_ID 0x9014 9562 #define MLXSW_REG_MCIA_LEN 0x40 9563 9564 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9565 9566 /* reg_mcia_l 9567 * Lock bit. Setting this bit will lock the access to the specific 9568 * cable. Used for updating a full page in a cable EPROM. Any access 9569 * other then subsequence writes will fail while the port is locked. 9570 * Access: RW 9571 */ 9572 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9573 9574 /* reg_mcia_module 9575 * Module number. 9576 * Access: Index 9577 */ 9578 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9579 9580 /* reg_mcia_slot_index 9581 * Slot index (0: Main board) 9582 * Access: Index 9583 */ 9584 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9585 9586 enum { 9587 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9588 /* No response from module's EEPROM. */ 9589 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9590 /* Module type not supported by the device. */ 9591 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9592 /* No module present indication. */ 9593 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9594 /* Error occurred while trying to access module's EEPROM using I2C. */ 9595 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9596 /* Module is disabled. */ 9597 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9598 }; 9599 9600 /* reg_mcia_status 9601 * Module status. 9602 * Access: RO 9603 */ 9604 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9605 9606 /* reg_mcia_i2c_device_address 9607 * I2C device address. 9608 * Access: RW 9609 */ 9610 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9611 9612 /* reg_mcia_page_number 9613 * Page number. 9614 * Access: RW 9615 */ 9616 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9617 9618 /* reg_mcia_device_address 9619 * Device address. 9620 * Access: RW 9621 */ 9622 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9623 9624 /* reg_mcia_bank_number 9625 * Bank number. 9626 * Access: Index 9627 */ 9628 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9629 9630 /* reg_mcia_size 9631 * Number of bytes to read/write (up to 48 bytes). 9632 * Access: RW 9633 */ 9634 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9635 9636 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9637 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9638 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9639 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9640 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9641 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9642 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9643 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9644 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9645 #define MLXSW_REG_MCIA_PAGE0_LO 0 9646 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9647 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9648 9649 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9650 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9651 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9652 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9653 }; 9654 9655 enum mlxsw_reg_mcia_eeprom_module_info_id { 9656 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9657 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9658 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9659 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9660 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9661 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9662 }; 9663 9664 enum mlxsw_reg_mcia_eeprom_module_info { 9665 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9666 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9667 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9668 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9669 }; 9670 9671 /* reg_mcia_eeprom 9672 * Bytes to read/write. 9673 * Access: RW 9674 */ 9675 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9676 9677 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9678 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9679 * on offset 384 through 511, page 3 - on offset 512 through 639. 9680 */ 9681 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9682 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9683 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9684 9685 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9686 u8 lock, u8 page_number, 9687 u16 device_addr, u8 size, 9688 u8 i2c_device_addr) 9689 { 9690 MLXSW_REG_ZERO(mcia, payload); 9691 mlxsw_reg_mcia_slot_set(payload, slot_index); 9692 mlxsw_reg_mcia_module_set(payload, module); 9693 mlxsw_reg_mcia_l_set(payload, lock); 9694 mlxsw_reg_mcia_page_number_set(payload, page_number); 9695 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9696 mlxsw_reg_mcia_size_set(payload, size); 9697 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9698 } 9699 9700 /* MPAT - Monitoring Port Analyzer Table 9701 * ------------------------------------- 9702 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9703 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9704 */ 9705 #define MLXSW_REG_MPAT_ID 0x901A 9706 #define MLXSW_REG_MPAT_LEN 0x78 9707 9708 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9709 9710 /* reg_mpat_pa_id 9711 * Port Analyzer ID. 9712 * Access: Index 9713 */ 9714 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9715 9716 /* reg_mpat_session_id 9717 * Mirror Session ID. 9718 * Used for MIRROR_SESSION<i> trap. 9719 * Access: RW 9720 */ 9721 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9722 9723 /* reg_mpat_system_port 9724 * A unique port identifier for the final destination of the packet. 9725 * Access: RW 9726 */ 9727 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9728 9729 /* reg_mpat_e 9730 * Enable. Indicating the Port Analyzer is enabled. 9731 * Access: RW 9732 */ 9733 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9734 9735 /* reg_mpat_qos 9736 * Quality Of Service Mode. 9737 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9738 * PCP, DEI, DSCP or VL) are configured. 9739 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9740 * same as in the original packet that has triggered the mirroring. For 9741 * SPAN also the pcp,dei are maintained. 9742 * Access: RW 9743 */ 9744 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9745 9746 /* reg_mpat_be 9747 * Best effort mode. Indicates mirroring traffic should not cause packet 9748 * drop or back pressure, but will discard the mirrored packets. Mirrored 9749 * packets will be forwarded on a best effort manner. 9750 * 0: Do not discard mirrored packets 9751 * 1: Discard mirrored packets if causing congestion 9752 * Access: RW 9753 */ 9754 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9755 9756 enum mlxsw_reg_mpat_span_type { 9757 /* Local SPAN Ethernet. 9758 * The original packet is not encapsulated. 9759 */ 9760 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9761 9762 /* Remote SPAN Ethernet VLAN. 9763 * The packet is forwarded to the monitoring port on the monitoring 9764 * VLAN. 9765 */ 9766 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9767 9768 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9769 * The packet is encapsulated with GRE header. 9770 */ 9771 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9772 }; 9773 9774 /* reg_mpat_span_type 9775 * SPAN type. 9776 * Access: RW 9777 */ 9778 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9779 9780 /* reg_mpat_pide 9781 * Policer enable. 9782 * Access: RW 9783 */ 9784 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9785 9786 /* reg_mpat_pid 9787 * Policer ID. 9788 * Access: RW 9789 */ 9790 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9791 9792 /* Remote SPAN - Ethernet VLAN 9793 * - - - - - - - - - - - - - - 9794 */ 9795 9796 /* reg_mpat_eth_rspan_vid 9797 * Encapsulation header VLAN ID. 9798 * Access: RW 9799 */ 9800 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9801 9802 /* Encapsulated Remote SPAN - Ethernet L2 9803 * - - - - - - - - - - - - - - - - - - - 9804 */ 9805 9806 enum mlxsw_reg_mpat_eth_rspan_version { 9807 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9808 }; 9809 9810 /* reg_mpat_eth_rspan_version 9811 * RSPAN mirror header version. 9812 * Access: RW 9813 */ 9814 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9815 9816 /* reg_mpat_eth_rspan_mac 9817 * Destination MAC address. 9818 * Access: RW 9819 */ 9820 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9821 9822 /* reg_mpat_eth_rspan_tp 9823 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9824 * Access: RW 9825 */ 9826 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9827 9828 /* Encapsulated Remote SPAN - Ethernet L3 9829 * - - - - - - - - - - - - - - - - - - - 9830 */ 9831 9832 enum mlxsw_reg_mpat_eth_rspan_protocol { 9833 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9834 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9835 }; 9836 9837 /* reg_mpat_eth_rspan_protocol 9838 * SPAN encapsulation protocol. 9839 * Access: RW 9840 */ 9841 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9842 9843 /* reg_mpat_eth_rspan_ttl 9844 * Encapsulation header Time-to-Live/HopLimit. 9845 * Access: RW 9846 */ 9847 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9848 9849 /* reg_mpat_eth_rspan_smac 9850 * Source MAC address 9851 * Access: RW 9852 */ 9853 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9854 9855 /* reg_mpat_eth_rspan_dip* 9856 * Destination IP address. The IP version is configured by protocol. 9857 * Access: RW 9858 */ 9859 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9860 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9861 9862 /* reg_mpat_eth_rspan_sip* 9863 * Source IP address. The IP version is configured by protocol. 9864 * Access: RW 9865 */ 9866 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9867 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9868 9869 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9870 u16 system_port, bool e, 9871 enum mlxsw_reg_mpat_span_type span_type) 9872 { 9873 MLXSW_REG_ZERO(mpat, payload); 9874 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9875 mlxsw_reg_mpat_system_port_set(payload, system_port); 9876 mlxsw_reg_mpat_e_set(payload, e); 9877 mlxsw_reg_mpat_qos_set(payload, 1); 9878 mlxsw_reg_mpat_be_set(payload, 1); 9879 mlxsw_reg_mpat_span_type_set(payload, span_type); 9880 } 9881 9882 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9883 { 9884 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9885 } 9886 9887 static inline void 9888 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9889 enum mlxsw_reg_mpat_eth_rspan_version version, 9890 const char *mac, 9891 bool tp) 9892 { 9893 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9894 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9895 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9896 } 9897 9898 static inline void 9899 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9900 const char *smac, 9901 u32 sip, u32 dip) 9902 { 9903 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9904 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9905 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9906 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9907 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9908 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9909 } 9910 9911 static inline void 9912 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9913 const char *smac, 9914 struct in6_addr sip, struct in6_addr dip) 9915 { 9916 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9917 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9918 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9919 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9920 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9921 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9922 } 9923 9924 /* MPAR - Monitoring Port Analyzer Register 9925 * ---------------------------------------- 9926 * MPAR register is used to query and configure the port analyzer port mirroring 9927 * properties. 9928 */ 9929 #define MLXSW_REG_MPAR_ID 0x901B 9930 #define MLXSW_REG_MPAR_LEN 0x0C 9931 9932 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9933 9934 /* reg_mpar_local_port 9935 * The local port to mirror the packets from. 9936 * Access: Index 9937 */ 9938 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 9939 9940 enum mlxsw_reg_mpar_i_e { 9941 MLXSW_REG_MPAR_TYPE_EGRESS, 9942 MLXSW_REG_MPAR_TYPE_INGRESS, 9943 }; 9944 9945 /* reg_mpar_i_e 9946 * Ingress/Egress 9947 * Access: Index 9948 */ 9949 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9950 9951 /* reg_mpar_enable 9952 * Enable mirroring 9953 * By default, port mirroring is disabled for all ports. 9954 * Access: RW 9955 */ 9956 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9957 9958 /* reg_mpar_pa_id 9959 * Port Analyzer ID. 9960 * Access: RW 9961 */ 9962 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9963 9964 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 9965 9966 /* reg_mpar_probability_rate 9967 * Sampling rate. 9968 * Valid values are: 1 to 3.5*10^9 9969 * Value of 1 means "sample all". Default is 1. 9970 * Reserved when Spectrum-1. 9971 * Access: RW 9972 */ 9973 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 9974 9975 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 9976 enum mlxsw_reg_mpar_i_e i_e, 9977 bool enable, u8 pa_id, 9978 u32 probability_rate) 9979 { 9980 MLXSW_REG_ZERO(mpar, payload); 9981 mlxsw_reg_mpar_local_port_set(payload, local_port); 9982 mlxsw_reg_mpar_enable_set(payload, enable); 9983 mlxsw_reg_mpar_i_e_set(payload, i_e); 9984 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9985 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 9986 } 9987 9988 /* MGIR - Management General Information Register 9989 * ---------------------------------------------- 9990 * MGIR register allows software to query the hardware and firmware general 9991 * information. 9992 */ 9993 #define MLXSW_REG_MGIR_ID 0x9020 9994 #define MLXSW_REG_MGIR_LEN 0x9C 9995 9996 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9997 9998 /* reg_mgir_hw_info_device_hw_revision 9999 * Access: RO 10000 */ 10001 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10002 10003 /* reg_mgir_fw_info_latency_tlv 10004 * When set, latency-TLV is supported. 10005 * Access: RO 10006 */ 10007 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1); 10008 10009 /* reg_mgir_fw_info_string_tlv 10010 * When set, string-TLV is supported. 10011 * Access: RO 10012 */ 10013 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1); 10014 10015 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10016 10017 /* reg_mgir_fw_info_psid 10018 * PSID (ASCII string). 10019 * Access: RO 10020 */ 10021 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10022 10023 /* reg_mgir_fw_info_extended_major 10024 * Access: RO 10025 */ 10026 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10027 10028 /* reg_mgir_fw_info_extended_minor 10029 * Access: RO 10030 */ 10031 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10032 10033 /* reg_mgir_fw_info_extended_sub_minor 10034 * Access: RO 10035 */ 10036 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10037 10038 static inline void mlxsw_reg_mgir_pack(char *payload) 10039 { 10040 MLXSW_REG_ZERO(mgir, payload); 10041 } 10042 10043 static inline void 10044 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10045 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10046 { 10047 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10048 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10049 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10050 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10051 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10052 } 10053 10054 /* MRSR - Management Reset and Shutdown Register 10055 * --------------------------------------------- 10056 * MRSR register is used to reset or shutdown the switch or 10057 * the entire system (when applicable). 10058 */ 10059 #define MLXSW_REG_MRSR_ID 0x9023 10060 #define MLXSW_REG_MRSR_LEN 0x08 10061 10062 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10063 10064 /* reg_mrsr_command 10065 * Reset/shutdown command 10066 * 0 - do nothing 10067 * 1 - software reset 10068 * Access: WO 10069 */ 10070 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10071 10072 static inline void mlxsw_reg_mrsr_pack(char *payload) 10073 { 10074 MLXSW_REG_ZERO(mrsr, payload); 10075 mlxsw_reg_mrsr_command_set(payload, 1); 10076 } 10077 10078 /* MLCR - Management LED Control Register 10079 * -------------------------------------- 10080 * Controls the system LEDs. 10081 */ 10082 #define MLXSW_REG_MLCR_ID 0x902B 10083 #define MLXSW_REG_MLCR_LEN 0x0C 10084 10085 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10086 10087 /* reg_mlcr_local_port 10088 * Local port number. 10089 * Access: RW 10090 */ 10091 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10092 10093 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10094 10095 /* reg_mlcr_beacon_duration 10096 * Duration of the beacon to be active, in seconds. 10097 * 0x0 - Will turn off the beacon. 10098 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10099 * Access: RW 10100 */ 10101 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10102 10103 /* reg_mlcr_beacon_remain 10104 * Remaining duration of the beacon, in seconds. 10105 * 0xFFFF indicates an infinite amount of time. 10106 * Access: RO 10107 */ 10108 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10109 10110 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10111 bool active) 10112 { 10113 MLXSW_REG_ZERO(mlcr, payload); 10114 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10115 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10116 MLXSW_REG_MLCR_DURATION_MAX : 0); 10117 } 10118 10119 /* MCION - Management Cable IO and Notifications Register 10120 * ------------------------------------------------------ 10121 * The MCION register is used to query transceiver modules' IO pins and other 10122 * notifications. 10123 */ 10124 #define MLXSW_REG_MCION_ID 0x9052 10125 #define MLXSW_REG_MCION_LEN 0x18 10126 10127 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10128 10129 /* reg_mcion_module 10130 * Module number. 10131 * Access: Index 10132 */ 10133 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10134 10135 /* reg_mcion_slot_index 10136 * Slot index. 10137 * Access: Index 10138 */ 10139 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10140 10141 enum { 10142 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10143 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10144 }; 10145 10146 /* reg_mcion_module_status_bits 10147 * Module IO status as defined by SFF. 10148 * Access: RO 10149 */ 10150 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10151 10152 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10153 { 10154 MLXSW_REG_ZERO(mcion, payload); 10155 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10156 mlxsw_reg_mcion_module_set(payload, module); 10157 } 10158 10159 /* MTPPS - Management Pulse Per Second Register 10160 * -------------------------------------------- 10161 * This register provides the device PPS capabilities, configure the PPS in and 10162 * out modules and holds the PPS in time stamp. 10163 */ 10164 #define MLXSW_REG_MTPPS_ID 0x9053 10165 #define MLXSW_REG_MTPPS_LEN 0x3C 10166 10167 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10168 10169 /* reg_mtpps_enable 10170 * Enables the PPS functionality the specific pin. 10171 * A boolean variable. 10172 * Access: RW 10173 */ 10174 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10175 10176 enum mlxsw_reg_mtpps_pin_mode { 10177 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10178 }; 10179 10180 /* reg_mtpps_pin_mode 10181 * Pin mode to be used. The mode must comply with the supported modes of the 10182 * requested pin. 10183 * Access: RW 10184 */ 10185 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10186 10187 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10188 10189 /* reg_mtpps_pin 10190 * Pin to be configured or queried out of the supported pins. 10191 * Access: Index 10192 */ 10193 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10194 10195 /* reg_mtpps_time_stamp 10196 * When pin_mode = pps_in, the latched device time when it was triggered from 10197 * the external GPIO pin. 10198 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10199 * time to generate next output signal. 10200 * Time is in units of device clock. 10201 * Access: RW 10202 */ 10203 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10204 10205 static inline void 10206 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10207 { 10208 MLXSW_REG_ZERO(mtpps, payload); 10209 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10210 mlxsw_reg_mtpps_pin_mode_set(payload, 10211 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10212 mlxsw_reg_mtpps_enable_set(payload, true); 10213 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10214 } 10215 10216 /* MTUTC - Management UTC Register 10217 * ------------------------------- 10218 * Configures the HW UTC counter. 10219 */ 10220 #define MLXSW_REG_MTUTC_ID 0x9055 10221 #define MLXSW_REG_MTUTC_LEN 0x1C 10222 10223 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10224 10225 enum mlxsw_reg_mtutc_operation { 10226 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10227 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10228 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10229 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10230 }; 10231 10232 /* reg_mtutc_operation 10233 * Operation. 10234 * Access: OP 10235 */ 10236 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10237 10238 /* reg_mtutc_freq_adjustment 10239 * Frequency adjustment: Every PPS the HW frequency will be 10240 * adjusted by this value. Units of HW clock, where HW counts 10241 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10242 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10243 * frequency. 10244 * Access: RW 10245 */ 10246 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10247 10248 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10249 10250 /* reg_mtutc_utc_sec 10251 * UTC seconds. 10252 * Access: WO 10253 */ 10254 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10255 10256 /* reg_mtutc_utc_nsec 10257 * UTC nSecs. 10258 * Range 0..(10^9-1) 10259 * Updated when operation is SET_TIME_IMMEDIATE. 10260 * Reserved on Spectrum-1. 10261 * Access: WO 10262 */ 10263 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10264 10265 /* reg_mtutc_time_adjustment 10266 * Time adjustment. 10267 * Units of nSec. 10268 * Range is from -32768 to +32767. 10269 * Updated when operation is ADJUST_TIME. 10270 * Reserved on Spectrum-1. 10271 * Access: WO 10272 */ 10273 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10274 10275 static inline void 10276 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10277 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10278 { 10279 MLXSW_REG_ZERO(mtutc, payload); 10280 mlxsw_reg_mtutc_operation_set(payload, oper); 10281 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10282 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10283 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10284 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10285 } 10286 10287 /* MCQI - Management Component Query Information 10288 * --------------------------------------------- 10289 * This register allows querying information about firmware components. 10290 */ 10291 #define MLXSW_REG_MCQI_ID 0x9061 10292 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10293 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10294 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10295 10296 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10297 10298 /* reg_mcqi_component_index 10299 * Index of the accessed component. 10300 * Access: Index 10301 */ 10302 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10303 10304 enum mlxfw_reg_mcqi_info_type { 10305 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10306 }; 10307 10308 /* reg_mcqi_info_type 10309 * Component properties set. 10310 * Access: RW 10311 */ 10312 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10313 10314 /* reg_mcqi_offset 10315 * The requested/returned data offset from the section start, given in bytes. 10316 * Must be DWORD aligned. 10317 * Access: RW 10318 */ 10319 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10320 10321 /* reg_mcqi_data_size 10322 * The requested/returned data size, given in bytes. If data_size is not DWORD 10323 * aligned, the last bytes are zero padded. 10324 * Access: RW 10325 */ 10326 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10327 10328 /* reg_mcqi_cap_max_component_size 10329 * Maximum size for this component, given in bytes. 10330 * Access: RO 10331 */ 10332 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10333 10334 /* reg_mcqi_cap_log_mcda_word_size 10335 * Log 2 of the access word size in bytes. Read and write access must be aligned 10336 * to the word size. Write access must be done for an integer number of words. 10337 * Access: RO 10338 */ 10339 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10340 10341 /* reg_mcqi_cap_mcda_max_write_size 10342 * Maximal write size for MCDA register 10343 * Access: RO 10344 */ 10345 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10346 10347 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10348 { 10349 MLXSW_REG_ZERO(mcqi, payload); 10350 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10351 mlxsw_reg_mcqi_info_type_set(payload, 10352 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10353 mlxsw_reg_mcqi_offset_set(payload, 0); 10354 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10355 } 10356 10357 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10358 u32 *p_cap_max_component_size, 10359 u8 *p_cap_log_mcda_word_size, 10360 u16 *p_cap_mcda_max_write_size) 10361 { 10362 *p_cap_max_component_size = 10363 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10364 *p_cap_log_mcda_word_size = 10365 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10366 *p_cap_mcda_max_write_size = 10367 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10368 } 10369 10370 /* MCC - Management Component Control 10371 * ---------------------------------- 10372 * Controls the firmware component and updates the FSM. 10373 */ 10374 #define MLXSW_REG_MCC_ID 0x9062 10375 #define MLXSW_REG_MCC_LEN 0x1C 10376 10377 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10378 10379 enum mlxsw_reg_mcc_instruction { 10380 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10381 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10382 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10383 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10384 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10385 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10386 }; 10387 10388 /* reg_mcc_instruction 10389 * Command to be executed by the FSM. 10390 * Applicable for write operation only. 10391 * Access: RW 10392 */ 10393 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10394 10395 /* reg_mcc_component_index 10396 * Index of the accessed component. Applicable only for commands that 10397 * refer to components. Otherwise, this field is reserved. 10398 * Access: Index 10399 */ 10400 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10401 10402 /* reg_mcc_update_handle 10403 * Token representing the current flow executed by the FSM. 10404 * Access: WO 10405 */ 10406 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10407 10408 /* reg_mcc_error_code 10409 * Indicates the successful completion of the instruction, or the reason it 10410 * failed 10411 * Access: RO 10412 */ 10413 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10414 10415 /* reg_mcc_control_state 10416 * Current FSM state 10417 * Access: RO 10418 */ 10419 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10420 10421 /* reg_mcc_component_size 10422 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10423 * the size may shorten the update time. Value 0x0 means that size is 10424 * unspecified. 10425 * Access: WO 10426 */ 10427 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10428 10429 static inline void mlxsw_reg_mcc_pack(char *payload, 10430 enum mlxsw_reg_mcc_instruction instr, 10431 u16 component_index, u32 update_handle, 10432 u32 component_size) 10433 { 10434 MLXSW_REG_ZERO(mcc, payload); 10435 mlxsw_reg_mcc_instruction_set(payload, instr); 10436 mlxsw_reg_mcc_component_index_set(payload, component_index); 10437 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10438 mlxsw_reg_mcc_component_size_set(payload, component_size); 10439 } 10440 10441 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10442 u8 *p_error_code, u8 *p_control_state) 10443 { 10444 if (p_update_handle) 10445 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10446 if (p_error_code) 10447 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10448 if (p_control_state) 10449 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10450 } 10451 10452 /* MCDA - Management Component Data Access 10453 * --------------------------------------- 10454 * This register allows reading and writing a firmware component. 10455 */ 10456 #define MLXSW_REG_MCDA_ID 0x9063 10457 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10458 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10459 #define MLXSW_REG_MCDA_LEN \ 10460 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10461 10462 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10463 10464 /* reg_mcda_update_handle 10465 * Token representing the current flow executed by the FSM. 10466 * Access: RW 10467 */ 10468 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10469 10470 /* reg_mcda_offset 10471 * Offset of accessed address relative to component start. Accesses must be in 10472 * accordance to log_mcda_word_size in MCQI reg. 10473 * Access: RW 10474 */ 10475 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10476 10477 /* reg_mcda_size 10478 * Size of the data accessed, given in bytes. 10479 * Access: RW 10480 */ 10481 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10482 10483 /* reg_mcda_data 10484 * Data block accessed. 10485 * Access: RW 10486 */ 10487 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10488 10489 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10490 u32 offset, u16 size, u8 *data) 10491 { 10492 int i; 10493 10494 MLXSW_REG_ZERO(mcda, payload); 10495 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10496 mlxsw_reg_mcda_offset_set(payload, offset); 10497 mlxsw_reg_mcda_size_set(payload, size); 10498 10499 for (i = 0; i < size / 4; i++) 10500 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10501 } 10502 10503 /* MPSC - Monitoring Packet Sampling Configuration Register 10504 * -------------------------------------------------------- 10505 * MPSC Register is used to configure the Packet Sampling mechanism. 10506 */ 10507 #define MLXSW_REG_MPSC_ID 0x9080 10508 #define MLXSW_REG_MPSC_LEN 0x1C 10509 10510 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10511 10512 /* reg_mpsc_local_port 10513 * Local port number 10514 * Not supported for CPU port 10515 * Access: Index 10516 */ 10517 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10518 10519 /* reg_mpsc_e 10520 * Enable sampling on port local_port 10521 * Access: RW 10522 */ 10523 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10524 10525 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10526 10527 /* reg_mpsc_rate 10528 * Sampling rate = 1 out of rate packets (with randomization around 10529 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10530 * Access: RW 10531 */ 10532 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10533 10534 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10535 u32 rate) 10536 { 10537 MLXSW_REG_ZERO(mpsc, payload); 10538 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10539 mlxsw_reg_mpsc_e_set(payload, e); 10540 mlxsw_reg_mpsc_rate_set(payload, rate); 10541 } 10542 10543 /* MGPC - Monitoring General Purpose Counter Set Register 10544 * The MGPC register retrieves and sets the General Purpose Counter Set. 10545 */ 10546 #define MLXSW_REG_MGPC_ID 0x9081 10547 #define MLXSW_REG_MGPC_LEN 0x18 10548 10549 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10550 10551 /* reg_mgpc_counter_set_type 10552 * Counter set type. 10553 * Access: OP 10554 */ 10555 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10556 10557 /* reg_mgpc_counter_index 10558 * Counter index. 10559 * Access: Index 10560 */ 10561 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10562 10563 enum mlxsw_reg_mgpc_opcode { 10564 /* Nop */ 10565 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10566 /* Clear counters */ 10567 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10568 }; 10569 10570 /* reg_mgpc_opcode 10571 * Opcode. 10572 * Access: OP 10573 */ 10574 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10575 10576 /* reg_mgpc_byte_counter 10577 * Byte counter value. 10578 * Access: RW 10579 */ 10580 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10581 10582 /* reg_mgpc_packet_counter 10583 * Packet counter value. 10584 * Access: RW 10585 */ 10586 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10587 10588 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10589 enum mlxsw_reg_mgpc_opcode opcode, 10590 enum mlxsw_reg_flow_counter_set_type set_type) 10591 { 10592 MLXSW_REG_ZERO(mgpc, payload); 10593 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10594 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10595 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10596 } 10597 10598 /* MPRS - Monitoring Parsing State Register 10599 * ---------------------------------------- 10600 * The MPRS register is used for setting up the parsing for hash, 10601 * policy-engine and routing. 10602 */ 10603 #define MLXSW_REG_MPRS_ID 0x9083 10604 #define MLXSW_REG_MPRS_LEN 0x14 10605 10606 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10607 10608 /* reg_mprs_parsing_depth 10609 * Minimum parsing depth. 10610 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10611 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10612 * Access: RW 10613 */ 10614 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10615 10616 /* reg_mprs_parsing_en 10617 * Parsing enable. 10618 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10619 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10620 * Access: RW 10621 */ 10622 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10623 10624 /* reg_mprs_vxlan_udp_dport 10625 * VxLAN UDP destination port. 10626 * Used for identifying VxLAN packets and for dport field in 10627 * encapsulation. Default is 4789. 10628 * Access: RW 10629 */ 10630 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10631 10632 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10633 u16 vxlan_udp_dport) 10634 { 10635 MLXSW_REG_ZERO(mprs, payload); 10636 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10637 mlxsw_reg_mprs_parsing_en_set(payload, true); 10638 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10639 } 10640 10641 /* MOGCR - Monitoring Global Configuration Register 10642 * ------------------------------------------------ 10643 */ 10644 #define MLXSW_REG_MOGCR_ID 0x9086 10645 #define MLXSW_REG_MOGCR_LEN 0x20 10646 10647 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10648 10649 /* reg_mogcr_ptp_iftc 10650 * PTP Ingress FIFO Trap Clear 10651 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10652 * to this value. Default 0. 10653 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10654 * Access: RW 10655 */ 10656 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10657 10658 /* reg_mogcr_ptp_eftc 10659 * PTP Egress FIFO Trap Clear 10660 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10661 * to this value. Default 0. 10662 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10663 * Access: RW 10664 */ 10665 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10666 10667 /* reg_mogcr_mirroring_pid_base 10668 * Base policer id for mirroring policers. 10669 * Must have an even value (e.g. 1000, not 1001). 10670 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10671 * Access: RW 10672 */ 10673 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10674 10675 /* MPAGR - Monitoring Port Analyzer Global Register 10676 * ------------------------------------------------ 10677 * This register is used for global port analyzer configurations. 10678 * Note: This register is not supported by current FW versions for Spectrum-1. 10679 */ 10680 #define MLXSW_REG_MPAGR_ID 0x9089 10681 #define MLXSW_REG_MPAGR_LEN 0x0C 10682 10683 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10684 10685 enum mlxsw_reg_mpagr_trigger { 10686 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10687 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10688 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10689 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10690 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10691 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10692 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10693 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10694 }; 10695 10696 /* reg_mpagr_trigger 10697 * Mirror trigger. 10698 * Access: Index 10699 */ 10700 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10701 10702 /* reg_mpagr_pa_id 10703 * Port analyzer ID. 10704 * Access: RW 10705 */ 10706 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10707 10708 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10709 10710 /* reg_mpagr_probability_rate 10711 * Sampling rate. 10712 * Valid values are: 1 to 3.5*10^9 10713 * Value of 1 means "sample all". Default is 1. 10714 * Access: RW 10715 */ 10716 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10717 10718 static inline void mlxsw_reg_mpagr_pack(char *payload, 10719 enum mlxsw_reg_mpagr_trigger trigger, 10720 u8 pa_id, u32 probability_rate) 10721 { 10722 MLXSW_REG_ZERO(mpagr, payload); 10723 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10724 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10725 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10726 } 10727 10728 /* MOMTE - Monitoring Mirror Trigger Enable Register 10729 * ------------------------------------------------- 10730 * This register is used to configure the mirror enable for different mirror 10731 * reasons. 10732 */ 10733 #define MLXSW_REG_MOMTE_ID 0x908D 10734 #define MLXSW_REG_MOMTE_LEN 0x10 10735 10736 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10737 10738 /* reg_momte_local_port 10739 * Local port number. 10740 * Access: Index 10741 */ 10742 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10743 10744 enum mlxsw_reg_momte_type { 10745 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10746 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10747 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10748 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10749 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10750 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10751 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10752 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10753 }; 10754 10755 /* reg_momte_type 10756 * Type of mirroring. 10757 * Access: Index 10758 */ 10759 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10760 10761 /* reg_momte_tclass_en 10762 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10763 * 0: disable (default) 10764 * 1: enable 10765 * Access: RW 10766 */ 10767 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10768 10769 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10770 enum mlxsw_reg_momte_type type) 10771 { 10772 MLXSW_REG_ZERO(momte, payload); 10773 mlxsw_reg_momte_local_port_set(payload, local_port); 10774 mlxsw_reg_momte_type_set(payload, type); 10775 } 10776 10777 /* MTPPPC - Time Precision Packet Port Configuration 10778 * ------------------------------------------------- 10779 * This register serves for configuration of which PTP messages should be 10780 * timestamped. This is a global configuration, despite the register name. 10781 * 10782 * Reserved when Spectrum-2. 10783 */ 10784 #define MLXSW_REG_MTPPPC_ID 0x9090 10785 #define MLXSW_REG_MTPPPC_LEN 0x28 10786 10787 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10788 10789 /* reg_mtpppc_ing_timestamp_message_type 10790 * Bitwise vector of PTP message types to timestamp at ingress. 10791 * MessageType field as defined by IEEE 1588 10792 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10793 * Default all 0 10794 * Access: RW 10795 */ 10796 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10797 10798 /* reg_mtpppc_egr_timestamp_message_type 10799 * Bitwise vector of PTP message types to timestamp at egress. 10800 * MessageType field as defined by IEEE 1588 10801 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10802 * Default all 0 10803 * Access: RW 10804 */ 10805 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10806 10807 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10808 { 10809 MLXSW_REG_ZERO(mtpppc, payload); 10810 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10811 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10812 } 10813 10814 /* MTPPTR - Time Precision Packet Timestamping Reading 10815 * --------------------------------------------------- 10816 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10817 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10818 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10819 * trapped. The sequence number is used to synchronize the timestamp FIFO 10820 * entries and the trapped packets. 10821 * Reserved when Spectrum-2. 10822 */ 10823 10824 #define MLXSW_REG_MTPPTR_ID 0x9091 10825 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10826 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10827 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10828 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10829 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10830 10831 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10832 10833 /* reg_mtpptr_local_port 10834 * Not supported for CPU port. 10835 * Access: Index 10836 */ 10837 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10838 10839 enum mlxsw_reg_mtpptr_dir { 10840 MLXSW_REG_MTPPTR_DIR_INGRESS, 10841 MLXSW_REG_MTPPTR_DIR_EGRESS, 10842 }; 10843 10844 /* reg_mtpptr_dir 10845 * Direction. 10846 * Access: Index 10847 */ 10848 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10849 10850 /* reg_mtpptr_clr 10851 * Clear the records. 10852 * Access: OP 10853 */ 10854 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10855 10856 /* reg_mtpptr_num_rec 10857 * Number of valid records in the response 10858 * Range 0.. cap_ptp_timestamp_fifo 10859 * Access: RO 10860 */ 10861 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10862 10863 /* reg_mtpptr_rec_message_type 10864 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10865 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10866 * Access: RO 10867 */ 10868 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10869 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10870 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10871 10872 /* reg_mtpptr_rec_domain_number 10873 * DomainNumber field as defined by IEEE 1588 10874 * Access: RO 10875 */ 10876 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10877 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10878 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10879 10880 /* reg_mtpptr_rec_sequence_id 10881 * SequenceId field as defined by IEEE 1588 10882 * Access: RO 10883 */ 10884 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10885 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10886 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10887 10888 /* reg_mtpptr_rec_timestamp_high 10889 * Timestamp of when the PTP packet has passed through the port Units of PLL 10890 * clock time. 10891 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10892 * Access: RO 10893 */ 10894 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10895 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10896 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10897 10898 /* reg_mtpptr_rec_timestamp_low 10899 * See rec_timestamp_high. 10900 * Access: RO 10901 */ 10902 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10903 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10904 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10905 10906 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10907 unsigned int rec, 10908 u8 *p_message_type, 10909 u8 *p_domain_number, 10910 u16 *p_sequence_id, 10911 u64 *p_timestamp) 10912 { 10913 u32 timestamp_high, timestamp_low; 10914 10915 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10916 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10917 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10918 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10919 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10920 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10921 } 10922 10923 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10924 * --------------------------------------------------------- 10925 * This register is used for configuring under which trap to deliver PTP 10926 * packets depending on type of the packet. 10927 */ 10928 #define MLXSW_REG_MTPTPT_ID 0x9092 10929 #define MLXSW_REG_MTPTPT_LEN 0x08 10930 10931 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10932 10933 enum mlxsw_reg_mtptpt_trap_id { 10934 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10935 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10936 }; 10937 10938 /* reg_mtptpt_trap_id 10939 * Trap id. 10940 * Access: Index 10941 */ 10942 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10943 10944 /* reg_mtptpt_message_type 10945 * Bitwise vector of PTP message types to trap. This is a necessary but 10946 * non-sufficient condition since need to enable also per port. See MTPPPC. 10947 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10948 * Bit0: Sync, Bit1: Delay_Req) 10949 */ 10950 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10951 10952 static inline void mlxsw_reg_mtptpt_pack(char *payload, 10953 enum mlxsw_reg_mtptpt_trap_id trap_id, 10954 u16 message_type) 10955 { 10956 MLXSW_REG_ZERO(mtptpt, payload); 10957 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10958 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10959 } 10960 10961 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 10962 * ------------------------------------------------------------------------- 10963 */ 10964 #define MLXSW_REG_MTPCPC_ID 0x9093 10965 #define MLXSW_REG_MTPCPC_LEN 0x2C 10966 10967 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 10968 10969 /* reg_mtpcpc_pport 10970 * Per port: 10971 * 0: config is global. When reading - the local_port is 1. 10972 * 1: config is per port. 10973 * Access: Index 10974 */ 10975 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 10976 10977 /* reg_mtpcpc_local_port 10978 * Local port number. 10979 * Supported to/from CPU port. 10980 * Reserved when pport = 0. 10981 * Access: Index 10982 */ 10983 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 10984 10985 /* reg_mtpcpc_ptp_trap_en 10986 * Enable PTP traps. 10987 * The trap_id is configured by MTPTPT. 10988 * Access: RW 10989 */ 10990 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 10991 10992 /* reg_mtpcpc_ing_correction_message_type 10993 * Bitwise vector of PTP message types to update correction-field at ingress. 10994 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10995 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 10996 * Default all 0 10997 * Access: RW 10998 */ 10999 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 11000 11001 /* reg_mtpcpc_egr_correction_message_type 11002 * Bitwise vector of PTP message types to update correction-field at egress. 11003 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11004 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11005 * Default all 0 11006 * Access: RW 11007 */ 11008 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 11009 11010 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 11011 u16 local_port, bool ptp_trap_en, 11012 u16 ing, u16 egr) 11013 { 11014 MLXSW_REG_ZERO(mtpcpc, payload); 11015 mlxsw_reg_mtpcpc_pport_set(payload, pport); 11016 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 11017 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 11018 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 11019 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 11020 } 11021 11022 /* MFGD - Monitoring FW General Debug Register 11023 * ------------------------------------------- 11024 */ 11025 #define MLXSW_REG_MFGD_ID 0x90F0 11026 #define MLXSW_REG_MFGD_LEN 0x0C 11027 11028 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11029 11030 /* reg_mfgd_fw_fatal_event_mode 11031 * 0 - don't check FW fatal (default) 11032 * 1 - check FW fatal - enable MFDE trap 11033 * Access: RW 11034 */ 11035 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11036 11037 /* reg_mfgd_trigger_test 11038 * Access: WO 11039 */ 11040 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11041 11042 /* MGPIR - Management General Peripheral Information Register 11043 * ---------------------------------------------------------- 11044 * MGPIR register allows software to query the hardware and 11045 * firmware general information of peripheral entities. 11046 */ 11047 #define MLXSW_REG_MGPIR_ID 0x9100 11048 #define MLXSW_REG_MGPIR_LEN 0xA0 11049 11050 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11051 11052 enum mlxsw_reg_mgpir_device_type { 11053 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11054 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11055 }; 11056 11057 /* mgpir_slot_index 11058 * Slot index (0: Main board). 11059 * Access: Index 11060 */ 11061 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11062 11063 /* mgpir_device_type 11064 * Access: RO 11065 */ 11066 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11067 11068 /* mgpir_devices_per_flash 11069 * Number of devices of device_type per flash (can be shared by few devices). 11070 * Access: RO 11071 */ 11072 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11073 11074 /* mgpir_num_of_devices 11075 * Number of devices of device_type. 11076 * Access: RO 11077 */ 11078 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11079 11080 /* max_modules_per_slot 11081 * Maximum number of modules that can be connected per slot. 11082 * Access: RO 11083 */ 11084 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11085 11086 /* mgpir_num_of_slots 11087 * Number of slots in the system. 11088 * Access: RO 11089 */ 11090 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11091 11092 /* mgpir_num_of_modules 11093 * Number of modules. 11094 * Access: RO 11095 */ 11096 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11097 11098 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11099 { 11100 MLXSW_REG_ZERO(mgpir, payload); 11101 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11102 } 11103 11104 static inline void 11105 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11106 enum mlxsw_reg_mgpir_device_type *device_type, 11107 u8 *devices_per_flash, u8 *num_of_modules, 11108 u8 *num_of_slots) 11109 { 11110 if (num_of_devices) 11111 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11112 if (device_type) 11113 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11114 if (devices_per_flash) 11115 *devices_per_flash = 11116 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11117 if (num_of_modules) 11118 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11119 if (num_of_slots) 11120 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11121 } 11122 11123 /* MBCT - Management Binary Code Transfer Register 11124 * ----------------------------------------------- 11125 * This register allows to transfer binary codes from the host to 11126 * the management FW by transferring it by chunks of maximum 1KB. 11127 */ 11128 #define MLXSW_REG_MBCT_ID 0x9120 11129 #define MLXSW_REG_MBCT_LEN 0x420 11130 11131 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11132 11133 /* reg_mbct_slot_index 11134 * Slot index. 0 is reserved. 11135 * Access: Index 11136 */ 11137 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11138 11139 /* reg_mbct_data_size 11140 * Actual data field size in bytes for the current data transfer. 11141 * Access: WO 11142 */ 11143 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11144 11145 enum mlxsw_reg_mbct_op { 11146 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11147 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11148 MLXSW_REG_MBCT_OP_ACTIVATE, 11149 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11150 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11151 }; 11152 11153 /* reg_mbct_op 11154 * Access: WO 11155 */ 11156 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11157 11158 /* reg_mbct_last 11159 * Indicates that the current data field is the last chunk of the INI. 11160 * Access: WO 11161 */ 11162 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11163 11164 /* reg_mbct_oee 11165 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11166 * was executed and the fsm_state has changed. 11167 * Access: WO 11168 */ 11169 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11170 11171 enum mlxsw_reg_mbct_status { 11172 /* Partial data transfer completed successfully and ready for next 11173 * data transfer. 11174 */ 11175 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11176 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11177 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11178 /* Error - trying to erase INI while it being used. */ 11179 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11180 /* Last data transfer completed, applying magic pattern. */ 11181 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11182 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11183 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11184 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11185 }; 11186 11187 /* reg_mbct_status 11188 * Status. 11189 * Access: RO 11190 */ 11191 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11192 11193 enum mlxsw_reg_mbct_fsm_state { 11194 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11195 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11196 }; 11197 11198 /* reg_mbct_fsm_state 11199 * FSM state. 11200 * Access: RO 11201 */ 11202 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11203 11204 #define MLXSW_REG_MBCT_DATA_LEN 1024 11205 11206 /* reg_mbct_data 11207 * Up to 1KB of data. 11208 * Access: WO 11209 */ 11210 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11211 11212 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11213 enum mlxsw_reg_mbct_op op, bool oee) 11214 { 11215 MLXSW_REG_ZERO(mbct, payload); 11216 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11217 mlxsw_reg_mbct_op_set(payload, op); 11218 mlxsw_reg_mbct_oee_set(payload, oee); 11219 } 11220 11221 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11222 u16 data_size, bool last, 11223 const char *data) 11224 { 11225 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11226 return; 11227 mlxsw_reg_mbct_data_size_set(payload, data_size); 11228 mlxsw_reg_mbct_last_set(payload, last); 11229 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11230 } 11231 11232 static inline void 11233 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11234 enum mlxsw_reg_mbct_status *p_status, 11235 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11236 { 11237 if (p_slot_index) 11238 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11239 *p_status = mlxsw_reg_mbct_status_get(payload); 11240 if (p_fsm_state) 11241 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11242 } 11243 11244 /* MDDT - Management DownStream Device Tunneling Register 11245 * ------------------------------------------------------ 11246 * This register allows to deliver query and request messages (PRM registers, 11247 * commands) to a DownStream device. 11248 */ 11249 #define MLXSW_REG_MDDT_ID 0x9160 11250 #define MLXSW_REG_MDDT_LEN 0x110 11251 11252 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11253 11254 /* reg_mddt_slot_index 11255 * Slot index. 11256 * Access: Index 11257 */ 11258 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11259 11260 /* reg_mddt_device_index 11261 * Device index. 11262 * Access: Index 11263 */ 11264 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11265 11266 /* reg_mddt_read_size 11267 * Read size in D-Words. 11268 * Access: OP 11269 */ 11270 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11271 11272 /* reg_mddt_write_size 11273 * Write size in D-Words. 11274 * Access: OP 11275 */ 11276 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11277 11278 enum mlxsw_reg_mddt_status { 11279 MLXSW_REG_MDDT_STATUS_OK, 11280 }; 11281 11282 /* reg_mddt_status 11283 * Return code of the Downstream Device to the register that was sent. 11284 * Access: RO 11285 */ 11286 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11287 11288 enum mlxsw_reg_mddt_method { 11289 MLXSW_REG_MDDT_METHOD_QUERY, 11290 MLXSW_REG_MDDT_METHOD_WRITE, 11291 }; 11292 11293 /* reg_mddt_method 11294 * Access: OP 11295 */ 11296 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11297 11298 /* reg_mddt_register_id 11299 * Access: Index 11300 */ 11301 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11302 11303 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11304 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11305 11306 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11307 { 11308 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11309 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11310 } 11311 11312 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11313 u8 device_index, 11314 enum mlxsw_reg_mddt_method method, 11315 const struct mlxsw_reg_info *reg, 11316 char **inner_payload) 11317 { 11318 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11319 11320 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11321 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11322 11323 MLXSW_REG_ZERO(mddt, payload); 11324 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11325 mlxsw_reg_mddt_device_index_set(payload, device_index); 11326 mlxsw_reg_mddt_method_set(payload, method); 11327 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11328 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11329 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11330 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11331 } 11332 11333 /* MDDQ - Management DownStream Device Query Register 11334 * -------------------------------------------------- 11335 * This register allows to query the DownStream device properties. The desired 11336 * information is chosen upon the query_type field and is delivered by 32B 11337 * of data blocks. 11338 */ 11339 #define MLXSW_REG_MDDQ_ID 0x9161 11340 #define MLXSW_REG_MDDQ_LEN 0x30 11341 11342 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11343 11344 /* reg_mddq_sie 11345 * Slot info event enable. 11346 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11347 * active / ready will generate a DSDSC event. 11348 * Access: RW 11349 */ 11350 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11351 11352 enum mlxsw_reg_mddq_query_type { 11353 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11354 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11355 * on the slot, data_valid 11356 * will be '0'. 11357 */ 11358 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11359 }; 11360 11361 /* reg_mddq_query_type 11362 * Access: Index 11363 */ 11364 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11365 11366 /* reg_mddq_slot_index 11367 * Slot index. 0 is reserved. 11368 * Access: Index 11369 */ 11370 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11371 11372 /* reg_mddq_response_msg_seq 11373 * Response message sequential number. For a specific request, the response 11374 * message sequential number is the following one. In addition, the last 11375 * message should be 0. 11376 * Access: RO 11377 */ 11378 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11379 11380 /* reg_mddq_request_msg_seq 11381 * Request message sequential number. 11382 * The first message number should be 0. 11383 * Access: Index 11384 */ 11385 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11386 11387 /* reg_mddq_data_valid 11388 * If set, the data in the data field is valid and contain the information 11389 * for the queried index. 11390 * Access: RO 11391 */ 11392 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11393 11394 /* reg_mddq_slot_info_provisioned 11395 * If set, the INI file is applied and the card is provisioned. 11396 * Access: RO 11397 */ 11398 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11399 11400 /* reg_mddq_slot_info_sr_valid 11401 * If set, Shift Register is valid (after being provisioned) and data 11402 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11403 * Access: RO 11404 */ 11405 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11406 11407 enum mlxsw_reg_mddq_slot_info_ready { 11408 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11409 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11410 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11411 }; 11412 11413 /* reg_mddq_slot_info_lc_ready 11414 * If set, the LC is powered on, matching the INI version and a new FW 11415 * version can be burnt (if necessary). 11416 * Access: RO 11417 */ 11418 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11419 11420 /* reg_mddq_slot_info_active 11421 * If set, the FW has completed the MDDC.device_enable command. 11422 * Access: RO 11423 */ 11424 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11425 11426 /* reg_mddq_slot_info_hw_revision 11427 * Major user-configured version number of the current INI file. 11428 * Valid only when active or ready are '1'. 11429 * Access: RO 11430 */ 11431 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11432 11433 /* reg_mddq_slot_info_ini_file_version 11434 * User-configured version number of the current INI file. 11435 * Valid only when active or lc_ready are '1'. 11436 * Access: RO 11437 */ 11438 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11439 11440 /* reg_mddq_slot_info_card_type 11441 * Access: RO 11442 */ 11443 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11444 11445 static inline void 11446 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11447 enum mlxsw_reg_mddq_query_type query_type) 11448 { 11449 MLXSW_REG_ZERO(mddq, payload); 11450 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11451 mlxsw_reg_mddq_query_type_set(payload, query_type); 11452 } 11453 11454 static inline void 11455 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11456 { 11457 __mlxsw_reg_mddq_pack(payload, slot_index, 11458 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11459 mlxsw_reg_mddq_sie_set(payload, sie); 11460 } 11461 11462 static inline void 11463 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11464 bool *p_provisioned, bool *p_sr_valid, 11465 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11466 bool *p_active, u16 *p_hw_revision, 11467 u16 *p_ini_file_version, 11468 u8 *p_card_type) 11469 { 11470 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11471 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11472 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11473 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11474 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11475 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11476 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11477 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11478 } 11479 11480 /* reg_mddq_device_info_flash_owner 11481 * If set, the device is the flash owner. Otherwise, a shared flash 11482 * is used by this device (another device is the flash owner). 11483 * Access: RO 11484 */ 11485 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11486 11487 /* reg_mddq_device_info_device_index 11488 * Device index. The first device should number 0. 11489 * Access: RO 11490 */ 11491 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11492 11493 /* reg_mddq_device_info_fw_major 11494 * Major FW version number. 11495 * Access: RO 11496 */ 11497 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11498 11499 /* reg_mddq_device_info_fw_minor 11500 * Minor FW version number. 11501 * Access: RO 11502 */ 11503 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11504 11505 /* reg_mddq_device_info_fw_sub_minor 11506 * Sub-minor FW version number. 11507 * Access: RO 11508 */ 11509 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11510 11511 static inline void 11512 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11513 u8 request_msg_seq) 11514 { 11515 __mlxsw_reg_mddq_pack(payload, slot_index, 11516 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11517 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11518 } 11519 11520 static inline void 11521 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11522 bool *p_data_valid, bool *p_flash_owner, 11523 u8 *p_device_index, u16 *p_fw_major, 11524 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11525 { 11526 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11527 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11528 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11529 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11530 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11531 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11532 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11533 } 11534 11535 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11536 11537 /* reg_mddq_slot_ascii_name 11538 * Slot's ASCII name. 11539 * Access: RO 11540 */ 11541 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11542 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11543 11544 static inline void 11545 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11546 { 11547 __mlxsw_reg_mddq_pack(payload, slot_index, 11548 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11549 } 11550 11551 static inline void 11552 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11553 { 11554 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11555 } 11556 11557 /* MDDC - Management DownStream Device Control Register 11558 * ---------------------------------------------------- 11559 * This register allows to control downstream devices and line cards. 11560 */ 11561 #define MLXSW_REG_MDDC_ID 0x9163 11562 #define MLXSW_REG_MDDC_LEN 0x30 11563 11564 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11565 11566 /* reg_mddc_slot_index 11567 * Slot index. 0 is reserved. 11568 * Access: Index 11569 */ 11570 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11571 11572 /* reg_mddc_rst 11573 * Reset request. 11574 * Access: OP 11575 */ 11576 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11577 11578 /* reg_mddc_device_enable 11579 * When set, FW is the manager and allowed to program the downstream device. 11580 * Access: RW 11581 */ 11582 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11583 11584 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11585 bool device_enable) 11586 { 11587 MLXSW_REG_ZERO(mddc, payload); 11588 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11589 mlxsw_reg_mddc_rst_set(payload, rst); 11590 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11591 } 11592 11593 /* MFDE - Monitoring FW Debug Register 11594 * ----------------------------------- 11595 */ 11596 #define MLXSW_REG_MFDE_ID 0x9200 11597 #define MLXSW_REG_MFDE_LEN 0x30 11598 11599 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11600 11601 /* reg_mfde_irisc_id 11602 * Which irisc triggered the event 11603 * Access: RO 11604 */ 11605 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11606 11607 enum mlxsw_reg_mfde_severity { 11608 /* Unrecoverable switch behavior */ 11609 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11610 /* Unexpected state with possible systemic failure */ 11611 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11612 /* Unexpected state without systemic failure */ 11613 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11614 }; 11615 11616 /* reg_mfde_severity 11617 * The severity of the event. 11618 * Access: RO 11619 */ 11620 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11621 11622 enum mlxsw_reg_mfde_event_id { 11623 /* CRspace timeout */ 11624 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11625 /* KVD insertion machine stopped */ 11626 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11627 /* Triggered by MFGD.trigger_test */ 11628 MLXSW_REG_MFDE_EVENT_ID_TEST, 11629 /* Triggered when firmware hits an assert */ 11630 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11631 /* Fatal error interrupt from hardware */ 11632 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11633 }; 11634 11635 /* reg_mfde_event_id 11636 * Access: RO 11637 */ 11638 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11639 11640 enum mlxsw_reg_mfde_method { 11641 MLXSW_REG_MFDE_METHOD_QUERY, 11642 MLXSW_REG_MFDE_METHOD_WRITE, 11643 }; 11644 11645 /* reg_mfde_method 11646 * Access: RO 11647 */ 11648 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11649 11650 /* reg_mfde_long_process 11651 * Indicates if the command is in long_process mode. 11652 * Access: RO 11653 */ 11654 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11655 11656 enum mlxsw_reg_mfde_command_type { 11657 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11658 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11659 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11660 }; 11661 11662 /* reg_mfde_command_type 11663 * Access: RO 11664 */ 11665 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11666 11667 /* reg_mfde_reg_attr_id 11668 * EMAD - register id, MAD - attibute id 11669 * Access: RO 11670 */ 11671 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11672 11673 /* reg_mfde_crspace_to_log_address 11674 * crspace address accessed, which resulted in timeout. 11675 * Access: RO 11676 */ 11677 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11678 11679 /* reg_mfde_crspace_to_oe 11680 * 0 - New event 11681 * 1 - Old event, occurred before MFGD activation. 11682 * Access: RO 11683 */ 11684 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11685 11686 /* reg_mfde_crspace_to_log_id 11687 * Which irisc triggered the timeout. 11688 * Access: RO 11689 */ 11690 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11691 11692 /* reg_mfde_crspace_to_log_ip 11693 * IP (instruction pointer) that triggered the timeout. 11694 * Access: RO 11695 */ 11696 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11697 11698 /* reg_mfde_kvd_im_stop_oe 11699 * 0 - New event 11700 * 1 - Old event, occurred before MFGD activation. 11701 * Access: RO 11702 */ 11703 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11704 11705 /* reg_mfde_kvd_im_stop_pipes_mask 11706 * Bit per kvh pipe. 11707 * Access: RO 11708 */ 11709 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11710 11711 /* reg_mfde_fw_assert_var0-4 11712 * Variables passed to assert. 11713 * Access: RO 11714 */ 11715 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11716 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11717 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11718 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11719 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11720 11721 /* reg_mfde_fw_assert_existptr 11722 * The instruction pointer when assert was triggered. 11723 * Access: RO 11724 */ 11725 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11726 11727 /* reg_mfde_fw_assert_callra 11728 * The return address after triggering assert. 11729 * Access: RO 11730 */ 11731 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11732 11733 /* reg_mfde_fw_assert_oe 11734 * 0 - New event 11735 * 1 - Old event, occurred before MFGD activation. 11736 * Access: RO 11737 */ 11738 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11739 11740 /* reg_mfde_fw_assert_tile_v 11741 * 0: The assert was from main 11742 * 1: The assert was from a tile 11743 * Access: RO 11744 */ 11745 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11746 11747 /* reg_mfde_fw_assert_tile_index 11748 * When tile_v=1, the tile_index that caused the assert. 11749 * Access: RO 11750 */ 11751 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11752 11753 /* reg_mfde_fw_assert_ext_synd 11754 * A generated one-to-one identifier which is specific per-assert. 11755 * Access: RO 11756 */ 11757 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11758 11759 /* reg_mfde_fatal_cause_id 11760 * HW interrupt cause id. 11761 * Access: RO 11762 */ 11763 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11764 11765 /* reg_mfde_fatal_cause_tile_v 11766 * 0: The assert was from main 11767 * 1: The assert was from a tile 11768 * Access: RO 11769 */ 11770 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11771 11772 /* reg_mfde_fatal_cause_tile_index 11773 * When tile_v=1, the tile_index that caused the assert. 11774 * Access: RO 11775 */ 11776 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11777 11778 /* TNGCR - Tunneling NVE General Configuration Register 11779 * ---------------------------------------------------- 11780 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11781 */ 11782 #define MLXSW_REG_TNGCR_ID 0xA001 11783 #define MLXSW_REG_TNGCR_LEN 0x44 11784 11785 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11786 11787 enum mlxsw_reg_tngcr_type { 11788 MLXSW_REG_TNGCR_TYPE_VXLAN, 11789 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11790 MLXSW_REG_TNGCR_TYPE_GENEVE, 11791 MLXSW_REG_TNGCR_TYPE_NVGRE, 11792 }; 11793 11794 /* reg_tngcr_type 11795 * Tunnel type for encapsulation and decapsulation. The types are mutually 11796 * exclusive. 11797 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11798 * Access: RW 11799 */ 11800 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11801 11802 /* reg_tngcr_nve_valid 11803 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11804 * Access: RW 11805 */ 11806 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11807 11808 /* reg_tngcr_nve_ttl_uc 11809 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11810 * Access: RW 11811 */ 11812 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11813 11814 /* reg_tngcr_nve_ttl_mc 11815 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11816 * Access: RW 11817 */ 11818 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11819 11820 enum { 11821 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11822 MLXSW_REG_TNGCR_FL_NO_COPY, 11823 /* Copy flow label from inner packet if packet is IPv6 and 11824 * encapsulation is by IPv6. Otherwise, calculate flow label using 11825 * nve_flh. 11826 */ 11827 MLXSW_REG_TNGCR_FL_COPY, 11828 }; 11829 11830 /* reg_tngcr_nve_flc 11831 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11832 * Access: RW 11833 */ 11834 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11835 11836 enum { 11837 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11838 * uses {nve_fl_prefix, nve_fl_suffix}. 11839 */ 11840 MLXSW_REG_TNGCR_FL_NO_HASH, 11841 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11842 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11843 */ 11844 MLXSW_REG_TNGCR_FL_HASH, 11845 }; 11846 11847 /* reg_tngcr_nve_flh 11848 * NVE flow label hash. 11849 * Access: RW 11850 */ 11851 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11852 11853 /* reg_tngcr_nve_fl_prefix 11854 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11855 * Access: RW 11856 */ 11857 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11858 11859 /* reg_tngcr_nve_fl_suffix 11860 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11861 * Reserved when nve_flh=1 and for Spectrum. 11862 * Access: RW 11863 */ 11864 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11865 11866 enum { 11867 /* Source UDP port is fixed (default '0') */ 11868 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11869 /* Source UDP port is calculated based on hash */ 11870 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11871 }; 11872 11873 /* reg_tngcr_nve_udp_sport_type 11874 * NVE UDP source port type. 11875 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11876 * When the source UDP port is calculated based on hash, then the 8 LSBs 11877 * are calculated from hash the 8 MSBs are configured by 11878 * nve_udp_sport_prefix. 11879 * Access: RW 11880 */ 11881 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11882 11883 /* reg_tngcr_nve_udp_sport_prefix 11884 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11885 * Reserved when NVE type is NVGRE. 11886 * Access: RW 11887 */ 11888 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11889 11890 /* reg_tngcr_nve_group_size_mc 11891 * The amount of sequential linked lists of MC entries. The first linked 11892 * list is configured by SFD.underlay_mc_ptr. 11893 * Valid values: 1, 2, 4, 8, 16, 32, 64 11894 * The linked list are configured by TNUMT. 11895 * The hash is set by LAG hash. 11896 * Access: RW 11897 */ 11898 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11899 11900 /* reg_tngcr_nve_group_size_flood 11901 * The amount of sequential linked lists of flooding entries. The first 11902 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11903 * Valid values: 1, 2, 4, 8, 16, 32, 64 11904 * The linked list are configured by TNUMT. 11905 * The hash is set by LAG hash. 11906 * Access: RW 11907 */ 11908 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11909 11910 /* reg_tngcr_learn_enable 11911 * During decapsulation, whether to learn from NVE port. 11912 * Reserved when Spectrum-2. See TNPC. 11913 * Access: RW 11914 */ 11915 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11916 11917 /* reg_tngcr_underlay_virtual_router 11918 * Underlay virtual router. 11919 * Reserved when Spectrum-2. 11920 * Access: RW 11921 */ 11922 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11923 11924 /* reg_tngcr_underlay_rif 11925 * Underlay ingress router interface. RIF type should be loopback generic. 11926 * Reserved when Spectrum. 11927 * Access: RW 11928 */ 11929 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11930 11931 /* reg_tngcr_usipv4 11932 * Underlay source IPv4 address of the NVE. 11933 * Access: RW 11934 */ 11935 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11936 11937 /* reg_tngcr_usipv6 11938 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11939 * modified under traffic of NVE tunneling encapsulation. 11940 * Access: RW 11941 */ 11942 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11943 11944 static inline void mlxsw_reg_tngcr_pack(char *payload, 11945 enum mlxsw_reg_tngcr_type type, 11946 bool valid, u8 ttl) 11947 { 11948 MLXSW_REG_ZERO(tngcr, payload); 11949 mlxsw_reg_tngcr_type_set(payload, type); 11950 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11951 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11952 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11953 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11954 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11955 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11956 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11957 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11958 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11959 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11960 } 11961 11962 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11963 * ------------------------------------------------------- 11964 * The TNUMT register is for building the underlay MC table. It is used 11965 * for MC, flooding and BC traffic into the NVE tunnel. 11966 */ 11967 #define MLXSW_REG_TNUMT_ID 0xA003 11968 #define MLXSW_REG_TNUMT_LEN 0x20 11969 11970 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11971 11972 enum mlxsw_reg_tnumt_record_type { 11973 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11974 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11975 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11976 }; 11977 11978 /* reg_tnumt_record_type 11979 * Record type. 11980 * Access: RW 11981 */ 11982 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11983 11984 /* reg_tnumt_tunnel_port 11985 * Tunnel port. 11986 * Access: RW 11987 */ 11988 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11989 11990 /* reg_tnumt_underlay_mc_ptr 11991 * Index to the underlay multicast table. 11992 * For Spectrum the index is to the KVD linear. 11993 * Access: Index 11994 */ 11995 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11996 11997 /* reg_tnumt_vnext 11998 * The next_underlay_mc_ptr is valid. 11999 * Access: RW 12000 */ 12001 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 12002 12003 /* reg_tnumt_next_underlay_mc_ptr 12004 * The next index to the underlay multicast table. 12005 * Access: RW 12006 */ 12007 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 12008 12009 /* reg_tnumt_record_size 12010 * Number of IP addresses in the record. 12011 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 12012 * Access: RW 12013 */ 12014 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 12015 12016 /* reg_tnumt_udip 12017 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 12018 * Access: RW 12019 */ 12020 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 12021 12022 /* reg_tnumt_udip_ptr 12023 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 12024 * i >= size. The IPv6 addresses are configured by RIPS. 12025 * Access: RW 12026 */ 12027 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 12028 12029 static inline void mlxsw_reg_tnumt_pack(char *payload, 12030 enum mlxsw_reg_tnumt_record_type type, 12031 enum mlxsw_reg_tunnel_port tport, 12032 u32 underlay_mc_ptr, bool vnext, 12033 u32 next_underlay_mc_ptr, 12034 u8 record_size) 12035 { 12036 MLXSW_REG_ZERO(tnumt, payload); 12037 mlxsw_reg_tnumt_record_type_set(payload, type); 12038 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12039 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12040 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12041 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12042 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12043 } 12044 12045 /* TNQCR - Tunneling NVE QoS Configuration Register 12046 * ------------------------------------------------ 12047 * The TNQCR register configures how QoS is set in encapsulation into the 12048 * underlay network. 12049 */ 12050 #define MLXSW_REG_TNQCR_ID 0xA010 12051 #define MLXSW_REG_TNQCR_LEN 0x0C 12052 12053 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12054 12055 /* reg_tnqcr_enc_set_dscp 12056 * For encapsulation: How to set DSCP field: 12057 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12058 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12059 * 1 - Set the DSCP field as TNQDR.dscp 12060 * Access: RW 12061 */ 12062 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12063 12064 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12065 { 12066 MLXSW_REG_ZERO(tnqcr, payload); 12067 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12068 } 12069 12070 /* TNQDR - Tunneling NVE QoS Default Register 12071 * ------------------------------------------ 12072 * The TNQDR register configures the default QoS settings for NVE 12073 * encapsulation. 12074 */ 12075 #define MLXSW_REG_TNQDR_ID 0xA011 12076 #define MLXSW_REG_TNQDR_LEN 0x08 12077 12078 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12079 12080 /* reg_tnqdr_local_port 12081 * Local port number (receive port). CPU port is supported. 12082 * Access: Index 12083 */ 12084 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12085 12086 /* reg_tnqdr_dscp 12087 * For encapsulation, the default DSCP. 12088 * Access: RW 12089 */ 12090 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12091 12092 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12093 { 12094 MLXSW_REG_ZERO(tnqdr, payload); 12095 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12096 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12097 } 12098 12099 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12100 * -------------------------------------------------------- 12101 * The TNEEM register maps ECN of the IP header at the ingress to the 12102 * encapsulation to the ECN of the underlay network. 12103 */ 12104 #define MLXSW_REG_TNEEM_ID 0xA012 12105 #define MLXSW_REG_TNEEM_LEN 0x0C 12106 12107 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12108 12109 /* reg_tneem_overlay_ecn 12110 * ECN of the IP header in the overlay network. 12111 * Access: Index 12112 */ 12113 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12114 12115 /* reg_tneem_underlay_ecn 12116 * ECN of the IP header in the underlay network. 12117 * Access: RW 12118 */ 12119 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12120 12121 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12122 u8 underlay_ecn) 12123 { 12124 MLXSW_REG_ZERO(tneem, payload); 12125 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12126 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12127 } 12128 12129 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12130 * -------------------------------------------------------- 12131 * The TNDEM register configures the actions that are done in the 12132 * decapsulation. 12133 */ 12134 #define MLXSW_REG_TNDEM_ID 0xA013 12135 #define MLXSW_REG_TNDEM_LEN 0x0C 12136 12137 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12138 12139 /* reg_tndem_underlay_ecn 12140 * ECN field of the IP header in the underlay network. 12141 * Access: Index 12142 */ 12143 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12144 12145 /* reg_tndem_overlay_ecn 12146 * ECN field of the IP header in the overlay network. 12147 * Access: Index 12148 */ 12149 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12150 12151 /* reg_tndem_eip_ecn 12152 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12153 * from the decapsulation. 12154 * Access: RW 12155 */ 12156 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12157 12158 /* reg_tndem_trap_en 12159 * Trap enable: 12160 * 0 - No trap due to decap ECN 12161 * 1 - Trap enable with trap_id 12162 * Access: RW 12163 */ 12164 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12165 12166 /* reg_tndem_trap_id 12167 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12168 * Reserved when trap_en is '0'. 12169 * Access: RW 12170 */ 12171 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12172 12173 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12174 u8 overlay_ecn, u8 ecn, bool trap_en, 12175 u16 trap_id) 12176 { 12177 MLXSW_REG_ZERO(tndem, payload); 12178 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12179 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12180 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12181 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12182 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12183 } 12184 12185 /* TNPC - Tunnel Port Configuration Register 12186 * ----------------------------------------- 12187 * The TNPC register is used for tunnel port configuration. 12188 * Reserved when Spectrum. 12189 */ 12190 #define MLXSW_REG_TNPC_ID 0xA020 12191 #define MLXSW_REG_TNPC_LEN 0x18 12192 12193 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12194 12195 /* reg_tnpc_tunnel_port 12196 * Tunnel port. 12197 * Access: Index 12198 */ 12199 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12200 12201 /* reg_tnpc_learn_enable_v6 12202 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12203 * Access: RW 12204 */ 12205 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12206 12207 /* reg_tnpc_learn_enable_v4 12208 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12209 * Access: RW 12210 */ 12211 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12212 12213 static inline void mlxsw_reg_tnpc_pack(char *payload, 12214 enum mlxsw_reg_tunnel_port tport, 12215 bool learn_enable) 12216 { 12217 MLXSW_REG_ZERO(tnpc, payload); 12218 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12219 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12220 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12221 } 12222 12223 /* TIGCR - Tunneling IPinIP General Configuration Register 12224 * ------------------------------------------------------- 12225 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12226 */ 12227 #define MLXSW_REG_TIGCR_ID 0xA801 12228 #define MLXSW_REG_TIGCR_LEN 0x10 12229 12230 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12231 12232 /* reg_tigcr_ipip_ttlc 12233 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12234 * header. 12235 * Access: RW 12236 */ 12237 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12238 12239 /* reg_tigcr_ipip_ttl_uc 12240 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12241 * reg_tigcr_ipip_ttlc is unset. 12242 * Access: RW 12243 */ 12244 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12245 12246 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12247 { 12248 MLXSW_REG_ZERO(tigcr, payload); 12249 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12250 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12251 } 12252 12253 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12254 * ----------------------------------------------------------- 12255 * The TIEEM register maps ECN of the IP header at the ingress to the 12256 * encapsulation to the ECN of the underlay network. 12257 */ 12258 #define MLXSW_REG_TIEEM_ID 0xA812 12259 #define MLXSW_REG_TIEEM_LEN 0x0C 12260 12261 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12262 12263 /* reg_tieem_overlay_ecn 12264 * ECN of the IP header in the overlay network. 12265 * Access: Index 12266 */ 12267 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12268 12269 /* reg_tineem_underlay_ecn 12270 * ECN of the IP header in the underlay network. 12271 * Access: RW 12272 */ 12273 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12274 12275 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12276 u8 underlay_ecn) 12277 { 12278 MLXSW_REG_ZERO(tieem, payload); 12279 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12280 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12281 } 12282 12283 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12284 * ----------------------------------------------------------- 12285 * The TIDEM register configures the actions that are done in the 12286 * decapsulation. 12287 */ 12288 #define MLXSW_REG_TIDEM_ID 0xA813 12289 #define MLXSW_REG_TIDEM_LEN 0x0C 12290 12291 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12292 12293 /* reg_tidem_underlay_ecn 12294 * ECN field of the IP header in the underlay network. 12295 * Access: Index 12296 */ 12297 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12298 12299 /* reg_tidem_overlay_ecn 12300 * ECN field of the IP header in the overlay network. 12301 * Access: Index 12302 */ 12303 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12304 12305 /* reg_tidem_eip_ecn 12306 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12307 * from the decapsulation. 12308 * Access: RW 12309 */ 12310 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12311 12312 /* reg_tidem_trap_en 12313 * Trap enable: 12314 * 0 - No trap due to decap ECN 12315 * 1 - Trap enable with trap_id 12316 * Access: RW 12317 */ 12318 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12319 12320 /* reg_tidem_trap_id 12321 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12322 * Reserved when trap_en is '0'. 12323 * Access: RW 12324 */ 12325 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12326 12327 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12328 u8 overlay_ecn, u8 eip_ecn, 12329 bool trap_en, u16 trap_id) 12330 { 12331 MLXSW_REG_ZERO(tidem, payload); 12332 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12333 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12334 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12335 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12336 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12337 } 12338 12339 /* SBPR - Shared Buffer Pools Register 12340 * ----------------------------------- 12341 * The SBPR configures and retrieves the shared buffer pools and configuration. 12342 */ 12343 #define MLXSW_REG_SBPR_ID 0xB001 12344 #define MLXSW_REG_SBPR_LEN 0x14 12345 12346 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12347 12348 /* reg_sbpr_desc 12349 * When set, configures descriptor buffer. 12350 * Access: Index 12351 */ 12352 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12353 12354 /* shared direstion enum for SBPR, SBCM, SBPM */ 12355 enum mlxsw_reg_sbxx_dir { 12356 MLXSW_REG_SBXX_DIR_INGRESS, 12357 MLXSW_REG_SBXX_DIR_EGRESS, 12358 }; 12359 12360 /* reg_sbpr_dir 12361 * Direction. 12362 * Access: Index 12363 */ 12364 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12365 12366 /* reg_sbpr_pool 12367 * Pool index. 12368 * Access: Index 12369 */ 12370 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12371 12372 /* reg_sbpr_infi_size 12373 * Size is infinite. 12374 * Access: RW 12375 */ 12376 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12377 12378 /* reg_sbpr_size 12379 * Pool size in buffer cells. 12380 * Reserved when infi_size = 1. 12381 * Access: RW 12382 */ 12383 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12384 12385 enum mlxsw_reg_sbpr_mode { 12386 MLXSW_REG_SBPR_MODE_STATIC, 12387 MLXSW_REG_SBPR_MODE_DYNAMIC, 12388 }; 12389 12390 /* reg_sbpr_mode 12391 * Pool quota calculation mode. 12392 * Access: RW 12393 */ 12394 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12395 12396 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12397 enum mlxsw_reg_sbxx_dir dir, 12398 enum mlxsw_reg_sbpr_mode mode, u32 size, 12399 bool infi_size) 12400 { 12401 MLXSW_REG_ZERO(sbpr, payload); 12402 mlxsw_reg_sbpr_pool_set(payload, pool); 12403 mlxsw_reg_sbpr_dir_set(payload, dir); 12404 mlxsw_reg_sbpr_mode_set(payload, mode); 12405 mlxsw_reg_sbpr_size_set(payload, size); 12406 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12407 } 12408 12409 /* SBCM - Shared Buffer Class Management Register 12410 * ---------------------------------------------- 12411 * The SBCM register configures and retrieves the shared buffer allocation 12412 * and configuration according to Port-PG, including the binding to pool 12413 * and definition of the associated quota. 12414 */ 12415 #define MLXSW_REG_SBCM_ID 0xB002 12416 #define MLXSW_REG_SBCM_LEN 0x28 12417 12418 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12419 12420 /* reg_sbcm_local_port 12421 * Local port number. 12422 * For Ingress: excludes CPU port and Router port 12423 * For Egress: excludes IP Router 12424 * Access: Index 12425 */ 12426 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12427 12428 /* reg_sbcm_pg_buff 12429 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12430 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12431 * For traffic class: range is 0..cap_max_tclass - 1 12432 * Note that when traffic class is in MC aware mode then the traffic 12433 * classes which are MC aware cannot be configured. 12434 * Access: Index 12435 */ 12436 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12437 12438 /* reg_sbcm_dir 12439 * Direction. 12440 * Access: Index 12441 */ 12442 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12443 12444 /* reg_sbcm_min_buff 12445 * Minimum buffer size for the limiter, in cells. 12446 * Access: RW 12447 */ 12448 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12449 12450 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12451 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12452 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12453 12454 /* reg_sbcm_infi_max 12455 * Max buffer is infinite. 12456 * Access: RW 12457 */ 12458 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12459 12460 /* reg_sbcm_max_buff 12461 * When the pool associated to the port-pg/tclass is configured to 12462 * static, Maximum buffer size for the limiter configured in cells. 12463 * When the pool associated to the port-pg/tclass is configured to 12464 * dynamic, the max_buff holds the "alpha" parameter, supporting 12465 * the following values: 12466 * 0: 0 12467 * i: (1/128)*2^(i-1), for i=1..14 12468 * 0xFF: Infinity 12469 * Reserved when infi_max = 1. 12470 * Access: RW 12471 */ 12472 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12473 12474 /* reg_sbcm_pool 12475 * Association of the port-priority to a pool. 12476 * Access: RW 12477 */ 12478 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12479 12480 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12481 enum mlxsw_reg_sbxx_dir dir, 12482 u32 min_buff, u32 max_buff, 12483 bool infi_max, u8 pool) 12484 { 12485 MLXSW_REG_ZERO(sbcm, payload); 12486 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12487 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12488 mlxsw_reg_sbcm_dir_set(payload, dir); 12489 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12490 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12491 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12492 mlxsw_reg_sbcm_pool_set(payload, pool); 12493 } 12494 12495 /* SBPM - Shared Buffer Port Management Register 12496 * --------------------------------------------- 12497 * The SBPM register configures and retrieves the shared buffer allocation 12498 * and configuration according to Port-Pool, including the definition 12499 * of the associated quota. 12500 */ 12501 #define MLXSW_REG_SBPM_ID 0xB003 12502 #define MLXSW_REG_SBPM_LEN 0x28 12503 12504 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12505 12506 /* reg_sbpm_local_port 12507 * Local port number. 12508 * For Ingress: excludes CPU port and Router port 12509 * For Egress: excludes IP Router 12510 * Access: Index 12511 */ 12512 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12513 12514 /* reg_sbpm_pool 12515 * The pool associated to quota counting on the local_port. 12516 * Access: Index 12517 */ 12518 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12519 12520 /* reg_sbpm_dir 12521 * Direction. 12522 * Access: Index 12523 */ 12524 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12525 12526 /* reg_sbpm_buff_occupancy 12527 * Current buffer occupancy in cells. 12528 * Access: RO 12529 */ 12530 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12531 12532 /* reg_sbpm_clr 12533 * Clear Max Buffer Occupancy 12534 * When this bit is set, max_buff_occupancy field is cleared (and a 12535 * new max value is tracked from the time the clear was performed). 12536 * Access: OP 12537 */ 12538 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12539 12540 /* reg_sbpm_max_buff_occupancy 12541 * Maximum value of buffer occupancy in cells monitored. Cleared by 12542 * writing to the clr field. 12543 * Access: RO 12544 */ 12545 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12546 12547 /* reg_sbpm_min_buff 12548 * Minimum buffer size for the limiter, in cells. 12549 * Access: RW 12550 */ 12551 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12552 12553 /* reg_sbpm_max_buff 12554 * When the pool associated to the port-pg/tclass is configured to 12555 * static, Maximum buffer size for the limiter configured in cells. 12556 * When the pool associated to the port-pg/tclass is configured to 12557 * dynamic, the max_buff holds the "alpha" parameter, supporting 12558 * the following values: 12559 * 0: 0 12560 * i: (1/128)*2^(i-1), for i=1..14 12561 * 0xFF: Infinity 12562 * Access: RW 12563 */ 12564 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12565 12566 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12567 enum mlxsw_reg_sbxx_dir dir, bool clr, 12568 u32 min_buff, u32 max_buff) 12569 { 12570 MLXSW_REG_ZERO(sbpm, payload); 12571 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12572 mlxsw_reg_sbpm_pool_set(payload, pool); 12573 mlxsw_reg_sbpm_dir_set(payload, dir); 12574 mlxsw_reg_sbpm_clr_set(payload, clr); 12575 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12576 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12577 } 12578 12579 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12580 u32 *p_max_buff_occupancy) 12581 { 12582 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12583 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12584 } 12585 12586 /* SBMM - Shared Buffer Multicast Management Register 12587 * -------------------------------------------------- 12588 * The SBMM register configures and retrieves the shared buffer allocation 12589 * and configuration for MC packets according to Switch-Priority, including 12590 * the binding to pool and definition of the associated quota. 12591 */ 12592 #define MLXSW_REG_SBMM_ID 0xB004 12593 #define MLXSW_REG_SBMM_LEN 0x28 12594 12595 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12596 12597 /* reg_sbmm_prio 12598 * Switch Priority. 12599 * Access: Index 12600 */ 12601 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12602 12603 /* reg_sbmm_min_buff 12604 * Minimum buffer size for the limiter, in cells. 12605 * Access: RW 12606 */ 12607 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12608 12609 /* reg_sbmm_max_buff 12610 * When the pool associated to the port-pg/tclass is configured to 12611 * static, Maximum buffer size for the limiter configured in cells. 12612 * When the pool associated to the port-pg/tclass is configured to 12613 * dynamic, the max_buff holds the "alpha" parameter, supporting 12614 * the following values: 12615 * 0: 0 12616 * i: (1/128)*2^(i-1), for i=1..14 12617 * 0xFF: Infinity 12618 * Access: RW 12619 */ 12620 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12621 12622 /* reg_sbmm_pool 12623 * Association of the port-priority to a pool. 12624 * Access: RW 12625 */ 12626 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12627 12628 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12629 u32 max_buff, u8 pool) 12630 { 12631 MLXSW_REG_ZERO(sbmm, payload); 12632 mlxsw_reg_sbmm_prio_set(payload, prio); 12633 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12634 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12635 mlxsw_reg_sbmm_pool_set(payload, pool); 12636 } 12637 12638 /* SBSR - Shared Buffer Status Register 12639 * ------------------------------------ 12640 * The SBSR register retrieves the shared buffer occupancy according to 12641 * Port-Pool. Note that this register enables reading a large amount of data. 12642 * It is the user's responsibility to limit the amount of data to ensure the 12643 * response can match the maximum transfer unit. In case the response exceeds 12644 * the maximum transport unit, it will be truncated with no special notice. 12645 */ 12646 #define MLXSW_REG_SBSR_ID 0xB005 12647 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12648 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12649 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12650 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12651 MLXSW_REG_SBSR_REC_LEN * \ 12652 MLXSW_REG_SBSR_REC_MAX_COUNT) 12653 12654 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12655 12656 /* reg_sbsr_clr 12657 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12658 * field is cleared (and a new max value is tracked from the time the clear 12659 * was performed). 12660 * Access: OP 12661 */ 12662 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12663 12664 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12665 12666 /* reg_sbsr_port_page 12667 * Determines the range of the ports specified in the 'ingress_port_mask' 12668 * and 'egress_port_mask' bit masks. 12669 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12670 * Access: Index 12671 */ 12672 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12673 12674 /* reg_sbsr_ingress_port_mask 12675 * Bit vector for all ingress network ports. 12676 * Indicates which of the ports (for which the relevant bit is set) 12677 * are affected by the set operation. Configuration of any other port 12678 * does not change. 12679 * Access: Index 12680 */ 12681 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12682 12683 /* reg_sbsr_pg_buff_mask 12684 * Bit vector for all switch priority groups. 12685 * Indicates which of the priorities (for which the relevant bit is set) 12686 * are affected by the set operation. Configuration of any other priority 12687 * does not change. 12688 * Range is 0..cap_max_pg_buffers - 1 12689 * Access: Index 12690 */ 12691 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12692 12693 /* reg_sbsr_egress_port_mask 12694 * Bit vector for all egress network ports. 12695 * Indicates which of the ports (for which the relevant bit is set) 12696 * are affected by the set operation. Configuration of any other port 12697 * does not change. 12698 * Access: Index 12699 */ 12700 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12701 12702 /* reg_sbsr_tclass_mask 12703 * Bit vector for all traffic classes. 12704 * Indicates which of the traffic classes (for which the relevant bit is 12705 * set) are affected by the set operation. Configuration of any other 12706 * traffic class does not change. 12707 * Range is 0..cap_max_tclass - 1 12708 * Access: Index 12709 */ 12710 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12711 12712 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12713 { 12714 MLXSW_REG_ZERO(sbsr, payload); 12715 mlxsw_reg_sbsr_clr_set(payload, clr); 12716 } 12717 12718 /* reg_sbsr_rec_buff_occupancy 12719 * Current buffer occupancy in cells. 12720 * Access: RO 12721 */ 12722 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12723 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12724 12725 /* reg_sbsr_rec_max_buff_occupancy 12726 * Maximum value of buffer occupancy in cells monitored. Cleared by 12727 * writing to the clr field. 12728 * Access: RO 12729 */ 12730 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12731 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12732 12733 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12734 u32 *p_buff_occupancy, 12735 u32 *p_max_buff_occupancy) 12736 { 12737 *p_buff_occupancy = 12738 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12739 *p_max_buff_occupancy = 12740 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12741 } 12742 12743 /* SBIB - Shared Buffer Internal Buffer Register 12744 * --------------------------------------------- 12745 * The SBIB register configures per port buffers for internal use. The internal 12746 * buffers consume memory on the port buffers (note that the port buffers are 12747 * used also by PBMC). 12748 * 12749 * For Spectrum this is used for egress mirroring. 12750 */ 12751 #define MLXSW_REG_SBIB_ID 0xB006 12752 #define MLXSW_REG_SBIB_LEN 0x10 12753 12754 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12755 12756 /* reg_sbib_local_port 12757 * Local port number 12758 * Not supported for CPU port and router port 12759 * Access: Index 12760 */ 12761 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12762 12763 /* reg_sbib_buff_size 12764 * Units represented in cells 12765 * Allowed range is 0 to (cap_max_headroom_size - 1) 12766 * Default is 0 12767 * Access: RW 12768 */ 12769 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12770 12771 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12772 u32 buff_size) 12773 { 12774 MLXSW_REG_ZERO(sbib, payload); 12775 mlxsw_reg_sbib_local_port_set(payload, local_port); 12776 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12777 } 12778 12779 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12780 MLXSW_REG(sgcr), 12781 MLXSW_REG(spad), 12782 MLXSW_REG(sspr), 12783 MLXSW_REG(sfdat), 12784 MLXSW_REG(sfd), 12785 MLXSW_REG(sfn), 12786 MLXSW_REG(spms), 12787 MLXSW_REG(spvid), 12788 MLXSW_REG(spvm), 12789 MLXSW_REG(spaft), 12790 MLXSW_REG(sfgc), 12791 MLXSW_REG(sfdf), 12792 MLXSW_REG(sldr), 12793 MLXSW_REG(slcr), 12794 MLXSW_REG(slcor), 12795 MLXSW_REG(spmlr), 12796 MLXSW_REG(svfa), 12797 MLXSW_REG(spvtr), 12798 MLXSW_REG(svpe), 12799 MLXSW_REG(sfmr), 12800 MLXSW_REG(spvmlr), 12801 MLXSW_REG(spfsr), 12802 MLXSW_REG(spvc), 12803 MLXSW_REG(spevet), 12804 MLXSW_REG(smpe), 12805 MLXSW_REG(smid2), 12806 MLXSW_REG(cwtp), 12807 MLXSW_REG(cwtpm), 12808 MLXSW_REG(pgcr), 12809 MLXSW_REG(ppbt), 12810 MLXSW_REG(pacl), 12811 MLXSW_REG(pagt), 12812 MLXSW_REG(ptar), 12813 MLXSW_REG(ppbs), 12814 MLXSW_REG(prcr), 12815 MLXSW_REG(pefa), 12816 MLXSW_REG(pemrbt), 12817 MLXSW_REG(ptce2), 12818 MLXSW_REG(perpt), 12819 MLXSW_REG(peabfe), 12820 MLXSW_REG(perar), 12821 MLXSW_REG(ptce3), 12822 MLXSW_REG(percr), 12823 MLXSW_REG(pererp), 12824 MLXSW_REG(iedr), 12825 MLXSW_REG(qpts), 12826 MLXSW_REG(qpcr), 12827 MLXSW_REG(qtct), 12828 MLXSW_REG(qeec), 12829 MLXSW_REG(qrwe), 12830 MLXSW_REG(qpdsm), 12831 MLXSW_REG(qpdp), 12832 MLXSW_REG(qpdpm), 12833 MLXSW_REG(qtctm), 12834 MLXSW_REG(qpsc), 12835 MLXSW_REG(pmlp), 12836 MLXSW_REG(pmtu), 12837 MLXSW_REG(ptys), 12838 MLXSW_REG(ppad), 12839 MLXSW_REG(paos), 12840 MLXSW_REG(pfcc), 12841 MLXSW_REG(ppcnt), 12842 MLXSW_REG(pptb), 12843 MLXSW_REG(pbmc), 12844 MLXSW_REG(pspa), 12845 MLXSW_REG(pmaos), 12846 MLXSW_REG(pplr), 12847 MLXSW_REG(pmtdb), 12848 MLXSW_REG(pmecr), 12849 MLXSW_REG(pmpe), 12850 MLXSW_REG(pddr), 12851 MLXSW_REG(pmmp), 12852 MLXSW_REG(pllp), 12853 MLXSW_REG(pmtm), 12854 MLXSW_REG(htgt), 12855 MLXSW_REG(hpkt), 12856 MLXSW_REG(rgcr), 12857 MLXSW_REG(ritr), 12858 MLXSW_REG(rtar), 12859 MLXSW_REG(ratr), 12860 MLXSW_REG(rtdp), 12861 MLXSW_REG(rips), 12862 MLXSW_REG(ratrad), 12863 MLXSW_REG(rdpm), 12864 MLXSW_REG(ricnt), 12865 MLXSW_REG(rrcr), 12866 MLXSW_REG(ralta), 12867 MLXSW_REG(ralst), 12868 MLXSW_REG(raltb), 12869 MLXSW_REG(ralue), 12870 MLXSW_REG(rauht), 12871 MLXSW_REG(raleu), 12872 MLXSW_REG(rauhtd), 12873 MLXSW_REG(rigr2), 12874 MLXSW_REG(recr2), 12875 MLXSW_REG(rmft2), 12876 MLXSW_REG(reiv), 12877 MLXSW_REG(mfcr), 12878 MLXSW_REG(mfsc), 12879 MLXSW_REG(mfsm), 12880 MLXSW_REG(mfsl), 12881 MLXSW_REG(fore), 12882 MLXSW_REG(mtcap), 12883 MLXSW_REG(mtmp), 12884 MLXSW_REG(mtwe), 12885 MLXSW_REG(mtbr), 12886 MLXSW_REG(mcia), 12887 MLXSW_REG(mpat), 12888 MLXSW_REG(mpar), 12889 MLXSW_REG(mgir), 12890 MLXSW_REG(mrsr), 12891 MLXSW_REG(mlcr), 12892 MLXSW_REG(mcion), 12893 MLXSW_REG(mtpps), 12894 MLXSW_REG(mtutc), 12895 MLXSW_REG(mpsc), 12896 MLXSW_REG(mcqi), 12897 MLXSW_REG(mcc), 12898 MLXSW_REG(mcda), 12899 MLXSW_REG(mgpc), 12900 MLXSW_REG(mprs), 12901 MLXSW_REG(mogcr), 12902 MLXSW_REG(mpagr), 12903 MLXSW_REG(momte), 12904 MLXSW_REG(mtpppc), 12905 MLXSW_REG(mtpptr), 12906 MLXSW_REG(mtptpt), 12907 MLXSW_REG(mtpcpc), 12908 MLXSW_REG(mfgd), 12909 MLXSW_REG(mgpir), 12910 MLXSW_REG(mbct), 12911 MLXSW_REG(mddt), 12912 MLXSW_REG(mddq), 12913 MLXSW_REG(mddc), 12914 MLXSW_REG(mfde), 12915 MLXSW_REG(tngcr), 12916 MLXSW_REG(tnumt), 12917 MLXSW_REG(tnqcr), 12918 MLXSW_REG(tnqdr), 12919 MLXSW_REG(tneem), 12920 MLXSW_REG(tndem), 12921 MLXSW_REG(tnpc), 12922 MLXSW_REG(tigcr), 12923 MLXSW_REG(tieem), 12924 MLXSW_REG(tidem), 12925 MLXSW_REG(sbpr), 12926 MLXSW_REG(sbcm), 12927 MLXSW_REG(sbpm), 12928 MLXSW_REG(sbmm), 12929 MLXSW_REG(sbsr), 12930 MLXSW_REG(sbib), 12931 }; 12932 12933 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12934 { 12935 const struct mlxsw_reg_info *reg_info; 12936 int i; 12937 12938 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12939 reg_info = mlxsw_reg_infos[i]; 12940 if (reg_info->id == reg_id) 12941 return reg_info->name; 12942 } 12943 return "*UNKNOWN*"; 12944 } 12945 12946 /* PUDE - Port Up / Down Event 12947 * --------------------------- 12948 * Reports the operational state change of a port. 12949 */ 12950 #define MLXSW_REG_PUDE_LEN 0x10 12951 12952 /* reg_pude_swid 12953 * Switch partition ID with which to associate the port. 12954 * Access: Index 12955 */ 12956 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12957 12958 /* reg_pude_local_port 12959 * Local port number. 12960 * Access: Index 12961 */ 12962 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12963 12964 /* reg_pude_admin_status 12965 * Port administrative state (the desired state). 12966 * 1 - Up. 12967 * 2 - Down. 12968 * 3 - Up once. This means that in case of link failure, the port won't go 12969 * into polling mode, but will wait to be re-enabled by software. 12970 * 4 - Disabled by system. Can only be set by hardware. 12971 * Access: RO 12972 */ 12973 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12974 12975 /* reg_pude_oper_status 12976 * Port operatioanl state. 12977 * 1 - Up. 12978 * 2 - Down. 12979 * 3 - Down by port failure. This means that the device will not let the 12980 * port up again until explicitly specified by software. 12981 * Access: RO 12982 */ 12983 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12984 12985 #endif 12986