1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/pci_hw.h 3 * Copyright (c) 2015-2016 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the names of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") version 2 as published by the Free 20 * Software Foundation. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _MLXSW_PCI_HW_H 36 #define _MLXSW_PCI_HW_H 37 38 #include <linux/bitops.h> 39 40 #include "item.h" 41 42 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */ 43 #define MLXSW_PCI_PAGE_SIZE 4096 44 45 #define MLXSW_PCI_CIR_BASE 0x71000 46 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE 47 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04) 48 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08) 49 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C) 50 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10) 51 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14) 52 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18) 53 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23) 54 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22) 55 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12 56 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24 57 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000 58 59 #define MLXSW_PCI_SW_RESET 0xF0010 60 #define MLXSW_PCI_SW_RESET_RST_BIT BIT(0) 61 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 5000 62 #define MLXSW_PCI_SW_RESET_WAIT_MSECS 100 63 #define MLXSW_PCI_FW_READY 0xA1844 64 #define MLXSW_PCI_FW_READY_MASK 0xFFFF 65 #define MLXSW_PCI_FW_READY_MAGIC 0x5E 66 67 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000 68 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200 69 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400 70 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600 71 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800 72 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00 73 74 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \ 75 ((offset) + (type_offset) + (num) * 4) 76 77 #define MLXSW_PCI_CQS_MAX 96 78 #define MLXSW_PCI_EQS_COUNT 2 79 #define MLXSW_PCI_EQ_ASYNC_NUM 0 80 #define MLXSW_PCI_EQ_COMP_NUM 1 81 82 #define MLXSW_PCI_AQ_PAGES 8 83 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES) 84 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */ 85 #define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */ 86 #define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */ 87 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */ 88 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE) 89 #define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE) 90 #define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE) 91 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE) 92 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80 93 94 #define MLXSW_PCI_WQE_SG_ENTRIES 3 95 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA 96 97 /* pci_wqe_c 98 * If set it indicates that a completion should be reported upon 99 * execution of this descriptor. 100 */ 101 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1); 102 103 /* pci_wqe_lp 104 * Local Processing, set if packet should be processed by the local 105 * switch hardware: 106 * For Ethernet EMAD (Direct Route and non Direct Route) - 107 * must be set if packet destination is local device 108 * For InfiniBand CTL - must be set if packet destination is local device 109 * Otherwise it must be clear 110 * Local Process packets must not exceed the size of 2K (including payload 111 * and headers). 112 */ 113 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1); 114 115 /* pci_wqe_type 116 * Packet type. 117 */ 118 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4); 119 120 /* pci_wqe_byte_count 121 * Size of i-th scatter/gather entry, 0 if entry is unused. 122 */ 123 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false); 124 125 /* pci_wqe_address 126 * Physical address of i-th scatter/gather entry. 127 * Gather Entries must be 2Byte aligned. 128 */ 129 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false); 130 131 enum mlxsw_pci_cqe_v { 132 MLXSW_PCI_CQE_V0, 133 MLXSW_PCI_CQE_V1, 134 MLXSW_PCI_CQE_V2, 135 }; 136 137 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \ 138 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \ 139 { \ 140 switch (v) { \ 141 default: \ 142 case MLXSW_PCI_CQE_V0: \ 143 return mlxsw_pci_cqe##v0##_##name##_get(cqe); \ 144 case MLXSW_PCI_CQE_V1: \ 145 return mlxsw_pci_cqe##v1##_##name##_get(cqe); \ 146 case MLXSW_PCI_CQE_V2: \ 147 return mlxsw_pci_cqe##v2##_##name##_get(cqe); \ 148 } \ 149 } \ 150 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \ 151 char *cqe, u32 val) \ 152 { \ 153 switch (v) { \ 154 default: \ 155 case MLXSW_PCI_CQE_V0: \ 156 mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \ 157 break; \ 158 case MLXSW_PCI_CQE_V1: \ 159 mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \ 160 break; \ 161 case MLXSW_PCI_CQE_V2: \ 162 mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \ 163 break; \ 164 } \ 165 } 166 167 /* pci_cqe_lag 168 * Packet arrives from a port which is a LAG 169 */ 170 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1); 171 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1); 172 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12); 173 174 /* pci_cqe_system_port/lag_id 175 * When lag=0: System port on which the packet was received 176 * When lag=1: 177 * bits [15:4] LAG ID on which the packet was received 178 * bits [3:0] sub_port on which the packet was received 179 */ 180 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16); 181 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12); 182 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16); 183 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12); 184 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4); 185 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8); 186 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12); 187 188 /* pci_cqe_wqe_counter 189 * WQE count of the WQEs completed on the associated dqn 190 */ 191 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16); 192 193 /* pci_cqe_byte_count 194 * Byte count of received packets including additional two 195 * Reserved Bytes that are append to the end of the frame. 196 * Reserved for Send CQE. 197 */ 198 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14); 199 200 /* pci_cqe_trap_id 201 * Trap ID that captured the packet. 202 */ 203 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9); 204 205 /* pci_cqe_crc 206 * Length include CRC. Indicates the length field includes 207 * the packet's CRC. 208 */ 209 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1); 210 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1); 211 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12); 212 213 /* pci_cqe_e 214 * CQE with Error. 215 */ 216 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1); 217 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1); 218 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12); 219 220 /* pci_cqe_sr 221 * 1 - Send Queue 222 * 0 - Receive Queue 223 */ 224 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1); 225 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1); 226 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12); 227 228 /* pci_cqe_dqn 229 * Descriptor Queue (DQ) Number. 230 */ 231 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5); 232 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6); 233 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12); 234 235 /* pci_cqe_owner 236 * Ownership bit. 237 */ 238 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1); 239 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1); 240 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2); 241 242 /* pci_eqe_event_type 243 * Event type. 244 */ 245 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8); 246 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00 247 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A 248 249 /* pci_eqe_event_sub_type 250 * Event type. 251 */ 252 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8); 253 254 /* pci_eqe_cqn 255 * Completion Queue that triggeret this EQE. 256 */ 257 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7); 258 259 /* pci_eqe_owner 260 * Ownership bit. 261 */ 262 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1); 263 264 /* pci_eqe_cmd_token 265 * Command completion event - token 266 */ 267 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16); 268 269 /* pci_eqe_cmd_status 270 * Command completion event - status 271 */ 272 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8); 273 274 /* pci_eqe_cmd_out_param_h 275 * Command completion event - output parameter - higher part 276 */ 277 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32); 278 279 /* pci_eqe_cmd_out_param_l 280 * Command completion event - output parameter - lower part 281 */ 282 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32); 283 284 #endif 285