1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_PCI_HW_H 5 #define _MLXSW_PCI_HW_H 6 7 #include <linux/bitops.h> 8 9 #include "item.h" 10 11 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */ 12 #define MLXSW_PCI_PAGE_SIZE 4096 13 14 #define MLXSW_PCI_CIR_BASE 0x71000 15 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE 16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04) 17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08) 18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C) 19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10) 20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14) 21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18) 22 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23) 23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22) 24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12 25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24 26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000 27 28 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 900000 29 #define MLXSW_PCI_SW_RESET_WAIT_MSECS 200 30 #define MLXSW_PCI_FW_READY 0xA1844 31 #define MLXSW_PCI_FW_READY_MASK 0xFFFF 32 #define MLXSW_PCI_FW_READY_MAGIC 0x5E 33 34 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000 35 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200 36 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400 37 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600 38 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800 39 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00 40 41 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \ 42 ((offset) + (type_offset) + (num) * 4) 43 44 #define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset) (offset) 45 #define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset) ((offset) + 4) 46 47 #define MLXSW_PCI_CQS_MAX 96 48 #define MLXSW_PCI_EQS_COUNT 2 49 #define MLXSW_PCI_EQ_ASYNC_NUM 0 50 #define MLXSW_PCI_EQ_COMP_NUM 1 51 52 #define MLXSW_PCI_SDQS_MIN 2 /* EMAD and control traffic */ 53 #define MLXSW_PCI_SDQ_EMAD_INDEX 0 54 #define MLXSW_PCI_SDQ_EMAD_TC 0 55 #define MLXSW_PCI_SDQ_CTL_TC 3 56 57 #define MLXSW_PCI_AQ_PAGES 8 58 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES) 59 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */ 60 #define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */ 61 #define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */ 62 #define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE 63 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */ 64 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE) 65 #define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE) 66 #define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE) 67 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE) 68 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80 69 70 #define MLXSW_PCI_WQE_SG_ENTRIES 3 71 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA 72 73 /* pci_wqe_c 74 * If set it indicates that a completion should be reported upon 75 * execution of this descriptor. 76 */ 77 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1); 78 79 /* pci_wqe_lp 80 * Local Processing, set if packet should be processed by the local 81 * switch hardware: 82 * For Ethernet EMAD (Direct Route and non Direct Route) - 83 * must be set if packet destination is local device 84 * For InfiniBand CTL - must be set if packet destination is local device 85 * Otherwise it must be clear 86 * Local Process packets must not exceed the size of 2K (including payload 87 * and headers). 88 */ 89 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1); 90 91 /* pci_wqe_type 92 * Packet type. 93 */ 94 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4); 95 96 /* pci_wqe_byte_count 97 * Size of i-th scatter/gather entry, 0 if entry is unused. 98 */ 99 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false); 100 101 /* pci_wqe_address 102 * Physical address of i-th scatter/gather entry. 103 * Gather Entries must be 2Byte aligned. 104 */ 105 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false); 106 107 enum mlxsw_pci_cqe_v { 108 MLXSW_PCI_CQE_V0, 109 MLXSW_PCI_CQE_V1, 110 MLXSW_PCI_CQE_V2, 111 }; 112 113 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \ 114 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \ 115 { \ 116 switch (v) { \ 117 default: \ 118 case MLXSW_PCI_CQE_V0: \ 119 return mlxsw_pci_cqe##v0##_##name##_get(cqe); \ 120 case MLXSW_PCI_CQE_V1: \ 121 return mlxsw_pci_cqe##v1##_##name##_get(cqe); \ 122 case MLXSW_PCI_CQE_V2: \ 123 return mlxsw_pci_cqe##v2##_##name##_get(cqe); \ 124 } \ 125 } \ 126 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \ 127 char *cqe, u32 val) \ 128 { \ 129 switch (v) { \ 130 default: \ 131 case MLXSW_PCI_CQE_V0: \ 132 mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \ 133 break; \ 134 case MLXSW_PCI_CQE_V1: \ 135 mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \ 136 break; \ 137 case MLXSW_PCI_CQE_V2: \ 138 mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \ 139 break; \ 140 } \ 141 } 142 143 /* pci_cqe_lag 144 * Packet arrives from a port which is a LAG 145 */ 146 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1); 147 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1); 148 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12); 149 150 /* pci_cqe_system_port/lag_id 151 * When lag=0: System port on which the packet was received 152 * When lag=1: 153 * bits [15:4] LAG ID on which the packet was received 154 * bits [3:0] sub_port on which the packet was received 155 */ 156 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16); 157 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12); 158 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16); 159 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12); 160 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4); 161 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8); 162 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12); 163 164 /* pci_cqe_wqe_counter 165 * WQE count of the WQEs completed on the associated dqn 166 */ 167 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16); 168 169 /* pci_cqe_byte_count 170 * Byte count of received packets including additional two 171 * Reserved Bytes that are append to the end of the frame. 172 * Reserved for Send CQE. 173 */ 174 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14); 175 176 /* pci_cqe_trap_id 177 * Trap ID that captured the packet. 178 */ 179 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10); 180 181 /* pci_cqe_crc 182 * Length include CRC. Indicates the length field includes 183 * the packet's CRC. 184 */ 185 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1); 186 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1); 187 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12); 188 189 /* pci_cqe_e 190 * CQE with Error. 191 */ 192 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1); 193 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1); 194 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12); 195 196 /* pci_cqe_sr 197 * 1 - Send Queue 198 * 0 - Receive Queue 199 */ 200 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1); 201 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1); 202 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12); 203 204 /* pci_cqe_dqn 205 * Descriptor Queue (DQ) Number. 206 */ 207 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5); 208 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6); 209 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12); 210 211 /* pci_cqe_user_def_val_orig_pkt_len 212 * When trap_id is an ACL: User defined value from policy engine action. 213 */ 214 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20); 215 216 /* pci_cqe_mirror_reason 217 * Mirror reason. 218 */ 219 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8); 220 221 /* pci_cqe_owner 222 * Ownership bit. 223 */ 224 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1); 225 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1); 226 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2); 227 228 /* pci_eqe_event_type 229 * Event type. 230 */ 231 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8); 232 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00 233 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A 234 235 /* pci_eqe_event_sub_type 236 * Event type. 237 */ 238 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8); 239 240 /* pci_eqe_cqn 241 * Completion Queue that triggered this EQE. 242 */ 243 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7); 244 245 /* pci_eqe_owner 246 * Ownership bit. 247 */ 248 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1); 249 250 /* pci_eqe_cmd_token 251 * Command completion event - token 252 */ 253 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16); 254 255 /* pci_eqe_cmd_status 256 * Command completion event - status 257 */ 258 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8); 259 260 /* pci_eqe_cmd_out_param_h 261 * Command completion event - output parameter - higher part 262 */ 263 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32); 264 265 /* pci_eqe_cmd_out_param_l 266 * Command completion event - output parameter - lower part 267 */ 268 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32); 269 270 #endif 271