1 /*
2  * drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
3  * Copyright (c) 2015-2016 Mellanox Technologies. All rights reserved.
4  * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the names of the copyright holders nor the names of its
15  *    contributors may be used to endorse or promote products derived from
16  *    this software without specific prior written permission.
17  *
18  * Alternatively, this software may be distributed under the terms of the
19  * GNU General Public License ("GPL") version 2 as published by the Free
20  * Software Foundation.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  * POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef _MLXSW_PCI_HW_H
36 #define _MLXSW_PCI_HW_H
37 
38 #include <linux/bitops.h>
39 
40 #include "item.h"
41 
42 #define MLXSW_PCI_BAR0_SIZE		(1024 * 1024) /* 1MB */
43 #define MLXSW_PCI_PAGE_SIZE		4096
44 
45 #define MLXSW_PCI_CIR_BASE			0x71000
46 #define MLXSW_PCI_CIR_IN_PARAM_HI		MLXSW_PCI_CIR_BASE
47 #define MLXSW_PCI_CIR_IN_PARAM_LO		(MLXSW_PCI_CIR_BASE + 0x04)
48 #define MLXSW_PCI_CIR_IN_MODIFIER		(MLXSW_PCI_CIR_BASE + 0x08)
49 #define MLXSW_PCI_CIR_OUT_PARAM_HI		(MLXSW_PCI_CIR_BASE + 0x0C)
50 #define MLXSW_PCI_CIR_OUT_PARAM_LO		(MLXSW_PCI_CIR_BASE + 0x10)
51 #define MLXSW_PCI_CIR_TOKEN			(MLXSW_PCI_CIR_BASE + 0x14)
52 #define MLXSW_PCI_CIR_CTRL			(MLXSW_PCI_CIR_BASE + 0x18)
53 #define MLXSW_PCI_CIR_CTRL_GO_BIT		BIT(23)
54 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT		BIT(22)
55 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT	12
56 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT		24
57 #define MLXSW_PCI_CIR_TIMEOUT_MSECS		1000
58 
59 #define MLXSW_PCI_SW_RESET			0xF0010
60 #define MLXSW_PCI_SW_RESET_RST_BIT		BIT(0)
61 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS	5000
62 #define MLXSW_PCI_FW_READY			0xA1844
63 #define MLXSW_PCI_FW_READY_MASK			0xFFFF
64 #define MLXSW_PCI_FW_READY_MAGIC		0x5E
65 
66 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET		0x000
67 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET		0x200
68 #define MLXSW_PCI_DOORBELL_CQ_OFFSET		0x400
69 #define MLXSW_PCI_DOORBELL_EQ_OFFSET		0x600
70 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET	0x800
71 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET	0xA00
72 
73 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)	\
74 	((offset) + (type_offset) + (num) * 4)
75 
76 #define MLXSW_PCI_CQS_MAX	96
77 #define MLXSW_PCI_EQS_COUNT	2
78 #define MLXSW_PCI_EQ_ASYNC_NUM	0
79 #define MLXSW_PCI_EQ_COMP_NUM	1
80 
81 #define MLXSW_PCI_AQ_PAGES	8
82 #define MLXSW_PCI_AQ_SIZE	(MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
83 #define MLXSW_PCI_WQE_SIZE	32 /* 32 bytes per element */
84 #define MLXSW_PCI_CQE_SIZE	16 /* 16 bytes per element */
85 #define MLXSW_PCI_EQE_SIZE	16 /* 16 bytes per element */
86 #define MLXSW_PCI_WQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
87 #define MLXSW_PCI_CQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE_SIZE)
88 #define MLXSW_PCI_EQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
89 #define MLXSW_PCI_EQE_UPDATE_COUNT	0x80
90 
91 #define MLXSW_PCI_WQE_SG_ENTRIES	3
92 #define MLXSW_PCI_WQE_TYPE_ETHERNET	0xA
93 
94 /* pci_wqe_c
95  * If set it indicates that a completion should be reported upon
96  * execution of this descriptor.
97  */
98 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
99 
100 /* pci_wqe_lp
101  * Local Processing, set if packet should be processed by the local
102  * switch hardware:
103  * For Ethernet EMAD (Direct Route and non Direct Route) -
104  * must be set if packet destination is local device
105  * For InfiniBand CTL - must be set if packet destination is local device
106  * Otherwise it must be clear
107  * Local Process packets must not exceed the size of 2K (including payload
108  * and headers).
109  */
110 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
111 
112 /* pci_wqe_type
113  * Packet type.
114  */
115 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
116 
117 /* pci_wqe_byte_count
118  * Size of i-th scatter/gather entry, 0 if entry is unused.
119  */
120 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
121 
122 /* pci_wqe_address
123  * Physical address of i-th scatter/gather entry.
124  * Gather Entries must be 2Byte aligned.
125  */
126 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
127 
128 /* pci_cqe_lag
129  * Packet arrives from a port which is a LAG
130  */
131 MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1);
132 
133 /* pci_cqe_system_port/lag_id
134  * When lag=0: System port on which the packet was received
135  * When lag=1:
136  * bits [15:4] LAG ID on which the packet was received
137  * bits [3:0] sub_port on which the packet was received
138  */
139 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
140 MLXSW_ITEM32(pci, cqe, lag_id, 0x00, 4, 12);
141 MLXSW_ITEM32(pci, cqe, lag_port_index, 0x00, 0, 4);
142 
143 /* pci_cqe_wqe_counter
144  * WQE count of the WQEs completed on the associated dqn
145  */
146 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
147 
148 /* pci_cqe_byte_count
149  * Byte count of received packets including additional two
150  * Reserved Bytes that are append to the end of the frame.
151  * Reserved for Send CQE.
152  */
153 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
154 
155 /* pci_cqe_trap_id
156  * Trap ID that captured the packet.
157  */
158 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
159 
160 /* pci_cqe_crc
161  * Length include CRC. Indicates the length field includes
162  * the packet's CRC.
163  */
164 MLXSW_ITEM32(pci, cqe, crc, 0x0C, 8, 1);
165 
166 /* pci_cqe_e
167  * CQE with Error.
168  */
169 MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1);
170 
171 /* pci_cqe_sr
172  * 1 - Send Queue
173  * 0 - Receive Queue
174  */
175 MLXSW_ITEM32(pci, cqe, sr, 0x0C, 6, 1);
176 
177 /* pci_cqe_dqn
178  * Descriptor Queue (DQ) Number.
179  */
180 MLXSW_ITEM32(pci, cqe, dqn, 0x0C, 1, 5);
181 
182 /* pci_cqe_owner
183  * Ownership bit.
184  */
185 MLXSW_ITEM32(pci, cqe, owner, 0x0C, 0, 1);
186 
187 /* pci_eqe_event_type
188  * Event type.
189  */
190 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
191 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP	0x00
192 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD	0x0A
193 
194 /* pci_eqe_event_sub_type
195  * Event type.
196  */
197 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
198 
199 /* pci_eqe_cqn
200  * Completion Queue that triggeret this EQE.
201  */
202 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
203 
204 /* pci_eqe_owner
205  * Ownership bit.
206  */
207 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
208 
209 /* pci_eqe_cmd_token
210  * Command completion event - token
211  */
212 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
213 
214 /* pci_eqe_cmd_status
215  * Command completion event - status
216  */
217 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
218 
219 /* pci_eqe_cmd_out_param_h
220  * Command completion event - output parameter - higher part
221  */
222 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
223 
224 /* pci_eqe_cmd_out_param_l
225  * Command completion event - output parameter - lower part
226  */
227 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
228 
229 #endif
230