1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_PCI_HW_H 5 #define _MLXSW_PCI_HW_H 6 7 #include <linux/bitops.h> 8 9 #include "item.h" 10 11 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */ 12 #define MLXSW_PCI_PAGE_SIZE 4096 13 14 #define MLXSW_PCI_CIR_BASE 0x71000 15 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE 16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04) 17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08) 18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C) 19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10) 20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14) 21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18) 22 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23) 23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22) 24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12 25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24 26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000 27 28 #define MLXSW_PCI_SW_RESET 0xF0010 29 #define MLXSW_PCI_SW_RESET_RST_BIT BIT(0) 30 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 20000 31 #define MLXSW_PCI_SW_RESET_WAIT_MSECS 100 32 #define MLXSW_PCI_FW_READY 0xA1844 33 #define MLXSW_PCI_FW_READY_MASK 0xFFFF 34 #define MLXSW_PCI_FW_READY_MAGIC 0x5E 35 36 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000 37 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200 38 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400 39 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600 40 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800 41 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00 42 43 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \ 44 ((offset) + (type_offset) + (num) * 4) 45 46 #define MLXSW_PCI_CQS_MAX 96 47 #define MLXSW_PCI_EQS_COUNT 2 48 #define MLXSW_PCI_EQ_ASYNC_NUM 0 49 #define MLXSW_PCI_EQ_COMP_NUM 1 50 51 #define MLXSW_PCI_AQ_PAGES 8 52 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES) 53 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */ 54 #define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */ 55 #define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */ 56 #define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE 57 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */ 58 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE) 59 #define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE) 60 #define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE) 61 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE) 62 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80 63 64 #define MLXSW_PCI_WQE_SG_ENTRIES 3 65 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA 66 67 /* pci_wqe_c 68 * If set it indicates that a completion should be reported upon 69 * execution of this descriptor. 70 */ 71 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1); 72 73 /* pci_wqe_lp 74 * Local Processing, set if packet should be processed by the local 75 * switch hardware: 76 * For Ethernet EMAD (Direct Route and non Direct Route) - 77 * must be set if packet destination is local device 78 * For InfiniBand CTL - must be set if packet destination is local device 79 * Otherwise it must be clear 80 * Local Process packets must not exceed the size of 2K (including payload 81 * and headers). 82 */ 83 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1); 84 85 /* pci_wqe_type 86 * Packet type. 87 */ 88 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4); 89 90 /* pci_wqe_byte_count 91 * Size of i-th scatter/gather entry, 0 if entry is unused. 92 */ 93 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false); 94 95 /* pci_wqe_address 96 * Physical address of i-th scatter/gather entry. 97 * Gather Entries must be 2Byte aligned. 98 */ 99 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false); 100 101 enum mlxsw_pci_cqe_v { 102 MLXSW_PCI_CQE_V0, 103 MLXSW_PCI_CQE_V1, 104 MLXSW_PCI_CQE_V2, 105 }; 106 107 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \ 108 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \ 109 { \ 110 switch (v) { \ 111 default: \ 112 case MLXSW_PCI_CQE_V0: \ 113 return mlxsw_pci_cqe##v0##_##name##_get(cqe); \ 114 case MLXSW_PCI_CQE_V1: \ 115 return mlxsw_pci_cqe##v1##_##name##_get(cqe); \ 116 case MLXSW_PCI_CQE_V2: \ 117 return mlxsw_pci_cqe##v2##_##name##_get(cqe); \ 118 } \ 119 } \ 120 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \ 121 char *cqe, u32 val) \ 122 { \ 123 switch (v) { \ 124 default: \ 125 case MLXSW_PCI_CQE_V0: \ 126 mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \ 127 break; \ 128 case MLXSW_PCI_CQE_V1: \ 129 mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \ 130 break; \ 131 case MLXSW_PCI_CQE_V2: \ 132 mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \ 133 break; \ 134 } \ 135 } 136 137 /* pci_cqe_lag 138 * Packet arrives from a port which is a LAG 139 */ 140 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1); 141 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1); 142 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12); 143 144 /* pci_cqe_system_port/lag_id 145 * When lag=0: System port on which the packet was received 146 * When lag=1: 147 * bits [15:4] LAG ID on which the packet was received 148 * bits [3:0] sub_port on which the packet was received 149 */ 150 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16); 151 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12); 152 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16); 153 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12); 154 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4); 155 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8); 156 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12); 157 158 /* pci_cqe_wqe_counter 159 * WQE count of the WQEs completed on the associated dqn 160 */ 161 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16); 162 163 /* pci_cqe_byte_count 164 * Byte count of received packets including additional two 165 * Reserved Bytes that are append to the end of the frame. 166 * Reserved for Send CQE. 167 */ 168 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14); 169 170 /* pci_cqe_trap_id 171 * Trap ID that captured the packet. 172 */ 173 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9); 174 175 /* pci_cqe_crc 176 * Length include CRC. Indicates the length field includes 177 * the packet's CRC. 178 */ 179 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1); 180 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1); 181 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12); 182 183 /* pci_cqe_e 184 * CQE with Error. 185 */ 186 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1); 187 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1); 188 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12); 189 190 /* pci_cqe_sr 191 * 1 - Send Queue 192 * 0 - Receive Queue 193 */ 194 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1); 195 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1); 196 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12); 197 198 /* pci_cqe_dqn 199 * Descriptor Queue (DQ) Number. 200 */ 201 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5); 202 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6); 203 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12); 204 205 /* pci_cqe_owner 206 * Ownership bit. 207 */ 208 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1); 209 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1); 210 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2); 211 212 /* pci_eqe_event_type 213 * Event type. 214 */ 215 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8); 216 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00 217 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A 218 219 /* pci_eqe_event_sub_type 220 * Event type. 221 */ 222 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8); 223 224 /* pci_eqe_cqn 225 * Completion Queue that triggered this EQE. 226 */ 227 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7); 228 229 /* pci_eqe_owner 230 * Ownership bit. 231 */ 232 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1); 233 234 /* pci_eqe_cmd_token 235 * Command completion event - token 236 */ 237 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16); 238 239 /* pci_eqe_cmd_status 240 * Command completion event - status 241 */ 242 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8); 243 244 /* pci_eqe_cmd_out_param_h 245 * Command completion event - output parameter - higher part 246 */ 247 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32); 248 249 /* pci_eqe_cmd_out_param_l 250 * Command completion event - output parameter - lower part 251 */ 252 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32); 253 254 #endif 255