1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/pci.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the names of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") version 2 as published by the Free 20 * Software Foundation. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _MLXSW_PCI_H 36 #define _MLXSW_PCI_H 37 38 #include <linux/bitops.h> 39 40 #include "item.h" 41 42 #define PCI_DEVICE_ID_MELLANOX_SWITCHX2 0xc738 43 #define PCI_DEVICE_ID_MELLANOX_SPECTRUM 0xcb84 44 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */ 45 #define MLXSW_PCI_PAGE_SIZE 4096 46 47 #define MLXSW_PCI_CIR_BASE 0x71000 48 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE 49 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04) 50 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08) 51 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C) 52 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10) 53 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14) 54 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18) 55 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23) 56 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22) 57 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12 58 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24 59 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000 60 61 #define MLXSW_PCI_SW_RESET 0xF0010 62 #define MLXSW_PCI_SW_RESET_RST_BIT BIT(0) 63 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 5000 64 65 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000 66 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200 67 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400 68 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600 69 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800 70 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00 71 72 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \ 73 ((offset) + (type_offset) + (num) * 4) 74 75 #define MLXSW_PCI_CQS_MAX 96 76 #define MLXSW_PCI_EQS_COUNT 2 77 #define MLXSW_PCI_EQ_ASYNC_NUM 0 78 #define MLXSW_PCI_EQ_COMP_NUM 1 79 80 #define MLXSW_PCI_AQ_PAGES 8 81 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES) 82 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */ 83 #define MLXSW_PCI_CQE_SIZE 16 /* 16 bytes per element */ 84 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */ 85 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE) 86 #define MLXSW_PCI_CQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE_SIZE) 87 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE) 88 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80 89 90 #define MLXSW_PCI_WQE_SG_ENTRIES 3 91 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA 92 93 /* pci_wqe_c 94 * If set it indicates that a completion should be reported upon 95 * execution of this descriptor. 96 */ 97 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1); 98 99 /* pci_wqe_lp 100 * Local Processing, set if packet should be processed by the local 101 * switch hardware: 102 * For Ethernet EMAD (Direct Route and non Direct Route) - 103 * must be set if packet destination is local device 104 * For InfiniBand CTL - must be set if packet destination is local device 105 * Otherwise it must be clear 106 * Local Process packets must not exceed the size of 2K (including payload 107 * and headers). 108 */ 109 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1); 110 111 /* pci_wqe_type 112 * Packet type. 113 */ 114 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4); 115 116 /* pci_wqe_byte_count 117 * Size of i-th scatter/gather entry, 0 if entry is unused. 118 */ 119 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false); 120 121 /* pci_wqe_address 122 * Physical address of i-th scatter/gather entry. 123 * Gather Entries must be 2Byte aligned. 124 */ 125 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false); 126 127 /* pci_cqe_lag 128 * Packet arrives from a port which is a LAG 129 */ 130 MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1); 131 132 /* pci_cqe_system_port 133 * When lag=0: System port on which the packet was received 134 * When lag=1: 135 * bits [15:4] LAG ID on which the packet was received 136 * bits [3:0] sub_port on which the packet was received 137 */ 138 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16); 139 140 /* pci_cqe_wqe_counter 141 * WQE count of the WQEs completed on the associated dqn 142 */ 143 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16); 144 145 /* pci_cqe_byte_count 146 * Byte count of received packets including additional two 147 * Reserved Bytes that are append to the end of the frame. 148 * Reserved for Send CQE. 149 */ 150 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14); 151 152 /* pci_cqe_trap_id 153 * Trap ID that captured the packet. 154 */ 155 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8); 156 157 /* pci_cqe_crc 158 * Length include CRC. Indicates the length field includes 159 * the packet's CRC. 160 */ 161 MLXSW_ITEM32(pci, cqe, crc, 0x0C, 8, 1); 162 163 /* pci_cqe_e 164 * CQE with Error. 165 */ 166 MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1); 167 168 /* pci_cqe_sr 169 * 1 - Send Queue 170 * 0 - Receive Queue 171 */ 172 MLXSW_ITEM32(pci, cqe, sr, 0x0C, 6, 1); 173 174 /* pci_cqe_dqn 175 * Descriptor Queue (DQ) Number. 176 */ 177 MLXSW_ITEM32(pci, cqe, dqn, 0x0C, 1, 5); 178 179 /* pci_cqe_owner 180 * Ownership bit. 181 */ 182 MLXSW_ITEM32(pci, cqe, owner, 0x0C, 0, 1); 183 184 /* pci_eqe_event_type 185 * Event type. 186 */ 187 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8); 188 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00 189 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A 190 191 /* pci_eqe_event_sub_type 192 * Event type. 193 */ 194 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8); 195 196 /* pci_eqe_cqn 197 * Completion Queue that triggeret this EQE. 198 */ 199 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7); 200 201 /* pci_eqe_owner 202 * Ownership bit. 203 */ 204 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1); 205 206 /* pci_eqe_cmd_token 207 * Command completion event - token 208 */ 209 MLXSW_ITEM32(pci, eqe, cmd_token, 0x08, 16, 16); 210 211 /* pci_eqe_cmd_status 212 * Command completion event - status 213 */ 214 MLXSW_ITEM32(pci, eqe, cmd_status, 0x08, 0, 8); 215 216 /* pci_eqe_cmd_out_param_h 217 * Command completion event - output parameter - higher part 218 */ 219 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x0C, 0, 32); 220 221 /* pci_eqe_cmd_out_param_l 222 * Command completion event - output parameter - lower part 223 */ 224 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x10, 0, 32); 225 226 #endif 227