1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/export.h>
7 #include <linux/err.h>
8 #include <linux/device.h>
9 #include <linux/pci.h>
10 #include <linux/interrupt.h>
11 #include <linux/wait.h>
12 #include <linux/types.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/log2.h>
16 #include <linux/string.h>
17 
18 #include "pci_hw.h"
19 #include "pci.h"
20 #include "core.h"
21 #include "cmd.h"
22 #include "port.h"
23 #include "resources.h"
24 
25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
26 	iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
27 #define mlxsw_pci_read32(mlxsw_pci, reg) \
28 	ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
29 
30 enum mlxsw_pci_queue_type {
31 	MLXSW_PCI_QUEUE_TYPE_SDQ,
32 	MLXSW_PCI_QUEUE_TYPE_RDQ,
33 	MLXSW_PCI_QUEUE_TYPE_CQ,
34 	MLXSW_PCI_QUEUE_TYPE_EQ,
35 };
36 
37 #define MLXSW_PCI_QUEUE_TYPE_COUNT	4
38 
39 static const u16 mlxsw_pci_doorbell_type_offset[] = {
40 	MLXSW_PCI_DOORBELL_SDQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
41 	MLXSW_PCI_DOORBELL_RDQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
42 	MLXSW_PCI_DOORBELL_CQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_CQ */
43 	MLXSW_PCI_DOORBELL_EQ_OFFSET,	/* for type MLXSW_PCI_QUEUE_TYPE_EQ */
44 };
45 
46 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
47 	0, /* unused */
48 	0, /* unused */
49 	MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
50 	MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
51 };
52 
53 struct mlxsw_pci_mem_item {
54 	char *buf;
55 	dma_addr_t mapaddr;
56 	size_t size;
57 };
58 
59 struct mlxsw_pci_queue_elem_info {
60 	char *elem; /* pointer to actual dma mapped element mem chunk */
61 	union {
62 		struct {
63 			struct sk_buff *skb;
64 		} sdq;
65 		struct {
66 			struct sk_buff *skb;
67 		} rdq;
68 	} u;
69 };
70 
71 struct mlxsw_pci_queue {
72 	spinlock_t lock; /* for queue accesses */
73 	struct mlxsw_pci_mem_item mem_item;
74 	struct mlxsw_pci_queue_elem_info *elem_info;
75 	u16 producer_counter;
76 	u16 consumer_counter;
77 	u16 count; /* number of elements in queue */
78 	u8 num; /* queue number */
79 	u8 elem_size; /* size of one element */
80 	enum mlxsw_pci_queue_type type;
81 	struct tasklet_struct tasklet; /* queue processing tasklet */
82 	struct mlxsw_pci *pci;
83 	union {
84 		struct {
85 			u32 comp_sdq_count;
86 			u32 comp_rdq_count;
87 			enum mlxsw_pci_cqe_v v;
88 		} cq;
89 		struct {
90 			u32 ev_cmd_count;
91 			u32 ev_comp_count;
92 			u32 ev_other_count;
93 		} eq;
94 	} u;
95 };
96 
97 struct mlxsw_pci_queue_type_group {
98 	struct mlxsw_pci_queue *q;
99 	u8 count; /* number of queues in group */
100 };
101 
102 struct mlxsw_pci {
103 	struct pci_dev *pdev;
104 	u8 __iomem *hw_addr;
105 	u64 free_running_clock_offset;
106 	struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
107 	u32 doorbell_offset;
108 	struct mlxsw_core *core;
109 	struct {
110 		struct mlxsw_pci_mem_item *items;
111 		unsigned int count;
112 	} fw_area;
113 	struct {
114 		struct mlxsw_pci_mem_item out_mbox;
115 		struct mlxsw_pci_mem_item in_mbox;
116 		struct mutex lock; /* Lock access to command registers */
117 		bool nopoll;
118 		wait_queue_head_t wait;
119 		bool wait_done;
120 		struct {
121 			u8 status;
122 			u64 out_param;
123 		} comp;
124 	} cmd;
125 	struct mlxsw_bus_info bus_info;
126 	const struct pci_device_id *id;
127 	enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */
128 	u8 num_sdq_cqs; /* Number of CQs used for SDQs */
129 };
130 
131 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
132 {
133 	tasklet_schedule(&q->tasklet);
134 }
135 
136 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
137 					size_t elem_size, int elem_index)
138 {
139 	return q->mem_item.buf + (elem_size * elem_index);
140 }
141 
142 static struct mlxsw_pci_queue_elem_info *
143 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
144 {
145 	return &q->elem_info[elem_index];
146 }
147 
148 static struct mlxsw_pci_queue_elem_info *
149 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
150 {
151 	int index = q->producer_counter & (q->count - 1);
152 
153 	if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
154 		return NULL;
155 	return mlxsw_pci_queue_elem_info_get(q, index);
156 }
157 
158 static struct mlxsw_pci_queue_elem_info *
159 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
160 {
161 	int index = q->consumer_counter & (q->count - 1);
162 
163 	return mlxsw_pci_queue_elem_info_get(q, index);
164 }
165 
166 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
167 {
168 	return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
169 }
170 
171 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
172 {
173 	return owner_bit != !!(q->consumer_counter & q->count);
174 }
175 
176 static struct mlxsw_pci_queue_type_group *
177 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
178 			       enum mlxsw_pci_queue_type q_type)
179 {
180 	return &mlxsw_pci->queues[q_type];
181 }
182 
183 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
184 				  enum mlxsw_pci_queue_type q_type)
185 {
186 	struct mlxsw_pci_queue_type_group *queue_group;
187 
188 	queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
189 	return queue_group->count;
190 }
191 
192 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
193 {
194 	return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
195 }
196 
197 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
198 {
199 	return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
200 }
201 
202 static struct mlxsw_pci_queue *
203 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
204 		      enum mlxsw_pci_queue_type q_type, u8 q_num)
205 {
206 	return &mlxsw_pci->queues[q_type].q[q_num];
207 }
208 
209 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
210 						 u8 q_num)
211 {
212 	return __mlxsw_pci_queue_get(mlxsw_pci,
213 				     MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
214 }
215 
216 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
217 						 u8 q_num)
218 {
219 	return __mlxsw_pci_queue_get(mlxsw_pci,
220 				     MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
221 }
222 
223 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
224 						u8 q_num)
225 {
226 	return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
227 }
228 
229 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
230 						u8 q_num)
231 {
232 	return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
233 }
234 
235 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
236 					   struct mlxsw_pci_queue *q,
237 					   u16 val)
238 {
239 	mlxsw_pci_write32(mlxsw_pci,
240 			  DOORBELL(mlxsw_pci->doorbell_offset,
241 				   mlxsw_pci_doorbell_type_offset[q->type],
242 				   q->num), val);
243 }
244 
245 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
246 					       struct mlxsw_pci_queue *q,
247 					       u16 val)
248 {
249 	mlxsw_pci_write32(mlxsw_pci,
250 			  DOORBELL(mlxsw_pci->doorbell_offset,
251 				   mlxsw_pci_doorbell_arm_type_offset[q->type],
252 				   q->num), val);
253 }
254 
255 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
256 						   struct mlxsw_pci_queue *q)
257 {
258 	wmb(); /* ensure all writes are done before we ring a bell */
259 	__mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
260 }
261 
262 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
263 						   struct mlxsw_pci_queue *q)
264 {
265 	wmb(); /* ensure all writes are done before we ring a bell */
266 	__mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
267 				       q->consumer_counter + q->count);
268 }
269 
270 static void
271 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
272 					   struct mlxsw_pci_queue *q)
273 {
274 	wmb(); /* ensure all writes are done before we ring a bell */
275 	__mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
276 }
277 
278 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
279 					     int page_index)
280 {
281 	return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
282 }
283 
284 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
285 			      struct mlxsw_pci_queue *q)
286 {
287 	int tclass;
288 	int i;
289 	int err;
290 
291 	q->producer_counter = 0;
292 	q->consumer_counter = 0;
293 	tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC :
294 						      MLXSW_PCI_SDQ_CTL_TC;
295 
296 	/* Set CQ of same number of this SDQ. */
297 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
298 	mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass);
299 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
300 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
301 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
302 
303 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
304 	}
305 
306 	err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
307 	if (err)
308 		return err;
309 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
310 	return 0;
311 }
312 
313 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
314 			       struct mlxsw_pci_queue *q)
315 {
316 	mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
317 }
318 
319 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
320 				  int index, char *frag_data, size_t frag_len,
321 				  int direction)
322 {
323 	struct pci_dev *pdev = mlxsw_pci->pdev;
324 	dma_addr_t mapaddr;
325 
326 	mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
327 	if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
328 		dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
329 		return -EIO;
330 	}
331 	mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
332 	mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
333 	return 0;
334 }
335 
336 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
337 				     int index, int direction)
338 {
339 	struct pci_dev *pdev = mlxsw_pci->pdev;
340 	size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
341 	dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
342 
343 	if (!frag_len)
344 		return;
345 	pci_unmap_single(pdev, mapaddr, frag_len, direction);
346 }
347 
348 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
349 				   struct mlxsw_pci_queue_elem_info *elem_info)
350 {
351 	size_t buf_len = MLXSW_PORT_MAX_MTU;
352 	char *wqe = elem_info->elem;
353 	struct sk_buff *skb;
354 	int err;
355 
356 	elem_info->u.rdq.skb = NULL;
357 	skb = netdev_alloc_skb_ip_align(NULL, buf_len);
358 	if (!skb)
359 		return -ENOMEM;
360 
361 	/* Assume that wqe was previously zeroed. */
362 
363 	err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
364 				     buf_len, DMA_FROM_DEVICE);
365 	if (err)
366 		goto err_frag_map;
367 
368 	elem_info->u.rdq.skb = skb;
369 	return 0;
370 
371 err_frag_map:
372 	dev_kfree_skb_any(skb);
373 	return err;
374 }
375 
376 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
377 				   struct mlxsw_pci_queue_elem_info *elem_info)
378 {
379 	struct sk_buff *skb;
380 	char *wqe;
381 
382 	skb = elem_info->u.rdq.skb;
383 	wqe = elem_info->elem;
384 
385 	mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
386 	dev_kfree_skb_any(skb);
387 }
388 
389 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
390 			      struct mlxsw_pci_queue *q)
391 {
392 	struct mlxsw_pci_queue_elem_info *elem_info;
393 	u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
394 	int i;
395 	int err;
396 
397 	q->producer_counter = 0;
398 	q->consumer_counter = 0;
399 
400 	/* Set CQ of same number of this RDQ with base
401 	 * above SDQ count as the lower ones are assigned to SDQs.
402 	 */
403 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
404 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
405 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
406 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
407 
408 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
409 	}
410 
411 	err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
412 	if (err)
413 		return err;
414 
415 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
416 
417 	for (i = 0; i < q->count; i++) {
418 		elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
419 		BUG_ON(!elem_info);
420 		err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
421 		if (err)
422 			goto rollback;
423 		/* Everything is set up, ring doorbell to pass elem to HW */
424 		q->producer_counter++;
425 		mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
426 	}
427 
428 	return 0;
429 
430 rollback:
431 	for (i--; i >= 0; i--) {
432 		elem_info = mlxsw_pci_queue_elem_info_get(q, i);
433 		mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
434 	}
435 	mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
436 
437 	return err;
438 }
439 
440 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
441 			       struct mlxsw_pci_queue *q)
442 {
443 	struct mlxsw_pci_queue_elem_info *elem_info;
444 	int i;
445 
446 	mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
447 	for (i = 0; i < q->count; i++) {
448 		elem_info = mlxsw_pci_queue_elem_info_get(q, i);
449 		mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
450 	}
451 }
452 
453 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
454 				  struct mlxsw_pci_queue *q)
455 {
456 	q->u.cq.v = mlxsw_pci->max_cqe_ver;
457 
458 	/* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */
459 	if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
460 	    q->num < mlxsw_pci->num_sdq_cqs)
461 		q->u.cq.v = MLXSW_PCI_CQE_V1;
462 }
463 
464 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
465 			     struct mlxsw_pci_queue *q)
466 {
467 	int i;
468 	int err;
469 
470 	q->consumer_counter = 0;
471 
472 	for (i = 0; i < q->count; i++) {
473 		char *elem = mlxsw_pci_queue_elem_get(q, i);
474 
475 		mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
476 	}
477 
478 	if (q->u.cq.v == MLXSW_PCI_CQE_V1)
479 		mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
480 				MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
481 	else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
482 		mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
483 				MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
484 
485 	mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
486 	mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
487 	mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
488 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
489 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
490 
491 		mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
492 	}
493 	err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
494 	if (err)
495 		return err;
496 	mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
497 	mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
498 	return 0;
499 }
500 
501 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
502 			      struct mlxsw_pci_queue *q)
503 {
504 	mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
505 }
506 
507 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
508 				     struct mlxsw_pci_queue *q,
509 				     u16 consumer_counter_limit,
510 				     char *cqe)
511 {
512 	struct pci_dev *pdev = mlxsw_pci->pdev;
513 	struct mlxsw_pci_queue_elem_info *elem_info;
514 	struct mlxsw_tx_info tx_info;
515 	char *wqe;
516 	struct sk_buff *skb;
517 	int i;
518 
519 	spin_lock(&q->lock);
520 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
521 	tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info;
522 	skb = elem_info->u.sdq.skb;
523 	wqe = elem_info->elem;
524 	for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
525 		mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
526 
527 	if (unlikely(!tx_info.is_emad &&
528 		     skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
529 		mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb,
530 					   tx_info.local_port);
531 		skb = NULL;
532 	}
533 
534 	if (skb)
535 		dev_kfree_skb_any(skb);
536 	elem_info->u.sdq.skb = NULL;
537 
538 	if (q->consumer_counter++ != consumer_counter_limit)
539 		dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
540 	spin_unlock(&q->lock);
541 }
542 
543 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
544 				     struct mlxsw_pci_queue *q,
545 				     u16 consumer_counter_limit,
546 				     enum mlxsw_pci_cqe_v cqe_v, char *cqe)
547 {
548 	struct pci_dev *pdev = mlxsw_pci->pdev;
549 	struct mlxsw_pci_queue_elem_info *elem_info;
550 	char *wqe;
551 	struct sk_buff *skb;
552 	struct mlxsw_rx_info rx_info;
553 	u16 byte_count;
554 	int err;
555 
556 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
557 	skb = elem_info->u.sdq.skb;
558 	if (!skb)
559 		return;
560 	wqe = elem_info->elem;
561 	mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
562 
563 	if (q->consumer_counter++ != consumer_counter_limit)
564 		dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
565 
566 	if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) {
567 		rx_info.is_lag = true;
568 		rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe);
569 		rx_info.lag_port_index =
570 			mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe);
571 	} else {
572 		rx_info.is_lag = false;
573 		rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
574 	}
575 
576 	rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
577 
578 	if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL ||
579 	    rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) {
580 		u32 cookie_index = 0;
581 
582 		if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2)
583 			cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe);
584 		mlxsw_skb_cb(skb)->cookie_index = cookie_index;
585 	}
586 
587 	byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
588 	if (mlxsw_pci_cqe_crc_get(cqe_v, cqe))
589 		byte_count -= ETH_FCS_LEN;
590 	skb_put(skb, byte_count);
591 	mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
592 
593 	memset(wqe, 0, q->elem_size);
594 	err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
595 	if (err)
596 		dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
597 	/* Everything is set up, ring doorbell to pass elem to HW */
598 	q->producer_counter++;
599 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
600 	return;
601 }
602 
603 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
604 {
605 	struct mlxsw_pci_queue_elem_info *elem_info;
606 	char *elem;
607 	bool owner_bit;
608 
609 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
610 	elem = elem_info->elem;
611 	owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
612 	if (mlxsw_pci_elem_hw_owned(q, owner_bit))
613 		return NULL;
614 	q->consumer_counter++;
615 	rmb(); /* make sure we read owned bit before the rest of elem */
616 	return elem;
617 }
618 
619 static void mlxsw_pci_cq_tasklet(unsigned long data)
620 {
621 	struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
622 	struct mlxsw_pci *mlxsw_pci = q->pci;
623 	char *cqe;
624 	int items = 0;
625 	int credits = q->count >> 1;
626 
627 	while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
628 		u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
629 		u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
630 		u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
631 		char ncqe[MLXSW_PCI_CQE_SIZE_MAX];
632 
633 		memcpy(ncqe, cqe, q->elem_size);
634 		mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
635 
636 		if (sendq) {
637 			struct mlxsw_pci_queue *sdq;
638 
639 			sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
640 			mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
641 						 wqe_counter, ncqe);
642 			q->u.cq.comp_sdq_count++;
643 		} else {
644 			struct mlxsw_pci_queue *rdq;
645 
646 			rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
647 			mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
648 						 wqe_counter, q->u.cq.v, ncqe);
649 			q->u.cq.comp_rdq_count++;
650 		}
651 		if (++items == credits)
652 			break;
653 	}
654 	if (items)
655 		mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
656 }
657 
658 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
659 {
660 	return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
661 					       MLXSW_PCI_CQE01_COUNT;
662 }
663 
664 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
665 {
666 	return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
667 					       MLXSW_PCI_CQE01_SIZE;
668 }
669 
670 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
671 			     struct mlxsw_pci_queue *q)
672 {
673 	int i;
674 	int err;
675 
676 	q->consumer_counter = 0;
677 
678 	for (i = 0; i < q->count; i++) {
679 		char *elem = mlxsw_pci_queue_elem_get(q, i);
680 
681 		mlxsw_pci_eqe_owner_set(elem, 1);
682 	}
683 
684 	mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
685 	mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
686 	mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
687 	for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
688 		dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
689 
690 		mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
691 	}
692 	err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
693 	if (err)
694 		return err;
695 	mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
696 	mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
697 	return 0;
698 }
699 
700 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
701 			      struct mlxsw_pci_queue *q)
702 {
703 	mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
704 }
705 
706 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
707 {
708 	mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
709 	mlxsw_pci->cmd.comp.out_param =
710 		((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
711 		mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
712 	mlxsw_pci->cmd.wait_done = true;
713 	wake_up(&mlxsw_pci->cmd.wait);
714 }
715 
716 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
717 {
718 	struct mlxsw_pci_queue_elem_info *elem_info;
719 	char *elem;
720 	bool owner_bit;
721 
722 	elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
723 	elem = elem_info->elem;
724 	owner_bit = mlxsw_pci_eqe_owner_get(elem);
725 	if (mlxsw_pci_elem_hw_owned(q, owner_bit))
726 		return NULL;
727 	q->consumer_counter++;
728 	rmb(); /* make sure we read owned bit before the rest of elem */
729 	return elem;
730 }
731 
732 static void mlxsw_pci_eq_tasklet(unsigned long data)
733 {
734 	struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
735 	struct mlxsw_pci *mlxsw_pci = q->pci;
736 	u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
737 	unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
738 	char *eqe;
739 	u8 cqn;
740 	bool cq_handle = false;
741 	int items = 0;
742 	int credits = q->count >> 1;
743 
744 	memset(&active_cqns, 0, sizeof(active_cqns));
745 
746 	while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
747 
748 		/* Command interface completion events are always received on
749 		 * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events
750 		 * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1).
751 		 */
752 		switch (q->num) {
753 		case MLXSW_PCI_EQ_ASYNC_NUM:
754 			mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
755 			q->u.eq.ev_cmd_count++;
756 			break;
757 		case MLXSW_PCI_EQ_COMP_NUM:
758 			cqn = mlxsw_pci_eqe_cqn_get(eqe);
759 			set_bit(cqn, active_cqns);
760 			cq_handle = true;
761 			q->u.eq.ev_comp_count++;
762 			break;
763 		default:
764 			q->u.eq.ev_other_count++;
765 		}
766 		if (++items == credits)
767 			break;
768 	}
769 	if (items) {
770 		mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
771 		mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
772 	}
773 
774 	if (!cq_handle)
775 		return;
776 	for_each_set_bit(cqn, active_cqns, cq_count) {
777 		q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
778 		mlxsw_pci_queue_tasklet_schedule(q);
779 	}
780 }
781 
782 struct mlxsw_pci_queue_ops {
783 	const char *name;
784 	enum mlxsw_pci_queue_type type;
785 	void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
786 			 struct mlxsw_pci_queue *q);
787 	int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
788 		    struct mlxsw_pci_queue *q);
789 	void (*fini)(struct mlxsw_pci *mlxsw_pci,
790 		     struct mlxsw_pci_queue *q);
791 	void (*tasklet)(unsigned long data);
792 	u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
793 	u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
794 	u16 elem_count;
795 	u8 elem_size;
796 };
797 
798 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
799 	.type		= MLXSW_PCI_QUEUE_TYPE_SDQ,
800 	.init		= mlxsw_pci_sdq_init,
801 	.fini		= mlxsw_pci_sdq_fini,
802 	.elem_count	= MLXSW_PCI_WQE_COUNT,
803 	.elem_size	= MLXSW_PCI_WQE_SIZE,
804 };
805 
806 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
807 	.type		= MLXSW_PCI_QUEUE_TYPE_RDQ,
808 	.init		= mlxsw_pci_rdq_init,
809 	.fini		= mlxsw_pci_rdq_fini,
810 	.elem_count	= MLXSW_PCI_WQE_COUNT,
811 	.elem_size	= MLXSW_PCI_WQE_SIZE
812 };
813 
814 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
815 	.type		= MLXSW_PCI_QUEUE_TYPE_CQ,
816 	.pre_init	= mlxsw_pci_cq_pre_init,
817 	.init		= mlxsw_pci_cq_init,
818 	.fini		= mlxsw_pci_cq_fini,
819 	.tasklet	= mlxsw_pci_cq_tasklet,
820 	.elem_count_f	= mlxsw_pci_cq_elem_count,
821 	.elem_size_f	= mlxsw_pci_cq_elem_size
822 };
823 
824 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
825 	.type		= MLXSW_PCI_QUEUE_TYPE_EQ,
826 	.init		= mlxsw_pci_eq_init,
827 	.fini		= mlxsw_pci_eq_fini,
828 	.tasklet	= mlxsw_pci_eq_tasklet,
829 	.elem_count	= MLXSW_PCI_EQE_COUNT,
830 	.elem_size	= MLXSW_PCI_EQE_SIZE
831 };
832 
833 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
834 				const struct mlxsw_pci_queue_ops *q_ops,
835 				struct mlxsw_pci_queue *q, u8 q_num)
836 {
837 	struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
838 	int i;
839 	int err;
840 
841 	q->num = q_num;
842 	if (q_ops->pre_init)
843 		q_ops->pre_init(mlxsw_pci, q);
844 
845 	spin_lock_init(&q->lock);
846 	q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
847 					 q_ops->elem_count;
848 	q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
849 					    q_ops->elem_size;
850 	q->type = q_ops->type;
851 	q->pci = mlxsw_pci;
852 
853 	if (q_ops->tasklet)
854 		tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
855 
856 	mem_item->size = MLXSW_PCI_AQ_SIZE;
857 	mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
858 					     mem_item->size,
859 					     &mem_item->mapaddr);
860 	if (!mem_item->buf)
861 		return -ENOMEM;
862 
863 	q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
864 	if (!q->elem_info) {
865 		err = -ENOMEM;
866 		goto err_elem_info_alloc;
867 	}
868 
869 	/* Initialize dma mapped elements info elem_info for
870 	 * future easy access.
871 	 */
872 	for (i = 0; i < q->count; i++) {
873 		struct mlxsw_pci_queue_elem_info *elem_info;
874 
875 		elem_info = mlxsw_pci_queue_elem_info_get(q, i);
876 		elem_info->elem =
877 			__mlxsw_pci_queue_elem_get(q, q->elem_size, i);
878 	}
879 
880 	mlxsw_cmd_mbox_zero(mbox);
881 	err = q_ops->init(mlxsw_pci, mbox, q);
882 	if (err)
883 		goto err_q_ops_init;
884 	return 0;
885 
886 err_q_ops_init:
887 	kfree(q->elem_info);
888 err_elem_info_alloc:
889 	pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
890 			    mem_item->buf, mem_item->mapaddr);
891 	return err;
892 }
893 
894 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
895 				 const struct mlxsw_pci_queue_ops *q_ops,
896 				 struct mlxsw_pci_queue *q)
897 {
898 	struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
899 
900 	q_ops->fini(mlxsw_pci, q);
901 	kfree(q->elem_info);
902 	pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
903 			    mem_item->buf, mem_item->mapaddr);
904 }
905 
906 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
907 				      const struct mlxsw_pci_queue_ops *q_ops,
908 				      u8 num_qs)
909 {
910 	struct mlxsw_pci_queue_type_group *queue_group;
911 	int i;
912 	int err;
913 
914 	queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
915 	queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
916 	if (!queue_group->q)
917 		return -ENOMEM;
918 
919 	for (i = 0; i < num_qs; i++) {
920 		err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
921 					   &queue_group->q[i], i);
922 		if (err)
923 			goto err_queue_init;
924 	}
925 	queue_group->count = num_qs;
926 
927 	return 0;
928 
929 err_queue_init:
930 	for (i--; i >= 0; i--)
931 		mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
932 	kfree(queue_group->q);
933 	return err;
934 }
935 
936 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
937 				       const struct mlxsw_pci_queue_ops *q_ops)
938 {
939 	struct mlxsw_pci_queue_type_group *queue_group;
940 	int i;
941 
942 	queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
943 	for (i = 0; i < queue_group->count; i++)
944 		mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
945 	kfree(queue_group->q);
946 }
947 
948 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
949 {
950 	struct pci_dev *pdev = mlxsw_pci->pdev;
951 	u8 num_sdqs;
952 	u8 sdq_log2sz;
953 	u8 num_rdqs;
954 	u8 rdq_log2sz;
955 	u8 num_cqs;
956 	u8 cq_log2sz;
957 	u8 cqv2_log2sz;
958 	u8 num_eqs;
959 	u8 eq_log2sz;
960 	int err;
961 
962 	mlxsw_cmd_mbox_zero(mbox);
963 	err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
964 	if (err)
965 		return err;
966 
967 	num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
968 	sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
969 	num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
970 	rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
971 	num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
972 	cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
973 	cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
974 	num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
975 	eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
976 
977 	if (num_sdqs + num_rdqs > num_cqs ||
978 	    num_sdqs < MLXSW_PCI_SDQS_MIN ||
979 	    num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
980 		dev_err(&pdev->dev, "Unsupported number of queues\n");
981 		return -EINVAL;
982 	}
983 
984 	if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
985 	    (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
986 	    (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
987 	    (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
988 	     (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
989 	    (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
990 		dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
991 		return -EINVAL;
992 	}
993 
994 	mlxsw_pci->num_sdq_cqs = num_sdqs;
995 
996 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
997 					 num_eqs);
998 	if (err) {
999 		dev_err(&pdev->dev, "Failed to initialize event queues\n");
1000 		return err;
1001 	}
1002 
1003 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1004 					 num_cqs);
1005 	if (err) {
1006 		dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1007 		goto err_cqs_init;
1008 	}
1009 
1010 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1011 					 num_sdqs);
1012 	if (err) {
1013 		dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1014 		goto err_sdqs_init;
1015 	}
1016 
1017 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1018 					 num_rdqs);
1019 	if (err) {
1020 		dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1021 		goto err_rdqs_init;
1022 	}
1023 
1024 	/* We have to poll in command interface until queues are initialized */
1025 	mlxsw_pci->cmd.nopoll = true;
1026 	return 0;
1027 
1028 err_rdqs_init:
1029 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1030 err_sdqs_init:
1031 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1032 err_cqs_init:
1033 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1034 	return err;
1035 }
1036 
1037 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1038 {
1039 	mlxsw_pci->cmd.nopoll = false;
1040 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1041 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1042 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1043 	mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1044 }
1045 
1046 static void
1047 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1048 				     char *mbox, int index,
1049 				     const struct mlxsw_swid_config *swid)
1050 {
1051 	u8 mask = 0;
1052 
1053 	if (swid->used_type) {
1054 		mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1055 			mbox, index, swid->type);
1056 		mask |= 1;
1057 	}
1058 	if (swid->used_properties) {
1059 		mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1060 			mbox, index, swid->properties);
1061 		mask |= 2;
1062 	}
1063 	mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1064 }
1065 
1066 static int
1067 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1068 				const struct mlxsw_config_profile *profile,
1069 				struct mlxsw_res *res)
1070 {
1071 	u64 single_size, double_size, linear_size;
1072 	int err;
1073 
1074 	err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1075 				       &single_size, &double_size,
1076 				       &linear_size);
1077 	if (err)
1078 		return err;
1079 
1080 	MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1081 	MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1082 	MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1083 
1084 	return 0;
1085 }
1086 
1087 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1088 				    const struct mlxsw_config_profile *profile,
1089 				    struct mlxsw_res *res)
1090 {
1091 	int i;
1092 	int err;
1093 
1094 	mlxsw_cmd_mbox_zero(mbox);
1095 
1096 	if (profile->used_max_vepa_channels) {
1097 		mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1098 			mbox, 1);
1099 		mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1100 			mbox, profile->max_vepa_channels);
1101 	}
1102 	if (profile->used_max_mid) {
1103 		mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1104 			mbox, 1);
1105 		mlxsw_cmd_mbox_config_profile_max_mid_set(
1106 			mbox, profile->max_mid);
1107 	}
1108 	if (profile->used_max_pgt) {
1109 		mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1110 			mbox, 1);
1111 		mlxsw_cmd_mbox_config_profile_max_pgt_set(
1112 			mbox, profile->max_pgt);
1113 	}
1114 	if (profile->used_max_system_port) {
1115 		mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1116 			mbox, 1);
1117 		mlxsw_cmd_mbox_config_profile_max_system_port_set(
1118 			mbox, profile->max_system_port);
1119 	}
1120 	if (profile->used_max_vlan_groups) {
1121 		mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1122 			mbox, 1);
1123 		mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1124 			mbox, profile->max_vlan_groups);
1125 	}
1126 	if (profile->used_max_regions) {
1127 		mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1128 			mbox, 1);
1129 		mlxsw_cmd_mbox_config_profile_max_regions_set(
1130 			mbox, profile->max_regions);
1131 	}
1132 	if (profile->used_flood_tables) {
1133 		mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1134 			mbox, 1);
1135 		mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1136 			mbox, profile->max_flood_tables);
1137 		mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1138 			mbox, profile->max_vid_flood_tables);
1139 		mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1140 			mbox, profile->max_fid_offset_flood_tables);
1141 		mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1142 			mbox, profile->fid_offset_flood_table_size);
1143 		mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1144 			mbox, profile->max_fid_flood_tables);
1145 		mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1146 			mbox, profile->fid_flood_table_size);
1147 	}
1148 	if (profile->used_flood_mode) {
1149 		mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1150 			mbox, 1);
1151 		mlxsw_cmd_mbox_config_profile_flood_mode_set(
1152 			mbox, profile->flood_mode);
1153 	}
1154 	if (profile->used_max_ib_mc) {
1155 		mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1156 			mbox, 1);
1157 		mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1158 			mbox, profile->max_ib_mc);
1159 	}
1160 	if (profile->used_max_pkey) {
1161 		mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1162 			mbox, 1);
1163 		mlxsw_cmd_mbox_config_profile_max_pkey_set(
1164 			mbox, profile->max_pkey);
1165 	}
1166 	if (profile->used_ar_sec) {
1167 		mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1168 			mbox, 1);
1169 		mlxsw_cmd_mbox_config_profile_ar_sec_set(
1170 			mbox, profile->ar_sec);
1171 	}
1172 	if (profile->used_adaptive_routing_group_cap) {
1173 		mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1174 			mbox, 1);
1175 		mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1176 			mbox, profile->adaptive_routing_group_cap);
1177 	}
1178 	if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {
1179 		err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1180 		if (err)
1181 			return err;
1182 
1183 		mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1184 		mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1185 					MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1186 		mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1187 									   1);
1188 		mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1189 					MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1190 		mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1191 								mbox, 1);
1192 		mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1193 					MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1194 	}
1195 
1196 	for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1197 		mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1198 						     &profile->swid_config[i]);
1199 
1200 	if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1201 		mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1202 		mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1203 	}
1204 
1205 	return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1206 }
1207 
1208 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1209 {
1210 	struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1211 	int err;
1212 
1213 	mlxsw_cmd_mbox_zero(mbox);
1214 	err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1215 	if (err)
1216 		return err;
1217 	mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1218 	mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1219 	return 0;
1220 }
1221 
1222 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1223 				  u16 num_pages)
1224 {
1225 	struct mlxsw_pci_mem_item *mem_item;
1226 	int nent = 0;
1227 	int i;
1228 	int err;
1229 
1230 	mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1231 					   GFP_KERNEL);
1232 	if (!mlxsw_pci->fw_area.items)
1233 		return -ENOMEM;
1234 	mlxsw_pci->fw_area.count = num_pages;
1235 
1236 	mlxsw_cmd_mbox_zero(mbox);
1237 	for (i = 0; i < num_pages; i++) {
1238 		mem_item = &mlxsw_pci->fw_area.items[i];
1239 
1240 		mem_item->size = MLXSW_PCI_PAGE_SIZE;
1241 		mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1242 						     mem_item->size,
1243 						     &mem_item->mapaddr);
1244 		if (!mem_item->buf) {
1245 			err = -ENOMEM;
1246 			goto err_alloc;
1247 		}
1248 		mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1249 		mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1250 		if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1251 			err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1252 			if (err)
1253 				goto err_cmd_map_fa;
1254 			nent = 0;
1255 			mlxsw_cmd_mbox_zero(mbox);
1256 		}
1257 	}
1258 
1259 	if (nent) {
1260 		err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1261 		if (err)
1262 			goto err_cmd_map_fa;
1263 	}
1264 
1265 	return 0;
1266 
1267 err_cmd_map_fa:
1268 err_alloc:
1269 	for (i--; i >= 0; i--) {
1270 		mem_item = &mlxsw_pci->fw_area.items[i];
1271 
1272 		pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1273 				    mem_item->buf, mem_item->mapaddr);
1274 	}
1275 	kfree(mlxsw_pci->fw_area.items);
1276 	return err;
1277 }
1278 
1279 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1280 {
1281 	struct mlxsw_pci_mem_item *mem_item;
1282 	int i;
1283 
1284 	mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1285 
1286 	for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1287 		mem_item = &mlxsw_pci->fw_area.items[i];
1288 
1289 		pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1290 				    mem_item->buf, mem_item->mapaddr);
1291 	}
1292 	kfree(mlxsw_pci->fw_area.items);
1293 }
1294 
1295 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1296 {
1297 	struct mlxsw_pci *mlxsw_pci = dev_id;
1298 	struct mlxsw_pci_queue *q;
1299 	int i;
1300 
1301 	for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1302 		q = mlxsw_pci_eq_get(mlxsw_pci, i);
1303 		mlxsw_pci_queue_tasklet_schedule(q);
1304 	}
1305 	return IRQ_HANDLED;
1306 }
1307 
1308 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1309 				struct mlxsw_pci_mem_item *mbox)
1310 {
1311 	struct pci_dev *pdev = mlxsw_pci->pdev;
1312 	int err = 0;
1313 
1314 	mbox->size = MLXSW_CMD_MBOX_SIZE;
1315 	mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1316 					 &mbox->mapaddr);
1317 	if (!mbox->buf) {
1318 		dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1319 		err = -ENOMEM;
1320 	}
1321 
1322 	return err;
1323 }
1324 
1325 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1326 				struct mlxsw_pci_mem_item *mbox)
1327 {
1328 	struct pci_dev *pdev = mlxsw_pci->pdev;
1329 
1330 	pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1331 			    mbox->mapaddr);
1332 }
1333 
1334 static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci,
1335 				    const struct pci_device_id *id,
1336 				    u32 *p_sys_status)
1337 {
1338 	unsigned long end;
1339 	u32 val;
1340 
1341 	if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1342 		msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1343 		return 0;
1344 	}
1345 
1346 	/* We must wait for the HW to become responsive. */
1347 	msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1348 
1349 	end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1350 	do {
1351 		val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1352 		if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1353 			return 0;
1354 		cond_resched();
1355 	} while (time_before(jiffies, end));
1356 
1357 	*p_sys_status = val & MLXSW_PCI_FW_READY_MASK;
1358 
1359 	return -EBUSY;
1360 }
1361 
1362 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1363 			      const struct pci_device_id *id)
1364 {
1365 	struct pci_dev *pdev = mlxsw_pci->pdev;
1366 	char mrsr_pl[MLXSW_REG_MRSR_LEN];
1367 	u32 sys_status;
1368 	int err;
1369 
1370 	err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1371 	if (err) {
1372 		dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n",
1373 			sys_status);
1374 		return err;
1375 	}
1376 
1377 	mlxsw_reg_mrsr_pack(mrsr_pl);
1378 	err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl);
1379 	if (err)
1380 		return err;
1381 
1382 	err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1383 	if (err) {
1384 		dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n",
1385 			sys_status);
1386 		return err;
1387 	}
1388 
1389 	return 0;
1390 }
1391 
1392 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1393 {
1394 	int err;
1395 
1396 	err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1397 	if (err < 0)
1398 		dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1399 	return err;
1400 }
1401 
1402 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1403 {
1404 	pci_free_irq_vectors(mlxsw_pci->pdev);
1405 }
1406 
1407 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1408 			  const struct mlxsw_config_profile *profile,
1409 			  struct mlxsw_res *res)
1410 {
1411 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1412 	struct pci_dev *pdev = mlxsw_pci->pdev;
1413 	char *mbox;
1414 	u16 num_pages;
1415 	int err;
1416 
1417 	mutex_init(&mlxsw_pci->cmd.lock);
1418 	init_waitqueue_head(&mlxsw_pci->cmd.wait);
1419 
1420 	mlxsw_pci->core = mlxsw_core;
1421 
1422 	mbox = mlxsw_cmd_mbox_alloc();
1423 	if (!mbox)
1424 		return -ENOMEM;
1425 
1426 	err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1427 	if (err)
1428 		goto mbox_put;
1429 
1430 	err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1431 	if (err)
1432 		goto err_out_mbox_alloc;
1433 
1434 	err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1435 	if (err)
1436 		goto err_sw_reset;
1437 
1438 	err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1439 	if (err < 0) {
1440 		dev_err(&pdev->dev, "MSI-X init failed\n");
1441 		goto err_alloc_irq;
1442 	}
1443 
1444 	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1445 	if (err)
1446 		goto err_query_fw;
1447 
1448 	mlxsw_pci->bus_info.fw_rev.major =
1449 		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1450 	mlxsw_pci->bus_info.fw_rev.minor =
1451 		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1452 	mlxsw_pci->bus_info.fw_rev.subminor =
1453 		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1454 
1455 	if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1456 		dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1457 		err = -EINVAL;
1458 		goto err_iface_rev;
1459 	}
1460 	if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1461 		dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1462 		err = -EINVAL;
1463 		goto err_doorbell_page_bar;
1464 	}
1465 
1466 	mlxsw_pci->doorbell_offset =
1467 		mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1468 
1469 	if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {
1470 		dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n");
1471 		err = -EINVAL;
1472 		goto err_fr_rn_clk_bar;
1473 	}
1474 
1475 	mlxsw_pci->free_running_clock_offset =
1476 		mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
1477 
1478 	num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1479 	err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1480 	if (err)
1481 		goto err_fw_area_init;
1482 
1483 	err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1484 	if (err)
1485 		goto err_boardinfo;
1486 
1487 	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1488 	if (err)
1489 		goto err_query_resources;
1490 
1491 	if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1492 	    MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1493 		mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1494 	else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1495 		 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1496 		mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1497 	else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1498 		  MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1499 		 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1500 		mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1501 	} else {
1502 		dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1503 		goto err_cqe_v_check;
1504 	}
1505 
1506 	err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1507 	if (err)
1508 		goto err_config_profile;
1509 
1510 	err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1511 	if (err)
1512 		goto err_aqs_init;
1513 
1514 	err = request_irq(pci_irq_vector(pdev, 0),
1515 			  mlxsw_pci_eq_irq_handler, 0,
1516 			  mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1517 	if (err) {
1518 		dev_err(&pdev->dev, "IRQ request failed\n");
1519 		goto err_request_eq_irq;
1520 	}
1521 
1522 	goto mbox_put;
1523 
1524 err_request_eq_irq:
1525 	mlxsw_pci_aqs_fini(mlxsw_pci);
1526 err_aqs_init:
1527 err_config_profile:
1528 err_cqe_v_check:
1529 err_query_resources:
1530 err_boardinfo:
1531 	mlxsw_pci_fw_area_fini(mlxsw_pci);
1532 err_fw_area_init:
1533 err_fr_rn_clk_bar:
1534 err_doorbell_page_bar:
1535 err_iface_rev:
1536 err_query_fw:
1537 	mlxsw_pci_free_irq_vectors(mlxsw_pci);
1538 err_alloc_irq:
1539 err_sw_reset:
1540 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1541 err_out_mbox_alloc:
1542 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1543 mbox_put:
1544 	mlxsw_cmd_mbox_free(mbox);
1545 	return err;
1546 }
1547 
1548 static void mlxsw_pci_fini(void *bus_priv)
1549 {
1550 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1551 
1552 	free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1553 	mlxsw_pci_aqs_fini(mlxsw_pci);
1554 	mlxsw_pci_fw_area_fini(mlxsw_pci);
1555 	mlxsw_pci_free_irq_vectors(mlxsw_pci);
1556 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1557 	mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1558 }
1559 
1560 static struct mlxsw_pci_queue *
1561 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1562 		   const struct mlxsw_tx_info *tx_info)
1563 {
1564 	u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1;
1565 	u8 sdqn;
1566 
1567 	if (tx_info->is_emad) {
1568 		sdqn = MLXSW_PCI_SDQ_EMAD_INDEX;
1569 	} else {
1570 		BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0);
1571 		sdqn = 1 + (tx_info->local_port % ctl_sdq_count);
1572 	}
1573 
1574 	return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1575 }
1576 
1577 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1578 					const struct mlxsw_tx_info *tx_info)
1579 {
1580 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1581 	struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1582 
1583 	return !mlxsw_pci_queue_elem_info_producer_get(q);
1584 }
1585 
1586 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1587 				  const struct mlxsw_tx_info *tx_info)
1588 {
1589 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1590 	struct mlxsw_pci_queue *q;
1591 	struct mlxsw_pci_queue_elem_info *elem_info;
1592 	char *wqe;
1593 	int i;
1594 	int err;
1595 
1596 	if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1597 		err = skb_linearize(skb);
1598 		if (err)
1599 			return err;
1600 	}
1601 
1602 	q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1603 	spin_lock_bh(&q->lock);
1604 	elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1605 	if (!elem_info) {
1606 		/* queue is full */
1607 		err = -EAGAIN;
1608 		goto unlock;
1609 	}
1610 	mlxsw_skb_cb(skb)->tx_info = *tx_info;
1611 	elem_info->u.sdq.skb = skb;
1612 
1613 	wqe = elem_info->elem;
1614 	mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1615 	mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1616 	mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1617 
1618 	err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1619 				     skb_headlen(skb), DMA_TO_DEVICE);
1620 	if (err)
1621 		goto unlock;
1622 
1623 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1624 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1625 
1626 		err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1627 					     skb_frag_address(frag),
1628 					     skb_frag_size(frag),
1629 					     DMA_TO_DEVICE);
1630 		if (err)
1631 			goto unmap_frags;
1632 	}
1633 
1634 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
1635 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1636 
1637 	/* Set unused sq entries byte count to zero. */
1638 	for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1639 		mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1640 
1641 	/* Everything is set up, ring producer doorbell to get HW going */
1642 	q->producer_counter++;
1643 	mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1644 
1645 	goto unlock;
1646 
1647 unmap_frags:
1648 	for (; i >= 0; i--)
1649 		mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1650 unlock:
1651 	spin_unlock_bh(&q->lock);
1652 	return err;
1653 }
1654 
1655 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1656 			      u32 in_mod, bool out_mbox_direct,
1657 			      char *in_mbox, size_t in_mbox_size,
1658 			      char *out_mbox, size_t out_mbox_size,
1659 			      u8 *p_status)
1660 {
1661 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1662 	dma_addr_t in_mapaddr = 0, out_mapaddr = 0;
1663 	bool evreq = mlxsw_pci->cmd.nopoll;
1664 	unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1665 	bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1666 	int err;
1667 
1668 	*p_status = MLXSW_CMD_STATUS_OK;
1669 
1670 	err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1671 	if (err)
1672 		return err;
1673 
1674 	if (in_mbox) {
1675 		memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1676 		in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1677 	}
1678 	mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1679 	mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1680 
1681 	if (out_mbox)
1682 		out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1683 	mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1684 	mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1685 
1686 	mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1687 	mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1688 
1689 	*p_wait_done = false;
1690 
1691 	wmb(); /* all needs to be written before we write control register */
1692 	mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1693 			  MLXSW_PCI_CIR_CTRL_GO_BIT |
1694 			  (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1695 			  (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1696 			  opcode);
1697 
1698 	if (!evreq) {
1699 		unsigned long end;
1700 
1701 		end = jiffies + timeout;
1702 		do {
1703 			u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1704 
1705 			if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1706 				*p_wait_done = true;
1707 				*p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1708 				break;
1709 			}
1710 			cond_resched();
1711 		} while (time_before(jiffies, end));
1712 	} else {
1713 		wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1714 		*p_status = mlxsw_pci->cmd.comp.status;
1715 	}
1716 
1717 	err = 0;
1718 	if (*p_wait_done) {
1719 		if (*p_status)
1720 			err = -EIO;
1721 	} else {
1722 		err = -ETIMEDOUT;
1723 	}
1724 
1725 	if (!err && out_mbox && out_mbox_direct) {
1726 		/* Some commands don't use output param as address to mailbox
1727 		 * but they store output directly into registers. In that case,
1728 		 * copy registers into mbox buffer.
1729 		 */
1730 		__be32 tmp;
1731 
1732 		if (!evreq) {
1733 			tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1734 							   CIR_OUT_PARAM_HI));
1735 			memcpy(out_mbox, &tmp, sizeof(tmp));
1736 			tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1737 							   CIR_OUT_PARAM_LO));
1738 			memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1739 		}
1740 	} else if (!err && out_mbox) {
1741 		memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1742 	}
1743 
1744 	mutex_unlock(&mlxsw_pci->cmd.lock);
1745 
1746 	return err;
1747 }
1748 
1749 static u32 mlxsw_pci_read_frc_h(void *bus_priv)
1750 {
1751 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1752 	u64 frc_offset;
1753 
1754 	frc_offset = mlxsw_pci->free_running_clock_offset;
1755 	return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset));
1756 }
1757 
1758 static u32 mlxsw_pci_read_frc_l(void *bus_priv)
1759 {
1760 	struct mlxsw_pci *mlxsw_pci = bus_priv;
1761 	u64 frc_offset;
1762 
1763 	frc_offset = mlxsw_pci->free_running_clock_offset;
1764 	return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset));
1765 }
1766 
1767 static const struct mlxsw_bus mlxsw_pci_bus = {
1768 	.kind			= "pci",
1769 	.init			= mlxsw_pci_init,
1770 	.fini			= mlxsw_pci_fini,
1771 	.skb_transmit_busy	= mlxsw_pci_skb_transmit_busy,
1772 	.skb_transmit		= mlxsw_pci_skb_transmit,
1773 	.cmd_exec		= mlxsw_pci_cmd_exec,
1774 	.read_frc_h		= mlxsw_pci_read_frc_h,
1775 	.read_frc_l		= mlxsw_pci_read_frc_l,
1776 	.features		= MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
1777 };
1778 
1779 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1780 {
1781 	const char *driver_name = pdev->driver->name;
1782 	struct mlxsw_pci *mlxsw_pci;
1783 	int err;
1784 
1785 	mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1786 	if (!mlxsw_pci)
1787 		return -ENOMEM;
1788 
1789 	err = pci_enable_device(pdev);
1790 	if (err) {
1791 		dev_err(&pdev->dev, "pci_enable_device failed\n");
1792 		goto err_pci_enable_device;
1793 	}
1794 
1795 	err = pci_request_regions(pdev, driver_name);
1796 	if (err) {
1797 		dev_err(&pdev->dev, "pci_request_regions failed\n");
1798 		goto err_pci_request_regions;
1799 	}
1800 
1801 	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1802 	if (!err) {
1803 		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1804 		if (err) {
1805 			dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1806 			goto err_pci_set_dma_mask;
1807 		}
1808 	} else {
1809 		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1810 		if (err) {
1811 			dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1812 			goto err_pci_set_dma_mask;
1813 		}
1814 	}
1815 
1816 	if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1817 		dev_err(&pdev->dev, "invalid PCI region size\n");
1818 		err = -EINVAL;
1819 		goto err_pci_resource_len_check;
1820 	}
1821 
1822 	mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1823 				     pci_resource_len(pdev, 0));
1824 	if (!mlxsw_pci->hw_addr) {
1825 		dev_err(&pdev->dev, "ioremap failed\n");
1826 		err = -EIO;
1827 		goto err_ioremap;
1828 	}
1829 	pci_set_master(pdev);
1830 
1831 	mlxsw_pci->pdev = pdev;
1832 	pci_set_drvdata(pdev, mlxsw_pci);
1833 
1834 	mlxsw_pci->bus_info.device_kind = driver_name;
1835 	mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1836 	mlxsw_pci->bus_info.dev = &pdev->dev;
1837 	mlxsw_pci->bus_info.read_frc_capable = true;
1838 	mlxsw_pci->id = id;
1839 
1840 	err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1841 					     &mlxsw_pci_bus, mlxsw_pci, false,
1842 					     NULL, NULL);
1843 	if (err) {
1844 		dev_err(&pdev->dev, "cannot register bus device\n");
1845 		goto err_bus_device_register;
1846 	}
1847 
1848 	return 0;
1849 
1850 err_bus_device_register:
1851 	iounmap(mlxsw_pci->hw_addr);
1852 err_ioremap:
1853 err_pci_resource_len_check:
1854 err_pci_set_dma_mask:
1855 	pci_release_regions(pdev);
1856 err_pci_request_regions:
1857 	pci_disable_device(pdev);
1858 err_pci_enable_device:
1859 	kfree(mlxsw_pci);
1860 	return err;
1861 }
1862 
1863 static void mlxsw_pci_remove(struct pci_dev *pdev)
1864 {
1865 	struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1866 
1867 	mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
1868 	iounmap(mlxsw_pci->hw_addr);
1869 	pci_release_regions(mlxsw_pci->pdev);
1870 	pci_disable_device(mlxsw_pci->pdev);
1871 	kfree(mlxsw_pci);
1872 }
1873 
1874 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1875 {
1876 	pci_driver->probe = mlxsw_pci_probe;
1877 	pci_driver->remove = mlxsw_pci_remove;
1878 	return pci_register_driver(pci_driver);
1879 }
1880 EXPORT_SYMBOL(mlxsw_pci_driver_register);
1881 
1882 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1883 {
1884 	pci_unregister_driver(pci_driver);
1885 }
1886 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1887 
1888 static int __init mlxsw_pci_module_init(void)
1889 {
1890 	return 0;
1891 }
1892 
1893 static void __exit mlxsw_pci_module_exit(void)
1894 {
1895 }
1896 
1897 module_init(mlxsw_pci_module_init);
1898 module_exit(mlxsw_pci_module_exit);
1899 
1900 MODULE_LICENSE("Dual BSD/GPL");
1901 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1902 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
1903