1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/pci.c 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the names of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") version 2 as published by the Free 20 * Software Foundation. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/export.h> 38 #include <linux/err.h> 39 #include <linux/device.h> 40 #include <linux/pci.h> 41 #include <linux/interrupt.h> 42 #include <linux/wait.h> 43 #include <linux/types.h> 44 #include <linux/skbuff.h> 45 #include <linux/if_vlan.h> 46 #include <linux/log2.h> 47 #include <linux/debugfs.h> 48 #include <linux/seq_file.h> 49 #include <linux/string.h> 50 51 #include "pci.h" 52 #include "core.h" 53 #include "cmd.h" 54 #include "port.h" 55 56 static const char mlxsw_pci_driver_name[] = "mlxsw_pci"; 57 58 static const struct pci_device_id mlxsw_pci_id_table[] = { 59 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0}, 60 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 61 {0, } 62 }; 63 64 static struct dentry *mlxsw_pci_dbg_root; 65 66 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id) 67 { 68 switch (id->device) { 69 case PCI_DEVICE_ID_MELLANOX_SWITCHX2: 70 return MLXSW_DEVICE_KIND_SWITCHX2; 71 case PCI_DEVICE_ID_MELLANOX_SPECTRUM: 72 return MLXSW_DEVICE_KIND_SPECTRUM; 73 default: 74 BUG(); 75 } 76 } 77 78 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 79 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 80 #define mlxsw_pci_read32(mlxsw_pci, reg) \ 81 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 82 83 enum mlxsw_pci_queue_type { 84 MLXSW_PCI_QUEUE_TYPE_SDQ, 85 MLXSW_PCI_QUEUE_TYPE_RDQ, 86 MLXSW_PCI_QUEUE_TYPE_CQ, 87 MLXSW_PCI_QUEUE_TYPE_EQ, 88 }; 89 90 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type) 91 { 92 switch (q_type) { 93 case MLXSW_PCI_QUEUE_TYPE_SDQ: 94 return "sdq"; 95 case MLXSW_PCI_QUEUE_TYPE_RDQ: 96 return "rdq"; 97 case MLXSW_PCI_QUEUE_TYPE_CQ: 98 return "cq"; 99 case MLXSW_PCI_QUEUE_TYPE_EQ: 100 return "eq"; 101 } 102 BUG(); 103 } 104 105 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 106 107 static const u16 mlxsw_pci_doorbell_type_offset[] = { 108 MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 109 MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 110 MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 111 MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 112 }; 113 114 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 115 0, /* unused */ 116 0, /* unused */ 117 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 118 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 119 }; 120 121 struct mlxsw_pci_mem_item { 122 char *buf; 123 dma_addr_t mapaddr; 124 size_t size; 125 }; 126 127 struct mlxsw_pci_queue_elem_info { 128 char *elem; /* pointer to actual dma mapped element mem chunk */ 129 union { 130 struct { 131 struct sk_buff *skb; 132 } sdq; 133 struct { 134 struct sk_buff *skb; 135 } rdq; 136 } u; 137 }; 138 139 struct mlxsw_pci_queue { 140 spinlock_t lock; /* for queue accesses */ 141 struct mlxsw_pci_mem_item mem_item; 142 struct mlxsw_pci_queue_elem_info *elem_info; 143 u16 producer_counter; 144 u16 consumer_counter; 145 u16 count; /* number of elements in queue */ 146 u8 num; /* queue number */ 147 u8 elem_size; /* size of one element */ 148 enum mlxsw_pci_queue_type type; 149 struct tasklet_struct tasklet; /* queue processing tasklet */ 150 struct mlxsw_pci *pci; 151 union { 152 struct { 153 u32 comp_sdq_count; 154 u32 comp_rdq_count; 155 } cq; 156 struct { 157 u32 ev_cmd_count; 158 u32 ev_comp_count; 159 u32 ev_other_count; 160 } eq; 161 } u; 162 }; 163 164 struct mlxsw_pci_queue_type_group { 165 struct mlxsw_pci_queue *q; 166 u8 count; /* number of queues in group */ 167 }; 168 169 struct mlxsw_pci { 170 struct pci_dev *pdev; 171 u8 __iomem *hw_addr; 172 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 173 u32 doorbell_offset; 174 struct msix_entry msix_entry; 175 struct mlxsw_core *core; 176 struct { 177 struct mlxsw_pci_mem_item *items; 178 unsigned int count; 179 } fw_area; 180 struct { 181 struct mlxsw_pci_mem_item out_mbox; 182 struct mlxsw_pci_mem_item in_mbox; 183 struct mutex lock; /* Lock access to command registers */ 184 bool nopoll; 185 wait_queue_head_t wait; 186 bool wait_done; 187 struct { 188 u8 status; 189 u64 out_param; 190 } comp; 191 } cmd; 192 struct mlxsw_bus_info bus_info; 193 struct dentry *dbg_dir; 194 }; 195 196 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 197 { 198 tasklet_schedule(&q->tasklet); 199 } 200 201 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 202 size_t elem_size, int elem_index) 203 { 204 return q->mem_item.buf + (elem_size * elem_index); 205 } 206 207 static struct mlxsw_pci_queue_elem_info * 208 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 209 { 210 return &q->elem_info[elem_index]; 211 } 212 213 static struct mlxsw_pci_queue_elem_info * 214 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 215 { 216 int index = q->producer_counter & (q->count - 1); 217 218 if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 219 return NULL; 220 return mlxsw_pci_queue_elem_info_get(q, index); 221 } 222 223 static struct mlxsw_pci_queue_elem_info * 224 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 225 { 226 int index = q->consumer_counter & (q->count - 1); 227 228 return mlxsw_pci_queue_elem_info_get(q, index); 229 } 230 231 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 232 { 233 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 234 } 235 236 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 237 { 238 return owner_bit != !!(q->consumer_counter & q->count); 239 } 240 241 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q, 242 u32 (*get_elem_owner_func)(char *)) 243 { 244 struct mlxsw_pci_queue_elem_info *elem_info; 245 char *elem; 246 bool owner_bit; 247 248 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 249 elem = elem_info->elem; 250 owner_bit = get_elem_owner_func(elem); 251 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 252 return NULL; 253 q->consumer_counter++; 254 rmb(); /* make sure we read owned bit before the rest of elem */ 255 return elem; 256 } 257 258 static struct mlxsw_pci_queue_type_group * 259 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 260 enum mlxsw_pci_queue_type q_type) 261 { 262 return &mlxsw_pci->queues[q_type]; 263 } 264 265 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 266 enum mlxsw_pci_queue_type q_type) 267 { 268 struct mlxsw_pci_queue_type_group *queue_group; 269 270 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 271 return queue_group->count; 272 } 273 274 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 275 { 276 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 277 } 278 279 static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci) 280 { 281 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ); 282 } 283 284 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 285 { 286 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 287 } 288 289 static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci) 290 { 291 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ); 292 } 293 294 static struct mlxsw_pci_queue * 295 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 296 enum mlxsw_pci_queue_type q_type, u8 q_num) 297 { 298 return &mlxsw_pci->queues[q_type].q[q_num]; 299 } 300 301 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 302 u8 q_num) 303 { 304 return __mlxsw_pci_queue_get(mlxsw_pci, 305 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 306 } 307 308 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 309 u8 q_num) 310 { 311 return __mlxsw_pci_queue_get(mlxsw_pci, 312 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 313 } 314 315 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 316 u8 q_num) 317 { 318 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 319 } 320 321 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 322 u8 q_num) 323 { 324 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 325 } 326 327 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 328 struct mlxsw_pci_queue *q, 329 u16 val) 330 { 331 mlxsw_pci_write32(mlxsw_pci, 332 DOORBELL(mlxsw_pci->doorbell_offset, 333 mlxsw_pci_doorbell_type_offset[q->type], 334 q->num), val); 335 } 336 337 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 338 struct mlxsw_pci_queue *q, 339 u16 val) 340 { 341 mlxsw_pci_write32(mlxsw_pci, 342 DOORBELL(mlxsw_pci->doorbell_offset, 343 mlxsw_pci_doorbell_arm_type_offset[q->type], 344 q->num), val); 345 } 346 347 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 348 struct mlxsw_pci_queue *q) 349 { 350 wmb(); /* ensure all writes are done before we ring a bell */ 351 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 352 } 353 354 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 355 struct mlxsw_pci_queue *q) 356 { 357 wmb(); /* ensure all writes are done before we ring a bell */ 358 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 359 q->consumer_counter + q->count); 360 } 361 362 static void 363 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 364 struct mlxsw_pci_queue *q) 365 { 366 wmb(); /* ensure all writes are done before we ring a bell */ 367 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 368 } 369 370 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 371 int page_index) 372 { 373 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 374 } 375 376 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 377 struct mlxsw_pci_queue *q) 378 { 379 int i; 380 int err; 381 382 q->producer_counter = 0; 383 q->consumer_counter = 0; 384 385 /* Set CQ of same number of this SDQ. */ 386 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 387 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3); 388 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 389 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 390 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 391 392 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 393 } 394 395 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 396 if (err) 397 return err; 398 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 399 return 0; 400 } 401 402 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 403 struct mlxsw_pci_queue *q) 404 { 405 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 406 } 407 408 static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data) 409 { 410 struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 411 struct mlxsw_pci_queue *q; 412 int i; 413 static const char hdr[] = 414 "NUM PROD_COUNT CONS_COUNT COUNT\n"; 415 416 seq_printf(file, hdr); 417 for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) { 418 q = mlxsw_pci_sdq_get(mlxsw_pci, i); 419 spin_lock_bh(&q->lock); 420 seq_printf(file, "%3d %10d %10d %5d\n", 421 i, q->producer_counter, q->consumer_counter, 422 q->count); 423 spin_unlock_bh(&q->lock); 424 } 425 return 0; 426 } 427 428 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 429 int index, char *frag_data, size_t frag_len, 430 int direction) 431 { 432 struct pci_dev *pdev = mlxsw_pci->pdev; 433 dma_addr_t mapaddr; 434 435 mapaddr = pci_map_single(pdev, frag_data, frag_len, direction); 436 if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) { 437 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 438 return -EIO; 439 } 440 mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 441 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 442 return 0; 443 } 444 445 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 446 int index, int direction) 447 { 448 struct pci_dev *pdev = mlxsw_pci->pdev; 449 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 450 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 451 452 if (!frag_len) 453 return; 454 pci_unmap_single(pdev, mapaddr, frag_len, direction); 455 } 456 457 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 458 struct mlxsw_pci_queue_elem_info *elem_info) 459 { 460 size_t buf_len = MLXSW_PORT_MAX_MTU; 461 char *wqe = elem_info->elem; 462 struct sk_buff *skb; 463 int err; 464 465 elem_info->u.rdq.skb = NULL; 466 skb = netdev_alloc_skb_ip_align(NULL, buf_len); 467 if (!skb) 468 return -ENOMEM; 469 470 /* Assume that wqe was previously zeroed. */ 471 472 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 473 buf_len, DMA_FROM_DEVICE); 474 if (err) 475 goto err_frag_map; 476 477 elem_info->u.rdq.skb = skb; 478 return 0; 479 480 err_frag_map: 481 dev_kfree_skb_any(skb); 482 return err; 483 } 484 485 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 486 struct mlxsw_pci_queue_elem_info *elem_info) 487 { 488 struct sk_buff *skb; 489 char *wqe; 490 491 skb = elem_info->u.rdq.skb; 492 wqe = elem_info->elem; 493 494 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 495 dev_kfree_skb_any(skb); 496 } 497 498 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 499 struct mlxsw_pci_queue *q) 500 { 501 struct mlxsw_pci_queue_elem_info *elem_info; 502 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 503 int i; 504 int err; 505 506 q->producer_counter = 0; 507 q->consumer_counter = 0; 508 509 /* Set CQ of same number of this RDQ with base 510 * above SDQ count as the lower ones are assigned to SDQs. 511 */ 512 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 513 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 514 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 515 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 516 517 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 518 } 519 520 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 521 if (err) 522 return err; 523 524 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 525 526 for (i = 0; i < q->count; i++) { 527 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 528 BUG_ON(!elem_info); 529 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 530 if (err) 531 goto rollback; 532 /* Everything is set up, ring doorbell to pass elem to HW */ 533 q->producer_counter++; 534 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 535 } 536 537 return 0; 538 539 rollback: 540 for (i--; i >= 0; i--) { 541 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 542 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 543 } 544 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 545 546 return err; 547 } 548 549 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 550 struct mlxsw_pci_queue *q) 551 { 552 struct mlxsw_pci_queue_elem_info *elem_info; 553 int i; 554 555 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 556 for (i = 0; i < q->count; i++) { 557 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 558 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 559 } 560 } 561 562 static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data) 563 { 564 struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 565 struct mlxsw_pci_queue *q; 566 int i; 567 static const char hdr[] = 568 "NUM PROD_COUNT CONS_COUNT COUNT\n"; 569 570 seq_printf(file, hdr); 571 for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) { 572 q = mlxsw_pci_rdq_get(mlxsw_pci, i); 573 spin_lock_bh(&q->lock); 574 seq_printf(file, "%3d %10d %10d %5d\n", 575 i, q->producer_counter, q->consumer_counter, 576 q->count); 577 spin_unlock_bh(&q->lock); 578 } 579 return 0; 580 } 581 582 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 583 struct mlxsw_pci_queue *q) 584 { 585 int i; 586 int err; 587 588 q->consumer_counter = 0; 589 590 for (i = 0; i < q->count; i++) { 591 char *elem = mlxsw_pci_queue_elem_get(q, i); 592 593 mlxsw_pci_cqe_owner_set(elem, 1); 594 } 595 596 mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */ 597 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 598 mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0); 599 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 600 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 601 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 602 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 603 604 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 605 } 606 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 607 if (err) 608 return err; 609 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 610 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 611 return 0; 612 } 613 614 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 615 struct mlxsw_pci_queue *q) 616 { 617 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 618 } 619 620 static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data) 621 { 622 struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 623 624 struct mlxsw_pci_queue *q; 625 int i; 626 static const char hdr[] = 627 "NUM CONS_INDEX SDQ_COUNT RDQ_COUNT COUNT\n"; 628 629 seq_printf(file, hdr); 630 for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) { 631 q = mlxsw_pci_cq_get(mlxsw_pci, i); 632 spin_lock_bh(&q->lock); 633 seq_printf(file, "%3d %10d %10d %10d %5d\n", 634 i, q->consumer_counter, q->u.cq.comp_sdq_count, 635 q->u.cq.comp_rdq_count, q->count); 636 spin_unlock_bh(&q->lock); 637 } 638 return 0; 639 } 640 641 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 642 struct mlxsw_pci_queue *q, 643 u16 consumer_counter_limit, 644 char *cqe) 645 { 646 struct pci_dev *pdev = mlxsw_pci->pdev; 647 struct mlxsw_pci_queue_elem_info *elem_info; 648 char *wqe; 649 struct sk_buff *skb; 650 int i; 651 652 spin_lock(&q->lock); 653 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 654 skb = elem_info->u.sdq.skb; 655 wqe = elem_info->elem; 656 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 657 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 658 dev_kfree_skb_any(skb); 659 elem_info->u.sdq.skb = NULL; 660 661 if (q->consumer_counter++ != consumer_counter_limit) 662 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 663 spin_unlock(&q->lock); 664 } 665 666 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 667 struct mlxsw_pci_queue *q, 668 u16 consumer_counter_limit, 669 char *cqe) 670 { 671 struct pci_dev *pdev = mlxsw_pci->pdev; 672 struct mlxsw_pci_queue_elem_info *elem_info; 673 char *wqe; 674 struct sk_buff *skb; 675 struct mlxsw_rx_info rx_info; 676 u16 byte_count; 677 int err; 678 679 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 680 skb = elem_info->u.sdq.skb; 681 if (!skb) 682 return; 683 wqe = elem_info->elem; 684 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 685 686 if (q->consumer_counter++ != consumer_counter_limit) 687 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 688 689 if (mlxsw_pci_cqe_lag_get(cqe)) { 690 rx_info.is_lag = true; 691 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe); 692 rx_info.lag_port_index = mlxsw_pci_cqe_lag_port_index_get(cqe); 693 } else { 694 rx_info.is_lag = false; 695 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 696 } 697 698 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 699 700 byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 701 if (mlxsw_pci_cqe_crc_get(cqe)) 702 byte_count -= ETH_FCS_LEN; 703 skb_put(skb, byte_count); 704 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 705 706 memset(wqe, 0, q->elem_size); 707 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 708 if (err) 709 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); 710 /* Everything is set up, ring doorbell to pass elem to HW */ 711 q->producer_counter++; 712 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 713 return; 714 } 715 716 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 717 { 718 return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get); 719 } 720 721 static void mlxsw_pci_cq_tasklet(unsigned long data) 722 { 723 struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 724 struct mlxsw_pci *mlxsw_pci = q->pci; 725 char *cqe; 726 int items = 0; 727 int credits = q->count >> 1; 728 729 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 730 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 731 u8 sendq = mlxsw_pci_cqe_sr_get(cqe); 732 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe); 733 734 if (sendq) { 735 struct mlxsw_pci_queue *sdq; 736 737 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 738 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 739 wqe_counter, cqe); 740 q->u.cq.comp_sdq_count++; 741 } else { 742 struct mlxsw_pci_queue *rdq; 743 744 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 745 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 746 wqe_counter, cqe); 747 q->u.cq.comp_rdq_count++; 748 } 749 if (++items == credits) 750 break; 751 } 752 if (items) { 753 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 754 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 755 } 756 } 757 758 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 759 struct mlxsw_pci_queue *q) 760 { 761 int i; 762 int err; 763 764 q->consumer_counter = 0; 765 766 for (i = 0; i < q->count; i++) { 767 char *elem = mlxsw_pci_queue_elem_get(q, i); 768 769 mlxsw_pci_eqe_owner_set(elem, 1); 770 } 771 772 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 773 mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0); 774 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 775 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 776 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 777 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 778 779 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 780 } 781 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 782 if (err) 783 return err; 784 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 785 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 786 return 0; 787 } 788 789 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 790 struct mlxsw_pci_queue *q) 791 { 792 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 793 } 794 795 static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data) 796 { 797 struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 798 struct mlxsw_pci_queue *q; 799 int i; 800 static const char hdr[] = 801 "NUM CONS_COUNT EV_CMD EV_COMP EV_OTHER COUNT\n"; 802 803 seq_printf(file, hdr); 804 for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) { 805 q = mlxsw_pci_eq_get(mlxsw_pci, i); 806 spin_lock_bh(&q->lock); 807 seq_printf(file, "%3d %10d %10d %10d %10d %5d\n", 808 i, q->consumer_counter, q->u.eq.ev_cmd_count, 809 q->u.eq.ev_comp_count, q->u.eq.ev_other_count, 810 q->count); 811 spin_unlock_bh(&q->lock); 812 } 813 return 0; 814 } 815 816 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 817 { 818 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 819 mlxsw_pci->cmd.comp.out_param = 820 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 821 mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 822 mlxsw_pci->cmd.wait_done = true; 823 wake_up(&mlxsw_pci->cmd.wait); 824 } 825 826 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 827 { 828 return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get); 829 } 830 831 static void mlxsw_pci_eq_tasklet(unsigned long data) 832 { 833 struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 834 struct mlxsw_pci *mlxsw_pci = q->pci; 835 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 836 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 837 char *eqe; 838 u8 cqn; 839 bool cq_handle = false; 840 int items = 0; 841 int credits = q->count >> 1; 842 843 memset(&active_cqns, 0, sizeof(active_cqns)); 844 845 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 846 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe); 847 848 switch (event_type) { 849 case MLXSW_PCI_EQE_EVENT_TYPE_CMD: 850 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 851 q->u.eq.ev_cmd_count++; 852 break; 853 case MLXSW_PCI_EQE_EVENT_TYPE_COMP: 854 cqn = mlxsw_pci_eqe_cqn_get(eqe); 855 set_bit(cqn, active_cqns); 856 cq_handle = true; 857 q->u.eq.ev_comp_count++; 858 break; 859 default: 860 q->u.eq.ev_other_count++; 861 } 862 if (++items == credits) 863 break; 864 } 865 if (items) { 866 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 867 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 868 } 869 870 if (!cq_handle) 871 return; 872 for_each_set_bit(cqn, active_cqns, cq_count) { 873 q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 874 mlxsw_pci_queue_tasklet_schedule(q); 875 } 876 } 877 878 struct mlxsw_pci_queue_ops { 879 const char *name; 880 enum mlxsw_pci_queue_type type; 881 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 882 struct mlxsw_pci_queue *q); 883 void (*fini)(struct mlxsw_pci *mlxsw_pci, 884 struct mlxsw_pci_queue *q); 885 void (*tasklet)(unsigned long data); 886 int (*dbg_read)(struct seq_file *s, void *data); 887 u16 elem_count; 888 u8 elem_size; 889 }; 890 891 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 892 .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 893 .init = mlxsw_pci_sdq_init, 894 .fini = mlxsw_pci_sdq_fini, 895 .dbg_read = mlxsw_pci_sdq_dbg_read, 896 .elem_count = MLXSW_PCI_WQE_COUNT, 897 .elem_size = MLXSW_PCI_WQE_SIZE, 898 }; 899 900 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 901 .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 902 .init = mlxsw_pci_rdq_init, 903 .fini = mlxsw_pci_rdq_fini, 904 .dbg_read = mlxsw_pci_rdq_dbg_read, 905 .elem_count = MLXSW_PCI_WQE_COUNT, 906 .elem_size = MLXSW_PCI_WQE_SIZE 907 }; 908 909 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 910 .type = MLXSW_PCI_QUEUE_TYPE_CQ, 911 .init = mlxsw_pci_cq_init, 912 .fini = mlxsw_pci_cq_fini, 913 .tasklet = mlxsw_pci_cq_tasklet, 914 .dbg_read = mlxsw_pci_cq_dbg_read, 915 .elem_count = MLXSW_PCI_CQE_COUNT, 916 .elem_size = MLXSW_PCI_CQE_SIZE 917 }; 918 919 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 920 .type = MLXSW_PCI_QUEUE_TYPE_EQ, 921 .init = mlxsw_pci_eq_init, 922 .fini = mlxsw_pci_eq_fini, 923 .tasklet = mlxsw_pci_eq_tasklet, 924 .dbg_read = mlxsw_pci_eq_dbg_read, 925 .elem_count = MLXSW_PCI_EQE_COUNT, 926 .elem_size = MLXSW_PCI_EQE_SIZE 927 }; 928 929 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 930 const struct mlxsw_pci_queue_ops *q_ops, 931 struct mlxsw_pci_queue *q, u8 q_num) 932 { 933 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 934 int i; 935 int err; 936 937 spin_lock_init(&q->lock); 938 q->num = q_num; 939 q->count = q_ops->elem_count; 940 q->elem_size = q_ops->elem_size; 941 q->type = q_ops->type; 942 q->pci = mlxsw_pci; 943 944 if (q_ops->tasklet) 945 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q); 946 947 mem_item->size = MLXSW_PCI_AQ_SIZE; 948 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 949 mem_item->size, 950 &mem_item->mapaddr); 951 if (!mem_item->buf) 952 return -ENOMEM; 953 memset(mem_item->buf, 0, mem_item->size); 954 955 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 956 if (!q->elem_info) { 957 err = -ENOMEM; 958 goto err_elem_info_alloc; 959 } 960 961 /* Initialize dma mapped elements info elem_info for 962 * future easy access. 963 */ 964 for (i = 0; i < q->count; i++) { 965 struct mlxsw_pci_queue_elem_info *elem_info; 966 967 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 968 elem_info->elem = 969 __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i); 970 } 971 972 mlxsw_cmd_mbox_zero(mbox); 973 err = q_ops->init(mlxsw_pci, mbox, q); 974 if (err) 975 goto err_q_ops_init; 976 return 0; 977 978 err_q_ops_init: 979 kfree(q->elem_info); 980 err_elem_info_alloc: 981 pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 982 mem_item->buf, mem_item->mapaddr); 983 return err; 984 } 985 986 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 987 const struct mlxsw_pci_queue_ops *q_ops, 988 struct mlxsw_pci_queue *q) 989 { 990 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 991 992 q_ops->fini(mlxsw_pci, q); 993 kfree(q->elem_info); 994 pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 995 mem_item->buf, mem_item->mapaddr); 996 } 997 998 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 999 const struct mlxsw_pci_queue_ops *q_ops, 1000 u8 num_qs) 1001 { 1002 struct pci_dev *pdev = mlxsw_pci->pdev; 1003 struct mlxsw_pci_queue_type_group *queue_group; 1004 char tmp[16]; 1005 int i; 1006 int err; 1007 1008 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1009 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 1010 if (!queue_group->q) 1011 return -ENOMEM; 1012 1013 for (i = 0; i < num_qs; i++) { 1014 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 1015 &queue_group->q[i], i); 1016 if (err) 1017 goto err_queue_init; 1018 } 1019 queue_group->count = num_qs; 1020 1021 sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type)); 1022 debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir, 1023 q_ops->dbg_read); 1024 1025 return 0; 1026 1027 err_queue_init: 1028 for (i--; i >= 0; i--) 1029 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1030 kfree(queue_group->q); 1031 return err; 1032 } 1033 1034 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 1035 const struct mlxsw_pci_queue_ops *q_ops) 1036 { 1037 struct mlxsw_pci_queue_type_group *queue_group; 1038 int i; 1039 1040 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1041 for (i = 0; i < queue_group->count; i++) 1042 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1043 kfree(queue_group->q); 1044 } 1045 1046 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1047 { 1048 struct pci_dev *pdev = mlxsw_pci->pdev; 1049 u8 num_sdqs; 1050 u8 sdq_log2sz; 1051 u8 num_rdqs; 1052 u8 rdq_log2sz; 1053 u8 num_cqs; 1054 u8 cq_log2sz; 1055 u8 num_eqs; 1056 u8 eq_log2sz; 1057 int err; 1058 1059 mlxsw_cmd_mbox_zero(mbox); 1060 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1061 if (err) 1062 return err; 1063 1064 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1065 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1066 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1067 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1068 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1069 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1070 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1071 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1072 1073 if (num_sdqs + num_rdqs > num_cqs || 1074 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 1075 dev_err(&pdev->dev, "Unsupported number of queues\n"); 1076 return -EINVAL; 1077 } 1078 1079 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1080 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1081 (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) || 1082 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1083 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1084 return -EINVAL; 1085 } 1086 1087 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1088 num_eqs); 1089 if (err) { 1090 dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1091 return err; 1092 } 1093 1094 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1095 num_cqs); 1096 if (err) { 1097 dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1098 goto err_cqs_init; 1099 } 1100 1101 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1102 num_sdqs); 1103 if (err) { 1104 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1105 goto err_sdqs_init; 1106 } 1107 1108 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1109 num_rdqs); 1110 if (err) { 1111 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1112 goto err_rdqs_init; 1113 } 1114 1115 /* We have to poll in command interface until queues are initialized */ 1116 mlxsw_pci->cmd.nopoll = true; 1117 return 0; 1118 1119 err_rdqs_init: 1120 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1121 err_sdqs_init: 1122 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1123 err_cqs_init: 1124 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1125 return err; 1126 } 1127 1128 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1129 { 1130 mlxsw_pci->cmd.nopoll = false; 1131 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1132 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1133 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1134 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1135 } 1136 1137 static void 1138 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1139 char *mbox, int index, 1140 const struct mlxsw_swid_config *swid) 1141 { 1142 u8 mask = 0; 1143 1144 if (swid->used_type) { 1145 mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1146 mbox, index, swid->type); 1147 mask |= 1; 1148 } 1149 if (swid->used_properties) { 1150 mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1151 mbox, index, swid->properties); 1152 mask |= 2; 1153 } 1154 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1155 } 1156 1157 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1158 const struct mlxsw_config_profile *profile) 1159 { 1160 int i; 1161 1162 mlxsw_cmd_mbox_zero(mbox); 1163 1164 if (profile->used_max_vepa_channels) { 1165 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1166 mbox, 1); 1167 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1168 mbox, profile->max_vepa_channels); 1169 } 1170 if (profile->used_max_lag) { 1171 mlxsw_cmd_mbox_config_profile_set_max_lag_set( 1172 mbox, 1); 1173 mlxsw_cmd_mbox_config_profile_max_lag_set( 1174 mbox, profile->max_lag); 1175 } 1176 if (profile->used_max_port_per_lag) { 1177 mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set( 1178 mbox, 1); 1179 mlxsw_cmd_mbox_config_profile_max_port_per_lag_set( 1180 mbox, profile->max_port_per_lag); 1181 } 1182 if (profile->used_max_mid) { 1183 mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1184 mbox, 1); 1185 mlxsw_cmd_mbox_config_profile_max_mid_set( 1186 mbox, profile->max_mid); 1187 } 1188 if (profile->used_max_pgt) { 1189 mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1190 mbox, 1); 1191 mlxsw_cmd_mbox_config_profile_max_pgt_set( 1192 mbox, profile->max_pgt); 1193 } 1194 if (profile->used_max_system_port) { 1195 mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1196 mbox, 1); 1197 mlxsw_cmd_mbox_config_profile_max_system_port_set( 1198 mbox, profile->max_system_port); 1199 } 1200 if (profile->used_max_vlan_groups) { 1201 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1202 mbox, 1); 1203 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1204 mbox, profile->max_vlan_groups); 1205 } 1206 if (profile->used_max_regions) { 1207 mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1208 mbox, 1); 1209 mlxsw_cmd_mbox_config_profile_max_regions_set( 1210 mbox, profile->max_regions); 1211 } 1212 if (profile->used_flood_tables) { 1213 mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1214 mbox, 1); 1215 mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1216 mbox, profile->max_flood_tables); 1217 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1218 mbox, profile->max_vid_flood_tables); 1219 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 1220 mbox, profile->max_fid_offset_flood_tables); 1221 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 1222 mbox, profile->fid_offset_flood_table_size); 1223 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1224 mbox, profile->max_fid_flood_tables); 1225 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1226 mbox, profile->fid_flood_table_size); 1227 } 1228 if (profile->used_flood_mode) { 1229 mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1230 mbox, 1); 1231 mlxsw_cmd_mbox_config_profile_flood_mode_set( 1232 mbox, profile->flood_mode); 1233 } 1234 if (profile->used_max_ib_mc) { 1235 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1236 mbox, 1); 1237 mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1238 mbox, profile->max_ib_mc); 1239 } 1240 if (profile->used_max_pkey) { 1241 mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1242 mbox, 1); 1243 mlxsw_cmd_mbox_config_profile_max_pkey_set( 1244 mbox, profile->max_pkey); 1245 } 1246 if (profile->used_ar_sec) { 1247 mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1248 mbox, 1); 1249 mlxsw_cmd_mbox_config_profile_ar_sec_set( 1250 mbox, profile->ar_sec); 1251 } 1252 if (profile->used_adaptive_routing_group_cap) { 1253 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1254 mbox, 1); 1255 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1256 mbox, profile->adaptive_routing_group_cap); 1257 } 1258 1259 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1260 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1261 &profile->swid_config[i]); 1262 1263 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1264 } 1265 1266 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1267 { 1268 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1269 int err; 1270 1271 mlxsw_cmd_mbox_zero(mbox); 1272 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1273 if (err) 1274 return err; 1275 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1276 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1277 return 0; 1278 } 1279 1280 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1281 u16 num_pages) 1282 { 1283 struct mlxsw_pci_mem_item *mem_item; 1284 int nent = 0; 1285 int i; 1286 int err; 1287 1288 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1289 GFP_KERNEL); 1290 if (!mlxsw_pci->fw_area.items) 1291 return -ENOMEM; 1292 mlxsw_pci->fw_area.count = num_pages; 1293 1294 mlxsw_cmd_mbox_zero(mbox); 1295 for (i = 0; i < num_pages; i++) { 1296 mem_item = &mlxsw_pci->fw_area.items[i]; 1297 1298 mem_item->size = MLXSW_PCI_PAGE_SIZE; 1299 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 1300 mem_item->size, 1301 &mem_item->mapaddr); 1302 if (!mem_item->buf) { 1303 err = -ENOMEM; 1304 goto err_alloc; 1305 } 1306 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 1307 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 1308 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 1309 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1310 if (err) 1311 goto err_cmd_map_fa; 1312 nent = 0; 1313 mlxsw_cmd_mbox_zero(mbox); 1314 } 1315 } 1316 1317 if (nent) { 1318 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1319 if (err) 1320 goto err_cmd_map_fa; 1321 } 1322 1323 return 0; 1324 1325 err_cmd_map_fa: 1326 err_alloc: 1327 for (i--; i >= 0; i--) { 1328 mem_item = &mlxsw_pci->fw_area.items[i]; 1329 1330 pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1331 mem_item->buf, mem_item->mapaddr); 1332 } 1333 kfree(mlxsw_pci->fw_area.items); 1334 return err; 1335 } 1336 1337 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1338 { 1339 struct mlxsw_pci_mem_item *mem_item; 1340 int i; 1341 1342 mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1343 1344 for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1345 mem_item = &mlxsw_pci->fw_area.items[i]; 1346 1347 pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1348 mem_item->buf, mem_item->mapaddr); 1349 } 1350 kfree(mlxsw_pci->fw_area.items); 1351 } 1352 1353 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1354 { 1355 struct mlxsw_pci *mlxsw_pci = dev_id; 1356 struct mlxsw_pci_queue *q; 1357 int i; 1358 1359 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1360 q = mlxsw_pci_eq_get(mlxsw_pci, i); 1361 mlxsw_pci_queue_tasklet_schedule(q); 1362 } 1363 return IRQ_HANDLED; 1364 } 1365 1366 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 1367 struct mlxsw_pci_mem_item *mbox) 1368 { 1369 struct pci_dev *pdev = mlxsw_pci->pdev; 1370 int err = 0; 1371 1372 mbox->size = MLXSW_CMD_MBOX_SIZE; 1373 mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE, 1374 &mbox->mapaddr); 1375 if (!mbox->buf) { 1376 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 1377 err = -ENOMEM; 1378 } 1379 1380 return err; 1381 } 1382 1383 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 1384 struct mlxsw_pci_mem_item *mbox) 1385 { 1386 struct pci_dev *pdev = mlxsw_pci->pdev; 1387 1388 pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 1389 mbox->mapaddr); 1390 } 1391 1392 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1393 const struct mlxsw_config_profile *profile) 1394 { 1395 struct mlxsw_pci *mlxsw_pci = bus_priv; 1396 struct pci_dev *pdev = mlxsw_pci->pdev; 1397 char *mbox; 1398 u16 num_pages; 1399 int err; 1400 1401 mutex_init(&mlxsw_pci->cmd.lock); 1402 init_waitqueue_head(&mlxsw_pci->cmd.wait); 1403 1404 mlxsw_pci->core = mlxsw_core; 1405 1406 mbox = mlxsw_cmd_mbox_alloc(); 1407 if (!mbox) 1408 return -ENOMEM; 1409 1410 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1411 if (err) 1412 goto mbox_put; 1413 1414 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1415 if (err) 1416 goto err_out_mbox_alloc; 1417 1418 err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1419 if (err) 1420 goto err_query_fw; 1421 1422 mlxsw_pci->bus_info.fw_rev.major = 1423 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1424 mlxsw_pci->bus_info.fw_rev.minor = 1425 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1426 mlxsw_pci->bus_info.fw_rev.subminor = 1427 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1428 1429 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1430 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1431 err = -EINVAL; 1432 goto err_iface_rev; 1433 } 1434 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1435 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1436 err = -EINVAL; 1437 goto err_doorbell_page_bar; 1438 } 1439 1440 mlxsw_pci->doorbell_offset = 1441 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1442 1443 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1444 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1445 if (err) 1446 goto err_fw_area_init; 1447 1448 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1449 if (err) 1450 goto err_boardinfo; 1451 1452 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile); 1453 if (err) 1454 goto err_config_profile; 1455 1456 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1457 if (err) 1458 goto err_aqs_init; 1459 1460 err = request_irq(mlxsw_pci->msix_entry.vector, 1461 mlxsw_pci_eq_irq_handler, 0, 1462 mlxsw_pci_driver_name, mlxsw_pci); 1463 if (err) { 1464 dev_err(&pdev->dev, "IRQ request failed\n"); 1465 goto err_request_eq_irq; 1466 } 1467 1468 goto mbox_put; 1469 1470 err_request_eq_irq: 1471 mlxsw_pci_aqs_fini(mlxsw_pci); 1472 err_aqs_init: 1473 err_config_profile: 1474 err_boardinfo: 1475 mlxsw_pci_fw_area_fini(mlxsw_pci); 1476 err_fw_area_init: 1477 err_doorbell_page_bar: 1478 err_iface_rev: 1479 err_query_fw: 1480 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1481 err_out_mbox_alloc: 1482 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1483 mbox_put: 1484 mlxsw_cmd_mbox_free(mbox); 1485 return err; 1486 } 1487 1488 static void mlxsw_pci_fini(void *bus_priv) 1489 { 1490 struct mlxsw_pci *mlxsw_pci = bus_priv; 1491 1492 free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci); 1493 mlxsw_pci_aqs_fini(mlxsw_pci); 1494 mlxsw_pci_fw_area_fini(mlxsw_pci); 1495 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1496 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1497 } 1498 1499 static struct mlxsw_pci_queue * 1500 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1501 const struct mlxsw_tx_info *tx_info) 1502 { 1503 u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci); 1504 1505 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1506 } 1507 1508 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1509 const struct mlxsw_tx_info *tx_info) 1510 { 1511 struct mlxsw_pci *mlxsw_pci = bus_priv; 1512 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1513 1514 return !mlxsw_pci_queue_elem_info_producer_get(q); 1515 } 1516 1517 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1518 const struct mlxsw_tx_info *tx_info) 1519 { 1520 struct mlxsw_pci *mlxsw_pci = bus_priv; 1521 struct mlxsw_pci_queue *q; 1522 struct mlxsw_pci_queue_elem_info *elem_info; 1523 char *wqe; 1524 int i; 1525 int err; 1526 1527 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1528 err = skb_linearize(skb); 1529 if (err) 1530 return err; 1531 } 1532 1533 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1534 spin_lock_bh(&q->lock); 1535 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1536 if (!elem_info) { 1537 /* queue is full */ 1538 err = -EAGAIN; 1539 goto unlock; 1540 } 1541 elem_info->u.sdq.skb = skb; 1542 1543 wqe = elem_info->elem; 1544 mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1545 mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1546 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1547 1548 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1549 skb_headlen(skb), DMA_TO_DEVICE); 1550 if (err) 1551 goto unlock; 1552 1553 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1554 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1555 1556 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1557 skb_frag_address(frag), 1558 skb_frag_size(frag), 1559 DMA_TO_DEVICE); 1560 if (err) 1561 goto unmap_frags; 1562 } 1563 1564 /* Set unused sq entries byte count to zero. */ 1565 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1566 mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1567 1568 /* Everything is set up, ring producer doorbell to get HW going */ 1569 q->producer_counter++; 1570 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1571 1572 goto unlock; 1573 1574 unmap_frags: 1575 for (; i >= 0; i--) 1576 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1577 unlock: 1578 spin_unlock_bh(&q->lock); 1579 return err; 1580 } 1581 1582 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1583 u32 in_mod, bool out_mbox_direct, 1584 char *in_mbox, size_t in_mbox_size, 1585 char *out_mbox, size_t out_mbox_size, 1586 u8 *p_status) 1587 { 1588 struct mlxsw_pci *mlxsw_pci = bus_priv; 1589 dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 1590 dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1591 bool evreq = mlxsw_pci->cmd.nopoll; 1592 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1593 bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1594 int err; 1595 1596 *p_status = MLXSW_CMD_STATUS_OK; 1597 1598 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1599 if (err) 1600 return err; 1601 1602 if (in_mbox) 1603 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1604 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 1605 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 1606 1607 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 1608 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 1609 1610 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1611 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1612 1613 *p_wait_done = false; 1614 1615 wmb(); /* all needs to be written before we write control register */ 1616 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1617 MLXSW_PCI_CIR_CTRL_GO_BIT | 1618 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1619 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1620 opcode); 1621 1622 if (!evreq) { 1623 unsigned long end; 1624 1625 end = jiffies + timeout; 1626 do { 1627 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1628 1629 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1630 *p_wait_done = true; 1631 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1632 break; 1633 } 1634 cond_resched(); 1635 } while (time_before(jiffies, end)); 1636 } else { 1637 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1638 *p_status = mlxsw_pci->cmd.comp.status; 1639 } 1640 1641 err = 0; 1642 if (*p_wait_done) { 1643 if (*p_status) 1644 err = -EIO; 1645 } else { 1646 err = -ETIMEDOUT; 1647 } 1648 1649 if (!err && out_mbox && out_mbox_direct) { 1650 /* Some commands don't use output param as address to mailbox 1651 * but they store output directly into registers. In that case, 1652 * copy registers into mbox buffer. 1653 */ 1654 __be32 tmp; 1655 1656 if (!evreq) { 1657 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1658 CIR_OUT_PARAM_HI)); 1659 memcpy(out_mbox, &tmp, sizeof(tmp)); 1660 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1661 CIR_OUT_PARAM_LO)); 1662 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1663 } 1664 } else if (!err && out_mbox) { 1665 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1666 } 1667 1668 mutex_unlock(&mlxsw_pci->cmd.lock); 1669 1670 return err; 1671 } 1672 1673 static const struct mlxsw_bus mlxsw_pci_bus = { 1674 .kind = "pci", 1675 .init = mlxsw_pci_init, 1676 .fini = mlxsw_pci_fini, 1677 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 1678 .skb_transmit = mlxsw_pci_skb_transmit, 1679 .cmd_exec = mlxsw_pci_cmd_exec, 1680 }; 1681 1682 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci) 1683 { 1684 unsigned long end; 1685 1686 mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT); 1687 wmb(); /* reset needs to be written before we read control register */ 1688 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1689 do { 1690 u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1691 1692 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 1693 break; 1694 cond_resched(); 1695 } while (time_before(jiffies, end)); 1696 return 0; 1697 } 1698 1699 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1700 { 1701 struct mlxsw_pci *mlxsw_pci; 1702 int err; 1703 1704 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1705 if (!mlxsw_pci) 1706 return -ENOMEM; 1707 1708 err = pci_enable_device(pdev); 1709 if (err) { 1710 dev_err(&pdev->dev, "pci_enable_device failed\n"); 1711 goto err_pci_enable_device; 1712 } 1713 1714 err = pci_request_regions(pdev, mlxsw_pci_driver_name); 1715 if (err) { 1716 dev_err(&pdev->dev, "pci_request_regions failed\n"); 1717 goto err_pci_request_regions; 1718 } 1719 1720 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1721 if (!err) { 1722 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1723 if (err) { 1724 dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n"); 1725 goto err_pci_set_dma_mask; 1726 } 1727 } else { 1728 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1729 if (err) { 1730 dev_err(&pdev->dev, "pci_set_dma_mask failed\n"); 1731 goto err_pci_set_dma_mask; 1732 } 1733 } 1734 1735 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1736 dev_err(&pdev->dev, "invalid PCI region size\n"); 1737 err = -EINVAL; 1738 goto err_pci_resource_len_check; 1739 } 1740 1741 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1742 pci_resource_len(pdev, 0)); 1743 if (!mlxsw_pci->hw_addr) { 1744 dev_err(&pdev->dev, "ioremap failed\n"); 1745 err = -EIO; 1746 goto err_ioremap; 1747 } 1748 pci_set_master(pdev); 1749 1750 mlxsw_pci->pdev = pdev; 1751 pci_set_drvdata(pdev, mlxsw_pci); 1752 1753 err = mlxsw_pci_sw_reset(mlxsw_pci); 1754 if (err) { 1755 dev_err(&pdev->dev, "Software reset failed\n"); 1756 goto err_sw_reset; 1757 } 1758 1759 err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1); 1760 if (err) { 1761 dev_err(&pdev->dev, "MSI-X init failed\n"); 1762 goto err_msix_init; 1763 } 1764 1765 mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id); 1766 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1767 mlxsw_pci->bus_info.dev = &pdev->dev; 1768 1769 mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name, 1770 mlxsw_pci_dbg_root); 1771 if (!mlxsw_pci->dbg_dir) { 1772 dev_err(&pdev->dev, "Failed to create debugfs dir\n"); 1773 err = -ENOMEM; 1774 goto err_dbg_create_dir; 1775 } 1776 1777 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 1778 &mlxsw_pci_bus, mlxsw_pci); 1779 if (err) { 1780 dev_err(&pdev->dev, "cannot register bus device\n"); 1781 goto err_bus_device_register; 1782 } 1783 1784 return 0; 1785 1786 err_bus_device_register: 1787 debugfs_remove_recursive(mlxsw_pci->dbg_dir); 1788 err_dbg_create_dir: 1789 pci_disable_msix(mlxsw_pci->pdev); 1790 err_msix_init: 1791 err_sw_reset: 1792 iounmap(mlxsw_pci->hw_addr); 1793 err_ioremap: 1794 err_pci_resource_len_check: 1795 err_pci_set_dma_mask: 1796 pci_release_regions(pdev); 1797 err_pci_request_regions: 1798 pci_disable_device(pdev); 1799 err_pci_enable_device: 1800 kfree(mlxsw_pci); 1801 return err; 1802 } 1803 1804 static void mlxsw_pci_remove(struct pci_dev *pdev) 1805 { 1806 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1807 1808 mlxsw_core_bus_device_unregister(mlxsw_pci->core); 1809 debugfs_remove_recursive(mlxsw_pci->dbg_dir); 1810 pci_disable_msix(mlxsw_pci->pdev); 1811 iounmap(mlxsw_pci->hw_addr); 1812 pci_release_regions(mlxsw_pci->pdev); 1813 pci_disable_device(mlxsw_pci->pdev); 1814 kfree(mlxsw_pci); 1815 } 1816 1817 static struct pci_driver mlxsw_pci_driver = { 1818 .name = mlxsw_pci_driver_name, 1819 .id_table = mlxsw_pci_id_table, 1820 .probe = mlxsw_pci_probe, 1821 .remove = mlxsw_pci_remove, 1822 }; 1823 1824 static int __init mlxsw_pci_module_init(void) 1825 { 1826 int err; 1827 1828 mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL); 1829 if (!mlxsw_pci_dbg_root) 1830 return -ENOMEM; 1831 err = pci_register_driver(&mlxsw_pci_driver); 1832 if (err) 1833 goto err_register_driver; 1834 return 0; 1835 1836 err_register_driver: 1837 debugfs_remove_recursive(mlxsw_pci_dbg_root); 1838 return err; 1839 } 1840 1841 static void __exit mlxsw_pci_module_exit(void) 1842 { 1843 pci_unregister_driver(&mlxsw_pci_driver); 1844 debugfs_remove_recursive(mlxsw_pci_dbg_root); 1845 } 1846 1847 module_init(mlxsw_pci_module_init); 1848 module_exit(mlxsw_pci_module_exit); 1849 1850 MODULE_LICENSE("Dual BSD/GPL"); 1851 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 1852 MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 1853 MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table); 1854