1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/export.h> 7 #include <linux/err.h> 8 #include <linux/device.h> 9 #include <linux/pci.h> 10 #include <linux/interrupt.h> 11 #include <linux/wait.h> 12 #include <linux/types.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/log2.h> 16 #include <linux/string.h> 17 18 #include "pci_hw.h" 19 #include "pci.h" 20 #include "core.h" 21 #include "cmd.h" 22 #include "port.h" 23 #include "resources.h" 24 25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 26 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 27 #define mlxsw_pci_read32(mlxsw_pci, reg) \ 28 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 29 30 enum mlxsw_pci_queue_type { 31 MLXSW_PCI_QUEUE_TYPE_SDQ, 32 MLXSW_PCI_QUEUE_TYPE_RDQ, 33 MLXSW_PCI_QUEUE_TYPE_CQ, 34 MLXSW_PCI_QUEUE_TYPE_EQ, 35 }; 36 37 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 38 39 static const u16 mlxsw_pci_doorbell_type_offset[] = { 40 MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 41 MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 42 MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 43 MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 44 }; 45 46 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 47 0, /* unused */ 48 0, /* unused */ 49 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 50 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 51 }; 52 53 struct mlxsw_pci_mem_item { 54 char *buf; 55 dma_addr_t mapaddr; 56 size_t size; 57 }; 58 59 struct mlxsw_pci_queue_elem_info { 60 char *elem; /* pointer to actual dma mapped element mem chunk */ 61 union { 62 struct { 63 struct sk_buff *skb; 64 } sdq; 65 struct { 66 struct sk_buff *skb; 67 } rdq; 68 } u; 69 }; 70 71 struct mlxsw_pci_queue { 72 spinlock_t lock; /* for queue accesses */ 73 struct mlxsw_pci_mem_item mem_item; 74 struct mlxsw_pci_queue_elem_info *elem_info; 75 u16 producer_counter; 76 u16 consumer_counter; 77 u16 count; /* number of elements in queue */ 78 u8 num; /* queue number */ 79 u8 elem_size; /* size of one element */ 80 enum mlxsw_pci_queue_type type; 81 struct tasklet_struct tasklet; /* queue processing tasklet */ 82 struct mlxsw_pci *pci; 83 union { 84 struct { 85 u32 comp_sdq_count; 86 u32 comp_rdq_count; 87 enum mlxsw_pci_cqe_v v; 88 } cq; 89 struct { 90 u32 ev_cmd_count; 91 u32 ev_comp_count; 92 u32 ev_other_count; 93 } eq; 94 } u; 95 }; 96 97 struct mlxsw_pci_queue_type_group { 98 struct mlxsw_pci_queue *q; 99 u8 count; /* number of queues in group */ 100 }; 101 102 struct mlxsw_pci { 103 struct pci_dev *pdev; 104 u8 __iomem *hw_addr; 105 u64 free_running_clock_offset; 106 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 107 u32 doorbell_offset; 108 struct mlxsw_core *core; 109 struct { 110 struct mlxsw_pci_mem_item *items; 111 unsigned int count; 112 } fw_area; 113 struct { 114 struct mlxsw_pci_mem_item out_mbox; 115 struct mlxsw_pci_mem_item in_mbox; 116 struct mutex lock; /* Lock access to command registers */ 117 bool nopoll; 118 wait_queue_head_t wait; 119 bool wait_done; 120 struct { 121 u8 status; 122 u64 out_param; 123 } comp; 124 } cmd; 125 struct mlxsw_bus_info bus_info; 126 const struct pci_device_id *id; 127 enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ 128 u8 num_sdq_cqs; /* Number of CQs used for SDQs */ 129 }; 130 131 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 132 { 133 tasklet_schedule(&q->tasklet); 134 } 135 136 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 137 size_t elem_size, int elem_index) 138 { 139 return q->mem_item.buf + (elem_size * elem_index); 140 } 141 142 static struct mlxsw_pci_queue_elem_info * 143 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 144 { 145 return &q->elem_info[elem_index]; 146 } 147 148 static struct mlxsw_pci_queue_elem_info * 149 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 150 { 151 int index = q->producer_counter & (q->count - 1); 152 153 if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 154 return NULL; 155 return mlxsw_pci_queue_elem_info_get(q, index); 156 } 157 158 static struct mlxsw_pci_queue_elem_info * 159 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 160 { 161 int index = q->consumer_counter & (q->count - 1); 162 163 return mlxsw_pci_queue_elem_info_get(q, index); 164 } 165 166 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 167 { 168 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 169 } 170 171 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 172 { 173 return owner_bit != !!(q->consumer_counter & q->count); 174 } 175 176 static struct mlxsw_pci_queue_type_group * 177 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 178 enum mlxsw_pci_queue_type q_type) 179 { 180 return &mlxsw_pci->queues[q_type]; 181 } 182 183 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 184 enum mlxsw_pci_queue_type q_type) 185 { 186 struct mlxsw_pci_queue_type_group *queue_group; 187 188 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 189 return queue_group->count; 190 } 191 192 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 193 { 194 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 195 } 196 197 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 198 { 199 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 200 } 201 202 static struct mlxsw_pci_queue * 203 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 204 enum mlxsw_pci_queue_type q_type, u8 q_num) 205 { 206 return &mlxsw_pci->queues[q_type].q[q_num]; 207 } 208 209 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 210 u8 q_num) 211 { 212 return __mlxsw_pci_queue_get(mlxsw_pci, 213 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 214 } 215 216 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 217 u8 q_num) 218 { 219 return __mlxsw_pci_queue_get(mlxsw_pci, 220 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 221 } 222 223 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 224 u8 q_num) 225 { 226 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 227 } 228 229 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 230 u8 q_num) 231 { 232 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 233 } 234 235 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 236 struct mlxsw_pci_queue *q, 237 u16 val) 238 { 239 mlxsw_pci_write32(mlxsw_pci, 240 DOORBELL(mlxsw_pci->doorbell_offset, 241 mlxsw_pci_doorbell_type_offset[q->type], 242 q->num), val); 243 } 244 245 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 246 struct mlxsw_pci_queue *q, 247 u16 val) 248 { 249 mlxsw_pci_write32(mlxsw_pci, 250 DOORBELL(mlxsw_pci->doorbell_offset, 251 mlxsw_pci_doorbell_arm_type_offset[q->type], 252 q->num), val); 253 } 254 255 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 256 struct mlxsw_pci_queue *q) 257 { 258 wmb(); /* ensure all writes are done before we ring a bell */ 259 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 260 } 261 262 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 263 struct mlxsw_pci_queue *q) 264 { 265 wmb(); /* ensure all writes are done before we ring a bell */ 266 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 267 q->consumer_counter + q->count); 268 } 269 270 static void 271 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 272 struct mlxsw_pci_queue *q) 273 { 274 wmb(); /* ensure all writes are done before we ring a bell */ 275 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 276 } 277 278 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 279 int page_index) 280 { 281 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 282 } 283 284 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 285 struct mlxsw_pci_queue *q) 286 { 287 int tclass; 288 int i; 289 int err; 290 291 q->producer_counter = 0; 292 q->consumer_counter = 0; 293 tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC : 294 MLXSW_PCI_SDQ_CTL_TC; 295 296 /* Set CQ of same number of this SDQ. */ 297 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 298 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass); 299 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 300 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 301 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 302 303 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 304 } 305 306 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 307 if (err) 308 return err; 309 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 310 return 0; 311 } 312 313 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 314 struct mlxsw_pci_queue *q) 315 { 316 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 317 } 318 319 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 320 int index, char *frag_data, size_t frag_len, 321 int direction) 322 { 323 struct pci_dev *pdev = mlxsw_pci->pdev; 324 dma_addr_t mapaddr; 325 326 mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction); 327 if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) { 328 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 329 return -EIO; 330 } 331 mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 332 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 333 return 0; 334 } 335 336 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 337 int index, int direction) 338 { 339 struct pci_dev *pdev = mlxsw_pci->pdev; 340 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 341 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 342 343 if (!frag_len) 344 return; 345 dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); 346 } 347 348 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 349 struct mlxsw_pci_queue_elem_info *elem_info) 350 { 351 size_t buf_len = MLXSW_PORT_MAX_MTU; 352 char *wqe = elem_info->elem; 353 struct sk_buff *skb; 354 int err; 355 356 elem_info->u.rdq.skb = NULL; 357 skb = netdev_alloc_skb_ip_align(NULL, buf_len); 358 if (!skb) 359 return -ENOMEM; 360 361 /* Assume that wqe was previously zeroed. */ 362 363 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 364 buf_len, DMA_FROM_DEVICE); 365 if (err) 366 goto err_frag_map; 367 368 elem_info->u.rdq.skb = skb; 369 return 0; 370 371 err_frag_map: 372 dev_kfree_skb_any(skb); 373 return err; 374 } 375 376 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 377 struct mlxsw_pci_queue_elem_info *elem_info) 378 { 379 struct sk_buff *skb; 380 char *wqe; 381 382 skb = elem_info->u.rdq.skb; 383 wqe = elem_info->elem; 384 385 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 386 dev_kfree_skb_any(skb); 387 } 388 389 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 390 struct mlxsw_pci_queue *q) 391 { 392 struct mlxsw_pci_queue_elem_info *elem_info; 393 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 394 int i; 395 int err; 396 397 q->producer_counter = 0; 398 q->consumer_counter = 0; 399 400 /* Set CQ of same number of this RDQ with base 401 * above SDQ count as the lower ones are assigned to SDQs. 402 */ 403 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 404 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 405 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 406 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 407 408 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 409 } 410 411 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 412 if (err) 413 return err; 414 415 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 416 417 for (i = 0; i < q->count; i++) { 418 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 419 BUG_ON(!elem_info); 420 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 421 if (err) 422 goto rollback; 423 /* Everything is set up, ring doorbell to pass elem to HW */ 424 q->producer_counter++; 425 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 426 } 427 428 return 0; 429 430 rollback: 431 for (i--; i >= 0; i--) { 432 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 433 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 434 } 435 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 436 437 return err; 438 } 439 440 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 441 struct mlxsw_pci_queue *q) 442 { 443 struct mlxsw_pci_queue_elem_info *elem_info; 444 int i; 445 446 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 447 for (i = 0; i < q->count; i++) { 448 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 449 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 450 } 451 } 452 453 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci, 454 struct mlxsw_pci_queue *q) 455 { 456 q->u.cq.v = mlxsw_pci->max_cqe_ver; 457 458 /* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */ 459 if (q->u.cq.v == MLXSW_PCI_CQE_V2 && 460 q->num < mlxsw_pci->num_sdq_cqs) 461 q->u.cq.v = MLXSW_PCI_CQE_V1; 462 } 463 464 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 465 struct mlxsw_pci_queue *q) 466 { 467 int i; 468 int err; 469 470 q->consumer_counter = 0; 471 472 for (i = 0; i < q->count; i++) { 473 char *elem = mlxsw_pci_queue_elem_get(q, i); 474 475 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1); 476 } 477 478 if (q->u.cq.v == MLXSW_PCI_CQE_V1) 479 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 480 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1); 481 else if (q->u.cq.v == MLXSW_PCI_CQE_V2) 482 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 483 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2); 484 485 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 486 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 487 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 488 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 489 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 490 491 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 492 } 493 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 494 if (err) 495 return err; 496 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 497 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 498 return 0; 499 } 500 501 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 502 struct mlxsw_pci_queue *q) 503 { 504 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 505 } 506 507 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 508 struct mlxsw_pci_queue *q, 509 u16 consumer_counter_limit, 510 char *cqe) 511 { 512 struct pci_dev *pdev = mlxsw_pci->pdev; 513 struct mlxsw_pci_queue_elem_info *elem_info; 514 struct mlxsw_tx_info tx_info; 515 char *wqe; 516 struct sk_buff *skb; 517 int i; 518 519 spin_lock(&q->lock); 520 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 521 tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info; 522 skb = elem_info->u.sdq.skb; 523 wqe = elem_info->elem; 524 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 525 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 526 527 if (unlikely(!tx_info.is_emad && 528 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 529 mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb, 530 tx_info.local_port); 531 skb = NULL; 532 } 533 534 if (skb) 535 dev_kfree_skb_any(skb); 536 elem_info->u.sdq.skb = NULL; 537 538 if (q->consumer_counter++ != consumer_counter_limit) 539 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 540 spin_unlock(&q->lock); 541 } 542 543 static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb, 544 const char *cqe) 545 { 546 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 547 548 if (mlxsw_pci_cqe2_tx_lag_get(cqe)) { 549 cb->rx_md_info.tx_port_is_lag = true; 550 cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe); 551 cb->rx_md_info.tx_lag_port_index = 552 mlxsw_pci_cqe2_tx_lag_subport_get(cqe); 553 } else { 554 cb->rx_md_info.tx_port_is_lag = false; 555 cb->rx_md_info.tx_sys_port = 556 mlxsw_pci_cqe2_tx_system_port_get(cqe); 557 } 558 559 if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT && 560 cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID) 561 cb->rx_md_info.tx_port_valid = 1; 562 else 563 cb->rx_md_info.tx_port_valid = 0; 564 } 565 566 static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe) 567 { 568 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 569 570 cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe); 571 if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID) 572 cb->rx_md_info.tx_congestion_valid = 1; 573 else 574 cb->rx_md_info.tx_congestion_valid = 0; 575 cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT; 576 577 cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe); 578 if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID) 579 cb->rx_md_info.latency_valid = 1; 580 else 581 cb->rx_md_info.latency_valid = 0; 582 583 cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe); 584 if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID) 585 cb->rx_md_info.tx_tc_valid = 1; 586 else 587 cb->rx_md_info.tx_tc_valid = 0; 588 589 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 590 } 591 592 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 593 struct mlxsw_pci_queue *q, 594 u16 consumer_counter_limit, 595 enum mlxsw_pci_cqe_v cqe_v, char *cqe) 596 { 597 struct pci_dev *pdev = mlxsw_pci->pdev; 598 struct mlxsw_pci_queue_elem_info *elem_info; 599 struct mlxsw_rx_info rx_info = {}; 600 char *wqe; 601 struct sk_buff *skb; 602 u16 byte_count; 603 int err; 604 605 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 606 skb = elem_info->u.sdq.skb; 607 if (!skb) 608 return; 609 wqe = elem_info->elem; 610 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 611 612 if (q->consumer_counter++ != consumer_counter_limit) 613 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 614 615 if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { 616 rx_info.is_lag = true; 617 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); 618 rx_info.lag_port_index = 619 mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); 620 } else { 621 rx_info.is_lag = false; 622 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 623 } 624 625 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 626 627 if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL || 628 rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) { 629 u32 cookie_index = 0; 630 631 if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) 632 cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe); 633 mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index; 634 } else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 && 635 rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 && 636 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 637 rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe); 638 mlxsw_pci_cqe_rdq_md_init(skb, cqe); 639 } else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE && 640 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 641 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 642 } 643 644 byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 645 if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) 646 byte_count -= ETH_FCS_LEN; 647 skb_put(skb, byte_count); 648 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 649 650 memset(wqe, 0, q->elem_size); 651 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 652 if (err) 653 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); 654 /* Everything is set up, ring doorbell to pass elem to HW */ 655 q->producer_counter++; 656 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 657 return; 658 } 659 660 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 661 { 662 struct mlxsw_pci_queue_elem_info *elem_info; 663 char *elem; 664 bool owner_bit; 665 666 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 667 elem = elem_info->elem; 668 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem); 669 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 670 return NULL; 671 q->consumer_counter++; 672 rmb(); /* make sure we read owned bit before the rest of elem */ 673 return elem; 674 } 675 676 static void mlxsw_pci_cq_tasklet(struct tasklet_struct *t) 677 { 678 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 679 struct mlxsw_pci *mlxsw_pci = q->pci; 680 char *cqe; 681 int items = 0; 682 int credits = q->count >> 1; 683 684 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 685 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 686 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 687 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 688 char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; 689 690 memcpy(ncqe, cqe, q->elem_size); 691 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 692 693 if (sendq) { 694 struct mlxsw_pci_queue *sdq; 695 696 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 697 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 698 wqe_counter, ncqe); 699 q->u.cq.comp_sdq_count++; 700 } else { 701 struct mlxsw_pci_queue *rdq; 702 703 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 704 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 705 wqe_counter, q->u.cq.v, ncqe); 706 q->u.cq.comp_rdq_count++; 707 } 708 if (++items == credits) 709 break; 710 } 711 if (items) 712 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 713 } 714 715 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q) 716 { 717 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT : 718 MLXSW_PCI_CQE01_COUNT; 719 } 720 721 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q) 722 { 723 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE : 724 MLXSW_PCI_CQE01_SIZE; 725 } 726 727 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 728 struct mlxsw_pci_queue *q) 729 { 730 int i; 731 int err; 732 733 q->consumer_counter = 0; 734 735 for (i = 0; i < q->count; i++) { 736 char *elem = mlxsw_pci_queue_elem_get(q, i); 737 738 mlxsw_pci_eqe_owner_set(elem, 1); 739 } 740 741 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 742 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 743 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 744 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 745 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 746 747 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 748 } 749 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 750 if (err) 751 return err; 752 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 753 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 754 return 0; 755 } 756 757 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 758 struct mlxsw_pci_queue *q) 759 { 760 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 761 } 762 763 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 764 { 765 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 766 mlxsw_pci->cmd.comp.out_param = 767 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 768 mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 769 mlxsw_pci->cmd.wait_done = true; 770 wake_up(&mlxsw_pci->cmd.wait); 771 } 772 773 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 774 { 775 struct mlxsw_pci_queue_elem_info *elem_info; 776 char *elem; 777 bool owner_bit; 778 779 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 780 elem = elem_info->elem; 781 owner_bit = mlxsw_pci_eqe_owner_get(elem); 782 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 783 return NULL; 784 q->consumer_counter++; 785 rmb(); /* make sure we read owned bit before the rest of elem */ 786 return elem; 787 } 788 789 static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t) 790 { 791 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 792 struct mlxsw_pci *mlxsw_pci = q->pci; 793 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 794 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 795 char *eqe; 796 u8 cqn; 797 bool cq_handle = false; 798 int items = 0; 799 int credits = q->count >> 1; 800 801 memset(&active_cqns, 0, sizeof(active_cqns)); 802 803 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 804 805 /* Command interface completion events are always received on 806 * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events 807 * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1). 808 */ 809 switch (q->num) { 810 case MLXSW_PCI_EQ_ASYNC_NUM: 811 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 812 q->u.eq.ev_cmd_count++; 813 break; 814 case MLXSW_PCI_EQ_COMP_NUM: 815 cqn = mlxsw_pci_eqe_cqn_get(eqe); 816 set_bit(cqn, active_cqns); 817 cq_handle = true; 818 q->u.eq.ev_comp_count++; 819 break; 820 default: 821 q->u.eq.ev_other_count++; 822 } 823 if (++items == credits) 824 break; 825 } 826 if (items) { 827 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 828 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 829 } 830 831 if (!cq_handle) 832 return; 833 for_each_set_bit(cqn, active_cqns, cq_count) { 834 q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 835 mlxsw_pci_queue_tasklet_schedule(q); 836 } 837 } 838 839 struct mlxsw_pci_queue_ops { 840 const char *name; 841 enum mlxsw_pci_queue_type type; 842 void (*pre_init)(struct mlxsw_pci *mlxsw_pci, 843 struct mlxsw_pci_queue *q); 844 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 845 struct mlxsw_pci_queue *q); 846 void (*fini)(struct mlxsw_pci *mlxsw_pci, 847 struct mlxsw_pci_queue *q); 848 void (*tasklet)(struct tasklet_struct *t); 849 u16 (*elem_count_f)(const struct mlxsw_pci_queue *q); 850 u8 (*elem_size_f)(const struct mlxsw_pci_queue *q); 851 u16 elem_count; 852 u8 elem_size; 853 }; 854 855 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 856 .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 857 .init = mlxsw_pci_sdq_init, 858 .fini = mlxsw_pci_sdq_fini, 859 .elem_count = MLXSW_PCI_WQE_COUNT, 860 .elem_size = MLXSW_PCI_WQE_SIZE, 861 }; 862 863 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 864 .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 865 .init = mlxsw_pci_rdq_init, 866 .fini = mlxsw_pci_rdq_fini, 867 .elem_count = MLXSW_PCI_WQE_COUNT, 868 .elem_size = MLXSW_PCI_WQE_SIZE 869 }; 870 871 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 872 .type = MLXSW_PCI_QUEUE_TYPE_CQ, 873 .pre_init = mlxsw_pci_cq_pre_init, 874 .init = mlxsw_pci_cq_init, 875 .fini = mlxsw_pci_cq_fini, 876 .tasklet = mlxsw_pci_cq_tasklet, 877 .elem_count_f = mlxsw_pci_cq_elem_count, 878 .elem_size_f = mlxsw_pci_cq_elem_size 879 }; 880 881 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 882 .type = MLXSW_PCI_QUEUE_TYPE_EQ, 883 .init = mlxsw_pci_eq_init, 884 .fini = mlxsw_pci_eq_fini, 885 .tasklet = mlxsw_pci_eq_tasklet, 886 .elem_count = MLXSW_PCI_EQE_COUNT, 887 .elem_size = MLXSW_PCI_EQE_SIZE 888 }; 889 890 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 891 const struct mlxsw_pci_queue_ops *q_ops, 892 struct mlxsw_pci_queue *q, u8 q_num) 893 { 894 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 895 int i; 896 int err; 897 898 q->num = q_num; 899 if (q_ops->pre_init) 900 q_ops->pre_init(mlxsw_pci, q); 901 902 spin_lock_init(&q->lock); 903 q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) : 904 q_ops->elem_count; 905 q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) : 906 q_ops->elem_size; 907 q->type = q_ops->type; 908 q->pci = mlxsw_pci; 909 910 if (q_ops->tasklet) 911 tasklet_setup(&q->tasklet, q_ops->tasklet); 912 913 mem_item->size = MLXSW_PCI_AQ_SIZE; 914 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 915 mem_item->size, &mem_item->mapaddr, 916 GFP_KERNEL); 917 if (!mem_item->buf) 918 return -ENOMEM; 919 920 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 921 if (!q->elem_info) { 922 err = -ENOMEM; 923 goto err_elem_info_alloc; 924 } 925 926 /* Initialize dma mapped elements info elem_info for 927 * future easy access. 928 */ 929 for (i = 0; i < q->count; i++) { 930 struct mlxsw_pci_queue_elem_info *elem_info; 931 932 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 933 elem_info->elem = 934 __mlxsw_pci_queue_elem_get(q, q->elem_size, i); 935 } 936 937 mlxsw_cmd_mbox_zero(mbox); 938 err = q_ops->init(mlxsw_pci, mbox, q); 939 if (err) 940 goto err_q_ops_init; 941 return 0; 942 943 err_q_ops_init: 944 kfree(q->elem_info); 945 err_elem_info_alloc: 946 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 947 mem_item->buf, mem_item->mapaddr); 948 return err; 949 } 950 951 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 952 const struct mlxsw_pci_queue_ops *q_ops, 953 struct mlxsw_pci_queue *q) 954 { 955 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 956 957 q_ops->fini(mlxsw_pci, q); 958 kfree(q->elem_info); 959 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 960 mem_item->buf, mem_item->mapaddr); 961 } 962 963 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 964 const struct mlxsw_pci_queue_ops *q_ops, 965 u8 num_qs) 966 { 967 struct mlxsw_pci_queue_type_group *queue_group; 968 int i; 969 int err; 970 971 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 972 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 973 if (!queue_group->q) 974 return -ENOMEM; 975 976 for (i = 0; i < num_qs; i++) { 977 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 978 &queue_group->q[i], i); 979 if (err) 980 goto err_queue_init; 981 } 982 queue_group->count = num_qs; 983 984 return 0; 985 986 err_queue_init: 987 for (i--; i >= 0; i--) 988 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 989 kfree(queue_group->q); 990 return err; 991 } 992 993 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 994 const struct mlxsw_pci_queue_ops *q_ops) 995 { 996 struct mlxsw_pci_queue_type_group *queue_group; 997 int i; 998 999 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1000 for (i = 0; i < queue_group->count; i++) 1001 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1002 kfree(queue_group->q); 1003 } 1004 1005 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1006 { 1007 struct pci_dev *pdev = mlxsw_pci->pdev; 1008 u8 num_sdqs; 1009 u8 sdq_log2sz; 1010 u8 num_rdqs; 1011 u8 rdq_log2sz; 1012 u8 num_cqs; 1013 u8 cq_log2sz; 1014 u8 cqv2_log2sz; 1015 u8 num_eqs; 1016 u8 eq_log2sz; 1017 int err; 1018 1019 mlxsw_cmd_mbox_zero(mbox); 1020 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1021 if (err) 1022 return err; 1023 1024 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1025 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1026 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1027 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1028 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1029 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1030 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox); 1031 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1032 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1033 1034 if (num_sdqs + num_rdqs > num_cqs || 1035 num_sdqs < MLXSW_PCI_SDQS_MIN || 1036 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 1037 dev_err(&pdev->dev, "Unsupported number of queues\n"); 1038 return -EINVAL; 1039 } 1040 1041 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1042 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1043 (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) || 1044 (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 && 1045 (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) || 1046 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1047 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1048 return -EINVAL; 1049 } 1050 1051 mlxsw_pci->num_sdq_cqs = num_sdqs; 1052 1053 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1054 num_eqs); 1055 if (err) { 1056 dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1057 return err; 1058 } 1059 1060 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1061 num_cqs); 1062 if (err) { 1063 dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1064 goto err_cqs_init; 1065 } 1066 1067 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1068 num_sdqs); 1069 if (err) { 1070 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1071 goto err_sdqs_init; 1072 } 1073 1074 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1075 num_rdqs); 1076 if (err) { 1077 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1078 goto err_rdqs_init; 1079 } 1080 1081 /* We have to poll in command interface until queues are initialized */ 1082 mlxsw_pci->cmd.nopoll = true; 1083 return 0; 1084 1085 err_rdqs_init: 1086 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1087 err_sdqs_init: 1088 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1089 err_cqs_init: 1090 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1091 return err; 1092 } 1093 1094 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1095 { 1096 mlxsw_pci->cmd.nopoll = false; 1097 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1098 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1099 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1100 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1101 } 1102 1103 static void 1104 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1105 char *mbox, int index, 1106 const struct mlxsw_swid_config *swid) 1107 { 1108 u8 mask = 0; 1109 1110 if (swid->used_type) { 1111 mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1112 mbox, index, swid->type); 1113 mask |= 1; 1114 } 1115 if (swid->used_properties) { 1116 mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1117 mbox, index, swid->properties); 1118 mask |= 2; 1119 } 1120 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1121 } 1122 1123 static int 1124 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci, 1125 const struct mlxsw_config_profile *profile, 1126 struct mlxsw_res *res) 1127 { 1128 u64 single_size, double_size, linear_size; 1129 int err; 1130 1131 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile, 1132 &single_size, &double_size, 1133 &linear_size); 1134 if (err) 1135 return err; 1136 1137 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size); 1138 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size); 1139 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size); 1140 1141 return 0; 1142 } 1143 1144 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1145 const struct mlxsw_config_profile *profile, 1146 struct mlxsw_res *res) 1147 { 1148 int i; 1149 int err; 1150 1151 mlxsw_cmd_mbox_zero(mbox); 1152 1153 if (profile->used_max_vepa_channels) { 1154 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1155 mbox, 1); 1156 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1157 mbox, profile->max_vepa_channels); 1158 } 1159 if (profile->used_max_mid) { 1160 mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1161 mbox, 1); 1162 mlxsw_cmd_mbox_config_profile_max_mid_set( 1163 mbox, profile->max_mid); 1164 } 1165 if (profile->used_max_pgt) { 1166 mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1167 mbox, 1); 1168 mlxsw_cmd_mbox_config_profile_max_pgt_set( 1169 mbox, profile->max_pgt); 1170 } 1171 if (profile->used_max_system_port) { 1172 mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1173 mbox, 1); 1174 mlxsw_cmd_mbox_config_profile_max_system_port_set( 1175 mbox, profile->max_system_port); 1176 } 1177 if (profile->used_max_vlan_groups) { 1178 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1179 mbox, 1); 1180 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1181 mbox, profile->max_vlan_groups); 1182 } 1183 if (profile->used_max_regions) { 1184 mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1185 mbox, 1); 1186 mlxsw_cmd_mbox_config_profile_max_regions_set( 1187 mbox, profile->max_regions); 1188 } 1189 if (profile->used_flood_tables) { 1190 mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1191 mbox, 1); 1192 mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1193 mbox, profile->max_flood_tables); 1194 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1195 mbox, profile->max_vid_flood_tables); 1196 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 1197 mbox, profile->max_fid_offset_flood_tables); 1198 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 1199 mbox, profile->fid_offset_flood_table_size); 1200 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1201 mbox, profile->max_fid_flood_tables); 1202 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1203 mbox, profile->fid_flood_table_size); 1204 } 1205 if (profile->used_flood_mode) { 1206 mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1207 mbox, 1); 1208 mlxsw_cmd_mbox_config_profile_flood_mode_set( 1209 mbox, profile->flood_mode); 1210 } 1211 if (profile->used_max_ib_mc) { 1212 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1213 mbox, 1); 1214 mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1215 mbox, profile->max_ib_mc); 1216 } 1217 if (profile->used_max_pkey) { 1218 mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1219 mbox, 1); 1220 mlxsw_cmd_mbox_config_profile_max_pkey_set( 1221 mbox, profile->max_pkey); 1222 } 1223 if (profile->used_ar_sec) { 1224 mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1225 mbox, 1); 1226 mlxsw_cmd_mbox_config_profile_ar_sec_set( 1227 mbox, profile->ar_sec); 1228 } 1229 if (profile->used_adaptive_routing_group_cap) { 1230 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1231 mbox, 1); 1232 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1233 mbox, profile->adaptive_routing_group_cap); 1234 } 1235 if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) { 1236 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res); 1237 if (err) 1238 return err; 1239 1240 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1); 1241 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox, 1242 MLXSW_RES_GET(res, KVD_LINEAR_SIZE)); 1243 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox, 1244 1); 1245 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox, 1246 MLXSW_RES_GET(res, KVD_SINGLE_SIZE)); 1247 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set( 1248 mbox, 1); 1249 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox, 1250 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE)); 1251 } 1252 if (profile->used_kvh_xlt_cache_mode) { 1253 mlxsw_cmd_mbox_config_profile_set_kvh_xlt_cache_mode_set( 1254 mbox, 1); 1255 mlxsw_cmd_mbox_config_profile_kvh_xlt_cache_mode_set( 1256 mbox, profile->kvh_xlt_cache_mode); 1257 } 1258 1259 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1260 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1261 &profile->swid_config[i]); 1262 1263 if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) { 1264 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1); 1265 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1); 1266 } 1267 1268 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1269 } 1270 1271 static int mlxsw_pci_boardinfo_xm_process(struct mlxsw_pci *mlxsw_pci, 1272 struct mlxsw_bus_info *bus_info, 1273 char *mbox) 1274 { 1275 int count = mlxsw_cmd_mbox_boardinfo_xm_num_local_ports_get(mbox); 1276 int i; 1277 1278 if (!mlxsw_cmd_mbox_boardinfo_xm_exists_get(mbox)) 1279 return 0; 1280 1281 bus_info->xm_exists = true; 1282 1283 if (count > MLXSW_BUS_INFO_XM_LOCAL_PORTS_MAX) { 1284 dev_err(&mlxsw_pci->pdev->dev, "Invalid number of XM local ports\n"); 1285 return -EINVAL; 1286 } 1287 bus_info->xm_local_ports_count = count; 1288 for (i = 0; i < count; i++) 1289 bus_info->xm_local_ports[i] = 1290 mlxsw_cmd_mbox_boardinfo_xm_local_port_entry_get(mbox, 1291 i); 1292 return 0; 1293 } 1294 1295 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1296 { 1297 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1298 int err; 1299 1300 mlxsw_cmd_mbox_zero(mbox); 1301 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1302 if (err) 1303 return err; 1304 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1305 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1306 1307 return mlxsw_pci_boardinfo_xm_process(mlxsw_pci, bus_info, mbox); 1308 } 1309 1310 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1311 u16 num_pages) 1312 { 1313 struct mlxsw_pci_mem_item *mem_item; 1314 int nent = 0; 1315 int i; 1316 int err; 1317 1318 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1319 GFP_KERNEL); 1320 if (!mlxsw_pci->fw_area.items) 1321 return -ENOMEM; 1322 mlxsw_pci->fw_area.count = num_pages; 1323 1324 mlxsw_cmd_mbox_zero(mbox); 1325 for (i = 0; i < num_pages; i++) { 1326 mem_item = &mlxsw_pci->fw_area.items[i]; 1327 1328 mem_item->size = MLXSW_PCI_PAGE_SIZE; 1329 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 1330 mem_item->size, 1331 &mem_item->mapaddr, GFP_KERNEL); 1332 if (!mem_item->buf) { 1333 err = -ENOMEM; 1334 goto err_alloc; 1335 } 1336 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 1337 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 1338 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 1339 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1340 if (err) 1341 goto err_cmd_map_fa; 1342 nent = 0; 1343 mlxsw_cmd_mbox_zero(mbox); 1344 } 1345 } 1346 1347 if (nent) { 1348 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1349 if (err) 1350 goto err_cmd_map_fa; 1351 } 1352 1353 return 0; 1354 1355 err_cmd_map_fa: 1356 err_alloc: 1357 for (i--; i >= 0; i--) { 1358 mem_item = &mlxsw_pci->fw_area.items[i]; 1359 1360 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1361 mem_item->buf, mem_item->mapaddr); 1362 } 1363 kfree(mlxsw_pci->fw_area.items); 1364 return err; 1365 } 1366 1367 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1368 { 1369 struct mlxsw_pci_mem_item *mem_item; 1370 int i; 1371 1372 mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1373 1374 for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1375 mem_item = &mlxsw_pci->fw_area.items[i]; 1376 1377 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1378 mem_item->buf, mem_item->mapaddr); 1379 } 1380 kfree(mlxsw_pci->fw_area.items); 1381 } 1382 1383 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1384 { 1385 struct mlxsw_pci *mlxsw_pci = dev_id; 1386 struct mlxsw_pci_queue *q; 1387 int i; 1388 1389 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1390 q = mlxsw_pci_eq_get(mlxsw_pci, i); 1391 mlxsw_pci_queue_tasklet_schedule(q); 1392 } 1393 return IRQ_HANDLED; 1394 } 1395 1396 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 1397 struct mlxsw_pci_mem_item *mbox) 1398 { 1399 struct pci_dev *pdev = mlxsw_pci->pdev; 1400 int err = 0; 1401 1402 mbox->size = MLXSW_CMD_MBOX_SIZE; 1403 mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, 1404 &mbox->mapaddr, GFP_KERNEL); 1405 if (!mbox->buf) { 1406 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 1407 err = -ENOMEM; 1408 } 1409 1410 return err; 1411 } 1412 1413 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 1414 struct mlxsw_pci_mem_item *mbox) 1415 { 1416 struct pci_dev *pdev = mlxsw_pci->pdev; 1417 1418 dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 1419 mbox->mapaddr); 1420 } 1421 1422 static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, 1423 const struct pci_device_id *id, 1424 u32 *p_sys_status) 1425 { 1426 unsigned long end; 1427 u32 val; 1428 1429 /* We must wait for the HW to become responsive. */ 1430 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS); 1431 1432 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1433 do { 1434 val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1435 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 1436 return 0; 1437 cond_resched(); 1438 } while (time_before(jiffies, end)); 1439 1440 *p_sys_status = val & MLXSW_PCI_FW_READY_MASK; 1441 1442 return -EBUSY; 1443 } 1444 1445 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, 1446 const struct pci_device_id *id) 1447 { 1448 struct pci_dev *pdev = mlxsw_pci->pdev; 1449 char mrsr_pl[MLXSW_REG_MRSR_LEN]; 1450 u32 sys_status; 1451 int err; 1452 1453 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1454 if (err) { 1455 dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n", 1456 sys_status); 1457 return err; 1458 } 1459 1460 mlxsw_reg_mrsr_pack(mrsr_pl); 1461 err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 1462 if (err) 1463 return err; 1464 1465 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1466 if (err) { 1467 dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n", 1468 sys_status); 1469 return err; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1476 { 1477 int err; 1478 1479 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX); 1480 if (err < 0) 1481 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n"); 1482 return err; 1483 } 1484 1485 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1486 { 1487 pci_free_irq_vectors(mlxsw_pci->pdev); 1488 } 1489 1490 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1491 const struct mlxsw_config_profile *profile, 1492 struct mlxsw_res *res) 1493 { 1494 struct mlxsw_pci *mlxsw_pci = bus_priv; 1495 struct pci_dev *pdev = mlxsw_pci->pdev; 1496 char *mbox; 1497 u16 num_pages; 1498 int err; 1499 1500 mlxsw_pci->core = mlxsw_core; 1501 1502 mbox = mlxsw_cmd_mbox_alloc(); 1503 if (!mbox) 1504 return -ENOMEM; 1505 1506 err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id); 1507 if (err) 1508 goto err_sw_reset; 1509 1510 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); 1511 if (err < 0) { 1512 dev_err(&pdev->dev, "MSI-X init failed\n"); 1513 goto err_alloc_irq; 1514 } 1515 1516 err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1517 if (err) 1518 goto err_query_fw; 1519 1520 mlxsw_pci->bus_info.fw_rev.major = 1521 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1522 mlxsw_pci->bus_info.fw_rev.minor = 1523 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1524 mlxsw_pci->bus_info.fw_rev.subminor = 1525 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1526 1527 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1528 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1529 err = -EINVAL; 1530 goto err_iface_rev; 1531 } 1532 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1533 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1534 err = -EINVAL; 1535 goto err_doorbell_page_bar; 1536 } 1537 1538 mlxsw_pci->doorbell_offset = 1539 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1540 1541 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) { 1542 dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n"); 1543 err = -EINVAL; 1544 goto err_fr_rn_clk_bar; 1545 } 1546 1547 mlxsw_pci->free_running_clock_offset = 1548 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox); 1549 1550 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1551 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1552 if (err) 1553 goto err_fw_area_init; 1554 1555 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1556 if (err) 1557 goto err_boardinfo; 1558 1559 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 1560 if (err) 1561 goto err_query_resources; 1562 1563 if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) && 1564 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) 1565 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2; 1566 else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) && 1567 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) 1568 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1; 1569 else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) && 1570 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || 1571 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) { 1572 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0; 1573 } else { 1574 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n"); 1575 goto err_cqe_v_check; 1576 } 1577 1578 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res); 1579 if (err) 1580 goto err_config_profile; 1581 1582 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1583 if (err) 1584 goto err_aqs_init; 1585 1586 err = request_irq(pci_irq_vector(pdev, 0), 1587 mlxsw_pci_eq_irq_handler, 0, 1588 mlxsw_pci->bus_info.device_kind, mlxsw_pci); 1589 if (err) { 1590 dev_err(&pdev->dev, "IRQ request failed\n"); 1591 goto err_request_eq_irq; 1592 } 1593 1594 goto mbox_put; 1595 1596 err_request_eq_irq: 1597 mlxsw_pci_aqs_fini(mlxsw_pci); 1598 err_aqs_init: 1599 err_config_profile: 1600 err_cqe_v_check: 1601 err_query_resources: 1602 err_boardinfo: 1603 mlxsw_pci_fw_area_fini(mlxsw_pci); 1604 err_fw_area_init: 1605 err_fr_rn_clk_bar: 1606 err_doorbell_page_bar: 1607 err_iface_rev: 1608 err_query_fw: 1609 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1610 err_alloc_irq: 1611 err_sw_reset: 1612 mbox_put: 1613 mlxsw_cmd_mbox_free(mbox); 1614 return err; 1615 } 1616 1617 static void mlxsw_pci_fini(void *bus_priv) 1618 { 1619 struct mlxsw_pci *mlxsw_pci = bus_priv; 1620 1621 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 1622 mlxsw_pci_aqs_fini(mlxsw_pci); 1623 mlxsw_pci_fw_area_fini(mlxsw_pci); 1624 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1625 } 1626 1627 static struct mlxsw_pci_queue * 1628 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1629 const struct mlxsw_tx_info *tx_info) 1630 { 1631 u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1; 1632 u8 sdqn; 1633 1634 if (tx_info->is_emad) { 1635 sdqn = MLXSW_PCI_SDQ_EMAD_INDEX; 1636 } else { 1637 BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0); 1638 sdqn = 1 + (tx_info->local_port % ctl_sdq_count); 1639 } 1640 1641 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1642 } 1643 1644 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1645 const struct mlxsw_tx_info *tx_info) 1646 { 1647 struct mlxsw_pci *mlxsw_pci = bus_priv; 1648 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1649 1650 return !mlxsw_pci_queue_elem_info_producer_get(q); 1651 } 1652 1653 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1654 const struct mlxsw_tx_info *tx_info) 1655 { 1656 struct mlxsw_pci *mlxsw_pci = bus_priv; 1657 struct mlxsw_pci_queue *q; 1658 struct mlxsw_pci_queue_elem_info *elem_info; 1659 char *wqe; 1660 int i; 1661 int err; 1662 1663 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1664 err = skb_linearize(skb); 1665 if (err) 1666 return err; 1667 } 1668 1669 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1670 spin_lock_bh(&q->lock); 1671 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1672 if (!elem_info) { 1673 /* queue is full */ 1674 err = -EAGAIN; 1675 goto unlock; 1676 } 1677 mlxsw_skb_cb(skb)->tx_info = *tx_info; 1678 elem_info->u.sdq.skb = skb; 1679 1680 wqe = elem_info->elem; 1681 mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1682 mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1683 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1684 1685 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1686 skb_headlen(skb), DMA_TO_DEVICE); 1687 if (err) 1688 goto unlock; 1689 1690 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1691 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1692 1693 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1694 skb_frag_address(frag), 1695 skb_frag_size(frag), 1696 DMA_TO_DEVICE); 1697 if (err) 1698 goto unmap_frags; 1699 } 1700 1701 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 1702 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1703 1704 /* Set unused sq entries byte count to zero. */ 1705 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1706 mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1707 1708 /* Everything is set up, ring producer doorbell to get HW going */ 1709 q->producer_counter++; 1710 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1711 1712 goto unlock; 1713 1714 unmap_frags: 1715 for (; i >= 0; i--) 1716 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1717 unlock: 1718 spin_unlock_bh(&q->lock); 1719 return err; 1720 } 1721 1722 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1723 u32 in_mod, bool out_mbox_direct, 1724 char *in_mbox, size_t in_mbox_size, 1725 char *out_mbox, size_t out_mbox_size, 1726 u8 *p_status) 1727 { 1728 struct mlxsw_pci *mlxsw_pci = bus_priv; 1729 dma_addr_t in_mapaddr = 0, out_mapaddr = 0; 1730 bool evreq = mlxsw_pci->cmd.nopoll; 1731 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1732 bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1733 int err; 1734 1735 *p_status = MLXSW_CMD_STATUS_OK; 1736 1737 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1738 if (err) 1739 return err; 1740 1741 if (in_mbox) { 1742 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1743 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 1744 } 1745 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 1746 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 1747 1748 if (out_mbox) 1749 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1750 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 1751 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 1752 1753 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1754 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1755 1756 *p_wait_done = false; 1757 1758 wmb(); /* all needs to be written before we write control register */ 1759 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1760 MLXSW_PCI_CIR_CTRL_GO_BIT | 1761 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1762 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1763 opcode); 1764 1765 if (!evreq) { 1766 unsigned long end; 1767 1768 end = jiffies + timeout; 1769 do { 1770 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1771 1772 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1773 *p_wait_done = true; 1774 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1775 break; 1776 } 1777 cond_resched(); 1778 } while (time_before(jiffies, end)); 1779 } else { 1780 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1781 *p_status = mlxsw_pci->cmd.comp.status; 1782 } 1783 1784 err = 0; 1785 if (*p_wait_done) { 1786 if (*p_status) 1787 err = -EIO; 1788 } else { 1789 err = -ETIMEDOUT; 1790 } 1791 1792 if (!err && out_mbox && out_mbox_direct) { 1793 /* Some commands don't use output param as address to mailbox 1794 * but they store output directly into registers. In that case, 1795 * copy registers into mbox buffer. 1796 */ 1797 __be32 tmp; 1798 1799 if (!evreq) { 1800 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1801 CIR_OUT_PARAM_HI)); 1802 memcpy(out_mbox, &tmp, sizeof(tmp)); 1803 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1804 CIR_OUT_PARAM_LO)); 1805 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1806 } 1807 } else if (!err && out_mbox) { 1808 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1809 } 1810 1811 mutex_unlock(&mlxsw_pci->cmd.lock); 1812 1813 return err; 1814 } 1815 1816 static u32 mlxsw_pci_read_frc_h(void *bus_priv) 1817 { 1818 struct mlxsw_pci *mlxsw_pci = bus_priv; 1819 u64 frc_offset; 1820 1821 frc_offset = mlxsw_pci->free_running_clock_offset; 1822 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset)); 1823 } 1824 1825 static u32 mlxsw_pci_read_frc_l(void *bus_priv) 1826 { 1827 struct mlxsw_pci *mlxsw_pci = bus_priv; 1828 u64 frc_offset; 1829 1830 frc_offset = mlxsw_pci->free_running_clock_offset; 1831 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset)); 1832 } 1833 1834 static const struct mlxsw_bus mlxsw_pci_bus = { 1835 .kind = "pci", 1836 .init = mlxsw_pci_init, 1837 .fini = mlxsw_pci_fini, 1838 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 1839 .skb_transmit = mlxsw_pci_skb_transmit, 1840 .cmd_exec = mlxsw_pci_cmd_exec, 1841 .read_frc_h = mlxsw_pci_read_frc_h, 1842 .read_frc_l = mlxsw_pci_read_frc_l, 1843 .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, 1844 }; 1845 1846 static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci) 1847 { 1848 int err; 1849 1850 mutex_init(&mlxsw_pci->cmd.lock); 1851 init_waitqueue_head(&mlxsw_pci->cmd.wait); 1852 1853 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1854 if (err) 1855 goto err_in_mbox_alloc; 1856 1857 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1858 if (err) 1859 goto err_out_mbox_alloc; 1860 1861 return 0; 1862 1863 err_out_mbox_alloc: 1864 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1865 err_in_mbox_alloc: 1866 mutex_destroy(&mlxsw_pci->cmd.lock); 1867 return err; 1868 } 1869 1870 static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci) 1871 { 1872 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1873 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1874 mutex_destroy(&mlxsw_pci->cmd.lock); 1875 } 1876 1877 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1878 { 1879 const char *driver_name = pdev->driver->name; 1880 struct mlxsw_pci *mlxsw_pci; 1881 int err; 1882 1883 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1884 if (!mlxsw_pci) 1885 return -ENOMEM; 1886 1887 err = pci_enable_device(pdev); 1888 if (err) { 1889 dev_err(&pdev->dev, "pci_enable_device failed\n"); 1890 goto err_pci_enable_device; 1891 } 1892 1893 err = pci_request_regions(pdev, driver_name); 1894 if (err) { 1895 dev_err(&pdev->dev, "pci_request_regions failed\n"); 1896 goto err_pci_request_regions; 1897 } 1898 1899 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1900 if (err) { 1901 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1902 if (err) { 1903 dev_err(&pdev->dev, "dma_set_mask failed\n"); 1904 goto err_pci_set_dma_mask; 1905 } 1906 } 1907 1908 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1909 dev_err(&pdev->dev, "invalid PCI region size\n"); 1910 err = -EINVAL; 1911 goto err_pci_resource_len_check; 1912 } 1913 1914 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1915 pci_resource_len(pdev, 0)); 1916 if (!mlxsw_pci->hw_addr) { 1917 dev_err(&pdev->dev, "ioremap failed\n"); 1918 err = -EIO; 1919 goto err_ioremap; 1920 } 1921 pci_set_master(pdev); 1922 1923 mlxsw_pci->pdev = pdev; 1924 pci_set_drvdata(pdev, mlxsw_pci); 1925 1926 err = mlxsw_pci_cmd_init(mlxsw_pci); 1927 if (err) 1928 goto err_pci_cmd_init; 1929 1930 mlxsw_pci->bus_info.device_kind = driver_name; 1931 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1932 mlxsw_pci->bus_info.dev = &pdev->dev; 1933 mlxsw_pci->bus_info.read_frc_capable = true; 1934 mlxsw_pci->id = id; 1935 1936 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 1937 &mlxsw_pci_bus, mlxsw_pci, false, 1938 NULL, NULL); 1939 if (err) { 1940 dev_err(&pdev->dev, "cannot register bus device\n"); 1941 goto err_bus_device_register; 1942 } 1943 1944 return 0; 1945 1946 err_bus_device_register: 1947 mlxsw_pci_cmd_fini(mlxsw_pci); 1948 err_pci_cmd_init: 1949 iounmap(mlxsw_pci->hw_addr); 1950 err_ioremap: 1951 err_pci_resource_len_check: 1952 err_pci_set_dma_mask: 1953 pci_release_regions(pdev); 1954 err_pci_request_regions: 1955 pci_disable_device(pdev); 1956 err_pci_enable_device: 1957 kfree(mlxsw_pci); 1958 return err; 1959 } 1960 1961 static void mlxsw_pci_remove(struct pci_dev *pdev) 1962 { 1963 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1964 1965 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 1966 mlxsw_pci_cmd_fini(mlxsw_pci); 1967 iounmap(mlxsw_pci->hw_addr); 1968 pci_release_regions(mlxsw_pci->pdev); 1969 pci_disable_device(mlxsw_pci->pdev); 1970 kfree(mlxsw_pci); 1971 } 1972 1973 int mlxsw_pci_driver_register(struct pci_driver *pci_driver) 1974 { 1975 pci_driver->probe = mlxsw_pci_probe; 1976 pci_driver->remove = mlxsw_pci_remove; 1977 return pci_register_driver(pci_driver); 1978 } 1979 EXPORT_SYMBOL(mlxsw_pci_driver_register); 1980 1981 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver) 1982 { 1983 pci_unregister_driver(pci_driver); 1984 } 1985 EXPORT_SYMBOL(mlxsw_pci_driver_unregister); 1986 1987 static int __init mlxsw_pci_module_init(void) 1988 { 1989 return 0; 1990 } 1991 1992 static void __exit mlxsw_pci_module_exit(void) 1993 { 1994 } 1995 1996 module_init(mlxsw_pci_module_init); 1997 module_exit(mlxsw_pci_module_exit); 1998 1999 MODULE_LICENSE("Dual BSD/GPL"); 2000 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 2001 MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 2002