1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/export.h> 7 #include <linux/err.h> 8 #include <linux/device.h> 9 #include <linux/pci.h> 10 #include <linux/interrupt.h> 11 #include <linux/wait.h> 12 #include <linux/types.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/log2.h> 16 #include <linux/string.h> 17 18 #include "pci_hw.h" 19 #include "pci.h" 20 #include "core.h" 21 #include "cmd.h" 22 #include "port.h" 23 #include "resources.h" 24 25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 26 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 27 #define mlxsw_pci_read32(mlxsw_pci, reg) \ 28 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 29 30 enum mlxsw_pci_queue_type { 31 MLXSW_PCI_QUEUE_TYPE_SDQ, 32 MLXSW_PCI_QUEUE_TYPE_RDQ, 33 MLXSW_PCI_QUEUE_TYPE_CQ, 34 MLXSW_PCI_QUEUE_TYPE_EQ, 35 }; 36 37 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 38 39 static const u16 mlxsw_pci_doorbell_type_offset[] = { 40 MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 41 MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 42 MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 43 MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 44 }; 45 46 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 47 0, /* unused */ 48 0, /* unused */ 49 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 50 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 51 }; 52 53 struct mlxsw_pci_mem_item { 54 char *buf; 55 dma_addr_t mapaddr; 56 size_t size; 57 }; 58 59 struct mlxsw_pci_queue_elem_info { 60 char *elem; /* pointer to actual dma mapped element mem chunk */ 61 union { 62 struct { 63 struct sk_buff *skb; 64 } sdq; 65 struct { 66 struct sk_buff *skb; 67 } rdq; 68 } u; 69 }; 70 71 struct mlxsw_pci_queue { 72 spinlock_t lock; /* for queue accesses */ 73 struct mlxsw_pci_mem_item mem_item; 74 struct mlxsw_pci_queue_elem_info *elem_info; 75 u16 producer_counter; 76 u16 consumer_counter; 77 u16 count; /* number of elements in queue */ 78 u8 num; /* queue number */ 79 u8 elem_size; /* size of one element */ 80 enum mlxsw_pci_queue_type type; 81 struct tasklet_struct tasklet; /* queue processing tasklet */ 82 struct mlxsw_pci *pci; 83 union { 84 struct { 85 u32 comp_sdq_count; 86 u32 comp_rdq_count; 87 enum mlxsw_pci_cqe_v v; 88 } cq; 89 struct { 90 u32 ev_cmd_count; 91 u32 ev_comp_count; 92 u32 ev_other_count; 93 } eq; 94 } u; 95 }; 96 97 struct mlxsw_pci_queue_type_group { 98 struct mlxsw_pci_queue *q; 99 u8 count; /* number of queues in group */ 100 }; 101 102 struct mlxsw_pci { 103 struct pci_dev *pdev; 104 u8 __iomem *hw_addr; 105 u64 free_running_clock_offset; 106 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 107 u32 doorbell_offset; 108 struct mlxsw_core *core; 109 struct { 110 struct mlxsw_pci_mem_item *items; 111 unsigned int count; 112 } fw_area; 113 struct { 114 struct mlxsw_pci_mem_item out_mbox; 115 struct mlxsw_pci_mem_item in_mbox; 116 struct mutex lock; /* Lock access to command registers */ 117 bool nopoll; 118 wait_queue_head_t wait; 119 bool wait_done; 120 struct { 121 u8 status; 122 u64 out_param; 123 } comp; 124 } cmd; 125 struct mlxsw_bus_info bus_info; 126 const struct pci_device_id *id; 127 enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ 128 u8 num_sdq_cqs; /* Number of CQs used for SDQs */ 129 }; 130 131 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 132 { 133 tasklet_schedule(&q->tasklet); 134 } 135 136 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 137 size_t elem_size, int elem_index) 138 { 139 return q->mem_item.buf + (elem_size * elem_index); 140 } 141 142 static struct mlxsw_pci_queue_elem_info * 143 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 144 { 145 return &q->elem_info[elem_index]; 146 } 147 148 static struct mlxsw_pci_queue_elem_info * 149 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 150 { 151 int index = q->producer_counter & (q->count - 1); 152 153 if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 154 return NULL; 155 return mlxsw_pci_queue_elem_info_get(q, index); 156 } 157 158 static struct mlxsw_pci_queue_elem_info * 159 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 160 { 161 int index = q->consumer_counter & (q->count - 1); 162 163 return mlxsw_pci_queue_elem_info_get(q, index); 164 } 165 166 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 167 { 168 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 169 } 170 171 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 172 { 173 return owner_bit != !!(q->consumer_counter & q->count); 174 } 175 176 static struct mlxsw_pci_queue_type_group * 177 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 178 enum mlxsw_pci_queue_type q_type) 179 { 180 return &mlxsw_pci->queues[q_type]; 181 } 182 183 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 184 enum mlxsw_pci_queue_type q_type) 185 { 186 struct mlxsw_pci_queue_type_group *queue_group; 187 188 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 189 return queue_group->count; 190 } 191 192 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 193 { 194 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 195 } 196 197 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 198 { 199 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 200 } 201 202 static struct mlxsw_pci_queue * 203 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 204 enum mlxsw_pci_queue_type q_type, u8 q_num) 205 { 206 return &mlxsw_pci->queues[q_type].q[q_num]; 207 } 208 209 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 210 u8 q_num) 211 { 212 return __mlxsw_pci_queue_get(mlxsw_pci, 213 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 214 } 215 216 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 217 u8 q_num) 218 { 219 return __mlxsw_pci_queue_get(mlxsw_pci, 220 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 221 } 222 223 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 224 u8 q_num) 225 { 226 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 227 } 228 229 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 230 u8 q_num) 231 { 232 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 233 } 234 235 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 236 struct mlxsw_pci_queue *q, 237 u16 val) 238 { 239 mlxsw_pci_write32(mlxsw_pci, 240 DOORBELL(mlxsw_pci->doorbell_offset, 241 mlxsw_pci_doorbell_type_offset[q->type], 242 q->num), val); 243 } 244 245 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 246 struct mlxsw_pci_queue *q, 247 u16 val) 248 { 249 mlxsw_pci_write32(mlxsw_pci, 250 DOORBELL(mlxsw_pci->doorbell_offset, 251 mlxsw_pci_doorbell_arm_type_offset[q->type], 252 q->num), val); 253 } 254 255 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 256 struct mlxsw_pci_queue *q) 257 { 258 wmb(); /* ensure all writes are done before we ring a bell */ 259 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 260 } 261 262 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 263 struct mlxsw_pci_queue *q) 264 { 265 wmb(); /* ensure all writes are done before we ring a bell */ 266 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 267 q->consumer_counter + q->count); 268 } 269 270 static void 271 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 272 struct mlxsw_pci_queue *q) 273 { 274 wmb(); /* ensure all writes are done before we ring a bell */ 275 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 276 } 277 278 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 279 int page_index) 280 { 281 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 282 } 283 284 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 285 struct mlxsw_pci_queue *q) 286 { 287 int tclass; 288 int i; 289 int err; 290 291 q->producer_counter = 0; 292 q->consumer_counter = 0; 293 tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC : 294 MLXSW_PCI_SDQ_CTL_TC; 295 296 /* Set CQ of same number of this SDQ. */ 297 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 298 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass); 299 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 300 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 301 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 302 303 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 304 } 305 306 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 307 if (err) 308 return err; 309 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 310 return 0; 311 } 312 313 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 314 struct mlxsw_pci_queue *q) 315 { 316 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 317 } 318 319 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 320 int index, char *frag_data, size_t frag_len, 321 int direction) 322 { 323 struct pci_dev *pdev = mlxsw_pci->pdev; 324 dma_addr_t mapaddr; 325 326 mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction); 327 if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) { 328 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 329 return -EIO; 330 } 331 mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 332 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 333 return 0; 334 } 335 336 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 337 int index, int direction) 338 { 339 struct pci_dev *pdev = mlxsw_pci->pdev; 340 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 341 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 342 343 if (!frag_len) 344 return; 345 dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); 346 } 347 348 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 349 struct mlxsw_pci_queue_elem_info *elem_info) 350 { 351 size_t buf_len = MLXSW_PORT_MAX_MTU; 352 char *wqe = elem_info->elem; 353 struct sk_buff *skb; 354 int err; 355 356 skb = netdev_alloc_skb_ip_align(NULL, buf_len); 357 if (!skb) 358 return -ENOMEM; 359 360 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 361 buf_len, DMA_FROM_DEVICE); 362 if (err) 363 goto err_frag_map; 364 365 elem_info->u.rdq.skb = skb; 366 return 0; 367 368 err_frag_map: 369 dev_kfree_skb_any(skb); 370 return err; 371 } 372 373 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 374 struct mlxsw_pci_queue_elem_info *elem_info) 375 { 376 struct sk_buff *skb; 377 char *wqe; 378 379 skb = elem_info->u.rdq.skb; 380 wqe = elem_info->elem; 381 382 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 383 dev_kfree_skb_any(skb); 384 } 385 386 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 387 struct mlxsw_pci_queue *q) 388 { 389 struct mlxsw_pci_queue_elem_info *elem_info; 390 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 391 int i; 392 int err; 393 394 q->producer_counter = 0; 395 q->consumer_counter = 0; 396 397 /* Set CQ of same number of this RDQ with base 398 * above SDQ count as the lower ones are assigned to SDQs. 399 */ 400 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 401 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 402 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 403 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 404 405 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 406 } 407 408 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 409 if (err) 410 return err; 411 412 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 413 414 for (i = 0; i < q->count; i++) { 415 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 416 BUG_ON(!elem_info); 417 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 418 if (err) 419 goto rollback; 420 /* Everything is set up, ring doorbell to pass elem to HW */ 421 q->producer_counter++; 422 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 423 } 424 425 return 0; 426 427 rollback: 428 for (i--; i >= 0; i--) { 429 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 430 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 431 } 432 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 433 434 return err; 435 } 436 437 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 438 struct mlxsw_pci_queue *q) 439 { 440 struct mlxsw_pci_queue_elem_info *elem_info; 441 int i; 442 443 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 444 for (i = 0; i < q->count; i++) { 445 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 446 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 447 } 448 } 449 450 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci, 451 struct mlxsw_pci_queue *q) 452 { 453 q->u.cq.v = mlxsw_pci->max_cqe_ver; 454 455 /* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */ 456 if (q->u.cq.v == MLXSW_PCI_CQE_V2 && 457 q->num < mlxsw_pci->num_sdq_cqs) 458 q->u.cq.v = MLXSW_PCI_CQE_V1; 459 } 460 461 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 462 struct mlxsw_pci_queue *q) 463 { 464 int i; 465 int err; 466 467 q->consumer_counter = 0; 468 469 for (i = 0; i < q->count; i++) { 470 char *elem = mlxsw_pci_queue_elem_get(q, i); 471 472 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1); 473 } 474 475 if (q->u.cq.v == MLXSW_PCI_CQE_V1) 476 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 477 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1); 478 else if (q->u.cq.v == MLXSW_PCI_CQE_V2) 479 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 480 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2); 481 482 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 483 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 484 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 485 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 486 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 487 488 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 489 } 490 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 491 if (err) 492 return err; 493 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 494 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 495 return 0; 496 } 497 498 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 499 struct mlxsw_pci_queue *q) 500 { 501 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 502 } 503 504 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 505 struct mlxsw_pci_queue *q, 506 u16 consumer_counter_limit, 507 char *cqe) 508 { 509 struct pci_dev *pdev = mlxsw_pci->pdev; 510 struct mlxsw_pci_queue_elem_info *elem_info; 511 struct mlxsw_tx_info tx_info; 512 char *wqe; 513 struct sk_buff *skb; 514 int i; 515 516 spin_lock(&q->lock); 517 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 518 tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info; 519 skb = elem_info->u.sdq.skb; 520 wqe = elem_info->elem; 521 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 522 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 523 524 if (unlikely(!tx_info.is_emad && 525 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 526 mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb, 527 tx_info.local_port); 528 skb = NULL; 529 } 530 531 if (skb) 532 dev_kfree_skb_any(skb); 533 elem_info->u.sdq.skb = NULL; 534 535 if (q->consumer_counter++ != consumer_counter_limit) 536 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 537 spin_unlock(&q->lock); 538 } 539 540 static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb, 541 const char *cqe) 542 { 543 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 544 545 if (mlxsw_pci_cqe2_tx_lag_get(cqe)) { 546 cb->rx_md_info.tx_port_is_lag = true; 547 cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe); 548 cb->rx_md_info.tx_lag_port_index = 549 mlxsw_pci_cqe2_tx_lag_subport_get(cqe); 550 } else { 551 cb->rx_md_info.tx_port_is_lag = false; 552 cb->rx_md_info.tx_sys_port = 553 mlxsw_pci_cqe2_tx_system_port_get(cqe); 554 } 555 556 if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT && 557 cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID) 558 cb->rx_md_info.tx_port_valid = 1; 559 else 560 cb->rx_md_info.tx_port_valid = 0; 561 } 562 563 static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe) 564 { 565 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 566 567 cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe); 568 if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID) 569 cb->rx_md_info.tx_congestion_valid = 1; 570 else 571 cb->rx_md_info.tx_congestion_valid = 0; 572 cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT; 573 574 cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe); 575 if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID) 576 cb->rx_md_info.latency_valid = 1; 577 else 578 cb->rx_md_info.latency_valid = 0; 579 580 cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe); 581 if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID) 582 cb->rx_md_info.tx_tc_valid = 1; 583 else 584 cb->rx_md_info.tx_tc_valid = 0; 585 586 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 587 } 588 589 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 590 struct mlxsw_pci_queue *q, 591 u16 consumer_counter_limit, 592 enum mlxsw_pci_cqe_v cqe_v, char *cqe) 593 { 594 struct pci_dev *pdev = mlxsw_pci->pdev; 595 struct mlxsw_pci_queue_elem_info *elem_info; 596 struct mlxsw_rx_info rx_info = {}; 597 char wqe[MLXSW_PCI_WQE_SIZE]; 598 struct sk_buff *skb; 599 u16 byte_count; 600 int err; 601 602 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 603 skb = elem_info->u.rdq.skb; 604 memcpy(wqe, elem_info->elem, MLXSW_PCI_WQE_SIZE); 605 606 if (q->consumer_counter++ != consumer_counter_limit) 607 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 608 609 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 610 if (err) { 611 dev_err_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); 612 goto out; 613 } 614 615 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 616 617 if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { 618 rx_info.is_lag = true; 619 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); 620 rx_info.lag_port_index = 621 mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); 622 } else { 623 rx_info.is_lag = false; 624 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 625 } 626 627 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 628 629 if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL || 630 rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) { 631 u32 cookie_index = 0; 632 633 if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) 634 cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe); 635 mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index; 636 } else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 && 637 rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 && 638 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 639 rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe); 640 mlxsw_pci_cqe_rdq_md_init(skb, cqe); 641 } else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE && 642 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 643 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 644 } 645 646 byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 647 if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) 648 byte_count -= ETH_FCS_LEN; 649 skb_put(skb, byte_count); 650 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 651 652 out: 653 /* Everything is set up, ring doorbell to pass elem to HW */ 654 q->producer_counter++; 655 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 656 return; 657 } 658 659 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 660 { 661 struct mlxsw_pci_queue_elem_info *elem_info; 662 char *elem; 663 bool owner_bit; 664 665 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 666 elem = elem_info->elem; 667 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem); 668 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 669 return NULL; 670 q->consumer_counter++; 671 rmb(); /* make sure we read owned bit before the rest of elem */ 672 return elem; 673 } 674 675 static void mlxsw_pci_cq_tasklet(struct tasklet_struct *t) 676 { 677 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 678 struct mlxsw_pci *mlxsw_pci = q->pci; 679 char *cqe; 680 int items = 0; 681 int credits = q->count >> 1; 682 683 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 684 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 685 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 686 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 687 char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; 688 689 memcpy(ncqe, cqe, q->elem_size); 690 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 691 692 if (sendq) { 693 struct mlxsw_pci_queue *sdq; 694 695 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 696 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 697 wqe_counter, ncqe); 698 q->u.cq.comp_sdq_count++; 699 } else { 700 struct mlxsw_pci_queue *rdq; 701 702 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 703 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 704 wqe_counter, q->u.cq.v, ncqe); 705 q->u.cq.comp_rdq_count++; 706 } 707 if (++items == credits) 708 break; 709 } 710 if (items) 711 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 712 } 713 714 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q) 715 { 716 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT : 717 MLXSW_PCI_CQE01_COUNT; 718 } 719 720 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q) 721 { 722 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE : 723 MLXSW_PCI_CQE01_SIZE; 724 } 725 726 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 727 struct mlxsw_pci_queue *q) 728 { 729 int i; 730 int err; 731 732 q->consumer_counter = 0; 733 734 for (i = 0; i < q->count; i++) { 735 char *elem = mlxsw_pci_queue_elem_get(q, i); 736 737 mlxsw_pci_eqe_owner_set(elem, 1); 738 } 739 740 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 741 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 742 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 743 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 744 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 745 746 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 747 } 748 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 749 if (err) 750 return err; 751 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 752 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 753 return 0; 754 } 755 756 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 757 struct mlxsw_pci_queue *q) 758 { 759 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 760 } 761 762 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 763 { 764 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 765 mlxsw_pci->cmd.comp.out_param = 766 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 767 mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 768 mlxsw_pci->cmd.wait_done = true; 769 wake_up(&mlxsw_pci->cmd.wait); 770 } 771 772 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 773 { 774 struct mlxsw_pci_queue_elem_info *elem_info; 775 char *elem; 776 bool owner_bit; 777 778 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 779 elem = elem_info->elem; 780 owner_bit = mlxsw_pci_eqe_owner_get(elem); 781 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 782 return NULL; 783 q->consumer_counter++; 784 rmb(); /* make sure we read owned bit before the rest of elem */ 785 return elem; 786 } 787 788 static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t) 789 { 790 struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 791 struct mlxsw_pci *mlxsw_pci = q->pci; 792 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 793 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 794 char *eqe; 795 u8 cqn; 796 bool cq_handle = false; 797 int items = 0; 798 int credits = q->count >> 1; 799 800 memset(&active_cqns, 0, sizeof(active_cqns)); 801 802 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 803 804 /* Command interface completion events are always received on 805 * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events 806 * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1). 807 */ 808 switch (q->num) { 809 case MLXSW_PCI_EQ_ASYNC_NUM: 810 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 811 q->u.eq.ev_cmd_count++; 812 break; 813 case MLXSW_PCI_EQ_COMP_NUM: 814 cqn = mlxsw_pci_eqe_cqn_get(eqe); 815 set_bit(cqn, active_cqns); 816 cq_handle = true; 817 q->u.eq.ev_comp_count++; 818 break; 819 default: 820 q->u.eq.ev_other_count++; 821 } 822 if (++items == credits) 823 break; 824 } 825 if (items) { 826 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 827 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 828 } 829 830 if (!cq_handle) 831 return; 832 for_each_set_bit(cqn, active_cqns, cq_count) { 833 q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 834 mlxsw_pci_queue_tasklet_schedule(q); 835 } 836 } 837 838 struct mlxsw_pci_queue_ops { 839 const char *name; 840 enum mlxsw_pci_queue_type type; 841 void (*pre_init)(struct mlxsw_pci *mlxsw_pci, 842 struct mlxsw_pci_queue *q); 843 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 844 struct mlxsw_pci_queue *q); 845 void (*fini)(struct mlxsw_pci *mlxsw_pci, 846 struct mlxsw_pci_queue *q); 847 void (*tasklet)(struct tasklet_struct *t); 848 u16 (*elem_count_f)(const struct mlxsw_pci_queue *q); 849 u8 (*elem_size_f)(const struct mlxsw_pci_queue *q); 850 u16 elem_count; 851 u8 elem_size; 852 }; 853 854 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 855 .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 856 .init = mlxsw_pci_sdq_init, 857 .fini = mlxsw_pci_sdq_fini, 858 .elem_count = MLXSW_PCI_WQE_COUNT, 859 .elem_size = MLXSW_PCI_WQE_SIZE, 860 }; 861 862 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 863 .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 864 .init = mlxsw_pci_rdq_init, 865 .fini = mlxsw_pci_rdq_fini, 866 .elem_count = MLXSW_PCI_WQE_COUNT, 867 .elem_size = MLXSW_PCI_WQE_SIZE 868 }; 869 870 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 871 .type = MLXSW_PCI_QUEUE_TYPE_CQ, 872 .pre_init = mlxsw_pci_cq_pre_init, 873 .init = mlxsw_pci_cq_init, 874 .fini = mlxsw_pci_cq_fini, 875 .tasklet = mlxsw_pci_cq_tasklet, 876 .elem_count_f = mlxsw_pci_cq_elem_count, 877 .elem_size_f = mlxsw_pci_cq_elem_size 878 }; 879 880 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 881 .type = MLXSW_PCI_QUEUE_TYPE_EQ, 882 .init = mlxsw_pci_eq_init, 883 .fini = mlxsw_pci_eq_fini, 884 .tasklet = mlxsw_pci_eq_tasklet, 885 .elem_count = MLXSW_PCI_EQE_COUNT, 886 .elem_size = MLXSW_PCI_EQE_SIZE 887 }; 888 889 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 890 const struct mlxsw_pci_queue_ops *q_ops, 891 struct mlxsw_pci_queue *q, u8 q_num) 892 { 893 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 894 int i; 895 int err; 896 897 q->num = q_num; 898 if (q_ops->pre_init) 899 q_ops->pre_init(mlxsw_pci, q); 900 901 spin_lock_init(&q->lock); 902 q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) : 903 q_ops->elem_count; 904 q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) : 905 q_ops->elem_size; 906 q->type = q_ops->type; 907 q->pci = mlxsw_pci; 908 909 if (q_ops->tasklet) 910 tasklet_setup(&q->tasklet, q_ops->tasklet); 911 912 mem_item->size = MLXSW_PCI_AQ_SIZE; 913 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 914 mem_item->size, &mem_item->mapaddr, 915 GFP_KERNEL); 916 if (!mem_item->buf) 917 return -ENOMEM; 918 919 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 920 if (!q->elem_info) { 921 err = -ENOMEM; 922 goto err_elem_info_alloc; 923 } 924 925 /* Initialize dma mapped elements info elem_info for 926 * future easy access. 927 */ 928 for (i = 0; i < q->count; i++) { 929 struct mlxsw_pci_queue_elem_info *elem_info; 930 931 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 932 elem_info->elem = 933 __mlxsw_pci_queue_elem_get(q, q->elem_size, i); 934 } 935 936 mlxsw_cmd_mbox_zero(mbox); 937 err = q_ops->init(mlxsw_pci, mbox, q); 938 if (err) 939 goto err_q_ops_init; 940 return 0; 941 942 err_q_ops_init: 943 kfree(q->elem_info); 944 err_elem_info_alloc: 945 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 946 mem_item->buf, mem_item->mapaddr); 947 return err; 948 } 949 950 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 951 const struct mlxsw_pci_queue_ops *q_ops, 952 struct mlxsw_pci_queue *q) 953 { 954 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 955 956 q_ops->fini(mlxsw_pci, q); 957 kfree(q->elem_info); 958 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 959 mem_item->buf, mem_item->mapaddr); 960 } 961 962 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 963 const struct mlxsw_pci_queue_ops *q_ops, 964 u8 num_qs) 965 { 966 struct mlxsw_pci_queue_type_group *queue_group; 967 int i; 968 int err; 969 970 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 971 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 972 if (!queue_group->q) 973 return -ENOMEM; 974 975 for (i = 0; i < num_qs; i++) { 976 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 977 &queue_group->q[i], i); 978 if (err) 979 goto err_queue_init; 980 } 981 queue_group->count = num_qs; 982 983 return 0; 984 985 err_queue_init: 986 for (i--; i >= 0; i--) 987 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 988 kfree(queue_group->q); 989 return err; 990 } 991 992 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 993 const struct mlxsw_pci_queue_ops *q_ops) 994 { 995 struct mlxsw_pci_queue_type_group *queue_group; 996 int i; 997 998 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 999 for (i = 0; i < queue_group->count; i++) 1000 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1001 kfree(queue_group->q); 1002 } 1003 1004 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1005 { 1006 struct pci_dev *pdev = mlxsw_pci->pdev; 1007 u8 num_sdqs; 1008 u8 sdq_log2sz; 1009 u8 num_rdqs; 1010 u8 rdq_log2sz; 1011 u8 num_cqs; 1012 u8 cq_log2sz; 1013 u8 cqv2_log2sz; 1014 u8 num_eqs; 1015 u8 eq_log2sz; 1016 int err; 1017 1018 mlxsw_cmd_mbox_zero(mbox); 1019 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1020 if (err) 1021 return err; 1022 1023 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1024 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1025 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1026 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1027 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1028 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1029 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox); 1030 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1031 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1032 1033 if (num_sdqs + num_rdqs > num_cqs || 1034 num_sdqs < MLXSW_PCI_SDQS_MIN || 1035 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 1036 dev_err(&pdev->dev, "Unsupported number of queues\n"); 1037 return -EINVAL; 1038 } 1039 1040 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1041 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1042 (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) || 1043 (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 && 1044 (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) || 1045 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1046 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1047 return -EINVAL; 1048 } 1049 1050 mlxsw_pci->num_sdq_cqs = num_sdqs; 1051 1052 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1053 num_eqs); 1054 if (err) { 1055 dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1056 return err; 1057 } 1058 1059 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1060 num_cqs); 1061 if (err) { 1062 dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1063 goto err_cqs_init; 1064 } 1065 1066 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1067 num_sdqs); 1068 if (err) { 1069 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1070 goto err_sdqs_init; 1071 } 1072 1073 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1074 num_rdqs); 1075 if (err) { 1076 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1077 goto err_rdqs_init; 1078 } 1079 1080 /* We have to poll in command interface until queues are initialized */ 1081 mlxsw_pci->cmd.nopoll = true; 1082 return 0; 1083 1084 err_rdqs_init: 1085 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1086 err_sdqs_init: 1087 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1088 err_cqs_init: 1089 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1090 return err; 1091 } 1092 1093 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1094 { 1095 mlxsw_pci->cmd.nopoll = false; 1096 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1097 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1098 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1099 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1100 } 1101 1102 static void 1103 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1104 char *mbox, int index, 1105 const struct mlxsw_swid_config *swid) 1106 { 1107 u8 mask = 0; 1108 1109 if (swid->used_type) { 1110 mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1111 mbox, index, swid->type); 1112 mask |= 1; 1113 } 1114 if (swid->used_properties) { 1115 mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1116 mbox, index, swid->properties); 1117 mask |= 2; 1118 } 1119 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1120 } 1121 1122 static int 1123 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci, 1124 const struct mlxsw_config_profile *profile, 1125 struct mlxsw_res *res) 1126 { 1127 u64 single_size, double_size, linear_size; 1128 int err; 1129 1130 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile, 1131 &single_size, &double_size, 1132 &linear_size); 1133 if (err) 1134 return err; 1135 1136 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size); 1137 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size); 1138 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size); 1139 1140 return 0; 1141 } 1142 1143 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1144 const struct mlxsw_config_profile *profile, 1145 struct mlxsw_res *res) 1146 { 1147 int i; 1148 int err; 1149 1150 mlxsw_cmd_mbox_zero(mbox); 1151 1152 if (profile->used_max_vepa_channels) { 1153 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1154 mbox, 1); 1155 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1156 mbox, profile->max_vepa_channels); 1157 } 1158 if (profile->used_max_mid) { 1159 mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1160 mbox, 1); 1161 mlxsw_cmd_mbox_config_profile_max_mid_set( 1162 mbox, profile->max_mid); 1163 } 1164 if (profile->used_max_pgt) { 1165 mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1166 mbox, 1); 1167 mlxsw_cmd_mbox_config_profile_max_pgt_set( 1168 mbox, profile->max_pgt); 1169 } 1170 if (profile->used_max_system_port) { 1171 mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1172 mbox, 1); 1173 mlxsw_cmd_mbox_config_profile_max_system_port_set( 1174 mbox, profile->max_system_port); 1175 } 1176 if (profile->used_max_vlan_groups) { 1177 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1178 mbox, 1); 1179 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1180 mbox, profile->max_vlan_groups); 1181 } 1182 if (profile->used_max_regions) { 1183 mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1184 mbox, 1); 1185 mlxsw_cmd_mbox_config_profile_max_regions_set( 1186 mbox, profile->max_regions); 1187 } 1188 if (profile->used_flood_tables) { 1189 mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1190 mbox, 1); 1191 mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1192 mbox, profile->max_flood_tables); 1193 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1194 mbox, profile->max_vid_flood_tables); 1195 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 1196 mbox, profile->max_fid_offset_flood_tables); 1197 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 1198 mbox, profile->fid_offset_flood_table_size); 1199 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1200 mbox, profile->max_fid_flood_tables); 1201 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1202 mbox, profile->fid_flood_table_size); 1203 } 1204 if (profile->used_flood_mode) { 1205 mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1206 mbox, 1); 1207 mlxsw_cmd_mbox_config_profile_flood_mode_set( 1208 mbox, profile->flood_mode); 1209 } 1210 if (profile->used_max_ib_mc) { 1211 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1212 mbox, 1); 1213 mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1214 mbox, profile->max_ib_mc); 1215 } 1216 if (profile->used_max_pkey) { 1217 mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1218 mbox, 1); 1219 mlxsw_cmd_mbox_config_profile_max_pkey_set( 1220 mbox, profile->max_pkey); 1221 } 1222 if (profile->used_ar_sec) { 1223 mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1224 mbox, 1); 1225 mlxsw_cmd_mbox_config_profile_ar_sec_set( 1226 mbox, profile->ar_sec); 1227 } 1228 if (profile->used_adaptive_routing_group_cap) { 1229 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1230 mbox, 1); 1231 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1232 mbox, profile->adaptive_routing_group_cap); 1233 } 1234 if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) { 1235 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res); 1236 if (err) 1237 return err; 1238 1239 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1); 1240 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox, 1241 MLXSW_RES_GET(res, KVD_LINEAR_SIZE)); 1242 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox, 1243 1); 1244 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox, 1245 MLXSW_RES_GET(res, KVD_SINGLE_SIZE)); 1246 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set( 1247 mbox, 1); 1248 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox, 1249 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE)); 1250 } 1251 if (profile->used_kvh_xlt_cache_mode) { 1252 mlxsw_cmd_mbox_config_profile_set_kvh_xlt_cache_mode_set( 1253 mbox, 1); 1254 mlxsw_cmd_mbox_config_profile_kvh_xlt_cache_mode_set( 1255 mbox, profile->kvh_xlt_cache_mode); 1256 } 1257 1258 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1259 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1260 &profile->swid_config[i]); 1261 1262 if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) { 1263 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1); 1264 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1); 1265 } 1266 1267 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1268 } 1269 1270 static int mlxsw_pci_boardinfo_xm_process(struct mlxsw_pci *mlxsw_pci, 1271 struct mlxsw_bus_info *bus_info, 1272 char *mbox) 1273 { 1274 int count = mlxsw_cmd_mbox_boardinfo_xm_num_local_ports_get(mbox); 1275 int i; 1276 1277 if (!mlxsw_cmd_mbox_boardinfo_xm_exists_get(mbox)) 1278 return 0; 1279 1280 bus_info->xm_exists = true; 1281 1282 if (count > MLXSW_BUS_INFO_XM_LOCAL_PORTS_MAX) { 1283 dev_err(&mlxsw_pci->pdev->dev, "Invalid number of XM local ports\n"); 1284 return -EINVAL; 1285 } 1286 bus_info->xm_local_ports_count = count; 1287 for (i = 0; i < count; i++) 1288 bus_info->xm_local_ports[i] = 1289 mlxsw_cmd_mbox_boardinfo_xm_local_port_entry_get(mbox, 1290 i); 1291 return 0; 1292 } 1293 1294 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1295 { 1296 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1297 int err; 1298 1299 mlxsw_cmd_mbox_zero(mbox); 1300 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1301 if (err) 1302 return err; 1303 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1304 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1305 1306 return mlxsw_pci_boardinfo_xm_process(mlxsw_pci, bus_info, mbox); 1307 } 1308 1309 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1310 u16 num_pages) 1311 { 1312 struct mlxsw_pci_mem_item *mem_item; 1313 int nent = 0; 1314 int i; 1315 int err; 1316 1317 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1318 GFP_KERNEL); 1319 if (!mlxsw_pci->fw_area.items) 1320 return -ENOMEM; 1321 mlxsw_pci->fw_area.count = num_pages; 1322 1323 mlxsw_cmd_mbox_zero(mbox); 1324 for (i = 0; i < num_pages; i++) { 1325 mem_item = &mlxsw_pci->fw_area.items[i]; 1326 1327 mem_item->size = MLXSW_PCI_PAGE_SIZE; 1328 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 1329 mem_item->size, 1330 &mem_item->mapaddr, GFP_KERNEL); 1331 if (!mem_item->buf) { 1332 err = -ENOMEM; 1333 goto err_alloc; 1334 } 1335 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 1336 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 1337 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 1338 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1339 if (err) 1340 goto err_cmd_map_fa; 1341 nent = 0; 1342 mlxsw_cmd_mbox_zero(mbox); 1343 } 1344 } 1345 1346 if (nent) { 1347 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1348 if (err) 1349 goto err_cmd_map_fa; 1350 } 1351 1352 return 0; 1353 1354 err_cmd_map_fa: 1355 err_alloc: 1356 for (i--; i >= 0; i--) { 1357 mem_item = &mlxsw_pci->fw_area.items[i]; 1358 1359 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1360 mem_item->buf, mem_item->mapaddr); 1361 } 1362 kfree(mlxsw_pci->fw_area.items); 1363 return err; 1364 } 1365 1366 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1367 { 1368 struct mlxsw_pci_mem_item *mem_item; 1369 int i; 1370 1371 mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1372 1373 for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1374 mem_item = &mlxsw_pci->fw_area.items[i]; 1375 1376 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1377 mem_item->buf, mem_item->mapaddr); 1378 } 1379 kfree(mlxsw_pci->fw_area.items); 1380 } 1381 1382 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1383 { 1384 struct mlxsw_pci *mlxsw_pci = dev_id; 1385 struct mlxsw_pci_queue *q; 1386 int i; 1387 1388 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1389 q = mlxsw_pci_eq_get(mlxsw_pci, i); 1390 mlxsw_pci_queue_tasklet_schedule(q); 1391 } 1392 return IRQ_HANDLED; 1393 } 1394 1395 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 1396 struct mlxsw_pci_mem_item *mbox) 1397 { 1398 struct pci_dev *pdev = mlxsw_pci->pdev; 1399 int err = 0; 1400 1401 mbox->size = MLXSW_CMD_MBOX_SIZE; 1402 mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, 1403 &mbox->mapaddr, GFP_KERNEL); 1404 if (!mbox->buf) { 1405 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 1406 err = -ENOMEM; 1407 } 1408 1409 return err; 1410 } 1411 1412 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 1413 struct mlxsw_pci_mem_item *mbox) 1414 { 1415 struct pci_dev *pdev = mlxsw_pci->pdev; 1416 1417 dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 1418 mbox->mapaddr); 1419 } 1420 1421 static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, 1422 const struct pci_device_id *id, 1423 u32 *p_sys_status) 1424 { 1425 unsigned long end; 1426 u32 val; 1427 1428 /* We must wait for the HW to become responsive. */ 1429 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS); 1430 1431 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1432 do { 1433 val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1434 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 1435 return 0; 1436 cond_resched(); 1437 } while (time_before(jiffies, end)); 1438 1439 *p_sys_status = val & MLXSW_PCI_FW_READY_MASK; 1440 1441 return -EBUSY; 1442 } 1443 1444 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, 1445 const struct pci_device_id *id) 1446 { 1447 struct pci_dev *pdev = mlxsw_pci->pdev; 1448 char mrsr_pl[MLXSW_REG_MRSR_LEN]; 1449 u32 sys_status; 1450 int err; 1451 1452 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1453 if (err) { 1454 dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n", 1455 sys_status); 1456 return err; 1457 } 1458 1459 mlxsw_reg_mrsr_pack(mrsr_pl); 1460 err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 1461 if (err) 1462 return err; 1463 1464 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1465 if (err) { 1466 dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n", 1467 sys_status); 1468 return err; 1469 } 1470 1471 return 0; 1472 } 1473 1474 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1475 { 1476 int err; 1477 1478 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX); 1479 if (err < 0) 1480 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n"); 1481 return err; 1482 } 1483 1484 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1485 { 1486 pci_free_irq_vectors(mlxsw_pci->pdev); 1487 } 1488 1489 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1490 const struct mlxsw_config_profile *profile, 1491 struct mlxsw_res *res) 1492 { 1493 struct mlxsw_pci *mlxsw_pci = bus_priv; 1494 struct pci_dev *pdev = mlxsw_pci->pdev; 1495 char *mbox; 1496 u16 num_pages; 1497 int err; 1498 1499 mlxsw_pci->core = mlxsw_core; 1500 1501 mbox = mlxsw_cmd_mbox_alloc(); 1502 if (!mbox) 1503 return -ENOMEM; 1504 1505 err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id); 1506 if (err) 1507 goto err_sw_reset; 1508 1509 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); 1510 if (err < 0) { 1511 dev_err(&pdev->dev, "MSI-X init failed\n"); 1512 goto err_alloc_irq; 1513 } 1514 1515 err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1516 if (err) 1517 goto err_query_fw; 1518 1519 mlxsw_pci->bus_info.fw_rev.major = 1520 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1521 mlxsw_pci->bus_info.fw_rev.minor = 1522 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1523 mlxsw_pci->bus_info.fw_rev.subminor = 1524 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1525 1526 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1527 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1528 err = -EINVAL; 1529 goto err_iface_rev; 1530 } 1531 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1532 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1533 err = -EINVAL; 1534 goto err_doorbell_page_bar; 1535 } 1536 1537 mlxsw_pci->doorbell_offset = 1538 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1539 1540 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) { 1541 dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n"); 1542 err = -EINVAL; 1543 goto err_fr_rn_clk_bar; 1544 } 1545 1546 mlxsw_pci->free_running_clock_offset = 1547 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox); 1548 1549 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1550 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1551 if (err) 1552 goto err_fw_area_init; 1553 1554 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1555 if (err) 1556 goto err_boardinfo; 1557 1558 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 1559 if (err) 1560 goto err_query_resources; 1561 1562 if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) && 1563 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) 1564 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2; 1565 else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) && 1566 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) 1567 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1; 1568 else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) && 1569 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || 1570 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) { 1571 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0; 1572 } else { 1573 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n"); 1574 goto err_cqe_v_check; 1575 } 1576 1577 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res); 1578 if (err) 1579 goto err_config_profile; 1580 1581 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1582 if (err) 1583 goto err_aqs_init; 1584 1585 err = request_irq(pci_irq_vector(pdev, 0), 1586 mlxsw_pci_eq_irq_handler, 0, 1587 mlxsw_pci->bus_info.device_kind, mlxsw_pci); 1588 if (err) { 1589 dev_err(&pdev->dev, "IRQ request failed\n"); 1590 goto err_request_eq_irq; 1591 } 1592 1593 goto mbox_put; 1594 1595 err_request_eq_irq: 1596 mlxsw_pci_aqs_fini(mlxsw_pci); 1597 err_aqs_init: 1598 err_config_profile: 1599 err_cqe_v_check: 1600 err_query_resources: 1601 err_boardinfo: 1602 mlxsw_pci_fw_area_fini(mlxsw_pci); 1603 err_fw_area_init: 1604 err_fr_rn_clk_bar: 1605 err_doorbell_page_bar: 1606 err_iface_rev: 1607 err_query_fw: 1608 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1609 err_alloc_irq: 1610 err_sw_reset: 1611 mbox_put: 1612 mlxsw_cmd_mbox_free(mbox); 1613 return err; 1614 } 1615 1616 static void mlxsw_pci_fini(void *bus_priv) 1617 { 1618 struct mlxsw_pci *mlxsw_pci = bus_priv; 1619 1620 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 1621 mlxsw_pci_aqs_fini(mlxsw_pci); 1622 mlxsw_pci_fw_area_fini(mlxsw_pci); 1623 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1624 } 1625 1626 static struct mlxsw_pci_queue * 1627 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1628 const struct mlxsw_tx_info *tx_info) 1629 { 1630 u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1; 1631 u8 sdqn; 1632 1633 if (tx_info->is_emad) { 1634 sdqn = MLXSW_PCI_SDQ_EMAD_INDEX; 1635 } else { 1636 BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0); 1637 sdqn = 1 + (tx_info->local_port % ctl_sdq_count); 1638 } 1639 1640 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1641 } 1642 1643 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1644 const struct mlxsw_tx_info *tx_info) 1645 { 1646 struct mlxsw_pci *mlxsw_pci = bus_priv; 1647 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1648 1649 return !mlxsw_pci_queue_elem_info_producer_get(q); 1650 } 1651 1652 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1653 const struct mlxsw_tx_info *tx_info) 1654 { 1655 struct mlxsw_pci *mlxsw_pci = bus_priv; 1656 struct mlxsw_pci_queue *q; 1657 struct mlxsw_pci_queue_elem_info *elem_info; 1658 char *wqe; 1659 int i; 1660 int err; 1661 1662 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1663 err = skb_linearize(skb); 1664 if (err) 1665 return err; 1666 } 1667 1668 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1669 spin_lock_bh(&q->lock); 1670 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1671 if (!elem_info) { 1672 /* queue is full */ 1673 err = -EAGAIN; 1674 goto unlock; 1675 } 1676 mlxsw_skb_cb(skb)->tx_info = *tx_info; 1677 elem_info->u.sdq.skb = skb; 1678 1679 wqe = elem_info->elem; 1680 mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1681 mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1682 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1683 1684 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1685 skb_headlen(skb), DMA_TO_DEVICE); 1686 if (err) 1687 goto unlock; 1688 1689 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1690 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1691 1692 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1693 skb_frag_address(frag), 1694 skb_frag_size(frag), 1695 DMA_TO_DEVICE); 1696 if (err) 1697 goto unmap_frags; 1698 } 1699 1700 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 1701 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1702 1703 /* Set unused sq entries byte count to zero. */ 1704 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1705 mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1706 1707 /* Everything is set up, ring producer doorbell to get HW going */ 1708 q->producer_counter++; 1709 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1710 1711 goto unlock; 1712 1713 unmap_frags: 1714 for (; i >= 0; i--) 1715 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1716 unlock: 1717 spin_unlock_bh(&q->lock); 1718 return err; 1719 } 1720 1721 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1722 u32 in_mod, bool out_mbox_direct, 1723 char *in_mbox, size_t in_mbox_size, 1724 char *out_mbox, size_t out_mbox_size, 1725 u8 *p_status) 1726 { 1727 struct mlxsw_pci *mlxsw_pci = bus_priv; 1728 dma_addr_t in_mapaddr = 0, out_mapaddr = 0; 1729 bool evreq = mlxsw_pci->cmd.nopoll; 1730 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1731 bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1732 int err; 1733 1734 *p_status = MLXSW_CMD_STATUS_OK; 1735 1736 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1737 if (err) 1738 return err; 1739 1740 if (in_mbox) { 1741 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1742 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 1743 } 1744 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 1745 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 1746 1747 if (out_mbox) 1748 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1749 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 1750 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 1751 1752 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1753 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1754 1755 *p_wait_done = false; 1756 1757 wmb(); /* all needs to be written before we write control register */ 1758 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1759 MLXSW_PCI_CIR_CTRL_GO_BIT | 1760 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1761 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1762 opcode); 1763 1764 if (!evreq) { 1765 unsigned long end; 1766 1767 end = jiffies + timeout; 1768 do { 1769 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1770 1771 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1772 *p_wait_done = true; 1773 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1774 break; 1775 } 1776 cond_resched(); 1777 } while (time_before(jiffies, end)); 1778 } else { 1779 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1780 *p_status = mlxsw_pci->cmd.comp.status; 1781 } 1782 1783 err = 0; 1784 if (*p_wait_done) { 1785 if (*p_status) 1786 err = -EIO; 1787 } else { 1788 err = -ETIMEDOUT; 1789 } 1790 1791 if (!err && out_mbox && out_mbox_direct) { 1792 /* Some commands don't use output param as address to mailbox 1793 * but they store output directly into registers. In that case, 1794 * copy registers into mbox buffer. 1795 */ 1796 __be32 tmp; 1797 1798 if (!evreq) { 1799 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1800 CIR_OUT_PARAM_HI)); 1801 memcpy(out_mbox, &tmp, sizeof(tmp)); 1802 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1803 CIR_OUT_PARAM_LO)); 1804 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1805 } 1806 } else if (!err && out_mbox) { 1807 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1808 } 1809 1810 mutex_unlock(&mlxsw_pci->cmd.lock); 1811 1812 return err; 1813 } 1814 1815 static u32 mlxsw_pci_read_frc_h(void *bus_priv) 1816 { 1817 struct mlxsw_pci *mlxsw_pci = bus_priv; 1818 u64 frc_offset; 1819 1820 frc_offset = mlxsw_pci->free_running_clock_offset; 1821 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset)); 1822 } 1823 1824 static u32 mlxsw_pci_read_frc_l(void *bus_priv) 1825 { 1826 struct mlxsw_pci *mlxsw_pci = bus_priv; 1827 u64 frc_offset; 1828 1829 frc_offset = mlxsw_pci->free_running_clock_offset; 1830 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset)); 1831 } 1832 1833 static const struct mlxsw_bus mlxsw_pci_bus = { 1834 .kind = "pci", 1835 .init = mlxsw_pci_init, 1836 .fini = mlxsw_pci_fini, 1837 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 1838 .skb_transmit = mlxsw_pci_skb_transmit, 1839 .cmd_exec = mlxsw_pci_cmd_exec, 1840 .read_frc_h = mlxsw_pci_read_frc_h, 1841 .read_frc_l = mlxsw_pci_read_frc_l, 1842 .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, 1843 }; 1844 1845 static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci) 1846 { 1847 int err; 1848 1849 mutex_init(&mlxsw_pci->cmd.lock); 1850 init_waitqueue_head(&mlxsw_pci->cmd.wait); 1851 1852 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1853 if (err) 1854 goto err_in_mbox_alloc; 1855 1856 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1857 if (err) 1858 goto err_out_mbox_alloc; 1859 1860 return 0; 1861 1862 err_out_mbox_alloc: 1863 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1864 err_in_mbox_alloc: 1865 mutex_destroy(&mlxsw_pci->cmd.lock); 1866 return err; 1867 } 1868 1869 static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci) 1870 { 1871 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1872 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1873 mutex_destroy(&mlxsw_pci->cmd.lock); 1874 } 1875 1876 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1877 { 1878 const char *driver_name = dev_driver_string(&pdev->dev); 1879 struct mlxsw_pci *mlxsw_pci; 1880 int err; 1881 1882 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1883 if (!mlxsw_pci) 1884 return -ENOMEM; 1885 1886 err = pci_enable_device(pdev); 1887 if (err) { 1888 dev_err(&pdev->dev, "pci_enable_device failed\n"); 1889 goto err_pci_enable_device; 1890 } 1891 1892 err = pci_request_regions(pdev, driver_name); 1893 if (err) { 1894 dev_err(&pdev->dev, "pci_request_regions failed\n"); 1895 goto err_pci_request_regions; 1896 } 1897 1898 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1899 if (err) { 1900 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1901 if (err) { 1902 dev_err(&pdev->dev, "dma_set_mask failed\n"); 1903 goto err_pci_set_dma_mask; 1904 } 1905 } 1906 1907 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1908 dev_err(&pdev->dev, "invalid PCI region size\n"); 1909 err = -EINVAL; 1910 goto err_pci_resource_len_check; 1911 } 1912 1913 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1914 pci_resource_len(pdev, 0)); 1915 if (!mlxsw_pci->hw_addr) { 1916 dev_err(&pdev->dev, "ioremap failed\n"); 1917 err = -EIO; 1918 goto err_ioremap; 1919 } 1920 pci_set_master(pdev); 1921 1922 mlxsw_pci->pdev = pdev; 1923 pci_set_drvdata(pdev, mlxsw_pci); 1924 1925 err = mlxsw_pci_cmd_init(mlxsw_pci); 1926 if (err) 1927 goto err_pci_cmd_init; 1928 1929 mlxsw_pci->bus_info.device_kind = driver_name; 1930 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1931 mlxsw_pci->bus_info.dev = &pdev->dev; 1932 mlxsw_pci->bus_info.read_frc_capable = true; 1933 mlxsw_pci->id = id; 1934 1935 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 1936 &mlxsw_pci_bus, mlxsw_pci, false, 1937 NULL, NULL); 1938 if (err) { 1939 dev_err(&pdev->dev, "cannot register bus device\n"); 1940 goto err_bus_device_register; 1941 } 1942 1943 return 0; 1944 1945 err_bus_device_register: 1946 mlxsw_pci_cmd_fini(mlxsw_pci); 1947 err_pci_cmd_init: 1948 iounmap(mlxsw_pci->hw_addr); 1949 err_ioremap: 1950 err_pci_resource_len_check: 1951 err_pci_set_dma_mask: 1952 pci_release_regions(pdev); 1953 err_pci_request_regions: 1954 pci_disable_device(pdev); 1955 err_pci_enable_device: 1956 kfree(mlxsw_pci); 1957 return err; 1958 } 1959 1960 static void mlxsw_pci_remove(struct pci_dev *pdev) 1961 { 1962 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1963 1964 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 1965 mlxsw_pci_cmd_fini(mlxsw_pci); 1966 iounmap(mlxsw_pci->hw_addr); 1967 pci_release_regions(mlxsw_pci->pdev); 1968 pci_disable_device(mlxsw_pci->pdev); 1969 kfree(mlxsw_pci); 1970 } 1971 1972 int mlxsw_pci_driver_register(struct pci_driver *pci_driver) 1973 { 1974 pci_driver->probe = mlxsw_pci_probe; 1975 pci_driver->remove = mlxsw_pci_remove; 1976 return pci_register_driver(pci_driver); 1977 } 1978 EXPORT_SYMBOL(mlxsw_pci_driver_register); 1979 1980 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver) 1981 { 1982 pci_unregister_driver(pci_driver); 1983 } 1984 EXPORT_SYMBOL(mlxsw_pci_driver_unregister); 1985 1986 static int __init mlxsw_pci_module_init(void) 1987 { 1988 return 0; 1989 } 1990 1991 static void __exit mlxsw_pci_module_exit(void) 1992 { 1993 } 1994 1995 module_init(mlxsw_pci_module_init); 1996 module_exit(mlxsw_pci_module_exit); 1997 1998 MODULE_LICENSE("Dual BSD/GPL"); 1999 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 2000 MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 2001