19948a064SJiri Pirko // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 29948a064SJiri Pirko /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3eda6500aSJiri Pirko 4eda6500aSJiri Pirko #include <linux/kernel.h> 5eda6500aSJiri Pirko #include <linux/module.h> 6eda6500aSJiri Pirko #include <linux/export.h> 7eda6500aSJiri Pirko #include <linux/err.h> 8eda6500aSJiri Pirko #include <linux/device.h> 9eda6500aSJiri Pirko #include <linux/pci.h> 10eda6500aSJiri Pirko #include <linux/interrupt.h> 11eda6500aSJiri Pirko #include <linux/wait.h> 12eda6500aSJiri Pirko #include <linux/types.h> 13eda6500aSJiri Pirko #include <linux/skbuff.h> 14eda6500aSJiri Pirko #include <linux/if_vlan.h> 15eda6500aSJiri Pirko #include <linux/log2.h> 161e81779aSIdo Schimmel #include <linux/string.h> 17eda6500aSJiri Pirko 1862e86f9eSJiri Pirko #include "pci_hw.h" 191d20d23cSJiri Pirko #include "pci.h" 20eda6500aSJiri Pirko #include "core.h" 21eda6500aSJiri Pirko #include "cmd.h" 22eda6500aSJiri Pirko #include "port.h" 23c1a38311SJiri Pirko #include "resources.h" 24eda6500aSJiri Pirko 25eda6500aSJiri Pirko #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 26eda6500aSJiri Pirko iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 27eda6500aSJiri Pirko #define mlxsw_pci_read32(mlxsw_pci, reg) \ 28eda6500aSJiri Pirko ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 29eda6500aSJiri Pirko 30eda6500aSJiri Pirko enum mlxsw_pci_queue_type { 31eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, 32eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, 33eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_CQ, 34eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_EQ, 35eda6500aSJiri Pirko }; 36eda6500aSJiri Pirko 37eda6500aSJiri Pirko #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 38eda6500aSJiri Pirko 39eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_type_offset[] = { 40eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 41eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 42eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 43eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 44eda6500aSJiri Pirko }; 45eda6500aSJiri Pirko 46eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 47eda6500aSJiri Pirko 0, /* unused */ 48eda6500aSJiri Pirko 0, /* unused */ 49eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 50eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 51eda6500aSJiri Pirko }; 52eda6500aSJiri Pirko 53eda6500aSJiri Pirko struct mlxsw_pci_mem_item { 54eda6500aSJiri Pirko char *buf; 55eda6500aSJiri Pirko dma_addr_t mapaddr; 56eda6500aSJiri Pirko size_t size; 57eda6500aSJiri Pirko }; 58eda6500aSJiri Pirko 59eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info { 60eda6500aSJiri Pirko char *elem; /* pointer to actual dma mapped element mem chunk */ 61eda6500aSJiri Pirko union { 62eda6500aSJiri Pirko struct { 63eda6500aSJiri Pirko struct sk_buff *skb; 64eda6500aSJiri Pirko } sdq; 65eda6500aSJiri Pirko struct { 66eda6500aSJiri Pirko struct sk_buff *skb; 67eda6500aSJiri Pirko } rdq; 68eda6500aSJiri Pirko } u; 69eda6500aSJiri Pirko }; 70eda6500aSJiri Pirko 71eda6500aSJiri Pirko struct mlxsw_pci_queue { 72eda6500aSJiri Pirko spinlock_t lock; /* for queue accesses */ 73eda6500aSJiri Pirko struct mlxsw_pci_mem_item mem_item; 74eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 75eda6500aSJiri Pirko u16 producer_counter; 76eda6500aSJiri Pirko u16 consumer_counter; 77eda6500aSJiri Pirko u16 count; /* number of elements in queue */ 78eda6500aSJiri Pirko u8 num; /* queue number */ 79eda6500aSJiri Pirko u8 elem_size; /* size of one element */ 80eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 81eda6500aSJiri Pirko struct tasklet_struct tasklet; /* queue processing tasklet */ 82eda6500aSJiri Pirko struct mlxsw_pci *pci; 83eda6500aSJiri Pirko union { 84eda6500aSJiri Pirko struct { 85eda6500aSJiri Pirko u32 comp_sdq_count; 86eda6500aSJiri Pirko u32 comp_rdq_count; 87b76550bbSJiri Pirko enum mlxsw_pci_cqe_v v; 88eda6500aSJiri Pirko } cq; 89eda6500aSJiri Pirko struct { 90eda6500aSJiri Pirko u32 ev_cmd_count; 91eda6500aSJiri Pirko u32 ev_comp_count; 92eda6500aSJiri Pirko u32 ev_other_count; 93eda6500aSJiri Pirko } eq; 94eda6500aSJiri Pirko } u; 95eda6500aSJiri Pirko }; 96eda6500aSJiri Pirko 97eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group { 98eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 99eda6500aSJiri Pirko u8 count; /* number of queues in group */ 100eda6500aSJiri Pirko }; 101eda6500aSJiri Pirko 102eda6500aSJiri Pirko struct mlxsw_pci { 103eda6500aSJiri Pirko struct pci_dev *pdev; 104eda6500aSJiri Pirko u8 __iomem *hw_addr; 1058289169dSShalom Toledo u64 free_running_clock_offset; 106eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 107eda6500aSJiri Pirko u32 doorbell_offset; 108eda6500aSJiri Pirko struct mlxsw_core *core; 109eda6500aSJiri Pirko struct { 110eda6500aSJiri Pirko struct mlxsw_pci_mem_item *items; 1113e2206daSJiri Pirko unsigned int count; 112eda6500aSJiri Pirko } fw_area; 113eda6500aSJiri Pirko struct { 1141e81779aSIdo Schimmel struct mlxsw_pci_mem_item out_mbox; 1151e81779aSIdo Schimmel struct mlxsw_pci_mem_item in_mbox; 116eda6500aSJiri Pirko struct mutex lock; /* Lock access to command registers */ 117eda6500aSJiri Pirko bool nopoll; 118eda6500aSJiri Pirko wait_queue_head_t wait; 119eda6500aSJiri Pirko bool wait_done; 120eda6500aSJiri Pirko struct { 121eda6500aSJiri Pirko u8 status; 122eda6500aSJiri Pirko u64 out_param; 123eda6500aSJiri Pirko } comp; 124eda6500aSJiri Pirko } cmd; 125eda6500aSJiri Pirko struct mlxsw_bus_info bus_info; 12654a2e8d4SArkadi Sharshevsky const struct pci_device_id *id; 1278404f6f2SJiri Pirko enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ 1288404f6f2SJiri Pirko u8 num_sdq_cqs; /* Number of CQs used for SDQs */ 129eda6500aSJiri Pirko }; 130eda6500aSJiri Pirko 131eda6500aSJiri Pirko static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 132eda6500aSJiri Pirko { 133eda6500aSJiri Pirko tasklet_schedule(&q->tasklet); 134eda6500aSJiri Pirko } 135eda6500aSJiri Pirko 136eda6500aSJiri Pirko static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 137eda6500aSJiri Pirko size_t elem_size, int elem_index) 138eda6500aSJiri Pirko { 139eda6500aSJiri Pirko return q->mem_item.buf + (elem_size * elem_index); 140eda6500aSJiri Pirko } 141eda6500aSJiri Pirko 142eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 143eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 144eda6500aSJiri Pirko { 145eda6500aSJiri Pirko return &q->elem_info[elem_index]; 146eda6500aSJiri Pirko } 147eda6500aSJiri Pirko 148eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 149eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 150eda6500aSJiri Pirko { 151eda6500aSJiri Pirko int index = q->producer_counter & (q->count - 1); 152eda6500aSJiri Pirko 1535091730dSIdo Schimmel if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 154eda6500aSJiri Pirko return NULL; 155eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 156eda6500aSJiri Pirko } 157eda6500aSJiri Pirko 158eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 159eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 160eda6500aSJiri Pirko { 161eda6500aSJiri Pirko int index = q->consumer_counter & (q->count - 1); 162eda6500aSJiri Pirko 163eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 164eda6500aSJiri Pirko } 165eda6500aSJiri Pirko 166eda6500aSJiri Pirko static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 167eda6500aSJiri Pirko { 168eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 169eda6500aSJiri Pirko } 170eda6500aSJiri Pirko 171eda6500aSJiri Pirko static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 172eda6500aSJiri Pirko { 173eda6500aSJiri Pirko return owner_bit != !!(q->consumer_counter & q->count); 174eda6500aSJiri Pirko } 175eda6500aSJiri Pirko 176eda6500aSJiri Pirko static struct mlxsw_pci_queue_type_group * 177eda6500aSJiri Pirko mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 178eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 179eda6500aSJiri Pirko { 180eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type]; 181eda6500aSJiri Pirko } 182eda6500aSJiri Pirko 183eda6500aSJiri Pirko static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 184eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 185eda6500aSJiri Pirko { 186eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 187eda6500aSJiri Pirko 188eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 189eda6500aSJiri Pirko return queue_group->count; 190eda6500aSJiri Pirko } 191eda6500aSJiri Pirko 192eda6500aSJiri Pirko static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 193eda6500aSJiri Pirko { 194eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 195eda6500aSJiri Pirko } 196eda6500aSJiri Pirko 197eda6500aSJiri Pirko static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 198eda6500aSJiri Pirko { 199eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 200eda6500aSJiri Pirko } 201eda6500aSJiri Pirko 202eda6500aSJiri Pirko static struct mlxsw_pci_queue * 203eda6500aSJiri Pirko __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 204eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type, u8 q_num) 205eda6500aSJiri Pirko { 206eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type].q[q_num]; 207eda6500aSJiri Pirko } 208eda6500aSJiri Pirko 209eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 210eda6500aSJiri Pirko u8 q_num) 211eda6500aSJiri Pirko { 212eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 213eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 214eda6500aSJiri Pirko } 215eda6500aSJiri Pirko 216eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 217eda6500aSJiri Pirko u8 q_num) 218eda6500aSJiri Pirko { 219eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 220eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 221eda6500aSJiri Pirko } 222eda6500aSJiri Pirko 223eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 224eda6500aSJiri Pirko u8 q_num) 225eda6500aSJiri Pirko { 226eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 227eda6500aSJiri Pirko } 228eda6500aSJiri Pirko 229eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 230eda6500aSJiri Pirko u8 q_num) 231eda6500aSJiri Pirko { 232eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 233eda6500aSJiri Pirko } 234eda6500aSJiri Pirko 235eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 236eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 237eda6500aSJiri Pirko u16 val) 238eda6500aSJiri Pirko { 239eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 240eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 241eda6500aSJiri Pirko mlxsw_pci_doorbell_type_offset[q->type], 242eda6500aSJiri Pirko q->num), val); 243eda6500aSJiri Pirko } 244eda6500aSJiri Pirko 245eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 246eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 247eda6500aSJiri Pirko u16 val) 248eda6500aSJiri Pirko { 249eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 250eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 251eda6500aSJiri Pirko mlxsw_pci_doorbell_arm_type_offset[q->type], 252eda6500aSJiri Pirko q->num), val); 253eda6500aSJiri Pirko } 254eda6500aSJiri Pirko 255eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 256eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 257eda6500aSJiri Pirko { 258eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 259eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 260eda6500aSJiri Pirko } 261eda6500aSJiri Pirko 262eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 263eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 264eda6500aSJiri Pirko { 265eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 266eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 267eda6500aSJiri Pirko q->consumer_counter + q->count); 268eda6500aSJiri Pirko } 269eda6500aSJiri Pirko 270eda6500aSJiri Pirko static void 271eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 272eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 273eda6500aSJiri Pirko { 274eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 275eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 276eda6500aSJiri Pirko } 277eda6500aSJiri Pirko 278eda6500aSJiri Pirko static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 279eda6500aSJiri Pirko int page_index) 280eda6500aSJiri Pirko { 281eda6500aSJiri Pirko return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 282eda6500aSJiri Pirko } 283eda6500aSJiri Pirko 284eda6500aSJiri Pirko static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 285eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 286eda6500aSJiri Pirko { 2876aaee55cSPetr Machata int tclass; 288eda6500aSJiri Pirko int i; 289eda6500aSJiri Pirko int err; 290eda6500aSJiri Pirko 291eda6500aSJiri Pirko q->producer_counter = 0; 292eda6500aSJiri Pirko q->consumer_counter = 0; 2936aaee55cSPetr Machata tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC : 2946aaee55cSPetr Machata MLXSW_PCI_SDQ_CTL_TC; 295eda6500aSJiri Pirko 296eda6500aSJiri Pirko /* Set CQ of same number of this SDQ. */ 297eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 2986aaee55cSPetr Machata mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass); 299eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 300eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 301eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 302eda6500aSJiri Pirko 303eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 304eda6500aSJiri Pirko } 305eda6500aSJiri Pirko 306eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 307eda6500aSJiri Pirko if (err) 308eda6500aSJiri Pirko return err; 309eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 310eda6500aSJiri Pirko return 0; 311eda6500aSJiri Pirko } 312eda6500aSJiri Pirko 313eda6500aSJiri Pirko static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 314eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 315eda6500aSJiri Pirko { 316eda6500aSJiri Pirko mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 317eda6500aSJiri Pirko } 318eda6500aSJiri Pirko 319eda6500aSJiri Pirko static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 320eda6500aSJiri Pirko int index, char *frag_data, size_t frag_len, 321eda6500aSJiri Pirko int direction) 322eda6500aSJiri Pirko { 323eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 324eda6500aSJiri Pirko dma_addr_t mapaddr; 325eda6500aSJiri Pirko 326bb5c64c8SChristophe JAILLET mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction); 327bb5c64c8SChristophe JAILLET if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) { 3286cf9dc8bSJiri Pirko dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 329eda6500aSJiri Pirko return -EIO; 330eda6500aSJiri Pirko } 331eda6500aSJiri Pirko mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 332eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 333eda6500aSJiri Pirko return 0; 334eda6500aSJiri Pirko } 335eda6500aSJiri Pirko 336eda6500aSJiri Pirko static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 337eda6500aSJiri Pirko int index, int direction) 338eda6500aSJiri Pirko { 339eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 340eda6500aSJiri Pirko size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 341eda6500aSJiri Pirko dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 342eda6500aSJiri Pirko 343eda6500aSJiri Pirko if (!frag_len) 344eda6500aSJiri Pirko return; 345bb5c64c8SChristophe JAILLET dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); 346eda6500aSJiri Pirko } 347eda6500aSJiri Pirko 348eda6500aSJiri Pirko static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 349eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 350eda6500aSJiri Pirko { 351eda6500aSJiri Pirko size_t buf_len = MLXSW_PORT_MAX_MTU; 352eda6500aSJiri Pirko char *wqe = elem_info->elem; 353eda6500aSJiri Pirko struct sk_buff *skb; 354eda6500aSJiri Pirko int err; 355eda6500aSJiri Pirko 356eda6500aSJiri Pirko skb = netdev_alloc_skb_ip_align(NULL, buf_len); 357eda6500aSJiri Pirko if (!skb) 358eda6500aSJiri Pirko return -ENOMEM; 359eda6500aSJiri Pirko 360eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 361eda6500aSJiri Pirko buf_len, DMA_FROM_DEVICE); 362eda6500aSJiri Pirko if (err) 363eda6500aSJiri Pirko goto err_frag_map; 364eda6500aSJiri Pirko 365eda6500aSJiri Pirko elem_info->u.rdq.skb = skb; 366eda6500aSJiri Pirko return 0; 367eda6500aSJiri Pirko 368eda6500aSJiri Pirko err_frag_map: 369eda6500aSJiri Pirko dev_kfree_skb_any(skb); 370eda6500aSJiri Pirko return err; 371eda6500aSJiri Pirko } 372eda6500aSJiri Pirko 373eda6500aSJiri Pirko static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 374eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 375eda6500aSJiri Pirko { 376eda6500aSJiri Pirko struct sk_buff *skb; 377eda6500aSJiri Pirko char *wqe; 378eda6500aSJiri Pirko 379eda6500aSJiri Pirko skb = elem_info->u.rdq.skb; 380eda6500aSJiri Pirko wqe = elem_info->elem; 381eda6500aSJiri Pirko 382eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 383eda6500aSJiri Pirko dev_kfree_skb_any(skb); 384eda6500aSJiri Pirko } 385eda6500aSJiri Pirko 386eda6500aSJiri Pirko static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 387eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 388eda6500aSJiri Pirko { 389eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 390424e1114SJiri Pirko u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 391eda6500aSJiri Pirko int i; 392eda6500aSJiri Pirko int err; 393eda6500aSJiri Pirko 394eda6500aSJiri Pirko q->producer_counter = 0; 395eda6500aSJiri Pirko q->consumer_counter = 0; 396eda6500aSJiri Pirko 397eda6500aSJiri Pirko /* Set CQ of same number of this RDQ with base 398424e1114SJiri Pirko * above SDQ count as the lower ones are assigned to SDQs. 399eda6500aSJiri Pirko */ 400424e1114SJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 401eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 402eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 403eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 404eda6500aSJiri Pirko 405eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 406eda6500aSJiri Pirko } 407eda6500aSJiri Pirko 408eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 409eda6500aSJiri Pirko if (err) 410eda6500aSJiri Pirko return err; 411eda6500aSJiri Pirko 412eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 413eda6500aSJiri Pirko 414eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 415eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 416eda6500aSJiri Pirko BUG_ON(!elem_info); 417eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 418eda6500aSJiri Pirko if (err) 419eda6500aSJiri Pirko goto rollback; 420eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 421eda6500aSJiri Pirko q->producer_counter++; 422eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 423eda6500aSJiri Pirko } 424eda6500aSJiri Pirko 425eda6500aSJiri Pirko return 0; 426eda6500aSJiri Pirko 427eda6500aSJiri Pirko rollback: 428eda6500aSJiri Pirko for (i--; i >= 0; i--) { 429eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 430eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 431eda6500aSJiri Pirko } 432eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 433eda6500aSJiri Pirko 434eda6500aSJiri Pirko return err; 435eda6500aSJiri Pirko } 436eda6500aSJiri Pirko 437eda6500aSJiri Pirko static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 438eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 439eda6500aSJiri Pirko { 440eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 441eda6500aSJiri Pirko int i; 442eda6500aSJiri Pirko 443eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 444eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 445eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 446eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 447eda6500aSJiri Pirko } 448eda6500aSJiri Pirko } 449eda6500aSJiri Pirko 4508404f6f2SJiri Pirko static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci, 4518404f6f2SJiri Pirko struct mlxsw_pci_queue *q) 4528404f6f2SJiri Pirko { 4538404f6f2SJiri Pirko q->u.cq.v = mlxsw_pci->max_cqe_ver; 4548404f6f2SJiri Pirko 4558404f6f2SJiri Pirko /* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */ 4568404f6f2SJiri Pirko if (q->u.cq.v == MLXSW_PCI_CQE_V2 && 4578404f6f2SJiri Pirko q->num < mlxsw_pci->num_sdq_cqs) 4588404f6f2SJiri Pirko q->u.cq.v = MLXSW_PCI_CQE_V1; 4598404f6f2SJiri Pirko } 4608404f6f2SJiri Pirko 461eda6500aSJiri Pirko static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 462eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 463eda6500aSJiri Pirko { 464eda6500aSJiri Pirko int i; 465eda6500aSJiri Pirko int err; 466eda6500aSJiri Pirko 467eda6500aSJiri Pirko q->consumer_counter = 0; 468eda6500aSJiri Pirko 469eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 470eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 471eda6500aSJiri Pirko 472b76550bbSJiri Pirko mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1); 473eda6500aSJiri Pirko } 474eda6500aSJiri Pirko 4758404f6f2SJiri Pirko if (q->u.cq.v == MLXSW_PCI_CQE_V1) 4768404f6f2SJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 4778404f6f2SJiri Pirko MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1); 4788404f6f2SJiri Pirko else if (q->u.cq.v == MLXSW_PCI_CQE_V2) 4798404f6f2SJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 4808404f6f2SJiri Pirko MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2); 4818404f6f2SJiri Pirko 482eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 483eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 484eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 485eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 486eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 487eda6500aSJiri Pirko 488eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 489eda6500aSJiri Pirko } 490eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 491eda6500aSJiri Pirko if (err) 492eda6500aSJiri Pirko return err; 493eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 494eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 495eda6500aSJiri Pirko return 0; 496eda6500aSJiri Pirko } 497eda6500aSJiri Pirko 498eda6500aSJiri Pirko static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 499eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 500eda6500aSJiri Pirko { 501eda6500aSJiri Pirko mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 502eda6500aSJiri Pirko } 503eda6500aSJiri Pirko 504eda6500aSJiri Pirko static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 505eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 506eda6500aSJiri Pirko u16 consumer_counter_limit, 507eda6500aSJiri Pirko char *cqe) 508eda6500aSJiri Pirko { 509eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 510eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 5110714256cSPetr Machata struct mlxsw_tx_info tx_info; 512eda6500aSJiri Pirko char *wqe; 513eda6500aSJiri Pirko struct sk_buff *skb; 514eda6500aSJiri Pirko int i; 515eda6500aSJiri Pirko 516eda6500aSJiri Pirko spin_lock(&q->lock); 517eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 5180714256cSPetr Machata tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info; 519eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 520eda6500aSJiri Pirko wqe = elem_info->elem; 521eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 522eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 5230714256cSPetr Machata 5240714256cSPetr Machata if (unlikely(!tx_info.is_emad && 5250714256cSPetr Machata skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5260714256cSPetr Machata mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb, 5270714256cSPetr Machata tx_info.local_port); 5280714256cSPetr Machata skb = NULL; 5290714256cSPetr Machata } 5300714256cSPetr Machata 5310714256cSPetr Machata if (skb) 532eda6500aSJiri Pirko dev_kfree_skb_any(skb); 533eda6500aSJiri Pirko elem_info->u.sdq.skb = NULL; 534eda6500aSJiri Pirko 535eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 536eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 537eda6500aSJiri Pirko spin_unlock(&q->lock); 538eda6500aSJiri Pirko } 539eda6500aSJiri Pirko 5405ab6dc9fSIdo Schimmel static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb, 5415ab6dc9fSIdo Schimmel const char *cqe) 5425ab6dc9fSIdo Schimmel { 5435ab6dc9fSIdo Schimmel struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 5445ab6dc9fSIdo Schimmel 5455ab6dc9fSIdo Schimmel if (mlxsw_pci_cqe2_tx_lag_get(cqe)) { 5465ab6dc9fSIdo Schimmel cb->rx_md_info.tx_port_is_lag = true; 5475ab6dc9fSIdo Schimmel cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe); 5485ab6dc9fSIdo Schimmel cb->rx_md_info.tx_lag_port_index = 5495ab6dc9fSIdo Schimmel mlxsw_pci_cqe2_tx_lag_subport_get(cqe); 5505ab6dc9fSIdo Schimmel } else { 5515ab6dc9fSIdo Schimmel cb->rx_md_info.tx_port_is_lag = false; 5525ab6dc9fSIdo Schimmel cb->rx_md_info.tx_sys_port = 5535ab6dc9fSIdo Schimmel mlxsw_pci_cqe2_tx_system_port_get(cqe); 5545ab6dc9fSIdo Schimmel } 5555ab6dc9fSIdo Schimmel 5565ab6dc9fSIdo Schimmel if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT && 5575ab6dc9fSIdo Schimmel cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID) 5585ab6dc9fSIdo Schimmel cb->rx_md_info.tx_port_valid = 1; 5595ab6dc9fSIdo Schimmel else 5605ab6dc9fSIdo Schimmel cb->rx_md_info.tx_port_valid = 0; 5615ab6dc9fSIdo Schimmel } 5625ab6dc9fSIdo Schimmel 5635ab6dc9fSIdo Schimmel static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe) 5645ab6dc9fSIdo Schimmel { 5655ab6dc9fSIdo Schimmel struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 5665ab6dc9fSIdo Schimmel 5675ab6dc9fSIdo Schimmel cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe); 5685ab6dc9fSIdo Schimmel if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID) 5695ab6dc9fSIdo Schimmel cb->rx_md_info.tx_congestion_valid = 1; 5705ab6dc9fSIdo Schimmel else 5715ab6dc9fSIdo Schimmel cb->rx_md_info.tx_congestion_valid = 0; 5725ab6dc9fSIdo Schimmel cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT; 5735ab6dc9fSIdo Schimmel 5745ab6dc9fSIdo Schimmel cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe); 5755ab6dc9fSIdo Schimmel if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID) 5765ab6dc9fSIdo Schimmel cb->rx_md_info.latency_valid = 1; 5775ab6dc9fSIdo Schimmel else 5785ab6dc9fSIdo Schimmel cb->rx_md_info.latency_valid = 0; 5795ab6dc9fSIdo Schimmel 5805ab6dc9fSIdo Schimmel cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe); 5815ab6dc9fSIdo Schimmel if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID) 5825ab6dc9fSIdo Schimmel cb->rx_md_info.tx_tc_valid = 1; 5835ab6dc9fSIdo Schimmel else 5845ab6dc9fSIdo Schimmel cb->rx_md_info.tx_tc_valid = 0; 5855ab6dc9fSIdo Schimmel 5865ab6dc9fSIdo Schimmel mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 5875ab6dc9fSIdo Schimmel } 5885ab6dc9fSIdo Schimmel 589eda6500aSJiri Pirko static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 590eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 591eda6500aSJiri Pirko u16 consumer_counter_limit, 592b76550bbSJiri Pirko enum mlxsw_pci_cqe_v cqe_v, char *cqe) 593eda6500aSJiri Pirko { 594eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 595eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 596eacc86ecSIdo Schimmel struct mlxsw_rx_info rx_info = {}; 597*75963576SIdo Schimmel char wqe[MLXSW_PCI_WQE_SIZE]; 598eda6500aSJiri Pirko struct sk_buff *skb; 5997b7b9cffSJiri Pirko u16 byte_count; 600eda6500aSJiri Pirko int err; 601eda6500aSJiri Pirko 602eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 603*75963576SIdo Schimmel skb = elem_info->u.rdq.skb; 604*75963576SIdo Schimmel memcpy(wqe, elem_info->elem, MLXSW_PCI_WQE_SIZE); 605eda6500aSJiri Pirko 606eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 607eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 608eda6500aSJiri Pirko 609*75963576SIdo Schimmel err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 610*75963576SIdo Schimmel if (err) { 611*75963576SIdo Schimmel dev_err_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); 612*75963576SIdo Schimmel goto out; 613*75963576SIdo Schimmel } 614*75963576SIdo Schimmel 615*75963576SIdo Schimmel mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 616*75963576SIdo Schimmel 617b76550bbSJiri Pirko if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { 618d2292e87SJiri Pirko rx_info.is_lag = true; 619b76550bbSJiri Pirko rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); 620b76550bbSJiri Pirko rx_info.lag_port_index = 621b76550bbSJiri Pirko mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); 622d2292e87SJiri Pirko } else { 6238060646aSJiri Pirko rx_info.is_lag = false; 6248060646aSJiri Pirko rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 625d2292e87SJiri Pirko } 6268060646aSJiri Pirko 627eda6500aSJiri Pirko rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 628eda6500aSJiri Pirko 62978a7dcb7SJiri Pirko if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL || 63078a7dcb7SJiri Pirko rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) { 63178a7dcb7SJiri Pirko u32 cookie_index = 0; 63278a7dcb7SJiri Pirko 63378a7dcb7SJiri Pirko if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) 63478a7dcb7SJiri Pirko cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe); 635d4cabaadSIdo Schimmel mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index; 636eacc86ecSIdo Schimmel } else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 && 637eacc86ecSIdo Schimmel rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 && 638eacc86ecSIdo Schimmel mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 639eacc86ecSIdo Schimmel rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe); 6405ab6dc9fSIdo Schimmel mlxsw_pci_cqe_rdq_md_init(skb, cqe); 6415ab6dc9fSIdo Schimmel } else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE && 6425ab6dc9fSIdo Schimmel mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 6435ab6dc9fSIdo Schimmel mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 64478a7dcb7SJiri Pirko } 64578a7dcb7SJiri Pirko 6467b7b9cffSJiri Pirko byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 647b76550bbSJiri Pirko if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) 6487b7b9cffSJiri Pirko byte_count -= ETH_FCS_LEN; 6497b7b9cffSJiri Pirko skb_put(skb, byte_count); 650eda6500aSJiri Pirko mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 651eda6500aSJiri Pirko 652*75963576SIdo Schimmel out: 653eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 654eda6500aSJiri Pirko q->producer_counter++; 655eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 656eda6500aSJiri Pirko return; 657eda6500aSJiri Pirko } 658eda6500aSJiri Pirko 659eda6500aSJiri Pirko static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 660eda6500aSJiri Pirko { 661b76550bbSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 662b76550bbSJiri Pirko char *elem; 663b76550bbSJiri Pirko bool owner_bit; 664b76550bbSJiri Pirko 665b76550bbSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 666b76550bbSJiri Pirko elem = elem_info->elem; 667b76550bbSJiri Pirko owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem); 668b76550bbSJiri Pirko if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 669b76550bbSJiri Pirko return NULL; 670b76550bbSJiri Pirko q->consumer_counter++; 671b76550bbSJiri Pirko rmb(); /* make sure we read owned bit before the rest of elem */ 672b76550bbSJiri Pirko return elem; 673eda6500aSJiri Pirko } 674eda6500aSJiri Pirko 675a1be161aSAllen Pais static void mlxsw_pci_cq_tasklet(struct tasklet_struct *t) 676eda6500aSJiri Pirko { 677a1be161aSAllen Pais struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 678eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 679eda6500aSJiri Pirko char *cqe; 680eda6500aSJiri Pirko int items = 0; 681eda6500aSJiri Pirko int credits = q->count >> 1; 682eda6500aSJiri Pirko 683eda6500aSJiri Pirko while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 684eda6500aSJiri Pirko u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 685b76550bbSJiri Pirko u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 686b76550bbSJiri Pirko u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 687c9ebea04SIdo Schimmel char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; 688c9ebea04SIdo Schimmel 689c9ebea04SIdo Schimmel memcpy(ncqe, cqe, q->elem_size); 690c9ebea04SIdo Schimmel mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 691eda6500aSJiri Pirko 692eda6500aSJiri Pirko if (sendq) { 693eda6500aSJiri Pirko struct mlxsw_pci_queue *sdq; 694eda6500aSJiri Pirko 695eda6500aSJiri Pirko sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 696eda6500aSJiri Pirko mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 697c9ebea04SIdo Schimmel wqe_counter, ncqe); 698eda6500aSJiri Pirko q->u.cq.comp_sdq_count++; 699eda6500aSJiri Pirko } else { 700eda6500aSJiri Pirko struct mlxsw_pci_queue *rdq; 701eda6500aSJiri Pirko 702eda6500aSJiri Pirko rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 703eda6500aSJiri Pirko mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 704c9ebea04SIdo Schimmel wqe_counter, q->u.cq.v, ncqe); 705eda6500aSJiri Pirko q->u.cq.comp_rdq_count++; 706eda6500aSJiri Pirko } 707eda6500aSJiri Pirko if (++items == credits) 708eda6500aSJiri Pirko break; 709eda6500aSJiri Pirko } 710c9ebea04SIdo Schimmel if (items) 711eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 712eda6500aSJiri Pirko } 713eda6500aSJiri Pirko 7148404f6f2SJiri Pirko static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q) 7158404f6f2SJiri Pirko { 7168404f6f2SJiri Pirko return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT : 7178404f6f2SJiri Pirko MLXSW_PCI_CQE01_COUNT; 7188404f6f2SJiri Pirko } 7198404f6f2SJiri Pirko 7208404f6f2SJiri Pirko static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q) 7218404f6f2SJiri Pirko { 7228404f6f2SJiri Pirko return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE : 7238404f6f2SJiri Pirko MLXSW_PCI_CQE01_SIZE; 7248404f6f2SJiri Pirko } 7258404f6f2SJiri Pirko 726eda6500aSJiri Pirko static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 727eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 728eda6500aSJiri Pirko { 729eda6500aSJiri Pirko int i; 730eda6500aSJiri Pirko int err; 731eda6500aSJiri Pirko 732eda6500aSJiri Pirko q->consumer_counter = 0; 733eda6500aSJiri Pirko 734eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 735eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 736eda6500aSJiri Pirko 737eda6500aSJiri Pirko mlxsw_pci_eqe_owner_set(elem, 1); 738eda6500aSJiri Pirko } 739eda6500aSJiri Pirko 740eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 741eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 742eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 743eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 744eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 745eda6500aSJiri Pirko 746eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 747eda6500aSJiri Pirko } 748eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 749eda6500aSJiri Pirko if (err) 750eda6500aSJiri Pirko return err; 751eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 752eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 753eda6500aSJiri Pirko return 0; 754eda6500aSJiri Pirko } 755eda6500aSJiri Pirko 756eda6500aSJiri Pirko static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 757eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 758eda6500aSJiri Pirko { 759eda6500aSJiri Pirko mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 760eda6500aSJiri Pirko } 761eda6500aSJiri Pirko 762eda6500aSJiri Pirko static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 763eda6500aSJiri Pirko { 764eda6500aSJiri Pirko mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 765eda6500aSJiri Pirko mlxsw_pci->cmd.comp.out_param = 766eda6500aSJiri Pirko ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 767eda6500aSJiri Pirko mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 768eda6500aSJiri Pirko mlxsw_pci->cmd.wait_done = true; 769eda6500aSJiri Pirko wake_up(&mlxsw_pci->cmd.wait); 770eda6500aSJiri Pirko } 771eda6500aSJiri Pirko 772eda6500aSJiri Pirko static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 773eda6500aSJiri Pirko { 774b76550bbSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 775b76550bbSJiri Pirko char *elem; 776b76550bbSJiri Pirko bool owner_bit; 777b76550bbSJiri Pirko 778b76550bbSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 779b76550bbSJiri Pirko elem = elem_info->elem; 780b76550bbSJiri Pirko owner_bit = mlxsw_pci_eqe_owner_get(elem); 781b76550bbSJiri Pirko if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 782b76550bbSJiri Pirko return NULL; 783b76550bbSJiri Pirko q->consumer_counter++; 784b76550bbSJiri Pirko rmb(); /* make sure we read owned bit before the rest of elem */ 785b76550bbSJiri Pirko return elem; 786eda6500aSJiri Pirko } 787eda6500aSJiri Pirko 788a1be161aSAllen Pais static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t) 789eda6500aSJiri Pirko { 790a1be161aSAllen Pais struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); 791eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 792e4c870b1SJiri Pirko u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 793e4c870b1SJiri Pirko unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 794eda6500aSJiri Pirko char *eqe; 795eda6500aSJiri Pirko u8 cqn; 796eda6500aSJiri Pirko bool cq_handle = false; 797eda6500aSJiri Pirko int items = 0; 798eda6500aSJiri Pirko int credits = q->count >> 1; 799eda6500aSJiri Pirko 800eda6500aSJiri Pirko memset(&active_cqns, 0, sizeof(active_cqns)); 801eda6500aSJiri Pirko 802eda6500aSJiri Pirko while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 803eda6500aSJiri Pirko 804f3c84a8eSNir Dotan /* Command interface completion events are always received on 805f3c84a8eSNir Dotan * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events 806f3c84a8eSNir Dotan * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1). 807f3c84a8eSNir Dotan */ 808f3c84a8eSNir Dotan switch (q->num) { 809f3c84a8eSNir Dotan case MLXSW_PCI_EQ_ASYNC_NUM: 810eda6500aSJiri Pirko mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 811eda6500aSJiri Pirko q->u.eq.ev_cmd_count++; 812eda6500aSJiri Pirko break; 813f3c84a8eSNir Dotan case MLXSW_PCI_EQ_COMP_NUM: 814eda6500aSJiri Pirko cqn = mlxsw_pci_eqe_cqn_get(eqe); 815eda6500aSJiri Pirko set_bit(cqn, active_cqns); 816eda6500aSJiri Pirko cq_handle = true; 817eda6500aSJiri Pirko q->u.eq.ev_comp_count++; 818eda6500aSJiri Pirko break; 819eda6500aSJiri Pirko default: 820eda6500aSJiri Pirko q->u.eq.ev_other_count++; 821eda6500aSJiri Pirko } 822eda6500aSJiri Pirko if (++items == credits) 823eda6500aSJiri Pirko break; 824eda6500aSJiri Pirko } 825eda6500aSJiri Pirko if (items) { 826eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 827eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 828eda6500aSJiri Pirko } 829eda6500aSJiri Pirko 830eda6500aSJiri Pirko if (!cq_handle) 831eda6500aSJiri Pirko return; 832e4c870b1SJiri Pirko for_each_set_bit(cqn, active_cqns, cq_count) { 833eda6500aSJiri Pirko q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 834eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 835eda6500aSJiri Pirko } 836eda6500aSJiri Pirko } 837eda6500aSJiri Pirko 838eda6500aSJiri Pirko struct mlxsw_pci_queue_ops { 839eda6500aSJiri Pirko const char *name; 840eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 8418404f6f2SJiri Pirko void (*pre_init)(struct mlxsw_pci *mlxsw_pci, 8428404f6f2SJiri Pirko struct mlxsw_pci_queue *q); 843eda6500aSJiri Pirko int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 844eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 845eda6500aSJiri Pirko void (*fini)(struct mlxsw_pci *mlxsw_pci, 846eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 847a1be161aSAllen Pais void (*tasklet)(struct tasklet_struct *t); 8488404f6f2SJiri Pirko u16 (*elem_count_f)(const struct mlxsw_pci_queue *q); 8498404f6f2SJiri Pirko u8 (*elem_size_f)(const struct mlxsw_pci_queue *q); 850eda6500aSJiri Pirko u16 elem_count; 851eda6500aSJiri Pirko u8 elem_size; 852eda6500aSJiri Pirko }; 853eda6500aSJiri Pirko 854eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 855eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 856eda6500aSJiri Pirko .init = mlxsw_pci_sdq_init, 857eda6500aSJiri Pirko .fini = mlxsw_pci_sdq_fini, 858eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 859eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE, 860eda6500aSJiri Pirko }; 861eda6500aSJiri Pirko 862eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 863eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 864eda6500aSJiri Pirko .init = mlxsw_pci_rdq_init, 865eda6500aSJiri Pirko .fini = mlxsw_pci_rdq_fini, 866eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 867eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE 868eda6500aSJiri Pirko }; 869eda6500aSJiri Pirko 870eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 871eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_CQ, 8728404f6f2SJiri Pirko .pre_init = mlxsw_pci_cq_pre_init, 873eda6500aSJiri Pirko .init = mlxsw_pci_cq_init, 874eda6500aSJiri Pirko .fini = mlxsw_pci_cq_fini, 875eda6500aSJiri Pirko .tasklet = mlxsw_pci_cq_tasklet, 8768404f6f2SJiri Pirko .elem_count_f = mlxsw_pci_cq_elem_count, 8778404f6f2SJiri Pirko .elem_size_f = mlxsw_pci_cq_elem_size 878eda6500aSJiri Pirko }; 879eda6500aSJiri Pirko 880eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 881eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_EQ, 882eda6500aSJiri Pirko .init = mlxsw_pci_eq_init, 883eda6500aSJiri Pirko .fini = mlxsw_pci_eq_fini, 884eda6500aSJiri Pirko .tasklet = mlxsw_pci_eq_tasklet, 885eda6500aSJiri Pirko .elem_count = MLXSW_PCI_EQE_COUNT, 886eda6500aSJiri Pirko .elem_size = MLXSW_PCI_EQE_SIZE 887eda6500aSJiri Pirko }; 888eda6500aSJiri Pirko 889eda6500aSJiri Pirko static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 890eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 891eda6500aSJiri Pirko struct mlxsw_pci_queue *q, u8 q_num) 892eda6500aSJiri Pirko { 893eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 894eda6500aSJiri Pirko int i; 895eda6500aSJiri Pirko int err; 896eda6500aSJiri Pirko 8978404f6f2SJiri Pirko q->num = q_num; 8988404f6f2SJiri Pirko if (q_ops->pre_init) 8998404f6f2SJiri Pirko q_ops->pre_init(mlxsw_pci, q); 900b76550bbSJiri Pirko 901eda6500aSJiri Pirko spin_lock_init(&q->lock); 9028404f6f2SJiri Pirko q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) : 9038404f6f2SJiri Pirko q_ops->elem_count; 9048404f6f2SJiri Pirko q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) : 9058404f6f2SJiri Pirko q_ops->elem_size; 906eda6500aSJiri Pirko q->type = q_ops->type; 907eda6500aSJiri Pirko q->pci = mlxsw_pci; 908eda6500aSJiri Pirko 909eda6500aSJiri Pirko if (q_ops->tasklet) 910a1be161aSAllen Pais tasklet_setup(&q->tasklet, q_ops->tasklet); 911eda6500aSJiri Pirko 912eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_AQ_SIZE; 913bb5c64c8SChristophe JAILLET mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 914bb5c64c8SChristophe JAILLET mem_item->size, &mem_item->mapaddr, 915bb5c64c8SChristophe JAILLET GFP_KERNEL); 916eda6500aSJiri Pirko if (!mem_item->buf) 917eda6500aSJiri Pirko return -ENOMEM; 918eda6500aSJiri Pirko 919eda6500aSJiri Pirko q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 920eda6500aSJiri Pirko if (!q->elem_info) { 921eda6500aSJiri Pirko err = -ENOMEM; 922eda6500aSJiri Pirko goto err_elem_info_alloc; 923eda6500aSJiri Pirko } 924eda6500aSJiri Pirko 925eda6500aSJiri Pirko /* Initialize dma mapped elements info elem_info for 926eda6500aSJiri Pirko * future easy access. 927eda6500aSJiri Pirko */ 928eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 929eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 930eda6500aSJiri Pirko 931eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 932eda6500aSJiri Pirko elem_info->elem = 9338404f6f2SJiri Pirko __mlxsw_pci_queue_elem_get(q, q->elem_size, i); 934eda6500aSJiri Pirko } 935eda6500aSJiri Pirko 936eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 937eda6500aSJiri Pirko err = q_ops->init(mlxsw_pci, mbox, q); 938eda6500aSJiri Pirko if (err) 939eda6500aSJiri Pirko goto err_q_ops_init; 940eda6500aSJiri Pirko return 0; 941eda6500aSJiri Pirko 942eda6500aSJiri Pirko err_q_ops_init: 943eda6500aSJiri Pirko kfree(q->elem_info); 944eda6500aSJiri Pirko err_elem_info_alloc: 945bb5c64c8SChristophe JAILLET dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 946eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 947eda6500aSJiri Pirko return err; 948eda6500aSJiri Pirko } 949eda6500aSJiri Pirko 950eda6500aSJiri Pirko static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 951eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 952eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 953eda6500aSJiri Pirko { 954eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 955eda6500aSJiri Pirko 956eda6500aSJiri Pirko q_ops->fini(mlxsw_pci, q); 957eda6500aSJiri Pirko kfree(q->elem_info); 958bb5c64c8SChristophe JAILLET dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 959eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 960eda6500aSJiri Pirko } 961eda6500aSJiri Pirko 962eda6500aSJiri Pirko static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 963eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 964eda6500aSJiri Pirko u8 num_qs) 965eda6500aSJiri Pirko { 966eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 967eda6500aSJiri Pirko int i; 968eda6500aSJiri Pirko int err; 969eda6500aSJiri Pirko 970eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 971eda6500aSJiri Pirko queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 972eda6500aSJiri Pirko if (!queue_group->q) 973eda6500aSJiri Pirko return -ENOMEM; 974eda6500aSJiri Pirko 975eda6500aSJiri Pirko for (i = 0; i < num_qs; i++) { 976eda6500aSJiri Pirko err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 977eda6500aSJiri Pirko &queue_group->q[i], i); 978eda6500aSJiri Pirko if (err) 979eda6500aSJiri Pirko goto err_queue_init; 980eda6500aSJiri Pirko } 981eda6500aSJiri Pirko queue_group->count = num_qs; 982eda6500aSJiri Pirko 983eda6500aSJiri Pirko return 0; 984eda6500aSJiri Pirko 985eda6500aSJiri Pirko err_queue_init: 986eda6500aSJiri Pirko for (i--; i >= 0; i--) 987eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 988eda6500aSJiri Pirko kfree(queue_group->q); 989eda6500aSJiri Pirko return err; 990eda6500aSJiri Pirko } 991eda6500aSJiri Pirko 992eda6500aSJiri Pirko static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 993eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops) 994eda6500aSJiri Pirko { 995eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 996eda6500aSJiri Pirko int i; 997eda6500aSJiri Pirko 998eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 999eda6500aSJiri Pirko for (i = 0; i < queue_group->count; i++) 1000eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1001eda6500aSJiri Pirko kfree(queue_group->q); 1002eda6500aSJiri Pirko } 1003eda6500aSJiri Pirko 1004eda6500aSJiri Pirko static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1005eda6500aSJiri Pirko { 1006eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1007eda6500aSJiri Pirko u8 num_sdqs; 1008eda6500aSJiri Pirko u8 sdq_log2sz; 1009eda6500aSJiri Pirko u8 num_rdqs; 1010eda6500aSJiri Pirko u8 rdq_log2sz; 1011eda6500aSJiri Pirko u8 num_cqs; 1012eda6500aSJiri Pirko u8 cq_log2sz; 101341107685SJiri Pirko u8 cqv2_log2sz; 1014eda6500aSJiri Pirko u8 num_eqs; 1015eda6500aSJiri Pirko u8 eq_log2sz; 1016eda6500aSJiri Pirko int err; 1017eda6500aSJiri Pirko 1018eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1019eda6500aSJiri Pirko err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1020eda6500aSJiri Pirko if (err) 1021eda6500aSJiri Pirko return err; 1022eda6500aSJiri Pirko 1023eda6500aSJiri Pirko num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1024eda6500aSJiri Pirko sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1025eda6500aSJiri Pirko num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1026eda6500aSJiri Pirko rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1027eda6500aSJiri Pirko num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1028eda6500aSJiri Pirko cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 102941107685SJiri Pirko cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox); 1030eda6500aSJiri Pirko num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1031eda6500aSJiri Pirko eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1032eda6500aSJiri Pirko 1033c85c3882SJiri Pirko if (num_sdqs + num_rdqs > num_cqs || 10346aaee55cSPetr Machata num_sdqs < MLXSW_PCI_SDQS_MIN || 1035e4c870b1SJiri Pirko num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 1036eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of queues\n"); 1037eda6500aSJiri Pirko return -EINVAL; 1038eda6500aSJiri Pirko } 1039eda6500aSJiri Pirko 1040eda6500aSJiri Pirko if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1041eda6500aSJiri Pirko (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1042b76550bbSJiri Pirko (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) || 104341107685SJiri Pirko (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 && 104441107685SJiri Pirko (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) || 1045eda6500aSJiri Pirko (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1046eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1047eda6500aSJiri Pirko return -EINVAL; 1048eda6500aSJiri Pirko } 1049eda6500aSJiri Pirko 10508404f6f2SJiri Pirko mlxsw_pci->num_sdq_cqs = num_sdqs; 10518404f6f2SJiri Pirko 1052eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1053eda6500aSJiri Pirko num_eqs); 1054eda6500aSJiri Pirko if (err) { 1055eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1056eda6500aSJiri Pirko return err; 1057eda6500aSJiri Pirko } 1058eda6500aSJiri Pirko 1059eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1060eda6500aSJiri Pirko num_cqs); 1061eda6500aSJiri Pirko if (err) { 1062eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1063eda6500aSJiri Pirko goto err_cqs_init; 1064eda6500aSJiri Pirko } 1065eda6500aSJiri Pirko 1066eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1067eda6500aSJiri Pirko num_sdqs); 1068eda6500aSJiri Pirko if (err) { 1069eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1070eda6500aSJiri Pirko goto err_sdqs_init; 1071eda6500aSJiri Pirko } 1072eda6500aSJiri Pirko 1073eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1074eda6500aSJiri Pirko num_rdqs); 1075eda6500aSJiri Pirko if (err) { 1076eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1077eda6500aSJiri Pirko goto err_rdqs_init; 1078eda6500aSJiri Pirko } 1079eda6500aSJiri Pirko 1080eda6500aSJiri Pirko /* We have to poll in command interface until queues are initialized */ 1081eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = true; 1082eda6500aSJiri Pirko return 0; 1083eda6500aSJiri Pirko 1084eda6500aSJiri Pirko err_rdqs_init: 1085eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1086eda6500aSJiri Pirko err_sdqs_init: 1087eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1088eda6500aSJiri Pirko err_cqs_init: 1089eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1090eda6500aSJiri Pirko return err; 1091eda6500aSJiri Pirko } 1092eda6500aSJiri Pirko 1093eda6500aSJiri Pirko static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1094eda6500aSJiri Pirko { 1095eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = false; 1096eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1097eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1098eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1099eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1100eda6500aSJiri Pirko } 1101eda6500aSJiri Pirko 1102eda6500aSJiri Pirko static void 1103eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1104eda6500aSJiri Pirko char *mbox, int index, 1105eda6500aSJiri Pirko const struct mlxsw_swid_config *swid) 1106eda6500aSJiri Pirko { 1107eda6500aSJiri Pirko u8 mask = 0; 1108eda6500aSJiri Pirko 1109eda6500aSJiri Pirko if (swid->used_type) { 1110eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1111eda6500aSJiri Pirko mbox, index, swid->type); 1112eda6500aSJiri Pirko mask |= 1; 1113eda6500aSJiri Pirko } 1114eda6500aSJiri Pirko if (swid->used_properties) { 1115eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1116eda6500aSJiri Pirko mbox, index, swid->properties); 1117eda6500aSJiri Pirko mask |= 2; 1118eda6500aSJiri Pirko } 1119eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1120eda6500aSJiri Pirko } 1121eda6500aSJiri Pirko 1122c1a38311SJiri Pirko static int 1123e21d21caSArkadi Sharshevsky mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci, 1124e21d21caSArkadi Sharshevsky const struct mlxsw_config_profile *profile, 1125c1a38311SJiri Pirko struct mlxsw_res *res) 1126403547d3SNogah Frankel { 1127e21d21caSArkadi Sharshevsky u64 single_size, double_size, linear_size; 1128e21d21caSArkadi Sharshevsky int err; 1129403547d3SNogah Frankel 1130e21d21caSArkadi Sharshevsky err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile, 1131e21d21caSArkadi Sharshevsky &single_size, &double_size, 1132e21d21caSArkadi Sharshevsky &linear_size); 1133e21d21caSArkadi Sharshevsky if (err) 1134e21d21caSArkadi Sharshevsky return err; 1135403547d3SNogah Frankel 1136c1a38311SJiri Pirko MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size); 1137c1a38311SJiri Pirko MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size); 1138c1a38311SJiri Pirko MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size); 1139403547d3SNogah Frankel 1140403547d3SNogah Frankel return 0; 1141403547d3SNogah Frankel } 1142403547d3SNogah Frankel 1143eda6500aSJiri Pirko static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1144403547d3SNogah Frankel const struct mlxsw_config_profile *profile, 1145c1a38311SJiri Pirko struct mlxsw_res *res) 1146eda6500aSJiri Pirko { 1147eda6500aSJiri Pirko int i; 1148403547d3SNogah Frankel int err; 1149eda6500aSJiri Pirko 1150eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1151eda6500aSJiri Pirko 1152eda6500aSJiri Pirko if (profile->used_max_vepa_channels) { 1153eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1154eda6500aSJiri Pirko mbox, 1); 1155eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1156eda6500aSJiri Pirko mbox, profile->max_vepa_channels); 1157eda6500aSJiri Pirko } 1158eda6500aSJiri Pirko if (profile->used_max_mid) { 1159eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1160eda6500aSJiri Pirko mbox, 1); 1161eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_mid_set( 1162eda6500aSJiri Pirko mbox, profile->max_mid); 1163eda6500aSJiri Pirko } 1164eda6500aSJiri Pirko if (profile->used_max_pgt) { 1165eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1166eda6500aSJiri Pirko mbox, 1); 1167eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pgt_set( 1168eda6500aSJiri Pirko mbox, profile->max_pgt); 1169eda6500aSJiri Pirko } 1170eda6500aSJiri Pirko if (profile->used_max_system_port) { 1171eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1172eda6500aSJiri Pirko mbox, 1); 1173eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_system_port_set( 1174eda6500aSJiri Pirko mbox, profile->max_system_port); 1175eda6500aSJiri Pirko } 1176eda6500aSJiri Pirko if (profile->used_max_vlan_groups) { 1177eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1178eda6500aSJiri Pirko mbox, 1); 1179eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1180eda6500aSJiri Pirko mbox, profile->max_vlan_groups); 1181eda6500aSJiri Pirko } 1182eda6500aSJiri Pirko if (profile->used_max_regions) { 1183eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1184eda6500aSJiri Pirko mbox, 1); 1185eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_regions_set( 1186eda6500aSJiri Pirko mbox, profile->max_regions); 1187eda6500aSJiri Pirko } 1188eda6500aSJiri Pirko if (profile->used_flood_tables) { 1189eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1190eda6500aSJiri Pirko mbox, 1); 1191eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1192eda6500aSJiri Pirko mbox, profile->max_flood_tables); 1193eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1194eda6500aSJiri Pirko mbox, profile->max_vid_flood_tables); 119512fd35abSIdo Schimmel mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 119612fd35abSIdo Schimmel mbox, profile->max_fid_offset_flood_tables); 119712fd35abSIdo Schimmel mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 119812fd35abSIdo Schimmel mbox, profile->fid_offset_flood_table_size); 1199453b6a8dSIdo Schimmel mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1200453b6a8dSIdo Schimmel mbox, profile->max_fid_flood_tables); 1201453b6a8dSIdo Schimmel mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1202453b6a8dSIdo Schimmel mbox, profile->fid_flood_table_size); 1203eda6500aSJiri Pirko } 1204eda6500aSJiri Pirko if (profile->used_flood_mode) { 1205eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1206eda6500aSJiri Pirko mbox, 1); 1207eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_flood_mode_set( 1208eda6500aSJiri Pirko mbox, profile->flood_mode); 1209eda6500aSJiri Pirko } 1210eda6500aSJiri Pirko if (profile->used_max_ib_mc) { 1211eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1212eda6500aSJiri Pirko mbox, 1); 1213eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1214eda6500aSJiri Pirko mbox, profile->max_ib_mc); 1215eda6500aSJiri Pirko } 1216eda6500aSJiri Pirko if (profile->used_max_pkey) { 1217eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1218eda6500aSJiri Pirko mbox, 1); 1219eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pkey_set( 1220eda6500aSJiri Pirko mbox, profile->max_pkey); 1221eda6500aSJiri Pirko } 1222eda6500aSJiri Pirko if (profile->used_ar_sec) { 1223eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1224eda6500aSJiri Pirko mbox, 1); 1225eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_ar_sec_set( 1226eda6500aSJiri Pirko mbox, profile->ar_sec); 1227eda6500aSJiri Pirko } 1228eda6500aSJiri Pirko if (profile->used_adaptive_routing_group_cap) { 1229eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1230eda6500aSJiri Pirko mbox, 1); 1231eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1232eda6500aSJiri Pirko mbox, profile->adaptive_routing_group_cap); 1233eda6500aSJiri Pirko } 1234110d2d21SJiri Pirko if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) { 1235e21d21caSArkadi Sharshevsky err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res); 1236403547d3SNogah Frankel if (err) 1237403547d3SNogah Frankel return err; 1238403547d3SNogah Frankel 1239403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1); 1240403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox, 1241c1a38311SJiri Pirko MLXSW_RES_GET(res, KVD_LINEAR_SIZE)); 1242403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox, 1243403547d3SNogah Frankel 1); 1244403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox, 1245c1a38311SJiri Pirko MLXSW_RES_GET(res, KVD_SINGLE_SIZE)); 1246489107bdSJiri Pirko mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set( 1247489107bdSJiri Pirko mbox, 1); 1248403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox, 1249c1a38311SJiri Pirko MLXSW_RES_GET(res, KVD_DOUBLE_SIZE)); 1250489107bdSJiri Pirko } 1251dffd5661SJiri Pirko if (profile->used_kvh_xlt_cache_mode) { 1252dffd5661SJiri Pirko mlxsw_cmd_mbox_config_profile_set_kvh_xlt_cache_mode_set( 1253dffd5661SJiri Pirko mbox, 1); 1254dffd5661SJiri Pirko mlxsw_cmd_mbox_config_profile_kvh_xlt_cache_mode_set( 1255dffd5661SJiri Pirko mbox, profile->kvh_xlt_cache_mode); 1256dffd5661SJiri Pirko } 1257eda6500aSJiri Pirko 1258eda6500aSJiri Pirko for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1259eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1260eda6500aSJiri Pirko &profile->swid_config[i]); 1261eda6500aSJiri Pirko 12628404f6f2SJiri Pirko if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) { 12638404f6f2SJiri Pirko mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1); 12648404f6f2SJiri Pirko mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1); 12658404f6f2SJiri Pirko } 12668404f6f2SJiri Pirko 1267eda6500aSJiri Pirko return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1268eda6500aSJiri Pirko } 1269eda6500aSJiri Pirko 12702ea3f4c7SJiri Pirko static int mlxsw_pci_boardinfo_xm_process(struct mlxsw_pci *mlxsw_pci, 12712ea3f4c7SJiri Pirko struct mlxsw_bus_info *bus_info, 12722ea3f4c7SJiri Pirko char *mbox) 12732ea3f4c7SJiri Pirko { 12742ea3f4c7SJiri Pirko int count = mlxsw_cmd_mbox_boardinfo_xm_num_local_ports_get(mbox); 12752ea3f4c7SJiri Pirko int i; 12762ea3f4c7SJiri Pirko 12772ea3f4c7SJiri Pirko if (!mlxsw_cmd_mbox_boardinfo_xm_exists_get(mbox)) 12782ea3f4c7SJiri Pirko return 0; 12792ea3f4c7SJiri Pirko 12802ea3f4c7SJiri Pirko bus_info->xm_exists = true; 12812ea3f4c7SJiri Pirko 12822ea3f4c7SJiri Pirko if (count > MLXSW_BUS_INFO_XM_LOCAL_PORTS_MAX) { 12832ea3f4c7SJiri Pirko dev_err(&mlxsw_pci->pdev->dev, "Invalid number of XM local ports\n"); 12842ea3f4c7SJiri Pirko return -EINVAL; 12852ea3f4c7SJiri Pirko } 12862ea3f4c7SJiri Pirko bus_info->xm_local_ports_count = count; 12872ea3f4c7SJiri Pirko for (i = 0; i < count; i++) 12882ea3f4c7SJiri Pirko bus_info->xm_local_ports[i] = 12892ea3f4c7SJiri Pirko mlxsw_cmd_mbox_boardinfo_xm_local_port_entry_get(mbox, 12902ea3f4c7SJiri Pirko i); 12912ea3f4c7SJiri Pirko return 0; 12922ea3f4c7SJiri Pirko } 12932ea3f4c7SJiri Pirko 1294eda6500aSJiri Pirko static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1295eda6500aSJiri Pirko { 1296eda6500aSJiri Pirko struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1297eda6500aSJiri Pirko int err; 1298eda6500aSJiri Pirko 1299eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1300eda6500aSJiri Pirko err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1301eda6500aSJiri Pirko if (err) 1302eda6500aSJiri Pirko return err; 1303eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1304eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 13052ea3f4c7SJiri Pirko 13062ea3f4c7SJiri Pirko return mlxsw_pci_boardinfo_xm_process(mlxsw_pci, bus_info, mbox); 1307eda6500aSJiri Pirko } 1308eda6500aSJiri Pirko 1309eda6500aSJiri Pirko static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1310eda6500aSJiri Pirko u16 num_pages) 1311eda6500aSJiri Pirko { 1312eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 13133e2206daSJiri Pirko int nent = 0; 1314eda6500aSJiri Pirko int i; 1315eda6500aSJiri Pirko int err; 1316eda6500aSJiri Pirko 1317eda6500aSJiri Pirko mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1318eda6500aSJiri Pirko GFP_KERNEL); 1319eda6500aSJiri Pirko if (!mlxsw_pci->fw_area.items) 1320eda6500aSJiri Pirko return -ENOMEM; 13213e2206daSJiri Pirko mlxsw_pci->fw_area.count = num_pages; 1322eda6500aSJiri Pirko 1323eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1324eda6500aSJiri Pirko for (i = 0; i < num_pages; i++) { 1325eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1326eda6500aSJiri Pirko 1327eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_PAGE_SIZE; 1328bb5c64c8SChristophe JAILLET mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 1329eda6500aSJiri Pirko mem_item->size, 1330bb5c64c8SChristophe JAILLET &mem_item->mapaddr, GFP_KERNEL); 1331eda6500aSJiri Pirko if (!mem_item->buf) { 1332eda6500aSJiri Pirko err = -ENOMEM; 1333eda6500aSJiri Pirko goto err_alloc; 1334eda6500aSJiri Pirko } 13353e2206daSJiri Pirko mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 13363e2206daSJiri Pirko mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 13373e2206daSJiri Pirko if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 13383e2206daSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1339eda6500aSJiri Pirko if (err) 1340eda6500aSJiri Pirko goto err_cmd_map_fa; 13413e2206daSJiri Pirko nent = 0; 13423e2206daSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 13433e2206daSJiri Pirko } 13443e2206daSJiri Pirko } 13453e2206daSJiri Pirko 13463e2206daSJiri Pirko if (nent) { 13473e2206daSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 13483e2206daSJiri Pirko if (err) 13493e2206daSJiri Pirko goto err_cmd_map_fa; 13503e2206daSJiri Pirko } 1351eda6500aSJiri Pirko 1352eda6500aSJiri Pirko return 0; 1353eda6500aSJiri Pirko 1354eda6500aSJiri Pirko err_cmd_map_fa: 1355eda6500aSJiri Pirko err_alloc: 1356eda6500aSJiri Pirko for (i--; i >= 0; i--) { 1357eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1358eda6500aSJiri Pirko 1359bb5c64c8SChristophe JAILLET dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1360eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1361eda6500aSJiri Pirko } 1362eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1363eda6500aSJiri Pirko return err; 1364eda6500aSJiri Pirko } 1365eda6500aSJiri Pirko 1366eda6500aSJiri Pirko static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1367eda6500aSJiri Pirko { 1368eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 1369eda6500aSJiri Pirko int i; 1370eda6500aSJiri Pirko 1371eda6500aSJiri Pirko mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1372eda6500aSJiri Pirko 13733e2206daSJiri Pirko for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1374eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1375eda6500aSJiri Pirko 1376bb5c64c8SChristophe JAILLET dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1377eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1378eda6500aSJiri Pirko } 1379eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1380eda6500aSJiri Pirko } 1381eda6500aSJiri Pirko 1382eda6500aSJiri Pirko static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1383eda6500aSJiri Pirko { 1384eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_id; 1385eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1386eda6500aSJiri Pirko int i; 1387eda6500aSJiri Pirko 1388eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1389eda6500aSJiri Pirko q = mlxsw_pci_eq_get(mlxsw_pci, i); 1390eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 1391eda6500aSJiri Pirko } 1392eda6500aSJiri Pirko return IRQ_HANDLED; 1393eda6500aSJiri Pirko } 1394eda6500aSJiri Pirko 13951e81779aSIdo Schimmel static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 13961e81779aSIdo Schimmel struct mlxsw_pci_mem_item *mbox) 13971e81779aSIdo Schimmel { 13981e81779aSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 13991e81779aSIdo Schimmel int err = 0; 14001e81779aSIdo Schimmel 14011e81779aSIdo Schimmel mbox->size = MLXSW_CMD_MBOX_SIZE; 1402bb5c64c8SChristophe JAILLET mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, 1403bb5c64c8SChristophe JAILLET &mbox->mapaddr, GFP_KERNEL); 14041e81779aSIdo Schimmel if (!mbox->buf) { 14051e81779aSIdo Schimmel dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 14061e81779aSIdo Schimmel err = -ENOMEM; 14071e81779aSIdo Schimmel } 14081e81779aSIdo Schimmel 14091e81779aSIdo Schimmel return err; 14101e81779aSIdo Schimmel } 14111e81779aSIdo Schimmel 14121e81779aSIdo Schimmel static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 14131e81779aSIdo Schimmel struct mlxsw_pci_mem_item *mbox) 14141e81779aSIdo Schimmel { 14151e81779aSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 14161e81779aSIdo Schimmel 1417bb5c64c8SChristophe JAILLET dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 14181e81779aSIdo Schimmel mbox->mapaddr); 14191e81779aSIdo Schimmel } 14201e81779aSIdo Schimmel 14216002059dSIdo Schimmel static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, 14226002059dSIdo Schimmel const struct pci_device_id *id, 14236002059dSIdo Schimmel u32 *p_sys_status) 1424f3a52c61SJiri Pirko { 1425f3a52c61SJiri Pirko unsigned long end; 14266002059dSIdo Schimmel u32 val; 1427f3a52c61SJiri Pirko 14286002059dSIdo Schimmel /* We must wait for the HW to become responsive. */ 1429f3a52c61SJiri Pirko msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS); 1430f3a52c61SJiri Pirko 1431f3a52c61SJiri Pirko end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1432f3a52c61SJiri Pirko do { 14336002059dSIdo Schimmel val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1434f3a52c61SJiri Pirko if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 143567c14cc9SNir Dotan return 0; 1436f3a52c61SJiri Pirko cond_resched(); 1437f3a52c61SJiri Pirko } while (time_before(jiffies, end)); 14386002059dSIdo Schimmel 14396002059dSIdo Schimmel *p_sys_status = val & MLXSW_PCI_FW_READY_MASK; 14406002059dSIdo Schimmel 144167c14cc9SNir Dotan return -EBUSY; 1442f3a52c61SJiri Pirko } 1443f3a52c61SJiri Pirko 14446002059dSIdo Schimmel static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, 14456002059dSIdo Schimmel const struct pci_device_id *id) 14466002059dSIdo Schimmel { 14476002059dSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 14486002059dSIdo Schimmel char mrsr_pl[MLXSW_REG_MRSR_LEN]; 14496002059dSIdo Schimmel u32 sys_status; 14506002059dSIdo Schimmel int err; 14516002059dSIdo Schimmel 14526002059dSIdo Schimmel err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 14536002059dSIdo Schimmel if (err) { 14546002059dSIdo Schimmel dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n", 14556002059dSIdo Schimmel sys_status); 14566002059dSIdo Schimmel return err; 14576002059dSIdo Schimmel } 14586002059dSIdo Schimmel 14596002059dSIdo Schimmel mlxsw_reg_mrsr_pack(mrsr_pl); 14606002059dSIdo Schimmel err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 14616002059dSIdo Schimmel if (err) 14626002059dSIdo Schimmel return err; 14636002059dSIdo Schimmel 14646002059dSIdo Schimmel err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 14656002059dSIdo Schimmel if (err) { 14666002059dSIdo Schimmel dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n", 14676002059dSIdo Schimmel sys_status); 14686002059dSIdo Schimmel return err; 14696002059dSIdo Schimmel } 14706002059dSIdo Schimmel 14716002059dSIdo Schimmel return 0; 14726002059dSIdo Schimmel } 14736002059dSIdo Schimmel 1474f3a52c61SJiri Pirko static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1475f3a52c61SJiri Pirko { 1476f3a52c61SJiri Pirko int err; 1477f3a52c61SJiri Pirko 1478f3a52c61SJiri Pirko err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX); 1479f3a52c61SJiri Pirko if (err < 0) 1480f3a52c61SJiri Pirko dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n"); 1481f3a52c61SJiri Pirko return err; 1482f3a52c61SJiri Pirko } 1483f3a52c61SJiri Pirko 1484f3a52c61SJiri Pirko static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1485f3a52c61SJiri Pirko { 1486f3a52c61SJiri Pirko pci_free_irq_vectors(mlxsw_pci->pdev); 1487f3a52c61SJiri Pirko } 1488f3a52c61SJiri Pirko 1489eda6500aSJiri Pirko static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 149057d316baSNogah Frankel const struct mlxsw_config_profile *profile, 1491c1a38311SJiri Pirko struct mlxsw_res *res) 1492eda6500aSJiri Pirko { 1493eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1494eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1495eda6500aSJiri Pirko char *mbox; 1496eda6500aSJiri Pirko u16 num_pages; 1497eda6500aSJiri Pirko int err; 1498eda6500aSJiri Pirko 1499eda6500aSJiri Pirko mlxsw_pci->core = mlxsw_core; 1500eda6500aSJiri Pirko 1501eda6500aSJiri Pirko mbox = mlxsw_cmd_mbox_alloc(); 1502eda6500aSJiri Pirko if (!mbox) 1503eda6500aSJiri Pirko return -ENOMEM; 15041e81779aSIdo Schimmel 1505f3a52c61SJiri Pirko err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id); 1506f3a52c61SJiri Pirko if (err) 1507f3a52c61SJiri Pirko goto err_sw_reset; 1508f3a52c61SJiri Pirko 1509f3a52c61SJiri Pirko err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); 1510f3a52c61SJiri Pirko if (err < 0) { 1511f3a52c61SJiri Pirko dev_err(&pdev->dev, "MSI-X init failed\n"); 1512f3a52c61SJiri Pirko goto err_alloc_irq; 1513f3a52c61SJiri Pirko } 1514f3a52c61SJiri Pirko 1515eda6500aSJiri Pirko err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1516eda6500aSJiri Pirko if (err) 1517eda6500aSJiri Pirko goto err_query_fw; 1518eda6500aSJiri Pirko 1519eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.major = 1520eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1521eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.minor = 1522eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1523eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.subminor = 1524eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1525eda6500aSJiri Pirko 1526eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1527eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1528eda6500aSJiri Pirko err = -EINVAL; 1529eda6500aSJiri Pirko goto err_iface_rev; 1530eda6500aSJiri Pirko } 1531eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1532eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1533eda6500aSJiri Pirko err = -EINVAL; 1534eda6500aSJiri Pirko goto err_doorbell_page_bar; 1535eda6500aSJiri Pirko } 1536eda6500aSJiri Pirko 1537eda6500aSJiri Pirko mlxsw_pci->doorbell_offset = 1538eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1539eda6500aSJiri Pirko 15408289169dSShalom Toledo if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) { 15418289169dSShalom Toledo dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n"); 15428289169dSShalom Toledo err = -EINVAL; 15438289169dSShalom Toledo goto err_fr_rn_clk_bar; 15448289169dSShalom Toledo } 15458289169dSShalom Toledo 15468289169dSShalom Toledo mlxsw_pci->free_running_clock_offset = 15478289169dSShalom Toledo mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox); 15488289169dSShalom Toledo 1549eda6500aSJiri Pirko num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1550eda6500aSJiri Pirko err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1551eda6500aSJiri Pirko if (err) 1552eda6500aSJiri Pirko goto err_fw_area_init; 1553eda6500aSJiri Pirko 1554eda6500aSJiri Pirko err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1555eda6500aSJiri Pirko if (err) 1556eda6500aSJiri Pirko goto err_boardinfo; 1557eda6500aSJiri Pirko 1558e5ba7803SVadim Pasternak err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 155957d316baSNogah Frankel if (err) 156057d316baSNogah Frankel goto err_query_resources; 156157d316baSNogah Frankel 15628404f6f2SJiri Pirko if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) && 15638404f6f2SJiri Pirko MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) 15648404f6f2SJiri Pirko mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2; 15658404f6f2SJiri Pirko else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) && 15668404f6f2SJiri Pirko MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) 15678404f6f2SJiri Pirko mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1; 15688404f6f2SJiri Pirko else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) && 15698404f6f2SJiri Pirko MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || 15708404f6f2SJiri Pirko !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) { 15718404f6f2SJiri Pirko mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0; 15728404f6f2SJiri Pirko } else { 15738404f6f2SJiri Pirko dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n"); 15748404f6f2SJiri Pirko goto err_cqe_v_check; 15758404f6f2SJiri Pirko } 15768404f6f2SJiri Pirko 1577c1a38311SJiri Pirko err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res); 1578eda6500aSJiri Pirko if (err) 1579eda6500aSJiri Pirko goto err_config_profile; 1580eda6500aSJiri Pirko 1581eda6500aSJiri Pirko err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1582eda6500aSJiri Pirko if (err) 1583eda6500aSJiri Pirko goto err_aqs_init; 1584eda6500aSJiri Pirko 15853680b1f6SChristoph Hellwig err = request_irq(pci_irq_vector(pdev, 0), 1586eda6500aSJiri Pirko mlxsw_pci_eq_irq_handler, 0, 15871d20d23cSJiri Pirko mlxsw_pci->bus_info.device_kind, mlxsw_pci); 1588eda6500aSJiri Pirko if (err) { 1589eda6500aSJiri Pirko dev_err(&pdev->dev, "IRQ request failed\n"); 1590eda6500aSJiri Pirko goto err_request_eq_irq; 1591eda6500aSJiri Pirko } 1592eda6500aSJiri Pirko 1593eda6500aSJiri Pirko goto mbox_put; 1594eda6500aSJiri Pirko 1595eda6500aSJiri Pirko err_request_eq_irq: 1596eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1597eda6500aSJiri Pirko err_aqs_init: 1598eda6500aSJiri Pirko err_config_profile: 15998404f6f2SJiri Pirko err_cqe_v_check: 160057d316baSNogah Frankel err_query_resources: 1601eda6500aSJiri Pirko err_boardinfo: 1602eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1603eda6500aSJiri Pirko err_fw_area_init: 16048289169dSShalom Toledo err_fr_rn_clk_bar: 1605eda6500aSJiri Pirko err_doorbell_page_bar: 1606eda6500aSJiri Pirko err_iface_rev: 1607eda6500aSJiri Pirko err_query_fw: 1608f3a52c61SJiri Pirko mlxsw_pci_free_irq_vectors(mlxsw_pci); 1609f3a52c61SJiri Pirko err_alloc_irq: 1610f3a52c61SJiri Pirko err_sw_reset: 1611eda6500aSJiri Pirko mbox_put: 1612eda6500aSJiri Pirko mlxsw_cmd_mbox_free(mbox); 1613eda6500aSJiri Pirko return err; 1614eda6500aSJiri Pirko } 1615eda6500aSJiri Pirko 1616eda6500aSJiri Pirko static void mlxsw_pci_fini(void *bus_priv) 1617eda6500aSJiri Pirko { 1618eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1619eda6500aSJiri Pirko 16203680b1f6SChristoph Hellwig free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 1621eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1622eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1623f3a52c61SJiri Pirko mlxsw_pci_free_irq_vectors(mlxsw_pci); 1624eda6500aSJiri Pirko } 1625eda6500aSJiri Pirko 1626eda6500aSJiri Pirko static struct mlxsw_pci_queue * 1627eda6500aSJiri Pirko mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1628eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1629eda6500aSJiri Pirko { 16306aaee55cSPetr Machata u8 ctl_sdq_count = mlxsw_pci_sdq_count(mlxsw_pci) - 1; 16316aaee55cSPetr Machata u8 sdqn; 16326aaee55cSPetr Machata 16336aaee55cSPetr Machata if (tx_info->is_emad) { 16346aaee55cSPetr Machata sdqn = MLXSW_PCI_SDQ_EMAD_INDEX; 16356aaee55cSPetr Machata } else { 16366aaee55cSPetr Machata BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0); 16376aaee55cSPetr Machata sdqn = 1 + (tx_info->local_port % ctl_sdq_count); 16386aaee55cSPetr Machata } 1639eda6500aSJiri Pirko 1640eda6500aSJiri Pirko return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1641eda6500aSJiri Pirko } 1642eda6500aSJiri Pirko 1643d003462aSIdo Schimmel static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1644d003462aSIdo Schimmel const struct mlxsw_tx_info *tx_info) 1645d003462aSIdo Schimmel { 1646d003462aSIdo Schimmel struct mlxsw_pci *mlxsw_pci = bus_priv; 1647d003462aSIdo Schimmel struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1648d003462aSIdo Schimmel 1649d003462aSIdo Schimmel return !mlxsw_pci_queue_elem_info_producer_get(q); 1650d003462aSIdo Schimmel } 1651d003462aSIdo Schimmel 1652eda6500aSJiri Pirko static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1653eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1654eda6500aSJiri Pirko { 1655eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1656eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1657eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 1658eda6500aSJiri Pirko char *wqe; 1659eda6500aSJiri Pirko int i; 1660eda6500aSJiri Pirko int err; 1661eda6500aSJiri Pirko 1662eda6500aSJiri Pirko if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1663eda6500aSJiri Pirko err = skb_linearize(skb); 1664eda6500aSJiri Pirko if (err) 1665eda6500aSJiri Pirko return err; 1666eda6500aSJiri Pirko } 1667eda6500aSJiri Pirko 1668eda6500aSJiri Pirko q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1669eda6500aSJiri Pirko spin_lock_bh(&q->lock); 1670eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1671eda6500aSJiri Pirko if (!elem_info) { 1672eda6500aSJiri Pirko /* queue is full */ 1673eda6500aSJiri Pirko err = -EAGAIN; 1674eda6500aSJiri Pirko goto unlock; 1675eda6500aSJiri Pirko } 16760714256cSPetr Machata mlxsw_skb_cb(skb)->tx_info = *tx_info; 1677eda6500aSJiri Pirko elem_info->u.sdq.skb = skb; 1678eda6500aSJiri Pirko 1679eda6500aSJiri Pirko wqe = elem_info->elem; 1680eda6500aSJiri Pirko mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1681eda6500aSJiri Pirko mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1682eda6500aSJiri Pirko mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1683eda6500aSJiri Pirko 1684eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1685eda6500aSJiri Pirko skb_headlen(skb), DMA_TO_DEVICE); 1686eda6500aSJiri Pirko if (err) 1687eda6500aSJiri Pirko goto unlock; 1688eda6500aSJiri Pirko 1689eda6500aSJiri Pirko for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1690eda6500aSJiri Pirko const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1691eda6500aSJiri Pirko 1692eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1693eda6500aSJiri Pirko skb_frag_address(frag), 1694eda6500aSJiri Pirko skb_frag_size(frag), 1695eda6500aSJiri Pirko DMA_TO_DEVICE); 1696eda6500aSJiri Pirko if (err) 1697eda6500aSJiri Pirko goto unmap_frags; 1698eda6500aSJiri Pirko } 1699eda6500aSJiri Pirko 17000714256cSPetr Machata if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 17010714256cSPetr Machata skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 17020714256cSPetr Machata 1703eda6500aSJiri Pirko /* Set unused sq entries byte count to zero. */ 1704eda6500aSJiri Pirko for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1705eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1706eda6500aSJiri Pirko 1707eda6500aSJiri Pirko /* Everything is set up, ring producer doorbell to get HW going */ 1708eda6500aSJiri Pirko q->producer_counter++; 1709eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1710eda6500aSJiri Pirko 1711eda6500aSJiri Pirko goto unlock; 1712eda6500aSJiri Pirko 1713eda6500aSJiri Pirko unmap_frags: 1714eda6500aSJiri Pirko for (; i >= 0; i--) 1715eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1716eda6500aSJiri Pirko unlock: 1717eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 1718eda6500aSJiri Pirko return err; 1719eda6500aSJiri Pirko } 1720eda6500aSJiri Pirko 1721eda6500aSJiri Pirko static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1722eda6500aSJiri Pirko u32 in_mod, bool out_mbox_direct, 1723eda6500aSJiri Pirko char *in_mbox, size_t in_mbox_size, 1724eda6500aSJiri Pirko char *out_mbox, size_t out_mbox_size, 1725eda6500aSJiri Pirko u8 *p_status) 1726eda6500aSJiri Pirko { 1727eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1728830a8b1bSShalom Toledo dma_addr_t in_mapaddr = 0, out_mapaddr = 0; 1729eda6500aSJiri Pirko bool evreq = mlxsw_pci->cmd.nopoll; 1730eda6500aSJiri Pirko unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1731eda6500aSJiri Pirko bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1732eda6500aSJiri Pirko int err; 1733eda6500aSJiri Pirko 1734eda6500aSJiri Pirko *p_status = MLXSW_CMD_STATUS_OK; 1735eda6500aSJiri Pirko 1736eda6500aSJiri Pirko err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1737eda6500aSJiri Pirko if (err) 1738eda6500aSJiri Pirko return err; 1739eda6500aSJiri Pirko 1740830a8b1bSShalom Toledo if (in_mbox) { 17411e81779aSIdo Schimmel memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1742830a8b1bSShalom Toledo in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 1743830a8b1bSShalom Toledo } 1744bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 1745bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 1746eda6500aSJiri Pirko 1747830a8b1bSShalom Toledo if (out_mbox) 1748830a8b1bSShalom Toledo out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1749bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 1750bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 1751eda6500aSJiri Pirko 1752eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1753eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1754eda6500aSJiri Pirko 1755eda6500aSJiri Pirko *p_wait_done = false; 1756eda6500aSJiri Pirko 1757eda6500aSJiri Pirko wmb(); /* all needs to be written before we write control register */ 1758eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1759eda6500aSJiri Pirko MLXSW_PCI_CIR_CTRL_GO_BIT | 1760eda6500aSJiri Pirko (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1761eda6500aSJiri Pirko (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1762eda6500aSJiri Pirko opcode); 1763eda6500aSJiri Pirko 1764eda6500aSJiri Pirko if (!evreq) { 1765eda6500aSJiri Pirko unsigned long end; 1766eda6500aSJiri Pirko 1767eda6500aSJiri Pirko end = jiffies + timeout; 1768eda6500aSJiri Pirko do { 1769eda6500aSJiri Pirko u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1770eda6500aSJiri Pirko 1771eda6500aSJiri Pirko if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1772eda6500aSJiri Pirko *p_wait_done = true; 1773eda6500aSJiri Pirko *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1774eda6500aSJiri Pirko break; 1775eda6500aSJiri Pirko } 1776eda6500aSJiri Pirko cond_resched(); 1777eda6500aSJiri Pirko } while (time_before(jiffies, end)); 1778eda6500aSJiri Pirko } else { 1779eda6500aSJiri Pirko wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1780eda6500aSJiri Pirko *p_status = mlxsw_pci->cmd.comp.status; 1781eda6500aSJiri Pirko } 1782eda6500aSJiri Pirko 1783eda6500aSJiri Pirko err = 0; 1784eda6500aSJiri Pirko if (*p_wait_done) { 1785eda6500aSJiri Pirko if (*p_status) 1786eda6500aSJiri Pirko err = -EIO; 1787eda6500aSJiri Pirko } else { 1788eda6500aSJiri Pirko err = -ETIMEDOUT; 1789eda6500aSJiri Pirko } 1790eda6500aSJiri Pirko 1791eda6500aSJiri Pirko if (!err && out_mbox && out_mbox_direct) { 17921e81779aSIdo Schimmel /* Some commands don't use output param as address to mailbox 1793eda6500aSJiri Pirko * but they store output directly into registers. In that case, 1794eda6500aSJiri Pirko * copy registers into mbox buffer. 1795eda6500aSJiri Pirko */ 1796eda6500aSJiri Pirko __be32 tmp; 1797eda6500aSJiri Pirko 1798eda6500aSJiri Pirko if (!evreq) { 1799eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1800eda6500aSJiri Pirko CIR_OUT_PARAM_HI)); 1801eda6500aSJiri Pirko memcpy(out_mbox, &tmp, sizeof(tmp)); 1802eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1803eda6500aSJiri Pirko CIR_OUT_PARAM_LO)); 1804eda6500aSJiri Pirko memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1805eda6500aSJiri Pirko } 1806d9324f68SOr Gerlitz } else if (!err && out_mbox) { 18071e81779aSIdo Schimmel memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1808d9324f68SOr Gerlitz } 1809eda6500aSJiri Pirko 1810eda6500aSJiri Pirko mutex_unlock(&mlxsw_pci->cmd.lock); 1811eda6500aSJiri Pirko 1812eda6500aSJiri Pirko return err; 1813eda6500aSJiri Pirko } 1814eda6500aSJiri Pirko 18158289169dSShalom Toledo static u32 mlxsw_pci_read_frc_h(void *bus_priv) 18168289169dSShalom Toledo { 18178289169dSShalom Toledo struct mlxsw_pci *mlxsw_pci = bus_priv; 18188289169dSShalom Toledo u64 frc_offset; 18198289169dSShalom Toledo 18208289169dSShalom Toledo frc_offset = mlxsw_pci->free_running_clock_offset; 18218289169dSShalom Toledo return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset)); 18228289169dSShalom Toledo } 18238289169dSShalom Toledo 18248289169dSShalom Toledo static u32 mlxsw_pci_read_frc_l(void *bus_priv) 18258289169dSShalom Toledo { 18268289169dSShalom Toledo struct mlxsw_pci *mlxsw_pci = bus_priv; 18278289169dSShalom Toledo u64 frc_offset; 18288289169dSShalom Toledo 18298289169dSShalom Toledo frc_offset = mlxsw_pci->free_running_clock_offset; 18308289169dSShalom Toledo return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset)); 18318289169dSShalom Toledo } 18328289169dSShalom Toledo 183354a2e8d4SArkadi Sharshevsky static const struct mlxsw_bus mlxsw_pci_bus = { 183454a2e8d4SArkadi Sharshevsky .kind = "pci", 183554a2e8d4SArkadi Sharshevsky .init = mlxsw_pci_init, 183654a2e8d4SArkadi Sharshevsky .fini = mlxsw_pci_fini, 183754a2e8d4SArkadi Sharshevsky .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 183854a2e8d4SArkadi Sharshevsky .skb_transmit = mlxsw_pci_skb_transmit, 183954a2e8d4SArkadi Sharshevsky .cmd_exec = mlxsw_pci_cmd_exec, 18408289169dSShalom Toledo .read_frc_h = mlxsw_pci_read_frc_h, 18418289169dSShalom Toledo .read_frc_l = mlxsw_pci_read_frc_l, 1842f3a52c61SJiri Pirko .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, 184354a2e8d4SArkadi Sharshevsky }; 184454a2e8d4SArkadi Sharshevsky 1845c4317b11SIdo Schimmel static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci) 1846c4317b11SIdo Schimmel { 1847c4317b11SIdo Schimmel int err; 1848c4317b11SIdo Schimmel 1849c4317b11SIdo Schimmel mutex_init(&mlxsw_pci->cmd.lock); 1850c4317b11SIdo Schimmel init_waitqueue_head(&mlxsw_pci->cmd.wait); 1851c4317b11SIdo Schimmel 1852c4317b11SIdo Schimmel err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1853c4317b11SIdo Schimmel if (err) 1854c4317b11SIdo Schimmel goto err_in_mbox_alloc; 1855c4317b11SIdo Schimmel 1856c4317b11SIdo Schimmel err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1857c4317b11SIdo Schimmel if (err) 1858c4317b11SIdo Schimmel goto err_out_mbox_alloc; 1859c4317b11SIdo Schimmel 1860c4317b11SIdo Schimmel return 0; 1861c4317b11SIdo Schimmel 1862c4317b11SIdo Schimmel err_out_mbox_alloc: 1863c4317b11SIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1864c4317b11SIdo Schimmel err_in_mbox_alloc: 1865c4317b11SIdo Schimmel mutex_destroy(&mlxsw_pci->cmd.lock); 1866c4317b11SIdo Schimmel return err; 1867c4317b11SIdo Schimmel } 1868c4317b11SIdo Schimmel 1869c4317b11SIdo Schimmel static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci) 1870c4317b11SIdo Schimmel { 1871c4317b11SIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 1872c4317b11SIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1873c4317b11SIdo Schimmel mutex_destroy(&mlxsw_pci->cmd.lock); 1874c4317b11SIdo Schimmel } 1875c4317b11SIdo Schimmel 1876eda6500aSJiri Pirko static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1877eda6500aSJiri Pirko { 18781d20d23cSJiri Pirko const char *driver_name = pdev->driver->name; 1879eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci; 1880eda6500aSJiri Pirko int err; 1881eda6500aSJiri Pirko 1882eda6500aSJiri Pirko mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1883eda6500aSJiri Pirko if (!mlxsw_pci) 1884eda6500aSJiri Pirko return -ENOMEM; 1885eda6500aSJiri Pirko 1886eda6500aSJiri Pirko err = pci_enable_device(pdev); 1887eda6500aSJiri Pirko if (err) { 1888eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_enable_device failed\n"); 1889eda6500aSJiri Pirko goto err_pci_enable_device; 1890eda6500aSJiri Pirko } 1891eda6500aSJiri Pirko 18921d20d23cSJiri Pirko err = pci_request_regions(pdev, driver_name); 1893eda6500aSJiri Pirko if (err) { 1894eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_request_regions failed\n"); 1895eda6500aSJiri Pirko goto err_pci_request_regions; 1896eda6500aSJiri Pirko } 1897eda6500aSJiri Pirko 1898bb5c64c8SChristophe JAILLET err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1899eda6500aSJiri Pirko if (err) { 1900bb5c64c8SChristophe JAILLET err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1901eda6500aSJiri Pirko if (err) { 1902bb5c64c8SChristophe JAILLET dev_err(&pdev->dev, "dma_set_mask failed\n"); 1903eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1904eda6500aSJiri Pirko } 1905eda6500aSJiri Pirko } 1906eda6500aSJiri Pirko 1907eda6500aSJiri Pirko if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1908eda6500aSJiri Pirko dev_err(&pdev->dev, "invalid PCI region size\n"); 1909eda6500aSJiri Pirko err = -EINVAL; 1910eda6500aSJiri Pirko goto err_pci_resource_len_check; 1911eda6500aSJiri Pirko } 1912eda6500aSJiri Pirko 1913eda6500aSJiri Pirko mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1914eda6500aSJiri Pirko pci_resource_len(pdev, 0)); 1915eda6500aSJiri Pirko if (!mlxsw_pci->hw_addr) { 1916eda6500aSJiri Pirko dev_err(&pdev->dev, "ioremap failed\n"); 1917eda6500aSJiri Pirko err = -EIO; 1918eda6500aSJiri Pirko goto err_ioremap; 1919eda6500aSJiri Pirko } 1920eda6500aSJiri Pirko pci_set_master(pdev); 1921eda6500aSJiri Pirko 1922eda6500aSJiri Pirko mlxsw_pci->pdev = pdev; 1923eda6500aSJiri Pirko pci_set_drvdata(pdev, mlxsw_pci); 1924eda6500aSJiri Pirko 1925c4317b11SIdo Schimmel err = mlxsw_pci_cmd_init(mlxsw_pci); 1926c4317b11SIdo Schimmel if (err) 1927c4317b11SIdo Schimmel goto err_pci_cmd_init; 1928c4317b11SIdo Schimmel 19291d20d23cSJiri Pirko mlxsw_pci->bus_info.device_kind = driver_name; 1930eda6500aSJiri Pirko mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1931eda6500aSJiri Pirko mlxsw_pci->bus_info.dev = &pdev->dev; 19328289169dSShalom Toledo mlxsw_pci->bus_info.read_frc_capable = true; 193354a2e8d4SArkadi Sharshevsky mlxsw_pci->id = id; 1934eda6500aSJiri Pirko 1935eda6500aSJiri Pirko err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 193624cc68adSArkadi Sharshevsky &mlxsw_pci_bus, mlxsw_pci, false, 19375bcfb6a4SJiri Pirko NULL, NULL); 193803bffcadSShalom Toledo if (err) { 1939eda6500aSJiri Pirko dev_err(&pdev->dev, "cannot register bus device\n"); 1940eda6500aSJiri Pirko goto err_bus_device_register; 1941eda6500aSJiri Pirko } 1942eda6500aSJiri Pirko 1943eda6500aSJiri Pirko return 0; 1944eda6500aSJiri Pirko 1945eda6500aSJiri Pirko err_bus_device_register: 1946c4317b11SIdo Schimmel mlxsw_pci_cmd_fini(mlxsw_pci); 1947c4317b11SIdo Schimmel err_pci_cmd_init: 1948eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1949eda6500aSJiri Pirko err_ioremap: 1950eda6500aSJiri Pirko err_pci_resource_len_check: 1951eda6500aSJiri Pirko err_pci_set_dma_mask: 1952eda6500aSJiri Pirko pci_release_regions(pdev); 1953eda6500aSJiri Pirko err_pci_request_regions: 1954eda6500aSJiri Pirko pci_disable_device(pdev); 1955eda6500aSJiri Pirko err_pci_enable_device: 1956eda6500aSJiri Pirko kfree(mlxsw_pci); 1957eda6500aSJiri Pirko return err; 1958eda6500aSJiri Pirko } 1959eda6500aSJiri Pirko 1960eda6500aSJiri Pirko static void mlxsw_pci_remove(struct pci_dev *pdev) 1961eda6500aSJiri Pirko { 1962eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1963eda6500aSJiri Pirko 196424cc68adSArkadi Sharshevsky mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 1965c4317b11SIdo Schimmel mlxsw_pci_cmd_fini(mlxsw_pci); 1966eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1967eda6500aSJiri Pirko pci_release_regions(mlxsw_pci->pdev); 1968eda6500aSJiri Pirko pci_disable_device(mlxsw_pci->pdev); 1969eda6500aSJiri Pirko kfree(mlxsw_pci); 1970eda6500aSJiri Pirko } 1971eda6500aSJiri Pirko 19721d20d23cSJiri Pirko int mlxsw_pci_driver_register(struct pci_driver *pci_driver) 19731d20d23cSJiri Pirko { 19741d20d23cSJiri Pirko pci_driver->probe = mlxsw_pci_probe; 19751d20d23cSJiri Pirko pci_driver->remove = mlxsw_pci_remove; 19761d20d23cSJiri Pirko return pci_register_driver(pci_driver); 19771d20d23cSJiri Pirko } 19781d20d23cSJiri Pirko EXPORT_SYMBOL(mlxsw_pci_driver_register); 19791d20d23cSJiri Pirko 19801d20d23cSJiri Pirko void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver) 19811d20d23cSJiri Pirko { 19821d20d23cSJiri Pirko pci_unregister_driver(pci_driver); 19831d20d23cSJiri Pirko } 19841d20d23cSJiri Pirko EXPORT_SYMBOL(mlxsw_pci_driver_unregister); 1985eda6500aSJiri Pirko 1986eda6500aSJiri Pirko static int __init mlxsw_pci_module_init(void) 1987eda6500aSJiri Pirko { 1988eda6500aSJiri Pirko return 0; 1989eda6500aSJiri Pirko } 1990eda6500aSJiri Pirko 1991eda6500aSJiri Pirko static void __exit mlxsw_pci_module_exit(void) 1992eda6500aSJiri Pirko { 1993eda6500aSJiri Pirko } 1994eda6500aSJiri Pirko 1995eda6500aSJiri Pirko module_init(mlxsw_pci_module_init); 1996eda6500aSJiri Pirko module_exit(mlxsw_pci_module_exit); 1997eda6500aSJiri Pirko 1998eda6500aSJiri Pirko MODULE_LICENSE("Dual BSD/GPL"); 1999eda6500aSJiri Pirko MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 2000eda6500aSJiri Pirko MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 2001