1eda6500aSJiri Pirko /* 2eda6500aSJiri Pirko * drivers/net/ethernet/mellanox/mlxsw/pci.c 3eda6500aSJiri Pirko * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4eda6500aSJiri Pirko * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5eda6500aSJiri Pirko * 6eda6500aSJiri Pirko * Redistribution and use in source and binary forms, with or without 7eda6500aSJiri Pirko * modification, are permitted provided that the following conditions are met: 8eda6500aSJiri Pirko * 9eda6500aSJiri Pirko * 1. Redistributions of source code must retain the above copyright 10eda6500aSJiri Pirko * notice, this list of conditions and the following disclaimer. 11eda6500aSJiri Pirko * 2. Redistributions in binary form must reproduce the above copyright 12eda6500aSJiri Pirko * notice, this list of conditions and the following disclaimer in the 13eda6500aSJiri Pirko * documentation and/or other materials provided with the distribution. 14eda6500aSJiri Pirko * 3. Neither the names of the copyright holders nor the names of its 15eda6500aSJiri Pirko * contributors may be used to endorse or promote products derived from 16eda6500aSJiri Pirko * this software without specific prior written permission. 17eda6500aSJiri Pirko * 18eda6500aSJiri Pirko * Alternatively, this software may be distributed under the terms of the 19eda6500aSJiri Pirko * GNU General Public License ("GPL") version 2 as published by the Free 20eda6500aSJiri Pirko * Software Foundation. 21eda6500aSJiri Pirko * 22eda6500aSJiri Pirko * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23eda6500aSJiri Pirko * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24eda6500aSJiri Pirko * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25eda6500aSJiri Pirko * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26eda6500aSJiri Pirko * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27eda6500aSJiri Pirko * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28eda6500aSJiri Pirko * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29eda6500aSJiri Pirko * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30eda6500aSJiri Pirko * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31eda6500aSJiri Pirko * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32eda6500aSJiri Pirko * POSSIBILITY OF SUCH DAMAGE. 33eda6500aSJiri Pirko */ 34eda6500aSJiri Pirko 35eda6500aSJiri Pirko #include <linux/kernel.h> 36eda6500aSJiri Pirko #include <linux/module.h> 37eda6500aSJiri Pirko #include <linux/export.h> 38eda6500aSJiri Pirko #include <linux/err.h> 39eda6500aSJiri Pirko #include <linux/device.h> 40eda6500aSJiri Pirko #include <linux/pci.h> 41eda6500aSJiri Pirko #include <linux/interrupt.h> 42eda6500aSJiri Pirko #include <linux/wait.h> 43eda6500aSJiri Pirko #include <linux/types.h> 44eda6500aSJiri Pirko #include <linux/skbuff.h> 45eda6500aSJiri Pirko #include <linux/if_vlan.h> 46eda6500aSJiri Pirko #include <linux/log2.h> 47eda6500aSJiri Pirko #include <linux/debugfs.h> 48eda6500aSJiri Pirko #include <linux/seq_file.h> 49eda6500aSJiri Pirko 50eda6500aSJiri Pirko #include "pci.h" 51eda6500aSJiri Pirko #include "core.h" 52eda6500aSJiri Pirko #include "cmd.h" 53eda6500aSJiri Pirko #include "port.h" 54eda6500aSJiri Pirko 55eda6500aSJiri Pirko static const char mlxsw_pci_driver_name[] = "mlxsw_pci"; 56eda6500aSJiri Pirko 57eda6500aSJiri Pirko static const struct pci_device_id mlxsw_pci_id_table[] = { 5831557f0fSJiri Pirko {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0}, 59eda6500aSJiri Pirko {0, } 60eda6500aSJiri Pirko }; 61eda6500aSJiri Pirko 62eda6500aSJiri Pirko static struct dentry *mlxsw_pci_dbg_root; 63eda6500aSJiri Pirko 64eda6500aSJiri Pirko static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id) 65eda6500aSJiri Pirko { 66eda6500aSJiri Pirko switch (id->device) { 6731557f0fSJiri Pirko case PCI_DEVICE_ID_MELLANOX_SWITCHX2: 6831557f0fSJiri Pirko return MLXSW_DEVICE_KIND_SWITCHX2; 69eda6500aSJiri Pirko default: 70eda6500aSJiri Pirko BUG(); 71eda6500aSJiri Pirko } 72eda6500aSJiri Pirko } 73eda6500aSJiri Pirko 74eda6500aSJiri Pirko #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 75eda6500aSJiri Pirko iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 76eda6500aSJiri Pirko #define mlxsw_pci_read32(mlxsw_pci, reg) \ 77eda6500aSJiri Pirko ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 78eda6500aSJiri Pirko 79eda6500aSJiri Pirko enum mlxsw_pci_queue_type { 80eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, 81eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, 82eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_CQ, 83eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_EQ, 84eda6500aSJiri Pirko }; 85eda6500aSJiri Pirko 86eda6500aSJiri Pirko static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type) 87eda6500aSJiri Pirko { 88eda6500aSJiri Pirko switch (q_type) { 89eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_SDQ: 90eda6500aSJiri Pirko return "sdq"; 91eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_RDQ: 92eda6500aSJiri Pirko return "rdq"; 93eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_CQ: 94eda6500aSJiri Pirko return "cq"; 95eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_EQ: 96eda6500aSJiri Pirko return "eq"; 97eda6500aSJiri Pirko } 98eda6500aSJiri Pirko BUG(); 99eda6500aSJiri Pirko } 100eda6500aSJiri Pirko 101eda6500aSJiri Pirko #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 102eda6500aSJiri Pirko 103eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_type_offset[] = { 104eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 105eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 106eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 107eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 108eda6500aSJiri Pirko }; 109eda6500aSJiri Pirko 110eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 111eda6500aSJiri Pirko 0, /* unused */ 112eda6500aSJiri Pirko 0, /* unused */ 113eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 114eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 115eda6500aSJiri Pirko }; 116eda6500aSJiri Pirko 117eda6500aSJiri Pirko struct mlxsw_pci_mem_item { 118eda6500aSJiri Pirko char *buf; 119eda6500aSJiri Pirko dma_addr_t mapaddr; 120eda6500aSJiri Pirko size_t size; 121eda6500aSJiri Pirko }; 122eda6500aSJiri Pirko 123eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info { 124eda6500aSJiri Pirko char *elem; /* pointer to actual dma mapped element mem chunk */ 125eda6500aSJiri Pirko union { 126eda6500aSJiri Pirko struct { 127eda6500aSJiri Pirko struct sk_buff *skb; 128eda6500aSJiri Pirko } sdq; 129eda6500aSJiri Pirko struct { 130eda6500aSJiri Pirko struct sk_buff *skb; 131eda6500aSJiri Pirko } rdq; 132eda6500aSJiri Pirko } u; 133eda6500aSJiri Pirko }; 134eda6500aSJiri Pirko 135eda6500aSJiri Pirko struct mlxsw_pci_queue { 136eda6500aSJiri Pirko spinlock_t lock; /* for queue accesses */ 137eda6500aSJiri Pirko struct mlxsw_pci_mem_item mem_item; 138eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 139eda6500aSJiri Pirko u16 producer_counter; 140eda6500aSJiri Pirko u16 consumer_counter; 141eda6500aSJiri Pirko u16 count; /* number of elements in queue */ 142eda6500aSJiri Pirko u8 num; /* queue number */ 143eda6500aSJiri Pirko u8 elem_size; /* size of one element */ 144eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 145eda6500aSJiri Pirko struct tasklet_struct tasklet; /* queue processing tasklet */ 146eda6500aSJiri Pirko struct mlxsw_pci *pci; 147eda6500aSJiri Pirko union { 148eda6500aSJiri Pirko struct { 149eda6500aSJiri Pirko u32 comp_sdq_count; 150eda6500aSJiri Pirko u32 comp_rdq_count; 151eda6500aSJiri Pirko } cq; 152eda6500aSJiri Pirko struct { 153eda6500aSJiri Pirko u32 ev_cmd_count; 154eda6500aSJiri Pirko u32 ev_comp_count; 155eda6500aSJiri Pirko u32 ev_other_count; 156eda6500aSJiri Pirko } eq; 157eda6500aSJiri Pirko } u; 158eda6500aSJiri Pirko }; 159eda6500aSJiri Pirko 160eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group { 161eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 162eda6500aSJiri Pirko u8 count; /* number of queues in group */ 163eda6500aSJiri Pirko }; 164eda6500aSJiri Pirko 165eda6500aSJiri Pirko struct mlxsw_pci { 166eda6500aSJiri Pirko struct pci_dev *pdev; 167eda6500aSJiri Pirko u8 __iomem *hw_addr; 168eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 169eda6500aSJiri Pirko u32 doorbell_offset; 170eda6500aSJiri Pirko struct msix_entry msix_entry; 171eda6500aSJiri Pirko struct mlxsw_core *core; 172eda6500aSJiri Pirko struct { 173eda6500aSJiri Pirko u16 num_pages; 174eda6500aSJiri Pirko struct mlxsw_pci_mem_item *items; 175eda6500aSJiri Pirko } fw_area; 176eda6500aSJiri Pirko struct { 177eda6500aSJiri Pirko struct mutex lock; /* Lock access to command registers */ 178eda6500aSJiri Pirko bool nopoll; 179eda6500aSJiri Pirko wait_queue_head_t wait; 180eda6500aSJiri Pirko bool wait_done; 181eda6500aSJiri Pirko struct { 182eda6500aSJiri Pirko u8 status; 183eda6500aSJiri Pirko u64 out_param; 184eda6500aSJiri Pirko } comp; 185eda6500aSJiri Pirko } cmd; 186eda6500aSJiri Pirko struct mlxsw_bus_info bus_info; 187eda6500aSJiri Pirko struct dentry *dbg_dir; 188eda6500aSJiri Pirko }; 189eda6500aSJiri Pirko 190eda6500aSJiri Pirko static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 191eda6500aSJiri Pirko { 192eda6500aSJiri Pirko tasklet_schedule(&q->tasklet); 193eda6500aSJiri Pirko } 194eda6500aSJiri Pirko 195eda6500aSJiri Pirko static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 196eda6500aSJiri Pirko size_t elem_size, int elem_index) 197eda6500aSJiri Pirko { 198eda6500aSJiri Pirko return q->mem_item.buf + (elem_size * elem_index); 199eda6500aSJiri Pirko } 200eda6500aSJiri Pirko 201eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 202eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 203eda6500aSJiri Pirko { 204eda6500aSJiri Pirko return &q->elem_info[elem_index]; 205eda6500aSJiri Pirko } 206eda6500aSJiri Pirko 207eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 208eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 209eda6500aSJiri Pirko { 210eda6500aSJiri Pirko int index = q->producer_counter & (q->count - 1); 211eda6500aSJiri Pirko 212eda6500aSJiri Pirko if ((q->producer_counter - q->consumer_counter) == q->count) 213eda6500aSJiri Pirko return NULL; 214eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 215eda6500aSJiri Pirko } 216eda6500aSJiri Pirko 217eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 218eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 219eda6500aSJiri Pirko { 220eda6500aSJiri Pirko int index = q->consumer_counter & (q->count - 1); 221eda6500aSJiri Pirko 222eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 223eda6500aSJiri Pirko } 224eda6500aSJiri Pirko 225eda6500aSJiri Pirko static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 226eda6500aSJiri Pirko { 227eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 228eda6500aSJiri Pirko } 229eda6500aSJiri Pirko 230eda6500aSJiri Pirko static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 231eda6500aSJiri Pirko { 232eda6500aSJiri Pirko return owner_bit != !!(q->consumer_counter & q->count); 233eda6500aSJiri Pirko } 234eda6500aSJiri Pirko 235eda6500aSJiri Pirko static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q, 236eda6500aSJiri Pirko u32 (*get_elem_owner_func)(char *)) 237eda6500aSJiri Pirko { 238eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 239eda6500aSJiri Pirko char *elem; 240eda6500aSJiri Pirko bool owner_bit; 241eda6500aSJiri Pirko 242eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 243eda6500aSJiri Pirko elem = elem_info->elem; 244eda6500aSJiri Pirko owner_bit = get_elem_owner_func(elem); 245eda6500aSJiri Pirko if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 246eda6500aSJiri Pirko return NULL; 247eda6500aSJiri Pirko q->consumer_counter++; 248eda6500aSJiri Pirko rmb(); /* make sure we read owned bit before the rest of elem */ 249eda6500aSJiri Pirko return elem; 250eda6500aSJiri Pirko } 251eda6500aSJiri Pirko 252eda6500aSJiri Pirko static struct mlxsw_pci_queue_type_group * 253eda6500aSJiri Pirko mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 254eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 255eda6500aSJiri Pirko { 256eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type]; 257eda6500aSJiri Pirko } 258eda6500aSJiri Pirko 259eda6500aSJiri Pirko static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 260eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 261eda6500aSJiri Pirko { 262eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 263eda6500aSJiri Pirko 264eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 265eda6500aSJiri Pirko return queue_group->count; 266eda6500aSJiri Pirko } 267eda6500aSJiri Pirko 268eda6500aSJiri Pirko static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 269eda6500aSJiri Pirko { 270eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 271eda6500aSJiri Pirko } 272eda6500aSJiri Pirko 273eda6500aSJiri Pirko static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci) 274eda6500aSJiri Pirko { 275eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ); 276eda6500aSJiri Pirko } 277eda6500aSJiri Pirko 278eda6500aSJiri Pirko static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 279eda6500aSJiri Pirko { 280eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 281eda6500aSJiri Pirko } 282eda6500aSJiri Pirko 283eda6500aSJiri Pirko static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci) 284eda6500aSJiri Pirko { 285eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ); 286eda6500aSJiri Pirko } 287eda6500aSJiri Pirko 288eda6500aSJiri Pirko static struct mlxsw_pci_queue * 289eda6500aSJiri Pirko __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 290eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type, u8 q_num) 291eda6500aSJiri Pirko { 292eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type].q[q_num]; 293eda6500aSJiri Pirko } 294eda6500aSJiri Pirko 295eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 296eda6500aSJiri Pirko u8 q_num) 297eda6500aSJiri Pirko { 298eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 299eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 300eda6500aSJiri Pirko } 301eda6500aSJiri Pirko 302eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 303eda6500aSJiri Pirko u8 q_num) 304eda6500aSJiri Pirko { 305eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 306eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 307eda6500aSJiri Pirko } 308eda6500aSJiri Pirko 309eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 310eda6500aSJiri Pirko u8 q_num) 311eda6500aSJiri Pirko { 312eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 313eda6500aSJiri Pirko } 314eda6500aSJiri Pirko 315eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 316eda6500aSJiri Pirko u8 q_num) 317eda6500aSJiri Pirko { 318eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 319eda6500aSJiri Pirko } 320eda6500aSJiri Pirko 321eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 322eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 323eda6500aSJiri Pirko u16 val) 324eda6500aSJiri Pirko { 325eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 326eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 327eda6500aSJiri Pirko mlxsw_pci_doorbell_type_offset[q->type], 328eda6500aSJiri Pirko q->num), val); 329eda6500aSJiri Pirko } 330eda6500aSJiri Pirko 331eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 332eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 333eda6500aSJiri Pirko u16 val) 334eda6500aSJiri Pirko { 335eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 336eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 337eda6500aSJiri Pirko mlxsw_pci_doorbell_arm_type_offset[q->type], 338eda6500aSJiri Pirko q->num), val); 339eda6500aSJiri Pirko } 340eda6500aSJiri Pirko 341eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 342eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 343eda6500aSJiri Pirko { 344eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 345eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 346eda6500aSJiri Pirko } 347eda6500aSJiri Pirko 348eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 349eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 350eda6500aSJiri Pirko { 351eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 352eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 353eda6500aSJiri Pirko q->consumer_counter + q->count); 354eda6500aSJiri Pirko } 355eda6500aSJiri Pirko 356eda6500aSJiri Pirko static void 357eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 358eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 359eda6500aSJiri Pirko { 360eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 361eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 362eda6500aSJiri Pirko } 363eda6500aSJiri Pirko 364eda6500aSJiri Pirko static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 365eda6500aSJiri Pirko int page_index) 366eda6500aSJiri Pirko { 367eda6500aSJiri Pirko return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 368eda6500aSJiri Pirko } 369eda6500aSJiri Pirko 370eda6500aSJiri Pirko static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 371eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 372eda6500aSJiri Pirko { 373eda6500aSJiri Pirko int i; 374eda6500aSJiri Pirko int err; 375eda6500aSJiri Pirko 376eda6500aSJiri Pirko q->producer_counter = 0; 377eda6500aSJiri Pirko q->consumer_counter = 0; 378eda6500aSJiri Pirko 379eda6500aSJiri Pirko /* Set CQ of same number of this SDQ. */ 380eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 381eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 7); 382eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 383eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 384eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 385eda6500aSJiri Pirko 386eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 387eda6500aSJiri Pirko } 388eda6500aSJiri Pirko 389eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 390eda6500aSJiri Pirko if (err) 391eda6500aSJiri Pirko return err; 392eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 393eda6500aSJiri Pirko return 0; 394eda6500aSJiri Pirko } 395eda6500aSJiri Pirko 396eda6500aSJiri Pirko static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 397eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 398eda6500aSJiri Pirko { 399eda6500aSJiri Pirko mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 400eda6500aSJiri Pirko } 401eda6500aSJiri Pirko 402eda6500aSJiri Pirko static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data) 403eda6500aSJiri Pirko { 404eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 405eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 406eda6500aSJiri Pirko int i; 407eda6500aSJiri Pirko static const char hdr[] = 408eda6500aSJiri Pirko "NUM PROD_COUNT CONS_COUNT COUNT\n"; 409eda6500aSJiri Pirko 410eda6500aSJiri Pirko seq_printf(file, hdr); 411eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) { 412eda6500aSJiri Pirko q = mlxsw_pci_sdq_get(mlxsw_pci, i); 413eda6500aSJiri Pirko spin_lock_bh(&q->lock); 414eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %5d\n", 415eda6500aSJiri Pirko i, q->producer_counter, q->consumer_counter, 416eda6500aSJiri Pirko q->count); 417eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 418eda6500aSJiri Pirko } 419eda6500aSJiri Pirko return 0; 420eda6500aSJiri Pirko } 421eda6500aSJiri Pirko 422eda6500aSJiri Pirko static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 423eda6500aSJiri Pirko int index, char *frag_data, size_t frag_len, 424eda6500aSJiri Pirko int direction) 425eda6500aSJiri Pirko { 426eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 427eda6500aSJiri Pirko dma_addr_t mapaddr; 428eda6500aSJiri Pirko 429eda6500aSJiri Pirko mapaddr = pci_map_single(pdev, frag_data, frag_len, direction); 430eda6500aSJiri Pirko if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) { 431eda6500aSJiri Pirko if (net_ratelimit()) 432eda6500aSJiri Pirko dev_err(&pdev->dev, "failed to dma map tx frag\n"); 433eda6500aSJiri Pirko return -EIO; 434eda6500aSJiri Pirko } 435eda6500aSJiri Pirko mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 436eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 437eda6500aSJiri Pirko return 0; 438eda6500aSJiri Pirko } 439eda6500aSJiri Pirko 440eda6500aSJiri Pirko static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 441eda6500aSJiri Pirko int index, int direction) 442eda6500aSJiri Pirko { 443eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 444eda6500aSJiri Pirko size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 445eda6500aSJiri Pirko dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 446eda6500aSJiri Pirko 447eda6500aSJiri Pirko if (!frag_len) 448eda6500aSJiri Pirko return; 449eda6500aSJiri Pirko pci_unmap_single(pdev, mapaddr, frag_len, direction); 450eda6500aSJiri Pirko } 451eda6500aSJiri Pirko 452eda6500aSJiri Pirko static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 453eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 454eda6500aSJiri Pirko { 455eda6500aSJiri Pirko size_t buf_len = MLXSW_PORT_MAX_MTU; 456eda6500aSJiri Pirko char *wqe = elem_info->elem; 457eda6500aSJiri Pirko struct sk_buff *skb; 458eda6500aSJiri Pirko int err; 459eda6500aSJiri Pirko 460eda6500aSJiri Pirko elem_info->u.rdq.skb = NULL; 461eda6500aSJiri Pirko skb = netdev_alloc_skb_ip_align(NULL, buf_len); 462eda6500aSJiri Pirko if (!skb) 463eda6500aSJiri Pirko return -ENOMEM; 464eda6500aSJiri Pirko 465eda6500aSJiri Pirko /* Assume that wqe was previously zeroed. */ 466eda6500aSJiri Pirko 467eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 468eda6500aSJiri Pirko buf_len, DMA_FROM_DEVICE); 469eda6500aSJiri Pirko if (err) 470eda6500aSJiri Pirko goto err_frag_map; 471eda6500aSJiri Pirko 472eda6500aSJiri Pirko elem_info->u.rdq.skb = skb; 473eda6500aSJiri Pirko return 0; 474eda6500aSJiri Pirko 475eda6500aSJiri Pirko err_frag_map: 476eda6500aSJiri Pirko dev_kfree_skb_any(skb); 477eda6500aSJiri Pirko return err; 478eda6500aSJiri Pirko } 479eda6500aSJiri Pirko 480eda6500aSJiri Pirko static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 481eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 482eda6500aSJiri Pirko { 483eda6500aSJiri Pirko struct sk_buff *skb; 484eda6500aSJiri Pirko char *wqe; 485eda6500aSJiri Pirko 486eda6500aSJiri Pirko skb = elem_info->u.rdq.skb; 487eda6500aSJiri Pirko wqe = elem_info->elem; 488eda6500aSJiri Pirko 489eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 490eda6500aSJiri Pirko dev_kfree_skb_any(skb); 491eda6500aSJiri Pirko } 492eda6500aSJiri Pirko 493eda6500aSJiri Pirko static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 494eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 495eda6500aSJiri Pirko { 496eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 497eda6500aSJiri Pirko int i; 498eda6500aSJiri Pirko int err; 499eda6500aSJiri Pirko 500eda6500aSJiri Pirko q->producer_counter = 0; 501eda6500aSJiri Pirko q->consumer_counter = 0; 502eda6500aSJiri Pirko 503eda6500aSJiri Pirko /* Set CQ of same number of this RDQ with base 504eda6500aSJiri Pirko * above MLXSW_PCI_SDQS_MAX as the lower ones are assigned to SDQs. 505eda6500aSJiri Pirko */ 506eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num + MLXSW_PCI_SDQS_COUNT); 507eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 508eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 509eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 510eda6500aSJiri Pirko 511eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 512eda6500aSJiri Pirko } 513eda6500aSJiri Pirko 514eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 515eda6500aSJiri Pirko if (err) 516eda6500aSJiri Pirko return err; 517eda6500aSJiri Pirko 518eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 519eda6500aSJiri Pirko 520eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 521eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 522eda6500aSJiri Pirko BUG_ON(!elem_info); 523eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 524eda6500aSJiri Pirko if (err) 525eda6500aSJiri Pirko goto rollback; 526eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 527eda6500aSJiri Pirko q->producer_counter++; 528eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 529eda6500aSJiri Pirko } 530eda6500aSJiri Pirko 531eda6500aSJiri Pirko return 0; 532eda6500aSJiri Pirko 533eda6500aSJiri Pirko rollback: 534eda6500aSJiri Pirko for (i--; i >= 0; i--) { 535eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 536eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 537eda6500aSJiri Pirko } 538eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 539eda6500aSJiri Pirko 540eda6500aSJiri Pirko return err; 541eda6500aSJiri Pirko } 542eda6500aSJiri Pirko 543eda6500aSJiri Pirko static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 544eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 545eda6500aSJiri Pirko { 546eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 547eda6500aSJiri Pirko int i; 548eda6500aSJiri Pirko 549eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 550eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 551eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 552eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 553eda6500aSJiri Pirko } 554eda6500aSJiri Pirko } 555eda6500aSJiri Pirko 556eda6500aSJiri Pirko static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data) 557eda6500aSJiri Pirko { 558eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 559eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 560eda6500aSJiri Pirko int i; 561eda6500aSJiri Pirko static const char hdr[] = 562eda6500aSJiri Pirko "NUM PROD_COUNT CONS_COUNT COUNT\n"; 563eda6500aSJiri Pirko 564eda6500aSJiri Pirko seq_printf(file, hdr); 565eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) { 566eda6500aSJiri Pirko q = mlxsw_pci_rdq_get(mlxsw_pci, i); 567eda6500aSJiri Pirko spin_lock_bh(&q->lock); 568eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %5d\n", 569eda6500aSJiri Pirko i, q->producer_counter, q->consumer_counter, 570eda6500aSJiri Pirko q->count); 571eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 572eda6500aSJiri Pirko } 573eda6500aSJiri Pirko return 0; 574eda6500aSJiri Pirko } 575eda6500aSJiri Pirko 576eda6500aSJiri Pirko static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 577eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 578eda6500aSJiri Pirko { 579eda6500aSJiri Pirko int i; 580eda6500aSJiri Pirko int err; 581eda6500aSJiri Pirko 582eda6500aSJiri Pirko q->consumer_counter = 0; 583eda6500aSJiri Pirko 584eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 585eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 586eda6500aSJiri Pirko 587eda6500aSJiri Pirko mlxsw_pci_cqe_owner_set(elem, 1); 588eda6500aSJiri Pirko } 589eda6500aSJiri Pirko 590eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */ 591eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 592eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0); 593eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 594eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 595eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 596eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 597eda6500aSJiri Pirko 598eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 599eda6500aSJiri Pirko } 600eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 601eda6500aSJiri Pirko if (err) 602eda6500aSJiri Pirko return err; 603eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 604eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 605eda6500aSJiri Pirko return 0; 606eda6500aSJiri Pirko } 607eda6500aSJiri Pirko 608eda6500aSJiri Pirko static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 609eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 610eda6500aSJiri Pirko { 611eda6500aSJiri Pirko mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 612eda6500aSJiri Pirko } 613eda6500aSJiri Pirko 614eda6500aSJiri Pirko static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data) 615eda6500aSJiri Pirko { 616eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 617eda6500aSJiri Pirko 618eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 619eda6500aSJiri Pirko int i; 620eda6500aSJiri Pirko static const char hdr[] = 621eda6500aSJiri Pirko "NUM CONS_INDEX SDQ_COUNT RDQ_COUNT COUNT\n"; 622eda6500aSJiri Pirko 623eda6500aSJiri Pirko seq_printf(file, hdr); 624eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) { 625eda6500aSJiri Pirko q = mlxsw_pci_cq_get(mlxsw_pci, i); 626eda6500aSJiri Pirko spin_lock_bh(&q->lock); 627eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %10d %5d\n", 628eda6500aSJiri Pirko i, q->consumer_counter, q->u.cq.comp_sdq_count, 629eda6500aSJiri Pirko q->u.cq.comp_rdq_count, q->count); 630eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 631eda6500aSJiri Pirko } 632eda6500aSJiri Pirko return 0; 633eda6500aSJiri Pirko } 634eda6500aSJiri Pirko 635eda6500aSJiri Pirko static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 636eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 637eda6500aSJiri Pirko u16 consumer_counter_limit, 638eda6500aSJiri Pirko char *cqe) 639eda6500aSJiri Pirko { 640eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 641eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 642eda6500aSJiri Pirko char *wqe; 643eda6500aSJiri Pirko struct sk_buff *skb; 644eda6500aSJiri Pirko int i; 645eda6500aSJiri Pirko 646eda6500aSJiri Pirko spin_lock(&q->lock); 647eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 648eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 649eda6500aSJiri Pirko wqe = elem_info->elem; 650eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 651eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 652eda6500aSJiri Pirko dev_kfree_skb_any(skb); 653eda6500aSJiri Pirko elem_info->u.sdq.skb = NULL; 654eda6500aSJiri Pirko 655eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 656eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 657eda6500aSJiri Pirko spin_unlock(&q->lock); 658eda6500aSJiri Pirko } 659eda6500aSJiri Pirko 660eda6500aSJiri Pirko static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 661eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 662eda6500aSJiri Pirko u16 consumer_counter_limit, 663eda6500aSJiri Pirko char *cqe) 664eda6500aSJiri Pirko { 665eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 666eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 667eda6500aSJiri Pirko char *wqe; 668eda6500aSJiri Pirko struct sk_buff *skb; 669eda6500aSJiri Pirko struct mlxsw_rx_info rx_info; 6707b7b9cffSJiri Pirko u16 byte_count; 671eda6500aSJiri Pirko int err; 672eda6500aSJiri Pirko 673eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 674eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 675eda6500aSJiri Pirko if (!skb) 676eda6500aSJiri Pirko return; 677eda6500aSJiri Pirko wqe = elem_info->elem; 678eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 679eda6500aSJiri Pirko 680eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 681eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 682eda6500aSJiri Pirko 683eda6500aSJiri Pirko /* We do not support lag now */ 684eda6500aSJiri Pirko if (mlxsw_pci_cqe_lag_get(cqe)) 685eda6500aSJiri Pirko goto drop; 686eda6500aSJiri Pirko 687eda6500aSJiri Pirko rx_info.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 688eda6500aSJiri Pirko rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 689eda6500aSJiri Pirko 6907b7b9cffSJiri Pirko byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 6917b7b9cffSJiri Pirko if (mlxsw_pci_cqe_crc_get(cqe)) 6927b7b9cffSJiri Pirko byte_count -= ETH_FCS_LEN; 6937b7b9cffSJiri Pirko skb_put(skb, byte_count); 694eda6500aSJiri Pirko mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 695eda6500aSJiri Pirko 696eda6500aSJiri Pirko put_new_skb: 697eda6500aSJiri Pirko memset(wqe, 0, q->elem_size); 698eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 699eda6500aSJiri Pirko if (err && net_ratelimit()) 700eda6500aSJiri Pirko dev_dbg(&pdev->dev, "Failed to alloc skb for RDQ\n"); 701eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 702eda6500aSJiri Pirko q->producer_counter++; 703eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 704eda6500aSJiri Pirko return; 705eda6500aSJiri Pirko 706eda6500aSJiri Pirko drop: 707eda6500aSJiri Pirko dev_kfree_skb_any(skb); 708eda6500aSJiri Pirko goto put_new_skb; 709eda6500aSJiri Pirko } 710eda6500aSJiri Pirko 711eda6500aSJiri Pirko static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 712eda6500aSJiri Pirko { 713eda6500aSJiri Pirko return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get); 714eda6500aSJiri Pirko } 715eda6500aSJiri Pirko 716eda6500aSJiri Pirko static void mlxsw_pci_cq_tasklet(unsigned long data) 717eda6500aSJiri Pirko { 718eda6500aSJiri Pirko struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 719eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 720eda6500aSJiri Pirko char *cqe; 721eda6500aSJiri Pirko int items = 0; 722eda6500aSJiri Pirko int credits = q->count >> 1; 723eda6500aSJiri Pirko 724eda6500aSJiri Pirko while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 725eda6500aSJiri Pirko u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 726eda6500aSJiri Pirko u8 sendq = mlxsw_pci_cqe_sr_get(cqe); 727eda6500aSJiri Pirko u8 dqn = mlxsw_pci_cqe_dqn_get(cqe); 728eda6500aSJiri Pirko 729eda6500aSJiri Pirko if (sendq) { 730eda6500aSJiri Pirko struct mlxsw_pci_queue *sdq; 731eda6500aSJiri Pirko 732eda6500aSJiri Pirko sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 733eda6500aSJiri Pirko mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 734eda6500aSJiri Pirko wqe_counter, cqe); 735eda6500aSJiri Pirko q->u.cq.comp_sdq_count++; 736eda6500aSJiri Pirko } else { 737eda6500aSJiri Pirko struct mlxsw_pci_queue *rdq; 738eda6500aSJiri Pirko 739eda6500aSJiri Pirko rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 740eda6500aSJiri Pirko mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 741eda6500aSJiri Pirko wqe_counter, cqe); 742eda6500aSJiri Pirko q->u.cq.comp_rdq_count++; 743eda6500aSJiri Pirko } 744eda6500aSJiri Pirko if (++items == credits) 745eda6500aSJiri Pirko break; 746eda6500aSJiri Pirko } 747eda6500aSJiri Pirko if (items) { 748eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 749eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 750eda6500aSJiri Pirko } 751eda6500aSJiri Pirko } 752eda6500aSJiri Pirko 753eda6500aSJiri Pirko static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 754eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 755eda6500aSJiri Pirko { 756eda6500aSJiri Pirko int i; 757eda6500aSJiri Pirko int err; 758eda6500aSJiri Pirko 759eda6500aSJiri Pirko q->consumer_counter = 0; 760eda6500aSJiri Pirko 761eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 762eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 763eda6500aSJiri Pirko 764eda6500aSJiri Pirko mlxsw_pci_eqe_owner_set(elem, 1); 765eda6500aSJiri Pirko } 766eda6500aSJiri Pirko 767eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 768eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0); 769eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 770eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 771eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 772eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 773eda6500aSJiri Pirko 774eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 775eda6500aSJiri Pirko } 776eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 777eda6500aSJiri Pirko if (err) 778eda6500aSJiri Pirko return err; 779eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 780eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 781eda6500aSJiri Pirko return 0; 782eda6500aSJiri Pirko } 783eda6500aSJiri Pirko 784eda6500aSJiri Pirko static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 785eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 786eda6500aSJiri Pirko { 787eda6500aSJiri Pirko mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 788eda6500aSJiri Pirko } 789eda6500aSJiri Pirko 790eda6500aSJiri Pirko static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data) 791eda6500aSJiri Pirko { 792eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 793eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 794eda6500aSJiri Pirko int i; 795eda6500aSJiri Pirko static const char hdr[] = 796eda6500aSJiri Pirko "NUM CONS_COUNT EV_CMD EV_COMP EV_OTHER COUNT\n"; 797eda6500aSJiri Pirko 798eda6500aSJiri Pirko seq_printf(file, hdr); 799eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) { 800eda6500aSJiri Pirko q = mlxsw_pci_eq_get(mlxsw_pci, i); 801eda6500aSJiri Pirko spin_lock_bh(&q->lock); 802eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %10d %10d %5d\n", 803eda6500aSJiri Pirko i, q->consumer_counter, q->u.eq.ev_cmd_count, 804eda6500aSJiri Pirko q->u.eq.ev_comp_count, q->u.eq.ev_other_count, 805eda6500aSJiri Pirko q->count); 806eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 807eda6500aSJiri Pirko } 808eda6500aSJiri Pirko return 0; 809eda6500aSJiri Pirko } 810eda6500aSJiri Pirko 811eda6500aSJiri Pirko static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 812eda6500aSJiri Pirko { 813eda6500aSJiri Pirko mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 814eda6500aSJiri Pirko mlxsw_pci->cmd.comp.out_param = 815eda6500aSJiri Pirko ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 816eda6500aSJiri Pirko mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 817eda6500aSJiri Pirko mlxsw_pci->cmd.wait_done = true; 818eda6500aSJiri Pirko wake_up(&mlxsw_pci->cmd.wait); 819eda6500aSJiri Pirko } 820eda6500aSJiri Pirko 821eda6500aSJiri Pirko static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 822eda6500aSJiri Pirko { 823eda6500aSJiri Pirko return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get); 824eda6500aSJiri Pirko } 825eda6500aSJiri Pirko 826eda6500aSJiri Pirko static void mlxsw_pci_eq_tasklet(unsigned long data) 827eda6500aSJiri Pirko { 828eda6500aSJiri Pirko struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 829eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 830eda6500aSJiri Pirko unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_COUNT)]; 831eda6500aSJiri Pirko char *eqe; 832eda6500aSJiri Pirko u8 cqn; 833eda6500aSJiri Pirko bool cq_handle = false; 834eda6500aSJiri Pirko int items = 0; 835eda6500aSJiri Pirko int credits = q->count >> 1; 836eda6500aSJiri Pirko 837eda6500aSJiri Pirko memset(&active_cqns, 0, sizeof(active_cqns)); 838eda6500aSJiri Pirko 839eda6500aSJiri Pirko while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 840eda6500aSJiri Pirko u8 event_type = mlxsw_pci_eqe_event_type_get(eqe); 841eda6500aSJiri Pirko 842eda6500aSJiri Pirko switch (event_type) { 843eda6500aSJiri Pirko case MLXSW_PCI_EQE_EVENT_TYPE_CMD: 844eda6500aSJiri Pirko mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 845eda6500aSJiri Pirko q->u.eq.ev_cmd_count++; 846eda6500aSJiri Pirko break; 847eda6500aSJiri Pirko case MLXSW_PCI_EQE_EVENT_TYPE_COMP: 848eda6500aSJiri Pirko cqn = mlxsw_pci_eqe_cqn_get(eqe); 849eda6500aSJiri Pirko set_bit(cqn, active_cqns); 850eda6500aSJiri Pirko cq_handle = true; 851eda6500aSJiri Pirko q->u.eq.ev_comp_count++; 852eda6500aSJiri Pirko break; 853eda6500aSJiri Pirko default: 854eda6500aSJiri Pirko q->u.eq.ev_other_count++; 855eda6500aSJiri Pirko } 856eda6500aSJiri Pirko if (++items == credits) 857eda6500aSJiri Pirko break; 858eda6500aSJiri Pirko } 859eda6500aSJiri Pirko if (items) { 860eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 861eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 862eda6500aSJiri Pirko } 863eda6500aSJiri Pirko 864eda6500aSJiri Pirko if (!cq_handle) 865eda6500aSJiri Pirko return; 866eda6500aSJiri Pirko for_each_set_bit(cqn, active_cqns, MLXSW_PCI_CQS_COUNT) { 867eda6500aSJiri Pirko q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 868eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 869eda6500aSJiri Pirko } 870eda6500aSJiri Pirko } 871eda6500aSJiri Pirko 872eda6500aSJiri Pirko struct mlxsw_pci_queue_ops { 873eda6500aSJiri Pirko const char *name; 874eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 875eda6500aSJiri Pirko int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 876eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 877eda6500aSJiri Pirko void (*fini)(struct mlxsw_pci *mlxsw_pci, 878eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 879eda6500aSJiri Pirko void (*tasklet)(unsigned long data); 880eda6500aSJiri Pirko int (*dbg_read)(struct seq_file *s, void *data); 881eda6500aSJiri Pirko u16 elem_count; 882eda6500aSJiri Pirko u8 elem_size; 883eda6500aSJiri Pirko }; 884eda6500aSJiri Pirko 885eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 886eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 887eda6500aSJiri Pirko .init = mlxsw_pci_sdq_init, 888eda6500aSJiri Pirko .fini = mlxsw_pci_sdq_fini, 889eda6500aSJiri Pirko .dbg_read = mlxsw_pci_sdq_dbg_read, 890eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 891eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE, 892eda6500aSJiri Pirko }; 893eda6500aSJiri Pirko 894eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 895eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 896eda6500aSJiri Pirko .init = mlxsw_pci_rdq_init, 897eda6500aSJiri Pirko .fini = mlxsw_pci_rdq_fini, 898eda6500aSJiri Pirko .dbg_read = mlxsw_pci_rdq_dbg_read, 899eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 900eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE 901eda6500aSJiri Pirko }; 902eda6500aSJiri Pirko 903eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 904eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_CQ, 905eda6500aSJiri Pirko .init = mlxsw_pci_cq_init, 906eda6500aSJiri Pirko .fini = mlxsw_pci_cq_fini, 907eda6500aSJiri Pirko .tasklet = mlxsw_pci_cq_tasklet, 908eda6500aSJiri Pirko .dbg_read = mlxsw_pci_cq_dbg_read, 909eda6500aSJiri Pirko .elem_count = MLXSW_PCI_CQE_COUNT, 910eda6500aSJiri Pirko .elem_size = MLXSW_PCI_CQE_SIZE 911eda6500aSJiri Pirko }; 912eda6500aSJiri Pirko 913eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 914eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_EQ, 915eda6500aSJiri Pirko .init = mlxsw_pci_eq_init, 916eda6500aSJiri Pirko .fini = mlxsw_pci_eq_fini, 917eda6500aSJiri Pirko .tasklet = mlxsw_pci_eq_tasklet, 918eda6500aSJiri Pirko .dbg_read = mlxsw_pci_eq_dbg_read, 919eda6500aSJiri Pirko .elem_count = MLXSW_PCI_EQE_COUNT, 920eda6500aSJiri Pirko .elem_size = MLXSW_PCI_EQE_SIZE 921eda6500aSJiri Pirko }; 922eda6500aSJiri Pirko 923eda6500aSJiri Pirko static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 924eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 925eda6500aSJiri Pirko struct mlxsw_pci_queue *q, u8 q_num) 926eda6500aSJiri Pirko { 927eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 928eda6500aSJiri Pirko int i; 929eda6500aSJiri Pirko int err; 930eda6500aSJiri Pirko 931eda6500aSJiri Pirko spin_lock_init(&q->lock); 932eda6500aSJiri Pirko q->num = q_num; 933eda6500aSJiri Pirko q->count = q_ops->elem_count; 934eda6500aSJiri Pirko q->elem_size = q_ops->elem_size; 935eda6500aSJiri Pirko q->type = q_ops->type; 936eda6500aSJiri Pirko q->pci = mlxsw_pci; 937eda6500aSJiri Pirko 938eda6500aSJiri Pirko if (q_ops->tasklet) 939eda6500aSJiri Pirko tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q); 940eda6500aSJiri Pirko 941eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_AQ_SIZE; 942eda6500aSJiri Pirko mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 943eda6500aSJiri Pirko mem_item->size, 944eda6500aSJiri Pirko &mem_item->mapaddr); 945eda6500aSJiri Pirko if (!mem_item->buf) 946eda6500aSJiri Pirko return -ENOMEM; 947eda6500aSJiri Pirko memset(mem_item->buf, 0, mem_item->size); 948eda6500aSJiri Pirko 949eda6500aSJiri Pirko q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 950eda6500aSJiri Pirko if (!q->elem_info) { 951eda6500aSJiri Pirko err = -ENOMEM; 952eda6500aSJiri Pirko goto err_elem_info_alloc; 953eda6500aSJiri Pirko } 954eda6500aSJiri Pirko 955eda6500aSJiri Pirko /* Initialize dma mapped elements info elem_info for 956eda6500aSJiri Pirko * future easy access. 957eda6500aSJiri Pirko */ 958eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 959eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 960eda6500aSJiri Pirko 961eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 962eda6500aSJiri Pirko elem_info->elem = 963eda6500aSJiri Pirko __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i); 964eda6500aSJiri Pirko } 965eda6500aSJiri Pirko 966eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 967eda6500aSJiri Pirko err = q_ops->init(mlxsw_pci, mbox, q); 968eda6500aSJiri Pirko if (err) 969eda6500aSJiri Pirko goto err_q_ops_init; 970eda6500aSJiri Pirko return 0; 971eda6500aSJiri Pirko 972eda6500aSJiri Pirko err_q_ops_init: 973eda6500aSJiri Pirko kfree(q->elem_info); 974eda6500aSJiri Pirko err_elem_info_alloc: 975eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 976eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 977eda6500aSJiri Pirko return err; 978eda6500aSJiri Pirko } 979eda6500aSJiri Pirko 980eda6500aSJiri Pirko static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 981eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 982eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 983eda6500aSJiri Pirko { 984eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 985eda6500aSJiri Pirko 986eda6500aSJiri Pirko q_ops->fini(mlxsw_pci, q); 987eda6500aSJiri Pirko kfree(q->elem_info); 988eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 989eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 990eda6500aSJiri Pirko } 991eda6500aSJiri Pirko 992eda6500aSJiri Pirko static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 993eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 994eda6500aSJiri Pirko u8 num_qs) 995eda6500aSJiri Pirko { 996eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 997eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 998eda6500aSJiri Pirko char tmp[16]; 999eda6500aSJiri Pirko int i; 1000eda6500aSJiri Pirko int err; 1001eda6500aSJiri Pirko 1002eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1003eda6500aSJiri Pirko queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 1004eda6500aSJiri Pirko if (!queue_group->q) 1005eda6500aSJiri Pirko return -ENOMEM; 1006eda6500aSJiri Pirko 1007eda6500aSJiri Pirko for (i = 0; i < num_qs; i++) { 1008eda6500aSJiri Pirko err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 1009eda6500aSJiri Pirko &queue_group->q[i], i); 1010eda6500aSJiri Pirko if (err) 1011eda6500aSJiri Pirko goto err_queue_init; 1012eda6500aSJiri Pirko } 1013eda6500aSJiri Pirko queue_group->count = num_qs; 1014eda6500aSJiri Pirko 1015eda6500aSJiri Pirko sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type)); 1016eda6500aSJiri Pirko debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir, 1017eda6500aSJiri Pirko q_ops->dbg_read); 1018eda6500aSJiri Pirko 1019eda6500aSJiri Pirko return 0; 1020eda6500aSJiri Pirko 1021eda6500aSJiri Pirko err_queue_init: 1022eda6500aSJiri Pirko for (i--; i >= 0; i--) 1023eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1024eda6500aSJiri Pirko kfree(queue_group->q); 1025eda6500aSJiri Pirko return err; 1026eda6500aSJiri Pirko } 1027eda6500aSJiri Pirko 1028eda6500aSJiri Pirko static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 1029eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops) 1030eda6500aSJiri Pirko { 1031eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 1032eda6500aSJiri Pirko int i; 1033eda6500aSJiri Pirko 1034eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1035eda6500aSJiri Pirko for (i = 0; i < queue_group->count; i++) 1036eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1037eda6500aSJiri Pirko kfree(queue_group->q); 1038eda6500aSJiri Pirko } 1039eda6500aSJiri Pirko 1040eda6500aSJiri Pirko static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1041eda6500aSJiri Pirko { 1042eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1043eda6500aSJiri Pirko u8 num_sdqs; 1044eda6500aSJiri Pirko u8 sdq_log2sz; 1045eda6500aSJiri Pirko u8 num_rdqs; 1046eda6500aSJiri Pirko u8 rdq_log2sz; 1047eda6500aSJiri Pirko u8 num_cqs; 1048eda6500aSJiri Pirko u8 cq_log2sz; 1049eda6500aSJiri Pirko u8 num_eqs; 1050eda6500aSJiri Pirko u8 eq_log2sz; 1051eda6500aSJiri Pirko int err; 1052eda6500aSJiri Pirko 1053eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1054eda6500aSJiri Pirko err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1055eda6500aSJiri Pirko if (err) 1056eda6500aSJiri Pirko return err; 1057eda6500aSJiri Pirko 1058eda6500aSJiri Pirko num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1059eda6500aSJiri Pirko sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1060eda6500aSJiri Pirko num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1061eda6500aSJiri Pirko rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1062eda6500aSJiri Pirko num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1063eda6500aSJiri Pirko cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1064eda6500aSJiri Pirko num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1065eda6500aSJiri Pirko eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1066eda6500aSJiri Pirko 1067eda6500aSJiri Pirko if ((num_sdqs != MLXSW_PCI_SDQS_COUNT) || 1068eda6500aSJiri Pirko (num_rdqs != MLXSW_PCI_RDQS_COUNT) || 1069eda6500aSJiri Pirko (num_cqs != MLXSW_PCI_CQS_COUNT) || 1070eda6500aSJiri Pirko (num_eqs != MLXSW_PCI_EQS_COUNT)) { 1071eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of queues\n"); 1072eda6500aSJiri Pirko return -EINVAL; 1073eda6500aSJiri Pirko } 1074eda6500aSJiri Pirko 1075eda6500aSJiri Pirko if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1076eda6500aSJiri Pirko (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1077eda6500aSJiri Pirko (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) || 1078eda6500aSJiri Pirko (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1079eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1080eda6500aSJiri Pirko return -EINVAL; 1081eda6500aSJiri Pirko } 1082eda6500aSJiri Pirko 1083eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1084eda6500aSJiri Pirko num_eqs); 1085eda6500aSJiri Pirko if (err) { 1086eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1087eda6500aSJiri Pirko return err; 1088eda6500aSJiri Pirko } 1089eda6500aSJiri Pirko 1090eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1091eda6500aSJiri Pirko num_cqs); 1092eda6500aSJiri Pirko if (err) { 1093eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1094eda6500aSJiri Pirko goto err_cqs_init; 1095eda6500aSJiri Pirko } 1096eda6500aSJiri Pirko 1097eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1098eda6500aSJiri Pirko num_sdqs); 1099eda6500aSJiri Pirko if (err) { 1100eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1101eda6500aSJiri Pirko goto err_sdqs_init; 1102eda6500aSJiri Pirko } 1103eda6500aSJiri Pirko 1104eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1105eda6500aSJiri Pirko num_rdqs); 1106eda6500aSJiri Pirko if (err) { 1107eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1108eda6500aSJiri Pirko goto err_rdqs_init; 1109eda6500aSJiri Pirko } 1110eda6500aSJiri Pirko 1111eda6500aSJiri Pirko /* We have to poll in command interface until queues are initialized */ 1112eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = true; 1113eda6500aSJiri Pirko return 0; 1114eda6500aSJiri Pirko 1115eda6500aSJiri Pirko err_rdqs_init: 1116eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1117eda6500aSJiri Pirko err_sdqs_init: 1118eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1119eda6500aSJiri Pirko err_cqs_init: 1120eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1121eda6500aSJiri Pirko return err; 1122eda6500aSJiri Pirko } 1123eda6500aSJiri Pirko 1124eda6500aSJiri Pirko static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1125eda6500aSJiri Pirko { 1126eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = false; 1127eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1128eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1129eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1130eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1131eda6500aSJiri Pirko } 1132eda6500aSJiri Pirko 1133eda6500aSJiri Pirko static void 1134eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1135eda6500aSJiri Pirko char *mbox, int index, 1136eda6500aSJiri Pirko const struct mlxsw_swid_config *swid) 1137eda6500aSJiri Pirko { 1138eda6500aSJiri Pirko u8 mask = 0; 1139eda6500aSJiri Pirko 1140eda6500aSJiri Pirko if (swid->used_type) { 1141eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1142eda6500aSJiri Pirko mbox, index, swid->type); 1143eda6500aSJiri Pirko mask |= 1; 1144eda6500aSJiri Pirko } 1145eda6500aSJiri Pirko if (swid->used_properties) { 1146eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1147eda6500aSJiri Pirko mbox, index, swid->properties); 1148eda6500aSJiri Pirko mask |= 2; 1149eda6500aSJiri Pirko } 1150eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1151eda6500aSJiri Pirko } 1152eda6500aSJiri Pirko 1153eda6500aSJiri Pirko static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1154eda6500aSJiri Pirko const struct mlxsw_config_profile *profile) 1155eda6500aSJiri Pirko { 1156eda6500aSJiri Pirko int i; 1157eda6500aSJiri Pirko 1158eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1159eda6500aSJiri Pirko 1160eda6500aSJiri Pirko if (profile->used_max_vepa_channels) { 1161eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1162eda6500aSJiri Pirko mbox, 1); 1163eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1164eda6500aSJiri Pirko mbox, profile->max_vepa_channels); 1165eda6500aSJiri Pirko } 1166eda6500aSJiri Pirko if (profile->used_max_lag) { 1167eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_lag_set( 1168eda6500aSJiri Pirko mbox, 1); 1169eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_lag_set( 1170eda6500aSJiri Pirko mbox, profile->max_lag); 1171eda6500aSJiri Pirko } 1172eda6500aSJiri Pirko if (profile->used_max_port_per_lag) { 1173eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set( 1174eda6500aSJiri Pirko mbox, 1); 1175eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_port_per_lag_set( 1176eda6500aSJiri Pirko mbox, profile->max_port_per_lag); 1177eda6500aSJiri Pirko } 1178eda6500aSJiri Pirko if (profile->used_max_mid) { 1179eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1180eda6500aSJiri Pirko mbox, 1); 1181eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_mid_set( 1182eda6500aSJiri Pirko mbox, profile->max_mid); 1183eda6500aSJiri Pirko } 1184eda6500aSJiri Pirko if (profile->used_max_pgt) { 1185eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1186eda6500aSJiri Pirko mbox, 1); 1187eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pgt_set( 1188eda6500aSJiri Pirko mbox, profile->max_pgt); 1189eda6500aSJiri Pirko } 1190eda6500aSJiri Pirko if (profile->used_max_system_port) { 1191eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1192eda6500aSJiri Pirko mbox, 1); 1193eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_system_port_set( 1194eda6500aSJiri Pirko mbox, profile->max_system_port); 1195eda6500aSJiri Pirko } 1196eda6500aSJiri Pirko if (profile->used_max_vlan_groups) { 1197eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1198eda6500aSJiri Pirko mbox, 1); 1199eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1200eda6500aSJiri Pirko mbox, profile->max_vlan_groups); 1201eda6500aSJiri Pirko } 1202eda6500aSJiri Pirko if (profile->used_max_regions) { 1203eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1204eda6500aSJiri Pirko mbox, 1); 1205eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_regions_set( 1206eda6500aSJiri Pirko mbox, profile->max_regions); 1207eda6500aSJiri Pirko } 1208eda6500aSJiri Pirko if (profile->used_flood_tables) { 1209eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1210eda6500aSJiri Pirko mbox, 1); 1211eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1212eda6500aSJiri Pirko mbox, profile->max_flood_tables); 1213eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1214eda6500aSJiri Pirko mbox, profile->max_vid_flood_tables); 1215eda6500aSJiri Pirko } 1216eda6500aSJiri Pirko if (profile->used_flood_mode) { 1217eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1218eda6500aSJiri Pirko mbox, 1); 1219eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_flood_mode_set( 1220eda6500aSJiri Pirko mbox, profile->flood_mode); 1221eda6500aSJiri Pirko } 1222eda6500aSJiri Pirko if (profile->used_max_ib_mc) { 1223eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1224eda6500aSJiri Pirko mbox, 1); 1225eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1226eda6500aSJiri Pirko mbox, profile->max_ib_mc); 1227eda6500aSJiri Pirko } 1228eda6500aSJiri Pirko if (profile->used_max_pkey) { 1229eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1230eda6500aSJiri Pirko mbox, 1); 1231eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pkey_set( 1232eda6500aSJiri Pirko mbox, profile->max_pkey); 1233eda6500aSJiri Pirko } 1234eda6500aSJiri Pirko if (profile->used_ar_sec) { 1235eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1236eda6500aSJiri Pirko mbox, 1); 1237eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_ar_sec_set( 1238eda6500aSJiri Pirko mbox, profile->ar_sec); 1239eda6500aSJiri Pirko } 1240eda6500aSJiri Pirko if (profile->used_adaptive_routing_group_cap) { 1241eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1242eda6500aSJiri Pirko mbox, 1); 1243eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1244eda6500aSJiri Pirko mbox, profile->adaptive_routing_group_cap); 1245eda6500aSJiri Pirko } 1246eda6500aSJiri Pirko 1247eda6500aSJiri Pirko for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1248eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1249eda6500aSJiri Pirko &profile->swid_config[i]); 1250eda6500aSJiri Pirko 1251eda6500aSJiri Pirko return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1252eda6500aSJiri Pirko } 1253eda6500aSJiri Pirko 1254eda6500aSJiri Pirko static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1255eda6500aSJiri Pirko { 1256eda6500aSJiri Pirko struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1257eda6500aSJiri Pirko int err; 1258eda6500aSJiri Pirko 1259eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1260eda6500aSJiri Pirko err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1261eda6500aSJiri Pirko if (err) 1262eda6500aSJiri Pirko return err; 1263eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1264eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1265eda6500aSJiri Pirko return 0; 1266eda6500aSJiri Pirko } 1267eda6500aSJiri Pirko 1268eda6500aSJiri Pirko static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1269eda6500aSJiri Pirko u16 num_pages) 1270eda6500aSJiri Pirko { 1271eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 1272eda6500aSJiri Pirko int i; 1273eda6500aSJiri Pirko int err; 1274eda6500aSJiri Pirko 1275eda6500aSJiri Pirko mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1276eda6500aSJiri Pirko GFP_KERNEL); 1277eda6500aSJiri Pirko if (!mlxsw_pci->fw_area.items) 1278eda6500aSJiri Pirko return -ENOMEM; 1279eda6500aSJiri Pirko mlxsw_pci->fw_area.num_pages = num_pages; 1280eda6500aSJiri Pirko 1281eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1282eda6500aSJiri Pirko for (i = 0; i < num_pages; i++) { 1283eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1284eda6500aSJiri Pirko 1285eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_PAGE_SIZE; 1286eda6500aSJiri Pirko mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 1287eda6500aSJiri Pirko mem_item->size, 1288eda6500aSJiri Pirko &mem_item->mapaddr); 1289eda6500aSJiri Pirko if (!mem_item->buf) { 1290eda6500aSJiri Pirko err = -ENOMEM; 1291eda6500aSJiri Pirko goto err_alloc; 1292eda6500aSJiri Pirko } 1293eda6500aSJiri Pirko mlxsw_cmd_mbox_map_fa_pa_set(mbox, i, mem_item->mapaddr); 1294eda6500aSJiri Pirko mlxsw_cmd_mbox_map_fa_log2size_set(mbox, i, 0); /* 1 page */ 1295eda6500aSJiri Pirko } 1296eda6500aSJiri Pirko 1297eda6500aSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, num_pages); 1298eda6500aSJiri Pirko if (err) 1299eda6500aSJiri Pirko goto err_cmd_map_fa; 1300eda6500aSJiri Pirko 1301eda6500aSJiri Pirko return 0; 1302eda6500aSJiri Pirko 1303eda6500aSJiri Pirko err_cmd_map_fa: 1304eda6500aSJiri Pirko err_alloc: 1305eda6500aSJiri Pirko for (i--; i >= 0; i--) { 1306eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1307eda6500aSJiri Pirko 1308eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1309eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1310eda6500aSJiri Pirko } 1311eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1312eda6500aSJiri Pirko return err; 1313eda6500aSJiri Pirko } 1314eda6500aSJiri Pirko 1315eda6500aSJiri Pirko static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1316eda6500aSJiri Pirko { 1317eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 1318eda6500aSJiri Pirko int i; 1319eda6500aSJiri Pirko 1320eda6500aSJiri Pirko mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1321eda6500aSJiri Pirko 1322eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci->fw_area.num_pages; i++) { 1323eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1324eda6500aSJiri Pirko 1325eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1326eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1327eda6500aSJiri Pirko } 1328eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1329eda6500aSJiri Pirko } 1330eda6500aSJiri Pirko 1331eda6500aSJiri Pirko static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1332eda6500aSJiri Pirko { 1333eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_id; 1334eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1335eda6500aSJiri Pirko int i; 1336eda6500aSJiri Pirko 1337eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1338eda6500aSJiri Pirko q = mlxsw_pci_eq_get(mlxsw_pci, i); 1339eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 1340eda6500aSJiri Pirko } 1341eda6500aSJiri Pirko return IRQ_HANDLED; 1342eda6500aSJiri Pirko } 1343eda6500aSJiri Pirko 1344eda6500aSJiri Pirko static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1345eda6500aSJiri Pirko const struct mlxsw_config_profile *profile) 1346eda6500aSJiri Pirko { 1347eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1348eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1349eda6500aSJiri Pirko char *mbox; 1350eda6500aSJiri Pirko u16 num_pages; 1351eda6500aSJiri Pirko int err; 1352eda6500aSJiri Pirko 1353eda6500aSJiri Pirko mutex_init(&mlxsw_pci->cmd.lock); 1354eda6500aSJiri Pirko init_waitqueue_head(&mlxsw_pci->cmd.wait); 1355eda6500aSJiri Pirko 1356eda6500aSJiri Pirko mlxsw_pci->core = mlxsw_core; 1357eda6500aSJiri Pirko 1358eda6500aSJiri Pirko mbox = mlxsw_cmd_mbox_alloc(); 1359eda6500aSJiri Pirko if (!mbox) 1360eda6500aSJiri Pirko return -ENOMEM; 1361eda6500aSJiri Pirko err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1362eda6500aSJiri Pirko if (err) 1363eda6500aSJiri Pirko goto err_query_fw; 1364eda6500aSJiri Pirko 1365eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.major = 1366eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1367eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.minor = 1368eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1369eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.subminor = 1370eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1371eda6500aSJiri Pirko 1372eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1373eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1374eda6500aSJiri Pirko err = -EINVAL; 1375eda6500aSJiri Pirko goto err_iface_rev; 1376eda6500aSJiri Pirko } 1377eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1378eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1379eda6500aSJiri Pirko err = -EINVAL; 1380eda6500aSJiri Pirko goto err_doorbell_page_bar; 1381eda6500aSJiri Pirko } 1382eda6500aSJiri Pirko 1383eda6500aSJiri Pirko mlxsw_pci->doorbell_offset = 1384eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1385eda6500aSJiri Pirko 1386eda6500aSJiri Pirko num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1387eda6500aSJiri Pirko err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1388eda6500aSJiri Pirko if (err) 1389eda6500aSJiri Pirko goto err_fw_area_init; 1390eda6500aSJiri Pirko 1391eda6500aSJiri Pirko err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1392eda6500aSJiri Pirko if (err) 1393eda6500aSJiri Pirko goto err_boardinfo; 1394eda6500aSJiri Pirko 1395eda6500aSJiri Pirko err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile); 1396eda6500aSJiri Pirko if (err) 1397eda6500aSJiri Pirko goto err_config_profile; 1398eda6500aSJiri Pirko 1399eda6500aSJiri Pirko err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1400eda6500aSJiri Pirko if (err) 1401eda6500aSJiri Pirko goto err_aqs_init; 1402eda6500aSJiri Pirko 1403eda6500aSJiri Pirko err = request_irq(mlxsw_pci->msix_entry.vector, 1404eda6500aSJiri Pirko mlxsw_pci_eq_irq_handler, 0, 1405eda6500aSJiri Pirko mlxsw_pci_driver_name, mlxsw_pci); 1406eda6500aSJiri Pirko if (err) { 1407eda6500aSJiri Pirko dev_err(&pdev->dev, "IRQ request failed\n"); 1408eda6500aSJiri Pirko goto err_request_eq_irq; 1409eda6500aSJiri Pirko } 1410eda6500aSJiri Pirko 1411eda6500aSJiri Pirko goto mbox_put; 1412eda6500aSJiri Pirko 1413eda6500aSJiri Pirko err_request_eq_irq: 1414eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1415eda6500aSJiri Pirko err_aqs_init: 1416eda6500aSJiri Pirko err_config_profile: 1417eda6500aSJiri Pirko err_boardinfo: 1418eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1419eda6500aSJiri Pirko err_fw_area_init: 1420eda6500aSJiri Pirko err_doorbell_page_bar: 1421eda6500aSJiri Pirko err_iface_rev: 1422eda6500aSJiri Pirko err_query_fw: 1423eda6500aSJiri Pirko mbox_put: 1424eda6500aSJiri Pirko mlxsw_cmd_mbox_free(mbox); 1425eda6500aSJiri Pirko return err; 1426eda6500aSJiri Pirko } 1427eda6500aSJiri Pirko 1428eda6500aSJiri Pirko static void mlxsw_pci_fini(void *bus_priv) 1429eda6500aSJiri Pirko { 1430eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1431eda6500aSJiri Pirko 1432eda6500aSJiri Pirko free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci); 1433eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1434eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1435eda6500aSJiri Pirko } 1436eda6500aSJiri Pirko 1437eda6500aSJiri Pirko static struct mlxsw_pci_queue * 1438eda6500aSJiri Pirko mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1439eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1440eda6500aSJiri Pirko { 1441eda6500aSJiri Pirko u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci); 1442eda6500aSJiri Pirko 1443eda6500aSJiri Pirko return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1444eda6500aSJiri Pirko } 1445eda6500aSJiri Pirko 1446d003462aSIdo Schimmel static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1447d003462aSIdo Schimmel const struct mlxsw_tx_info *tx_info) 1448d003462aSIdo Schimmel { 1449d003462aSIdo Schimmel struct mlxsw_pci *mlxsw_pci = bus_priv; 1450d003462aSIdo Schimmel struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1451d003462aSIdo Schimmel 1452d003462aSIdo Schimmel return !mlxsw_pci_queue_elem_info_producer_get(q); 1453d003462aSIdo Schimmel } 1454d003462aSIdo Schimmel 1455eda6500aSJiri Pirko static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1456eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1457eda6500aSJiri Pirko { 1458eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1459eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1460eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 1461eda6500aSJiri Pirko char *wqe; 1462eda6500aSJiri Pirko int i; 1463eda6500aSJiri Pirko int err; 1464eda6500aSJiri Pirko 1465eda6500aSJiri Pirko if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1466eda6500aSJiri Pirko err = skb_linearize(skb); 1467eda6500aSJiri Pirko if (err) 1468eda6500aSJiri Pirko return err; 1469eda6500aSJiri Pirko } 1470eda6500aSJiri Pirko 1471eda6500aSJiri Pirko q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1472eda6500aSJiri Pirko spin_lock_bh(&q->lock); 1473eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1474eda6500aSJiri Pirko if (!elem_info) { 1475eda6500aSJiri Pirko /* queue is full */ 1476eda6500aSJiri Pirko err = -EAGAIN; 1477eda6500aSJiri Pirko goto unlock; 1478eda6500aSJiri Pirko } 1479eda6500aSJiri Pirko elem_info->u.sdq.skb = skb; 1480eda6500aSJiri Pirko 1481eda6500aSJiri Pirko wqe = elem_info->elem; 1482eda6500aSJiri Pirko mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1483eda6500aSJiri Pirko mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1484eda6500aSJiri Pirko mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1485eda6500aSJiri Pirko 1486eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1487eda6500aSJiri Pirko skb_headlen(skb), DMA_TO_DEVICE); 1488eda6500aSJiri Pirko if (err) 1489eda6500aSJiri Pirko goto unlock; 1490eda6500aSJiri Pirko 1491eda6500aSJiri Pirko for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1492eda6500aSJiri Pirko const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1493eda6500aSJiri Pirko 1494eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1495eda6500aSJiri Pirko skb_frag_address(frag), 1496eda6500aSJiri Pirko skb_frag_size(frag), 1497eda6500aSJiri Pirko DMA_TO_DEVICE); 1498eda6500aSJiri Pirko if (err) 1499eda6500aSJiri Pirko goto unmap_frags; 1500eda6500aSJiri Pirko } 1501eda6500aSJiri Pirko 1502eda6500aSJiri Pirko /* Set unused sq entries byte count to zero. */ 1503eda6500aSJiri Pirko for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1504eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1505eda6500aSJiri Pirko 1506eda6500aSJiri Pirko /* Everything is set up, ring producer doorbell to get HW going */ 1507eda6500aSJiri Pirko q->producer_counter++; 1508eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1509eda6500aSJiri Pirko 1510eda6500aSJiri Pirko goto unlock; 1511eda6500aSJiri Pirko 1512eda6500aSJiri Pirko unmap_frags: 1513eda6500aSJiri Pirko for (; i >= 0; i--) 1514eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1515eda6500aSJiri Pirko unlock: 1516eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 1517eda6500aSJiri Pirko return err; 1518eda6500aSJiri Pirko } 1519eda6500aSJiri Pirko 1520eda6500aSJiri Pirko static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1521eda6500aSJiri Pirko u32 in_mod, bool out_mbox_direct, 1522eda6500aSJiri Pirko char *in_mbox, size_t in_mbox_size, 1523eda6500aSJiri Pirko char *out_mbox, size_t out_mbox_size, 1524eda6500aSJiri Pirko u8 *p_status) 1525eda6500aSJiri Pirko { 1526eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1527eda6500aSJiri Pirko dma_addr_t in_mapaddr = 0; 1528eda6500aSJiri Pirko dma_addr_t out_mapaddr = 0; 1529eda6500aSJiri Pirko bool evreq = mlxsw_pci->cmd.nopoll; 1530eda6500aSJiri Pirko unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1531eda6500aSJiri Pirko bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1532eda6500aSJiri Pirko int err; 1533eda6500aSJiri Pirko 1534eda6500aSJiri Pirko *p_status = MLXSW_CMD_STATUS_OK; 1535eda6500aSJiri Pirko 1536eda6500aSJiri Pirko err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1537eda6500aSJiri Pirko if (err) 1538eda6500aSJiri Pirko return err; 1539eda6500aSJiri Pirko 1540eda6500aSJiri Pirko if (in_mbox) { 1541eda6500aSJiri Pirko in_mapaddr = pci_map_single(mlxsw_pci->pdev, in_mbox, 1542eda6500aSJiri Pirko in_mbox_size, PCI_DMA_TODEVICE); 1543eda6500aSJiri Pirko if (unlikely(pci_dma_mapping_error(mlxsw_pci->pdev, 1544eda6500aSJiri Pirko in_mapaddr))) { 1545eda6500aSJiri Pirko err = -EIO; 1546eda6500aSJiri Pirko goto err_in_mbox_map; 1547eda6500aSJiri Pirko } 1548eda6500aSJiri Pirko } 1549eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, in_mapaddr >> 32); 1550eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, in_mapaddr); 1551eda6500aSJiri Pirko 1552eda6500aSJiri Pirko if (out_mbox) { 1553eda6500aSJiri Pirko out_mapaddr = pci_map_single(mlxsw_pci->pdev, out_mbox, 1554eda6500aSJiri Pirko out_mbox_size, PCI_DMA_FROMDEVICE); 1555eda6500aSJiri Pirko if (unlikely(pci_dma_mapping_error(mlxsw_pci->pdev, 1556eda6500aSJiri Pirko out_mapaddr))) { 1557eda6500aSJiri Pirko err = -EIO; 1558eda6500aSJiri Pirko goto err_out_mbox_map; 1559eda6500aSJiri Pirko } 1560eda6500aSJiri Pirko } 1561eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, out_mapaddr >> 32); 1562eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, out_mapaddr); 1563eda6500aSJiri Pirko 1564eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1565eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1566eda6500aSJiri Pirko 1567eda6500aSJiri Pirko *p_wait_done = false; 1568eda6500aSJiri Pirko 1569eda6500aSJiri Pirko wmb(); /* all needs to be written before we write control register */ 1570eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1571eda6500aSJiri Pirko MLXSW_PCI_CIR_CTRL_GO_BIT | 1572eda6500aSJiri Pirko (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1573eda6500aSJiri Pirko (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1574eda6500aSJiri Pirko opcode); 1575eda6500aSJiri Pirko 1576eda6500aSJiri Pirko if (!evreq) { 1577eda6500aSJiri Pirko unsigned long end; 1578eda6500aSJiri Pirko 1579eda6500aSJiri Pirko end = jiffies + timeout; 1580eda6500aSJiri Pirko do { 1581eda6500aSJiri Pirko u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1582eda6500aSJiri Pirko 1583eda6500aSJiri Pirko if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1584eda6500aSJiri Pirko *p_wait_done = true; 1585eda6500aSJiri Pirko *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1586eda6500aSJiri Pirko break; 1587eda6500aSJiri Pirko } 1588eda6500aSJiri Pirko cond_resched(); 1589eda6500aSJiri Pirko } while (time_before(jiffies, end)); 1590eda6500aSJiri Pirko } else { 1591eda6500aSJiri Pirko wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1592eda6500aSJiri Pirko *p_status = mlxsw_pci->cmd.comp.status; 1593eda6500aSJiri Pirko } 1594eda6500aSJiri Pirko 1595eda6500aSJiri Pirko err = 0; 1596eda6500aSJiri Pirko if (*p_wait_done) { 1597eda6500aSJiri Pirko if (*p_status) 1598eda6500aSJiri Pirko err = -EIO; 1599eda6500aSJiri Pirko } else { 1600eda6500aSJiri Pirko err = -ETIMEDOUT; 1601eda6500aSJiri Pirko } 1602eda6500aSJiri Pirko 1603eda6500aSJiri Pirko if (!err && out_mbox && out_mbox_direct) { 1604eda6500aSJiri Pirko /* Some commands does not use output param as address to mailbox 1605eda6500aSJiri Pirko * but they store output directly into registers. In that case, 1606eda6500aSJiri Pirko * copy registers into mbox buffer. 1607eda6500aSJiri Pirko */ 1608eda6500aSJiri Pirko __be32 tmp; 1609eda6500aSJiri Pirko 1610eda6500aSJiri Pirko if (!evreq) { 1611eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1612eda6500aSJiri Pirko CIR_OUT_PARAM_HI)); 1613eda6500aSJiri Pirko memcpy(out_mbox, &tmp, sizeof(tmp)); 1614eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1615eda6500aSJiri Pirko CIR_OUT_PARAM_LO)); 1616eda6500aSJiri Pirko memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1617eda6500aSJiri Pirko } 1618eda6500aSJiri Pirko } 1619eda6500aSJiri Pirko 1620eda6500aSJiri Pirko if (out_mapaddr) 1621eda6500aSJiri Pirko pci_unmap_single(mlxsw_pci->pdev, out_mapaddr, out_mbox_size, 1622eda6500aSJiri Pirko PCI_DMA_FROMDEVICE); 1623eda6500aSJiri Pirko 1624eda6500aSJiri Pirko /* fall through */ 1625eda6500aSJiri Pirko 1626eda6500aSJiri Pirko err_out_mbox_map: 1627eda6500aSJiri Pirko if (in_mapaddr) 1628eda6500aSJiri Pirko pci_unmap_single(mlxsw_pci->pdev, in_mapaddr, in_mbox_size, 1629eda6500aSJiri Pirko PCI_DMA_TODEVICE); 1630eda6500aSJiri Pirko err_in_mbox_map: 1631eda6500aSJiri Pirko mutex_unlock(&mlxsw_pci->cmd.lock); 1632eda6500aSJiri Pirko 1633eda6500aSJiri Pirko return err; 1634eda6500aSJiri Pirko } 1635eda6500aSJiri Pirko 1636eda6500aSJiri Pirko static const struct mlxsw_bus mlxsw_pci_bus = { 1637eda6500aSJiri Pirko .kind = "pci", 1638eda6500aSJiri Pirko .init = mlxsw_pci_init, 1639eda6500aSJiri Pirko .fini = mlxsw_pci_fini, 1640d003462aSIdo Schimmel .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 1641eda6500aSJiri Pirko .skb_transmit = mlxsw_pci_skb_transmit, 1642eda6500aSJiri Pirko .cmd_exec = mlxsw_pci_cmd_exec, 1643eda6500aSJiri Pirko }; 1644eda6500aSJiri Pirko 1645eda6500aSJiri Pirko static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci) 1646eda6500aSJiri Pirko { 1647eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT); 1648eda6500aSJiri Pirko /* Current firware does not let us know when the reset is done. 1649eda6500aSJiri Pirko * So we just wait here for constant time and hope for the best. 1650eda6500aSJiri Pirko */ 1651eda6500aSJiri Pirko msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1652eda6500aSJiri Pirko return 0; 1653eda6500aSJiri Pirko } 1654eda6500aSJiri Pirko 1655eda6500aSJiri Pirko static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1656eda6500aSJiri Pirko { 1657eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci; 1658eda6500aSJiri Pirko int err; 1659eda6500aSJiri Pirko 1660eda6500aSJiri Pirko mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1661eda6500aSJiri Pirko if (!mlxsw_pci) 1662eda6500aSJiri Pirko return -ENOMEM; 1663eda6500aSJiri Pirko 1664eda6500aSJiri Pirko err = pci_enable_device(pdev); 1665eda6500aSJiri Pirko if (err) { 1666eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_enable_device failed\n"); 1667eda6500aSJiri Pirko goto err_pci_enable_device; 1668eda6500aSJiri Pirko } 1669eda6500aSJiri Pirko 1670eda6500aSJiri Pirko err = pci_request_regions(pdev, mlxsw_pci_driver_name); 1671eda6500aSJiri Pirko if (err) { 1672eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_request_regions failed\n"); 1673eda6500aSJiri Pirko goto err_pci_request_regions; 1674eda6500aSJiri Pirko } 1675eda6500aSJiri Pirko 1676eda6500aSJiri Pirko err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1677eda6500aSJiri Pirko if (!err) { 1678eda6500aSJiri Pirko err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1679eda6500aSJiri Pirko if (err) { 1680eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n"); 1681eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1682eda6500aSJiri Pirko } 1683eda6500aSJiri Pirko } else { 1684eda6500aSJiri Pirko err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1685eda6500aSJiri Pirko if (err) { 1686eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_set_dma_mask failed\n"); 1687eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1688eda6500aSJiri Pirko } 1689eda6500aSJiri Pirko } 1690eda6500aSJiri Pirko 1691eda6500aSJiri Pirko if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1692eda6500aSJiri Pirko dev_err(&pdev->dev, "invalid PCI region size\n"); 1693eda6500aSJiri Pirko err = -EINVAL; 1694eda6500aSJiri Pirko goto err_pci_resource_len_check; 1695eda6500aSJiri Pirko } 1696eda6500aSJiri Pirko 1697eda6500aSJiri Pirko mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1698eda6500aSJiri Pirko pci_resource_len(pdev, 0)); 1699eda6500aSJiri Pirko if (!mlxsw_pci->hw_addr) { 1700eda6500aSJiri Pirko dev_err(&pdev->dev, "ioremap failed\n"); 1701eda6500aSJiri Pirko err = -EIO; 1702eda6500aSJiri Pirko goto err_ioremap; 1703eda6500aSJiri Pirko } 1704eda6500aSJiri Pirko pci_set_master(pdev); 1705eda6500aSJiri Pirko 1706eda6500aSJiri Pirko mlxsw_pci->pdev = pdev; 1707eda6500aSJiri Pirko pci_set_drvdata(pdev, mlxsw_pci); 1708eda6500aSJiri Pirko 1709eda6500aSJiri Pirko err = mlxsw_pci_sw_reset(mlxsw_pci); 1710eda6500aSJiri Pirko if (err) { 1711eda6500aSJiri Pirko dev_err(&pdev->dev, "Software reset failed\n"); 1712eda6500aSJiri Pirko goto err_sw_reset; 1713eda6500aSJiri Pirko } 1714eda6500aSJiri Pirko 1715eda6500aSJiri Pirko err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1); 1716eda6500aSJiri Pirko if (err) { 1717eda6500aSJiri Pirko dev_err(&pdev->dev, "MSI-X init failed\n"); 1718eda6500aSJiri Pirko goto err_msix_init; 1719eda6500aSJiri Pirko } 1720eda6500aSJiri Pirko 1721eda6500aSJiri Pirko mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id); 1722eda6500aSJiri Pirko mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1723eda6500aSJiri Pirko mlxsw_pci->bus_info.dev = &pdev->dev; 1724eda6500aSJiri Pirko 1725eda6500aSJiri Pirko mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name, 1726eda6500aSJiri Pirko mlxsw_pci_dbg_root); 1727eda6500aSJiri Pirko if (!mlxsw_pci->dbg_dir) { 1728eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to create debugfs dir\n"); 17295c121979SJulia Lawall err = -ENOMEM; 1730eda6500aSJiri Pirko goto err_dbg_create_dir; 1731eda6500aSJiri Pirko } 1732eda6500aSJiri Pirko 1733eda6500aSJiri Pirko err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 1734eda6500aSJiri Pirko &mlxsw_pci_bus, mlxsw_pci); 1735eda6500aSJiri Pirko if (err) { 1736eda6500aSJiri Pirko dev_err(&pdev->dev, "cannot register bus device\n"); 1737eda6500aSJiri Pirko goto err_bus_device_register; 1738eda6500aSJiri Pirko } 1739eda6500aSJiri Pirko 1740eda6500aSJiri Pirko return 0; 1741eda6500aSJiri Pirko 1742eda6500aSJiri Pirko err_bus_device_register: 1743eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci->dbg_dir); 1744eda6500aSJiri Pirko err_dbg_create_dir: 1745eda6500aSJiri Pirko pci_disable_msix(mlxsw_pci->pdev); 1746eda6500aSJiri Pirko err_msix_init: 1747eda6500aSJiri Pirko err_sw_reset: 1748eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1749eda6500aSJiri Pirko err_ioremap: 1750eda6500aSJiri Pirko err_pci_resource_len_check: 1751eda6500aSJiri Pirko err_pci_set_dma_mask: 1752eda6500aSJiri Pirko pci_release_regions(pdev); 1753eda6500aSJiri Pirko err_pci_request_regions: 1754eda6500aSJiri Pirko pci_disable_device(pdev); 1755eda6500aSJiri Pirko err_pci_enable_device: 1756eda6500aSJiri Pirko kfree(mlxsw_pci); 1757eda6500aSJiri Pirko return err; 1758eda6500aSJiri Pirko } 1759eda6500aSJiri Pirko 1760eda6500aSJiri Pirko static void mlxsw_pci_remove(struct pci_dev *pdev) 1761eda6500aSJiri Pirko { 1762eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1763eda6500aSJiri Pirko 1764eda6500aSJiri Pirko mlxsw_core_bus_device_unregister(mlxsw_pci->core); 1765eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci->dbg_dir); 1766eda6500aSJiri Pirko pci_disable_msix(mlxsw_pci->pdev); 1767eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1768eda6500aSJiri Pirko pci_release_regions(mlxsw_pci->pdev); 1769eda6500aSJiri Pirko pci_disable_device(mlxsw_pci->pdev); 1770eda6500aSJiri Pirko kfree(mlxsw_pci); 1771eda6500aSJiri Pirko } 1772eda6500aSJiri Pirko 1773eda6500aSJiri Pirko static struct pci_driver mlxsw_pci_driver = { 1774eda6500aSJiri Pirko .name = mlxsw_pci_driver_name, 1775eda6500aSJiri Pirko .id_table = mlxsw_pci_id_table, 1776eda6500aSJiri Pirko .probe = mlxsw_pci_probe, 1777eda6500aSJiri Pirko .remove = mlxsw_pci_remove, 1778eda6500aSJiri Pirko }; 1779eda6500aSJiri Pirko 1780eda6500aSJiri Pirko static int __init mlxsw_pci_module_init(void) 1781eda6500aSJiri Pirko { 1782eda6500aSJiri Pirko int err; 1783eda6500aSJiri Pirko 1784eda6500aSJiri Pirko mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL); 1785eda6500aSJiri Pirko if (!mlxsw_pci_dbg_root) 1786eda6500aSJiri Pirko return -ENOMEM; 1787eda6500aSJiri Pirko err = pci_register_driver(&mlxsw_pci_driver); 1788eda6500aSJiri Pirko if (err) 1789eda6500aSJiri Pirko goto err_register_driver; 1790eda6500aSJiri Pirko return 0; 1791eda6500aSJiri Pirko 1792eda6500aSJiri Pirko err_register_driver: 1793eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci_dbg_root); 1794eda6500aSJiri Pirko return err; 1795eda6500aSJiri Pirko } 1796eda6500aSJiri Pirko 1797eda6500aSJiri Pirko static void __exit mlxsw_pci_module_exit(void) 1798eda6500aSJiri Pirko { 1799eda6500aSJiri Pirko pci_unregister_driver(&mlxsw_pci_driver); 1800eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci_dbg_root); 1801eda6500aSJiri Pirko } 1802eda6500aSJiri Pirko 1803eda6500aSJiri Pirko module_init(mlxsw_pci_module_init); 1804eda6500aSJiri Pirko module_exit(mlxsw_pci_module_exit); 1805eda6500aSJiri Pirko 1806eda6500aSJiri Pirko MODULE_LICENSE("Dual BSD/GPL"); 1807eda6500aSJiri Pirko MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 1808eda6500aSJiri Pirko MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 1809eda6500aSJiri Pirko MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table); 1810