1eda6500aSJiri Pirko /* 2eda6500aSJiri Pirko * drivers/net/ethernet/mellanox/mlxsw/pci.c 3eda6500aSJiri Pirko * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4eda6500aSJiri Pirko * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5eda6500aSJiri Pirko * 6eda6500aSJiri Pirko * Redistribution and use in source and binary forms, with or without 7eda6500aSJiri Pirko * modification, are permitted provided that the following conditions are met: 8eda6500aSJiri Pirko * 9eda6500aSJiri Pirko * 1. Redistributions of source code must retain the above copyright 10eda6500aSJiri Pirko * notice, this list of conditions and the following disclaimer. 11eda6500aSJiri Pirko * 2. Redistributions in binary form must reproduce the above copyright 12eda6500aSJiri Pirko * notice, this list of conditions and the following disclaimer in the 13eda6500aSJiri Pirko * documentation and/or other materials provided with the distribution. 14eda6500aSJiri Pirko * 3. Neither the names of the copyright holders nor the names of its 15eda6500aSJiri Pirko * contributors may be used to endorse or promote products derived from 16eda6500aSJiri Pirko * this software without specific prior written permission. 17eda6500aSJiri Pirko * 18eda6500aSJiri Pirko * Alternatively, this software may be distributed under the terms of the 19eda6500aSJiri Pirko * GNU General Public License ("GPL") version 2 as published by the Free 20eda6500aSJiri Pirko * Software Foundation. 21eda6500aSJiri Pirko * 22eda6500aSJiri Pirko * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23eda6500aSJiri Pirko * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24eda6500aSJiri Pirko * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25eda6500aSJiri Pirko * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26eda6500aSJiri Pirko * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27eda6500aSJiri Pirko * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28eda6500aSJiri Pirko * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29eda6500aSJiri Pirko * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30eda6500aSJiri Pirko * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31eda6500aSJiri Pirko * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32eda6500aSJiri Pirko * POSSIBILITY OF SUCH DAMAGE. 33eda6500aSJiri Pirko */ 34eda6500aSJiri Pirko 35eda6500aSJiri Pirko #include <linux/kernel.h> 36eda6500aSJiri Pirko #include <linux/module.h> 37eda6500aSJiri Pirko #include <linux/export.h> 38eda6500aSJiri Pirko #include <linux/err.h> 39eda6500aSJiri Pirko #include <linux/device.h> 40eda6500aSJiri Pirko #include <linux/pci.h> 41eda6500aSJiri Pirko #include <linux/interrupt.h> 42eda6500aSJiri Pirko #include <linux/wait.h> 43eda6500aSJiri Pirko #include <linux/types.h> 44eda6500aSJiri Pirko #include <linux/skbuff.h> 45eda6500aSJiri Pirko #include <linux/if_vlan.h> 46eda6500aSJiri Pirko #include <linux/log2.h> 47eda6500aSJiri Pirko #include <linux/debugfs.h> 48eda6500aSJiri Pirko #include <linux/seq_file.h> 491e81779aSIdo Schimmel #include <linux/string.h> 50eda6500aSJiri Pirko 51eda6500aSJiri Pirko #include "pci.h" 52eda6500aSJiri Pirko #include "core.h" 53eda6500aSJiri Pirko #include "cmd.h" 54eda6500aSJiri Pirko #include "port.h" 55eda6500aSJiri Pirko 56eda6500aSJiri Pirko static const char mlxsw_pci_driver_name[] = "mlxsw_pci"; 57eda6500aSJiri Pirko 58eda6500aSJiri Pirko static const struct pci_device_id mlxsw_pci_id_table[] = { 5931557f0fSJiri Pirko {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0}, 60eda6500aSJiri Pirko {0, } 61eda6500aSJiri Pirko }; 62eda6500aSJiri Pirko 63eda6500aSJiri Pirko static struct dentry *mlxsw_pci_dbg_root; 64eda6500aSJiri Pirko 65eda6500aSJiri Pirko static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id) 66eda6500aSJiri Pirko { 67eda6500aSJiri Pirko switch (id->device) { 6831557f0fSJiri Pirko case PCI_DEVICE_ID_MELLANOX_SWITCHX2: 6931557f0fSJiri Pirko return MLXSW_DEVICE_KIND_SWITCHX2; 70eda6500aSJiri Pirko default: 71eda6500aSJiri Pirko BUG(); 72eda6500aSJiri Pirko } 73eda6500aSJiri Pirko } 74eda6500aSJiri Pirko 75eda6500aSJiri Pirko #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 76eda6500aSJiri Pirko iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 77eda6500aSJiri Pirko #define mlxsw_pci_read32(mlxsw_pci, reg) \ 78eda6500aSJiri Pirko ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 79eda6500aSJiri Pirko 80eda6500aSJiri Pirko enum mlxsw_pci_queue_type { 81eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, 82eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, 83eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_CQ, 84eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_EQ, 85eda6500aSJiri Pirko }; 86eda6500aSJiri Pirko 87eda6500aSJiri Pirko static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type) 88eda6500aSJiri Pirko { 89eda6500aSJiri Pirko switch (q_type) { 90eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_SDQ: 91eda6500aSJiri Pirko return "sdq"; 92eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_RDQ: 93eda6500aSJiri Pirko return "rdq"; 94eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_CQ: 95eda6500aSJiri Pirko return "cq"; 96eda6500aSJiri Pirko case MLXSW_PCI_QUEUE_TYPE_EQ: 97eda6500aSJiri Pirko return "eq"; 98eda6500aSJiri Pirko } 99eda6500aSJiri Pirko BUG(); 100eda6500aSJiri Pirko } 101eda6500aSJiri Pirko 102eda6500aSJiri Pirko #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 103eda6500aSJiri Pirko 104eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_type_offset[] = { 105eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 106eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 107eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 108eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 109eda6500aSJiri Pirko }; 110eda6500aSJiri Pirko 111eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 112eda6500aSJiri Pirko 0, /* unused */ 113eda6500aSJiri Pirko 0, /* unused */ 114eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 115eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 116eda6500aSJiri Pirko }; 117eda6500aSJiri Pirko 118eda6500aSJiri Pirko struct mlxsw_pci_mem_item { 119eda6500aSJiri Pirko char *buf; 120eda6500aSJiri Pirko dma_addr_t mapaddr; 121eda6500aSJiri Pirko size_t size; 122eda6500aSJiri Pirko }; 123eda6500aSJiri Pirko 124eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info { 125eda6500aSJiri Pirko char *elem; /* pointer to actual dma mapped element mem chunk */ 126eda6500aSJiri Pirko union { 127eda6500aSJiri Pirko struct { 128eda6500aSJiri Pirko struct sk_buff *skb; 129eda6500aSJiri Pirko } sdq; 130eda6500aSJiri Pirko struct { 131eda6500aSJiri Pirko struct sk_buff *skb; 132eda6500aSJiri Pirko } rdq; 133eda6500aSJiri Pirko } u; 134eda6500aSJiri Pirko }; 135eda6500aSJiri Pirko 136eda6500aSJiri Pirko struct mlxsw_pci_queue { 137eda6500aSJiri Pirko spinlock_t lock; /* for queue accesses */ 138eda6500aSJiri Pirko struct mlxsw_pci_mem_item mem_item; 139eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 140eda6500aSJiri Pirko u16 producer_counter; 141eda6500aSJiri Pirko u16 consumer_counter; 142eda6500aSJiri Pirko u16 count; /* number of elements in queue */ 143eda6500aSJiri Pirko u8 num; /* queue number */ 144eda6500aSJiri Pirko u8 elem_size; /* size of one element */ 145eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 146eda6500aSJiri Pirko struct tasklet_struct tasklet; /* queue processing tasklet */ 147eda6500aSJiri Pirko struct mlxsw_pci *pci; 148eda6500aSJiri Pirko union { 149eda6500aSJiri Pirko struct { 150eda6500aSJiri Pirko u32 comp_sdq_count; 151eda6500aSJiri Pirko u32 comp_rdq_count; 152eda6500aSJiri Pirko } cq; 153eda6500aSJiri Pirko struct { 154eda6500aSJiri Pirko u32 ev_cmd_count; 155eda6500aSJiri Pirko u32 ev_comp_count; 156eda6500aSJiri Pirko u32 ev_other_count; 157eda6500aSJiri Pirko } eq; 158eda6500aSJiri Pirko } u; 159eda6500aSJiri Pirko }; 160eda6500aSJiri Pirko 161eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group { 162eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 163eda6500aSJiri Pirko u8 count; /* number of queues in group */ 164eda6500aSJiri Pirko }; 165eda6500aSJiri Pirko 166eda6500aSJiri Pirko struct mlxsw_pci { 167eda6500aSJiri Pirko struct pci_dev *pdev; 168eda6500aSJiri Pirko u8 __iomem *hw_addr; 169eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 170eda6500aSJiri Pirko u32 doorbell_offset; 171eda6500aSJiri Pirko struct msix_entry msix_entry; 172eda6500aSJiri Pirko struct mlxsw_core *core; 173eda6500aSJiri Pirko struct { 174eda6500aSJiri Pirko struct mlxsw_pci_mem_item *items; 1753e2206daSJiri Pirko unsigned int count; 176eda6500aSJiri Pirko } fw_area; 177eda6500aSJiri Pirko struct { 1781e81779aSIdo Schimmel struct mlxsw_pci_mem_item out_mbox; 1791e81779aSIdo Schimmel struct mlxsw_pci_mem_item in_mbox; 180eda6500aSJiri Pirko struct mutex lock; /* Lock access to command registers */ 181eda6500aSJiri Pirko bool nopoll; 182eda6500aSJiri Pirko wait_queue_head_t wait; 183eda6500aSJiri Pirko bool wait_done; 184eda6500aSJiri Pirko struct { 185eda6500aSJiri Pirko u8 status; 186eda6500aSJiri Pirko u64 out_param; 187eda6500aSJiri Pirko } comp; 188eda6500aSJiri Pirko } cmd; 189eda6500aSJiri Pirko struct mlxsw_bus_info bus_info; 190eda6500aSJiri Pirko struct dentry *dbg_dir; 191eda6500aSJiri Pirko }; 192eda6500aSJiri Pirko 193eda6500aSJiri Pirko static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 194eda6500aSJiri Pirko { 195eda6500aSJiri Pirko tasklet_schedule(&q->tasklet); 196eda6500aSJiri Pirko } 197eda6500aSJiri Pirko 198eda6500aSJiri Pirko static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 199eda6500aSJiri Pirko size_t elem_size, int elem_index) 200eda6500aSJiri Pirko { 201eda6500aSJiri Pirko return q->mem_item.buf + (elem_size * elem_index); 202eda6500aSJiri Pirko } 203eda6500aSJiri Pirko 204eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 205eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 206eda6500aSJiri Pirko { 207eda6500aSJiri Pirko return &q->elem_info[elem_index]; 208eda6500aSJiri Pirko } 209eda6500aSJiri Pirko 210eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 211eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 212eda6500aSJiri Pirko { 213eda6500aSJiri Pirko int index = q->producer_counter & (q->count - 1); 214eda6500aSJiri Pirko 215eda6500aSJiri Pirko if ((q->producer_counter - q->consumer_counter) == q->count) 216eda6500aSJiri Pirko return NULL; 217eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 218eda6500aSJiri Pirko } 219eda6500aSJiri Pirko 220eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 221eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 222eda6500aSJiri Pirko { 223eda6500aSJiri Pirko int index = q->consumer_counter & (q->count - 1); 224eda6500aSJiri Pirko 225eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 226eda6500aSJiri Pirko } 227eda6500aSJiri Pirko 228eda6500aSJiri Pirko static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 229eda6500aSJiri Pirko { 230eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 231eda6500aSJiri Pirko } 232eda6500aSJiri Pirko 233eda6500aSJiri Pirko static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 234eda6500aSJiri Pirko { 235eda6500aSJiri Pirko return owner_bit != !!(q->consumer_counter & q->count); 236eda6500aSJiri Pirko } 237eda6500aSJiri Pirko 238eda6500aSJiri Pirko static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q, 239eda6500aSJiri Pirko u32 (*get_elem_owner_func)(char *)) 240eda6500aSJiri Pirko { 241eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 242eda6500aSJiri Pirko char *elem; 243eda6500aSJiri Pirko bool owner_bit; 244eda6500aSJiri Pirko 245eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 246eda6500aSJiri Pirko elem = elem_info->elem; 247eda6500aSJiri Pirko owner_bit = get_elem_owner_func(elem); 248eda6500aSJiri Pirko if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 249eda6500aSJiri Pirko return NULL; 250eda6500aSJiri Pirko q->consumer_counter++; 251eda6500aSJiri Pirko rmb(); /* make sure we read owned bit before the rest of elem */ 252eda6500aSJiri Pirko return elem; 253eda6500aSJiri Pirko } 254eda6500aSJiri Pirko 255eda6500aSJiri Pirko static struct mlxsw_pci_queue_type_group * 256eda6500aSJiri Pirko mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 257eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 258eda6500aSJiri Pirko { 259eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type]; 260eda6500aSJiri Pirko } 261eda6500aSJiri Pirko 262eda6500aSJiri Pirko static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 263eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 264eda6500aSJiri Pirko { 265eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 266eda6500aSJiri Pirko 267eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 268eda6500aSJiri Pirko return queue_group->count; 269eda6500aSJiri Pirko } 270eda6500aSJiri Pirko 271eda6500aSJiri Pirko static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 272eda6500aSJiri Pirko { 273eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 274eda6500aSJiri Pirko } 275eda6500aSJiri Pirko 276eda6500aSJiri Pirko static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci) 277eda6500aSJiri Pirko { 278eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ); 279eda6500aSJiri Pirko } 280eda6500aSJiri Pirko 281eda6500aSJiri Pirko static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 282eda6500aSJiri Pirko { 283eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 284eda6500aSJiri Pirko } 285eda6500aSJiri Pirko 286eda6500aSJiri Pirko static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci) 287eda6500aSJiri Pirko { 288eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ); 289eda6500aSJiri Pirko } 290eda6500aSJiri Pirko 291eda6500aSJiri Pirko static struct mlxsw_pci_queue * 292eda6500aSJiri Pirko __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 293eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type, u8 q_num) 294eda6500aSJiri Pirko { 295eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type].q[q_num]; 296eda6500aSJiri Pirko } 297eda6500aSJiri Pirko 298eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 299eda6500aSJiri Pirko u8 q_num) 300eda6500aSJiri Pirko { 301eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 302eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 303eda6500aSJiri Pirko } 304eda6500aSJiri Pirko 305eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 306eda6500aSJiri Pirko u8 q_num) 307eda6500aSJiri Pirko { 308eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 309eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 310eda6500aSJiri Pirko } 311eda6500aSJiri Pirko 312eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 313eda6500aSJiri Pirko u8 q_num) 314eda6500aSJiri Pirko { 315eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 316eda6500aSJiri Pirko } 317eda6500aSJiri Pirko 318eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 319eda6500aSJiri Pirko u8 q_num) 320eda6500aSJiri Pirko { 321eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 322eda6500aSJiri Pirko } 323eda6500aSJiri Pirko 324eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 325eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 326eda6500aSJiri Pirko u16 val) 327eda6500aSJiri Pirko { 328eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 329eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 330eda6500aSJiri Pirko mlxsw_pci_doorbell_type_offset[q->type], 331eda6500aSJiri Pirko q->num), val); 332eda6500aSJiri Pirko } 333eda6500aSJiri Pirko 334eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 335eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 336eda6500aSJiri Pirko u16 val) 337eda6500aSJiri Pirko { 338eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 339eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 340eda6500aSJiri Pirko mlxsw_pci_doorbell_arm_type_offset[q->type], 341eda6500aSJiri Pirko q->num), val); 342eda6500aSJiri Pirko } 343eda6500aSJiri Pirko 344eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 345eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 346eda6500aSJiri Pirko { 347eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 348eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 349eda6500aSJiri Pirko } 350eda6500aSJiri Pirko 351eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 352eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 353eda6500aSJiri Pirko { 354eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 355eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 356eda6500aSJiri Pirko q->consumer_counter + q->count); 357eda6500aSJiri Pirko } 358eda6500aSJiri Pirko 359eda6500aSJiri Pirko static void 360eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 361eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 362eda6500aSJiri Pirko { 363eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 364eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 365eda6500aSJiri Pirko } 366eda6500aSJiri Pirko 367eda6500aSJiri Pirko static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 368eda6500aSJiri Pirko int page_index) 369eda6500aSJiri Pirko { 370eda6500aSJiri Pirko return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 371eda6500aSJiri Pirko } 372eda6500aSJiri Pirko 373eda6500aSJiri Pirko static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 374eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 375eda6500aSJiri Pirko { 376eda6500aSJiri Pirko int i; 377eda6500aSJiri Pirko int err; 378eda6500aSJiri Pirko 379eda6500aSJiri Pirko q->producer_counter = 0; 380eda6500aSJiri Pirko q->consumer_counter = 0; 381eda6500aSJiri Pirko 382eda6500aSJiri Pirko /* Set CQ of same number of this SDQ. */ 383eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 384eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 7); 385eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 386eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 387eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 388eda6500aSJiri Pirko 389eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 390eda6500aSJiri Pirko } 391eda6500aSJiri Pirko 392eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 393eda6500aSJiri Pirko if (err) 394eda6500aSJiri Pirko return err; 395eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 396eda6500aSJiri Pirko return 0; 397eda6500aSJiri Pirko } 398eda6500aSJiri Pirko 399eda6500aSJiri Pirko static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 400eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 401eda6500aSJiri Pirko { 402eda6500aSJiri Pirko mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 403eda6500aSJiri Pirko } 404eda6500aSJiri Pirko 405eda6500aSJiri Pirko static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data) 406eda6500aSJiri Pirko { 407eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 408eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 409eda6500aSJiri Pirko int i; 410eda6500aSJiri Pirko static const char hdr[] = 411eda6500aSJiri Pirko "NUM PROD_COUNT CONS_COUNT COUNT\n"; 412eda6500aSJiri Pirko 413eda6500aSJiri Pirko seq_printf(file, hdr); 414eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) { 415eda6500aSJiri Pirko q = mlxsw_pci_sdq_get(mlxsw_pci, i); 416eda6500aSJiri Pirko spin_lock_bh(&q->lock); 417eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %5d\n", 418eda6500aSJiri Pirko i, q->producer_counter, q->consumer_counter, 419eda6500aSJiri Pirko q->count); 420eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 421eda6500aSJiri Pirko } 422eda6500aSJiri Pirko return 0; 423eda6500aSJiri Pirko } 424eda6500aSJiri Pirko 425eda6500aSJiri Pirko static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 426eda6500aSJiri Pirko int index, char *frag_data, size_t frag_len, 427eda6500aSJiri Pirko int direction) 428eda6500aSJiri Pirko { 429eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 430eda6500aSJiri Pirko dma_addr_t mapaddr; 431eda6500aSJiri Pirko 432eda6500aSJiri Pirko mapaddr = pci_map_single(pdev, frag_data, frag_len, direction); 433eda6500aSJiri Pirko if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) { 434eda6500aSJiri Pirko if (net_ratelimit()) 435eda6500aSJiri Pirko dev_err(&pdev->dev, "failed to dma map tx frag\n"); 436eda6500aSJiri Pirko return -EIO; 437eda6500aSJiri Pirko } 438eda6500aSJiri Pirko mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 439eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 440eda6500aSJiri Pirko return 0; 441eda6500aSJiri Pirko } 442eda6500aSJiri Pirko 443eda6500aSJiri Pirko static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 444eda6500aSJiri Pirko int index, int direction) 445eda6500aSJiri Pirko { 446eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 447eda6500aSJiri Pirko size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 448eda6500aSJiri Pirko dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 449eda6500aSJiri Pirko 450eda6500aSJiri Pirko if (!frag_len) 451eda6500aSJiri Pirko return; 452eda6500aSJiri Pirko pci_unmap_single(pdev, mapaddr, frag_len, direction); 453eda6500aSJiri Pirko } 454eda6500aSJiri Pirko 455eda6500aSJiri Pirko static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 456eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 457eda6500aSJiri Pirko { 458eda6500aSJiri Pirko size_t buf_len = MLXSW_PORT_MAX_MTU; 459eda6500aSJiri Pirko char *wqe = elem_info->elem; 460eda6500aSJiri Pirko struct sk_buff *skb; 461eda6500aSJiri Pirko int err; 462eda6500aSJiri Pirko 463eda6500aSJiri Pirko elem_info->u.rdq.skb = NULL; 464eda6500aSJiri Pirko skb = netdev_alloc_skb_ip_align(NULL, buf_len); 465eda6500aSJiri Pirko if (!skb) 466eda6500aSJiri Pirko return -ENOMEM; 467eda6500aSJiri Pirko 468eda6500aSJiri Pirko /* Assume that wqe was previously zeroed. */ 469eda6500aSJiri Pirko 470eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 471eda6500aSJiri Pirko buf_len, DMA_FROM_DEVICE); 472eda6500aSJiri Pirko if (err) 473eda6500aSJiri Pirko goto err_frag_map; 474eda6500aSJiri Pirko 475eda6500aSJiri Pirko elem_info->u.rdq.skb = skb; 476eda6500aSJiri Pirko return 0; 477eda6500aSJiri Pirko 478eda6500aSJiri Pirko err_frag_map: 479eda6500aSJiri Pirko dev_kfree_skb_any(skb); 480eda6500aSJiri Pirko return err; 481eda6500aSJiri Pirko } 482eda6500aSJiri Pirko 483eda6500aSJiri Pirko static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 484eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 485eda6500aSJiri Pirko { 486eda6500aSJiri Pirko struct sk_buff *skb; 487eda6500aSJiri Pirko char *wqe; 488eda6500aSJiri Pirko 489eda6500aSJiri Pirko skb = elem_info->u.rdq.skb; 490eda6500aSJiri Pirko wqe = elem_info->elem; 491eda6500aSJiri Pirko 492eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 493eda6500aSJiri Pirko dev_kfree_skb_any(skb); 494eda6500aSJiri Pirko } 495eda6500aSJiri Pirko 496eda6500aSJiri Pirko static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 497eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 498eda6500aSJiri Pirko { 499eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 500424e1114SJiri Pirko u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 501eda6500aSJiri Pirko int i; 502eda6500aSJiri Pirko int err; 503eda6500aSJiri Pirko 504eda6500aSJiri Pirko q->producer_counter = 0; 505eda6500aSJiri Pirko q->consumer_counter = 0; 506eda6500aSJiri Pirko 507eda6500aSJiri Pirko /* Set CQ of same number of this RDQ with base 508424e1114SJiri Pirko * above SDQ count as the lower ones are assigned to SDQs. 509eda6500aSJiri Pirko */ 510424e1114SJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 511eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 512eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 513eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 514eda6500aSJiri Pirko 515eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 516eda6500aSJiri Pirko } 517eda6500aSJiri Pirko 518eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 519eda6500aSJiri Pirko if (err) 520eda6500aSJiri Pirko return err; 521eda6500aSJiri Pirko 522eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 523eda6500aSJiri Pirko 524eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 525eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 526eda6500aSJiri Pirko BUG_ON(!elem_info); 527eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 528eda6500aSJiri Pirko if (err) 529eda6500aSJiri Pirko goto rollback; 530eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 531eda6500aSJiri Pirko q->producer_counter++; 532eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 533eda6500aSJiri Pirko } 534eda6500aSJiri Pirko 535eda6500aSJiri Pirko return 0; 536eda6500aSJiri Pirko 537eda6500aSJiri Pirko rollback: 538eda6500aSJiri Pirko for (i--; i >= 0; i--) { 539eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 540eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 541eda6500aSJiri Pirko } 542eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 543eda6500aSJiri Pirko 544eda6500aSJiri Pirko return err; 545eda6500aSJiri Pirko } 546eda6500aSJiri Pirko 547eda6500aSJiri Pirko static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 548eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 549eda6500aSJiri Pirko { 550eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 551eda6500aSJiri Pirko int i; 552eda6500aSJiri Pirko 553eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 554eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 555eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 556eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 557eda6500aSJiri Pirko } 558eda6500aSJiri Pirko } 559eda6500aSJiri Pirko 560eda6500aSJiri Pirko static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data) 561eda6500aSJiri Pirko { 562eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 563eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 564eda6500aSJiri Pirko int i; 565eda6500aSJiri Pirko static const char hdr[] = 566eda6500aSJiri Pirko "NUM PROD_COUNT CONS_COUNT COUNT\n"; 567eda6500aSJiri Pirko 568eda6500aSJiri Pirko seq_printf(file, hdr); 569eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) { 570eda6500aSJiri Pirko q = mlxsw_pci_rdq_get(mlxsw_pci, i); 571eda6500aSJiri Pirko spin_lock_bh(&q->lock); 572eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %5d\n", 573eda6500aSJiri Pirko i, q->producer_counter, q->consumer_counter, 574eda6500aSJiri Pirko q->count); 575eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 576eda6500aSJiri Pirko } 577eda6500aSJiri Pirko return 0; 578eda6500aSJiri Pirko } 579eda6500aSJiri Pirko 580eda6500aSJiri Pirko static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 581eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 582eda6500aSJiri Pirko { 583eda6500aSJiri Pirko int i; 584eda6500aSJiri Pirko int err; 585eda6500aSJiri Pirko 586eda6500aSJiri Pirko q->consumer_counter = 0; 587eda6500aSJiri Pirko 588eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 589eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 590eda6500aSJiri Pirko 591eda6500aSJiri Pirko mlxsw_pci_cqe_owner_set(elem, 1); 592eda6500aSJiri Pirko } 593eda6500aSJiri Pirko 594eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */ 595eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 596eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0); 597eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 598eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 599eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 600eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 601eda6500aSJiri Pirko 602eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 603eda6500aSJiri Pirko } 604eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 605eda6500aSJiri Pirko if (err) 606eda6500aSJiri Pirko return err; 607eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 608eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 609eda6500aSJiri Pirko return 0; 610eda6500aSJiri Pirko } 611eda6500aSJiri Pirko 612eda6500aSJiri Pirko static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 613eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 614eda6500aSJiri Pirko { 615eda6500aSJiri Pirko mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 616eda6500aSJiri Pirko } 617eda6500aSJiri Pirko 618eda6500aSJiri Pirko static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data) 619eda6500aSJiri Pirko { 620eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 621eda6500aSJiri Pirko 622eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 623eda6500aSJiri Pirko int i; 624eda6500aSJiri Pirko static const char hdr[] = 625eda6500aSJiri Pirko "NUM CONS_INDEX SDQ_COUNT RDQ_COUNT COUNT\n"; 626eda6500aSJiri Pirko 627eda6500aSJiri Pirko seq_printf(file, hdr); 628eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) { 629eda6500aSJiri Pirko q = mlxsw_pci_cq_get(mlxsw_pci, i); 630eda6500aSJiri Pirko spin_lock_bh(&q->lock); 631eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %10d %5d\n", 632eda6500aSJiri Pirko i, q->consumer_counter, q->u.cq.comp_sdq_count, 633eda6500aSJiri Pirko q->u.cq.comp_rdq_count, q->count); 634eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 635eda6500aSJiri Pirko } 636eda6500aSJiri Pirko return 0; 637eda6500aSJiri Pirko } 638eda6500aSJiri Pirko 639eda6500aSJiri Pirko static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 640eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 641eda6500aSJiri Pirko u16 consumer_counter_limit, 642eda6500aSJiri Pirko char *cqe) 643eda6500aSJiri Pirko { 644eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 645eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 646eda6500aSJiri Pirko char *wqe; 647eda6500aSJiri Pirko struct sk_buff *skb; 648eda6500aSJiri Pirko int i; 649eda6500aSJiri Pirko 650eda6500aSJiri Pirko spin_lock(&q->lock); 651eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 652eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 653eda6500aSJiri Pirko wqe = elem_info->elem; 654eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 655eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 656eda6500aSJiri Pirko dev_kfree_skb_any(skb); 657eda6500aSJiri Pirko elem_info->u.sdq.skb = NULL; 658eda6500aSJiri Pirko 659eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 660eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 661eda6500aSJiri Pirko spin_unlock(&q->lock); 662eda6500aSJiri Pirko } 663eda6500aSJiri Pirko 664eda6500aSJiri Pirko static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 665eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 666eda6500aSJiri Pirko u16 consumer_counter_limit, 667eda6500aSJiri Pirko char *cqe) 668eda6500aSJiri Pirko { 669eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 670eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 671eda6500aSJiri Pirko char *wqe; 672eda6500aSJiri Pirko struct sk_buff *skb; 673eda6500aSJiri Pirko struct mlxsw_rx_info rx_info; 6747b7b9cffSJiri Pirko u16 byte_count; 675eda6500aSJiri Pirko int err; 676eda6500aSJiri Pirko 677eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 678eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 679eda6500aSJiri Pirko if (!skb) 680eda6500aSJiri Pirko return; 681eda6500aSJiri Pirko wqe = elem_info->elem; 682eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 683eda6500aSJiri Pirko 684eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 685eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 686eda6500aSJiri Pirko 687eda6500aSJiri Pirko /* We do not support lag now */ 688eda6500aSJiri Pirko if (mlxsw_pci_cqe_lag_get(cqe)) 689eda6500aSJiri Pirko goto drop; 690eda6500aSJiri Pirko 691eda6500aSJiri Pirko rx_info.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 692eda6500aSJiri Pirko rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 693eda6500aSJiri Pirko 6947b7b9cffSJiri Pirko byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 6957b7b9cffSJiri Pirko if (mlxsw_pci_cqe_crc_get(cqe)) 6967b7b9cffSJiri Pirko byte_count -= ETH_FCS_LEN; 6977b7b9cffSJiri Pirko skb_put(skb, byte_count); 698eda6500aSJiri Pirko mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 699eda6500aSJiri Pirko 700eda6500aSJiri Pirko put_new_skb: 701eda6500aSJiri Pirko memset(wqe, 0, q->elem_size); 702eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 703eda6500aSJiri Pirko if (err && net_ratelimit()) 704eda6500aSJiri Pirko dev_dbg(&pdev->dev, "Failed to alloc skb for RDQ\n"); 705eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 706eda6500aSJiri Pirko q->producer_counter++; 707eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 708eda6500aSJiri Pirko return; 709eda6500aSJiri Pirko 710eda6500aSJiri Pirko drop: 711eda6500aSJiri Pirko dev_kfree_skb_any(skb); 712eda6500aSJiri Pirko goto put_new_skb; 713eda6500aSJiri Pirko } 714eda6500aSJiri Pirko 715eda6500aSJiri Pirko static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 716eda6500aSJiri Pirko { 717eda6500aSJiri Pirko return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get); 718eda6500aSJiri Pirko } 719eda6500aSJiri Pirko 720eda6500aSJiri Pirko static void mlxsw_pci_cq_tasklet(unsigned long data) 721eda6500aSJiri Pirko { 722eda6500aSJiri Pirko struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 723eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 724eda6500aSJiri Pirko char *cqe; 725eda6500aSJiri Pirko int items = 0; 726eda6500aSJiri Pirko int credits = q->count >> 1; 727eda6500aSJiri Pirko 728eda6500aSJiri Pirko while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 729eda6500aSJiri Pirko u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 730eda6500aSJiri Pirko u8 sendq = mlxsw_pci_cqe_sr_get(cqe); 731eda6500aSJiri Pirko u8 dqn = mlxsw_pci_cqe_dqn_get(cqe); 732eda6500aSJiri Pirko 733eda6500aSJiri Pirko if (sendq) { 734eda6500aSJiri Pirko struct mlxsw_pci_queue *sdq; 735eda6500aSJiri Pirko 736eda6500aSJiri Pirko sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 737eda6500aSJiri Pirko mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 738eda6500aSJiri Pirko wqe_counter, cqe); 739eda6500aSJiri Pirko q->u.cq.comp_sdq_count++; 740eda6500aSJiri Pirko } else { 741eda6500aSJiri Pirko struct mlxsw_pci_queue *rdq; 742eda6500aSJiri Pirko 743eda6500aSJiri Pirko rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 744eda6500aSJiri Pirko mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 745eda6500aSJiri Pirko wqe_counter, cqe); 746eda6500aSJiri Pirko q->u.cq.comp_rdq_count++; 747eda6500aSJiri Pirko } 748eda6500aSJiri Pirko if (++items == credits) 749eda6500aSJiri Pirko break; 750eda6500aSJiri Pirko } 751eda6500aSJiri Pirko if (items) { 752eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 753eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 754eda6500aSJiri Pirko } 755eda6500aSJiri Pirko } 756eda6500aSJiri Pirko 757eda6500aSJiri Pirko static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 758eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 759eda6500aSJiri Pirko { 760eda6500aSJiri Pirko int i; 761eda6500aSJiri Pirko int err; 762eda6500aSJiri Pirko 763eda6500aSJiri Pirko q->consumer_counter = 0; 764eda6500aSJiri Pirko 765eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 766eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 767eda6500aSJiri Pirko 768eda6500aSJiri Pirko mlxsw_pci_eqe_owner_set(elem, 1); 769eda6500aSJiri Pirko } 770eda6500aSJiri Pirko 771eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 772eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0); 773eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 774eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 775eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 776eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 777eda6500aSJiri Pirko 778eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 779eda6500aSJiri Pirko } 780eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 781eda6500aSJiri Pirko if (err) 782eda6500aSJiri Pirko return err; 783eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 784eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 785eda6500aSJiri Pirko return 0; 786eda6500aSJiri Pirko } 787eda6500aSJiri Pirko 788eda6500aSJiri Pirko static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 789eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 790eda6500aSJiri Pirko { 791eda6500aSJiri Pirko mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 792eda6500aSJiri Pirko } 793eda6500aSJiri Pirko 794eda6500aSJiri Pirko static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data) 795eda6500aSJiri Pirko { 796eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private); 797eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 798eda6500aSJiri Pirko int i; 799eda6500aSJiri Pirko static const char hdr[] = 800eda6500aSJiri Pirko "NUM CONS_COUNT EV_CMD EV_COMP EV_OTHER COUNT\n"; 801eda6500aSJiri Pirko 802eda6500aSJiri Pirko seq_printf(file, hdr); 803eda6500aSJiri Pirko for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) { 804eda6500aSJiri Pirko q = mlxsw_pci_eq_get(mlxsw_pci, i); 805eda6500aSJiri Pirko spin_lock_bh(&q->lock); 806eda6500aSJiri Pirko seq_printf(file, "%3d %10d %10d %10d %10d %5d\n", 807eda6500aSJiri Pirko i, q->consumer_counter, q->u.eq.ev_cmd_count, 808eda6500aSJiri Pirko q->u.eq.ev_comp_count, q->u.eq.ev_other_count, 809eda6500aSJiri Pirko q->count); 810eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 811eda6500aSJiri Pirko } 812eda6500aSJiri Pirko return 0; 813eda6500aSJiri Pirko } 814eda6500aSJiri Pirko 815eda6500aSJiri Pirko static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 816eda6500aSJiri Pirko { 817eda6500aSJiri Pirko mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 818eda6500aSJiri Pirko mlxsw_pci->cmd.comp.out_param = 819eda6500aSJiri Pirko ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 820eda6500aSJiri Pirko mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 821eda6500aSJiri Pirko mlxsw_pci->cmd.wait_done = true; 822eda6500aSJiri Pirko wake_up(&mlxsw_pci->cmd.wait); 823eda6500aSJiri Pirko } 824eda6500aSJiri Pirko 825eda6500aSJiri Pirko static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 826eda6500aSJiri Pirko { 827eda6500aSJiri Pirko return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get); 828eda6500aSJiri Pirko } 829eda6500aSJiri Pirko 830eda6500aSJiri Pirko static void mlxsw_pci_eq_tasklet(unsigned long data) 831eda6500aSJiri Pirko { 832eda6500aSJiri Pirko struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 833eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 834e4c870b1SJiri Pirko u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 835e4c870b1SJiri Pirko unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 836eda6500aSJiri Pirko char *eqe; 837eda6500aSJiri Pirko u8 cqn; 838eda6500aSJiri Pirko bool cq_handle = false; 839eda6500aSJiri Pirko int items = 0; 840eda6500aSJiri Pirko int credits = q->count >> 1; 841eda6500aSJiri Pirko 842eda6500aSJiri Pirko memset(&active_cqns, 0, sizeof(active_cqns)); 843eda6500aSJiri Pirko 844eda6500aSJiri Pirko while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 845eda6500aSJiri Pirko u8 event_type = mlxsw_pci_eqe_event_type_get(eqe); 846eda6500aSJiri Pirko 847eda6500aSJiri Pirko switch (event_type) { 848eda6500aSJiri Pirko case MLXSW_PCI_EQE_EVENT_TYPE_CMD: 849eda6500aSJiri Pirko mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 850eda6500aSJiri Pirko q->u.eq.ev_cmd_count++; 851eda6500aSJiri Pirko break; 852eda6500aSJiri Pirko case MLXSW_PCI_EQE_EVENT_TYPE_COMP: 853eda6500aSJiri Pirko cqn = mlxsw_pci_eqe_cqn_get(eqe); 854eda6500aSJiri Pirko set_bit(cqn, active_cqns); 855eda6500aSJiri Pirko cq_handle = true; 856eda6500aSJiri Pirko q->u.eq.ev_comp_count++; 857eda6500aSJiri Pirko break; 858eda6500aSJiri Pirko default: 859eda6500aSJiri Pirko q->u.eq.ev_other_count++; 860eda6500aSJiri Pirko } 861eda6500aSJiri Pirko if (++items == credits) 862eda6500aSJiri Pirko break; 863eda6500aSJiri Pirko } 864eda6500aSJiri Pirko if (items) { 865eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 866eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 867eda6500aSJiri Pirko } 868eda6500aSJiri Pirko 869eda6500aSJiri Pirko if (!cq_handle) 870eda6500aSJiri Pirko return; 871e4c870b1SJiri Pirko for_each_set_bit(cqn, active_cqns, cq_count) { 872eda6500aSJiri Pirko q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 873eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 874eda6500aSJiri Pirko } 875eda6500aSJiri Pirko } 876eda6500aSJiri Pirko 877eda6500aSJiri Pirko struct mlxsw_pci_queue_ops { 878eda6500aSJiri Pirko const char *name; 879eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 880eda6500aSJiri Pirko int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 881eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 882eda6500aSJiri Pirko void (*fini)(struct mlxsw_pci *mlxsw_pci, 883eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 884eda6500aSJiri Pirko void (*tasklet)(unsigned long data); 885eda6500aSJiri Pirko int (*dbg_read)(struct seq_file *s, void *data); 886eda6500aSJiri Pirko u16 elem_count; 887eda6500aSJiri Pirko u8 elem_size; 888eda6500aSJiri Pirko }; 889eda6500aSJiri Pirko 890eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 891eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 892eda6500aSJiri Pirko .init = mlxsw_pci_sdq_init, 893eda6500aSJiri Pirko .fini = mlxsw_pci_sdq_fini, 894eda6500aSJiri Pirko .dbg_read = mlxsw_pci_sdq_dbg_read, 895eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 896eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE, 897eda6500aSJiri Pirko }; 898eda6500aSJiri Pirko 899eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 900eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 901eda6500aSJiri Pirko .init = mlxsw_pci_rdq_init, 902eda6500aSJiri Pirko .fini = mlxsw_pci_rdq_fini, 903eda6500aSJiri Pirko .dbg_read = mlxsw_pci_rdq_dbg_read, 904eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 905eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE 906eda6500aSJiri Pirko }; 907eda6500aSJiri Pirko 908eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 909eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_CQ, 910eda6500aSJiri Pirko .init = mlxsw_pci_cq_init, 911eda6500aSJiri Pirko .fini = mlxsw_pci_cq_fini, 912eda6500aSJiri Pirko .tasklet = mlxsw_pci_cq_tasklet, 913eda6500aSJiri Pirko .dbg_read = mlxsw_pci_cq_dbg_read, 914eda6500aSJiri Pirko .elem_count = MLXSW_PCI_CQE_COUNT, 915eda6500aSJiri Pirko .elem_size = MLXSW_PCI_CQE_SIZE 916eda6500aSJiri Pirko }; 917eda6500aSJiri Pirko 918eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 919eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_EQ, 920eda6500aSJiri Pirko .init = mlxsw_pci_eq_init, 921eda6500aSJiri Pirko .fini = mlxsw_pci_eq_fini, 922eda6500aSJiri Pirko .tasklet = mlxsw_pci_eq_tasklet, 923eda6500aSJiri Pirko .dbg_read = mlxsw_pci_eq_dbg_read, 924eda6500aSJiri Pirko .elem_count = MLXSW_PCI_EQE_COUNT, 925eda6500aSJiri Pirko .elem_size = MLXSW_PCI_EQE_SIZE 926eda6500aSJiri Pirko }; 927eda6500aSJiri Pirko 928eda6500aSJiri Pirko static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 929eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 930eda6500aSJiri Pirko struct mlxsw_pci_queue *q, u8 q_num) 931eda6500aSJiri Pirko { 932eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 933eda6500aSJiri Pirko int i; 934eda6500aSJiri Pirko int err; 935eda6500aSJiri Pirko 936eda6500aSJiri Pirko spin_lock_init(&q->lock); 937eda6500aSJiri Pirko q->num = q_num; 938eda6500aSJiri Pirko q->count = q_ops->elem_count; 939eda6500aSJiri Pirko q->elem_size = q_ops->elem_size; 940eda6500aSJiri Pirko q->type = q_ops->type; 941eda6500aSJiri Pirko q->pci = mlxsw_pci; 942eda6500aSJiri Pirko 943eda6500aSJiri Pirko if (q_ops->tasklet) 944eda6500aSJiri Pirko tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q); 945eda6500aSJiri Pirko 946eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_AQ_SIZE; 947eda6500aSJiri Pirko mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 948eda6500aSJiri Pirko mem_item->size, 949eda6500aSJiri Pirko &mem_item->mapaddr); 950eda6500aSJiri Pirko if (!mem_item->buf) 951eda6500aSJiri Pirko return -ENOMEM; 952eda6500aSJiri Pirko memset(mem_item->buf, 0, mem_item->size); 953eda6500aSJiri Pirko 954eda6500aSJiri Pirko q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 955eda6500aSJiri Pirko if (!q->elem_info) { 956eda6500aSJiri Pirko err = -ENOMEM; 957eda6500aSJiri Pirko goto err_elem_info_alloc; 958eda6500aSJiri Pirko } 959eda6500aSJiri Pirko 960eda6500aSJiri Pirko /* Initialize dma mapped elements info elem_info for 961eda6500aSJiri Pirko * future easy access. 962eda6500aSJiri Pirko */ 963eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 964eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 965eda6500aSJiri Pirko 966eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 967eda6500aSJiri Pirko elem_info->elem = 968eda6500aSJiri Pirko __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i); 969eda6500aSJiri Pirko } 970eda6500aSJiri Pirko 971eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 972eda6500aSJiri Pirko err = q_ops->init(mlxsw_pci, mbox, q); 973eda6500aSJiri Pirko if (err) 974eda6500aSJiri Pirko goto err_q_ops_init; 975eda6500aSJiri Pirko return 0; 976eda6500aSJiri Pirko 977eda6500aSJiri Pirko err_q_ops_init: 978eda6500aSJiri Pirko kfree(q->elem_info); 979eda6500aSJiri Pirko err_elem_info_alloc: 980eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 981eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 982eda6500aSJiri Pirko return err; 983eda6500aSJiri Pirko } 984eda6500aSJiri Pirko 985eda6500aSJiri Pirko static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 986eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 987eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 988eda6500aSJiri Pirko { 989eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 990eda6500aSJiri Pirko 991eda6500aSJiri Pirko q_ops->fini(mlxsw_pci, q); 992eda6500aSJiri Pirko kfree(q->elem_info); 993eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 994eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 995eda6500aSJiri Pirko } 996eda6500aSJiri Pirko 997eda6500aSJiri Pirko static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 998eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 999eda6500aSJiri Pirko u8 num_qs) 1000eda6500aSJiri Pirko { 1001eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1002eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 1003eda6500aSJiri Pirko char tmp[16]; 1004eda6500aSJiri Pirko int i; 1005eda6500aSJiri Pirko int err; 1006eda6500aSJiri Pirko 1007eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1008eda6500aSJiri Pirko queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 1009eda6500aSJiri Pirko if (!queue_group->q) 1010eda6500aSJiri Pirko return -ENOMEM; 1011eda6500aSJiri Pirko 1012eda6500aSJiri Pirko for (i = 0; i < num_qs; i++) { 1013eda6500aSJiri Pirko err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 1014eda6500aSJiri Pirko &queue_group->q[i], i); 1015eda6500aSJiri Pirko if (err) 1016eda6500aSJiri Pirko goto err_queue_init; 1017eda6500aSJiri Pirko } 1018eda6500aSJiri Pirko queue_group->count = num_qs; 1019eda6500aSJiri Pirko 1020eda6500aSJiri Pirko sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type)); 1021eda6500aSJiri Pirko debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir, 1022eda6500aSJiri Pirko q_ops->dbg_read); 1023eda6500aSJiri Pirko 1024eda6500aSJiri Pirko return 0; 1025eda6500aSJiri Pirko 1026eda6500aSJiri Pirko err_queue_init: 1027eda6500aSJiri Pirko for (i--; i >= 0; i--) 1028eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1029eda6500aSJiri Pirko kfree(queue_group->q); 1030eda6500aSJiri Pirko return err; 1031eda6500aSJiri Pirko } 1032eda6500aSJiri Pirko 1033eda6500aSJiri Pirko static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 1034eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops) 1035eda6500aSJiri Pirko { 1036eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 1037eda6500aSJiri Pirko int i; 1038eda6500aSJiri Pirko 1039eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1040eda6500aSJiri Pirko for (i = 0; i < queue_group->count; i++) 1041eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1042eda6500aSJiri Pirko kfree(queue_group->q); 1043eda6500aSJiri Pirko } 1044eda6500aSJiri Pirko 1045eda6500aSJiri Pirko static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1046eda6500aSJiri Pirko { 1047eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1048eda6500aSJiri Pirko u8 num_sdqs; 1049eda6500aSJiri Pirko u8 sdq_log2sz; 1050eda6500aSJiri Pirko u8 num_rdqs; 1051eda6500aSJiri Pirko u8 rdq_log2sz; 1052eda6500aSJiri Pirko u8 num_cqs; 1053eda6500aSJiri Pirko u8 cq_log2sz; 1054eda6500aSJiri Pirko u8 num_eqs; 1055eda6500aSJiri Pirko u8 eq_log2sz; 1056eda6500aSJiri Pirko int err; 1057eda6500aSJiri Pirko 1058eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1059eda6500aSJiri Pirko err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1060eda6500aSJiri Pirko if (err) 1061eda6500aSJiri Pirko return err; 1062eda6500aSJiri Pirko 1063eda6500aSJiri Pirko num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1064eda6500aSJiri Pirko sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1065eda6500aSJiri Pirko num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1066eda6500aSJiri Pirko rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1067eda6500aSJiri Pirko num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1068eda6500aSJiri Pirko cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1069eda6500aSJiri Pirko num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1070eda6500aSJiri Pirko eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1071eda6500aSJiri Pirko 1072c85c3882SJiri Pirko if (num_sdqs + num_rdqs > num_cqs || 1073e4c870b1SJiri Pirko num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 1074eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of queues\n"); 1075eda6500aSJiri Pirko return -EINVAL; 1076eda6500aSJiri Pirko } 1077eda6500aSJiri Pirko 1078eda6500aSJiri Pirko if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1079eda6500aSJiri Pirko (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1080eda6500aSJiri Pirko (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) || 1081eda6500aSJiri Pirko (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1082eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1083eda6500aSJiri Pirko return -EINVAL; 1084eda6500aSJiri Pirko } 1085eda6500aSJiri Pirko 1086eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1087eda6500aSJiri Pirko num_eqs); 1088eda6500aSJiri Pirko if (err) { 1089eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1090eda6500aSJiri Pirko return err; 1091eda6500aSJiri Pirko } 1092eda6500aSJiri Pirko 1093eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1094eda6500aSJiri Pirko num_cqs); 1095eda6500aSJiri Pirko if (err) { 1096eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1097eda6500aSJiri Pirko goto err_cqs_init; 1098eda6500aSJiri Pirko } 1099eda6500aSJiri Pirko 1100eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1101eda6500aSJiri Pirko num_sdqs); 1102eda6500aSJiri Pirko if (err) { 1103eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1104eda6500aSJiri Pirko goto err_sdqs_init; 1105eda6500aSJiri Pirko } 1106eda6500aSJiri Pirko 1107eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1108eda6500aSJiri Pirko num_rdqs); 1109eda6500aSJiri Pirko if (err) { 1110eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1111eda6500aSJiri Pirko goto err_rdqs_init; 1112eda6500aSJiri Pirko } 1113eda6500aSJiri Pirko 1114eda6500aSJiri Pirko /* We have to poll in command interface until queues are initialized */ 1115eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = true; 1116eda6500aSJiri Pirko return 0; 1117eda6500aSJiri Pirko 1118eda6500aSJiri Pirko err_rdqs_init: 1119eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1120eda6500aSJiri Pirko err_sdqs_init: 1121eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1122eda6500aSJiri Pirko err_cqs_init: 1123eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1124eda6500aSJiri Pirko return err; 1125eda6500aSJiri Pirko } 1126eda6500aSJiri Pirko 1127eda6500aSJiri Pirko static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1128eda6500aSJiri Pirko { 1129eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = false; 1130eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1131eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1132eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1133eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1134eda6500aSJiri Pirko } 1135eda6500aSJiri Pirko 1136eda6500aSJiri Pirko static void 1137eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1138eda6500aSJiri Pirko char *mbox, int index, 1139eda6500aSJiri Pirko const struct mlxsw_swid_config *swid) 1140eda6500aSJiri Pirko { 1141eda6500aSJiri Pirko u8 mask = 0; 1142eda6500aSJiri Pirko 1143eda6500aSJiri Pirko if (swid->used_type) { 1144eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1145eda6500aSJiri Pirko mbox, index, swid->type); 1146eda6500aSJiri Pirko mask |= 1; 1147eda6500aSJiri Pirko } 1148eda6500aSJiri Pirko if (swid->used_properties) { 1149eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1150eda6500aSJiri Pirko mbox, index, swid->properties); 1151eda6500aSJiri Pirko mask |= 2; 1152eda6500aSJiri Pirko } 1153eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1154eda6500aSJiri Pirko } 1155eda6500aSJiri Pirko 1156eda6500aSJiri Pirko static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1157eda6500aSJiri Pirko const struct mlxsw_config_profile *profile) 1158eda6500aSJiri Pirko { 1159eda6500aSJiri Pirko int i; 1160eda6500aSJiri Pirko 1161eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1162eda6500aSJiri Pirko 1163eda6500aSJiri Pirko if (profile->used_max_vepa_channels) { 1164eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1165eda6500aSJiri Pirko mbox, 1); 1166eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1167eda6500aSJiri Pirko mbox, profile->max_vepa_channels); 1168eda6500aSJiri Pirko } 1169eda6500aSJiri Pirko if (profile->used_max_lag) { 1170eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_lag_set( 1171eda6500aSJiri Pirko mbox, 1); 1172eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_lag_set( 1173eda6500aSJiri Pirko mbox, profile->max_lag); 1174eda6500aSJiri Pirko } 1175eda6500aSJiri Pirko if (profile->used_max_port_per_lag) { 1176eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set( 1177eda6500aSJiri Pirko mbox, 1); 1178eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_port_per_lag_set( 1179eda6500aSJiri Pirko mbox, profile->max_port_per_lag); 1180eda6500aSJiri Pirko } 1181eda6500aSJiri Pirko if (profile->used_max_mid) { 1182eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1183eda6500aSJiri Pirko mbox, 1); 1184eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_mid_set( 1185eda6500aSJiri Pirko mbox, profile->max_mid); 1186eda6500aSJiri Pirko } 1187eda6500aSJiri Pirko if (profile->used_max_pgt) { 1188eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1189eda6500aSJiri Pirko mbox, 1); 1190eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pgt_set( 1191eda6500aSJiri Pirko mbox, profile->max_pgt); 1192eda6500aSJiri Pirko } 1193eda6500aSJiri Pirko if (profile->used_max_system_port) { 1194eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1195eda6500aSJiri Pirko mbox, 1); 1196eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_system_port_set( 1197eda6500aSJiri Pirko mbox, profile->max_system_port); 1198eda6500aSJiri Pirko } 1199eda6500aSJiri Pirko if (profile->used_max_vlan_groups) { 1200eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1201eda6500aSJiri Pirko mbox, 1); 1202eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1203eda6500aSJiri Pirko mbox, profile->max_vlan_groups); 1204eda6500aSJiri Pirko } 1205eda6500aSJiri Pirko if (profile->used_max_regions) { 1206eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1207eda6500aSJiri Pirko mbox, 1); 1208eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_regions_set( 1209eda6500aSJiri Pirko mbox, profile->max_regions); 1210eda6500aSJiri Pirko } 1211eda6500aSJiri Pirko if (profile->used_flood_tables) { 1212eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1213eda6500aSJiri Pirko mbox, 1); 1214eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1215eda6500aSJiri Pirko mbox, profile->max_flood_tables); 1216eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1217eda6500aSJiri Pirko mbox, profile->max_vid_flood_tables); 1218eda6500aSJiri Pirko } 1219eda6500aSJiri Pirko if (profile->used_flood_mode) { 1220eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1221eda6500aSJiri Pirko mbox, 1); 1222eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_flood_mode_set( 1223eda6500aSJiri Pirko mbox, profile->flood_mode); 1224eda6500aSJiri Pirko } 1225eda6500aSJiri Pirko if (profile->used_max_ib_mc) { 1226eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1227eda6500aSJiri Pirko mbox, 1); 1228eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1229eda6500aSJiri Pirko mbox, profile->max_ib_mc); 1230eda6500aSJiri Pirko } 1231eda6500aSJiri Pirko if (profile->used_max_pkey) { 1232eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1233eda6500aSJiri Pirko mbox, 1); 1234eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pkey_set( 1235eda6500aSJiri Pirko mbox, profile->max_pkey); 1236eda6500aSJiri Pirko } 1237eda6500aSJiri Pirko if (profile->used_ar_sec) { 1238eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1239eda6500aSJiri Pirko mbox, 1); 1240eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_ar_sec_set( 1241eda6500aSJiri Pirko mbox, profile->ar_sec); 1242eda6500aSJiri Pirko } 1243eda6500aSJiri Pirko if (profile->used_adaptive_routing_group_cap) { 1244eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1245eda6500aSJiri Pirko mbox, 1); 1246eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1247eda6500aSJiri Pirko mbox, profile->adaptive_routing_group_cap); 1248eda6500aSJiri Pirko } 1249eda6500aSJiri Pirko 1250eda6500aSJiri Pirko for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1251eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1252eda6500aSJiri Pirko &profile->swid_config[i]); 1253eda6500aSJiri Pirko 1254eda6500aSJiri Pirko return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1255eda6500aSJiri Pirko } 1256eda6500aSJiri Pirko 1257eda6500aSJiri Pirko static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1258eda6500aSJiri Pirko { 1259eda6500aSJiri Pirko struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1260eda6500aSJiri Pirko int err; 1261eda6500aSJiri Pirko 1262eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1263eda6500aSJiri Pirko err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1264eda6500aSJiri Pirko if (err) 1265eda6500aSJiri Pirko return err; 1266eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1267eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1268eda6500aSJiri Pirko return 0; 1269eda6500aSJiri Pirko } 1270eda6500aSJiri Pirko 1271eda6500aSJiri Pirko static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1272eda6500aSJiri Pirko u16 num_pages) 1273eda6500aSJiri Pirko { 1274eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 12753e2206daSJiri Pirko int nent = 0; 1276eda6500aSJiri Pirko int i; 1277eda6500aSJiri Pirko int err; 1278eda6500aSJiri Pirko 1279eda6500aSJiri Pirko mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1280eda6500aSJiri Pirko GFP_KERNEL); 1281eda6500aSJiri Pirko if (!mlxsw_pci->fw_area.items) 1282eda6500aSJiri Pirko return -ENOMEM; 12833e2206daSJiri Pirko mlxsw_pci->fw_area.count = num_pages; 1284eda6500aSJiri Pirko 1285eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1286eda6500aSJiri Pirko for (i = 0; i < num_pages; i++) { 1287eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1288eda6500aSJiri Pirko 1289eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_PAGE_SIZE; 1290eda6500aSJiri Pirko mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 1291eda6500aSJiri Pirko mem_item->size, 1292eda6500aSJiri Pirko &mem_item->mapaddr); 1293eda6500aSJiri Pirko if (!mem_item->buf) { 1294eda6500aSJiri Pirko err = -ENOMEM; 1295eda6500aSJiri Pirko goto err_alloc; 1296eda6500aSJiri Pirko } 12973e2206daSJiri Pirko mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 12983e2206daSJiri Pirko mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 12993e2206daSJiri Pirko if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 13003e2206daSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1301eda6500aSJiri Pirko if (err) 1302eda6500aSJiri Pirko goto err_cmd_map_fa; 13033e2206daSJiri Pirko nent = 0; 13043e2206daSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 13053e2206daSJiri Pirko } 13063e2206daSJiri Pirko } 13073e2206daSJiri Pirko 13083e2206daSJiri Pirko if (nent) { 13093e2206daSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 13103e2206daSJiri Pirko if (err) 13113e2206daSJiri Pirko goto err_cmd_map_fa; 13123e2206daSJiri Pirko } 1313eda6500aSJiri Pirko 1314eda6500aSJiri Pirko return 0; 1315eda6500aSJiri Pirko 1316eda6500aSJiri Pirko err_cmd_map_fa: 1317eda6500aSJiri Pirko err_alloc: 1318eda6500aSJiri Pirko for (i--; i >= 0; i--) { 1319eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1320eda6500aSJiri Pirko 1321eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1322eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1323eda6500aSJiri Pirko } 1324eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1325eda6500aSJiri Pirko return err; 1326eda6500aSJiri Pirko } 1327eda6500aSJiri Pirko 1328eda6500aSJiri Pirko static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1329eda6500aSJiri Pirko { 1330eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 1331eda6500aSJiri Pirko int i; 1332eda6500aSJiri Pirko 1333eda6500aSJiri Pirko mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1334eda6500aSJiri Pirko 13353e2206daSJiri Pirko for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1336eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1337eda6500aSJiri Pirko 1338eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1339eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1340eda6500aSJiri Pirko } 1341eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1342eda6500aSJiri Pirko } 1343eda6500aSJiri Pirko 1344eda6500aSJiri Pirko static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1345eda6500aSJiri Pirko { 1346eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_id; 1347eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1348eda6500aSJiri Pirko int i; 1349eda6500aSJiri Pirko 1350eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1351eda6500aSJiri Pirko q = mlxsw_pci_eq_get(mlxsw_pci, i); 1352eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 1353eda6500aSJiri Pirko } 1354eda6500aSJiri Pirko return IRQ_HANDLED; 1355eda6500aSJiri Pirko } 1356eda6500aSJiri Pirko 13571e81779aSIdo Schimmel static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 13581e81779aSIdo Schimmel struct mlxsw_pci_mem_item *mbox) 13591e81779aSIdo Schimmel { 13601e81779aSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 13611e81779aSIdo Schimmel int err = 0; 13621e81779aSIdo Schimmel 13631e81779aSIdo Schimmel mbox->size = MLXSW_CMD_MBOX_SIZE; 13641e81779aSIdo Schimmel mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE, 13651e81779aSIdo Schimmel &mbox->mapaddr); 13661e81779aSIdo Schimmel if (!mbox->buf) { 13671e81779aSIdo Schimmel dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 13681e81779aSIdo Schimmel err = -ENOMEM; 13691e81779aSIdo Schimmel } 13701e81779aSIdo Schimmel 13711e81779aSIdo Schimmel return err; 13721e81779aSIdo Schimmel } 13731e81779aSIdo Schimmel 13741e81779aSIdo Schimmel static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 13751e81779aSIdo Schimmel struct mlxsw_pci_mem_item *mbox) 13761e81779aSIdo Schimmel { 13771e81779aSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 13781e81779aSIdo Schimmel 13791e81779aSIdo Schimmel pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 13801e81779aSIdo Schimmel mbox->mapaddr); 13811e81779aSIdo Schimmel } 13821e81779aSIdo Schimmel 1383eda6500aSJiri Pirko static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1384eda6500aSJiri Pirko const struct mlxsw_config_profile *profile) 1385eda6500aSJiri Pirko { 1386eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1387eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1388eda6500aSJiri Pirko char *mbox; 1389eda6500aSJiri Pirko u16 num_pages; 1390eda6500aSJiri Pirko int err; 1391eda6500aSJiri Pirko 1392eda6500aSJiri Pirko mutex_init(&mlxsw_pci->cmd.lock); 1393eda6500aSJiri Pirko init_waitqueue_head(&mlxsw_pci->cmd.wait); 1394eda6500aSJiri Pirko 1395eda6500aSJiri Pirko mlxsw_pci->core = mlxsw_core; 1396eda6500aSJiri Pirko 1397eda6500aSJiri Pirko mbox = mlxsw_cmd_mbox_alloc(); 1398eda6500aSJiri Pirko if (!mbox) 1399eda6500aSJiri Pirko return -ENOMEM; 14001e81779aSIdo Schimmel 14011e81779aSIdo Schimmel err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 14021e81779aSIdo Schimmel if (err) 14031e81779aSIdo Schimmel goto mbox_put; 14041e81779aSIdo Schimmel 14051e81779aSIdo Schimmel err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 14061e81779aSIdo Schimmel if (err) 14071e81779aSIdo Schimmel goto err_out_mbox_alloc; 14081e81779aSIdo Schimmel 1409eda6500aSJiri Pirko err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1410eda6500aSJiri Pirko if (err) 1411eda6500aSJiri Pirko goto err_query_fw; 1412eda6500aSJiri Pirko 1413eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.major = 1414eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1415eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.minor = 1416eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1417eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.subminor = 1418eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1419eda6500aSJiri Pirko 1420eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1421eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1422eda6500aSJiri Pirko err = -EINVAL; 1423eda6500aSJiri Pirko goto err_iface_rev; 1424eda6500aSJiri Pirko } 1425eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1426eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1427eda6500aSJiri Pirko err = -EINVAL; 1428eda6500aSJiri Pirko goto err_doorbell_page_bar; 1429eda6500aSJiri Pirko } 1430eda6500aSJiri Pirko 1431eda6500aSJiri Pirko mlxsw_pci->doorbell_offset = 1432eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1433eda6500aSJiri Pirko 1434eda6500aSJiri Pirko num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1435eda6500aSJiri Pirko err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1436eda6500aSJiri Pirko if (err) 1437eda6500aSJiri Pirko goto err_fw_area_init; 1438eda6500aSJiri Pirko 1439eda6500aSJiri Pirko err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1440eda6500aSJiri Pirko if (err) 1441eda6500aSJiri Pirko goto err_boardinfo; 1442eda6500aSJiri Pirko 1443eda6500aSJiri Pirko err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile); 1444eda6500aSJiri Pirko if (err) 1445eda6500aSJiri Pirko goto err_config_profile; 1446eda6500aSJiri Pirko 1447eda6500aSJiri Pirko err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1448eda6500aSJiri Pirko if (err) 1449eda6500aSJiri Pirko goto err_aqs_init; 1450eda6500aSJiri Pirko 1451eda6500aSJiri Pirko err = request_irq(mlxsw_pci->msix_entry.vector, 1452eda6500aSJiri Pirko mlxsw_pci_eq_irq_handler, 0, 1453eda6500aSJiri Pirko mlxsw_pci_driver_name, mlxsw_pci); 1454eda6500aSJiri Pirko if (err) { 1455eda6500aSJiri Pirko dev_err(&pdev->dev, "IRQ request failed\n"); 1456eda6500aSJiri Pirko goto err_request_eq_irq; 1457eda6500aSJiri Pirko } 1458eda6500aSJiri Pirko 1459eda6500aSJiri Pirko goto mbox_put; 1460eda6500aSJiri Pirko 1461eda6500aSJiri Pirko err_request_eq_irq: 1462eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1463eda6500aSJiri Pirko err_aqs_init: 1464eda6500aSJiri Pirko err_config_profile: 1465eda6500aSJiri Pirko err_boardinfo: 1466eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1467eda6500aSJiri Pirko err_fw_area_init: 1468eda6500aSJiri Pirko err_doorbell_page_bar: 1469eda6500aSJiri Pirko err_iface_rev: 1470eda6500aSJiri Pirko err_query_fw: 14711e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 14721e81779aSIdo Schimmel err_out_mbox_alloc: 14731e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1474eda6500aSJiri Pirko mbox_put: 1475eda6500aSJiri Pirko mlxsw_cmd_mbox_free(mbox); 1476eda6500aSJiri Pirko return err; 1477eda6500aSJiri Pirko } 1478eda6500aSJiri Pirko 1479eda6500aSJiri Pirko static void mlxsw_pci_fini(void *bus_priv) 1480eda6500aSJiri Pirko { 1481eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1482eda6500aSJiri Pirko 1483eda6500aSJiri Pirko free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci); 1484eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1485eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 14861e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 14871e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1488eda6500aSJiri Pirko } 1489eda6500aSJiri Pirko 1490eda6500aSJiri Pirko static struct mlxsw_pci_queue * 1491eda6500aSJiri Pirko mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1492eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1493eda6500aSJiri Pirko { 1494eda6500aSJiri Pirko u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci); 1495eda6500aSJiri Pirko 1496eda6500aSJiri Pirko return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1497eda6500aSJiri Pirko } 1498eda6500aSJiri Pirko 1499d003462aSIdo Schimmel static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1500d003462aSIdo Schimmel const struct mlxsw_tx_info *tx_info) 1501d003462aSIdo Schimmel { 1502d003462aSIdo Schimmel struct mlxsw_pci *mlxsw_pci = bus_priv; 1503d003462aSIdo Schimmel struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1504d003462aSIdo Schimmel 1505d003462aSIdo Schimmel return !mlxsw_pci_queue_elem_info_producer_get(q); 1506d003462aSIdo Schimmel } 1507d003462aSIdo Schimmel 1508eda6500aSJiri Pirko static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1509eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1510eda6500aSJiri Pirko { 1511eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1512eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1513eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 1514eda6500aSJiri Pirko char *wqe; 1515eda6500aSJiri Pirko int i; 1516eda6500aSJiri Pirko int err; 1517eda6500aSJiri Pirko 1518eda6500aSJiri Pirko if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1519eda6500aSJiri Pirko err = skb_linearize(skb); 1520eda6500aSJiri Pirko if (err) 1521eda6500aSJiri Pirko return err; 1522eda6500aSJiri Pirko } 1523eda6500aSJiri Pirko 1524eda6500aSJiri Pirko q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1525eda6500aSJiri Pirko spin_lock_bh(&q->lock); 1526eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1527eda6500aSJiri Pirko if (!elem_info) { 1528eda6500aSJiri Pirko /* queue is full */ 1529eda6500aSJiri Pirko err = -EAGAIN; 1530eda6500aSJiri Pirko goto unlock; 1531eda6500aSJiri Pirko } 1532eda6500aSJiri Pirko elem_info->u.sdq.skb = skb; 1533eda6500aSJiri Pirko 1534eda6500aSJiri Pirko wqe = elem_info->elem; 1535eda6500aSJiri Pirko mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1536eda6500aSJiri Pirko mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1537eda6500aSJiri Pirko mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1538eda6500aSJiri Pirko 1539eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1540eda6500aSJiri Pirko skb_headlen(skb), DMA_TO_DEVICE); 1541eda6500aSJiri Pirko if (err) 1542eda6500aSJiri Pirko goto unlock; 1543eda6500aSJiri Pirko 1544eda6500aSJiri Pirko for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1545eda6500aSJiri Pirko const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1546eda6500aSJiri Pirko 1547eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1548eda6500aSJiri Pirko skb_frag_address(frag), 1549eda6500aSJiri Pirko skb_frag_size(frag), 1550eda6500aSJiri Pirko DMA_TO_DEVICE); 1551eda6500aSJiri Pirko if (err) 1552eda6500aSJiri Pirko goto unmap_frags; 1553eda6500aSJiri Pirko } 1554eda6500aSJiri Pirko 1555eda6500aSJiri Pirko /* Set unused sq entries byte count to zero. */ 1556eda6500aSJiri Pirko for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1557eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1558eda6500aSJiri Pirko 1559eda6500aSJiri Pirko /* Everything is set up, ring producer doorbell to get HW going */ 1560eda6500aSJiri Pirko q->producer_counter++; 1561eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1562eda6500aSJiri Pirko 1563eda6500aSJiri Pirko goto unlock; 1564eda6500aSJiri Pirko 1565eda6500aSJiri Pirko unmap_frags: 1566eda6500aSJiri Pirko for (; i >= 0; i--) 1567eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1568eda6500aSJiri Pirko unlock: 1569eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 1570eda6500aSJiri Pirko return err; 1571eda6500aSJiri Pirko } 1572eda6500aSJiri Pirko 1573eda6500aSJiri Pirko static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1574eda6500aSJiri Pirko u32 in_mod, bool out_mbox_direct, 1575eda6500aSJiri Pirko char *in_mbox, size_t in_mbox_size, 1576eda6500aSJiri Pirko char *out_mbox, size_t out_mbox_size, 1577eda6500aSJiri Pirko u8 *p_status) 1578eda6500aSJiri Pirko { 1579eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 15801e81779aSIdo Schimmel dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 15811e81779aSIdo Schimmel dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1582eda6500aSJiri Pirko bool evreq = mlxsw_pci->cmd.nopoll; 1583eda6500aSJiri Pirko unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1584eda6500aSJiri Pirko bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1585eda6500aSJiri Pirko int err; 1586eda6500aSJiri Pirko 1587eda6500aSJiri Pirko *p_status = MLXSW_CMD_STATUS_OK; 1588eda6500aSJiri Pirko 1589eda6500aSJiri Pirko err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1590eda6500aSJiri Pirko if (err) 1591eda6500aSJiri Pirko return err; 1592eda6500aSJiri Pirko 15931e81779aSIdo Schimmel if (in_mbox) 15941e81779aSIdo Schimmel memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1595eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, in_mapaddr >> 32); 1596eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, in_mapaddr); 1597eda6500aSJiri Pirko 1598eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, out_mapaddr >> 32); 1599eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, out_mapaddr); 1600eda6500aSJiri Pirko 1601eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1602eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1603eda6500aSJiri Pirko 1604eda6500aSJiri Pirko *p_wait_done = false; 1605eda6500aSJiri Pirko 1606eda6500aSJiri Pirko wmb(); /* all needs to be written before we write control register */ 1607eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1608eda6500aSJiri Pirko MLXSW_PCI_CIR_CTRL_GO_BIT | 1609eda6500aSJiri Pirko (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1610eda6500aSJiri Pirko (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1611eda6500aSJiri Pirko opcode); 1612eda6500aSJiri Pirko 1613eda6500aSJiri Pirko if (!evreq) { 1614eda6500aSJiri Pirko unsigned long end; 1615eda6500aSJiri Pirko 1616eda6500aSJiri Pirko end = jiffies + timeout; 1617eda6500aSJiri Pirko do { 1618eda6500aSJiri Pirko u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1619eda6500aSJiri Pirko 1620eda6500aSJiri Pirko if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1621eda6500aSJiri Pirko *p_wait_done = true; 1622eda6500aSJiri Pirko *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1623eda6500aSJiri Pirko break; 1624eda6500aSJiri Pirko } 1625eda6500aSJiri Pirko cond_resched(); 1626eda6500aSJiri Pirko } while (time_before(jiffies, end)); 1627eda6500aSJiri Pirko } else { 1628eda6500aSJiri Pirko wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1629eda6500aSJiri Pirko *p_status = mlxsw_pci->cmd.comp.status; 1630eda6500aSJiri Pirko } 1631eda6500aSJiri Pirko 1632eda6500aSJiri Pirko err = 0; 1633eda6500aSJiri Pirko if (*p_wait_done) { 1634eda6500aSJiri Pirko if (*p_status) 1635eda6500aSJiri Pirko err = -EIO; 1636eda6500aSJiri Pirko } else { 1637eda6500aSJiri Pirko err = -ETIMEDOUT; 1638eda6500aSJiri Pirko } 1639eda6500aSJiri Pirko 1640eda6500aSJiri Pirko if (!err && out_mbox && out_mbox_direct) { 16411e81779aSIdo Schimmel /* Some commands don't use output param as address to mailbox 1642eda6500aSJiri Pirko * but they store output directly into registers. In that case, 1643eda6500aSJiri Pirko * copy registers into mbox buffer. 1644eda6500aSJiri Pirko */ 1645eda6500aSJiri Pirko __be32 tmp; 1646eda6500aSJiri Pirko 1647eda6500aSJiri Pirko if (!evreq) { 1648eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1649eda6500aSJiri Pirko CIR_OUT_PARAM_HI)); 1650eda6500aSJiri Pirko memcpy(out_mbox, &tmp, sizeof(tmp)); 1651eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1652eda6500aSJiri Pirko CIR_OUT_PARAM_LO)); 1653eda6500aSJiri Pirko memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1654eda6500aSJiri Pirko } 16551e81779aSIdo Schimmel } else if (!err && out_mbox) 16561e81779aSIdo Schimmel memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1657eda6500aSJiri Pirko 1658eda6500aSJiri Pirko mutex_unlock(&mlxsw_pci->cmd.lock); 1659eda6500aSJiri Pirko 1660eda6500aSJiri Pirko return err; 1661eda6500aSJiri Pirko } 1662eda6500aSJiri Pirko 1663eda6500aSJiri Pirko static const struct mlxsw_bus mlxsw_pci_bus = { 1664eda6500aSJiri Pirko .kind = "pci", 1665eda6500aSJiri Pirko .init = mlxsw_pci_init, 1666eda6500aSJiri Pirko .fini = mlxsw_pci_fini, 1667d003462aSIdo Schimmel .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 1668eda6500aSJiri Pirko .skb_transmit = mlxsw_pci_skb_transmit, 1669eda6500aSJiri Pirko .cmd_exec = mlxsw_pci_cmd_exec, 1670eda6500aSJiri Pirko }; 1671eda6500aSJiri Pirko 1672eda6500aSJiri Pirko static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci) 1673eda6500aSJiri Pirko { 1674eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT); 1675eda6500aSJiri Pirko /* Current firware does not let us know when the reset is done. 1676eda6500aSJiri Pirko * So we just wait here for constant time and hope for the best. 1677eda6500aSJiri Pirko */ 1678eda6500aSJiri Pirko msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1679eda6500aSJiri Pirko return 0; 1680eda6500aSJiri Pirko } 1681eda6500aSJiri Pirko 1682eda6500aSJiri Pirko static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1683eda6500aSJiri Pirko { 1684eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci; 1685eda6500aSJiri Pirko int err; 1686eda6500aSJiri Pirko 1687eda6500aSJiri Pirko mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1688eda6500aSJiri Pirko if (!mlxsw_pci) 1689eda6500aSJiri Pirko return -ENOMEM; 1690eda6500aSJiri Pirko 1691eda6500aSJiri Pirko err = pci_enable_device(pdev); 1692eda6500aSJiri Pirko if (err) { 1693eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_enable_device failed\n"); 1694eda6500aSJiri Pirko goto err_pci_enable_device; 1695eda6500aSJiri Pirko } 1696eda6500aSJiri Pirko 1697eda6500aSJiri Pirko err = pci_request_regions(pdev, mlxsw_pci_driver_name); 1698eda6500aSJiri Pirko if (err) { 1699eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_request_regions failed\n"); 1700eda6500aSJiri Pirko goto err_pci_request_regions; 1701eda6500aSJiri Pirko } 1702eda6500aSJiri Pirko 1703eda6500aSJiri Pirko err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1704eda6500aSJiri Pirko if (!err) { 1705eda6500aSJiri Pirko err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1706eda6500aSJiri Pirko if (err) { 1707eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n"); 1708eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1709eda6500aSJiri Pirko } 1710eda6500aSJiri Pirko } else { 1711eda6500aSJiri Pirko err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1712eda6500aSJiri Pirko if (err) { 1713eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_set_dma_mask failed\n"); 1714eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1715eda6500aSJiri Pirko } 1716eda6500aSJiri Pirko } 1717eda6500aSJiri Pirko 1718eda6500aSJiri Pirko if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1719eda6500aSJiri Pirko dev_err(&pdev->dev, "invalid PCI region size\n"); 1720eda6500aSJiri Pirko err = -EINVAL; 1721eda6500aSJiri Pirko goto err_pci_resource_len_check; 1722eda6500aSJiri Pirko } 1723eda6500aSJiri Pirko 1724eda6500aSJiri Pirko mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1725eda6500aSJiri Pirko pci_resource_len(pdev, 0)); 1726eda6500aSJiri Pirko if (!mlxsw_pci->hw_addr) { 1727eda6500aSJiri Pirko dev_err(&pdev->dev, "ioremap failed\n"); 1728eda6500aSJiri Pirko err = -EIO; 1729eda6500aSJiri Pirko goto err_ioremap; 1730eda6500aSJiri Pirko } 1731eda6500aSJiri Pirko pci_set_master(pdev); 1732eda6500aSJiri Pirko 1733eda6500aSJiri Pirko mlxsw_pci->pdev = pdev; 1734eda6500aSJiri Pirko pci_set_drvdata(pdev, mlxsw_pci); 1735eda6500aSJiri Pirko 1736eda6500aSJiri Pirko err = mlxsw_pci_sw_reset(mlxsw_pci); 1737eda6500aSJiri Pirko if (err) { 1738eda6500aSJiri Pirko dev_err(&pdev->dev, "Software reset failed\n"); 1739eda6500aSJiri Pirko goto err_sw_reset; 1740eda6500aSJiri Pirko } 1741eda6500aSJiri Pirko 1742eda6500aSJiri Pirko err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1); 1743eda6500aSJiri Pirko if (err) { 1744eda6500aSJiri Pirko dev_err(&pdev->dev, "MSI-X init failed\n"); 1745eda6500aSJiri Pirko goto err_msix_init; 1746eda6500aSJiri Pirko } 1747eda6500aSJiri Pirko 1748eda6500aSJiri Pirko mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id); 1749eda6500aSJiri Pirko mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1750eda6500aSJiri Pirko mlxsw_pci->bus_info.dev = &pdev->dev; 1751eda6500aSJiri Pirko 1752eda6500aSJiri Pirko mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name, 1753eda6500aSJiri Pirko mlxsw_pci_dbg_root); 1754eda6500aSJiri Pirko if (!mlxsw_pci->dbg_dir) { 1755eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to create debugfs dir\n"); 17565c121979SJulia Lawall err = -ENOMEM; 1757eda6500aSJiri Pirko goto err_dbg_create_dir; 1758eda6500aSJiri Pirko } 1759eda6500aSJiri Pirko 1760eda6500aSJiri Pirko err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 1761eda6500aSJiri Pirko &mlxsw_pci_bus, mlxsw_pci); 1762eda6500aSJiri Pirko if (err) { 1763eda6500aSJiri Pirko dev_err(&pdev->dev, "cannot register bus device\n"); 1764eda6500aSJiri Pirko goto err_bus_device_register; 1765eda6500aSJiri Pirko } 1766eda6500aSJiri Pirko 1767eda6500aSJiri Pirko return 0; 1768eda6500aSJiri Pirko 1769eda6500aSJiri Pirko err_bus_device_register: 1770eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci->dbg_dir); 1771eda6500aSJiri Pirko err_dbg_create_dir: 1772eda6500aSJiri Pirko pci_disable_msix(mlxsw_pci->pdev); 1773eda6500aSJiri Pirko err_msix_init: 1774eda6500aSJiri Pirko err_sw_reset: 1775eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1776eda6500aSJiri Pirko err_ioremap: 1777eda6500aSJiri Pirko err_pci_resource_len_check: 1778eda6500aSJiri Pirko err_pci_set_dma_mask: 1779eda6500aSJiri Pirko pci_release_regions(pdev); 1780eda6500aSJiri Pirko err_pci_request_regions: 1781eda6500aSJiri Pirko pci_disable_device(pdev); 1782eda6500aSJiri Pirko err_pci_enable_device: 1783eda6500aSJiri Pirko kfree(mlxsw_pci); 1784eda6500aSJiri Pirko return err; 1785eda6500aSJiri Pirko } 1786eda6500aSJiri Pirko 1787eda6500aSJiri Pirko static void mlxsw_pci_remove(struct pci_dev *pdev) 1788eda6500aSJiri Pirko { 1789eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1790eda6500aSJiri Pirko 1791eda6500aSJiri Pirko mlxsw_core_bus_device_unregister(mlxsw_pci->core); 1792eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci->dbg_dir); 1793eda6500aSJiri Pirko pci_disable_msix(mlxsw_pci->pdev); 1794eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1795eda6500aSJiri Pirko pci_release_regions(mlxsw_pci->pdev); 1796eda6500aSJiri Pirko pci_disable_device(mlxsw_pci->pdev); 1797eda6500aSJiri Pirko kfree(mlxsw_pci); 1798eda6500aSJiri Pirko } 1799eda6500aSJiri Pirko 1800eda6500aSJiri Pirko static struct pci_driver mlxsw_pci_driver = { 1801eda6500aSJiri Pirko .name = mlxsw_pci_driver_name, 1802eda6500aSJiri Pirko .id_table = mlxsw_pci_id_table, 1803eda6500aSJiri Pirko .probe = mlxsw_pci_probe, 1804eda6500aSJiri Pirko .remove = mlxsw_pci_remove, 1805eda6500aSJiri Pirko }; 1806eda6500aSJiri Pirko 1807eda6500aSJiri Pirko static int __init mlxsw_pci_module_init(void) 1808eda6500aSJiri Pirko { 1809eda6500aSJiri Pirko int err; 1810eda6500aSJiri Pirko 1811eda6500aSJiri Pirko mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL); 1812eda6500aSJiri Pirko if (!mlxsw_pci_dbg_root) 1813eda6500aSJiri Pirko return -ENOMEM; 1814eda6500aSJiri Pirko err = pci_register_driver(&mlxsw_pci_driver); 1815eda6500aSJiri Pirko if (err) 1816eda6500aSJiri Pirko goto err_register_driver; 1817eda6500aSJiri Pirko return 0; 1818eda6500aSJiri Pirko 1819eda6500aSJiri Pirko err_register_driver: 1820eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci_dbg_root); 1821eda6500aSJiri Pirko return err; 1822eda6500aSJiri Pirko } 1823eda6500aSJiri Pirko 1824eda6500aSJiri Pirko static void __exit mlxsw_pci_module_exit(void) 1825eda6500aSJiri Pirko { 1826eda6500aSJiri Pirko pci_unregister_driver(&mlxsw_pci_driver); 1827eda6500aSJiri Pirko debugfs_remove_recursive(mlxsw_pci_dbg_root); 1828eda6500aSJiri Pirko } 1829eda6500aSJiri Pirko 1830eda6500aSJiri Pirko module_init(mlxsw_pci_module_init); 1831eda6500aSJiri Pirko module_exit(mlxsw_pci_module_exit); 1832eda6500aSJiri Pirko 1833eda6500aSJiri Pirko MODULE_LICENSE("Dual BSD/GPL"); 1834eda6500aSJiri Pirko MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 1835eda6500aSJiri Pirko MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 1836eda6500aSJiri Pirko MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table); 1837