19948a064SJiri Pirko // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 29948a064SJiri Pirko /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3eda6500aSJiri Pirko 4eda6500aSJiri Pirko #include <linux/kernel.h> 5eda6500aSJiri Pirko #include <linux/module.h> 6eda6500aSJiri Pirko #include <linux/export.h> 7eda6500aSJiri Pirko #include <linux/err.h> 8eda6500aSJiri Pirko #include <linux/device.h> 9eda6500aSJiri Pirko #include <linux/pci.h> 10eda6500aSJiri Pirko #include <linux/interrupt.h> 11eda6500aSJiri Pirko #include <linux/wait.h> 12eda6500aSJiri Pirko #include <linux/types.h> 13eda6500aSJiri Pirko #include <linux/skbuff.h> 14eda6500aSJiri Pirko #include <linux/if_vlan.h> 15eda6500aSJiri Pirko #include <linux/log2.h> 161e81779aSIdo Schimmel #include <linux/string.h> 17eda6500aSJiri Pirko 1862e86f9eSJiri Pirko #include "pci_hw.h" 191d20d23cSJiri Pirko #include "pci.h" 20eda6500aSJiri Pirko #include "core.h" 21eda6500aSJiri Pirko #include "cmd.h" 22eda6500aSJiri Pirko #include "port.h" 23c1a38311SJiri Pirko #include "resources.h" 24eda6500aSJiri Pirko 25eda6500aSJiri Pirko #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 26eda6500aSJiri Pirko iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 27eda6500aSJiri Pirko #define mlxsw_pci_read32(mlxsw_pci, reg) \ 28eda6500aSJiri Pirko ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 29eda6500aSJiri Pirko 30eda6500aSJiri Pirko enum mlxsw_pci_queue_type { 31eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, 32eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, 33eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_CQ, 34eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_EQ, 35eda6500aSJiri Pirko }; 36eda6500aSJiri Pirko 37eda6500aSJiri Pirko #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 38eda6500aSJiri Pirko 39eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_type_offset[] = { 40eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 41eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 42eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 43eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 44eda6500aSJiri Pirko }; 45eda6500aSJiri Pirko 46eda6500aSJiri Pirko static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 47eda6500aSJiri Pirko 0, /* unused */ 48eda6500aSJiri Pirko 0, /* unused */ 49eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 50eda6500aSJiri Pirko MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 51eda6500aSJiri Pirko }; 52eda6500aSJiri Pirko 53eda6500aSJiri Pirko struct mlxsw_pci_mem_item { 54eda6500aSJiri Pirko char *buf; 55eda6500aSJiri Pirko dma_addr_t mapaddr; 56eda6500aSJiri Pirko size_t size; 57eda6500aSJiri Pirko }; 58eda6500aSJiri Pirko 59eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info { 60eda6500aSJiri Pirko char *elem; /* pointer to actual dma mapped element mem chunk */ 61eda6500aSJiri Pirko union { 62eda6500aSJiri Pirko struct { 63eda6500aSJiri Pirko struct sk_buff *skb; 64eda6500aSJiri Pirko } sdq; 65eda6500aSJiri Pirko struct { 66eda6500aSJiri Pirko struct sk_buff *skb; 67eda6500aSJiri Pirko } rdq; 68eda6500aSJiri Pirko } u; 69eda6500aSJiri Pirko }; 70eda6500aSJiri Pirko 71eda6500aSJiri Pirko struct mlxsw_pci_queue { 72eda6500aSJiri Pirko spinlock_t lock; /* for queue accesses */ 73eda6500aSJiri Pirko struct mlxsw_pci_mem_item mem_item; 74eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 75eda6500aSJiri Pirko u16 producer_counter; 76eda6500aSJiri Pirko u16 consumer_counter; 77eda6500aSJiri Pirko u16 count; /* number of elements in queue */ 78eda6500aSJiri Pirko u8 num; /* queue number */ 79eda6500aSJiri Pirko u8 elem_size; /* size of one element */ 80eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 81eda6500aSJiri Pirko struct tasklet_struct tasklet; /* queue processing tasklet */ 82eda6500aSJiri Pirko struct mlxsw_pci *pci; 83eda6500aSJiri Pirko union { 84eda6500aSJiri Pirko struct { 85eda6500aSJiri Pirko u32 comp_sdq_count; 86eda6500aSJiri Pirko u32 comp_rdq_count; 87b76550bbSJiri Pirko enum mlxsw_pci_cqe_v v; 88eda6500aSJiri Pirko } cq; 89eda6500aSJiri Pirko struct { 90eda6500aSJiri Pirko u32 ev_cmd_count; 91eda6500aSJiri Pirko u32 ev_comp_count; 92eda6500aSJiri Pirko u32 ev_other_count; 93eda6500aSJiri Pirko } eq; 94eda6500aSJiri Pirko } u; 95eda6500aSJiri Pirko }; 96eda6500aSJiri Pirko 97eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group { 98eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 99eda6500aSJiri Pirko u8 count; /* number of queues in group */ 100eda6500aSJiri Pirko }; 101eda6500aSJiri Pirko 102eda6500aSJiri Pirko struct mlxsw_pci { 103eda6500aSJiri Pirko struct pci_dev *pdev; 104eda6500aSJiri Pirko u8 __iomem *hw_addr; 1058289169dSShalom Toledo u64 free_running_clock_offset; 106eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 107eda6500aSJiri Pirko u32 doorbell_offset; 108eda6500aSJiri Pirko struct mlxsw_core *core; 109eda6500aSJiri Pirko struct { 110eda6500aSJiri Pirko struct mlxsw_pci_mem_item *items; 1113e2206daSJiri Pirko unsigned int count; 112eda6500aSJiri Pirko } fw_area; 113eda6500aSJiri Pirko struct { 1141e81779aSIdo Schimmel struct mlxsw_pci_mem_item out_mbox; 1151e81779aSIdo Schimmel struct mlxsw_pci_mem_item in_mbox; 116eda6500aSJiri Pirko struct mutex lock; /* Lock access to command registers */ 117eda6500aSJiri Pirko bool nopoll; 118eda6500aSJiri Pirko wait_queue_head_t wait; 119eda6500aSJiri Pirko bool wait_done; 120eda6500aSJiri Pirko struct { 121eda6500aSJiri Pirko u8 status; 122eda6500aSJiri Pirko u64 out_param; 123eda6500aSJiri Pirko } comp; 124eda6500aSJiri Pirko } cmd; 125eda6500aSJiri Pirko struct mlxsw_bus_info bus_info; 12654a2e8d4SArkadi Sharshevsky const struct pci_device_id *id; 1278404f6f2SJiri Pirko enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ 1288404f6f2SJiri Pirko u8 num_sdq_cqs; /* Number of CQs used for SDQs */ 129eda6500aSJiri Pirko }; 130eda6500aSJiri Pirko 131eda6500aSJiri Pirko static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) 132eda6500aSJiri Pirko { 133eda6500aSJiri Pirko tasklet_schedule(&q->tasklet); 134eda6500aSJiri Pirko } 135eda6500aSJiri Pirko 136eda6500aSJiri Pirko static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 137eda6500aSJiri Pirko size_t elem_size, int elem_index) 138eda6500aSJiri Pirko { 139eda6500aSJiri Pirko return q->mem_item.buf + (elem_size * elem_index); 140eda6500aSJiri Pirko } 141eda6500aSJiri Pirko 142eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 143eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 144eda6500aSJiri Pirko { 145eda6500aSJiri Pirko return &q->elem_info[elem_index]; 146eda6500aSJiri Pirko } 147eda6500aSJiri Pirko 148eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 149eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 150eda6500aSJiri Pirko { 151eda6500aSJiri Pirko int index = q->producer_counter & (q->count - 1); 152eda6500aSJiri Pirko 1535091730dSIdo Schimmel if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 154eda6500aSJiri Pirko return NULL; 155eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 156eda6500aSJiri Pirko } 157eda6500aSJiri Pirko 158eda6500aSJiri Pirko static struct mlxsw_pci_queue_elem_info * 159eda6500aSJiri Pirko mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 160eda6500aSJiri Pirko { 161eda6500aSJiri Pirko int index = q->consumer_counter & (q->count - 1); 162eda6500aSJiri Pirko 163eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, index); 164eda6500aSJiri Pirko } 165eda6500aSJiri Pirko 166eda6500aSJiri Pirko static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 167eda6500aSJiri Pirko { 168eda6500aSJiri Pirko return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 169eda6500aSJiri Pirko } 170eda6500aSJiri Pirko 171eda6500aSJiri Pirko static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 172eda6500aSJiri Pirko { 173eda6500aSJiri Pirko return owner_bit != !!(q->consumer_counter & q->count); 174eda6500aSJiri Pirko } 175eda6500aSJiri Pirko 176eda6500aSJiri Pirko static struct mlxsw_pci_queue_type_group * 177eda6500aSJiri Pirko mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 178eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 179eda6500aSJiri Pirko { 180eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type]; 181eda6500aSJiri Pirko } 182eda6500aSJiri Pirko 183eda6500aSJiri Pirko static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci, 184eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type) 185eda6500aSJiri Pirko { 186eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 187eda6500aSJiri Pirko 188eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type); 189eda6500aSJiri Pirko return queue_group->count; 190eda6500aSJiri Pirko } 191eda6500aSJiri Pirko 192eda6500aSJiri Pirko static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci) 193eda6500aSJiri Pirko { 194eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ); 195eda6500aSJiri Pirko } 196eda6500aSJiri Pirko 197eda6500aSJiri Pirko static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci) 198eda6500aSJiri Pirko { 199eda6500aSJiri Pirko return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ); 200eda6500aSJiri Pirko } 201eda6500aSJiri Pirko 202eda6500aSJiri Pirko static struct mlxsw_pci_queue * 203eda6500aSJiri Pirko __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 204eda6500aSJiri Pirko enum mlxsw_pci_queue_type q_type, u8 q_num) 205eda6500aSJiri Pirko { 206eda6500aSJiri Pirko return &mlxsw_pci->queues[q_type].q[q_num]; 207eda6500aSJiri Pirko } 208eda6500aSJiri Pirko 209eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 210eda6500aSJiri Pirko u8 q_num) 211eda6500aSJiri Pirko { 212eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 213eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 214eda6500aSJiri Pirko } 215eda6500aSJiri Pirko 216eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci, 217eda6500aSJiri Pirko u8 q_num) 218eda6500aSJiri Pirko { 219eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, 220eda6500aSJiri Pirko MLXSW_PCI_QUEUE_TYPE_RDQ, q_num); 221eda6500aSJiri Pirko } 222eda6500aSJiri Pirko 223eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 224eda6500aSJiri Pirko u8 q_num) 225eda6500aSJiri Pirko { 226eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 227eda6500aSJiri Pirko } 228eda6500aSJiri Pirko 229eda6500aSJiri Pirko static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci, 230eda6500aSJiri Pirko u8 q_num) 231eda6500aSJiri Pirko { 232eda6500aSJiri Pirko return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num); 233eda6500aSJiri Pirko } 234eda6500aSJiri Pirko 235eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 236eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 237eda6500aSJiri Pirko u16 val) 238eda6500aSJiri Pirko { 239eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 240eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 241eda6500aSJiri Pirko mlxsw_pci_doorbell_type_offset[q->type], 242eda6500aSJiri Pirko q->num), val); 243eda6500aSJiri Pirko } 244eda6500aSJiri Pirko 245eda6500aSJiri Pirko static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 246eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 247eda6500aSJiri Pirko u16 val) 248eda6500aSJiri Pirko { 249eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, 250eda6500aSJiri Pirko DOORBELL(mlxsw_pci->doorbell_offset, 251eda6500aSJiri Pirko mlxsw_pci_doorbell_arm_type_offset[q->type], 252eda6500aSJiri Pirko q->num), val); 253eda6500aSJiri Pirko } 254eda6500aSJiri Pirko 255eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 256eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 257eda6500aSJiri Pirko { 258eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 259eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 260eda6500aSJiri Pirko } 261eda6500aSJiri Pirko 262eda6500aSJiri Pirko static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 263eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 264eda6500aSJiri Pirko { 265eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 266eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 267eda6500aSJiri Pirko q->consumer_counter + q->count); 268eda6500aSJiri Pirko } 269eda6500aSJiri Pirko 270eda6500aSJiri Pirko static void 271eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 272eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 273eda6500aSJiri Pirko { 274eda6500aSJiri Pirko wmb(); /* ensure all writes are done before we ring a bell */ 275eda6500aSJiri Pirko __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 276eda6500aSJiri Pirko } 277eda6500aSJiri Pirko 278eda6500aSJiri Pirko static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 279eda6500aSJiri Pirko int page_index) 280eda6500aSJiri Pirko { 281eda6500aSJiri Pirko return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 282eda6500aSJiri Pirko } 283eda6500aSJiri Pirko 284eda6500aSJiri Pirko static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 285eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 286eda6500aSJiri Pirko { 287eda6500aSJiri Pirko int i; 288eda6500aSJiri Pirko int err; 289eda6500aSJiri Pirko 290eda6500aSJiri Pirko q->producer_counter = 0; 291eda6500aSJiri Pirko q->consumer_counter = 0; 292eda6500aSJiri Pirko 293eda6500aSJiri Pirko /* Set CQ of same number of this SDQ. */ 294eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num); 295f0138e25SIdo Schimmel mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3); 296eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 297eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 298eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 299eda6500aSJiri Pirko 300eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 301eda6500aSJiri Pirko } 302eda6500aSJiri Pirko 303eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 304eda6500aSJiri Pirko if (err) 305eda6500aSJiri Pirko return err; 306eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 307eda6500aSJiri Pirko return 0; 308eda6500aSJiri Pirko } 309eda6500aSJiri Pirko 310eda6500aSJiri Pirko static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 311eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 312eda6500aSJiri Pirko { 313eda6500aSJiri Pirko mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 314eda6500aSJiri Pirko } 315eda6500aSJiri Pirko 316eda6500aSJiri Pirko static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 317eda6500aSJiri Pirko int index, char *frag_data, size_t frag_len, 318eda6500aSJiri Pirko int direction) 319eda6500aSJiri Pirko { 320eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 321eda6500aSJiri Pirko dma_addr_t mapaddr; 322eda6500aSJiri Pirko 323eda6500aSJiri Pirko mapaddr = pci_map_single(pdev, frag_data, frag_len, direction); 324eda6500aSJiri Pirko if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) { 3256cf9dc8bSJiri Pirko dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 326eda6500aSJiri Pirko return -EIO; 327eda6500aSJiri Pirko } 328eda6500aSJiri Pirko mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 329eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 330eda6500aSJiri Pirko return 0; 331eda6500aSJiri Pirko } 332eda6500aSJiri Pirko 333eda6500aSJiri Pirko static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 334eda6500aSJiri Pirko int index, int direction) 335eda6500aSJiri Pirko { 336eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 337eda6500aSJiri Pirko size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 338eda6500aSJiri Pirko dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 339eda6500aSJiri Pirko 340eda6500aSJiri Pirko if (!frag_len) 341eda6500aSJiri Pirko return; 342eda6500aSJiri Pirko pci_unmap_single(pdev, mapaddr, frag_len, direction); 343eda6500aSJiri Pirko } 344eda6500aSJiri Pirko 345eda6500aSJiri Pirko static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci, 346eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 347eda6500aSJiri Pirko { 348eda6500aSJiri Pirko size_t buf_len = MLXSW_PORT_MAX_MTU; 349eda6500aSJiri Pirko char *wqe = elem_info->elem; 350eda6500aSJiri Pirko struct sk_buff *skb; 351eda6500aSJiri Pirko int err; 352eda6500aSJiri Pirko 353eda6500aSJiri Pirko elem_info->u.rdq.skb = NULL; 354eda6500aSJiri Pirko skb = netdev_alloc_skb_ip_align(NULL, buf_len); 355eda6500aSJiri Pirko if (!skb) 356eda6500aSJiri Pirko return -ENOMEM; 357eda6500aSJiri Pirko 358eda6500aSJiri Pirko /* Assume that wqe was previously zeroed. */ 359eda6500aSJiri Pirko 360eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 361eda6500aSJiri Pirko buf_len, DMA_FROM_DEVICE); 362eda6500aSJiri Pirko if (err) 363eda6500aSJiri Pirko goto err_frag_map; 364eda6500aSJiri Pirko 365eda6500aSJiri Pirko elem_info->u.rdq.skb = skb; 366eda6500aSJiri Pirko return 0; 367eda6500aSJiri Pirko 368eda6500aSJiri Pirko err_frag_map: 369eda6500aSJiri Pirko dev_kfree_skb_any(skb); 370eda6500aSJiri Pirko return err; 371eda6500aSJiri Pirko } 372eda6500aSJiri Pirko 373eda6500aSJiri Pirko static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci, 374eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info) 375eda6500aSJiri Pirko { 376eda6500aSJiri Pirko struct sk_buff *skb; 377eda6500aSJiri Pirko char *wqe; 378eda6500aSJiri Pirko 379eda6500aSJiri Pirko skb = elem_info->u.rdq.skb; 380eda6500aSJiri Pirko wqe = elem_info->elem; 381eda6500aSJiri Pirko 382eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 383eda6500aSJiri Pirko dev_kfree_skb_any(skb); 384eda6500aSJiri Pirko } 385eda6500aSJiri Pirko 386eda6500aSJiri Pirko static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 387eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 388eda6500aSJiri Pirko { 389eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 390424e1114SJiri Pirko u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci); 391eda6500aSJiri Pirko int i; 392eda6500aSJiri Pirko int err; 393eda6500aSJiri Pirko 394eda6500aSJiri Pirko q->producer_counter = 0; 395eda6500aSJiri Pirko q->consumer_counter = 0; 396eda6500aSJiri Pirko 397eda6500aSJiri Pirko /* Set CQ of same number of this RDQ with base 398424e1114SJiri Pirko * above SDQ count as the lower ones are assigned to SDQs. 399eda6500aSJiri Pirko */ 400424e1114SJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num); 401eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 402eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 403eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 404eda6500aSJiri Pirko 405eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 406eda6500aSJiri Pirko } 407eda6500aSJiri Pirko 408eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 409eda6500aSJiri Pirko if (err) 410eda6500aSJiri Pirko return err; 411eda6500aSJiri Pirko 412eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 413eda6500aSJiri Pirko 414eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 415eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 416eda6500aSJiri Pirko BUG_ON(!elem_info); 417eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 418eda6500aSJiri Pirko if (err) 419eda6500aSJiri Pirko goto rollback; 420eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 421eda6500aSJiri Pirko q->producer_counter++; 422eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 423eda6500aSJiri Pirko } 424eda6500aSJiri Pirko 425eda6500aSJiri Pirko return 0; 426eda6500aSJiri Pirko 427eda6500aSJiri Pirko rollback: 428eda6500aSJiri Pirko for (i--; i >= 0; i--) { 429eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 430eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 431eda6500aSJiri Pirko } 432eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 433eda6500aSJiri Pirko 434eda6500aSJiri Pirko return err; 435eda6500aSJiri Pirko } 436eda6500aSJiri Pirko 437eda6500aSJiri Pirko static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 438eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 439eda6500aSJiri Pirko { 440eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 441eda6500aSJiri Pirko int i; 442eda6500aSJiri Pirko 443eda6500aSJiri Pirko mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 444eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 445eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 446eda6500aSJiri Pirko mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info); 447eda6500aSJiri Pirko } 448eda6500aSJiri Pirko } 449eda6500aSJiri Pirko 4508404f6f2SJiri Pirko static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci, 4518404f6f2SJiri Pirko struct mlxsw_pci_queue *q) 4528404f6f2SJiri Pirko { 4538404f6f2SJiri Pirko q->u.cq.v = mlxsw_pci->max_cqe_ver; 4548404f6f2SJiri Pirko 4558404f6f2SJiri Pirko /* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */ 4568404f6f2SJiri Pirko if (q->u.cq.v == MLXSW_PCI_CQE_V2 && 4578404f6f2SJiri Pirko q->num < mlxsw_pci->num_sdq_cqs) 4588404f6f2SJiri Pirko q->u.cq.v = MLXSW_PCI_CQE_V1; 4598404f6f2SJiri Pirko } 4608404f6f2SJiri Pirko 461eda6500aSJiri Pirko static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 462eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 463eda6500aSJiri Pirko { 464eda6500aSJiri Pirko int i; 465eda6500aSJiri Pirko int err; 466eda6500aSJiri Pirko 467eda6500aSJiri Pirko q->consumer_counter = 0; 468eda6500aSJiri Pirko 469eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 470eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 471eda6500aSJiri Pirko 472b76550bbSJiri Pirko mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1); 473eda6500aSJiri Pirko } 474eda6500aSJiri Pirko 4758404f6f2SJiri Pirko if (q->u.cq.v == MLXSW_PCI_CQE_V1) 4768404f6f2SJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 4778404f6f2SJiri Pirko MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1); 4788404f6f2SJiri Pirko else if (q->u.cq.v == MLXSW_PCI_CQE_V2) 4798404f6f2SJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 4808404f6f2SJiri Pirko MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2); 4818404f6f2SJiri Pirko 482eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 483eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 484eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 485eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 486eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 487eda6500aSJiri Pirko 488eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 489eda6500aSJiri Pirko } 490eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 491eda6500aSJiri Pirko if (err) 492eda6500aSJiri Pirko return err; 493eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 494eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 495eda6500aSJiri Pirko return 0; 496eda6500aSJiri Pirko } 497eda6500aSJiri Pirko 498eda6500aSJiri Pirko static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 499eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 500eda6500aSJiri Pirko { 501eda6500aSJiri Pirko mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 502eda6500aSJiri Pirko } 503eda6500aSJiri Pirko 504eda6500aSJiri Pirko static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 505eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 506eda6500aSJiri Pirko u16 consumer_counter_limit, 507eda6500aSJiri Pirko char *cqe) 508eda6500aSJiri Pirko { 509eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 510eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 5110714256cSPetr Machata struct mlxsw_tx_info tx_info; 512eda6500aSJiri Pirko char *wqe; 513eda6500aSJiri Pirko struct sk_buff *skb; 514eda6500aSJiri Pirko int i; 515eda6500aSJiri Pirko 516eda6500aSJiri Pirko spin_lock(&q->lock); 517eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 5180714256cSPetr Machata tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info; 519eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 520eda6500aSJiri Pirko wqe = elem_info->elem; 521eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 522eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 5230714256cSPetr Machata 5240714256cSPetr Machata if (unlikely(!tx_info.is_emad && 5250714256cSPetr Machata skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 5260714256cSPetr Machata mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb, 5270714256cSPetr Machata tx_info.local_port); 5280714256cSPetr Machata skb = NULL; 5290714256cSPetr Machata } 5300714256cSPetr Machata 5310714256cSPetr Machata if (skb) 532eda6500aSJiri Pirko dev_kfree_skb_any(skb); 533eda6500aSJiri Pirko elem_info->u.sdq.skb = NULL; 534eda6500aSJiri Pirko 535eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 536eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 537eda6500aSJiri Pirko spin_unlock(&q->lock); 538eda6500aSJiri Pirko } 539eda6500aSJiri Pirko 540eda6500aSJiri Pirko static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 541eda6500aSJiri Pirko struct mlxsw_pci_queue *q, 542eda6500aSJiri Pirko u16 consumer_counter_limit, 543b76550bbSJiri Pirko enum mlxsw_pci_cqe_v cqe_v, char *cqe) 544eda6500aSJiri Pirko { 545eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 546eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 547eda6500aSJiri Pirko char *wqe; 548eda6500aSJiri Pirko struct sk_buff *skb; 549eda6500aSJiri Pirko struct mlxsw_rx_info rx_info; 5507b7b9cffSJiri Pirko u16 byte_count; 551eda6500aSJiri Pirko int err; 552eda6500aSJiri Pirko 553eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 554eda6500aSJiri Pirko skb = elem_info->u.sdq.skb; 555eda6500aSJiri Pirko if (!skb) 556eda6500aSJiri Pirko return; 557eda6500aSJiri Pirko wqe = elem_info->elem; 558eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE); 559eda6500aSJiri Pirko 560eda6500aSJiri Pirko if (q->consumer_counter++ != consumer_counter_limit) 561eda6500aSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 562eda6500aSJiri Pirko 563b76550bbSJiri Pirko if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { 564d2292e87SJiri Pirko rx_info.is_lag = true; 565b76550bbSJiri Pirko rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); 566b76550bbSJiri Pirko rx_info.lag_port_index = 567b76550bbSJiri Pirko mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); 568d2292e87SJiri Pirko } else { 5698060646aSJiri Pirko rx_info.is_lag = false; 5708060646aSJiri Pirko rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 571d2292e87SJiri Pirko } 5728060646aSJiri Pirko 573eda6500aSJiri Pirko rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 574eda6500aSJiri Pirko 5757b7b9cffSJiri Pirko byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 576b76550bbSJiri Pirko if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) 5777b7b9cffSJiri Pirko byte_count -= ETH_FCS_LEN; 5787b7b9cffSJiri Pirko skb_put(skb, byte_count); 579eda6500aSJiri Pirko mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 580eda6500aSJiri Pirko 581eda6500aSJiri Pirko memset(wqe, 0, q->elem_size); 582eda6500aSJiri Pirko err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info); 5836cf9dc8bSJiri Pirko if (err) 5846cf9dc8bSJiri Pirko dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n"); 585eda6500aSJiri Pirko /* Everything is set up, ring doorbell to pass elem to HW */ 586eda6500aSJiri Pirko q->producer_counter++; 587eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 588eda6500aSJiri Pirko return; 589eda6500aSJiri Pirko } 590eda6500aSJiri Pirko 591eda6500aSJiri Pirko static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 592eda6500aSJiri Pirko { 593b76550bbSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 594b76550bbSJiri Pirko char *elem; 595b76550bbSJiri Pirko bool owner_bit; 596b76550bbSJiri Pirko 597b76550bbSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 598b76550bbSJiri Pirko elem = elem_info->elem; 599b76550bbSJiri Pirko owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem); 600b76550bbSJiri Pirko if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 601b76550bbSJiri Pirko return NULL; 602b76550bbSJiri Pirko q->consumer_counter++; 603b76550bbSJiri Pirko rmb(); /* make sure we read owned bit before the rest of elem */ 604b76550bbSJiri Pirko return elem; 605eda6500aSJiri Pirko } 606eda6500aSJiri Pirko 607eda6500aSJiri Pirko static void mlxsw_pci_cq_tasklet(unsigned long data) 608eda6500aSJiri Pirko { 609eda6500aSJiri Pirko struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 610eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 611eda6500aSJiri Pirko char *cqe; 612eda6500aSJiri Pirko int items = 0; 613eda6500aSJiri Pirko int credits = q->count >> 1; 614eda6500aSJiri Pirko 615eda6500aSJiri Pirko while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 616eda6500aSJiri Pirko u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 617b76550bbSJiri Pirko u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 618b76550bbSJiri Pirko u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 619c9ebea04SIdo Schimmel char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; 620c9ebea04SIdo Schimmel 621c9ebea04SIdo Schimmel memcpy(ncqe, cqe, q->elem_size); 622c9ebea04SIdo Schimmel mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 623eda6500aSJiri Pirko 624eda6500aSJiri Pirko if (sendq) { 625eda6500aSJiri Pirko struct mlxsw_pci_queue *sdq; 626eda6500aSJiri Pirko 627eda6500aSJiri Pirko sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn); 628eda6500aSJiri Pirko mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 629c9ebea04SIdo Schimmel wqe_counter, ncqe); 630eda6500aSJiri Pirko q->u.cq.comp_sdq_count++; 631eda6500aSJiri Pirko } else { 632eda6500aSJiri Pirko struct mlxsw_pci_queue *rdq; 633eda6500aSJiri Pirko 634eda6500aSJiri Pirko rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn); 635eda6500aSJiri Pirko mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 636c9ebea04SIdo Schimmel wqe_counter, q->u.cq.v, ncqe); 637eda6500aSJiri Pirko q->u.cq.comp_rdq_count++; 638eda6500aSJiri Pirko } 639eda6500aSJiri Pirko if (++items == credits) 640eda6500aSJiri Pirko break; 641eda6500aSJiri Pirko } 642c9ebea04SIdo Schimmel if (items) 643eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 644eda6500aSJiri Pirko } 645eda6500aSJiri Pirko 6468404f6f2SJiri Pirko static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q) 6478404f6f2SJiri Pirko { 6488404f6f2SJiri Pirko return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT : 6498404f6f2SJiri Pirko MLXSW_PCI_CQE01_COUNT; 6508404f6f2SJiri Pirko } 6518404f6f2SJiri Pirko 6528404f6f2SJiri Pirko static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q) 6538404f6f2SJiri Pirko { 6548404f6f2SJiri Pirko return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE : 6558404f6f2SJiri Pirko MLXSW_PCI_CQE01_SIZE; 6568404f6f2SJiri Pirko } 6578404f6f2SJiri Pirko 658eda6500aSJiri Pirko static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 659eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 660eda6500aSJiri Pirko { 661eda6500aSJiri Pirko int i; 662eda6500aSJiri Pirko int err; 663eda6500aSJiri Pirko 664eda6500aSJiri Pirko q->consumer_counter = 0; 665eda6500aSJiri Pirko 666eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 667eda6500aSJiri Pirko char *elem = mlxsw_pci_queue_elem_get(q, i); 668eda6500aSJiri Pirko 669eda6500aSJiri Pirko mlxsw_pci_eqe_owner_set(elem, 1); 670eda6500aSJiri Pirko } 671eda6500aSJiri Pirko 672eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 673eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 674eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 675eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 676eda6500aSJiri Pirko dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 677eda6500aSJiri Pirko 678eda6500aSJiri Pirko mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 679eda6500aSJiri Pirko } 680eda6500aSJiri Pirko err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 681eda6500aSJiri Pirko if (err) 682eda6500aSJiri Pirko return err; 683eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 684eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 685eda6500aSJiri Pirko return 0; 686eda6500aSJiri Pirko } 687eda6500aSJiri Pirko 688eda6500aSJiri Pirko static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 689eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 690eda6500aSJiri Pirko { 691eda6500aSJiri Pirko mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 692eda6500aSJiri Pirko } 693eda6500aSJiri Pirko 694eda6500aSJiri Pirko static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) 695eda6500aSJiri Pirko { 696eda6500aSJiri Pirko mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); 697eda6500aSJiri Pirko mlxsw_pci->cmd.comp.out_param = 698eda6500aSJiri Pirko ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | 699eda6500aSJiri Pirko mlxsw_pci_eqe_cmd_out_param_l_get(eqe); 700eda6500aSJiri Pirko mlxsw_pci->cmd.wait_done = true; 701eda6500aSJiri Pirko wake_up(&mlxsw_pci->cmd.wait); 702eda6500aSJiri Pirko } 703eda6500aSJiri Pirko 704eda6500aSJiri Pirko static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 705eda6500aSJiri Pirko { 706b76550bbSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 707b76550bbSJiri Pirko char *elem; 708b76550bbSJiri Pirko bool owner_bit; 709b76550bbSJiri Pirko 710b76550bbSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 711b76550bbSJiri Pirko elem = elem_info->elem; 712b76550bbSJiri Pirko owner_bit = mlxsw_pci_eqe_owner_get(elem); 713b76550bbSJiri Pirko if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 714b76550bbSJiri Pirko return NULL; 715b76550bbSJiri Pirko q->consumer_counter++; 716b76550bbSJiri Pirko rmb(); /* make sure we read owned bit before the rest of elem */ 717b76550bbSJiri Pirko return elem; 718eda6500aSJiri Pirko } 719eda6500aSJiri Pirko 720eda6500aSJiri Pirko static void mlxsw_pci_eq_tasklet(unsigned long data) 721eda6500aSJiri Pirko { 722eda6500aSJiri Pirko struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data; 723eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = q->pci; 724e4c870b1SJiri Pirko u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci); 725e4c870b1SJiri Pirko unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 726eda6500aSJiri Pirko char *eqe; 727eda6500aSJiri Pirko u8 cqn; 728eda6500aSJiri Pirko bool cq_handle = false; 729eda6500aSJiri Pirko int items = 0; 730eda6500aSJiri Pirko int credits = q->count >> 1; 731eda6500aSJiri Pirko 732eda6500aSJiri Pirko memset(&active_cqns, 0, sizeof(active_cqns)); 733eda6500aSJiri Pirko 734eda6500aSJiri Pirko while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 735eda6500aSJiri Pirko 736f3c84a8eSNir Dotan /* Command interface completion events are always received on 737f3c84a8eSNir Dotan * queue MLXSW_PCI_EQ_ASYNC_NUM (EQ0) and completion events 738f3c84a8eSNir Dotan * are mapped to queue MLXSW_PCI_EQ_COMP_NUM (EQ1). 739f3c84a8eSNir Dotan */ 740f3c84a8eSNir Dotan switch (q->num) { 741f3c84a8eSNir Dotan case MLXSW_PCI_EQ_ASYNC_NUM: 742eda6500aSJiri Pirko mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); 743eda6500aSJiri Pirko q->u.eq.ev_cmd_count++; 744eda6500aSJiri Pirko break; 745f3c84a8eSNir Dotan case MLXSW_PCI_EQ_COMP_NUM: 746eda6500aSJiri Pirko cqn = mlxsw_pci_eqe_cqn_get(eqe); 747eda6500aSJiri Pirko set_bit(cqn, active_cqns); 748eda6500aSJiri Pirko cq_handle = true; 749eda6500aSJiri Pirko q->u.eq.ev_comp_count++; 750eda6500aSJiri Pirko break; 751eda6500aSJiri Pirko default: 752eda6500aSJiri Pirko q->u.eq.ev_other_count++; 753eda6500aSJiri Pirko } 754eda6500aSJiri Pirko if (++items == credits) 755eda6500aSJiri Pirko break; 756eda6500aSJiri Pirko } 757eda6500aSJiri Pirko if (items) { 758eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 759eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 760eda6500aSJiri Pirko } 761eda6500aSJiri Pirko 762eda6500aSJiri Pirko if (!cq_handle) 763eda6500aSJiri Pirko return; 764e4c870b1SJiri Pirko for_each_set_bit(cqn, active_cqns, cq_count) { 765eda6500aSJiri Pirko q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 766eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 767eda6500aSJiri Pirko } 768eda6500aSJiri Pirko } 769eda6500aSJiri Pirko 770eda6500aSJiri Pirko struct mlxsw_pci_queue_ops { 771eda6500aSJiri Pirko const char *name; 772eda6500aSJiri Pirko enum mlxsw_pci_queue_type type; 7738404f6f2SJiri Pirko void (*pre_init)(struct mlxsw_pci *mlxsw_pci, 7748404f6f2SJiri Pirko struct mlxsw_pci_queue *q); 775eda6500aSJiri Pirko int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 776eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 777eda6500aSJiri Pirko void (*fini)(struct mlxsw_pci *mlxsw_pci, 778eda6500aSJiri Pirko struct mlxsw_pci_queue *q); 779eda6500aSJiri Pirko void (*tasklet)(unsigned long data); 7808404f6f2SJiri Pirko u16 (*elem_count_f)(const struct mlxsw_pci_queue *q); 7818404f6f2SJiri Pirko u8 (*elem_size_f)(const struct mlxsw_pci_queue *q); 782eda6500aSJiri Pirko u16 elem_count; 783eda6500aSJiri Pirko u8 elem_size; 784eda6500aSJiri Pirko }; 785eda6500aSJiri Pirko 786eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 787eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 788eda6500aSJiri Pirko .init = mlxsw_pci_sdq_init, 789eda6500aSJiri Pirko .fini = mlxsw_pci_sdq_fini, 790eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 791eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE, 792eda6500aSJiri Pirko }; 793eda6500aSJiri Pirko 794eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 795eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 796eda6500aSJiri Pirko .init = mlxsw_pci_rdq_init, 797eda6500aSJiri Pirko .fini = mlxsw_pci_rdq_fini, 798eda6500aSJiri Pirko .elem_count = MLXSW_PCI_WQE_COUNT, 799eda6500aSJiri Pirko .elem_size = MLXSW_PCI_WQE_SIZE 800eda6500aSJiri Pirko }; 801eda6500aSJiri Pirko 802eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 803eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_CQ, 8048404f6f2SJiri Pirko .pre_init = mlxsw_pci_cq_pre_init, 805eda6500aSJiri Pirko .init = mlxsw_pci_cq_init, 806eda6500aSJiri Pirko .fini = mlxsw_pci_cq_fini, 807eda6500aSJiri Pirko .tasklet = mlxsw_pci_cq_tasklet, 8088404f6f2SJiri Pirko .elem_count_f = mlxsw_pci_cq_elem_count, 8098404f6f2SJiri Pirko .elem_size_f = mlxsw_pci_cq_elem_size 810eda6500aSJiri Pirko }; 811eda6500aSJiri Pirko 812eda6500aSJiri Pirko static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 813eda6500aSJiri Pirko .type = MLXSW_PCI_QUEUE_TYPE_EQ, 814eda6500aSJiri Pirko .init = mlxsw_pci_eq_init, 815eda6500aSJiri Pirko .fini = mlxsw_pci_eq_fini, 816eda6500aSJiri Pirko .tasklet = mlxsw_pci_eq_tasklet, 817eda6500aSJiri Pirko .elem_count = MLXSW_PCI_EQE_COUNT, 818eda6500aSJiri Pirko .elem_size = MLXSW_PCI_EQE_SIZE 819eda6500aSJiri Pirko }; 820eda6500aSJiri Pirko 821eda6500aSJiri Pirko static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 822eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 823eda6500aSJiri Pirko struct mlxsw_pci_queue *q, u8 q_num) 824eda6500aSJiri Pirko { 825eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 826eda6500aSJiri Pirko int i; 827eda6500aSJiri Pirko int err; 828eda6500aSJiri Pirko 8298404f6f2SJiri Pirko q->num = q_num; 8308404f6f2SJiri Pirko if (q_ops->pre_init) 8318404f6f2SJiri Pirko q_ops->pre_init(mlxsw_pci, q); 832b76550bbSJiri Pirko 833eda6500aSJiri Pirko spin_lock_init(&q->lock); 8348404f6f2SJiri Pirko q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) : 8358404f6f2SJiri Pirko q_ops->elem_count; 8368404f6f2SJiri Pirko q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) : 8378404f6f2SJiri Pirko q_ops->elem_size; 838eda6500aSJiri Pirko q->type = q_ops->type; 839eda6500aSJiri Pirko q->pci = mlxsw_pci; 840eda6500aSJiri Pirko 841eda6500aSJiri Pirko if (q_ops->tasklet) 842eda6500aSJiri Pirko tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q); 843eda6500aSJiri Pirko 844eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_AQ_SIZE; 845eda6500aSJiri Pirko mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 846eda6500aSJiri Pirko mem_item->size, 847eda6500aSJiri Pirko &mem_item->mapaddr); 848eda6500aSJiri Pirko if (!mem_item->buf) 849eda6500aSJiri Pirko return -ENOMEM; 850eda6500aSJiri Pirko memset(mem_item->buf, 0, mem_item->size); 851eda6500aSJiri Pirko 852eda6500aSJiri Pirko q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 853eda6500aSJiri Pirko if (!q->elem_info) { 854eda6500aSJiri Pirko err = -ENOMEM; 855eda6500aSJiri Pirko goto err_elem_info_alloc; 856eda6500aSJiri Pirko } 857eda6500aSJiri Pirko 858eda6500aSJiri Pirko /* Initialize dma mapped elements info elem_info for 859eda6500aSJiri Pirko * future easy access. 860eda6500aSJiri Pirko */ 861eda6500aSJiri Pirko for (i = 0; i < q->count; i++) { 862eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 863eda6500aSJiri Pirko 864eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_get(q, i); 865eda6500aSJiri Pirko elem_info->elem = 8668404f6f2SJiri Pirko __mlxsw_pci_queue_elem_get(q, q->elem_size, i); 867eda6500aSJiri Pirko } 868eda6500aSJiri Pirko 869eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 870eda6500aSJiri Pirko err = q_ops->init(mlxsw_pci, mbox, q); 871eda6500aSJiri Pirko if (err) 872eda6500aSJiri Pirko goto err_q_ops_init; 873eda6500aSJiri Pirko return 0; 874eda6500aSJiri Pirko 875eda6500aSJiri Pirko err_q_ops_init: 876eda6500aSJiri Pirko kfree(q->elem_info); 877eda6500aSJiri Pirko err_elem_info_alloc: 878eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 879eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 880eda6500aSJiri Pirko return err; 881eda6500aSJiri Pirko } 882eda6500aSJiri Pirko 883eda6500aSJiri Pirko static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 884eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 885eda6500aSJiri Pirko struct mlxsw_pci_queue *q) 886eda6500aSJiri Pirko { 887eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 888eda6500aSJiri Pirko 889eda6500aSJiri Pirko q_ops->fini(mlxsw_pci, q); 890eda6500aSJiri Pirko kfree(q->elem_info); 891eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 892eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 893eda6500aSJiri Pirko } 894eda6500aSJiri Pirko 895eda6500aSJiri Pirko static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 896eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops, 897eda6500aSJiri Pirko u8 num_qs) 898eda6500aSJiri Pirko { 899eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 900eda6500aSJiri Pirko int i; 901eda6500aSJiri Pirko int err; 902eda6500aSJiri Pirko 903eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 904eda6500aSJiri Pirko queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 905eda6500aSJiri Pirko if (!queue_group->q) 906eda6500aSJiri Pirko return -ENOMEM; 907eda6500aSJiri Pirko 908eda6500aSJiri Pirko for (i = 0; i < num_qs; i++) { 909eda6500aSJiri Pirko err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 910eda6500aSJiri Pirko &queue_group->q[i], i); 911eda6500aSJiri Pirko if (err) 912eda6500aSJiri Pirko goto err_queue_init; 913eda6500aSJiri Pirko } 914eda6500aSJiri Pirko queue_group->count = num_qs; 915eda6500aSJiri Pirko 916eda6500aSJiri Pirko return 0; 917eda6500aSJiri Pirko 918eda6500aSJiri Pirko err_queue_init: 919eda6500aSJiri Pirko for (i--; i >= 0; i--) 920eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 921eda6500aSJiri Pirko kfree(queue_group->q); 922eda6500aSJiri Pirko return err; 923eda6500aSJiri Pirko } 924eda6500aSJiri Pirko 925eda6500aSJiri Pirko static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 926eda6500aSJiri Pirko const struct mlxsw_pci_queue_ops *q_ops) 927eda6500aSJiri Pirko { 928eda6500aSJiri Pirko struct mlxsw_pci_queue_type_group *queue_group; 929eda6500aSJiri Pirko int i; 930eda6500aSJiri Pirko 931eda6500aSJiri Pirko queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 932eda6500aSJiri Pirko for (i = 0; i < queue_group->count; i++) 933eda6500aSJiri Pirko mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 934eda6500aSJiri Pirko kfree(queue_group->q); 935eda6500aSJiri Pirko } 936eda6500aSJiri Pirko 937eda6500aSJiri Pirko static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 938eda6500aSJiri Pirko { 939eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 940eda6500aSJiri Pirko u8 num_sdqs; 941eda6500aSJiri Pirko u8 sdq_log2sz; 942eda6500aSJiri Pirko u8 num_rdqs; 943eda6500aSJiri Pirko u8 rdq_log2sz; 944eda6500aSJiri Pirko u8 num_cqs; 945eda6500aSJiri Pirko u8 cq_log2sz; 94641107685SJiri Pirko u8 cqv2_log2sz; 947eda6500aSJiri Pirko u8 num_eqs; 948eda6500aSJiri Pirko u8 eq_log2sz; 949eda6500aSJiri Pirko int err; 950eda6500aSJiri Pirko 951eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 952eda6500aSJiri Pirko err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 953eda6500aSJiri Pirko if (err) 954eda6500aSJiri Pirko return err; 955eda6500aSJiri Pirko 956eda6500aSJiri Pirko num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 957eda6500aSJiri Pirko sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 958eda6500aSJiri Pirko num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 959eda6500aSJiri Pirko rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 960eda6500aSJiri Pirko num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 961eda6500aSJiri Pirko cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 96241107685SJiri Pirko cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox); 963eda6500aSJiri Pirko num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 964eda6500aSJiri Pirko eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 965eda6500aSJiri Pirko 966c85c3882SJiri Pirko if (num_sdqs + num_rdqs > num_cqs || 967e4c870b1SJiri Pirko num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) { 968eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of queues\n"); 969eda6500aSJiri Pirko return -EINVAL; 970eda6500aSJiri Pirko } 971eda6500aSJiri Pirko 972eda6500aSJiri Pirko if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 973eda6500aSJiri Pirko (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 974b76550bbSJiri Pirko (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) || 97541107685SJiri Pirko (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 && 97641107685SJiri Pirko (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) || 977eda6500aSJiri Pirko (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 978eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 979eda6500aSJiri Pirko return -EINVAL; 980eda6500aSJiri Pirko } 981eda6500aSJiri Pirko 9828404f6f2SJiri Pirko mlxsw_pci->num_sdq_cqs = num_sdqs; 9838404f6f2SJiri Pirko 984eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 985eda6500aSJiri Pirko num_eqs); 986eda6500aSJiri Pirko if (err) { 987eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize event queues\n"); 988eda6500aSJiri Pirko return err; 989eda6500aSJiri Pirko } 990eda6500aSJiri Pirko 991eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 992eda6500aSJiri Pirko num_cqs); 993eda6500aSJiri Pirko if (err) { 994eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 995eda6500aSJiri Pirko goto err_cqs_init; 996eda6500aSJiri Pirko } 997eda6500aSJiri Pirko 998eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 999eda6500aSJiri Pirko num_sdqs); 1000eda6500aSJiri Pirko if (err) { 1001eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1002eda6500aSJiri Pirko goto err_sdqs_init; 1003eda6500aSJiri Pirko } 1004eda6500aSJiri Pirko 1005eda6500aSJiri Pirko err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1006eda6500aSJiri Pirko num_rdqs); 1007eda6500aSJiri Pirko if (err) { 1008eda6500aSJiri Pirko dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1009eda6500aSJiri Pirko goto err_rdqs_init; 1010eda6500aSJiri Pirko } 1011eda6500aSJiri Pirko 1012eda6500aSJiri Pirko /* We have to poll in command interface until queues are initialized */ 1013eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = true; 1014eda6500aSJiri Pirko return 0; 1015eda6500aSJiri Pirko 1016eda6500aSJiri Pirko err_rdqs_init: 1017eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1018eda6500aSJiri Pirko err_sdqs_init: 1019eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1020eda6500aSJiri Pirko err_cqs_init: 1021eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1022eda6500aSJiri Pirko return err; 1023eda6500aSJiri Pirko } 1024eda6500aSJiri Pirko 1025eda6500aSJiri Pirko static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1026eda6500aSJiri Pirko { 1027eda6500aSJiri Pirko mlxsw_pci->cmd.nopoll = false; 1028eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1029eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1030eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1031eda6500aSJiri Pirko mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1032eda6500aSJiri Pirko } 1033eda6500aSJiri Pirko 1034eda6500aSJiri Pirko static void 1035eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1036eda6500aSJiri Pirko char *mbox, int index, 1037eda6500aSJiri Pirko const struct mlxsw_swid_config *swid) 1038eda6500aSJiri Pirko { 1039eda6500aSJiri Pirko u8 mask = 0; 1040eda6500aSJiri Pirko 1041eda6500aSJiri Pirko if (swid->used_type) { 1042eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1043eda6500aSJiri Pirko mbox, index, swid->type); 1044eda6500aSJiri Pirko mask |= 1; 1045eda6500aSJiri Pirko } 1046eda6500aSJiri Pirko if (swid->used_properties) { 1047eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1048eda6500aSJiri Pirko mbox, index, swid->properties); 1049eda6500aSJiri Pirko mask |= 2; 1050eda6500aSJiri Pirko } 1051eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1052eda6500aSJiri Pirko } 1053eda6500aSJiri Pirko 1054c1a38311SJiri Pirko static int 1055e21d21caSArkadi Sharshevsky mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci, 1056e21d21caSArkadi Sharshevsky const struct mlxsw_config_profile *profile, 1057c1a38311SJiri Pirko struct mlxsw_res *res) 1058403547d3SNogah Frankel { 1059e21d21caSArkadi Sharshevsky u64 single_size, double_size, linear_size; 1060e21d21caSArkadi Sharshevsky int err; 1061403547d3SNogah Frankel 1062e21d21caSArkadi Sharshevsky err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile, 1063e21d21caSArkadi Sharshevsky &single_size, &double_size, 1064e21d21caSArkadi Sharshevsky &linear_size); 1065e21d21caSArkadi Sharshevsky if (err) 1066e21d21caSArkadi Sharshevsky return err; 1067403547d3SNogah Frankel 1068c1a38311SJiri Pirko MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size); 1069c1a38311SJiri Pirko MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size); 1070c1a38311SJiri Pirko MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size); 1071403547d3SNogah Frankel 1072403547d3SNogah Frankel return 0; 1073403547d3SNogah Frankel } 1074403547d3SNogah Frankel 1075eda6500aSJiri Pirko static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1076403547d3SNogah Frankel const struct mlxsw_config_profile *profile, 1077c1a38311SJiri Pirko struct mlxsw_res *res) 1078eda6500aSJiri Pirko { 1079eda6500aSJiri Pirko int i; 1080403547d3SNogah Frankel int err; 1081eda6500aSJiri Pirko 1082eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1083eda6500aSJiri Pirko 1084eda6500aSJiri Pirko if (profile->used_max_vepa_channels) { 1085eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1086eda6500aSJiri Pirko mbox, 1); 1087eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1088eda6500aSJiri Pirko mbox, profile->max_vepa_channels); 1089eda6500aSJiri Pirko } 1090eda6500aSJiri Pirko if (profile->used_max_mid) { 1091eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1092eda6500aSJiri Pirko mbox, 1); 1093eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_mid_set( 1094eda6500aSJiri Pirko mbox, profile->max_mid); 1095eda6500aSJiri Pirko } 1096eda6500aSJiri Pirko if (profile->used_max_pgt) { 1097eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1098eda6500aSJiri Pirko mbox, 1); 1099eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pgt_set( 1100eda6500aSJiri Pirko mbox, profile->max_pgt); 1101eda6500aSJiri Pirko } 1102eda6500aSJiri Pirko if (profile->used_max_system_port) { 1103eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1104eda6500aSJiri Pirko mbox, 1); 1105eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_system_port_set( 1106eda6500aSJiri Pirko mbox, profile->max_system_port); 1107eda6500aSJiri Pirko } 1108eda6500aSJiri Pirko if (profile->used_max_vlan_groups) { 1109eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1110eda6500aSJiri Pirko mbox, 1); 1111eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1112eda6500aSJiri Pirko mbox, profile->max_vlan_groups); 1113eda6500aSJiri Pirko } 1114eda6500aSJiri Pirko if (profile->used_max_regions) { 1115eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1116eda6500aSJiri Pirko mbox, 1); 1117eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_regions_set( 1118eda6500aSJiri Pirko mbox, profile->max_regions); 1119eda6500aSJiri Pirko } 1120eda6500aSJiri Pirko if (profile->used_flood_tables) { 1121eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1122eda6500aSJiri Pirko mbox, 1); 1123eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1124eda6500aSJiri Pirko mbox, profile->max_flood_tables); 1125eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1126eda6500aSJiri Pirko mbox, profile->max_vid_flood_tables); 112712fd35abSIdo Schimmel mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 112812fd35abSIdo Schimmel mbox, profile->max_fid_offset_flood_tables); 112912fd35abSIdo Schimmel mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 113012fd35abSIdo Schimmel mbox, profile->fid_offset_flood_table_size); 1131453b6a8dSIdo Schimmel mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1132453b6a8dSIdo Schimmel mbox, profile->max_fid_flood_tables); 1133453b6a8dSIdo Schimmel mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1134453b6a8dSIdo Schimmel mbox, profile->fid_flood_table_size); 1135eda6500aSJiri Pirko } 1136eda6500aSJiri Pirko if (profile->used_flood_mode) { 1137eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1138eda6500aSJiri Pirko mbox, 1); 1139eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_flood_mode_set( 1140eda6500aSJiri Pirko mbox, profile->flood_mode); 1141eda6500aSJiri Pirko } 1142eda6500aSJiri Pirko if (profile->used_max_ib_mc) { 1143eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1144eda6500aSJiri Pirko mbox, 1); 1145eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1146eda6500aSJiri Pirko mbox, profile->max_ib_mc); 1147eda6500aSJiri Pirko } 1148eda6500aSJiri Pirko if (profile->used_max_pkey) { 1149eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1150eda6500aSJiri Pirko mbox, 1); 1151eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_max_pkey_set( 1152eda6500aSJiri Pirko mbox, profile->max_pkey); 1153eda6500aSJiri Pirko } 1154eda6500aSJiri Pirko if (profile->used_ar_sec) { 1155eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1156eda6500aSJiri Pirko mbox, 1); 1157eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_ar_sec_set( 1158eda6500aSJiri Pirko mbox, profile->ar_sec); 1159eda6500aSJiri Pirko } 1160eda6500aSJiri Pirko if (profile->used_adaptive_routing_group_cap) { 1161eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1162eda6500aSJiri Pirko mbox, 1); 1163eda6500aSJiri Pirko mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1164eda6500aSJiri Pirko mbox, profile->adaptive_routing_group_cap); 1165eda6500aSJiri Pirko } 1166110d2d21SJiri Pirko if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) { 1167e21d21caSArkadi Sharshevsky err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res); 1168403547d3SNogah Frankel if (err) 1169403547d3SNogah Frankel return err; 1170403547d3SNogah Frankel 1171403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1); 1172403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox, 1173c1a38311SJiri Pirko MLXSW_RES_GET(res, KVD_LINEAR_SIZE)); 1174403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox, 1175403547d3SNogah Frankel 1); 1176403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox, 1177c1a38311SJiri Pirko MLXSW_RES_GET(res, KVD_SINGLE_SIZE)); 1178489107bdSJiri Pirko mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set( 1179489107bdSJiri Pirko mbox, 1); 1180403547d3SNogah Frankel mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox, 1181c1a38311SJiri Pirko MLXSW_RES_GET(res, KVD_DOUBLE_SIZE)); 1182489107bdSJiri Pirko } 1183eda6500aSJiri Pirko 1184eda6500aSJiri Pirko for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1185eda6500aSJiri Pirko mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1186eda6500aSJiri Pirko &profile->swid_config[i]); 1187eda6500aSJiri Pirko 11888404f6f2SJiri Pirko if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) { 11898404f6f2SJiri Pirko mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1); 11908404f6f2SJiri Pirko mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1); 11918404f6f2SJiri Pirko } 11928404f6f2SJiri Pirko 1193eda6500aSJiri Pirko return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1194eda6500aSJiri Pirko } 1195eda6500aSJiri Pirko 1196eda6500aSJiri Pirko static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1197eda6500aSJiri Pirko { 1198eda6500aSJiri Pirko struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1199eda6500aSJiri Pirko int err; 1200eda6500aSJiri Pirko 1201eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1202eda6500aSJiri Pirko err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1203eda6500aSJiri Pirko if (err) 1204eda6500aSJiri Pirko return err; 1205eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1206eda6500aSJiri Pirko mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1207eda6500aSJiri Pirko return 0; 1208eda6500aSJiri Pirko } 1209eda6500aSJiri Pirko 1210eda6500aSJiri Pirko static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1211eda6500aSJiri Pirko u16 num_pages) 1212eda6500aSJiri Pirko { 1213eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 12143e2206daSJiri Pirko int nent = 0; 1215eda6500aSJiri Pirko int i; 1216eda6500aSJiri Pirko int err; 1217eda6500aSJiri Pirko 1218eda6500aSJiri Pirko mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1219eda6500aSJiri Pirko GFP_KERNEL); 1220eda6500aSJiri Pirko if (!mlxsw_pci->fw_area.items) 1221eda6500aSJiri Pirko return -ENOMEM; 12223e2206daSJiri Pirko mlxsw_pci->fw_area.count = num_pages; 1223eda6500aSJiri Pirko 1224eda6500aSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 1225eda6500aSJiri Pirko for (i = 0; i < num_pages; i++) { 1226eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1227eda6500aSJiri Pirko 1228eda6500aSJiri Pirko mem_item->size = MLXSW_PCI_PAGE_SIZE; 1229eda6500aSJiri Pirko mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev, 1230eda6500aSJiri Pirko mem_item->size, 1231eda6500aSJiri Pirko &mem_item->mapaddr); 1232eda6500aSJiri Pirko if (!mem_item->buf) { 1233eda6500aSJiri Pirko err = -ENOMEM; 1234eda6500aSJiri Pirko goto err_alloc; 1235eda6500aSJiri Pirko } 12363e2206daSJiri Pirko mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 12373e2206daSJiri Pirko mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 12383e2206daSJiri Pirko if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 12393e2206daSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1240eda6500aSJiri Pirko if (err) 1241eda6500aSJiri Pirko goto err_cmd_map_fa; 12423e2206daSJiri Pirko nent = 0; 12433e2206daSJiri Pirko mlxsw_cmd_mbox_zero(mbox); 12443e2206daSJiri Pirko } 12453e2206daSJiri Pirko } 12463e2206daSJiri Pirko 12473e2206daSJiri Pirko if (nent) { 12483e2206daSJiri Pirko err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 12493e2206daSJiri Pirko if (err) 12503e2206daSJiri Pirko goto err_cmd_map_fa; 12513e2206daSJiri Pirko } 1252eda6500aSJiri Pirko 1253eda6500aSJiri Pirko return 0; 1254eda6500aSJiri Pirko 1255eda6500aSJiri Pirko err_cmd_map_fa: 1256eda6500aSJiri Pirko err_alloc: 1257eda6500aSJiri Pirko for (i--; i >= 0; i--) { 1258eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1259eda6500aSJiri Pirko 1260eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1261eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1262eda6500aSJiri Pirko } 1263eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1264eda6500aSJiri Pirko return err; 1265eda6500aSJiri Pirko } 1266eda6500aSJiri Pirko 1267eda6500aSJiri Pirko static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1268eda6500aSJiri Pirko { 1269eda6500aSJiri Pirko struct mlxsw_pci_mem_item *mem_item; 1270eda6500aSJiri Pirko int i; 1271eda6500aSJiri Pirko 1272eda6500aSJiri Pirko mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1273eda6500aSJiri Pirko 12743e2206daSJiri Pirko for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1275eda6500aSJiri Pirko mem_item = &mlxsw_pci->fw_area.items[i]; 1276eda6500aSJiri Pirko 1277eda6500aSJiri Pirko pci_free_consistent(mlxsw_pci->pdev, mem_item->size, 1278eda6500aSJiri Pirko mem_item->buf, mem_item->mapaddr); 1279eda6500aSJiri Pirko } 1280eda6500aSJiri Pirko kfree(mlxsw_pci->fw_area.items); 1281eda6500aSJiri Pirko } 1282eda6500aSJiri Pirko 1283eda6500aSJiri Pirko static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1284eda6500aSJiri Pirko { 1285eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = dev_id; 1286eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1287eda6500aSJiri Pirko int i; 1288eda6500aSJiri Pirko 1289eda6500aSJiri Pirko for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) { 1290eda6500aSJiri Pirko q = mlxsw_pci_eq_get(mlxsw_pci, i); 1291eda6500aSJiri Pirko mlxsw_pci_queue_tasklet_schedule(q); 1292eda6500aSJiri Pirko } 1293eda6500aSJiri Pirko return IRQ_HANDLED; 1294eda6500aSJiri Pirko } 1295eda6500aSJiri Pirko 12961e81779aSIdo Schimmel static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 12971e81779aSIdo Schimmel struct mlxsw_pci_mem_item *mbox) 12981e81779aSIdo Schimmel { 12991e81779aSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 13001e81779aSIdo Schimmel int err = 0; 13011e81779aSIdo Schimmel 13021e81779aSIdo Schimmel mbox->size = MLXSW_CMD_MBOX_SIZE; 13031e81779aSIdo Schimmel mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE, 13041e81779aSIdo Schimmel &mbox->mapaddr); 13051e81779aSIdo Schimmel if (!mbox->buf) { 13061e81779aSIdo Schimmel dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 13071e81779aSIdo Schimmel err = -ENOMEM; 13081e81779aSIdo Schimmel } 13091e81779aSIdo Schimmel 13101e81779aSIdo Schimmel return err; 13111e81779aSIdo Schimmel } 13121e81779aSIdo Schimmel 13131e81779aSIdo Schimmel static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 13141e81779aSIdo Schimmel struct mlxsw_pci_mem_item *mbox) 13151e81779aSIdo Schimmel { 13161e81779aSIdo Schimmel struct pci_dev *pdev = mlxsw_pci->pdev; 13171e81779aSIdo Schimmel 13181e81779aSIdo Schimmel pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 13191e81779aSIdo Schimmel mbox->mapaddr); 13201e81779aSIdo Schimmel } 13211e81779aSIdo Schimmel 1322f3a52c61SJiri Pirko static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, 1323f3a52c61SJiri Pirko const struct pci_device_id *id) 1324f3a52c61SJiri Pirko { 1325f3a52c61SJiri Pirko unsigned long end; 1326f3a52c61SJiri Pirko char mrsr_pl[MLXSW_REG_MRSR_LEN]; 1327f3a52c61SJiri Pirko int err; 1328f3a52c61SJiri Pirko 1329f3a52c61SJiri Pirko mlxsw_reg_mrsr_pack(mrsr_pl); 1330f3a52c61SJiri Pirko err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 1331f3a52c61SJiri Pirko if (err) 1332f3a52c61SJiri Pirko return err; 1333f3a52c61SJiri Pirko if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) { 1334f3a52c61SJiri Pirko msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1335f3a52c61SJiri Pirko return 0; 1336f3a52c61SJiri Pirko } 1337f3a52c61SJiri Pirko 1338f3a52c61SJiri Pirko /* We must wait for the HW to become responsive once again. */ 1339f3a52c61SJiri Pirko msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS); 1340f3a52c61SJiri Pirko 1341f3a52c61SJiri Pirko end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1342f3a52c61SJiri Pirko do { 1343f3a52c61SJiri Pirko u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1344f3a52c61SJiri Pirko 1345f3a52c61SJiri Pirko if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 134667c14cc9SNir Dotan return 0; 1347f3a52c61SJiri Pirko cond_resched(); 1348f3a52c61SJiri Pirko } while (time_before(jiffies, end)); 134967c14cc9SNir Dotan return -EBUSY; 1350f3a52c61SJiri Pirko } 1351f3a52c61SJiri Pirko 1352f3a52c61SJiri Pirko static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1353f3a52c61SJiri Pirko { 1354f3a52c61SJiri Pirko int err; 1355f3a52c61SJiri Pirko 1356f3a52c61SJiri Pirko err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX); 1357f3a52c61SJiri Pirko if (err < 0) 1358f3a52c61SJiri Pirko dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n"); 1359f3a52c61SJiri Pirko return err; 1360f3a52c61SJiri Pirko } 1361f3a52c61SJiri Pirko 1362f3a52c61SJiri Pirko static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1363f3a52c61SJiri Pirko { 1364f3a52c61SJiri Pirko pci_free_irq_vectors(mlxsw_pci->pdev); 1365f3a52c61SJiri Pirko } 1366f3a52c61SJiri Pirko 1367eda6500aSJiri Pirko static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 136857d316baSNogah Frankel const struct mlxsw_config_profile *profile, 1369c1a38311SJiri Pirko struct mlxsw_res *res) 1370eda6500aSJiri Pirko { 1371eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1372eda6500aSJiri Pirko struct pci_dev *pdev = mlxsw_pci->pdev; 1373eda6500aSJiri Pirko char *mbox; 1374eda6500aSJiri Pirko u16 num_pages; 1375eda6500aSJiri Pirko int err; 1376eda6500aSJiri Pirko 1377eda6500aSJiri Pirko mutex_init(&mlxsw_pci->cmd.lock); 1378eda6500aSJiri Pirko init_waitqueue_head(&mlxsw_pci->cmd.wait); 1379eda6500aSJiri Pirko 1380eda6500aSJiri Pirko mlxsw_pci->core = mlxsw_core; 1381eda6500aSJiri Pirko 1382eda6500aSJiri Pirko mbox = mlxsw_cmd_mbox_alloc(); 1383eda6500aSJiri Pirko if (!mbox) 1384eda6500aSJiri Pirko return -ENOMEM; 13851e81779aSIdo Schimmel 13861e81779aSIdo Schimmel err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 13871e81779aSIdo Schimmel if (err) 13881e81779aSIdo Schimmel goto mbox_put; 13891e81779aSIdo Schimmel 13901e81779aSIdo Schimmel err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 13911e81779aSIdo Schimmel if (err) 13921e81779aSIdo Schimmel goto err_out_mbox_alloc; 13931e81779aSIdo Schimmel 1394f3a52c61SJiri Pirko err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id); 1395f3a52c61SJiri Pirko if (err) 1396f3a52c61SJiri Pirko goto err_sw_reset; 1397f3a52c61SJiri Pirko 1398f3a52c61SJiri Pirko err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); 1399f3a52c61SJiri Pirko if (err < 0) { 1400f3a52c61SJiri Pirko dev_err(&pdev->dev, "MSI-X init failed\n"); 1401f3a52c61SJiri Pirko goto err_alloc_irq; 1402f3a52c61SJiri Pirko } 1403f3a52c61SJiri Pirko 1404eda6500aSJiri Pirko err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1405eda6500aSJiri Pirko if (err) 1406eda6500aSJiri Pirko goto err_query_fw; 1407eda6500aSJiri Pirko 1408eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.major = 1409eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1410eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.minor = 1411eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1412eda6500aSJiri Pirko mlxsw_pci->bus_info.fw_rev.subminor = 1413eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1414eda6500aSJiri Pirko 1415eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1416eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1417eda6500aSJiri Pirko err = -EINVAL; 1418eda6500aSJiri Pirko goto err_iface_rev; 1419eda6500aSJiri Pirko } 1420eda6500aSJiri Pirko if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1421eda6500aSJiri Pirko dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1422eda6500aSJiri Pirko err = -EINVAL; 1423eda6500aSJiri Pirko goto err_doorbell_page_bar; 1424eda6500aSJiri Pirko } 1425eda6500aSJiri Pirko 1426eda6500aSJiri Pirko mlxsw_pci->doorbell_offset = 1427eda6500aSJiri Pirko mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1428eda6500aSJiri Pirko 14298289169dSShalom Toledo if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) { 14308289169dSShalom Toledo dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n"); 14318289169dSShalom Toledo err = -EINVAL; 14328289169dSShalom Toledo goto err_fr_rn_clk_bar; 14338289169dSShalom Toledo } 14348289169dSShalom Toledo 14358289169dSShalom Toledo mlxsw_pci->free_running_clock_offset = 14368289169dSShalom Toledo mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox); 14378289169dSShalom Toledo 1438eda6500aSJiri Pirko num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1439eda6500aSJiri Pirko err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1440eda6500aSJiri Pirko if (err) 1441eda6500aSJiri Pirko goto err_fw_area_init; 1442eda6500aSJiri Pirko 1443eda6500aSJiri Pirko err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1444eda6500aSJiri Pirko if (err) 1445eda6500aSJiri Pirko goto err_boardinfo; 1446eda6500aSJiri Pirko 1447e5ba7803SVadim Pasternak err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 144857d316baSNogah Frankel if (err) 144957d316baSNogah Frankel goto err_query_resources; 145057d316baSNogah Frankel 14518404f6f2SJiri Pirko if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) && 14528404f6f2SJiri Pirko MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) 14538404f6f2SJiri Pirko mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2; 14548404f6f2SJiri Pirko else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) && 14558404f6f2SJiri Pirko MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) 14568404f6f2SJiri Pirko mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1; 14578404f6f2SJiri Pirko else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) && 14588404f6f2SJiri Pirko MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || 14598404f6f2SJiri Pirko !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) { 14608404f6f2SJiri Pirko mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0; 14618404f6f2SJiri Pirko } else { 14628404f6f2SJiri Pirko dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n"); 14638404f6f2SJiri Pirko goto err_cqe_v_check; 14648404f6f2SJiri Pirko } 14658404f6f2SJiri Pirko 1466c1a38311SJiri Pirko err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res); 1467eda6500aSJiri Pirko if (err) 1468eda6500aSJiri Pirko goto err_config_profile; 1469eda6500aSJiri Pirko 1470eda6500aSJiri Pirko err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1471eda6500aSJiri Pirko if (err) 1472eda6500aSJiri Pirko goto err_aqs_init; 1473eda6500aSJiri Pirko 14743680b1f6SChristoph Hellwig err = request_irq(pci_irq_vector(pdev, 0), 1475eda6500aSJiri Pirko mlxsw_pci_eq_irq_handler, 0, 14761d20d23cSJiri Pirko mlxsw_pci->bus_info.device_kind, mlxsw_pci); 1477eda6500aSJiri Pirko if (err) { 1478eda6500aSJiri Pirko dev_err(&pdev->dev, "IRQ request failed\n"); 1479eda6500aSJiri Pirko goto err_request_eq_irq; 1480eda6500aSJiri Pirko } 1481eda6500aSJiri Pirko 1482eda6500aSJiri Pirko goto mbox_put; 1483eda6500aSJiri Pirko 1484eda6500aSJiri Pirko err_request_eq_irq: 1485eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1486eda6500aSJiri Pirko err_aqs_init: 1487eda6500aSJiri Pirko err_config_profile: 14888404f6f2SJiri Pirko err_cqe_v_check: 148957d316baSNogah Frankel err_query_resources: 1490eda6500aSJiri Pirko err_boardinfo: 1491eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1492eda6500aSJiri Pirko err_fw_area_init: 14938289169dSShalom Toledo err_fr_rn_clk_bar: 1494eda6500aSJiri Pirko err_doorbell_page_bar: 1495eda6500aSJiri Pirko err_iface_rev: 1496eda6500aSJiri Pirko err_query_fw: 1497f3a52c61SJiri Pirko mlxsw_pci_free_irq_vectors(mlxsw_pci); 1498f3a52c61SJiri Pirko err_alloc_irq: 1499f3a52c61SJiri Pirko err_sw_reset: 15001e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 15011e81779aSIdo Schimmel err_out_mbox_alloc: 15021e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1503eda6500aSJiri Pirko mbox_put: 1504eda6500aSJiri Pirko mlxsw_cmd_mbox_free(mbox); 1505eda6500aSJiri Pirko return err; 1506eda6500aSJiri Pirko } 1507eda6500aSJiri Pirko 1508eda6500aSJiri Pirko static void mlxsw_pci_fini(void *bus_priv) 1509eda6500aSJiri Pirko { 1510eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1511eda6500aSJiri Pirko 15123680b1f6SChristoph Hellwig free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 1513eda6500aSJiri Pirko mlxsw_pci_aqs_fini(mlxsw_pci); 1514eda6500aSJiri Pirko mlxsw_pci_fw_area_fini(mlxsw_pci); 1515f3a52c61SJiri Pirko mlxsw_pci_free_irq_vectors(mlxsw_pci); 15161e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 15171e81779aSIdo Schimmel mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 1518eda6500aSJiri Pirko } 1519eda6500aSJiri Pirko 1520eda6500aSJiri Pirko static struct mlxsw_pci_queue * 1521eda6500aSJiri Pirko mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1522eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1523eda6500aSJiri Pirko { 1524eda6500aSJiri Pirko u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci); 1525eda6500aSJiri Pirko 1526eda6500aSJiri Pirko return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1527eda6500aSJiri Pirko } 1528eda6500aSJiri Pirko 1529d003462aSIdo Schimmel static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1530d003462aSIdo Schimmel const struct mlxsw_tx_info *tx_info) 1531d003462aSIdo Schimmel { 1532d003462aSIdo Schimmel struct mlxsw_pci *mlxsw_pci = bus_priv; 1533d003462aSIdo Schimmel struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1534d003462aSIdo Schimmel 1535d003462aSIdo Schimmel return !mlxsw_pci_queue_elem_info_producer_get(q); 1536d003462aSIdo Schimmel } 1537d003462aSIdo Schimmel 1538eda6500aSJiri Pirko static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1539eda6500aSJiri Pirko const struct mlxsw_tx_info *tx_info) 1540eda6500aSJiri Pirko { 1541eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1542eda6500aSJiri Pirko struct mlxsw_pci_queue *q; 1543eda6500aSJiri Pirko struct mlxsw_pci_queue_elem_info *elem_info; 1544eda6500aSJiri Pirko char *wqe; 1545eda6500aSJiri Pirko int i; 1546eda6500aSJiri Pirko int err; 1547eda6500aSJiri Pirko 1548eda6500aSJiri Pirko if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1549eda6500aSJiri Pirko err = skb_linearize(skb); 1550eda6500aSJiri Pirko if (err) 1551eda6500aSJiri Pirko return err; 1552eda6500aSJiri Pirko } 1553eda6500aSJiri Pirko 1554eda6500aSJiri Pirko q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1555eda6500aSJiri Pirko spin_lock_bh(&q->lock); 1556eda6500aSJiri Pirko elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1557eda6500aSJiri Pirko if (!elem_info) { 1558eda6500aSJiri Pirko /* queue is full */ 1559eda6500aSJiri Pirko err = -EAGAIN; 1560eda6500aSJiri Pirko goto unlock; 1561eda6500aSJiri Pirko } 15620714256cSPetr Machata mlxsw_skb_cb(skb)->tx_info = *tx_info; 1563eda6500aSJiri Pirko elem_info->u.sdq.skb = skb; 1564eda6500aSJiri Pirko 1565eda6500aSJiri Pirko wqe = elem_info->elem; 1566eda6500aSJiri Pirko mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 1567eda6500aSJiri Pirko mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad); 1568eda6500aSJiri Pirko mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 1569eda6500aSJiri Pirko 1570eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 1571eda6500aSJiri Pirko skb_headlen(skb), DMA_TO_DEVICE); 1572eda6500aSJiri Pirko if (err) 1573eda6500aSJiri Pirko goto unlock; 1574eda6500aSJiri Pirko 1575eda6500aSJiri Pirko for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1576eda6500aSJiri Pirko const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1577eda6500aSJiri Pirko 1578eda6500aSJiri Pirko err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 1579eda6500aSJiri Pirko skb_frag_address(frag), 1580eda6500aSJiri Pirko skb_frag_size(frag), 1581eda6500aSJiri Pirko DMA_TO_DEVICE); 1582eda6500aSJiri Pirko if (err) 1583eda6500aSJiri Pirko goto unmap_frags; 1584eda6500aSJiri Pirko } 1585eda6500aSJiri Pirko 15860714256cSPetr Machata if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 15870714256cSPetr Machata skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 15880714256cSPetr Machata 1589eda6500aSJiri Pirko /* Set unused sq entries byte count to zero. */ 1590eda6500aSJiri Pirko for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 1591eda6500aSJiri Pirko mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 1592eda6500aSJiri Pirko 1593eda6500aSJiri Pirko /* Everything is set up, ring producer doorbell to get HW going */ 1594eda6500aSJiri Pirko q->producer_counter++; 1595eda6500aSJiri Pirko mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 1596eda6500aSJiri Pirko 1597eda6500aSJiri Pirko goto unlock; 1598eda6500aSJiri Pirko 1599eda6500aSJiri Pirko unmap_frags: 1600eda6500aSJiri Pirko for (; i >= 0; i--) 1601eda6500aSJiri Pirko mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 1602eda6500aSJiri Pirko unlock: 1603eda6500aSJiri Pirko spin_unlock_bh(&q->lock); 1604eda6500aSJiri Pirko return err; 1605eda6500aSJiri Pirko } 1606eda6500aSJiri Pirko 1607eda6500aSJiri Pirko static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 1608eda6500aSJiri Pirko u32 in_mod, bool out_mbox_direct, 1609eda6500aSJiri Pirko char *in_mbox, size_t in_mbox_size, 1610eda6500aSJiri Pirko char *out_mbox, size_t out_mbox_size, 1611eda6500aSJiri Pirko u8 *p_status) 1612eda6500aSJiri Pirko { 1613eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = bus_priv; 1614830a8b1bSShalom Toledo dma_addr_t in_mapaddr = 0, out_mapaddr = 0; 1615eda6500aSJiri Pirko bool evreq = mlxsw_pci->cmd.nopoll; 1616eda6500aSJiri Pirko unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 1617eda6500aSJiri Pirko bool *p_wait_done = &mlxsw_pci->cmd.wait_done; 1618eda6500aSJiri Pirko int err; 1619eda6500aSJiri Pirko 1620eda6500aSJiri Pirko *p_status = MLXSW_CMD_STATUS_OK; 1621eda6500aSJiri Pirko 1622eda6500aSJiri Pirko err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 1623eda6500aSJiri Pirko if (err) 1624eda6500aSJiri Pirko return err; 1625eda6500aSJiri Pirko 1626830a8b1bSShalom Toledo if (in_mbox) { 16271e81779aSIdo Schimmel memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 1628830a8b1bSShalom Toledo in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 1629830a8b1bSShalom Toledo } 1630bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 1631bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 1632eda6500aSJiri Pirko 1633830a8b1bSShalom Toledo if (out_mbox) 1634830a8b1bSShalom Toledo out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 1635bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 1636bcb9db49SArnd Bergmann mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 1637eda6500aSJiri Pirko 1638eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 1639eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 1640eda6500aSJiri Pirko 1641eda6500aSJiri Pirko *p_wait_done = false; 1642eda6500aSJiri Pirko 1643eda6500aSJiri Pirko wmb(); /* all needs to be written before we write control register */ 1644eda6500aSJiri Pirko mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 1645eda6500aSJiri Pirko MLXSW_PCI_CIR_CTRL_GO_BIT | 1646eda6500aSJiri Pirko (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) | 1647eda6500aSJiri Pirko (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 1648eda6500aSJiri Pirko opcode); 1649eda6500aSJiri Pirko 1650eda6500aSJiri Pirko if (!evreq) { 1651eda6500aSJiri Pirko unsigned long end; 1652eda6500aSJiri Pirko 1653eda6500aSJiri Pirko end = jiffies + timeout; 1654eda6500aSJiri Pirko do { 1655eda6500aSJiri Pirko u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 1656eda6500aSJiri Pirko 1657eda6500aSJiri Pirko if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 1658eda6500aSJiri Pirko *p_wait_done = true; 1659eda6500aSJiri Pirko *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 1660eda6500aSJiri Pirko break; 1661eda6500aSJiri Pirko } 1662eda6500aSJiri Pirko cond_resched(); 1663eda6500aSJiri Pirko } while (time_before(jiffies, end)); 1664eda6500aSJiri Pirko } else { 1665eda6500aSJiri Pirko wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout); 1666eda6500aSJiri Pirko *p_status = mlxsw_pci->cmd.comp.status; 1667eda6500aSJiri Pirko } 1668eda6500aSJiri Pirko 1669eda6500aSJiri Pirko err = 0; 1670eda6500aSJiri Pirko if (*p_wait_done) { 1671eda6500aSJiri Pirko if (*p_status) 1672eda6500aSJiri Pirko err = -EIO; 1673eda6500aSJiri Pirko } else { 1674eda6500aSJiri Pirko err = -ETIMEDOUT; 1675eda6500aSJiri Pirko } 1676eda6500aSJiri Pirko 1677eda6500aSJiri Pirko if (!err && out_mbox && out_mbox_direct) { 16781e81779aSIdo Schimmel /* Some commands don't use output param as address to mailbox 1679eda6500aSJiri Pirko * but they store output directly into registers. In that case, 1680eda6500aSJiri Pirko * copy registers into mbox buffer. 1681eda6500aSJiri Pirko */ 1682eda6500aSJiri Pirko __be32 tmp; 1683eda6500aSJiri Pirko 1684eda6500aSJiri Pirko if (!evreq) { 1685eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1686eda6500aSJiri Pirko CIR_OUT_PARAM_HI)); 1687eda6500aSJiri Pirko memcpy(out_mbox, &tmp, sizeof(tmp)); 1688eda6500aSJiri Pirko tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 1689eda6500aSJiri Pirko CIR_OUT_PARAM_LO)); 1690eda6500aSJiri Pirko memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 1691eda6500aSJiri Pirko } 1692d9324f68SOr Gerlitz } else if (!err && out_mbox) { 16931e81779aSIdo Schimmel memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 1694d9324f68SOr Gerlitz } 1695eda6500aSJiri Pirko 1696eda6500aSJiri Pirko mutex_unlock(&mlxsw_pci->cmd.lock); 1697eda6500aSJiri Pirko 1698eda6500aSJiri Pirko return err; 1699eda6500aSJiri Pirko } 1700eda6500aSJiri Pirko 17018289169dSShalom Toledo static u32 mlxsw_pci_read_frc_h(void *bus_priv) 17028289169dSShalom Toledo { 17038289169dSShalom Toledo struct mlxsw_pci *mlxsw_pci = bus_priv; 17048289169dSShalom Toledo u64 frc_offset; 17058289169dSShalom Toledo 17068289169dSShalom Toledo frc_offset = mlxsw_pci->free_running_clock_offset; 17078289169dSShalom Toledo return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset)); 17088289169dSShalom Toledo } 17098289169dSShalom Toledo 17108289169dSShalom Toledo static u32 mlxsw_pci_read_frc_l(void *bus_priv) 17118289169dSShalom Toledo { 17128289169dSShalom Toledo struct mlxsw_pci *mlxsw_pci = bus_priv; 17138289169dSShalom Toledo u64 frc_offset; 17148289169dSShalom Toledo 17158289169dSShalom Toledo frc_offset = mlxsw_pci->free_running_clock_offset; 17168289169dSShalom Toledo return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset)); 17178289169dSShalom Toledo } 17188289169dSShalom Toledo 171954a2e8d4SArkadi Sharshevsky static const struct mlxsw_bus mlxsw_pci_bus = { 172054a2e8d4SArkadi Sharshevsky .kind = "pci", 172154a2e8d4SArkadi Sharshevsky .init = mlxsw_pci_init, 172254a2e8d4SArkadi Sharshevsky .fini = mlxsw_pci_fini, 172354a2e8d4SArkadi Sharshevsky .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 172454a2e8d4SArkadi Sharshevsky .skb_transmit = mlxsw_pci_skb_transmit, 172554a2e8d4SArkadi Sharshevsky .cmd_exec = mlxsw_pci_cmd_exec, 17268289169dSShalom Toledo .read_frc_h = mlxsw_pci_read_frc_h, 17278289169dSShalom Toledo .read_frc_l = mlxsw_pci_read_frc_l, 1728f3a52c61SJiri Pirko .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, 172954a2e8d4SArkadi Sharshevsky }; 173054a2e8d4SArkadi Sharshevsky 1731eda6500aSJiri Pirko static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1732eda6500aSJiri Pirko { 17331d20d23cSJiri Pirko const char *driver_name = pdev->driver->name; 1734eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci; 1735eda6500aSJiri Pirko int err; 1736eda6500aSJiri Pirko 1737eda6500aSJiri Pirko mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 1738eda6500aSJiri Pirko if (!mlxsw_pci) 1739eda6500aSJiri Pirko return -ENOMEM; 1740eda6500aSJiri Pirko 1741eda6500aSJiri Pirko err = pci_enable_device(pdev); 1742eda6500aSJiri Pirko if (err) { 1743eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_enable_device failed\n"); 1744eda6500aSJiri Pirko goto err_pci_enable_device; 1745eda6500aSJiri Pirko } 1746eda6500aSJiri Pirko 17471d20d23cSJiri Pirko err = pci_request_regions(pdev, driver_name); 1748eda6500aSJiri Pirko if (err) { 1749eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_request_regions failed\n"); 1750eda6500aSJiri Pirko goto err_pci_request_regions; 1751eda6500aSJiri Pirko } 1752eda6500aSJiri Pirko 1753eda6500aSJiri Pirko err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1754eda6500aSJiri Pirko if (!err) { 1755eda6500aSJiri Pirko err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1756eda6500aSJiri Pirko if (err) { 1757eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n"); 1758eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1759eda6500aSJiri Pirko } 1760eda6500aSJiri Pirko } else { 1761eda6500aSJiri Pirko err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1762eda6500aSJiri Pirko if (err) { 1763eda6500aSJiri Pirko dev_err(&pdev->dev, "pci_set_dma_mask failed\n"); 1764eda6500aSJiri Pirko goto err_pci_set_dma_mask; 1765eda6500aSJiri Pirko } 1766eda6500aSJiri Pirko } 1767eda6500aSJiri Pirko 1768eda6500aSJiri Pirko if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 1769eda6500aSJiri Pirko dev_err(&pdev->dev, "invalid PCI region size\n"); 1770eda6500aSJiri Pirko err = -EINVAL; 1771eda6500aSJiri Pirko goto err_pci_resource_len_check; 1772eda6500aSJiri Pirko } 1773eda6500aSJiri Pirko 1774eda6500aSJiri Pirko mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 1775eda6500aSJiri Pirko pci_resource_len(pdev, 0)); 1776eda6500aSJiri Pirko if (!mlxsw_pci->hw_addr) { 1777eda6500aSJiri Pirko dev_err(&pdev->dev, "ioremap failed\n"); 1778eda6500aSJiri Pirko err = -EIO; 1779eda6500aSJiri Pirko goto err_ioremap; 1780eda6500aSJiri Pirko } 1781eda6500aSJiri Pirko pci_set_master(pdev); 1782eda6500aSJiri Pirko 1783eda6500aSJiri Pirko mlxsw_pci->pdev = pdev; 1784eda6500aSJiri Pirko pci_set_drvdata(pdev, mlxsw_pci); 1785eda6500aSJiri Pirko 17861d20d23cSJiri Pirko mlxsw_pci->bus_info.device_kind = driver_name; 1787eda6500aSJiri Pirko mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 1788eda6500aSJiri Pirko mlxsw_pci->bus_info.dev = &pdev->dev; 17898289169dSShalom Toledo mlxsw_pci->bus_info.read_frc_capable = true; 179054a2e8d4SArkadi Sharshevsky mlxsw_pci->id = id; 1791eda6500aSJiri Pirko 1792eda6500aSJiri Pirko err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 179324cc68adSArkadi Sharshevsky &mlxsw_pci_bus, mlxsw_pci, false, 179424cc68adSArkadi Sharshevsky NULL); 179503bffcadSShalom Toledo if (err) { 1796eda6500aSJiri Pirko dev_err(&pdev->dev, "cannot register bus device\n"); 1797eda6500aSJiri Pirko goto err_bus_device_register; 1798eda6500aSJiri Pirko } 1799eda6500aSJiri Pirko 1800eda6500aSJiri Pirko return 0; 1801eda6500aSJiri Pirko 1802eda6500aSJiri Pirko err_bus_device_register: 1803eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1804eda6500aSJiri Pirko err_ioremap: 1805eda6500aSJiri Pirko err_pci_resource_len_check: 1806eda6500aSJiri Pirko err_pci_set_dma_mask: 1807eda6500aSJiri Pirko pci_release_regions(pdev); 1808eda6500aSJiri Pirko err_pci_request_regions: 1809eda6500aSJiri Pirko pci_disable_device(pdev); 1810eda6500aSJiri Pirko err_pci_enable_device: 1811eda6500aSJiri Pirko kfree(mlxsw_pci); 1812eda6500aSJiri Pirko return err; 1813eda6500aSJiri Pirko } 1814eda6500aSJiri Pirko 1815eda6500aSJiri Pirko static void mlxsw_pci_remove(struct pci_dev *pdev) 1816eda6500aSJiri Pirko { 1817eda6500aSJiri Pirko struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 1818eda6500aSJiri Pirko 181924cc68adSArkadi Sharshevsky mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 1820eda6500aSJiri Pirko iounmap(mlxsw_pci->hw_addr); 1821eda6500aSJiri Pirko pci_release_regions(mlxsw_pci->pdev); 1822eda6500aSJiri Pirko pci_disable_device(mlxsw_pci->pdev); 1823eda6500aSJiri Pirko kfree(mlxsw_pci); 1824eda6500aSJiri Pirko } 1825eda6500aSJiri Pirko 18261d20d23cSJiri Pirko int mlxsw_pci_driver_register(struct pci_driver *pci_driver) 18271d20d23cSJiri Pirko { 18281d20d23cSJiri Pirko pci_driver->probe = mlxsw_pci_probe; 18291d20d23cSJiri Pirko pci_driver->remove = mlxsw_pci_remove; 18301d20d23cSJiri Pirko return pci_register_driver(pci_driver); 18311d20d23cSJiri Pirko } 18321d20d23cSJiri Pirko EXPORT_SYMBOL(mlxsw_pci_driver_register); 18331d20d23cSJiri Pirko 18341d20d23cSJiri Pirko void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver) 18351d20d23cSJiri Pirko { 18361d20d23cSJiri Pirko pci_unregister_driver(pci_driver); 18371d20d23cSJiri Pirko } 18381d20d23cSJiri Pirko EXPORT_SYMBOL(mlxsw_pci_driver_unregister); 1839eda6500aSJiri Pirko 1840eda6500aSJiri Pirko static int __init mlxsw_pci_module_init(void) 1841eda6500aSJiri Pirko { 1842eda6500aSJiri Pirko return 0; 1843eda6500aSJiri Pirko } 1844eda6500aSJiri Pirko 1845eda6500aSJiri Pirko static void __exit mlxsw_pci_module_exit(void) 1846eda6500aSJiri Pirko { 1847eda6500aSJiri Pirko } 1848eda6500aSJiri Pirko 1849eda6500aSJiri Pirko module_init(mlxsw_pci_module_init); 1850eda6500aSJiri Pirko module_exit(mlxsw_pci_module_exit); 1851eda6500aSJiri Pirko 1852eda6500aSJiri Pirko MODULE_LICENSE("Dual BSD/GPL"); 1853eda6500aSJiri Pirko MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 1854eda6500aSJiri Pirko MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 1855