1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/err.h>
5 #include <linux/i2c.h>
6 #include <linux/init.h>
7 #include <linux/jiffies.h>
8 #include <linux/kernel.h>
9 #include <linux/mutex.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_data/mlxreg.h>
13 #include <linux/slab.h>
14 
15 #include "cmd.h"
16 #include "core.h"
17 #include "i2c.h"
18 #include "resources.h"
19 
20 #define MLXSW_I2C_CIR2_BASE		0x72000
21 #define MLXSW_I2C_CIR_STATUS_OFF	0x18
22 #define MLXSW_I2C_CIR2_OFF_STATUS	(MLXSW_I2C_CIR2_BASE + \
23 					 MLXSW_I2C_CIR_STATUS_OFF)
24 #define MLXSW_I2C_OPMOD_SHIFT		12
25 #define MLXSW_I2C_EVENT_BIT_SHIFT	22
26 #define MLXSW_I2C_GO_BIT_SHIFT		23
27 #define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT	24
28 #define MLXSW_I2C_EVENT_BIT		BIT(MLXSW_I2C_EVENT_BIT_SHIFT)
29 #define MLXSW_I2C_GO_BIT		BIT(MLXSW_I2C_GO_BIT_SHIFT)
30 #define MLXSW_I2C_GO_OPMODE		BIT(MLXSW_I2C_OPMOD_SHIFT)
31 #define MLXSW_I2C_SET_IMM_CMD		(MLXSW_I2C_GO_OPMODE | \
32 					 MLXSW_CMD_OPCODE_QUERY_FW)
33 #define MLXSW_I2C_PUSH_IMM_CMD		(MLXSW_I2C_GO_BIT | \
34 					 MLXSW_I2C_SET_IMM_CMD)
35 #define MLXSW_I2C_SET_CMD		(MLXSW_CMD_OPCODE_ACCESS_REG)
36 #define MLXSW_I2C_PUSH_CMD		(MLXSW_I2C_GO_BIT | MLXSW_I2C_SET_CMD)
37 #define MLXSW_I2C_TLV_HDR_SIZE		0x10
38 #define MLXSW_I2C_ADDR_WIDTH		4
39 #define MLXSW_I2C_PUSH_CMD_SIZE		(MLXSW_I2C_ADDR_WIDTH + 4)
40 #define MLXSW_I2C_SET_EVENT_CMD		(MLXSW_I2C_EVENT_BIT)
41 #define MLXSW_I2C_PUSH_EVENT_CMD	(MLXSW_I2C_GO_BIT | \
42 					 MLXSW_I2C_SET_EVENT_CMD)
43 #define MLXSW_I2C_READ_SEMA_SIZE	4
44 #define MLXSW_I2C_PREP_SIZE		(MLXSW_I2C_ADDR_WIDTH + 28)
45 #define MLXSW_I2C_MBOX_SIZE		20
46 #define MLXSW_I2C_MBOX_OUT_PARAM_OFF	12
47 #define MLXSW_I2C_MBOX_OFFSET_BITS	20
48 #define MLXSW_I2C_MBOX_SIZE_BITS	12
49 #define MLXSW_I2C_ADDR_BUF_SIZE		4
50 #define MLXSW_I2C_BLK_DEF		32
51 #define MLXSW_I2C_BLK_MAX		100
52 #define MLXSW_I2C_RETRY			5
53 #define MLXSW_I2C_TIMEOUT_MSECS		5000
54 #define MLXSW_I2C_MAX_DATA_SIZE		256
55 
56 /* Driver can be initialized by kernel platform driver or from the user
57  * space. In the first case IRQ line number is passed through the platform
58  * data, otherwise default IRQ line is to be used. Default IRQ is relevant
59  * only for specific I2C slave address, allowing 3.4 MHz I2C path to the chip
60  * (special hardware feature for I2C acceleration).
61  */
62 #define MLXSW_I2C_DEFAULT_IRQ		17
63 #define MLXSW_FAST_I2C_SLAVE		0x37
64 
65 /**
66  * struct mlxsw_i2c - device private data:
67  * @cmd: command attributes;
68  * @cmd.mb_size_in: input mailbox size;
69  * @cmd.mb_off_in: input mailbox offset in register space;
70  * @cmd.mb_size_out: output mailbox size;
71  * @cmd.mb_off_out: output mailbox offset in register space;
72  * @cmd.lock: command execution lock;
73  * @dev: I2C device;
74  * @core: switch core pointer;
75  * @bus_info: bus info block;
76  * @block_size: maximum block size allowed to pass to under layer;
77  * @pdata: device platform data;
78  * @irq_work: interrupts work item;
79  * @irq: IRQ line number;
80  */
81 struct mlxsw_i2c {
82 	struct {
83 		u32 mb_size_in;
84 		u32 mb_off_in;
85 		u32 mb_size_out;
86 		u32 mb_off_out;
87 		struct mutex lock;
88 	} cmd;
89 	struct device *dev;
90 	struct mlxsw_core *core;
91 	struct mlxsw_bus_info bus_info;
92 	u16 block_size;
93 	struct mlxreg_core_hotplug_platform_data *pdata;
94 	struct work_struct irq_work;
95 	int irq;
96 };
97 
98 #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) {	\
99 	{ .addr = (_client)->addr,				\
100 	  .buf = (_addr_buf),					\
101 	  .len = MLXSW_I2C_ADDR_BUF_SIZE,			\
102 	  .flags = 0 },						\
103 	{ .addr = (_client)->addr,				\
104 	  .buf = (_buf),					\
105 	  .len = (_len),					\
106 	  .flags = I2C_M_RD } }
107 
108 #define MLXSW_I2C_WRITE_MSG(_client, _buf, _len)		\
109 	{ .addr = (_client)->addr,				\
110 	  .buf = (u8 *)(_buf),					\
111 	  .len = (_len),					\
112 	  .flags = 0 }
113 
114 /* Routine converts in and out mail boxes offset and size. */
115 static inline void
116 mlxsw_i2c_convert_mbox(struct mlxsw_i2c *mlxsw_i2c, u8 *buf)
117 {
118 	u32 tmp;
119 
120 	/* Local in/out mailboxes: 20 bits for offset, 12 for size */
121 	tmp = be32_to_cpup((__be32 *) buf);
122 	mlxsw_i2c->cmd.mb_off_in = tmp &
123 				   GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
124 	mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31,
125 					MLXSW_I2C_MBOX_OFFSET_BITS)) >>
126 					MLXSW_I2C_MBOX_OFFSET_BITS;
127 
128 	tmp = be32_to_cpup((__be32 *) (buf + MLXSW_I2C_ADDR_WIDTH));
129 	mlxsw_i2c->cmd.mb_off_out = tmp &
130 				    GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
131 	mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31,
132 					MLXSW_I2C_MBOX_OFFSET_BITS)) >>
133 					MLXSW_I2C_MBOX_OFFSET_BITS;
134 }
135 
136 /* Routine obtains register size from mail box buffer. */
137 static inline int mlxsw_i2c_get_reg_size(u8 *in_mbox)
138 {
139 	u16  tmp = be16_to_cpup((__be16 *) (in_mbox + MLXSW_I2C_TLV_HDR_SIZE));
140 
141 	return (tmp & 0x7ff) * 4 + MLXSW_I2C_TLV_HDR_SIZE;
142 }
143 
144 /* Routine sets I2C device internal offset in the transaction buffer. */
145 static inline void mlxsw_i2c_set_slave_addr(u8 *buf, u32 off)
146 {
147 	__be32 *val = (__be32 *) buf;
148 
149 	*val = htonl(off);
150 }
151 
152 /* Routine waits until go bit is cleared. */
153 static int mlxsw_i2c_wait_go_bit(struct i2c_client *client,
154 				 struct mlxsw_i2c *mlxsw_i2c, u8 *p_status)
155 {
156 	u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
157 	u8 buf[MLXSW_I2C_READ_SEMA_SIZE];
158 	int len = MLXSW_I2C_READ_SEMA_SIZE;
159 	struct i2c_msg read_sema[] =
160 		MLXSW_I2C_READ_MSG(client, addr_buf, buf, len);
161 	bool wait_done = false;
162 	unsigned long end;
163 	int i = 0, err;
164 
165 	mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_OFF_STATUS);
166 
167 	end = jiffies + msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
168 	do {
169 		u32 ctrl;
170 
171 		err = i2c_transfer(client->adapter, read_sema,
172 				   ARRAY_SIZE(read_sema));
173 
174 		ctrl = be32_to_cpu(*(__be32 *) buf);
175 		if (err == ARRAY_SIZE(read_sema)) {
176 			if (!(ctrl & MLXSW_I2C_GO_BIT)) {
177 				wait_done = true;
178 				*p_status = ctrl >>
179 					    MLXSW_I2C_CIR_CTRL_STATUS_SHIFT;
180 				break;
181 			}
182 		}
183 		cond_resched();
184 	} while ((time_before(jiffies, end)) || (i++ < MLXSW_I2C_RETRY));
185 
186 	if (wait_done) {
187 		if (*p_status)
188 			err = -EIO;
189 	} else {
190 		return -ETIMEDOUT;
191 	}
192 
193 	return err > 0 ? 0 : err;
194 }
195 
196 /* Routine posts a command to ASIC through mail box. */
197 static int mlxsw_i2c_write_cmd(struct i2c_client *client,
198 			       struct mlxsw_i2c *mlxsw_i2c,
199 			       int immediate)
200 {
201 	__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
202 		0, cpu_to_be32(MLXSW_I2C_PUSH_IMM_CMD)
203 	};
204 	__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
205 		0, 0, 0, 0, 0, 0,
206 		cpu_to_be32(client->adapter->nr & 0xffff),
207 		cpu_to_be32(MLXSW_I2C_SET_IMM_CMD)
208 	};
209 	struct i2c_msg push_cmd =
210 		MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
211 				    MLXSW_I2C_PUSH_CMD_SIZE);
212 	struct i2c_msg prep_cmd =
213 		MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
214 	int err;
215 
216 	if (!immediate) {
217 		push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_CMD);
218 		prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_SET_CMD);
219 	}
220 	mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
221 				 MLXSW_I2C_CIR2_BASE);
222 	mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
223 				 MLXSW_I2C_CIR2_OFF_STATUS);
224 
225 	/* Prepare Command Interface Register for transaction */
226 	err = i2c_transfer(client->adapter, &prep_cmd, 1);
227 	if (err < 0)
228 		return err;
229 	else if (err != 1)
230 		return -EIO;
231 
232 	/* Write out Command Interface Register GO bit to push transaction */
233 	err = i2c_transfer(client->adapter, &push_cmd, 1);
234 	if (err < 0)
235 		return err;
236 	else if (err != 1)
237 		return -EIO;
238 
239 	return 0;
240 }
241 
242 /* Routine posts initialization command to ASIC through mail box. */
243 static int
244 mlxsw_i2c_write_init_cmd(struct i2c_client *client,
245 			 struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod)
246 {
247 	__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
248 		0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD)
249 	};
250 	__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
251 		0, 0, 0, 0, 0, 0,
252 		cpu_to_be32(client->adapter->nr & 0xffff),
253 		cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD)
254 	};
255 	struct i2c_msg push_cmd =
256 		MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
257 				    MLXSW_I2C_PUSH_CMD_SIZE);
258 	struct i2c_msg prep_cmd =
259 		MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
260 	u8 status;
261 	int err;
262 
263 	push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD | opcode);
264 	prep_cmd_buf[3] = cpu_to_be32(in_mod);
265 	prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_GO_BIT | opcode);
266 	mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
267 				 MLXSW_I2C_CIR2_BASE);
268 	mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
269 				 MLXSW_I2C_CIR2_OFF_STATUS);
270 
271 	/* Prepare Command Interface Register for transaction */
272 	err = i2c_transfer(client->adapter, &prep_cmd, 1);
273 	if (err < 0)
274 		return err;
275 	else if (err != 1)
276 		return -EIO;
277 
278 	/* Write out Command Interface Register GO bit to push transaction */
279 	err = i2c_transfer(client->adapter, &push_cmd, 1);
280 	if (err < 0)
281 		return err;
282 	else if (err != 1)
283 		return -EIO;
284 
285 	/* Wait until go bit is cleared. */
286 	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
287 	if (err) {
288 		dev_err(&client->dev, "HW semaphore is not released");
289 		return err;
290 	}
291 
292 	/* Validate transaction completion status. */
293 	if (status) {
294 		dev_err(&client->dev, "Bad transaction completion status %x\n",
295 			status);
296 		return -EIO;
297 	}
298 
299 	return 0;
300 }
301 
302 /* Routine obtains mail box offsets from ASIC register space. */
303 static int mlxsw_i2c_get_mbox(struct i2c_client *client,
304 			      struct mlxsw_i2c *mlxsw_i2c)
305 {
306 	u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
307 	u8 buf[MLXSW_I2C_MBOX_SIZE];
308 	struct i2c_msg mbox_cmd[] =
309 		MLXSW_I2C_READ_MSG(client, addr_buf, buf, MLXSW_I2C_MBOX_SIZE);
310 	int err;
311 
312 	/* Read mail boxes offsets. */
313 	mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_BASE);
314 	err = i2c_transfer(client->adapter, mbox_cmd, 2);
315 	if (err != 2) {
316 		dev_err(&client->dev, "Could not obtain mail boxes\n");
317 		if (!err)
318 			return -EIO;
319 		else
320 			return err;
321 	}
322 
323 	/* Convert mail boxes. */
324 	mlxsw_i2c_convert_mbox(mlxsw_i2c, &buf[MLXSW_I2C_MBOX_OUT_PARAM_OFF]);
325 
326 	return err;
327 }
328 
329 /* Routine sends I2C write transaction to ASIC device. */
330 static int
331 mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num,
332 		u8 *p_status)
333 {
334 	struct i2c_client *client = to_i2c_client(dev);
335 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
336 	unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
337 	int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j;
338 	unsigned long end;
339 	u8 *tran_buf;
340 	struct i2c_msg write_tran =
341 		MLXSW_I2C_WRITE_MSG(client, NULL, MLXSW_I2C_PUSH_CMD_SIZE);
342 	int err;
343 
344 	tran_buf = kmalloc(mlxsw_i2c->block_size + MLXSW_I2C_ADDR_BUF_SIZE,
345 			   GFP_KERNEL);
346 	if (!tran_buf)
347 		return -ENOMEM;
348 
349 	write_tran.buf = tran_buf;
350 	for (i = 0; i < num; i++) {
351 		chunk_size = (in_mbox_size > mlxsw_i2c->block_size) ?
352 			     mlxsw_i2c->block_size : in_mbox_size;
353 		write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size;
354 		mlxsw_i2c_set_slave_addr(tran_buf, off);
355 		memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox +
356 		       mlxsw_i2c->block_size * i, chunk_size);
357 
358 		j = 0;
359 		end = jiffies + timeout;
360 		do {
361 			err = i2c_transfer(client->adapter, &write_tran, 1);
362 			if (err == 1)
363 				break;
364 
365 			cond_resched();
366 		} while ((time_before(jiffies, end)) ||
367 			 (j++ < MLXSW_I2C_RETRY));
368 
369 		if (err != 1) {
370 			if (!err) {
371 				err = -EIO;
372 				goto mlxsw_i2c_write_exit;
373 			}
374 		}
375 
376 		off += chunk_size;
377 		in_mbox_size -= chunk_size;
378 	}
379 
380 	/* Prepare and write out Command Interface Register for transaction. */
381 	err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0);
382 	if (err) {
383 		dev_err(&client->dev, "Could not start transaction");
384 		err = -EIO;
385 		goto mlxsw_i2c_write_exit;
386 	}
387 
388 	/* Wait until go bit is cleared. */
389 	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status);
390 	if (err) {
391 		dev_err(&client->dev, "HW semaphore is not released");
392 		goto mlxsw_i2c_write_exit;
393 	}
394 
395 	/* Validate transaction completion status. */
396 	if (*p_status) {
397 		dev_err(&client->dev, "Bad transaction completion status %x\n",
398 			*p_status);
399 		err = -EIO;
400 	}
401 
402 mlxsw_i2c_write_exit:
403 	kfree(tran_buf);
404 	return err;
405 }
406 
407 /* Routine executes I2C command. */
408 static int
409 mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size,
410 	      u8 *in_mbox, size_t out_mbox_size, u8 *out_mbox, u8 *status)
411 {
412 	struct i2c_client *client = to_i2c_client(dev);
413 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
414 	unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
415 	u8 tran_buf[MLXSW_I2C_ADDR_BUF_SIZE];
416 	int num, chunk_size, reg_size, i, j;
417 	int off = mlxsw_i2c->cmd.mb_off_out;
418 	unsigned long end;
419 	struct i2c_msg read_tran[] =
420 		MLXSW_I2C_READ_MSG(client, tran_buf, NULL, 0);
421 	int err;
422 
423 	WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
424 
425 	if (in_mbox) {
426 		reg_size = mlxsw_i2c_get_reg_size(in_mbox);
427 		num = reg_size / mlxsw_i2c->block_size;
428 		if (reg_size % mlxsw_i2c->block_size)
429 			num++;
430 
431 		if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
432 			dev_err(&client->dev, "Could not acquire lock");
433 			return -EINVAL;
434 		}
435 
436 		err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
437 		if (err)
438 			goto cmd_fail;
439 
440 		/* No out mailbox is case of write transaction. */
441 		if (!out_mbox) {
442 			mutex_unlock(&mlxsw_i2c->cmd.lock);
443 			return 0;
444 		}
445 	} else {
446 		/* No input mailbox is case of initialization query command. */
447 		reg_size = MLXSW_I2C_MAX_DATA_SIZE;
448 		num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size);
449 
450 		if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
451 			dev_err(&client->dev, "Could not acquire lock");
452 			return -EINVAL;
453 		}
454 
455 		err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode,
456 					       in_mod);
457 		if (err)
458 			goto cmd_fail;
459 	}
460 
461 	/* Send read transaction to get output mailbox content. */
462 	read_tran[1].buf = out_mbox;
463 	for (i = 0; i < num; i++) {
464 		chunk_size = (reg_size > mlxsw_i2c->block_size) ?
465 			     mlxsw_i2c->block_size : reg_size;
466 		read_tran[1].len = chunk_size;
467 		mlxsw_i2c_set_slave_addr(tran_buf, off);
468 
469 		j = 0;
470 		end = jiffies + timeout;
471 		do {
472 			err = i2c_transfer(client->adapter, read_tran,
473 					   ARRAY_SIZE(read_tran));
474 			if (err == ARRAY_SIZE(read_tran))
475 				break;
476 
477 			cond_resched();
478 		} while ((time_before(jiffies, end)) ||
479 			 (j++ < MLXSW_I2C_RETRY));
480 
481 		if (err != ARRAY_SIZE(read_tran)) {
482 			if (!err)
483 				err = -EIO;
484 
485 			goto cmd_fail;
486 		}
487 
488 		off += chunk_size;
489 		reg_size -= chunk_size;
490 		read_tran[1].buf += chunk_size;
491 	}
492 
493 	mutex_unlock(&mlxsw_i2c->cmd.lock);
494 
495 	return 0;
496 
497 cmd_fail:
498 	mutex_unlock(&mlxsw_i2c->cmd.lock);
499 	return err;
500 }
501 
502 static int mlxsw_i2c_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
503 			      u32 in_mod, bool out_mbox_direct,
504 			      char *in_mbox, size_t in_mbox_size,
505 			      char *out_mbox, size_t out_mbox_size,
506 			      u8 *status)
507 {
508 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
509 
510 	return mlxsw_i2c_cmd(mlxsw_i2c->dev, opcode, in_mod, in_mbox_size,
511 			     in_mbox, out_mbox_size, out_mbox, status);
512 }
513 
514 static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv,
515 					const struct mlxsw_tx_info *tx_info)
516 {
517 	return false;
518 }
519 
520 static int mlxsw_i2c_skb_transmit(void *bus_priv, struct sk_buff *skb,
521 				  const struct mlxsw_tx_info *tx_info)
522 {
523 	return 0;
524 }
525 
526 static int
527 mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
528 	       const struct mlxsw_config_profile *profile,
529 	       struct mlxsw_res *res)
530 {
531 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
532 	char *mbox;
533 	int err;
534 
535 	mlxsw_i2c->core = mlxsw_core;
536 
537 	mbox = mlxsw_cmd_mbox_alloc();
538 	if (!mbox)
539 		return -ENOMEM;
540 
541 	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
542 	if (err)
543 		goto mbox_put;
544 
545 	mlxsw_i2c->bus_info.fw_rev.major =
546 		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
547 	mlxsw_i2c->bus_info.fw_rev.minor =
548 		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
549 	mlxsw_i2c->bus_info.fw_rev.subminor =
550 		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
551 
552 	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
553 
554 mbox_put:
555 	mlxsw_cmd_mbox_free(mbox);
556 	return err;
557 }
558 
559 static void mlxsw_i2c_fini(void *bus_priv)
560 {
561 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
562 
563 	mlxsw_i2c->core = NULL;
564 }
565 
566 static void mlxsw_i2c_work_handler(struct work_struct *work)
567 {
568 	struct mlxsw_i2c *mlxsw_i2c;
569 
570 	mlxsw_i2c = container_of(work, struct mlxsw_i2c, irq_work);
571 	mlxsw_core_irq_event_handlers_call(mlxsw_i2c->core);
572 }
573 
574 static irqreturn_t mlxsw_i2c_irq_handler(int irq, void *dev)
575 {
576 	struct mlxsw_i2c *mlxsw_i2c = dev;
577 
578 	mlxsw_core_schedule_work(&mlxsw_i2c->irq_work);
579 
580 	/* Interrupt handler shares IRQ line with 'main' interrupt handler.
581 	 * Return here IRQ_NONE, while main handler will return IRQ_HANDLED.
582 	 */
583 	return IRQ_NONE;
584 }
585 
586 static int mlxsw_i2c_irq_init(struct mlxsw_i2c *mlxsw_i2c, u8 addr)
587 {
588 	int err;
589 
590 	/* Initialize interrupt handler if system hotplug driver is reachable,
591 	 * otherwise interrupt line is not enabled and interrupts will not be
592 	 * raised to CPU. Also request_irq() call will be not valid.
593 	 */
594 	if (!IS_REACHABLE(CONFIG_MLXREG_HOTPLUG))
595 		return 0;
596 
597 	/* Set default interrupt line. */
598 	if (mlxsw_i2c->pdata && mlxsw_i2c->pdata->irq)
599 		mlxsw_i2c->irq = mlxsw_i2c->pdata->irq;
600 	else if (addr == MLXSW_FAST_I2C_SLAVE)
601 		mlxsw_i2c->irq = MLXSW_I2C_DEFAULT_IRQ;
602 
603 	if (!mlxsw_i2c->irq)
604 		return 0;
605 
606 	INIT_WORK(&mlxsw_i2c->irq_work, mlxsw_i2c_work_handler);
607 	err = request_irq(mlxsw_i2c->irq, mlxsw_i2c_irq_handler,
608 			  IRQF_TRIGGER_FALLING | IRQF_SHARED, "mlxsw-i2c",
609 			  mlxsw_i2c);
610 	if (err) {
611 		dev_err(mlxsw_i2c->bus_info.dev, "Failed to request irq: %d\n",
612 			err);
613 		return err;
614 	}
615 
616 	return 0;
617 }
618 
619 static void mlxsw_i2c_irq_fini(struct mlxsw_i2c *mlxsw_i2c)
620 {
621 	if (!IS_REACHABLE(CONFIG_MLXREG_HOTPLUG) || !mlxsw_i2c->irq)
622 		return;
623 	cancel_work_sync(&mlxsw_i2c->irq_work);
624 	free_irq(mlxsw_i2c->irq, mlxsw_i2c);
625 }
626 
627 static const struct mlxsw_bus mlxsw_i2c_bus = {
628 	.kind			= "i2c",
629 	.init			= mlxsw_i2c_init,
630 	.fini			= mlxsw_i2c_fini,
631 	.skb_transmit_busy	= mlxsw_i2c_skb_transmit_busy,
632 	.skb_transmit		= mlxsw_i2c_skb_transmit,
633 	.cmd_exec		= mlxsw_i2c_cmd_exec,
634 };
635 
636 static int mlxsw_i2c_probe(struct i2c_client *client)
637 {
638 	const struct i2c_device_id *id = i2c_client_get_device_id(client);
639 	const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
640 	struct mlxsw_i2c *mlxsw_i2c;
641 	u8 status;
642 	int err;
643 
644 	mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL);
645 	if (!mlxsw_i2c)
646 		return -ENOMEM;
647 
648 	if (quirks) {
649 		if ((quirks->max_read_len &&
650 		     quirks->max_read_len < MLXSW_I2C_BLK_DEF) ||
651 		    (quirks->max_write_len &&
652 		     quirks->max_write_len < MLXSW_I2C_BLK_DEF)) {
653 			dev_err(&client->dev, "Insufficient transaction buffer length\n");
654 			return -EOPNOTSUPP;
655 		}
656 
657 		mlxsw_i2c->block_size = min_t(u16, MLXSW_I2C_BLK_MAX,
658 					      min_t(u16, quirks->max_read_len,
659 						    quirks->max_write_len));
660 	} else {
661 		mlxsw_i2c->block_size = MLXSW_I2C_BLK_DEF;
662 	}
663 
664 	i2c_set_clientdata(client, mlxsw_i2c);
665 	mutex_init(&mlxsw_i2c->cmd.lock);
666 
667 	/* In order to use mailboxes through the i2c, special area is reserved
668 	 * on the i2c address space that can be used for input and output
669 	 * mailboxes. Such mailboxes are called local mailboxes. When using a
670 	 * local mailbox, software should specify 0 as the Input/Output
671 	 * parameters. The location of the Local Mailbox addresses on the i2c
672 	 * space can be retrieved through the QUERY_FW command.
673 	 * For this purpose QUERY_FW is to be issued with opcode modifier equal
674 	 * 0x01. For such command the output parameter is an immediate value.
675 	 * Here QUERY_FW command is invoked for ASIC probing and for getting
676 	 * local mailboxes addresses from immedate output parameters.
677 	 */
678 
679 	/* Prepare and write out Command Interface Register for transaction */
680 	err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 1);
681 	if (err) {
682 		dev_err(&client->dev, "Could not start transaction");
683 		goto errout;
684 	}
685 
686 	/* Wait until go bit is cleared. */
687 	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
688 	if (err) {
689 		dev_err(&client->dev, "HW semaphore is not released");
690 		goto errout;
691 	}
692 
693 	/* Validate transaction completion status. */
694 	if (status) {
695 		dev_err(&client->dev, "Bad transaction completion status %x\n",
696 			status);
697 		err = -EIO;
698 		goto errout;
699 	}
700 
701 	/* Get mailbox offsets. */
702 	err = mlxsw_i2c_get_mbox(client, mlxsw_i2c);
703 	if (err < 0) {
704 		dev_err(&client->dev, "Fail to get mailboxes\n");
705 		goto errout;
706 	}
707 
708 	dev_info(&client->dev, "%s mb size=%x off=0x%08x out mb size=%x off=0x%08x\n",
709 		 id->name, mlxsw_i2c->cmd.mb_size_in,
710 		 mlxsw_i2c->cmd.mb_off_in, mlxsw_i2c->cmd.mb_size_out,
711 		 mlxsw_i2c->cmd.mb_off_out);
712 
713 	/* Register device bus. */
714 	mlxsw_i2c->bus_info.device_kind = id->name;
715 	mlxsw_i2c->bus_info.device_name = client->name;
716 	mlxsw_i2c->bus_info.dev = &client->dev;
717 	mlxsw_i2c->bus_info.low_frequency = true;
718 	mlxsw_i2c->dev = &client->dev;
719 	mlxsw_i2c->pdata = client->dev.platform_data;
720 
721 	err = mlxsw_i2c_irq_init(mlxsw_i2c, client->addr);
722 	if (err)
723 		goto errout;
724 
725 	err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info,
726 					     &mlxsw_i2c_bus, mlxsw_i2c, false,
727 					     NULL, NULL);
728 	if (err) {
729 		dev_err(&client->dev, "Fail to register core bus\n");
730 		goto err_bus_device_register;
731 	}
732 
733 	return 0;
734 
735 err_bus_device_register:
736 	mlxsw_i2c_irq_fini(mlxsw_i2c);
737 errout:
738 	mutex_destroy(&mlxsw_i2c->cmd.lock);
739 	i2c_set_clientdata(client, NULL);
740 
741 	return err;
742 }
743 
744 static void mlxsw_i2c_remove(struct i2c_client *client)
745 {
746 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
747 
748 	mlxsw_core_bus_device_unregister(mlxsw_i2c->core, false);
749 	mlxsw_i2c_irq_fini(mlxsw_i2c);
750 	mutex_destroy(&mlxsw_i2c->cmd.lock);
751 }
752 
753 int mlxsw_i2c_driver_register(struct i2c_driver *i2c_driver)
754 {
755 	i2c_driver->probe = mlxsw_i2c_probe;
756 	i2c_driver->remove = mlxsw_i2c_remove;
757 	return i2c_add_driver(i2c_driver);
758 }
759 EXPORT_SYMBOL(mlxsw_i2c_driver_register);
760 
761 void mlxsw_i2c_driver_unregister(struct i2c_driver *i2c_driver)
762 {
763 	i2c_del_driver(i2c_driver);
764 }
765 EXPORT_SYMBOL(mlxsw_i2c_driver_unregister);
766 
767 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
768 MODULE_DESCRIPTION("Mellanox switch I2C interface driver");
769 MODULE_LICENSE("Dual BSD/GPL");
770