1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/err.h> 5 #include <linux/i2c.h> 6 #include <linux/init.h> 7 #include <linux/jiffies.h> 8 #include <linux/kernel.h> 9 #include <linux/mutex.h> 10 #include <linux/module.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/platform_data/mlxreg.h> 13 #include <linux/slab.h> 14 15 #include "cmd.h" 16 #include "core.h" 17 #include "i2c.h" 18 #include "resources.h" 19 20 #define MLXSW_I2C_CIR2_BASE 0x72000 21 #define MLXSW_I2C_CIR_STATUS_OFF 0x18 22 #define MLXSW_I2C_CIR2_OFF_STATUS (MLXSW_I2C_CIR2_BASE + \ 23 MLXSW_I2C_CIR_STATUS_OFF) 24 #define MLXSW_I2C_OPMOD_SHIFT 12 25 #define MLXSW_I2C_EVENT_BIT_SHIFT 22 26 #define MLXSW_I2C_GO_BIT_SHIFT 23 27 #define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT 24 28 #define MLXSW_I2C_EVENT_BIT BIT(MLXSW_I2C_EVENT_BIT_SHIFT) 29 #define MLXSW_I2C_GO_BIT BIT(MLXSW_I2C_GO_BIT_SHIFT) 30 #define MLXSW_I2C_GO_OPMODE BIT(MLXSW_I2C_OPMOD_SHIFT) 31 #define MLXSW_I2C_SET_IMM_CMD (MLXSW_I2C_GO_OPMODE | \ 32 MLXSW_CMD_OPCODE_QUERY_FW) 33 #define MLXSW_I2C_PUSH_IMM_CMD (MLXSW_I2C_GO_BIT | \ 34 MLXSW_I2C_SET_IMM_CMD) 35 #define MLXSW_I2C_SET_CMD (MLXSW_CMD_OPCODE_ACCESS_REG) 36 #define MLXSW_I2C_PUSH_CMD (MLXSW_I2C_GO_BIT | MLXSW_I2C_SET_CMD) 37 #define MLXSW_I2C_TLV_HDR_SIZE 0x10 38 #define MLXSW_I2C_ADDR_WIDTH 4 39 #define MLXSW_I2C_PUSH_CMD_SIZE (MLXSW_I2C_ADDR_WIDTH + 4) 40 #define MLXSW_I2C_SET_EVENT_CMD (MLXSW_I2C_EVENT_BIT) 41 #define MLXSW_I2C_PUSH_EVENT_CMD (MLXSW_I2C_GO_BIT | \ 42 MLXSW_I2C_SET_EVENT_CMD) 43 #define MLXSW_I2C_READ_SEMA_SIZE 4 44 #define MLXSW_I2C_PREP_SIZE (MLXSW_I2C_ADDR_WIDTH + 28) 45 #define MLXSW_I2C_MBOX_SIZE 20 46 #define MLXSW_I2C_MBOX_OUT_PARAM_OFF 12 47 #define MLXSW_I2C_MBOX_OFFSET_BITS 20 48 #define MLXSW_I2C_MBOX_SIZE_BITS 12 49 #define MLXSW_I2C_ADDR_BUF_SIZE 4 50 #define MLXSW_I2C_BLK_DEF 32 51 #define MLXSW_I2C_RETRY 5 52 #define MLXSW_I2C_TIMEOUT_MSECS 5000 53 #define MLXSW_I2C_MAX_DATA_SIZE 256 54 55 /* Driver can be initialized by kernel platform driver or from the user 56 * space. In the first case IRQ line number is passed through the platform 57 * data, otherwise default IRQ line is to be used. Default IRQ is relevant 58 * only for specific I2C slave address, allowing 3.4 MHz I2C path to the chip 59 * (special hardware feature for I2C acceleration). 60 */ 61 #define MLXSW_I2C_DEFAULT_IRQ 17 62 #define MLXSW_FAST_I2C_SLAVE 0x37 63 64 /** 65 * struct mlxsw_i2c - device private data: 66 * @cmd: command attributes; 67 * @cmd.mb_size_in: input mailbox size; 68 * @cmd.mb_off_in: input mailbox offset in register space; 69 * @cmd.mb_size_out: output mailbox size; 70 * @cmd.mb_off_out: output mailbox offset in register space; 71 * @cmd.lock: command execution lock; 72 * @dev: I2C device; 73 * @core: switch core pointer; 74 * @bus_info: bus info block; 75 * @block_size: maximum block size allowed to pass to under layer; 76 * @pdata: device platform data; 77 * @irq_work: interrupts work item; 78 * @irq: IRQ line number; 79 */ 80 struct mlxsw_i2c { 81 struct { 82 u32 mb_size_in; 83 u32 mb_off_in; 84 u32 mb_size_out; 85 u32 mb_off_out; 86 struct mutex lock; 87 } cmd; 88 struct device *dev; 89 struct mlxsw_core *core; 90 struct mlxsw_bus_info bus_info; 91 u16 block_size; 92 struct mlxreg_core_hotplug_platform_data *pdata; 93 struct work_struct irq_work; 94 int irq; 95 }; 96 97 #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) { \ 98 { .addr = (_client)->addr, \ 99 .buf = (_addr_buf), \ 100 .len = MLXSW_I2C_ADDR_BUF_SIZE, \ 101 .flags = 0 }, \ 102 { .addr = (_client)->addr, \ 103 .buf = (_buf), \ 104 .len = (_len), \ 105 .flags = I2C_M_RD } } 106 107 #define MLXSW_I2C_WRITE_MSG(_client, _buf, _len) \ 108 { .addr = (_client)->addr, \ 109 .buf = (u8 *)(_buf), \ 110 .len = (_len), \ 111 .flags = 0 } 112 113 /* Routine converts in and out mail boxes offset and size. */ 114 static inline void 115 mlxsw_i2c_convert_mbox(struct mlxsw_i2c *mlxsw_i2c, u8 *buf) 116 { 117 u32 tmp; 118 119 /* Local in/out mailboxes: 20 bits for offset, 12 for size */ 120 tmp = be32_to_cpup((__be32 *) buf); 121 mlxsw_i2c->cmd.mb_off_in = tmp & 122 GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0); 123 mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31, 124 MLXSW_I2C_MBOX_OFFSET_BITS)) >> 125 MLXSW_I2C_MBOX_OFFSET_BITS; 126 127 tmp = be32_to_cpup((__be32 *) (buf + MLXSW_I2C_ADDR_WIDTH)); 128 mlxsw_i2c->cmd.mb_off_out = tmp & 129 GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0); 130 mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31, 131 MLXSW_I2C_MBOX_OFFSET_BITS)) >> 132 MLXSW_I2C_MBOX_OFFSET_BITS; 133 } 134 135 /* Routine obtains register size from mail box buffer. */ 136 static inline int mlxsw_i2c_get_reg_size(u8 *in_mbox) 137 { 138 u16 tmp = be16_to_cpup((__be16 *) (in_mbox + MLXSW_I2C_TLV_HDR_SIZE)); 139 140 return (tmp & 0x7ff) * 4 + MLXSW_I2C_TLV_HDR_SIZE; 141 } 142 143 /* Routine sets I2C device internal offset in the transaction buffer. */ 144 static inline void mlxsw_i2c_set_slave_addr(u8 *buf, u32 off) 145 { 146 __be32 *val = (__be32 *) buf; 147 148 *val = htonl(off); 149 } 150 151 /* Routine waits until go bit is cleared. */ 152 static int mlxsw_i2c_wait_go_bit(struct i2c_client *client, 153 struct mlxsw_i2c *mlxsw_i2c, u8 *p_status) 154 { 155 u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE]; 156 u8 buf[MLXSW_I2C_READ_SEMA_SIZE]; 157 int len = MLXSW_I2C_READ_SEMA_SIZE; 158 struct i2c_msg read_sema[] = 159 MLXSW_I2C_READ_MSG(client, addr_buf, buf, len); 160 bool wait_done = false; 161 unsigned long end; 162 int i = 0, err; 163 164 mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_OFF_STATUS); 165 166 end = jiffies + msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS); 167 do { 168 u32 ctrl; 169 170 err = i2c_transfer(client->adapter, read_sema, 171 ARRAY_SIZE(read_sema)); 172 173 ctrl = be32_to_cpu(*(__be32 *) buf); 174 if (err == ARRAY_SIZE(read_sema)) { 175 if (!(ctrl & MLXSW_I2C_GO_BIT)) { 176 wait_done = true; 177 *p_status = ctrl >> 178 MLXSW_I2C_CIR_CTRL_STATUS_SHIFT; 179 break; 180 } 181 } 182 cond_resched(); 183 } while ((time_before(jiffies, end)) || (i++ < MLXSW_I2C_RETRY)); 184 185 if (wait_done) { 186 if (*p_status) 187 err = -EIO; 188 } else { 189 return -ETIMEDOUT; 190 } 191 192 return err > 0 ? 0 : err; 193 } 194 195 /* Routine posts a command to ASIC through mail box. */ 196 static int mlxsw_i2c_write_cmd(struct i2c_client *client, 197 struct mlxsw_i2c *mlxsw_i2c, 198 int immediate) 199 { 200 __be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = { 201 0, cpu_to_be32(MLXSW_I2C_PUSH_IMM_CMD) 202 }; 203 __be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = { 204 0, 0, 0, 0, 0, 0, 205 cpu_to_be32(client->adapter->nr & 0xffff), 206 cpu_to_be32(MLXSW_I2C_SET_IMM_CMD) 207 }; 208 struct i2c_msg push_cmd = 209 MLXSW_I2C_WRITE_MSG(client, push_cmd_buf, 210 MLXSW_I2C_PUSH_CMD_SIZE); 211 struct i2c_msg prep_cmd = 212 MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE); 213 int err; 214 215 if (!immediate) { 216 push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_CMD); 217 prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_SET_CMD); 218 } 219 mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf, 220 MLXSW_I2C_CIR2_BASE); 221 mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf, 222 MLXSW_I2C_CIR2_OFF_STATUS); 223 224 /* Prepare Command Interface Register for transaction */ 225 err = i2c_transfer(client->adapter, &prep_cmd, 1); 226 if (err < 0) 227 return err; 228 else if (err != 1) 229 return -EIO; 230 231 /* Write out Command Interface Register GO bit to push transaction */ 232 err = i2c_transfer(client->adapter, &push_cmd, 1); 233 if (err < 0) 234 return err; 235 else if (err != 1) 236 return -EIO; 237 238 return 0; 239 } 240 241 /* Routine posts initialization command to ASIC through mail box. */ 242 static int 243 mlxsw_i2c_write_init_cmd(struct i2c_client *client, 244 struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod) 245 { 246 __be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = { 247 0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD) 248 }; 249 __be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = { 250 0, 0, 0, 0, 0, 0, 251 cpu_to_be32(client->adapter->nr & 0xffff), 252 cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD) 253 }; 254 struct i2c_msg push_cmd = 255 MLXSW_I2C_WRITE_MSG(client, push_cmd_buf, 256 MLXSW_I2C_PUSH_CMD_SIZE); 257 struct i2c_msg prep_cmd = 258 MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE); 259 u8 status; 260 int err; 261 262 push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD | opcode); 263 prep_cmd_buf[3] = cpu_to_be32(in_mod); 264 prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_GO_BIT | opcode); 265 mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf, 266 MLXSW_I2C_CIR2_BASE); 267 mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf, 268 MLXSW_I2C_CIR2_OFF_STATUS); 269 270 /* Prepare Command Interface Register for transaction */ 271 err = i2c_transfer(client->adapter, &prep_cmd, 1); 272 if (err < 0) 273 return err; 274 else if (err != 1) 275 return -EIO; 276 277 /* Write out Command Interface Register GO bit to push transaction */ 278 err = i2c_transfer(client->adapter, &push_cmd, 1); 279 if (err < 0) 280 return err; 281 else if (err != 1) 282 return -EIO; 283 284 /* Wait until go bit is cleared. */ 285 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status); 286 if (err) { 287 dev_err(&client->dev, "HW semaphore is not released"); 288 return err; 289 } 290 291 /* Validate transaction completion status. */ 292 if (status) { 293 dev_err(&client->dev, "Bad transaction completion status %x\n", 294 status); 295 return -EIO; 296 } 297 298 return 0; 299 } 300 301 /* Routine obtains mail box offsets from ASIC register space. */ 302 static int mlxsw_i2c_get_mbox(struct i2c_client *client, 303 struct mlxsw_i2c *mlxsw_i2c) 304 { 305 u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE]; 306 u8 buf[MLXSW_I2C_MBOX_SIZE]; 307 struct i2c_msg mbox_cmd[] = 308 MLXSW_I2C_READ_MSG(client, addr_buf, buf, MLXSW_I2C_MBOX_SIZE); 309 int err; 310 311 /* Read mail boxes offsets. */ 312 mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_BASE); 313 err = i2c_transfer(client->adapter, mbox_cmd, 2); 314 if (err != 2) { 315 dev_err(&client->dev, "Could not obtain mail boxes\n"); 316 if (!err) 317 return -EIO; 318 else 319 return err; 320 } 321 322 /* Convert mail boxes. */ 323 mlxsw_i2c_convert_mbox(mlxsw_i2c, &buf[MLXSW_I2C_MBOX_OUT_PARAM_OFF]); 324 325 return err; 326 } 327 328 /* Routine sends I2C write transaction to ASIC device. */ 329 static int 330 mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num, 331 u8 *p_status) 332 { 333 struct i2c_client *client = to_i2c_client(dev); 334 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client); 335 unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS); 336 int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j; 337 unsigned long end; 338 u8 *tran_buf; 339 struct i2c_msg write_tran = 340 MLXSW_I2C_WRITE_MSG(client, NULL, MLXSW_I2C_PUSH_CMD_SIZE); 341 int err; 342 343 tran_buf = kmalloc(mlxsw_i2c->block_size + MLXSW_I2C_ADDR_BUF_SIZE, 344 GFP_KERNEL); 345 if (!tran_buf) 346 return -ENOMEM; 347 348 write_tran.buf = tran_buf; 349 for (i = 0; i < num; i++) { 350 chunk_size = (in_mbox_size > mlxsw_i2c->block_size) ? 351 mlxsw_i2c->block_size : in_mbox_size; 352 write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size; 353 mlxsw_i2c_set_slave_addr(tran_buf, off); 354 memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox + 355 mlxsw_i2c->block_size * i, chunk_size); 356 357 j = 0; 358 end = jiffies + timeout; 359 do { 360 err = i2c_transfer(client->adapter, &write_tran, 1); 361 if (err == 1) 362 break; 363 364 cond_resched(); 365 } while ((time_before(jiffies, end)) || 366 (j++ < MLXSW_I2C_RETRY)); 367 368 if (err != 1) { 369 if (!err) { 370 err = -EIO; 371 goto mlxsw_i2c_write_exit; 372 } 373 } 374 375 off += chunk_size; 376 in_mbox_size -= chunk_size; 377 } 378 379 /* Prepare and write out Command Interface Register for transaction. */ 380 err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0); 381 if (err) { 382 dev_err(&client->dev, "Could not start transaction"); 383 err = -EIO; 384 goto mlxsw_i2c_write_exit; 385 } 386 387 /* Wait until go bit is cleared. */ 388 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status); 389 if (err) { 390 dev_err(&client->dev, "HW semaphore is not released"); 391 goto mlxsw_i2c_write_exit; 392 } 393 394 /* Validate transaction completion status. */ 395 if (*p_status) { 396 dev_err(&client->dev, "Bad transaction completion status %x\n", 397 *p_status); 398 err = -EIO; 399 } 400 401 mlxsw_i2c_write_exit: 402 kfree(tran_buf); 403 return err; 404 } 405 406 /* Routine executes I2C command. */ 407 static int 408 mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size, 409 u8 *in_mbox, size_t out_mbox_size, u8 *out_mbox, u8 *status) 410 { 411 struct i2c_client *client = to_i2c_client(dev); 412 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client); 413 unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS); 414 u8 tran_buf[MLXSW_I2C_ADDR_BUF_SIZE]; 415 int num, chunk_size, reg_size, i, j; 416 int off = mlxsw_i2c->cmd.mb_off_out; 417 unsigned long end; 418 struct i2c_msg read_tran[] = 419 MLXSW_I2C_READ_MSG(client, tran_buf, NULL, 0); 420 int err; 421 422 WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 423 424 if (in_mbox) { 425 reg_size = mlxsw_i2c_get_reg_size(in_mbox); 426 num = reg_size / mlxsw_i2c->block_size; 427 if (reg_size % mlxsw_i2c->block_size) 428 num++; 429 430 if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { 431 dev_err(&client->dev, "Could not acquire lock"); 432 return -EINVAL; 433 } 434 435 err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status); 436 if (err) 437 goto cmd_fail; 438 439 /* No out mailbox is case of write transaction. */ 440 if (!out_mbox) { 441 mutex_unlock(&mlxsw_i2c->cmd.lock); 442 return 0; 443 } 444 } else { 445 /* No input mailbox is case of initialization query command. */ 446 reg_size = MLXSW_I2C_MAX_DATA_SIZE; 447 num = reg_size / mlxsw_i2c->block_size; 448 449 if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { 450 dev_err(&client->dev, "Could not acquire lock"); 451 return -EINVAL; 452 } 453 454 err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode, 455 in_mod); 456 if (err) 457 goto cmd_fail; 458 } 459 460 /* Send read transaction to get output mailbox content. */ 461 read_tran[1].buf = out_mbox; 462 for (i = 0; i < num; i++) { 463 chunk_size = (reg_size > mlxsw_i2c->block_size) ? 464 mlxsw_i2c->block_size : reg_size; 465 read_tran[1].len = chunk_size; 466 mlxsw_i2c_set_slave_addr(tran_buf, off); 467 468 j = 0; 469 end = jiffies + timeout; 470 do { 471 err = i2c_transfer(client->adapter, read_tran, 472 ARRAY_SIZE(read_tran)); 473 if (err == ARRAY_SIZE(read_tran)) 474 break; 475 476 cond_resched(); 477 } while ((time_before(jiffies, end)) || 478 (j++ < MLXSW_I2C_RETRY)); 479 480 if (err != ARRAY_SIZE(read_tran)) { 481 if (!err) 482 err = -EIO; 483 484 goto cmd_fail; 485 } 486 487 off += chunk_size; 488 reg_size -= chunk_size; 489 read_tran[1].buf += chunk_size; 490 } 491 492 mutex_unlock(&mlxsw_i2c->cmd.lock); 493 494 return 0; 495 496 cmd_fail: 497 mutex_unlock(&mlxsw_i2c->cmd.lock); 498 return err; 499 } 500 501 static int mlxsw_i2c_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 502 u32 in_mod, bool out_mbox_direct, 503 char *in_mbox, size_t in_mbox_size, 504 char *out_mbox, size_t out_mbox_size, 505 u8 *status) 506 { 507 struct mlxsw_i2c *mlxsw_i2c = bus_priv; 508 509 return mlxsw_i2c_cmd(mlxsw_i2c->dev, opcode, in_mod, in_mbox_size, 510 in_mbox, out_mbox_size, out_mbox, status); 511 } 512 513 static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv, 514 const struct mlxsw_tx_info *tx_info) 515 { 516 return false; 517 } 518 519 static int mlxsw_i2c_skb_transmit(void *bus_priv, struct sk_buff *skb, 520 const struct mlxsw_tx_info *tx_info) 521 { 522 return 0; 523 } 524 525 static int 526 mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 527 const struct mlxsw_config_profile *profile, 528 struct mlxsw_res *res) 529 { 530 struct mlxsw_i2c *mlxsw_i2c = bus_priv; 531 char *mbox; 532 int err; 533 534 mlxsw_i2c->core = mlxsw_core; 535 536 mbox = mlxsw_cmd_mbox_alloc(); 537 if (!mbox) 538 return -ENOMEM; 539 540 err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 541 if (err) 542 goto mbox_put; 543 544 mlxsw_i2c->bus_info.fw_rev.major = 545 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 546 mlxsw_i2c->bus_info.fw_rev.minor = 547 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 548 mlxsw_i2c->bus_info.fw_rev.subminor = 549 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 550 551 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 552 553 mbox_put: 554 mlxsw_cmd_mbox_free(mbox); 555 return err; 556 } 557 558 static void mlxsw_i2c_fini(void *bus_priv) 559 { 560 struct mlxsw_i2c *mlxsw_i2c = bus_priv; 561 562 mlxsw_i2c->core = NULL; 563 } 564 565 static void mlxsw_i2c_work_handler(struct work_struct *work) 566 { 567 struct mlxsw_i2c *mlxsw_i2c; 568 569 mlxsw_i2c = container_of(work, struct mlxsw_i2c, irq_work); 570 mlxsw_core_irq_event_handlers_call(mlxsw_i2c->core); 571 } 572 573 static irqreturn_t mlxsw_i2c_irq_handler(int irq, void *dev) 574 { 575 struct mlxsw_i2c *mlxsw_i2c = dev; 576 577 mlxsw_core_schedule_work(&mlxsw_i2c->irq_work); 578 579 /* Interrupt handler shares IRQ line with 'main' interrupt handler. 580 * Return here IRQ_NONE, while main handler will return IRQ_HANDLED. 581 */ 582 return IRQ_NONE; 583 } 584 585 static int mlxsw_i2c_irq_init(struct mlxsw_i2c *mlxsw_i2c, u8 addr) 586 { 587 int err; 588 589 /* Initialize interrupt handler if system hotplug driver is reachable, 590 * otherwise interrupt line is not enabled and interrupts will not be 591 * raised to CPU. Also request_irq() call will be not valid. 592 */ 593 if (!IS_REACHABLE(CONFIG_MLXREG_HOTPLUG)) 594 return 0; 595 596 /* Set default interrupt line. */ 597 if (mlxsw_i2c->pdata && mlxsw_i2c->pdata->irq) 598 mlxsw_i2c->irq = mlxsw_i2c->pdata->irq; 599 else if (addr == MLXSW_FAST_I2C_SLAVE) 600 mlxsw_i2c->irq = MLXSW_I2C_DEFAULT_IRQ; 601 602 if (!mlxsw_i2c->irq) 603 return 0; 604 605 INIT_WORK(&mlxsw_i2c->irq_work, mlxsw_i2c_work_handler); 606 err = request_irq(mlxsw_i2c->irq, mlxsw_i2c_irq_handler, 607 IRQF_TRIGGER_FALLING | IRQF_SHARED, "mlxsw-i2c", 608 mlxsw_i2c); 609 if (err) { 610 dev_err(mlxsw_i2c->bus_info.dev, "Failed to request irq: %d\n", 611 err); 612 return err; 613 } 614 615 return 0; 616 } 617 618 static void mlxsw_i2c_irq_fini(struct mlxsw_i2c *mlxsw_i2c) 619 { 620 if (!IS_REACHABLE(CONFIG_MLXREG_HOTPLUG) || !mlxsw_i2c->irq) 621 return; 622 cancel_work_sync(&mlxsw_i2c->irq_work); 623 free_irq(mlxsw_i2c->irq, mlxsw_i2c); 624 } 625 626 static const struct mlxsw_bus mlxsw_i2c_bus = { 627 .kind = "i2c", 628 .init = mlxsw_i2c_init, 629 .fini = mlxsw_i2c_fini, 630 .skb_transmit_busy = mlxsw_i2c_skb_transmit_busy, 631 .skb_transmit = mlxsw_i2c_skb_transmit, 632 .cmd_exec = mlxsw_i2c_cmd_exec, 633 }; 634 635 static int mlxsw_i2c_probe(struct i2c_client *client) 636 { 637 const struct i2c_device_id *id = i2c_client_get_device_id(client); 638 const struct i2c_adapter_quirks *quirks = client->adapter->quirks; 639 struct mlxsw_i2c *mlxsw_i2c; 640 u8 status; 641 int err; 642 643 mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL); 644 if (!mlxsw_i2c) 645 return -ENOMEM; 646 647 if (quirks) { 648 if ((quirks->max_read_len && 649 quirks->max_read_len < MLXSW_I2C_BLK_DEF) || 650 (quirks->max_write_len && 651 quirks->max_write_len < MLXSW_I2C_BLK_DEF)) { 652 dev_err(&client->dev, "Insufficient transaction buffer length\n"); 653 return -EOPNOTSUPP; 654 } 655 656 mlxsw_i2c->block_size = max_t(u16, MLXSW_I2C_BLK_DEF, 657 min_t(u16, quirks->max_read_len, 658 quirks->max_write_len)); 659 } else { 660 mlxsw_i2c->block_size = MLXSW_I2C_BLK_DEF; 661 } 662 663 i2c_set_clientdata(client, mlxsw_i2c); 664 mutex_init(&mlxsw_i2c->cmd.lock); 665 666 /* In order to use mailboxes through the i2c, special area is reserved 667 * on the i2c address space that can be used for input and output 668 * mailboxes. Such mailboxes are called local mailboxes. When using a 669 * local mailbox, software should specify 0 as the Input/Output 670 * parameters. The location of the Local Mailbox addresses on the i2c 671 * space can be retrieved through the QUERY_FW command. 672 * For this purpose QUERY_FW is to be issued with opcode modifier equal 673 * 0x01. For such command the output parameter is an immediate value. 674 * Here QUERY_FW command is invoked for ASIC probing and for getting 675 * local mailboxes addresses from immedate output parameters. 676 */ 677 678 /* Prepare and write out Command Interface Register for transaction */ 679 err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 1); 680 if (err) { 681 dev_err(&client->dev, "Could not start transaction"); 682 goto errout; 683 } 684 685 /* Wait until go bit is cleared. */ 686 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status); 687 if (err) { 688 dev_err(&client->dev, "HW semaphore is not released"); 689 goto errout; 690 } 691 692 /* Validate transaction completion status. */ 693 if (status) { 694 dev_err(&client->dev, "Bad transaction completion status %x\n", 695 status); 696 err = -EIO; 697 goto errout; 698 } 699 700 /* Get mailbox offsets. */ 701 err = mlxsw_i2c_get_mbox(client, mlxsw_i2c); 702 if (err < 0) { 703 dev_err(&client->dev, "Fail to get mailboxes\n"); 704 goto errout; 705 } 706 707 dev_info(&client->dev, "%s mb size=%x off=0x%08x out mb size=%x off=0x%08x\n", 708 id->name, mlxsw_i2c->cmd.mb_size_in, 709 mlxsw_i2c->cmd.mb_off_in, mlxsw_i2c->cmd.mb_size_out, 710 mlxsw_i2c->cmd.mb_off_out); 711 712 /* Register device bus. */ 713 mlxsw_i2c->bus_info.device_kind = id->name; 714 mlxsw_i2c->bus_info.device_name = client->name; 715 mlxsw_i2c->bus_info.dev = &client->dev; 716 mlxsw_i2c->bus_info.low_frequency = true; 717 mlxsw_i2c->dev = &client->dev; 718 mlxsw_i2c->pdata = client->dev.platform_data; 719 720 err = mlxsw_i2c_irq_init(mlxsw_i2c, client->addr); 721 if (err) 722 goto errout; 723 724 err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info, 725 &mlxsw_i2c_bus, mlxsw_i2c, false, 726 NULL, NULL); 727 if (err) { 728 dev_err(&client->dev, "Fail to register core bus\n"); 729 goto err_bus_device_register; 730 } 731 732 return 0; 733 734 err_bus_device_register: 735 mlxsw_i2c_irq_fini(mlxsw_i2c); 736 errout: 737 mutex_destroy(&mlxsw_i2c->cmd.lock); 738 i2c_set_clientdata(client, NULL); 739 740 return err; 741 } 742 743 static void mlxsw_i2c_remove(struct i2c_client *client) 744 { 745 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client); 746 747 mlxsw_core_bus_device_unregister(mlxsw_i2c->core, false); 748 mlxsw_i2c_irq_fini(mlxsw_i2c); 749 mutex_destroy(&mlxsw_i2c->cmd.lock); 750 } 751 752 int mlxsw_i2c_driver_register(struct i2c_driver *i2c_driver) 753 { 754 i2c_driver->probe = mlxsw_i2c_probe; 755 i2c_driver->remove = mlxsw_i2c_remove; 756 return i2c_add_driver(i2c_driver); 757 } 758 EXPORT_SYMBOL(mlxsw_i2c_driver_register); 759 760 void mlxsw_i2c_driver_unregister(struct i2c_driver *i2c_driver) 761 { 762 i2c_del_driver(i2c_driver); 763 } 764 EXPORT_SYMBOL(mlxsw_i2c_driver_unregister); 765 766 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>"); 767 MODULE_DESCRIPTION("Mellanox switch I2C interface driver"); 768 MODULE_LICENSE("Dual BSD/GPL"); 769