1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/err.h> 5 #include <linux/i2c.h> 6 #include <linux/init.h> 7 #include <linux/jiffies.h> 8 #include <linux/kernel.h> 9 #include <linux/mutex.h> 10 #include <linux/module.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/slab.h> 13 14 #include "cmd.h" 15 #include "core.h" 16 #include "i2c.h" 17 #include "resources.h" 18 19 #define MLXSW_I2C_CIR2_BASE 0x72000 20 #define MLXSW_I2C_CIR_STATUS_OFF 0x18 21 #define MLXSW_I2C_CIR2_OFF_STATUS (MLXSW_I2C_CIR2_BASE + \ 22 MLXSW_I2C_CIR_STATUS_OFF) 23 #define MLXSW_I2C_OPMOD_SHIFT 12 24 #define MLXSW_I2C_EVENT_BIT_SHIFT 22 25 #define MLXSW_I2C_GO_BIT_SHIFT 23 26 #define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT 24 27 #define MLXSW_I2C_EVENT_BIT BIT(MLXSW_I2C_EVENT_BIT_SHIFT) 28 #define MLXSW_I2C_GO_BIT BIT(MLXSW_I2C_GO_BIT_SHIFT) 29 #define MLXSW_I2C_GO_OPMODE BIT(MLXSW_I2C_OPMOD_SHIFT) 30 #define MLXSW_I2C_SET_IMM_CMD (MLXSW_I2C_GO_OPMODE | \ 31 MLXSW_CMD_OPCODE_QUERY_FW) 32 #define MLXSW_I2C_PUSH_IMM_CMD (MLXSW_I2C_GO_BIT | \ 33 MLXSW_I2C_SET_IMM_CMD) 34 #define MLXSW_I2C_SET_CMD (MLXSW_CMD_OPCODE_ACCESS_REG) 35 #define MLXSW_I2C_PUSH_CMD (MLXSW_I2C_GO_BIT | MLXSW_I2C_SET_CMD) 36 #define MLXSW_I2C_TLV_HDR_SIZE 0x10 37 #define MLXSW_I2C_ADDR_WIDTH 4 38 #define MLXSW_I2C_PUSH_CMD_SIZE (MLXSW_I2C_ADDR_WIDTH + 4) 39 #define MLXSW_I2C_SET_EVENT_CMD (MLXSW_I2C_EVENT_BIT) 40 #define MLXSW_I2C_PUSH_EVENT_CMD (MLXSW_I2C_GO_BIT | \ 41 MLXSW_I2C_SET_EVENT_CMD) 42 #define MLXSW_I2C_READ_SEMA_SIZE 4 43 #define MLXSW_I2C_PREP_SIZE (MLXSW_I2C_ADDR_WIDTH + 28) 44 #define MLXSW_I2C_MBOX_SIZE 20 45 #define MLXSW_I2C_MBOX_OUT_PARAM_OFF 12 46 #define MLXSW_I2C_MAX_BUFF_SIZE 32 47 #define MLXSW_I2C_MBOX_OFFSET_BITS 20 48 #define MLXSW_I2C_MBOX_SIZE_BITS 12 49 #define MLXSW_I2C_ADDR_BUF_SIZE 4 50 #define MLXSW_I2C_BLK_MAX 32 51 #define MLXSW_I2C_RETRY 5 52 #define MLXSW_I2C_TIMEOUT_MSECS 5000 53 #define MLXSW_I2C_MAX_DATA_SIZE 256 54 55 /** 56 * struct mlxsw_i2c - device private data: 57 * @cmd.mb_size_in: input mailbox size; 58 * @cmd.mb_off_in: input mailbox offset in register space; 59 * @cmd.mb_size_out: output mailbox size; 60 * @cmd.mb_off_out: output mailbox offset in register space; 61 * @cmd.lock: command execution lock; 62 * @dev: I2C device; 63 * @core: switch core pointer; 64 * @bus_info: bus info block; 65 */ 66 struct mlxsw_i2c { 67 struct { 68 u32 mb_size_in; 69 u32 mb_off_in; 70 u32 mb_size_out; 71 u32 mb_off_out; 72 struct mutex lock; 73 } cmd; 74 struct device *dev; 75 struct mlxsw_core *core; 76 struct mlxsw_bus_info bus_info; 77 }; 78 79 #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) { \ 80 { .addr = (_client)->addr, \ 81 .buf = (_addr_buf), \ 82 .len = MLXSW_I2C_ADDR_BUF_SIZE, \ 83 .flags = 0 }, \ 84 { .addr = (_client)->addr, \ 85 .buf = (_buf), \ 86 .len = (_len), \ 87 .flags = I2C_M_RD } } 88 89 #define MLXSW_I2C_WRITE_MSG(_client, _buf, _len) \ 90 { .addr = (_client)->addr, \ 91 .buf = (u8 *)(_buf), \ 92 .len = (_len), \ 93 .flags = 0 } 94 95 /* Routine converts in and out mail boxes offset and size. */ 96 static inline void 97 mlxsw_i2c_convert_mbox(struct mlxsw_i2c *mlxsw_i2c, u8 *buf) 98 { 99 u32 tmp; 100 101 /* Local in/out mailboxes: 20 bits for offset, 12 for size */ 102 tmp = be32_to_cpup((__be32 *) buf); 103 mlxsw_i2c->cmd.mb_off_in = tmp & 104 GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0); 105 mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31, 106 MLXSW_I2C_MBOX_OFFSET_BITS)) >> 107 MLXSW_I2C_MBOX_OFFSET_BITS; 108 109 tmp = be32_to_cpup((__be32 *) (buf + MLXSW_I2C_ADDR_WIDTH)); 110 mlxsw_i2c->cmd.mb_off_out = tmp & 111 GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0); 112 mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31, 113 MLXSW_I2C_MBOX_OFFSET_BITS)) >> 114 MLXSW_I2C_MBOX_OFFSET_BITS; 115 } 116 117 /* Routine obtains register size from mail box buffer. */ 118 static inline int mlxsw_i2c_get_reg_size(u8 *in_mbox) 119 { 120 u16 tmp = be16_to_cpup((__be16 *) (in_mbox + MLXSW_I2C_TLV_HDR_SIZE)); 121 122 return (tmp & 0x7ff) * 4 + MLXSW_I2C_TLV_HDR_SIZE; 123 } 124 125 /* Routine sets I2C device internal offset in the transaction buffer. */ 126 static inline void mlxsw_i2c_set_slave_addr(u8 *buf, u32 off) 127 { 128 __be32 *val = (__be32 *) buf; 129 130 *val = htonl(off); 131 } 132 133 /* Routine waits until go bit is cleared. */ 134 static int mlxsw_i2c_wait_go_bit(struct i2c_client *client, 135 struct mlxsw_i2c *mlxsw_i2c, u8 *p_status) 136 { 137 u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE]; 138 u8 buf[MLXSW_I2C_READ_SEMA_SIZE]; 139 int len = MLXSW_I2C_READ_SEMA_SIZE; 140 struct i2c_msg read_sema[] = 141 MLXSW_I2C_READ_MSG(client, addr_buf, buf, len); 142 bool wait_done = false; 143 unsigned long end; 144 int i = 0, err; 145 146 mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_OFF_STATUS); 147 148 end = jiffies + msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS); 149 do { 150 u32 ctrl; 151 152 err = i2c_transfer(client->adapter, read_sema, 153 ARRAY_SIZE(read_sema)); 154 155 ctrl = be32_to_cpu(*(__be32 *) buf); 156 if (err == ARRAY_SIZE(read_sema)) { 157 if (!(ctrl & MLXSW_I2C_GO_BIT)) { 158 wait_done = true; 159 *p_status = ctrl >> 160 MLXSW_I2C_CIR_CTRL_STATUS_SHIFT; 161 break; 162 } 163 } 164 cond_resched(); 165 } while ((time_before(jiffies, end)) || (i++ < MLXSW_I2C_RETRY)); 166 167 if (wait_done) { 168 if (*p_status) 169 err = -EIO; 170 } else { 171 return -ETIMEDOUT; 172 } 173 174 return err > 0 ? 0 : err; 175 } 176 177 /* Routine posts a command to ASIC through mail box. */ 178 static int mlxsw_i2c_write_cmd(struct i2c_client *client, 179 struct mlxsw_i2c *mlxsw_i2c, 180 int immediate) 181 { 182 __be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = { 183 0, cpu_to_be32(MLXSW_I2C_PUSH_IMM_CMD) 184 }; 185 __be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = { 186 0, 0, 0, 0, 0, 0, 187 cpu_to_be32(client->adapter->nr & 0xffff), 188 cpu_to_be32(MLXSW_I2C_SET_IMM_CMD) 189 }; 190 struct i2c_msg push_cmd = 191 MLXSW_I2C_WRITE_MSG(client, push_cmd_buf, 192 MLXSW_I2C_PUSH_CMD_SIZE); 193 struct i2c_msg prep_cmd = 194 MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE); 195 int err; 196 197 if (!immediate) { 198 push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_CMD); 199 prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_SET_CMD); 200 } 201 mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf, 202 MLXSW_I2C_CIR2_BASE); 203 mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf, 204 MLXSW_I2C_CIR2_OFF_STATUS); 205 206 /* Prepare Command Interface Register for transaction */ 207 err = i2c_transfer(client->adapter, &prep_cmd, 1); 208 if (err < 0) 209 return err; 210 else if (err != 1) 211 return -EIO; 212 213 /* Write out Command Interface Register GO bit to push transaction */ 214 err = i2c_transfer(client->adapter, &push_cmd, 1); 215 if (err < 0) 216 return err; 217 else if (err != 1) 218 return -EIO; 219 220 return 0; 221 } 222 223 /* Routine posts initialization command to ASIC through mail box. */ 224 static int 225 mlxsw_i2c_write_init_cmd(struct i2c_client *client, 226 struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod) 227 { 228 __be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = { 229 0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD) 230 }; 231 __be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = { 232 0, 0, 0, 0, 0, 0, 233 cpu_to_be32(client->adapter->nr & 0xffff), 234 cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD) 235 }; 236 struct i2c_msg push_cmd = 237 MLXSW_I2C_WRITE_MSG(client, push_cmd_buf, 238 MLXSW_I2C_PUSH_CMD_SIZE); 239 struct i2c_msg prep_cmd = 240 MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE); 241 u8 status; 242 int err; 243 244 push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD | opcode); 245 prep_cmd_buf[3] = cpu_to_be32(in_mod); 246 prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_GO_BIT | opcode); 247 mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf, 248 MLXSW_I2C_CIR2_BASE); 249 mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf, 250 MLXSW_I2C_CIR2_OFF_STATUS); 251 252 /* Prepare Command Interface Register for transaction */ 253 err = i2c_transfer(client->adapter, &prep_cmd, 1); 254 if (err < 0) 255 return err; 256 else if (err != 1) 257 return -EIO; 258 259 /* Write out Command Interface Register GO bit to push transaction */ 260 err = i2c_transfer(client->adapter, &push_cmd, 1); 261 if (err < 0) 262 return err; 263 else if (err != 1) 264 return -EIO; 265 266 /* Wait until go bit is cleared. */ 267 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status); 268 if (err) { 269 dev_err(&client->dev, "HW semaphore is not released"); 270 return err; 271 } 272 273 /* Validate transaction completion status. */ 274 if (status) { 275 dev_err(&client->dev, "Bad transaction completion status %x\n", 276 status); 277 return -EIO; 278 } 279 280 return 0; 281 } 282 283 /* Routine obtains mail box offsets from ASIC register space. */ 284 static int mlxsw_i2c_get_mbox(struct i2c_client *client, 285 struct mlxsw_i2c *mlxsw_i2c) 286 { 287 u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE]; 288 u8 buf[MLXSW_I2C_MBOX_SIZE]; 289 struct i2c_msg mbox_cmd[] = 290 MLXSW_I2C_READ_MSG(client, addr_buf, buf, MLXSW_I2C_MBOX_SIZE); 291 int err; 292 293 /* Read mail boxes offsets. */ 294 mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_BASE); 295 err = i2c_transfer(client->adapter, mbox_cmd, 2); 296 if (err != 2) { 297 dev_err(&client->dev, "Could not obtain mail boxes\n"); 298 if (!err) 299 return -EIO; 300 else 301 return err; 302 } 303 304 /* Convert mail boxes. */ 305 mlxsw_i2c_convert_mbox(mlxsw_i2c, &buf[MLXSW_I2C_MBOX_OUT_PARAM_OFF]); 306 307 return err; 308 } 309 310 /* Routine sends I2C write transaction to ASIC device. */ 311 static int 312 mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num, 313 u8 *p_status) 314 { 315 struct i2c_client *client = to_i2c_client(dev); 316 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client); 317 unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS); 318 u8 tran_buf[MLXSW_I2C_MAX_BUFF_SIZE + MLXSW_I2C_ADDR_BUF_SIZE]; 319 int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j; 320 unsigned long end; 321 struct i2c_msg write_tran = 322 MLXSW_I2C_WRITE_MSG(client, tran_buf, MLXSW_I2C_PUSH_CMD_SIZE); 323 int err; 324 325 for (i = 0; i < num; i++) { 326 chunk_size = (in_mbox_size > MLXSW_I2C_BLK_MAX) ? 327 MLXSW_I2C_BLK_MAX : in_mbox_size; 328 write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size; 329 mlxsw_i2c_set_slave_addr(tran_buf, off); 330 memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox + 331 MLXSW_I2C_BLK_MAX * i, chunk_size); 332 333 j = 0; 334 end = jiffies + timeout; 335 do { 336 err = i2c_transfer(client->adapter, &write_tran, 1); 337 if (err == 1) 338 break; 339 340 cond_resched(); 341 } while ((time_before(jiffies, end)) || 342 (j++ < MLXSW_I2C_RETRY)); 343 344 if (err != 1) { 345 if (!err) 346 err = -EIO; 347 return err; 348 } 349 350 off += chunk_size; 351 in_mbox_size -= chunk_size; 352 } 353 354 /* Prepare and write out Command Interface Register for transaction. */ 355 err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0); 356 if (err) { 357 dev_err(&client->dev, "Could not start transaction"); 358 return -EIO; 359 } 360 361 /* Wait until go bit is cleared. */ 362 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status); 363 if (err) { 364 dev_err(&client->dev, "HW semaphore is not released"); 365 return err; 366 } 367 368 /* Validate transaction completion status. */ 369 if (*p_status) { 370 dev_err(&client->dev, "Bad transaction completion status %x\n", 371 *p_status); 372 return -EIO; 373 } 374 375 return 0; 376 } 377 378 /* Routine executes I2C command. */ 379 static int 380 mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size, 381 u8 *in_mbox, size_t out_mbox_size, u8 *out_mbox, u8 *status) 382 { 383 struct i2c_client *client = to_i2c_client(dev); 384 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client); 385 unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS); 386 u8 tran_buf[MLXSW_I2C_ADDR_BUF_SIZE]; 387 int num, chunk_size, reg_size, i, j; 388 int off = mlxsw_i2c->cmd.mb_off_out; 389 unsigned long end; 390 struct i2c_msg read_tran[] = 391 MLXSW_I2C_READ_MSG(client, tran_buf, NULL, 0); 392 int err; 393 394 WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 395 396 if (in_mbox) { 397 reg_size = mlxsw_i2c_get_reg_size(in_mbox); 398 num = reg_size / MLXSW_I2C_BLK_MAX; 399 if (reg_size % MLXSW_I2C_BLK_MAX) 400 num++; 401 402 if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { 403 dev_err(&client->dev, "Could not acquire lock"); 404 return -EINVAL; 405 } 406 407 err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status); 408 if (err) 409 goto cmd_fail; 410 411 /* No out mailbox is case of write transaction. */ 412 if (!out_mbox) { 413 mutex_unlock(&mlxsw_i2c->cmd.lock); 414 return 0; 415 } 416 } else { 417 /* No input mailbox is case of initialization query command. */ 418 reg_size = MLXSW_I2C_MAX_DATA_SIZE; 419 num = reg_size / MLXSW_I2C_BLK_MAX; 420 421 if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { 422 dev_err(&client->dev, "Could not acquire lock"); 423 return -EINVAL; 424 } 425 426 err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode, 427 in_mod); 428 if (err) 429 goto cmd_fail; 430 } 431 432 /* Send read transaction to get output mailbox content. */ 433 read_tran[1].buf = out_mbox; 434 for (i = 0; i < num; i++) { 435 chunk_size = (reg_size > MLXSW_I2C_BLK_MAX) ? 436 MLXSW_I2C_BLK_MAX : reg_size; 437 read_tran[1].len = chunk_size; 438 mlxsw_i2c_set_slave_addr(tran_buf, off); 439 440 j = 0; 441 end = jiffies + timeout; 442 do { 443 err = i2c_transfer(client->adapter, read_tran, 444 ARRAY_SIZE(read_tran)); 445 if (err == ARRAY_SIZE(read_tran)) 446 break; 447 448 cond_resched(); 449 } while ((time_before(jiffies, end)) || 450 (j++ < MLXSW_I2C_RETRY)); 451 452 if (err != ARRAY_SIZE(read_tran)) { 453 if (!err) 454 err = -EIO; 455 456 goto cmd_fail; 457 } 458 459 off += chunk_size; 460 reg_size -= chunk_size; 461 read_tran[1].buf += chunk_size; 462 } 463 464 mutex_unlock(&mlxsw_i2c->cmd.lock); 465 466 return 0; 467 468 cmd_fail: 469 mutex_unlock(&mlxsw_i2c->cmd.lock); 470 return err; 471 } 472 473 static int mlxsw_i2c_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 474 u32 in_mod, bool out_mbox_direct, 475 char *in_mbox, size_t in_mbox_size, 476 char *out_mbox, size_t out_mbox_size, 477 u8 *status) 478 { 479 struct mlxsw_i2c *mlxsw_i2c = bus_priv; 480 481 return mlxsw_i2c_cmd(mlxsw_i2c->dev, opcode, in_mod, in_mbox_size, 482 in_mbox, out_mbox_size, out_mbox, status); 483 } 484 485 static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv, 486 const struct mlxsw_tx_info *tx_info) 487 { 488 return false; 489 } 490 491 static int mlxsw_i2c_skb_transmit(void *bus_priv, struct sk_buff *skb, 492 const struct mlxsw_tx_info *tx_info) 493 { 494 return 0; 495 } 496 497 static int 498 mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 499 const struct mlxsw_config_profile *profile, 500 struct mlxsw_res *res) 501 { 502 struct mlxsw_i2c *mlxsw_i2c = bus_priv; 503 char *mbox; 504 int err; 505 506 mlxsw_i2c->core = mlxsw_core; 507 508 mbox = mlxsw_cmd_mbox_alloc(); 509 if (!mbox) 510 return -ENOMEM; 511 512 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 513 514 mlxsw_cmd_mbox_free(mbox); 515 return err; 516 } 517 518 static void mlxsw_i2c_fini(void *bus_priv) 519 { 520 struct mlxsw_i2c *mlxsw_i2c = bus_priv; 521 522 mlxsw_i2c->core = NULL; 523 } 524 525 static const struct mlxsw_bus mlxsw_i2c_bus = { 526 .kind = "i2c", 527 .init = mlxsw_i2c_init, 528 .fini = mlxsw_i2c_fini, 529 .skb_transmit_busy = mlxsw_i2c_skb_transmit_busy, 530 .skb_transmit = mlxsw_i2c_skb_transmit, 531 .cmd_exec = mlxsw_i2c_cmd_exec, 532 }; 533 534 static int mlxsw_i2c_probe(struct i2c_client *client, 535 const struct i2c_device_id *id) 536 { 537 struct mlxsw_i2c *mlxsw_i2c; 538 u8 status; 539 int err; 540 541 mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL); 542 if (!mlxsw_i2c) 543 return -ENOMEM; 544 545 i2c_set_clientdata(client, mlxsw_i2c); 546 mutex_init(&mlxsw_i2c->cmd.lock); 547 548 /* In order to use mailboxes through the i2c, special area is reserved 549 * on the i2c address space that can be used for input and output 550 * mailboxes. Such mailboxes are called local mailboxes. When using a 551 * local mailbox, software should specify 0 as the Input/Output 552 * parameters. The location of the Local Mailbox addresses on the i2c 553 * space can be retrieved through the QUERY_FW command. 554 * For this purpose QUERY_FW is to be issued with opcode modifier equal 555 * 0x01. For such command the output parameter is an immediate value. 556 * Here QUERY_FW command is invoked for ASIC probing and for getting 557 * local mailboxes addresses from immedate output parameters. 558 */ 559 560 /* Prepare and write out Command Interface Register for transaction */ 561 err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 1); 562 if (err) { 563 dev_err(&client->dev, "Could not start transaction"); 564 goto errout; 565 } 566 567 /* Wait until go bit is cleared. */ 568 err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status); 569 if (err) { 570 dev_err(&client->dev, "HW semaphore is not released"); 571 goto errout; 572 } 573 574 /* Validate transaction completion status. */ 575 if (status) { 576 dev_err(&client->dev, "Bad transaction completion status %x\n", 577 status); 578 err = -EIO; 579 goto errout; 580 } 581 582 /* Get mailbox offsets. */ 583 err = mlxsw_i2c_get_mbox(client, mlxsw_i2c); 584 if (err < 0) { 585 dev_err(&client->dev, "Fail to get mailboxes\n"); 586 goto errout; 587 } 588 589 dev_info(&client->dev, "%s mb size=%x off=0x%08x out mb size=%x off=0x%08x\n", 590 id->name, mlxsw_i2c->cmd.mb_size_in, 591 mlxsw_i2c->cmd.mb_off_in, mlxsw_i2c->cmd.mb_size_out, 592 mlxsw_i2c->cmd.mb_off_out); 593 594 /* Register device bus. */ 595 mlxsw_i2c->bus_info.device_kind = id->name; 596 mlxsw_i2c->bus_info.device_name = client->name; 597 mlxsw_i2c->bus_info.dev = &client->dev; 598 mlxsw_i2c->bus_info.low_frequency = true; 599 mlxsw_i2c->dev = &client->dev; 600 601 err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info, 602 &mlxsw_i2c_bus, mlxsw_i2c, false, 603 NULL); 604 if (err) { 605 dev_err(&client->dev, "Fail to register core bus\n"); 606 return err; 607 } 608 609 return 0; 610 611 errout: 612 i2c_set_clientdata(client, NULL); 613 614 return err; 615 } 616 617 static int mlxsw_i2c_remove(struct i2c_client *client) 618 { 619 struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client); 620 621 mlxsw_core_bus_device_unregister(mlxsw_i2c->core, false); 622 mutex_destroy(&mlxsw_i2c->cmd.lock); 623 624 return 0; 625 } 626 627 int mlxsw_i2c_driver_register(struct i2c_driver *i2c_driver) 628 { 629 i2c_driver->probe = mlxsw_i2c_probe; 630 i2c_driver->remove = mlxsw_i2c_remove; 631 return i2c_add_driver(i2c_driver); 632 } 633 EXPORT_SYMBOL(mlxsw_i2c_driver_register); 634 635 void mlxsw_i2c_driver_unregister(struct i2c_driver *i2c_driver) 636 { 637 i2c_del_driver(i2c_driver); 638 } 639 EXPORT_SYMBOL(mlxsw_i2c_driver_unregister); 640 641 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>"); 642 MODULE_DESCRIPTION("Mellanox switch I2C interface driver"); 643 MODULE_LICENSE("Dual BSD/GPL"); 644