1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u8 local_port; 51 }; 52 53 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 54 { 55 return mlxsw_core_port->port_driver_priv; 56 } 57 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 58 59 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 60 { 61 return mlxsw_core_port->port_driver_priv != NULL; 62 } 63 64 struct mlxsw_core { 65 struct mlxsw_driver *driver; 66 const struct mlxsw_bus *bus; 67 void *bus_priv; 68 const struct mlxsw_bus_info *bus_info; 69 struct workqueue_struct *emad_wq; 70 struct list_head rx_listener_list; 71 struct list_head event_listener_list; 72 struct { 73 atomic64_t tid; 74 struct list_head trans_list; 75 spinlock_t trans_list_lock; /* protects trans_list writes */ 76 bool use_emad; 77 bool enable_string_tlv; 78 } emad; 79 struct { 80 u8 *mapping; /* lag_id+port_index to local_port mapping */ 81 } lag; 82 struct mlxsw_res res; 83 struct mlxsw_hwmon *hwmon; 84 struct mlxsw_thermal *thermal; 85 struct mlxsw_core_port *ports; 86 unsigned int max_ports; 87 atomic_t active_ports_count; 88 bool fw_flash_in_progress; 89 struct { 90 struct devlink_health_reporter *fw_fatal; 91 } health; 92 struct mlxsw_env *env; 93 unsigned long driver_priv[]; 94 /* driver_priv has to be always the last item */ 95 }; 96 97 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 98 99 static u64 mlxsw_ports_occ_get(void *priv) 100 { 101 struct mlxsw_core *mlxsw_core = priv; 102 103 return atomic_read(&mlxsw_core->active_ports_count); 104 } 105 106 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 107 { 108 struct devlink *devlink = priv_to_devlink(mlxsw_core); 109 struct devlink_resource_size_params ports_num_params; 110 u32 max_ports; 111 112 max_ports = mlxsw_core->max_ports - 1; 113 devlink_resource_size_params_init(&ports_num_params, max_ports, 114 max_ports, 1, 115 DEVLINK_RESOURCE_UNIT_ENTRY); 116 117 return devlink_resource_register(devlink, 118 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 119 max_ports, MLXSW_CORE_RESOURCE_PORTS, 120 DEVLINK_RESOURCE_ID_PARENT_TOP, 121 &ports_num_params); 122 } 123 124 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 125 { 126 struct devlink *devlink = priv_to_devlink(mlxsw_core); 127 int err; 128 129 /* Switch ports are numbered from 1 to queried value */ 130 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 131 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 132 MAX_SYSTEM_PORT) + 1; 133 else 134 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 135 136 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 137 sizeof(struct mlxsw_core_port), GFP_KERNEL); 138 if (!mlxsw_core->ports) 139 return -ENOMEM; 140 141 if (!reload) { 142 err = mlxsw_core_resources_ports_register(mlxsw_core); 143 if (err) 144 goto err_resources_ports_register; 145 } 146 atomic_set(&mlxsw_core->active_ports_count, 0); 147 devlink_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 148 mlxsw_ports_occ_get, mlxsw_core); 149 150 return 0; 151 152 err_resources_ports_register: 153 kfree(mlxsw_core->ports); 154 return err; 155 } 156 157 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 158 { 159 struct devlink *devlink = priv_to_devlink(mlxsw_core); 160 161 devlink_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 162 if (!reload) 163 devlink_resources_unregister(priv_to_devlink(mlxsw_core), NULL); 164 165 kfree(mlxsw_core->ports); 166 } 167 168 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 169 { 170 return mlxsw_core->max_ports; 171 } 172 EXPORT_SYMBOL(mlxsw_core_max_ports); 173 174 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 175 { 176 return mlxsw_core->driver_priv; 177 } 178 EXPORT_SYMBOL(mlxsw_core_driver_priv); 179 180 bool mlxsw_core_res_query_enabled(const struct mlxsw_core *mlxsw_core) 181 { 182 return mlxsw_core->driver->res_query_enabled; 183 } 184 EXPORT_SYMBOL(mlxsw_core_res_query_enabled); 185 186 bool mlxsw_core_temp_warn_enabled(const struct mlxsw_core *mlxsw_core) 187 { 188 return mlxsw_core->driver->temp_warn_enabled; 189 } 190 191 bool 192 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 193 const struct mlxsw_fw_rev *req_rev) 194 { 195 return rev->minor > req_rev->minor || 196 (rev->minor == req_rev->minor && 197 rev->subminor >= req_rev->subminor); 198 } 199 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 200 201 struct mlxsw_rx_listener_item { 202 struct list_head list; 203 struct mlxsw_rx_listener rxl; 204 void *priv; 205 bool enabled; 206 }; 207 208 struct mlxsw_event_listener_item { 209 struct list_head list; 210 struct mlxsw_core *mlxsw_core; 211 struct mlxsw_event_listener el; 212 void *priv; 213 }; 214 215 /****************** 216 * EMAD processing 217 ******************/ 218 219 /* emad_eth_hdr_dmac 220 * Destination MAC in EMAD's Ethernet header. 221 * Must be set to 01:02:c9:00:00:01 222 */ 223 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 224 225 /* emad_eth_hdr_smac 226 * Source MAC in EMAD's Ethernet header. 227 * Must be set to 00:02:c9:01:02:03 228 */ 229 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 230 231 /* emad_eth_hdr_ethertype 232 * Ethertype in EMAD's Ethernet header. 233 * Must be set to 0x8932 234 */ 235 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 236 237 /* emad_eth_hdr_mlx_proto 238 * Mellanox protocol. 239 * Must be set to 0x0. 240 */ 241 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 242 243 /* emad_eth_hdr_ver 244 * Mellanox protocol version. 245 * Must be set to 0x0. 246 */ 247 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 248 249 /* emad_op_tlv_type 250 * Type of the TLV. 251 * Must be set to 0x1 (operation TLV). 252 */ 253 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 254 255 /* emad_op_tlv_len 256 * Length of the operation TLV in u32. 257 * Must be set to 0x4. 258 */ 259 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 260 261 /* emad_op_tlv_dr 262 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 263 * EMAD. DR TLV must follow. 264 * 265 * Note: Currently not supported and must not be set. 266 */ 267 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 268 269 /* emad_op_tlv_status 270 * Returned status in case of EMAD response. Must be set to 0 in case 271 * of EMAD request. 272 * 0x0 - success 273 * 0x1 - device is busy. Requester should retry 274 * 0x2 - Mellanox protocol version not supported 275 * 0x3 - unknown TLV 276 * 0x4 - register not supported 277 * 0x5 - operation class not supported 278 * 0x6 - EMAD method not supported 279 * 0x7 - bad parameter (e.g. port out of range) 280 * 0x8 - resource not available 281 * 0x9 - message receipt acknowledgment. Requester should retry 282 * 0x70 - internal error 283 */ 284 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 285 286 /* emad_op_tlv_register_id 287 * Register ID of register within register TLV. 288 */ 289 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 290 291 /* emad_op_tlv_r 292 * Response bit. Setting to 1 indicates Response, otherwise request. 293 */ 294 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 295 296 /* emad_op_tlv_method 297 * EMAD method type. 298 * 0x1 - query 299 * 0x2 - write 300 * 0x3 - send (currently not supported) 301 * 0x4 - event 302 */ 303 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 304 305 /* emad_op_tlv_class 306 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 307 */ 308 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 309 310 /* emad_op_tlv_tid 311 * EMAD transaction ID. Used for pairing request and response EMADs. 312 */ 313 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 314 315 /* emad_string_tlv_type 316 * Type of the TLV. 317 * Must be set to 0x2 (string TLV). 318 */ 319 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 320 321 /* emad_string_tlv_len 322 * Length of the string TLV in u32. 323 */ 324 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 325 326 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 327 328 /* emad_string_tlv_string 329 * String provided by the device's firmware in case of erroneous register access 330 */ 331 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 332 MLXSW_EMAD_STRING_TLV_STRING_LEN); 333 334 /* emad_reg_tlv_type 335 * Type of the TLV. 336 * Must be set to 0x3 (register TLV). 337 */ 338 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 339 340 /* emad_reg_tlv_len 341 * Length of the operation TLV in u32. 342 */ 343 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 344 345 /* emad_end_tlv_type 346 * Type of the TLV. 347 * Must be set to 0x0 (end TLV). 348 */ 349 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 350 351 /* emad_end_tlv_len 352 * Length of the end TLV in u32. 353 * Must be set to 1. 354 */ 355 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 356 357 enum mlxsw_core_reg_access_type { 358 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 359 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 360 }; 361 362 static inline const char * 363 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 364 { 365 switch (type) { 366 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 367 return "query"; 368 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 369 return "write"; 370 } 371 BUG(); 372 } 373 374 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 375 { 376 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 377 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 378 } 379 380 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 381 const struct mlxsw_reg_info *reg, 382 char *payload) 383 { 384 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 385 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 386 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 387 } 388 389 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 390 { 391 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 392 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 393 } 394 395 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 396 const struct mlxsw_reg_info *reg, 397 enum mlxsw_core_reg_access_type type, 398 u64 tid) 399 { 400 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 401 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 402 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 403 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 404 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 405 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 406 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 407 mlxsw_emad_op_tlv_method_set(op_tlv, 408 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 409 else 410 mlxsw_emad_op_tlv_method_set(op_tlv, 411 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 412 mlxsw_emad_op_tlv_class_set(op_tlv, 413 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 414 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 415 } 416 417 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 418 { 419 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 420 421 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 422 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 423 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 424 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 425 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 426 427 skb_reset_mac_header(skb); 428 429 return 0; 430 } 431 432 static void mlxsw_emad_construct(struct sk_buff *skb, 433 const struct mlxsw_reg_info *reg, 434 char *payload, 435 enum mlxsw_core_reg_access_type type, 436 u64 tid, bool enable_string_tlv) 437 { 438 char *buf; 439 440 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 441 mlxsw_emad_pack_end_tlv(buf); 442 443 buf = skb_push(skb, reg->len + sizeof(u32)); 444 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 445 446 if (enable_string_tlv) { 447 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 448 mlxsw_emad_pack_string_tlv(buf); 449 } 450 451 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 452 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 453 454 mlxsw_emad_construct_eth_hdr(skb); 455 } 456 457 struct mlxsw_emad_tlv_offsets { 458 u16 op_tlv; 459 u16 string_tlv; 460 u16 reg_tlv; 461 }; 462 463 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 464 { 465 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 466 467 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 468 } 469 470 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 471 { 472 struct mlxsw_emad_tlv_offsets *offsets = 473 (struct mlxsw_emad_tlv_offsets *) skb->cb; 474 475 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 476 offsets->string_tlv = 0; 477 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 478 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 479 480 /* If string TLV is present, it must come after the operation TLV. */ 481 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 482 offsets->string_tlv = offsets->reg_tlv; 483 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 484 } 485 } 486 487 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 488 { 489 struct mlxsw_emad_tlv_offsets *offsets = 490 (struct mlxsw_emad_tlv_offsets *) skb->cb; 491 492 return ((char *) (skb->data + offsets->op_tlv)); 493 } 494 495 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 496 { 497 struct mlxsw_emad_tlv_offsets *offsets = 498 (struct mlxsw_emad_tlv_offsets *) skb->cb; 499 500 if (!offsets->string_tlv) 501 return NULL; 502 503 return ((char *) (skb->data + offsets->string_tlv)); 504 } 505 506 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 507 { 508 struct mlxsw_emad_tlv_offsets *offsets = 509 (struct mlxsw_emad_tlv_offsets *) skb->cb; 510 511 return ((char *) (skb->data + offsets->reg_tlv)); 512 } 513 514 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 515 { 516 return ((char *) (reg_tlv + sizeof(u32))); 517 } 518 519 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 520 { 521 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 522 } 523 524 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 525 { 526 char *op_tlv; 527 528 op_tlv = mlxsw_emad_op_tlv(skb); 529 return mlxsw_emad_op_tlv_tid_get(op_tlv); 530 } 531 532 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 533 { 534 char *op_tlv; 535 536 op_tlv = mlxsw_emad_op_tlv(skb); 537 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 538 } 539 540 static int mlxsw_emad_process_status(char *op_tlv, 541 enum mlxsw_emad_op_tlv_status *p_status) 542 { 543 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 544 545 switch (*p_status) { 546 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 547 return 0; 548 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 549 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 550 return -EAGAIN; 551 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 552 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 553 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 554 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 555 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 556 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 557 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 558 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 559 default: 560 return -EIO; 561 } 562 } 563 564 static int 565 mlxsw_emad_process_status_skb(struct sk_buff *skb, 566 enum mlxsw_emad_op_tlv_status *p_status) 567 { 568 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 569 } 570 571 struct mlxsw_reg_trans { 572 struct list_head list; 573 struct list_head bulk_list; 574 struct mlxsw_core *core; 575 struct sk_buff *tx_skb; 576 struct mlxsw_tx_info tx_info; 577 struct delayed_work timeout_dw; 578 unsigned int retries; 579 u64 tid; 580 struct completion completion; 581 atomic_t active; 582 mlxsw_reg_trans_cb_t *cb; 583 unsigned long cb_priv; 584 const struct mlxsw_reg_info *reg; 585 enum mlxsw_core_reg_access_type type; 586 int err; 587 char *emad_err_string; 588 enum mlxsw_emad_op_tlv_status emad_status; 589 struct rcu_head rcu; 590 }; 591 592 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 593 struct mlxsw_reg_trans *trans) 594 { 595 char *string_tlv; 596 char *string; 597 598 string_tlv = mlxsw_emad_string_tlv(skb); 599 if (!string_tlv) 600 return; 601 602 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 603 GFP_ATOMIC); 604 if (!trans->emad_err_string) 605 return; 606 607 string = mlxsw_emad_string_tlv_string_data(string_tlv); 608 strlcpy(trans->emad_err_string, string, 609 MLXSW_EMAD_STRING_TLV_STRING_LEN); 610 } 611 612 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 613 #define MLXSW_EMAD_TIMEOUT_MS 200 614 615 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 616 { 617 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 618 619 if (trans->core->fw_flash_in_progress) 620 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 621 622 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 623 timeout << trans->retries); 624 } 625 626 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 627 struct mlxsw_reg_trans *trans) 628 { 629 struct sk_buff *skb; 630 int err; 631 632 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 633 if (!skb) 634 return -ENOMEM; 635 636 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 637 skb->data + mlxsw_core->driver->txhdr_len, 638 skb->len - mlxsw_core->driver->txhdr_len); 639 640 atomic_set(&trans->active, 1); 641 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 642 if (err) { 643 dev_kfree_skb(skb); 644 return err; 645 } 646 mlxsw_emad_trans_timeout_schedule(trans); 647 return 0; 648 } 649 650 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 651 { 652 struct mlxsw_core *mlxsw_core = trans->core; 653 654 dev_kfree_skb(trans->tx_skb); 655 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 656 list_del_rcu(&trans->list); 657 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 658 trans->err = err; 659 complete(&trans->completion); 660 } 661 662 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 663 struct mlxsw_reg_trans *trans) 664 { 665 int err; 666 667 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 668 trans->retries++; 669 err = mlxsw_emad_transmit(trans->core, trans); 670 if (err == 0) 671 return; 672 673 if (!atomic_dec_and_test(&trans->active)) 674 return; 675 } else { 676 err = -EIO; 677 } 678 mlxsw_emad_trans_finish(trans, err); 679 } 680 681 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 682 { 683 struct mlxsw_reg_trans *trans = container_of(work, 684 struct mlxsw_reg_trans, 685 timeout_dw.work); 686 687 if (!atomic_dec_and_test(&trans->active)) 688 return; 689 690 mlxsw_emad_transmit_retry(trans->core, trans); 691 } 692 693 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 694 struct mlxsw_reg_trans *trans, 695 struct sk_buff *skb) 696 { 697 int err; 698 699 if (!atomic_dec_and_test(&trans->active)) 700 return; 701 702 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 703 if (err == -EAGAIN) { 704 mlxsw_emad_transmit_retry(mlxsw_core, trans); 705 } else { 706 if (err == 0) { 707 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 708 709 if (trans->cb) 710 trans->cb(mlxsw_core, 711 mlxsw_emad_reg_payload(reg_tlv), 712 trans->reg->len, trans->cb_priv); 713 } else { 714 mlxsw_emad_process_string_tlv(skb, trans); 715 } 716 mlxsw_emad_trans_finish(trans, err); 717 } 718 } 719 720 /* called with rcu read lock held */ 721 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u8 local_port, 722 void *priv) 723 { 724 struct mlxsw_core *mlxsw_core = priv; 725 struct mlxsw_reg_trans *trans; 726 727 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 728 skb->data, skb->len); 729 730 mlxsw_emad_tlv_parse(skb); 731 732 if (!mlxsw_emad_is_resp(skb)) 733 goto free_skb; 734 735 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 736 if (mlxsw_emad_get_tid(skb) == trans->tid) { 737 mlxsw_emad_process_response(mlxsw_core, trans, skb); 738 break; 739 } 740 } 741 742 free_skb: 743 dev_kfree_skb(skb); 744 } 745 746 static const struct mlxsw_listener mlxsw_emad_rx_listener = 747 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 748 EMAD, DISCARD); 749 750 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 751 { 752 struct workqueue_struct *emad_wq; 753 u64 tid; 754 int err; 755 756 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 757 return 0; 758 759 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 760 if (!emad_wq) 761 return -ENOMEM; 762 mlxsw_core->emad_wq = emad_wq; 763 764 /* Set the upper 32 bits of the transaction ID field to a random 765 * number. This allows us to discard EMADs addressed to other 766 * devices. 767 */ 768 get_random_bytes(&tid, 4); 769 tid <<= 32; 770 atomic64_set(&mlxsw_core->emad.tid, tid); 771 772 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 773 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 774 775 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 776 mlxsw_core); 777 if (err) 778 goto err_trap_register; 779 780 err = mlxsw_core->driver->basic_trap_groups_set(mlxsw_core); 781 if (err) 782 goto err_emad_trap_set; 783 mlxsw_core->emad.use_emad = true; 784 785 return 0; 786 787 err_emad_trap_set: 788 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 789 mlxsw_core); 790 err_trap_register: 791 destroy_workqueue(mlxsw_core->emad_wq); 792 return err; 793 } 794 795 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 796 { 797 798 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 799 return; 800 801 mlxsw_core->emad.use_emad = false; 802 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 803 mlxsw_core); 804 destroy_workqueue(mlxsw_core->emad_wq); 805 } 806 807 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 808 u16 reg_len, bool enable_string_tlv) 809 { 810 struct sk_buff *skb; 811 u16 emad_len; 812 813 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 814 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 815 sizeof(u32) + mlxsw_core->driver->txhdr_len); 816 if (enable_string_tlv) 817 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 818 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 819 return NULL; 820 821 skb = netdev_alloc_skb(NULL, emad_len); 822 if (!skb) 823 return NULL; 824 memset(skb->data, 0, emad_len); 825 skb_reserve(skb, emad_len); 826 827 return skb; 828 } 829 830 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 831 const struct mlxsw_reg_info *reg, 832 char *payload, 833 enum mlxsw_core_reg_access_type type, 834 struct mlxsw_reg_trans *trans, 835 struct list_head *bulk_list, 836 mlxsw_reg_trans_cb_t *cb, 837 unsigned long cb_priv, u64 tid) 838 { 839 bool enable_string_tlv; 840 struct sk_buff *skb; 841 int err; 842 843 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 844 tid, reg->id, mlxsw_reg_id_str(reg->id), 845 mlxsw_core_reg_access_type_str(type)); 846 847 /* Since this can be changed during emad_reg_access, read it once and 848 * use the value all the way. 849 */ 850 enable_string_tlv = mlxsw_core->emad.enable_string_tlv; 851 852 skb = mlxsw_emad_alloc(mlxsw_core, reg->len, enable_string_tlv); 853 if (!skb) 854 return -ENOMEM; 855 856 list_add_tail(&trans->bulk_list, bulk_list); 857 trans->core = mlxsw_core; 858 trans->tx_skb = skb; 859 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 860 trans->tx_info.is_emad = true; 861 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 862 trans->tid = tid; 863 init_completion(&trans->completion); 864 trans->cb = cb; 865 trans->cb_priv = cb_priv; 866 trans->reg = reg; 867 trans->type = type; 868 869 mlxsw_emad_construct(skb, reg, payload, type, trans->tid, 870 enable_string_tlv); 871 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 872 873 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 874 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 875 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 876 err = mlxsw_emad_transmit(mlxsw_core, trans); 877 if (err) 878 goto err_out; 879 return 0; 880 881 err_out: 882 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 883 list_del_rcu(&trans->list); 884 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 885 list_del(&trans->bulk_list); 886 dev_kfree_skb(trans->tx_skb); 887 return err; 888 } 889 890 /***************** 891 * Core functions 892 *****************/ 893 894 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 895 { 896 spin_lock(&mlxsw_core_driver_list_lock); 897 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 898 spin_unlock(&mlxsw_core_driver_list_lock); 899 return 0; 900 } 901 EXPORT_SYMBOL(mlxsw_core_driver_register); 902 903 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 904 { 905 spin_lock(&mlxsw_core_driver_list_lock); 906 list_del(&mlxsw_driver->list); 907 spin_unlock(&mlxsw_core_driver_list_lock); 908 } 909 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 910 911 static struct mlxsw_driver *__driver_find(const char *kind) 912 { 913 struct mlxsw_driver *mlxsw_driver; 914 915 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 916 if (strcmp(mlxsw_driver->kind, kind) == 0) 917 return mlxsw_driver; 918 } 919 return NULL; 920 } 921 922 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 923 { 924 struct mlxsw_driver *mlxsw_driver; 925 926 spin_lock(&mlxsw_core_driver_list_lock); 927 mlxsw_driver = __driver_find(kind); 928 spin_unlock(&mlxsw_core_driver_list_lock); 929 return mlxsw_driver; 930 } 931 932 struct mlxsw_core_fw_info { 933 struct mlxfw_dev mlxfw_dev; 934 struct mlxsw_core *mlxsw_core; 935 }; 936 937 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 938 u16 component_index, u32 *p_max_size, 939 u8 *p_align_bits, u16 *p_max_write_size) 940 { 941 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 942 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 943 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 944 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 945 int err; 946 947 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 948 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 949 if (err) 950 return err; 951 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 952 953 *p_align_bits = max_t(u8, *p_align_bits, 2); 954 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 955 return 0; 956 } 957 958 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 959 { 960 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 961 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 962 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 963 char mcc_pl[MLXSW_REG_MCC_LEN]; 964 u8 control_state; 965 int err; 966 967 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 968 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 969 if (err) 970 return err; 971 972 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 973 if (control_state != MLXFW_FSM_STATE_IDLE) 974 return -EBUSY; 975 976 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 977 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 978 } 979 980 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 981 u16 component_index, u32 component_size) 982 { 983 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 984 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 985 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 986 char mcc_pl[MLXSW_REG_MCC_LEN]; 987 988 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 989 component_index, fwhandle, component_size); 990 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 991 } 992 993 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 994 u8 *data, u16 size, u32 offset) 995 { 996 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 997 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 998 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 999 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1000 1001 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1002 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1003 } 1004 1005 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1006 u16 component_index) 1007 { 1008 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1009 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1010 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1011 char mcc_pl[MLXSW_REG_MCC_LEN]; 1012 1013 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1014 component_index, fwhandle, 0); 1015 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1016 } 1017 1018 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1019 { 1020 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1021 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1022 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1023 char mcc_pl[MLXSW_REG_MCC_LEN]; 1024 1025 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1026 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1027 } 1028 1029 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1030 enum mlxfw_fsm_state *fsm_state, 1031 enum mlxfw_fsm_state_err *fsm_state_err) 1032 { 1033 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1034 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1035 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1036 char mcc_pl[MLXSW_REG_MCC_LEN]; 1037 u8 control_state; 1038 u8 error_code; 1039 int err; 1040 1041 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1042 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1043 if (err) 1044 return err; 1045 1046 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1047 *fsm_state = control_state; 1048 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1049 return 0; 1050 } 1051 1052 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1053 { 1054 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1055 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1056 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1057 char mcc_pl[MLXSW_REG_MCC_LEN]; 1058 1059 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1060 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1061 } 1062 1063 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1064 { 1065 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1066 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1067 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1068 char mcc_pl[MLXSW_REG_MCC_LEN]; 1069 1070 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1071 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1072 } 1073 1074 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1075 .component_query = mlxsw_core_fw_component_query, 1076 .fsm_lock = mlxsw_core_fw_fsm_lock, 1077 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1078 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1079 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1080 .fsm_activate = mlxsw_core_fw_fsm_activate, 1081 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1082 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1083 .fsm_release = mlxsw_core_fw_fsm_release, 1084 }; 1085 1086 static int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, const struct firmware *firmware, 1087 struct netlink_ext_ack *extack) 1088 { 1089 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1090 .mlxfw_dev = { 1091 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1092 .psid = mlxsw_core->bus_info->psid, 1093 .psid_size = strlen(mlxsw_core->bus_info->psid), 1094 .devlink = priv_to_devlink(mlxsw_core), 1095 }, 1096 .mlxsw_core = mlxsw_core 1097 }; 1098 int err; 1099 1100 mlxsw_core->fw_flash_in_progress = true; 1101 err = mlxfw_firmware_flash(&mlxsw_core_fw_info.mlxfw_dev, firmware, extack); 1102 mlxsw_core->fw_flash_in_progress = false; 1103 1104 return err; 1105 } 1106 1107 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1108 const struct mlxsw_bus_info *mlxsw_bus_info, 1109 const struct mlxsw_fw_rev *req_rev, 1110 const char *filename) 1111 { 1112 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1113 union devlink_param_value value; 1114 const struct firmware *firmware; 1115 int err; 1116 1117 /* Don't check if driver does not require it */ 1118 if (!req_rev || !filename) 1119 return 0; 1120 1121 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1122 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1123 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1124 &value); 1125 if (err) 1126 return err; 1127 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1128 return 0; 1129 1130 /* Validate driver & FW are compatible */ 1131 if (rev->major != req_rev->major) { 1132 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1133 rev->major, req_rev->major); 1134 return -EINVAL; 1135 } 1136 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1137 return 0; 1138 1139 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1140 rev->major, rev->minor, rev->subminor, req_rev->major, 1141 req_rev->minor, req_rev->subminor); 1142 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1143 1144 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1145 if (err) { 1146 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1147 return err; 1148 } 1149 1150 err = mlxsw_core_fw_flash(mlxsw_core, firmware, NULL); 1151 release_firmware(firmware); 1152 if (err) 1153 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1154 1155 /* On FW flash success, tell the caller FW reset is needed 1156 * if current FW supports it. 1157 */ 1158 if (rev->minor >= req_rev->can_reset_minor) 1159 return err ? err : -EAGAIN; 1160 else 1161 return 0; 1162 } 1163 1164 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1165 struct devlink_flash_update_params *params, 1166 struct netlink_ext_ack *extack) 1167 { 1168 return mlxsw_core_fw_flash(mlxsw_core, params->fw, extack); 1169 } 1170 1171 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1172 union devlink_param_value val, 1173 struct netlink_ext_ack *extack) 1174 { 1175 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1176 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1177 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1178 return -EINVAL; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1185 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1186 mlxsw_core_devlink_param_fw_load_policy_validate), 1187 }; 1188 1189 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1190 { 1191 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1192 union devlink_param_value value; 1193 int err; 1194 1195 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1196 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1197 if (err) 1198 return err; 1199 1200 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1201 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1202 return 0; 1203 } 1204 1205 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1206 { 1207 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1208 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1209 } 1210 1211 static int mlxsw_devlink_port_split(struct devlink *devlink, 1212 unsigned int port_index, 1213 unsigned int count, 1214 struct netlink_ext_ack *extack) 1215 { 1216 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1217 1218 if (port_index >= mlxsw_core->max_ports) { 1219 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1220 return -EINVAL; 1221 } 1222 if (!mlxsw_core->driver->port_split) 1223 return -EOPNOTSUPP; 1224 return mlxsw_core->driver->port_split(mlxsw_core, port_index, count, 1225 extack); 1226 } 1227 1228 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1229 unsigned int port_index, 1230 struct netlink_ext_ack *extack) 1231 { 1232 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1233 1234 if (port_index >= mlxsw_core->max_ports) { 1235 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1236 return -EINVAL; 1237 } 1238 if (!mlxsw_core->driver->port_unsplit) 1239 return -EOPNOTSUPP; 1240 return mlxsw_core->driver->port_unsplit(mlxsw_core, port_index, 1241 extack); 1242 } 1243 1244 static int 1245 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1246 unsigned int sb_index, u16 pool_index, 1247 struct devlink_sb_pool_info *pool_info) 1248 { 1249 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1250 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1251 1252 if (!mlxsw_driver->sb_pool_get) 1253 return -EOPNOTSUPP; 1254 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1255 pool_index, pool_info); 1256 } 1257 1258 static int 1259 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1260 unsigned int sb_index, u16 pool_index, u32 size, 1261 enum devlink_sb_threshold_type threshold_type, 1262 struct netlink_ext_ack *extack) 1263 { 1264 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1265 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1266 1267 if (!mlxsw_driver->sb_pool_set) 1268 return -EOPNOTSUPP; 1269 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1270 pool_index, size, threshold_type, 1271 extack); 1272 } 1273 1274 static void *__dl_port(struct devlink_port *devlink_port) 1275 { 1276 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1277 } 1278 1279 static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port, 1280 enum devlink_port_type port_type) 1281 { 1282 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1283 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1284 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1285 1286 if (!mlxsw_driver->port_type_set) 1287 return -EOPNOTSUPP; 1288 1289 return mlxsw_driver->port_type_set(mlxsw_core, 1290 mlxsw_core_port->local_port, 1291 port_type); 1292 } 1293 1294 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1295 unsigned int sb_index, u16 pool_index, 1296 u32 *p_threshold) 1297 { 1298 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1299 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1300 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1301 1302 if (!mlxsw_driver->sb_port_pool_get || 1303 !mlxsw_core_port_check(mlxsw_core_port)) 1304 return -EOPNOTSUPP; 1305 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1306 pool_index, p_threshold); 1307 } 1308 1309 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1310 unsigned int sb_index, u16 pool_index, 1311 u32 threshold, 1312 struct netlink_ext_ack *extack) 1313 { 1314 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1315 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1316 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1317 1318 if (!mlxsw_driver->sb_port_pool_set || 1319 !mlxsw_core_port_check(mlxsw_core_port)) 1320 return -EOPNOTSUPP; 1321 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1322 pool_index, threshold, extack); 1323 } 1324 1325 static int 1326 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1327 unsigned int sb_index, u16 tc_index, 1328 enum devlink_sb_pool_type pool_type, 1329 u16 *p_pool_index, u32 *p_threshold) 1330 { 1331 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1332 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1333 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1334 1335 if (!mlxsw_driver->sb_tc_pool_bind_get || 1336 !mlxsw_core_port_check(mlxsw_core_port)) 1337 return -EOPNOTSUPP; 1338 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1339 tc_index, pool_type, 1340 p_pool_index, p_threshold); 1341 } 1342 1343 static int 1344 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1345 unsigned int sb_index, u16 tc_index, 1346 enum devlink_sb_pool_type pool_type, 1347 u16 pool_index, u32 threshold, 1348 struct netlink_ext_ack *extack) 1349 { 1350 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1351 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1352 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1353 1354 if (!mlxsw_driver->sb_tc_pool_bind_set || 1355 !mlxsw_core_port_check(mlxsw_core_port)) 1356 return -EOPNOTSUPP; 1357 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1358 tc_index, pool_type, 1359 pool_index, threshold, extack); 1360 } 1361 1362 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1363 unsigned int sb_index) 1364 { 1365 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1366 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1367 1368 if (!mlxsw_driver->sb_occ_snapshot) 1369 return -EOPNOTSUPP; 1370 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1371 } 1372 1373 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1374 unsigned int sb_index) 1375 { 1376 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1377 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1378 1379 if (!mlxsw_driver->sb_occ_max_clear) 1380 return -EOPNOTSUPP; 1381 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1382 } 1383 1384 static int 1385 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1386 unsigned int sb_index, u16 pool_index, 1387 u32 *p_cur, u32 *p_max) 1388 { 1389 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1390 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1391 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1392 1393 if (!mlxsw_driver->sb_occ_port_pool_get || 1394 !mlxsw_core_port_check(mlxsw_core_port)) 1395 return -EOPNOTSUPP; 1396 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1397 pool_index, p_cur, p_max); 1398 } 1399 1400 static int 1401 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1402 unsigned int sb_index, u16 tc_index, 1403 enum devlink_sb_pool_type pool_type, 1404 u32 *p_cur, u32 *p_max) 1405 { 1406 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1407 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1408 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1409 1410 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1411 !mlxsw_core_port_check(mlxsw_core_port)) 1412 return -EOPNOTSUPP; 1413 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1414 sb_index, tc_index, 1415 pool_type, p_cur, p_max); 1416 } 1417 1418 static int 1419 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1420 struct netlink_ext_ack *extack) 1421 { 1422 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1423 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1424 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1425 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1426 char buf[32]; 1427 int err; 1428 1429 err = devlink_info_driver_name_put(req, 1430 mlxsw_core->bus_info->device_kind); 1431 if (err) 1432 return err; 1433 1434 mlxsw_reg_mgir_pack(mgir_pl); 1435 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1436 if (err) 1437 return err; 1438 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1439 &fw_minor, &fw_sub_minor); 1440 1441 sprintf(buf, "%X", hw_rev); 1442 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1443 if (err) 1444 return err; 1445 1446 err = devlink_info_version_fixed_put(req, 1447 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1448 fw_info_psid); 1449 if (err) 1450 return err; 1451 1452 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1453 err = devlink_info_version_running_put(req, "fw.version", buf); 1454 if (err) 1455 return err; 1456 1457 return devlink_info_version_running_put(req, 1458 DEVLINK_INFO_VERSION_GENERIC_FW, 1459 buf); 1460 } 1461 1462 static int 1463 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1464 bool netns_change, enum devlink_reload_action action, 1465 enum devlink_reload_limit limit, 1466 struct netlink_ext_ack *extack) 1467 { 1468 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1469 1470 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1471 return -EOPNOTSUPP; 1472 1473 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1474 return 0; 1475 } 1476 1477 static int 1478 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1479 enum devlink_reload_limit limit, u32 *actions_performed, 1480 struct netlink_ext_ack *extack) 1481 { 1482 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1483 1484 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1485 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1486 return mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1487 mlxsw_core->bus, 1488 mlxsw_core->bus_priv, true, 1489 devlink, extack); 1490 } 1491 1492 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1493 struct devlink_flash_update_params *params, 1494 struct netlink_ext_ack *extack) 1495 { 1496 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1497 1498 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1499 } 1500 1501 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1502 const struct devlink_trap *trap, 1503 void *trap_ctx) 1504 { 1505 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1506 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1507 1508 if (!mlxsw_driver->trap_init) 1509 return -EOPNOTSUPP; 1510 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1511 } 1512 1513 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1514 const struct devlink_trap *trap, 1515 void *trap_ctx) 1516 { 1517 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1518 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1519 1520 if (!mlxsw_driver->trap_fini) 1521 return; 1522 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1523 } 1524 1525 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1526 const struct devlink_trap *trap, 1527 enum devlink_trap_action action, 1528 struct netlink_ext_ack *extack) 1529 { 1530 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1531 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1532 1533 if (!mlxsw_driver->trap_action_set) 1534 return -EOPNOTSUPP; 1535 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1536 } 1537 1538 static int 1539 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1540 const struct devlink_trap_group *group) 1541 { 1542 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1543 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1544 1545 if (!mlxsw_driver->trap_group_init) 1546 return -EOPNOTSUPP; 1547 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1548 } 1549 1550 static int 1551 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1552 const struct devlink_trap_group *group, 1553 const struct devlink_trap_policer *policer, 1554 struct netlink_ext_ack *extack) 1555 { 1556 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1557 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1558 1559 if (!mlxsw_driver->trap_group_set) 1560 return -EOPNOTSUPP; 1561 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1562 } 1563 1564 static int 1565 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1566 const struct devlink_trap_policer *policer) 1567 { 1568 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1569 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1570 1571 if (!mlxsw_driver->trap_policer_init) 1572 return -EOPNOTSUPP; 1573 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1574 } 1575 1576 static void 1577 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1578 const struct devlink_trap_policer *policer) 1579 { 1580 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1581 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1582 1583 if (!mlxsw_driver->trap_policer_fini) 1584 return; 1585 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1586 } 1587 1588 static int 1589 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1590 const struct devlink_trap_policer *policer, 1591 u64 rate, u64 burst, 1592 struct netlink_ext_ack *extack) 1593 { 1594 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1595 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1596 1597 if (!mlxsw_driver->trap_policer_set) 1598 return -EOPNOTSUPP; 1599 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1600 extack); 1601 } 1602 1603 static int 1604 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1605 const struct devlink_trap_policer *policer, 1606 u64 *p_drops) 1607 { 1608 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1609 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1610 1611 if (!mlxsw_driver->trap_policer_counter_get) 1612 return -EOPNOTSUPP; 1613 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1614 p_drops); 1615 } 1616 1617 static const struct devlink_ops mlxsw_devlink_ops = { 1618 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1619 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1620 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1621 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1622 .port_type_set = mlxsw_devlink_port_type_set, 1623 .port_split = mlxsw_devlink_port_split, 1624 .port_unsplit = mlxsw_devlink_port_unsplit, 1625 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1626 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1627 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1628 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1629 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1630 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1631 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1632 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1633 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1634 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1635 .info_get = mlxsw_devlink_info_get, 1636 .flash_update = mlxsw_devlink_flash_update, 1637 .trap_init = mlxsw_devlink_trap_init, 1638 .trap_fini = mlxsw_devlink_trap_fini, 1639 .trap_action_set = mlxsw_devlink_trap_action_set, 1640 .trap_group_init = mlxsw_devlink_trap_group_init, 1641 .trap_group_set = mlxsw_devlink_trap_group_set, 1642 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1643 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1644 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1645 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1646 }; 1647 1648 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1649 { 1650 int err; 1651 1652 err = mlxsw_core_fw_params_register(mlxsw_core); 1653 if (err) 1654 return err; 1655 1656 if (mlxsw_core->driver->params_register) { 1657 err = mlxsw_core->driver->params_register(mlxsw_core); 1658 if (err) 1659 goto err_params_register; 1660 } 1661 return 0; 1662 1663 err_params_register: 1664 mlxsw_core_fw_params_unregister(mlxsw_core); 1665 return err; 1666 } 1667 1668 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1669 { 1670 mlxsw_core_fw_params_unregister(mlxsw_core); 1671 if (mlxsw_core->driver->params_register) 1672 mlxsw_core->driver->params_unregister(mlxsw_core); 1673 } 1674 1675 struct mlxsw_core_health_event { 1676 struct mlxsw_core *mlxsw_core; 1677 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1678 struct work_struct work; 1679 }; 1680 1681 static void mlxsw_core_health_event_work(struct work_struct *work) 1682 { 1683 struct mlxsw_core_health_event *event; 1684 struct mlxsw_core *mlxsw_core; 1685 1686 event = container_of(work, struct mlxsw_core_health_event, work); 1687 mlxsw_core = event->mlxsw_core; 1688 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1689 event->mfde_pl); 1690 kfree(event); 1691 } 1692 1693 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1694 char *mfde_pl, void *priv) 1695 { 1696 struct mlxsw_core_health_event *event; 1697 struct mlxsw_core *mlxsw_core = priv; 1698 1699 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1700 if (!event) 1701 return; 1702 event->mlxsw_core = mlxsw_core; 1703 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1704 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1705 mlxsw_core_schedule_work(&event->work); 1706 } 1707 1708 static const struct mlxsw_listener mlxsw_core_health_listener = 1709 MLXSW_EVENTL(mlxsw_core_health_listener_func, MFDE, MFDE); 1710 1711 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1712 struct devlink_fmsg *fmsg, void *priv_ctx, 1713 struct netlink_ext_ack *extack) 1714 { 1715 char *mfde_pl = priv_ctx; 1716 char *val_str; 1717 u8 event_id; 1718 u32 val; 1719 int err; 1720 1721 if (!priv_ctx) 1722 /* User-triggered dumps are not possible */ 1723 return -EOPNOTSUPP; 1724 1725 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1726 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1727 if (err) 1728 return err; 1729 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1730 if (err) 1731 return err; 1732 1733 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1734 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1735 if (err) 1736 return err; 1737 switch (event_id) { 1738 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1739 val_str = "CR space timeout"; 1740 break; 1741 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1742 val_str = "KVD insertion machine stopped"; 1743 break; 1744 default: 1745 val_str = NULL; 1746 } 1747 if (val_str) { 1748 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1749 if (err) 1750 return err; 1751 } 1752 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1753 if (err) 1754 return err; 1755 1756 val = mlxsw_reg_mfde_method_get(mfde_pl); 1757 switch (val) { 1758 case MLXSW_REG_MFDE_METHOD_QUERY: 1759 val_str = "query"; 1760 break; 1761 case MLXSW_REG_MFDE_METHOD_WRITE: 1762 val_str = "write"; 1763 break; 1764 default: 1765 val_str = NULL; 1766 } 1767 if (val_str) { 1768 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 1769 if (err) 1770 return err; 1771 } 1772 1773 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 1774 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 1775 if (err) 1776 return err; 1777 1778 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 1779 switch (val) { 1780 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 1781 val_str = "mad"; 1782 break; 1783 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 1784 val_str = "emad"; 1785 break; 1786 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 1787 val_str = "cmdif"; 1788 break; 1789 default: 1790 val_str = NULL; 1791 } 1792 if (val_str) { 1793 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 1794 if (err) 1795 return err; 1796 } 1797 1798 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 1799 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 1800 if (err) 1801 return err; 1802 1803 if (event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO) { 1804 val = mlxsw_reg_mfde_log_address_get(mfde_pl); 1805 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1806 if (err) 1807 return err; 1808 val = mlxsw_reg_mfde_log_id_get(mfde_pl); 1809 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1810 if (err) 1811 return err; 1812 val = mlxsw_reg_mfde_log_ip_get(mfde_pl); 1813 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1814 if (err) 1815 return err; 1816 } else if (event_id == MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP) { 1817 val = mlxsw_reg_mfde_pipes_mask_get(mfde_pl); 1818 err = devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1819 if (err) 1820 return err; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int 1827 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 1828 struct netlink_ext_ack *extack) 1829 { 1830 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 1831 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 1832 int err; 1833 1834 /* Read the register first to make sure no other bits are changed. */ 1835 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1836 if (err) 1837 return err; 1838 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 1839 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1840 } 1841 1842 static const struct devlink_health_reporter_ops 1843 mlxsw_core_health_fw_fatal_ops = { 1844 .name = "fw_fatal", 1845 .dump = mlxsw_core_health_fw_fatal_dump, 1846 .test = mlxsw_core_health_fw_fatal_test, 1847 }; 1848 1849 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 1850 bool enable) 1851 { 1852 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 1853 int err; 1854 1855 /* Read the register first to make sure no other bits are changed. */ 1856 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1857 if (err) 1858 return err; 1859 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 1860 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1861 } 1862 1863 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 1864 { 1865 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1866 struct devlink_health_reporter *fw_fatal; 1867 int err; 1868 1869 if (!mlxsw_core->driver->fw_fatal_enabled) 1870 return 0; 1871 1872 fw_fatal = devlink_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 1873 0, mlxsw_core); 1874 if (IS_ERR(fw_fatal)) { 1875 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 1876 return PTR_ERR(fw_fatal); 1877 } 1878 mlxsw_core->health.fw_fatal = fw_fatal; 1879 1880 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 1881 if (err) 1882 goto err_trap_register; 1883 1884 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 1885 if (err) 1886 goto err_fw_fatal_config; 1887 1888 return 0; 1889 1890 err_fw_fatal_config: 1891 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 1892 err_trap_register: 1893 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 1894 return err; 1895 } 1896 1897 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 1898 { 1899 if (!mlxsw_core->driver->fw_fatal_enabled) 1900 return; 1901 1902 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 1903 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 1904 /* Make sure there is no more event work scheduled */ 1905 mlxsw_core_flush_owq(); 1906 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 1907 } 1908 1909 static int 1910 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 1911 const struct mlxsw_bus *mlxsw_bus, 1912 void *bus_priv, bool reload, 1913 struct devlink *devlink, 1914 struct netlink_ext_ack *extack) 1915 { 1916 const char *device_kind = mlxsw_bus_info->device_kind; 1917 struct mlxsw_core *mlxsw_core; 1918 struct mlxsw_driver *mlxsw_driver; 1919 struct mlxsw_res *res; 1920 size_t alloc_size; 1921 int err; 1922 1923 mlxsw_driver = mlxsw_core_driver_get(device_kind); 1924 if (!mlxsw_driver) 1925 return -EINVAL; 1926 1927 if (!reload) { 1928 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 1929 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 1930 mlxsw_bus_info->dev); 1931 if (!devlink) { 1932 err = -ENOMEM; 1933 goto err_devlink_alloc; 1934 } 1935 } 1936 1937 mlxsw_core = devlink_priv(devlink); 1938 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 1939 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 1940 mlxsw_core->driver = mlxsw_driver; 1941 mlxsw_core->bus = mlxsw_bus; 1942 mlxsw_core->bus_priv = bus_priv; 1943 mlxsw_core->bus_info = mlxsw_bus_info; 1944 1945 res = mlxsw_driver->res_query_enabled ? &mlxsw_core->res : NULL; 1946 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, res); 1947 if (err) 1948 goto err_bus_init; 1949 1950 if (mlxsw_driver->resources_register && !reload) { 1951 err = mlxsw_driver->resources_register(mlxsw_core); 1952 if (err) 1953 goto err_register_resources; 1954 } 1955 1956 err = mlxsw_ports_init(mlxsw_core, reload); 1957 if (err) 1958 goto err_ports_init; 1959 1960 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) && 1961 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 1962 alloc_size = sizeof(u8) * 1963 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * 1964 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 1965 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 1966 if (!mlxsw_core->lag.mapping) { 1967 err = -ENOMEM; 1968 goto err_alloc_lag_mapping; 1969 } 1970 } 1971 1972 err = mlxsw_emad_init(mlxsw_core); 1973 if (err) 1974 goto err_emad_init; 1975 1976 if (!reload) { 1977 err = mlxsw_core_params_register(mlxsw_core); 1978 if (err) 1979 goto err_register_params; 1980 } 1981 1982 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 1983 mlxsw_driver->fw_filename); 1984 if (err) 1985 goto err_fw_rev_validate; 1986 1987 err = mlxsw_core_health_init(mlxsw_core); 1988 if (err) 1989 goto err_health_init; 1990 1991 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 1992 if (err) 1993 goto err_hwmon_init; 1994 1995 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 1996 &mlxsw_core->thermal); 1997 if (err) 1998 goto err_thermal_init; 1999 2000 err = mlxsw_env_init(mlxsw_core, &mlxsw_core->env); 2001 if (err) 2002 goto err_env_init; 2003 2004 if (mlxsw_driver->init) { 2005 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2006 if (err) 2007 goto err_driver_init; 2008 } 2009 2010 if (!reload) { 2011 devlink_register(devlink); 2012 devlink_reload_enable(devlink); 2013 } 2014 2015 return 0; 2016 2017 err_driver_init: 2018 mlxsw_env_fini(mlxsw_core->env); 2019 err_env_init: 2020 mlxsw_thermal_fini(mlxsw_core->thermal); 2021 err_thermal_init: 2022 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2023 err_hwmon_init: 2024 mlxsw_core_health_fini(mlxsw_core); 2025 err_health_init: 2026 err_fw_rev_validate: 2027 if (!reload) 2028 mlxsw_core_params_unregister(mlxsw_core); 2029 err_register_params: 2030 mlxsw_emad_fini(mlxsw_core); 2031 err_emad_init: 2032 kfree(mlxsw_core->lag.mapping); 2033 err_alloc_lag_mapping: 2034 mlxsw_ports_fini(mlxsw_core, reload); 2035 err_ports_init: 2036 if (!reload) 2037 devlink_resources_unregister(devlink, NULL); 2038 err_register_resources: 2039 mlxsw_bus->fini(bus_priv); 2040 err_bus_init: 2041 if (!reload) 2042 devlink_free(devlink); 2043 err_devlink_alloc: 2044 return err; 2045 } 2046 2047 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2048 const struct mlxsw_bus *mlxsw_bus, 2049 void *bus_priv, bool reload, 2050 struct devlink *devlink, 2051 struct netlink_ext_ack *extack) 2052 { 2053 bool called_again = false; 2054 int err; 2055 2056 again: 2057 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2058 bus_priv, reload, 2059 devlink, extack); 2060 /* -EAGAIN is returned in case the FW was updated. FW needs 2061 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2062 * again. 2063 */ 2064 if (err == -EAGAIN && !called_again) { 2065 called_again = true; 2066 goto again; 2067 } 2068 2069 return err; 2070 } 2071 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2072 2073 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2074 bool reload) 2075 { 2076 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2077 2078 if (!reload) { 2079 devlink_reload_disable(devlink); 2080 devlink_unregister(devlink); 2081 } 2082 if (devlink_is_reload_failed(devlink)) { 2083 if (!reload) 2084 /* Only the parts that were not de-initialized in the 2085 * failed reload attempt need to be de-initialized. 2086 */ 2087 goto reload_fail_deinit; 2088 else 2089 return; 2090 } 2091 2092 if (mlxsw_core->driver->fini) 2093 mlxsw_core->driver->fini(mlxsw_core); 2094 mlxsw_env_fini(mlxsw_core->env); 2095 mlxsw_thermal_fini(mlxsw_core->thermal); 2096 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2097 mlxsw_core_health_fini(mlxsw_core); 2098 if (!reload) 2099 mlxsw_core_params_unregister(mlxsw_core); 2100 mlxsw_emad_fini(mlxsw_core); 2101 kfree(mlxsw_core->lag.mapping); 2102 mlxsw_ports_fini(mlxsw_core, reload); 2103 if (!reload) 2104 devlink_resources_unregister(devlink, NULL); 2105 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2106 if (!reload) 2107 devlink_free(devlink); 2108 2109 return; 2110 2111 reload_fail_deinit: 2112 mlxsw_core_params_unregister(mlxsw_core); 2113 devlink_resources_unregister(devlink, NULL); 2114 devlink_free(devlink); 2115 } 2116 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2117 2118 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2119 const struct mlxsw_tx_info *tx_info) 2120 { 2121 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2122 tx_info); 2123 } 2124 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2125 2126 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2127 const struct mlxsw_tx_info *tx_info) 2128 { 2129 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2130 tx_info); 2131 } 2132 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2133 2134 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2135 struct sk_buff *skb, u8 local_port) 2136 { 2137 if (mlxsw_core->driver->ptp_transmitted) 2138 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2139 local_port); 2140 } 2141 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2142 2143 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2144 const struct mlxsw_rx_listener *rxl_b) 2145 { 2146 return (rxl_a->func == rxl_b->func && 2147 rxl_a->local_port == rxl_b->local_port && 2148 rxl_a->trap_id == rxl_b->trap_id && 2149 rxl_a->mirror_reason == rxl_b->mirror_reason); 2150 } 2151 2152 static struct mlxsw_rx_listener_item * 2153 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2154 const struct mlxsw_rx_listener *rxl) 2155 { 2156 struct mlxsw_rx_listener_item *rxl_item; 2157 2158 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2159 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2160 return rxl_item; 2161 } 2162 return NULL; 2163 } 2164 2165 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2166 const struct mlxsw_rx_listener *rxl, 2167 void *priv, bool enabled) 2168 { 2169 struct mlxsw_rx_listener_item *rxl_item; 2170 2171 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2172 if (rxl_item) 2173 return -EEXIST; 2174 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2175 if (!rxl_item) 2176 return -ENOMEM; 2177 rxl_item->rxl = *rxl; 2178 rxl_item->priv = priv; 2179 rxl_item->enabled = enabled; 2180 2181 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2182 return 0; 2183 } 2184 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2185 2186 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2187 const struct mlxsw_rx_listener *rxl) 2188 { 2189 struct mlxsw_rx_listener_item *rxl_item; 2190 2191 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2192 if (!rxl_item) 2193 return; 2194 list_del_rcu(&rxl_item->list); 2195 synchronize_rcu(); 2196 kfree(rxl_item); 2197 } 2198 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2199 2200 static void 2201 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2202 const struct mlxsw_rx_listener *rxl, 2203 bool enabled) 2204 { 2205 struct mlxsw_rx_listener_item *rxl_item; 2206 2207 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2208 if (WARN_ON(!rxl_item)) 2209 return; 2210 rxl_item->enabled = enabled; 2211 } 2212 2213 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u8 local_port, 2214 void *priv) 2215 { 2216 struct mlxsw_event_listener_item *event_listener_item = priv; 2217 struct mlxsw_core *mlxsw_core; 2218 struct mlxsw_reg_info reg; 2219 char *payload; 2220 char *reg_tlv; 2221 char *op_tlv; 2222 2223 mlxsw_core = event_listener_item->mlxsw_core; 2224 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2225 skb->data, skb->len); 2226 2227 mlxsw_emad_tlv_parse(skb); 2228 op_tlv = mlxsw_emad_op_tlv(skb); 2229 reg_tlv = mlxsw_emad_reg_tlv(skb); 2230 2231 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2232 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2233 payload = mlxsw_emad_reg_payload(reg_tlv); 2234 event_listener_item->el.func(®, payload, event_listener_item->priv); 2235 dev_kfree_skb(skb); 2236 } 2237 2238 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2239 const struct mlxsw_event_listener *el_b) 2240 { 2241 return (el_a->func == el_b->func && 2242 el_a->trap_id == el_b->trap_id); 2243 } 2244 2245 static struct mlxsw_event_listener_item * 2246 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2247 const struct mlxsw_event_listener *el) 2248 { 2249 struct mlxsw_event_listener_item *el_item; 2250 2251 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2252 if (__is_event_listener_equal(&el_item->el, el)) 2253 return el_item; 2254 } 2255 return NULL; 2256 } 2257 2258 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2259 const struct mlxsw_event_listener *el, 2260 void *priv) 2261 { 2262 int err; 2263 struct mlxsw_event_listener_item *el_item; 2264 const struct mlxsw_rx_listener rxl = { 2265 .func = mlxsw_core_event_listener_func, 2266 .local_port = MLXSW_PORT_DONT_CARE, 2267 .trap_id = el->trap_id, 2268 }; 2269 2270 el_item = __find_event_listener_item(mlxsw_core, el); 2271 if (el_item) 2272 return -EEXIST; 2273 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2274 if (!el_item) 2275 return -ENOMEM; 2276 el_item->mlxsw_core = mlxsw_core; 2277 el_item->el = *el; 2278 el_item->priv = priv; 2279 2280 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2281 if (err) 2282 goto err_rx_listener_register; 2283 2284 /* No reason to save item if we did not manage to register an RX 2285 * listener for it. 2286 */ 2287 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2288 2289 return 0; 2290 2291 err_rx_listener_register: 2292 kfree(el_item); 2293 return err; 2294 } 2295 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2296 2297 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2298 const struct mlxsw_event_listener *el) 2299 { 2300 struct mlxsw_event_listener_item *el_item; 2301 const struct mlxsw_rx_listener rxl = { 2302 .func = mlxsw_core_event_listener_func, 2303 .local_port = MLXSW_PORT_DONT_CARE, 2304 .trap_id = el->trap_id, 2305 }; 2306 2307 el_item = __find_event_listener_item(mlxsw_core, el); 2308 if (!el_item) 2309 return; 2310 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2311 list_del(&el_item->list); 2312 kfree(el_item); 2313 } 2314 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2315 2316 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2317 const struct mlxsw_listener *listener, 2318 void *priv, bool enabled) 2319 { 2320 if (listener->is_event) { 2321 WARN_ON(!enabled); 2322 return mlxsw_core_event_listener_register(mlxsw_core, 2323 &listener->event_listener, 2324 priv); 2325 } else { 2326 return mlxsw_core_rx_listener_register(mlxsw_core, 2327 &listener->rx_listener, 2328 priv, enabled); 2329 } 2330 } 2331 2332 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2333 const struct mlxsw_listener *listener, 2334 void *priv) 2335 { 2336 if (listener->is_event) 2337 mlxsw_core_event_listener_unregister(mlxsw_core, 2338 &listener->event_listener); 2339 else 2340 mlxsw_core_rx_listener_unregister(mlxsw_core, 2341 &listener->rx_listener); 2342 } 2343 2344 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2345 const struct mlxsw_listener *listener, void *priv) 2346 { 2347 enum mlxsw_reg_htgt_trap_group trap_group; 2348 enum mlxsw_reg_hpkt_action action; 2349 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2350 int err; 2351 2352 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2353 listener->enabled_on_register); 2354 if (err) 2355 return err; 2356 2357 action = listener->enabled_on_register ? listener->en_action : 2358 listener->dis_action; 2359 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2360 listener->dis_trap_group; 2361 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2362 trap_group, listener->is_ctrl); 2363 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2364 if (err) 2365 goto err_trap_set; 2366 2367 return 0; 2368 2369 err_trap_set: 2370 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2371 return err; 2372 } 2373 EXPORT_SYMBOL(mlxsw_core_trap_register); 2374 2375 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2376 const struct mlxsw_listener *listener, 2377 void *priv) 2378 { 2379 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2380 2381 if (!listener->is_event) { 2382 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2383 listener->trap_id, listener->dis_trap_group, 2384 listener->is_ctrl); 2385 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2386 } 2387 2388 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2389 } 2390 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2391 2392 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2393 const struct mlxsw_listener *listener, 2394 bool enabled) 2395 { 2396 enum mlxsw_reg_htgt_trap_group trap_group; 2397 enum mlxsw_reg_hpkt_action action; 2398 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2399 int err; 2400 2401 /* Not supported for event listener */ 2402 if (WARN_ON(listener->is_event)) 2403 return -EINVAL; 2404 2405 action = enabled ? listener->en_action : listener->dis_action; 2406 trap_group = enabled ? listener->en_trap_group : 2407 listener->dis_trap_group; 2408 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2409 trap_group, listener->is_ctrl); 2410 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2411 if (err) 2412 return err; 2413 2414 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2415 enabled); 2416 return 0; 2417 } 2418 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2419 2420 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2421 { 2422 return atomic64_inc_return(&mlxsw_core->emad.tid); 2423 } 2424 2425 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2426 const struct mlxsw_reg_info *reg, 2427 char *payload, 2428 enum mlxsw_core_reg_access_type type, 2429 struct list_head *bulk_list, 2430 mlxsw_reg_trans_cb_t *cb, 2431 unsigned long cb_priv) 2432 { 2433 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2434 struct mlxsw_reg_trans *trans; 2435 int err; 2436 2437 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2438 if (!trans) 2439 return -ENOMEM; 2440 2441 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2442 bulk_list, cb, cb_priv, tid); 2443 if (err) { 2444 kfree_rcu(trans, rcu); 2445 return err; 2446 } 2447 return 0; 2448 } 2449 2450 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2451 const struct mlxsw_reg_info *reg, char *payload, 2452 struct list_head *bulk_list, 2453 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2454 { 2455 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2456 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2457 bulk_list, cb, cb_priv); 2458 } 2459 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2460 2461 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2462 const struct mlxsw_reg_info *reg, char *payload, 2463 struct list_head *bulk_list, 2464 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2465 { 2466 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2467 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2468 bulk_list, cb, cb_priv); 2469 } 2470 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2471 2472 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2473 2474 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2475 { 2476 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2477 struct mlxsw_core *mlxsw_core = trans->core; 2478 int err; 2479 2480 wait_for_completion(&trans->completion); 2481 cancel_delayed_work_sync(&trans->timeout_dw); 2482 err = trans->err; 2483 2484 if (trans->retries) 2485 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2486 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2487 if (err) { 2488 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2489 trans->tid, trans->reg->id, 2490 mlxsw_reg_id_str(trans->reg->id), 2491 mlxsw_core_reg_access_type_str(trans->type), 2492 trans->emad_status, 2493 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2494 2495 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2496 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2497 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2498 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2499 trans->emad_err_string ? trans->emad_err_string : ""); 2500 2501 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2502 trans->emad_status, err_string); 2503 2504 kfree(trans->emad_err_string); 2505 } 2506 2507 list_del(&trans->bulk_list); 2508 kfree_rcu(trans, rcu); 2509 return err; 2510 } 2511 2512 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2513 { 2514 struct mlxsw_reg_trans *trans; 2515 struct mlxsw_reg_trans *tmp; 2516 int sum_err = 0; 2517 int err; 2518 2519 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2520 err = mlxsw_reg_trans_wait(trans); 2521 if (err && sum_err == 0) 2522 sum_err = err; /* first error to be returned */ 2523 } 2524 return sum_err; 2525 } 2526 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2527 2528 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2529 const struct mlxsw_reg_info *reg, 2530 char *payload, 2531 enum mlxsw_core_reg_access_type type) 2532 { 2533 enum mlxsw_emad_op_tlv_status status; 2534 int err, n_retry; 2535 bool reset_ok; 2536 char *in_mbox, *out_mbox, *tmp; 2537 2538 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2539 reg->id, mlxsw_reg_id_str(reg->id), 2540 mlxsw_core_reg_access_type_str(type)); 2541 2542 in_mbox = mlxsw_cmd_mbox_alloc(); 2543 if (!in_mbox) 2544 return -ENOMEM; 2545 2546 out_mbox = mlxsw_cmd_mbox_alloc(); 2547 if (!out_mbox) { 2548 err = -ENOMEM; 2549 goto free_in_mbox; 2550 } 2551 2552 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2553 mlxsw_core_tid_get(mlxsw_core)); 2554 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2555 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2556 2557 /* There is a special treatment needed for MRSR (reset) register. 2558 * The command interface will return error after the command 2559 * is executed, so tell the lower layer to expect it 2560 * and cope accordingly. 2561 */ 2562 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2563 2564 n_retry = 0; 2565 retry: 2566 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2567 if (!err) { 2568 err = mlxsw_emad_process_status(out_mbox, &status); 2569 if (err) { 2570 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2571 goto retry; 2572 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2573 status, mlxsw_emad_op_tlv_status_str(status)); 2574 } 2575 } 2576 2577 if (!err) 2578 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2579 reg->len); 2580 2581 mlxsw_cmd_mbox_free(out_mbox); 2582 free_in_mbox: 2583 mlxsw_cmd_mbox_free(in_mbox); 2584 if (err) 2585 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2586 reg->id, mlxsw_reg_id_str(reg->id), 2587 mlxsw_core_reg_access_type_str(type)); 2588 return err; 2589 } 2590 2591 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2592 char *payload, size_t payload_len, 2593 unsigned long cb_priv) 2594 { 2595 char *orig_payload = (char *) cb_priv; 2596 2597 memcpy(orig_payload, payload, payload_len); 2598 } 2599 2600 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2601 const struct mlxsw_reg_info *reg, 2602 char *payload, 2603 enum mlxsw_core_reg_access_type type) 2604 { 2605 LIST_HEAD(bulk_list); 2606 int err; 2607 2608 /* During initialization EMAD interface is not available to us, 2609 * so we default to command interface. We switch to EMAD interface 2610 * after setting the appropriate traps. 2611 */ 2612 if (!mlxsw_core->emad.use_emad) 2613 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2614 payload, type); 2615 2616 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 2617 payload, type, &bulk_list, 2618 mlxsw_core_reg_access_cb, 2619 (unsigned long) payload); 2620 if (err) 2621 return err; 2622 return mlxsw_reg_trans_bulk_wait(&bulk_list); 2623 } 2624 2625 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 2626 const struct mlxsw_reg_info *reg, char *payload) 2627 { 2628 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2629 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 2630 } 2631 EXPORT_SYMBOL(mlxsw_reg_query); 2632 2633 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 2634 const struct mlxsw_reg_info *reg, char *payload) 2635 { 2636 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2637 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 2638 } 2639 EXPORT_SYMBOL(mlxsw_reg_write); 2640 2641 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2642 struct mlxsw_rx_info *rx_info) 2643 { 2644 struct mlxsw_rx_listener_item *rxl_item; 2645 const struct mlxsw_rx_listener *rxl; 2646 u8 local_port; 2647 bool found = false; 2648 2649 if (rx_info->is_lag) { 2650 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 2651 __func__, rx_info->u.lag_id, 2652 rx_info->trap_id); 2653 /* Upper layer does not care if the skb came from LAG or not, 2654 * so just get the local_port for the lag port and push it up. 2655 */ 2656 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 2657 rx_info->u.lag_id, 2658 rx_info->lag_port_index); 2659 } else { 2660 local_port = rx_info->u.sys_port; 2661 } 2662 2663 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 2664 __func__, local_port, rx_info->trap_id); 2665 2666 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 2667 (local_port >= mlxsw_core->max_ports)) 2668 goto drop; 2669 2670 rcu_read_lock(); 2671 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 2672 rxl = &rxl_item->rxl; 2673 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 2674 rxl->local_port == local_port) && 2675 rxl->trap_id == rx_info->trap_id && 2676 rxl->mirror_reason == rx_info->mirror_reason) { 2677 if (rxl_item->enabled) 2678 found = true; 2679 break; 2680 } 2681 } 2682 if (!found) { 2683 rcu_read_unlock(); 2684 goto drop; 2685 } 2686 2687 rxl->func(skb, local_port, rxl_item->priv); 2688 rcu_read_unlock(); 2689 return; 2690 2691 drop: 2692 dev_kfree_skb(skb); 2693 } 2694 EXPORT_SYMBOL(mlxsw_core_skb_receive); 2695 2696 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 2697 u16 lag_id, u8 port_index) 2698 { 2699 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 2700 port_index; 2701 } 2702 2703 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 2704 u16 lag_id, u8 port_index, u8 local_port) 2705 { 2706 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2707 lag_id, port_index); 2708 2709 mlxsw_core->lag.mapping[index] = local_port; 2710 } 2711 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 2712 2713 u8 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 2714 u16 lag_id, u8 port_index) 2715 { 2716 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2717 lag_id, port_index); 2718 2719 return mlxsw_core->lag.mapping[index]; 2720 } 2721 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 2722 2723 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 2724 u16 lag_id, u8 local_port) 2725 { 2726 int i; 2727 2728 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 2729 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2730 lag_id, i); 2731 2732 if (mlxsw_core->lag.mapping[index] == local_port) 2733 mlxsw_core->lag.mapping[index] = 0; 2734 } 2735 } 2736 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 2737 2738 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 2739 enum mlxsw_res_id res_id) 2740 { 2741 return mlxsw_res_valid(&mlxsw_core->res, res_id); 2742 } 2743 EXPORT_SYMBOL(mlxsw_core_res_valid); 2744 2745 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 2746 enum mlxsw_res_id res_id) 2747 { 2748 return mlxsw_res_get(&mlxsw_core->res, res_id); 2749 } 2750 EXPORT_SYMBOL(mlxsw_core_res_get); 2751 2752 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u8 local_port, 2753 enum devlink_port_flavour flavour, 2754 u32 port_number, bool split, 2755 u32 split_port_subnumber, 2756 bool splittable, u32 lanes, 2757 const unsigned char *switch_id, 2758 unsigned char switch_id_len) 2759 { 2760 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2761 struct mlxsw_core_port *mlxsw_core_port = 2762 &mlxsw_core->ports[local_port]; 2763 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2764 struct devlink_port_attrs attrs = {}; 2765 int err; 2766 2767 attrs.split = split; 2768 attrs.lanes = lanes; 2769 attrs.splittable = splittable; 2770 attrs.flavour = flavour; 2771 attrs.phys.port_number = port_number; 2772 attrs.phys.split_subport_number = split_port_subnumber; 2773 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 2774 attrs.switch_id.id_len = switch_id_len; 2775 mlxsw_core_port->local_port = local_port; 2776 devlink_port_attrs_set(devlink_port, &attrs); 2777 err = devlink_port_register(devlink, devlink_port, local_port); 2778 if (err) 2779 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2780 return err; 2781 } 2782 2783 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u8 local_port) 2784 { 2785 struct mlxsw_core_port *mlxsw_core_port = 2786 &mlxsw_core->ports[local_port]; 2787 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2788 2789 devlink_port_unregister(devlink_port); 2790 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2791 } 2792 2793 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u8 local_port, 2794 u32 port_number, bool split, 2795 u32 split_port_subnumber, 2796 bool splittable, u32 lanes, 2797 const unsigned char *switch_id, 2798 unsigned char switch_id_len) 2799 { 2800 int err; 2801 2802 err = __mlxsw_core_port_init(mlxsw_core, local_port, 2803 DEVLINK_PORT_FLAVOUR_PHYSICAL, 2804 port_number, split, split_port_subnumber, 2805 splittable, lanes, 2806 switch_id, switch_id_len); 2807 if (err) 2808 return err; 2809 2810 atomic_inc(&mlxsw_core->active_ports_count); 2811 return 0; 2812 } 2813 EXPORT_SYMBOL(mlxsw_core_port_init); 2814 2815 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u8 local_port) 2816 { 2817 atomic_dec(&mlxsw_core->active_ports_count); 2818 2819 __mlxsw_core_port_fini(mlxsw_core, local_port); 2820 } 2821 EXPORT_SYMBOL(mlxsw_core_port_fini); 2822 2823 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 2824 void *port_driver_priv, 2825 const unsigned char *switch_id, 2826 unsigned char switch_id_len) 2827 { 2828 struct mlxsw_core_port *mlxsw_core_port = 2829 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 2830 int err; 2831 2832 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 2833 DEVLINK_PORT_FLAVOUR_CPU, 2834 0, false, 0, false, 0, 2835 switch_id, switch_id_len); 2836 if (err) 2837 return err; 2838 2839 mlxsw_core_port->port_driver_priv = port_driver_priv; 2840 return 0; 2841 } 2842 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 2843 2844 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 2845 { 2846 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 2847 } 2848 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 2849 2850 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u8 local_port, 2851 void *port_driver_priv, struct net_device *dev) 2852 { 2853 struct mlxsw_core_port *mlxsw_core_port = 2854 &mlxsw_core->ports[local_port]; 2855 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2856 2857 mlxsw_core_port->port_driver_priv = port_driver_priv; 2858 devlink_port_type_eth_set(devlink_port, dev); 2859 } 2860 EXPORT_SYMBOL(mlxsw_core_port_eth_set); 2861 2862 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u8 local_port, 2863 void *port_driver_priv) 2864 { 2865 struct mlxsw_core_port *mlxsw_core_port = 2866 &mlxsw_core->ports[local_port]; 2867 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2868 2869 mlxsw_core_port->port_driver_priv = port_driver_priv; 2870 devlink_port_type_ib_set(devlink_port, NULL); 2871 } 2872 EXPORT_SYMBOL(mlxsw_core_port_ib_set); 2873 2874 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u8 local_port, 2875 void *port_driver_priv) 2876 { 2877 struct mlxsw_core_port *mlxsw_core_port = 2878 &mlxsw_core->ports[local_port]; 2879 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2880 2881 mlxsw_core_port->port_driver_priv = port_driver_priv; 2882 devlink_port_type_clear(devlink_port); 2883 } 2884 EXPORT_SYMBOL(mlxsw_core_port_clear); 2885 2886 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 2887 u8 local_port) 2888 { 2889 struct mlxsw_core_port *mlxsw_core_port = 2890 &mlxsw_core->ports[local_port]; 2891 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2892 2893 return devlink_port->type; 2894 } 2895 EXPORT_SYMBOL(mlxsw_core_port_type_get); 2896 2897 2898 struct devlink_port * 2899 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 2900 u8 local_port) 2901 { 2902 struct mlxsw_core_port *mlxsw_core_port = 2903 &mlxsw_core->ports[local_port]; 2904 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2905 2906 return devlink_port; 2907 } 2908 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 2909 2910 bool mlxsw_core_port_is_xm(const struct mlxsw_core *mlxsw_core, u8 local_port) 2911 { 2912 const struct mlxsw_bus_info *bus_info = mlxsw_core->bus_info; 2913 int i; 2914 2915 for (i = 0; i < bus_info->xm_local_ports_count; i++) 2916 if (bus_info->xm_local_ports[i] == local_port) 2917 return true; 2918 return false; 2919 } 2920 EXPORT_SYMBOL(mlxsw_core_port_is_xm); 2921 2922 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 2923 { 2924 return mlxsw_core->env; 2925 } 2926 2927 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 2928 const char *buf, size_t size) 2929 { 2930 __be32 *m = (__be32 *) buf; 2931 int i; 2932 int count = size / sizeof(__be32); 2933 2934 for (i = count - 1; i >= 0; i--) 2935 if (m[i]) 2936 break; 2937 i++; 2938 count = i ? i : 1; 2939 for (i = 0; i < count; i += 4) 2940 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 2941 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 2942 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 2943 } 2944 2945 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 2946 u32 in_mod, bool out_mbox_direct, bool reset_ok, 2947 char *in_mbox, size_t in_mbox_size, 2948 char *out_mbox, size_t out_mbox_size) 2949 { 2950 u8 status; 2951 int err; 2952 2953 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 2954 if (!mlxsw_core->bus->cmd_exec) 2955 return -EOPNOTSUPP; 2956 2957 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 2958 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 2959 if (in_mbox) { 2960 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 2961 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 2962 } 2963 2964 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 2965 opcode_mod, in_mod, out_mbox_direct, 2966 in_mbox, in_mbox_size, 2967 out_mbox, out_mbox_size, &status); 2968 2969 if (!err && out_mbox) { 2970 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 2971 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 2972 } 2973 2974 if (reset_ok && err == -EIO && 2975 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 2976 err = 0; 2977 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 2978 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 2979 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 2980 in_mod, status, mlxsw_cmd_status_str(status)); 2981 } else if (err == -ETIMEDOUT) { 2982 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 2983 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 2984 in_mod); 2985 } 2986 2987 return err; 2988 } 2989 EXPORT_SYMBOL(mlxsw_cmd_exec); 2990 2991 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 2992 { 2993 return queue_delayed_work(mlxsw_wq, dwork, delay); 2994 } 2995 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 2996 2997 bool mlxsw_core_schedule_work(struct work_struct *work) 2998 { 2999 return queue_work(mlxsw_owq, work); 3000 } 3001 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3002 3003 void mlxsw_core_flush_owq(void) 3004 { 3005 flush_workqueue(mlxsw_owq); 3006 } 3007 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3008 3009 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3010 const struct mlxsw_config_profile *profile, 3011 u64 *p_single_size, u64 *p_double_size, 3012 u64 *p_linear_size) 3013 { 3014 struct mlxsw_driver *driver = mlxsw_core->driver; 3015 3016 if (!driver->kvd_sizes_get) 3017 return -EINVAL; 3018 3019 return driver->kvd_sizes_get(mlxsw_core, profile, 3020 p_single_size, p_double_size, 3021 p_linear_size); 3022 } 3023 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3024 3025 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3026 struct mlxsw_res *res) 3027 { 3028 int index, i; 3029 u64 data; 3030 u16 id; 3031 int err; 3032 3033 if (!res) 3034 return 0; 3035 3036 mlxsw_cmd_mbox_zero(mbox); 3037 3038 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3039 index++) { 3040 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3041 if (err) 3042 return err; 3043 3044 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3045 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3046 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3047 3048 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3049 return 0; 3050 3051 mlxsw_res_parse(res, id, data); 3052 } 3053 } 3054 3055 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3056 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3057 */ 3058 return -EIO; 3059 } 3060 EXPORT_SYMBOL(mlxsw_core_resources_query); 3061 3062 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3063 { 3064 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3065 } 3066 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3067 3068 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3069 { 3070 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3071 } 3072 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3073 3074 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core) 3075 { 3076 mlxsw_core->emad.enable_string_tlv = true; 3077 } 3078 EXPORT_SYMBOL(mlxsw_core_emad_string_tlv_enable); 3079 3080 static int __init mlxsw_core_module_init(void) 3081 { 3082 int err; 3083 3084 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3085 if (!mlxsw_wq) 3086 return -ENOMEM; 3087 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3088 mlxsw_core_driver_name); 3089 if (!mlxsw_owq) { 3090 err = -ENOMEM; 3091 goto err_alloc_ordered_workqueue; 3092 } 3093 return 0; 3094 3095 err_alloc_ordered_workqueue: 3096 destroy_workqueue(mlxsw_wq); 3097 return err; 3098 } 3099 3100 static void __exit mlxsw_core_module_exit(void) 3101 { 3102 destroy_workqueue(mlxsw_owq); 3103 destroy_workqueue(mlxsw_wq); 3104 } 3105 3106 module_init(mlxsw_core_module_init); 3107 module_exit(mlxsw_core_module_exit); 3108 3109 MODULE_LICENSE("Dual BSD/GPL"); 3110 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3111 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3112