1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u16 local_port; 51 struct mlxsw_linecard *linecard; 52 }; 53 54 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 55 { 56 return mlxsw_core_port->port_driver_priv; 57 } 58 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 59 60 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 61 { 62 return mlxsw_core_port->port_driver_priv != NULL; 63 } 64 65 struct mlxsw_core { 66 struct mlxsw_driver *driver; 67 const struct mlxsw_bus *bus; 68 void *bus_priv; 69 const struct mlxsw_bus_info *bus_info; 70 struct workqueue_struct *emad_wq; 71 struct list_head rx_listener_list; 72 struct list_head event_listener_list; 73 struct list_head irq_event_handler_list; 74 struct mutex irq_event_handler_lock; /* Locks access to handlers list */ 75 struct { 76 atomic64_t tid; 77 struct list_head trans_list; 78 spinlock_t trans_list_lock; /* protects trans_list writes */ 79 bool use_emad; 80 bool enable_string_tlv; 81 } emad; 82 struct { 83 u16 *mapping; /* lag_id+port_index to local_port mapping */ 84 } lag; 85 struct mlxsw_res res; 86 struct mlxsw_hwmon *hwmon; 87 struct mlxsw_thermal *thermal; 88 struct mlxsw_linecards *linecards; 89 struct mlxsw_core_port *ports; 90 unsigned int max_ports; 91 atomic_t active_ports_count; 92 bool fw_flash_in_progress; 93 struct { 94 struct devlink_health_reporter *fw_fatal; 95 } health; 96 struct mlxsw_env *env; 97 unsigned long driver_priv[]; 98 /* driver_priv has to be always the last item */ 99 }; 100 101 struct mlxsw_linecards *mlxsw_core_linecards(struct mlxsw_core *mlxsw_core) 102 { 103 return mlxsw_core->linecards; 104 } 105 106 void mlxsw_core_linecards_set(struct mlxsw_core *mlxsw_core, 107 struct mlxsw_linecards *linecards) 108 { 109 mlxsw_core->linecards = linecards; 110 } 111 112 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 113 114 static u64 mlxsw_ports_occ_get(void *priv) 115 { 116 struct mlxsw_core *mlxsw_core = priv; 117 118 return atomic_read(&mlxsw_core->active_ports_count); 119 } 120 121 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 122 { 123 struct devlink *devlink = priv_to_devlink(mlxsw_core); 124 struct devlink_resource_size_params ports_num_params; 125 u32 max_ports; 126 127 max_ports = mlxsw_core->max_ports - 1; 128 devlink_resource_size_params_init(&ports_num_params, max_ports, 129 max_ports, 1, 130 DEVLINK_RESOURCE_UNIT_ENTRY); 131 132 return devl_resource_register(devlink, 133 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 134 max_ports, MLXSW_CORE_RESOURCE_PORTS, 135 DEVLINK_RESOURCE_ID_PARENT_TOP, 136 &ports_num_params); 137 } 138 139 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 140 { 141 struct devlink *devlink = priv_to_devlink(mlxsw_core); 142 int err; 143 144 /* Switch ports are numbered from 1 to queried value */ 145 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 146 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 147 MAX_SYSTEM_PORT) + 1; 148 else 149 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 150 151 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 152 sizeof(struct mlxsw_core_port), GFP_KERNEL); 153 if (!mlxsw_core->ports) 154 return -ENOMEM; 155 156 if (!reload) { 157 err = mlxsw_core_resources_ports_register(mlxsw_core); 158 if (err) 159 goto err_resources_ports_register; 160 } 161 atomic_set(&mlxsw_core->active_ports_count, 0); 162 devl_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 163 mlxsw_ports_occ_get, mlxsw_core); 164 165 return 0; 166 167 err_resources_ports_register: 168 kfree(mlxsw_core->ports); 169 return err; 170 } 171 172 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 173 { 174 struct devlink *devlink = priv_to_devlink(mlxsw_core); 175 176 devl_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 177 if (!reload) 178 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 179 180 kfree(mlxsw_core->ports); 181 } 182 183 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 184 { 185 return mlxsw_core->max_ports; 186 } 187 EXPORT_SYMBOL(mlxsw_core_max_ports); 188 189 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 190 { 191 return mlxsw_core->driver_priv; 192 } 193 EXPORT_SYMBOL(mlxsw_core_driver_priv); 194 195 bool 196 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 197 const struct mlxsw_fw_rev *req_rev) 198 { 199 return rev->minor > req_rev->minor || 200 (rev->minor == req_rev->minor && 201 rev->subminor >= req_rev->subminor); 202 } 203 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 204 205 struct mlxsw_rx_listener_item { 206 struct list_head list; 207 struct mlxsw_rx_listener rxl; 208 void *priv; 209 bool enabled; 210 }; 211 212 struct mlxsw_event_listener_item { 213 struct list_head list; 214 struct mlxsw_core *mlxsw_core; 215 struct mlxsw_event_listener el; 216 void *priv; 217 }; 218 219 static const u8 mlxsw_core_trap_groups[] = { 220 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 221 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 222 }; 223 224 static int mlxsw_core_trap_groups_set(struct mlxsw_core *mlxsw_core) 225 { 226 char htgt_pl[MLXSW_REG_HTGT_LEN]; 227 int err; 228 int i; 229 230 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 231 return 0; 232 233 for (i = 0; i < ARRAY_SIZE(mlxsw_core_trap_groups); i++) { 234 mlxsw_reg_htgt_pack(htgt_pl, mlxsw_core_trap_groups[i], 235 MLXSW_REG_HTGT_INVALID_POLICER, 236 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 237 MLXSW_REG_HTGT_DEFAULT_TC); 238 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 239 if (err) 240 return err; 241 } 242 return 0; 243 } 244 245 /****************** 246 * EMAD processing 247 ******************/ 248 249 /* emad_eth_hdr_dmac 250 * Destination MAC in EMAD's Ethernet header. 251 * Must be set to 01:02:c9:00:00:01 252 */ 253 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 254 255 /* emad_eth_hdr_smac 256 * Source MAC in EMAD's Ethernet header. 257 * Must be set to 00:02:c9:01:02:03 258 */ 259 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 260 261 /* emad_eth_hdr_ethertype 262 * Ethertype in EMAD's Ethernet header. 263 * Must be set to 0x8932 264 */ 265 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 266 267 /* emad_eth_hdr_mlx_proto 268 * Mellanox protocol. 269 * Must be set to 0x0. 270 */ 271 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 272 273 /* emad_eth_hdr_ver 274 * Mellanox protocol version. 275 * Must be set to 0x0. 276 */ 277 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 278 279 /* emad_op_tlv_type 280 * Type of the TLV. 281 * Must be set to 0x1 (operation TLV). 282 */ 283 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 284 285 /* emad_op_tlv_len 286 * Length of the operation TLV in u32. 287 * Must be set to 0x4. 288 */ 289 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 290 291 /* emad_op_tlv_dr 292 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 293 * EMAD. DR TLV must follow. 294 * 295 * Note: Currently not supported and must not be set. 296 */ 297 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 298 299 /* emad_op_tlv_status 300 * Returned status in case of EMAD response. Must be set to 0 in case 301 * of EMAD request. 302 * 0x0 - success 303 * 0x1 - device is busy. Requester should retry 304 * 0x2 - Mellanox protocol version not supported 305 * 0x3 - unknown TLV 306 * 0x4 - register not supported 307 * 0x5 - operation class not supported 308 * 0x6 - EMAD method not supported 309 * 0x7 - bad parameter (e.g. port out of range) 310 * 0x8 - resource not available 311 * 0x9 - message receipt acknowledgment. Requester should retry 312 * 0x70 - internal error 313 */ 314 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 315 316 /* emad_op_tlv_register_id 317 * Register ID of register within register TLV. 318 */ 319 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 320 321 /* emad_op_tlv_r 322 * Response bit. Setting to 1 indicates Response, otherwise request. 323 */ 324 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 325 326 /* emad_op_tlv_method 327 * EMAD method type. 328 * 0x1 - query 329 * 0x2 - write 330 * 0x3 - send (currently not supported) 331 * 0x4 - event 332 */ 333 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 334 335 /* emad_op_tlv_class 336 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 337 */ 338 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 339 340 /* emad_op_tlv_tid 341 * EMAD transaction ID. Used for pairing request and response EMADs. 342 */ 343 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 344 345 /* emad_string_tlv_type 346 * Type of the TLV. 347 * Must be set to 0x2 (string TLV). 348 */ 349 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 350 351 /* emad_string_tlv_len 352 * Length of the string TLV in u32. 353 */ 354 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 355 356 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 357 358 /* emad_string_tlv_string 359 * String provided by the device's firmware in case of erroneous register access 360 */ 361 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 362 MLXSW_EMAD_STRING_TLV_STRING_LEN); 363 364 /* emad_reg_tlv_type 365 * Type of the TLV. 366 * Must be set to 0x3 (register TLV). 367 */ 368 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 369 370 /* emad_reg_tlv_len 371 * Length of the operation TLV in u32. 372 */ 373 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 374 375 /* emad_end_tlv_type 376 * Type of the TLV. 377 * Must be set to 0x0 (end TLV). 378 */ 379 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 380 381 /* emad_end_tlv_len 382 * Length of the end TLV in u32. 383 * Must be set to 1. 384 */ 385 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 386 387 enum mlxsw_core_reg_access_type { 388 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 389 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 390 }; 391 392 static inline const char * 393 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 394 { 395 switch (type) { 396 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 397 return "query"; 398 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 399 return "write"; 400 } 401 BUG(); 402 } 403 404 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 405 { 406 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 407 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 408 } 409 410 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 411 const struct mlxsw_reg_info *reg, 412 char *payload) 413 { 414 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 415 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 416 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 417 } 418 419 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 420 { 421 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 422 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 423 } 424 425 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 426 const struct mlxsw_reg_info *reg, 427 enum mlxsw_core_reg_access_type type, 428 u64 tid) 429 { 430 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 431 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 432 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 433 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 434 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 435 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 436 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 437 mlxsw_emad_op_tlv_method_set(op_tlv, 438 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 439 else 440 mlxsw_emad_op_tlv_method_set(op_tlv, 441 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 442 mlxsw_emad_op_tlv_class_set(op_tlv, 443 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 444 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 445 } 446 447 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 448 { 449 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 450 451 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 452 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 453 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 454 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 455 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 456 457 skb_reset_mac_header(skb); 458 459 return 0; 460 } 461 462 static void mlxsw_emad_construct(struct sk_buff *skb, 463 const struct mlxsw_reg_info *reg, 464 char *payload, 465 enum mlxsw_core_reg_access_type type, 466 u64 tid, bool enable_string_tlv) 467 { 468 char *buf; 469 470 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 471 mlxsw_emad_pack_end_tlv(buf); 472 473 buf = skb_push(skb, reg->len + sizeof(u32)); 474 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 475 476 if (enable_string_tlv) { 477 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 478 mlxsw_emad_pack_string_tlv(buf); 479 } 480 481 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 482 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 483 484 mlxsw_emad_construct_eth_hdr(skb); 485 } 486 487 struct mlxsw_emad_tlv_offsets { 488 u16 op_tlv; 489 u16 string_tlv; 490 u16 reg_tlv; 491 }; 492 493 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 494 { 495 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 496 497 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 498 } 499 500 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 501 { 502 struct mlxsw_emad_tlv_offsets *offsets = 503 (struct mlxsw_emad_tlv_offsets *) skb->cb; 504 505 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 506 offsets->string_tlv = 0; 507 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 508 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 509 510 /* If string TLV is present, it must come after the operation TLV. */ 511 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 512 offsets->string_tlv = offsets->reg_tlv; 513 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 514 } 515 } 516 517 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 518 { 519 struct mlxsw_emad_tlv_offsets *offsets = 520 (struct mlxsw_emad_tlv_offsets *) skb->cb; 521 522 return ((char *) (skb->data + offsets->op_tlv)); 523 } 524 525 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 526 { 527 struct mlxsw_emad_tlv_offsets *offsets = 528 (struct mlxsw_emad_tlv_offsets *) skb->cb; 529 530 if (!offsets->string_tlv) 531 return NULL; 532 533 return ((char *) (skb->data + offsets->string_tlv)); 534 } 535 536 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 537 { 538 struct mlxsw_emad_tlv_offsets *offsets = 539 (struct mlxsw_emad_tlv_offsets *) skb->cb; 540 541 return ((char *) (skb->data + offsets->reg_tlv)); 542 } 543 544 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 545 { 546 return ((char *) (reg_tlv + sizeof(u32))); 547 } 548 549 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 550 { 551 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 552 } 553 554 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 555 { 556 char *op_tlv; 557 558 op_tlv = mlxsw_emad_op_tlv(skb); 559 return mlxsw_emad_op_tlv_tid_get(op_tlv); 560 } 561 562 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 563 { 564 char *op_tlv; 565 566 op_tlv = mlxsw_emad_op_tlv(skb); 567 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 568 } 569 570 static int mlxsw_emad_process_status(char *op_tlv, 571 enum mlxsw_emad_op_tlv_status *p_status) 572 { 573 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 574 575 switch (*p_status) { 576 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 577 return 0; 578 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 579 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 580 return -EAGAIN; 581 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 582 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 583 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 584 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 585 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 586 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 587 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 588 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 589 default: 590 return -EIO; 591 } 592 } 593 594 static int 595 mlxsw_emad_process_status_skb(struct sk_buff *skb, 596 enum mlxsw_emad_op_tlv_status *p_status) 597 { 598 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 599 } 600 601 struct mlxsw_reg_trans { 602 struct list_head list; 603 struct list_head bulk_list; 604 struct mlxsw_core *core; 605 struct sk_buff *tx_skb; 606 struct mlxsw_tx_info tx_info; 607 struct delayed_work timeout_dw; 608 unsigned int retries; 609 u64 tid; 610 struct completion completion; 611 atomic_t active; 612 mlxsw_reg_trans_cb_t *cb; 613 unsigned long cb_priv; 614 const struct mlxsw_reg_info *reg; 615 enum mlxsw_core_reg_access_type type; 616 int err; 617 char *emad_err_string; 618 enum mlxsw_emad_op_tlv_status emad_status; 619 struct rcu_head rcu; 620 }; 621 622 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 623 struct mlxsw_reg_trans *trans) 624 { 625 char *string_tlv; 626 char *string; 627 628 string_tlv = mlxsw_emad_string_tlv(skb); 629 if (!string_tlv) 630 return; 631 632 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 633 GFP_ATOMIC); 634 if (!trans->emad_err_string) 635 return; 636 637 string = mlxsw_emad_string_tlv_string_data(string_tlv); 638 strlcpy(trans->emad_err_string, string, 639 MLXSW_EMAD_STRING_TLV_STRING_LEN); 640 } 641 642 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 643 #define MLXSW_EMAD_TIMEOUT_MS 200 644 645 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 646 { 647 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 648 649 if (trans->core->fw_flash_in_progress) 650 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 651 652 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 653 timeout << trans->retries); 654 } 655 656 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 657 struct mlxsw_reg_trans *trans) 658 { 659 struct sk_buff *skb; 660 int err; 661 662 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 663 if (!skb) 664 return -ENOMEM; 665 666 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 667 skb->data + mlxsw_core->driver->txhdr_len, 668 skb->len - mlxsw_core->driver->txhdr_len); 669 670 atomic_set(&trans->active, 1); 671 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 672 if (err) { 673 dev_kfree_skb(skb); 674 return err; 675 } 676 mlxsw_emad_trans_timeout_schedule(trans); 677 return 0; 678 } 679 680 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 681 { 682 struct mlxsw_core *mlxsw_core = trans->core; 683 684 dev_kfree_skb(trans->tx_skb); 685 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 686 list_del_rcu(&trans->list); 687 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 688 trans->err = err; 689 complete(&trans->completion); 690 } 691 692 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 693 struct mlxsw_reg_trans *trans) 694 { 695 int err; 696 697 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 698 trans->retries++; 699 err = mlxsw_emad_transmit(trans->core, trans); 700 if (err == 0) 701 return; 702 703 if (!atomic_dec_and_test(&trans->active)) 704 return; 705 } else { 706 err = -EIO; 707 } 708 mlxsw_emad_trans_finish(trans, err); 709 } 710 711 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 712 { 713 struct mlxsw_reg_trans *trans = container_of(work, 714 struct mlxsw_reg_trans, 715 timeout_dw.work); 716 717 if (!atomic_dec_and_test(&trans->active)) 718 return; 719 720 mlxsw_emad_transmit_retry(trans->core, trans); 721 } 722 723 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 724 struct mlxsw_reg_trans *trans, 725 struct sk_buff *skb) 726 { 727 int err; 728 729 if (!atomic_dec_and_test(&trans->active)) 730 return; 731 732 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 733 if (err == -EAGAIN) { 734 mlxsw_emad_transmit_retry(mlxsw_core, trans); 735 } else { 736 if (err == 0) { 737 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 738 739 if (trans->cb) 740 trans->cb(mlxsw_core, 741 mlxsw_emad_reg_payload(reg_tlv), 742 trans->reg->len, trans->cb_priv); 743 } else { 744 mlxsw_emad_process_string_tlv(skb, trans); 745 } 746 mlxsw_emad_trans_finish(trans, err); 747 } 748 } 749 750 /* called with rcu read lock held */ 751 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, 752 void *priv) 753 { 754 struct mlxsw_core *mlxsw_core = priv; 755 struct mlxsw_reg_trans *trans; 756 757 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 758 skb->data, skb->len); 759 760 mlxsw_emad_tlv_parse(skb); 761 762 if (!mlxsw_emad_is_resp(skb)) 763 goto free_skb; 764 765 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 766 if (mlxsw_emad_get_tid(skb) == trans->tid) { 767 mlxsw_emad_process_response(mlxsw_core, trans, skb); 768 break; 769 } 770 } 771 772 free_skb: 773 dev_kfree_skb(skb); 774 } 775 776 static const struct mlxsw_listener mlxsw_emad_rx_listener = 777 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 778 EMAD, DISCARD); 779 780 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 781 { 782 struct workqueue_struct *emad_wq; 783 u64 tid; 784 int err; 785 786 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 787 return 0; 788 789 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 790 if (!emad_wq) 791 return -ENOMEM; 792 mlxsw_core->emad_wq = emad_wq; 793 794 /* Set the upper 32 bits of the transaction ID field to a random 795 * number. This allows us to discard EMADs addressed to other 796 * devices. 797 */ 798 get_random_bytes(&tid, 4); 799 tid <<= 32; 800 atomic64_set(&mlxsw_core->emad.tid, tid); 801 802 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 803 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 804 805 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 806 mlxsw_core); 807 if (err) 808 goto err_trap_register; 809 810 mlxsw_core->emad.use_emad = true; 811 812 return 0; 813 814 err_trap_register: 815 destroy_workqueue(mlxsw_core->emad_wq); 816 return err; 817 } 818 819 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 820 { 821 822 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 823 return; 824 825 mlxsw_core->emad.use_emad = false; 826 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 827 mlxsw_core); 828 destroy_workqueue(mlxsw_core->emad_wq); 829 } 830 831 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 832 u16 reg_len, bool enable_string_tlv) 833 { 834 struct sk_buff *skb; 835 u16 emad_len; 836 837 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 838 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 839 sizeof(u32) + mlxsw_core->driver->txhdr_len); 840 if (enable_string_tlv) 841 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 842 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 843 return NULL; 844 845 skb = netdev_alloc_skb(NULL, emad_len); 846 if (!skb) 847 return NULL; 848 memset(skb->data, 0, emad_len); 849 skb_reserve(skb, emad_len); 850 851 return skb; 852 } 853 854 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 855 const struct mlxsw_reg_info *reg, 856 char *payload, 857 enum mlxsw_core_reg_access_type type, 858 struct mlxsw_reg_trans *trans, 859 struct list_head *bulk_list, 860 mlxsw_reg_trans_cb_t *cb, 861 unsigned long cb_priv, u64 tid) 862 { 863 bool enable_string_tlv; 864 struct sk_buff *skb; 865 int err; 866 867 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 868 tid, reg->id, mlxsw_reg_id_str(reg->id), 869 mlxsw_core_reg_access_type_str(type)); 870 871 /* Since this can be changed during emad_reg_access, read it once and 872 * use the value all the way. 873 */ 874 enable_string_tlv = mlxsw_core->emad.enable_string_tlv; 875 876 skb = mlxsw_emad_alloc(mlxsw_core, reg->len, enable_string_tlv); 877 if (!skb) 878 return -ENOMEM; 879 880 list_add_tail(&trans->bulk_list, bulk_list); 881 trans->core = mlxsw_core; 882 trans->tx_skb = skb; 883 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 884 trans->tx_info.is_emad = true; 885 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 886 trans->tid = tid; 887 init_completion(&trans->completion); 888 trans->cb = cb; 889 trans->cb_priv = cb_priv; 890 trans->reg = reg; 891 trans->type = type; 892 893 mlxsw_emad_construct(skb, reg, payload, type, trans->tid, 894 enable_string_tlv); 895 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 896 897 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 898 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 899 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 900 err = mlxsw_emad_transmit(mlxsw_core, trans); 901 if (err) 902 goto err_out; 903 return 0; 904 905 err_out: 906 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 907 list_del_rcu(&trans->list); 908 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 909 list_del(&trans->bulk_list); 910 dev_kfree_skb(trans->tx_skb); 911 return err; 912 } 913 914 /***************** 915 * Core functions 916 *****************/ 917 918 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 919 { 920 spin_lock(&mlxsw_core_driver_list_lock); 921 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 922 spin_unlock(&mlxsw_core_driver_list_lock); 923 return 0; 924 } 925 EXPORT_SYMBOL(mlxsw_core_driver_register); 926 927 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 928 { 929 spin_lock(&mlxsw_core_driver_list_lock); 930 list_del(&mlxsw_driver->list); 931 spin_unlock(&mlxsw_core_driver_list_lock); 932 } 933 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 934 935 static struct mlxsw_driver *__driver_find(const char *kind) 936 { 937 struct mlxsw_driver *mlxsw_driver; 938 939 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 940 if (strcmp(mlxsw_driver->kind, kind) == 0) 941 return mlxsw_driver; 942 } 943 return NULL; 944 } 945 946 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 947 { 948 struct mlxsw_driver *mlxsw_driver; 949 950 spin_lock(&mlxsw_core_driver_list_lock); 951 mlxsw_driver = __driver_find(kind); 952 spin_unlock(&mlxsw_core_driver_list_lock); 953 return mlxsw_driver; 954 } 955 956 int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, 957 struct mlxfw_dev *mlxfw_dev, 958 const struct firmware *firmware, 959 struct netlink_ext_ack *extack) 960 { 961 int err; 962 963 mlxsw_core->fw_flash_in_progress = true; 964 err = mlxfw_firmware_flash(mlxfw_dev, firmware, extack); 965 mlxsw_core->fw_flash_in_progress = false; 966 967 return err; 968 } 969 970 struct mlxsw_core_fw_info { 971 struct mlxfw_dev mlxfw_dev; 972 struct mlxsw_core *mlxsw_core; 973 }; 974 975 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 976 u16 component_index, u32 *p_max_size, 977 u8 *p_align_bits, u16 *p_max_write_size) 978 { 979 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 980 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 981 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 982 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 983 int err; 984 985 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 986 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 987 if (err) 988 return err; 989 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 990 991 *p_align_bits = max_t(u8, *p_align_bits, 2); 992 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 993 return 0; 994 } 995 996 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 997 { 998 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 999 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1000 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1001 char mcc_pl[MLXSW_REG_MCC_LEN]; 1002 u8 control_state; 1003 int err; 1004 1005 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 1006 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1007 if (err) 1008 return err; 1009 1010 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 1011 if (control_state != MLXFW_FSM_STATE_IDLE) 1012 return -EBUSY; 1013 1014 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 1015 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1016 } 1017 1018 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1019 u16 component_index, u32 component_size) 1020 { 1021 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1022 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1023 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1024 char mcc_pl[MLXSW_REG_MCC_LEN]; 1025 1026 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 1027 component_index, fwhandle, component_size); 1028 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1029 } 1030 1031 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1032 u8 *data, u16 size, u32 offset) 1033 { 1034 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1035 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1036 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1037 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1038 1039 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1040 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1041 } 1042 1043 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1044 u16 component_index) 1045 { 1046 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1047 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1048 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1049 char mcc_pl[MLXSW_REG_MCC_LEN]; 1050 1051 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1052 component_index, fwhandle, 0); 1053 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1054 } 1055 1056 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1057 { 1058 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1059 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1060 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1061 char mcc_pl[MLXSW_REG_MCC_LEN]; 1062 1063 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1064 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1065 } 1066 1067 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1068 enum mlxfw_fsm_state *fsm_state, 1069 enum mlxfw_fsm_state_err *fsm_state_err) 1070 { 1071 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1072 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1073 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1074 char mcc_pl[MLXSW_REG_MCC_LEN]; 1075 u8 control_state; 1076 u8 error_code; 1077 int err; 1078 1079 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1080 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1081 if (err) 1082 return err; 1083 1084 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1085 *fsm_state = control_state; 1086 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1087 return 0; 1088 } 1089 1090 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1091 { 1092 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1093 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1094 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1095 char mcc_pl[MLXSW_REG_MCC_LEN]; 1096 1097 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1098 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1099 } 1100 1101 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1102 { 1103 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1104 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1105 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1106 char mcc_pl[MLXSW_REG_MCC_LEN]; 1107 1108 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1109 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1110 } 1111 1112 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1113 .component_query = mlxsw_core_fw_component_query, 1114 .fsm_lock = mlxsw_core_fw_fsm_lock, 1115 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1116 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1117 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1118 .fsm_activate = mlxsw_core_fw_fsm_activate, 1119 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1120 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1121 .fsm_release = mlxsw_core_fw_fsm_release, 1122 }; 1123 1124 static int mlxsw_core_dev_fw_flash(struct mlxsw_core *mlxsw_core, 1125 const struct firmware *firmware, 1126 struct netlink_ext_ack *extack) 1127 { 1128 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1129 .mlxfw_dev = { 1130 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1131 .psid = mlxsw_core->bus_info->psid, 1132 .psid_size = strlen(mlxsw_core->bus_info->psid), 1133 .devlink = priv_to_devlink(mlxsw_core), 1134 }, 1135 .mlxsw_core = mlxsw_core 1136 }; 1137 1138 return mlxsw_core_fw_flash(mlxsw_core, &mlxsw_core_fw_info.mlxfw_dev, 1139 firmware, extack); 1140 } 1141 1142 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1143 const struct mlxsw_bus_info *mlxsw_bus_info, 1144 const struct mlxsw_fw_rev *req_rev, 1145 const char *filename) 1146 { 1147 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1148 union devlink_param_value value; 1149 const struct firmware *firmware; 1150 int err; 1151 1152 /* Don't check if driver does not require it */ 1153 if (!req_rev || !filename) 1154 return 0; 1155 1156 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1157 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1158 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1159 &value); 1160 if (err) 1161 return err; 1162 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1163 return 0; 1164 1165 /* Validate driver & FW are compatible */ 1166 if (rev->major != req_rev->major) { 1167 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1168 rev->major, req_rev->major); 1169 return -EINVAL; 1170 } 1171 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1172 return 0; 1173 1174 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1175 rev->major, rev->minor, rev->subminor, req_rev->major, 1176 req_rev->minor, req_rev->subminor); 1177 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1178 1179 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1180 if (err) { 1181 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1182 return err; 1183 } 1184 1185 err = mlxsw_core_dev_fw_flash(mlxsw_core, firmware, NULL); 1186 release_firmware(firmware); 1187 if (err) 1188 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1189 1190 /* On FW flash success, tell the caller FW reset is needed 1191 * if current FW supports it. 1192 */ 1193 if (rev->minor >= req_rev->can_reset_minor) 1194 return err ? err : -EAGAIN; 1195 else 1196 return 0; 1197 } 1198 1199 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1200 struct devlink_flash_update_params *params, 1201 struct netlink_ext_ack *extack) 1202 { 1203 return mlxsw_core_dev_fw_flash(mlxsw_core, params->fw, extack); 1204 } 1205 1206 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1207 union devlink_param_value val, 1208 struct netlink_ext_ack *extack) 1209 { 1210 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1211 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1212 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1213 return -EINVAL; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1220 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1221 mlxsw_core_devlink_param_fw_load_policy_validate), 1222 }; 1223 1224 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1225 { 1226 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1227 union devlink_param_value value; 1228 int err; 1229 1230 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1231 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1232 if (err) 1233 return err; 1234 1235 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1236 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1237 return 0; 1238 } 1239 1240 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1241 { 1242 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1243 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1244 } 1245 1246 static void *__dl_port(struct devlink_port *devlink_port) 1247 { 1248 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1249 } 1250 1251 static int mlxsw_devlink_port_split(struct devlink *devlink, 1252 struct devlink_port *port, 1253 unsigned int count, 1254 struct netlink_ext_ack *extack) 1255 { 1256 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1257 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1258 1259 if (!mlxsw_core->driver->port_split) 1260 return -EOPNOTSUPP; 1261 return mlxsw_core->driver->port_split(mlxsw_core, 1262 mlxsw_core_port->local_port, 1263 count, extack); 1264 } 1265 1266 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1267 struct devlink_port *port, 1268 struct netlink_ext_ack *extack) 1269 { 1270 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1271 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1272 1273 if (!mlxsw_core->driver->port_unsplit) 1274 return -EOPNOTSUPP; 1275 return mlxsw_core->driver->port_unsplit(mlxsw_core, 1276 mlxsw_core_port->local_port, 1277 extack); 1278 } 1279 1280 static int 1281 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1282 unsigned int sb_index, u16 pool_index, 1283 struct devlink_sb_pool_info *pool_info) 1284 { 1285 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1286 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1287 1288 if (!mlxsw_driver->sb_pool_get) 1289 return -EOPNOTSUPP; 1290 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1291 pool_index, pool_info); 1292 } 1293 1294 static int 1295 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1296 unsigned int sb_index, u16 pool_index, u32 size, 1297 enum devlink_sb_threshold_type threshold_type, 1298 struct netlink_ext_ack *extack) 1299 { 1300 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1301 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1302 1303 if (!mlxsw_driver->sb_pool_set) 1304 return -EOPNOTSUPP; 1305 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1306 pool_index, size, threshold_type, 1307 extack); 1308 } 1309 1310 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1311 unsigned int sb_index, u16 pool_index, 1312 u32 *p_threshold) 1313 { 1314 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1315 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1316 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1317 1318 if (!mlxsw_driver->sb_port_pool_get || 1319 !mlxsw_core_port_check(mlxsw_core_port)) 1320 return -EOPNOTSUPP; 1321 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1322 pool_index, p_threshold); 1323 } 1324 1325 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1326 unsigned int sb_index, u16 pool_index, 1327 u32 threshold, 1328 struct netlink_ext_ack *extack) 1329 { 1330 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1331 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1332 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1333 1334 if (!mlxsw_driver->sb_port_pool_set || 1335 !mlxsw_core_port_check(mlxsw_core_port)) 1336 return -EOPNOTSUPP; 1337 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1338 pool_index, threshold, extack); 1339 } 1340 1341 static int 1342 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1343 unsigned int sb_index, u16 tc_index, 1344 enum devlink_sb_pool_type pool_type, 1345 u16 *p_pool_index, u32 *p_threshold) 1346 { 1347 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1348 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1349 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1350 1351 if (!mlxsw_driver->sb_tc_pool_bind_get || 1352 !mlxsw_core_port_check(mlxsw_core_port)) 1353 return -EOPNOTSUPP; 1354 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1355 tc_index, pool_type, 1356 p_pool_index, p_threshold); 1357 } 1358 1359 static int 1360 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1361 unsigned int sb_index, u16 tc_index, 1362 enum devlink_sb_pool_type pool_type, 1363 u16 pool_index, u32 threshold, 1364 struct netlink_ext_ack *extack) 1365 { 1366 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1367 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1368 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1369 1370 if (!mlxsw_driver->sb_tc_pool_bind_set || 1371 !mlxsw_core_port_check(mlxsw_core_port)) 1372 return -EOPNOTSUPP; 1373 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1374 tc_index, pool_type, 1375 pool_index, threshold, extack); 1376 } 1377 1378 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1379 unsigned int sb_index) 1380 { 1381 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1382 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1383 1384 if (!mlxsw_driver->sb_occ_snapshot) 1385 return -EOPNOTSUPP; 1386 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1387 } 1388 1389 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1390 unsigned int sb_index) 1391 { 1392 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1393 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1394 1395 if (!mlxsw_driver->sb_occ_max_clear) 1396 return -EOPNOTSUPP; 1397 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1398 } 1399 1400 static int 1401 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1402 unsigned int sb_index, u16 pool_index, 1403 u32 *p_cur, u32 *p_max) 1404 { 1405 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1406 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1407 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1408 1409 if (!mlxsw_driver->sb_occ_port_pool_get || 1410 !mlxsw_core_port_check(mlxsw_core_port)) 1411 return -EOPNOTSUPP; 1412 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1413 pool_index, p_cur, p_max); 1414 } 1415 1416 static int 1417 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1418 unsigned int sb_index, u16 tc_index, 1419 enum devlink_sb_pool_type pool_type, 1420 u32 *p_cur, u32 *p_max) 1421 { 1422 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1423 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1424 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1425 1426 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1427 !mlxsw_core_port_check(mlxsw_core_port)) 1428 return -EOPNOTSUPP; 1429 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1430 sb_index, tc_index, 1431 pool_type, p_cur, p_max); 1432 } 1433 1434 static int 1435 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1436 struct netlink_ext_ack *extack) 1437 { 1438 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1439 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1440 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1441 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1442 char buf[32]; 1443 int err; 1444 1445 err = devlink_info_driver_name_put(req, 1446 mlxsw_core->bus_info->device_kind); 1447 if (err) 1448 return err; 1449 1450 mlxsw_reg_mgir_pack(mgir_pl); 1451 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1452 if (err) 1453 return err; 1454 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1455 &fw_minor, &fw_sub_minor); 1456 1457 sprintf(buf, "%X", hw_rev); 1458 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1459 if (err) 1460 return err; 1461 1462 err = devlink_info_version_fixed_put(req, 1463 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1464 fw_info_psid); 1465 if (err) 1466 return err; 1467 1468 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1469 err = devlink_info_version_running_put(req, "fw.version", buf); 1470 if (err) 1471 return err; 1472 1473 return devlink_info_version_running_put(req, 1474 DEVLINK_INFO_VERSION_GENERIC_FW, 1475 buf); 1476 } 1477 1478 static int 1479 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1480 bool netns_change, enum devlink_reload_action action, 1481 enum devlink_reload_limit limit, 1482 struct netlink_ext_ack *extack) 1483 { 1484 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1485 1486 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1487 return -EOPNOTSUPP; 1488 1489 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1490 return 0; 1491 } 1492 1493 static int 1494 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1495 enum devlink_reload_limit limit, u32 *actions_performed, 1496 struct netlink_ext_ack *extack) 1497 { 1498 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1499 int err; 1500 1501 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1502 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1503 err = mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1504 mlxsw_core->bus, 1505 mlxsw_core->bus_priv, true, 1506 devlink, extack); 1507 return err; 1508 } 1509 1510 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1511 struct devlink_flash_update_params *params, 1512 struct netlink_ext_ack *extack) 1513 { 1514 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1515 1516 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1517 } 1518 1519 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1520 const struct devlink_trap *trap, 1521 void *trap_ctx) 1522 { 1523 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1524 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1525 1526 if (!mlxsw_driver->trap_init) 1527 return -EOPNOTSUPP; 1528 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1529 } 1530 1531 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1532 const struct devlink_trap *trap, 1533 void *trap_ctx) 1534 { 1535 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1536 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1537 1538 if (!mlxsw_driver->trap_fini) 1539 return; 1540 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1541 } 1542 1543 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1544 const struct devlink_trap *trap, 1545 enum devlink_trap_action action, 1546 struct netlink_ext_ack *extack) 1547 { 1548 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1549 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1550 1551 if (!mlxsw_driver->trap_action_set) 1552 return -EOPNOTSUPP; 1553 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1554 } 1555 1556 static int 1557 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1558 const struct devlink_trap_group *group) 1559 { 1560 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1561 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1562 1563 if (!mlxsw_driver->trap_group_init) 1564 return -EOPNOTSUPP; 1565 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1566 } 1567 1568 static int 1569 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1570 const struct devlink_trap_group *group, 1571 const struct devlink_trap_policer *policer, 1572 struct netlink_ext_ack *extack) 1573 { 1574 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1575 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1576 1577 if (!mlxsw_driver->trap_group_set) 1578 return -EOPNOTSUPP; 1579 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1580 } 1581 1582 static int 1583 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1584 const struct devlink_trap_policer *policer) 1585 { 1586 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1587 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1588 1589 if (!mlxsw_driver->trap_policer_init) 1590 return -EOPNOTSUPP; 1591 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1592 } 1593 1594 static void 1595 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1596 const struct devlink_trap_policer *policer) 1597 { 1598 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1599 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1600 1601 if (!mlxsw_driver->trap_policer_fini) 1602 return; 1603 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1604 } 1605 1606 static int 1607 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1608 const struct devlink_trap_policer *policer, 1609 u64 rate, u64 burst, 1610 struct netlink_ext_ack *extack) 1611 { 1612 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1613 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1614 1615 if (!mlxsw_driver->trap_policer_set) 1616 return -EOPNOTSUPP; 1617 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1618 extack); 1619 } 1620 1621 static int 1622 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1623 const struct devlink_trap_policer *policer, 1624 u64 *p_drops) 1625 { 1626 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1627 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1628 1629 if (!mlxsw_driver->trap_policer_counter_get) 1630 return -EOPNOTSUPP; 1631 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1632 p_drops); 1633 } 1634 1635 static const struct devlink_ops mlxsw_devlink_ops = { 1636 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1637 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1638 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1639 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1640 .port_split = mlxsw_devlink_port_split, 1641 .port_unsplit = mlxsw_devlink_port_unsplit, 1642 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1643 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1644 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1645 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1646 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1647 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1648 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1649 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1650 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1651 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1652 .info_get = mlxsw_devlink_info_get, 1653 .flash_update = mlxsw_devlink_flash_update, 1654 .trap_init = mlxsw_devlink_trap_init, 1655 .trap_fini = mlxsw_devlink_trap_fini, 1656 .trap_action_set = mlxsw_devlink_trap_action_set, 1657 .trap_group_init = mlxsw_devlink_trap_group_init, 1658 .trap_group_set = mlxsw_devlink_trap_group_set, 1659 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1660 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1661 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1662 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1663 }; 1664 1665 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1666 { 1667 int err; 1668 1669 err = mlxsw_core_fw_params_register(mlxsw_core); 1670 if (err) 1671 return err; 1672 1673 if (mlxsw_core->driver->params_register) { 1674 err = mlxsw_core->driver->params_register(mlxsw_core); 1675 if (err) 1676 goto err_params_register; 1677 } 1678 return 0; 1679 1680 err_params_register: 1681 mlxsw_core_fw_params_unregister(mlxsw_core); 1682 return err; 1683 } 1684 1685 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1686 { 1687 mlxsw_core_fw_params_unregister(mlxsw_core); 1688 if (mlxsw_core->driver->params_register) 1689 mlxsw_core->driver->params_unregister(mlxsw_core); 1690 } 1691 1692 struct mlxsw_core_health_event { 1693 struct mlxsw_core *mlxsw_core; 1694 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1695 struct work_struct work; 1696 }; 1697 1698 static void mlxsw_core_health_event_work(struct work_struct *work) 1699 { 1700 struct mlxsw_core_health_event *event; 1701 struct mlxsw_core *mlxsw_core; 1702 1703 event = container_of(work, struct mlxsw_core_health_event, work); 1704 mlxsw_core = event->mlxsw_core; 1705 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1706 event->mfde_pl); 1707 kfree(event); 1708 } 1709 1710 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1711 char *mfde_pl, void *priv) 1712 { 1713 struct mlxsw_core_health_event *event; 1714 struct mlxsw_core *mlxsw_core = priv; 1715 1716 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1717 if (!event) 1718 return; 1719 event->mlxsw_core = mlxsw_core; 1720 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1721 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1722 mlxsw_core_schedule_work(&event->work); 1723 } 1724 1725 static const struct mlxsw_listener mlxsw_core_health_listener = 1726 MLXSW_CORE_EVENTL(mlxsw_core_health_listener_func, MFDE); 1727 1728 static int 1729 mlxsw_core_health_fw_fatal_dump_fatal_cause(const char *mfde_pl, 1730 struct devlink_fmsg *fmsg) 1731 { 1732 u32 val, tile_v; 1733 int err; 1734 1735 val = mlxsw_reg_mfde_fatal_cause_id_get(mfde_pl); 1736 err = devlink_fmsg_u32_pair_put(fmsg, "cause_id", val); 1737 if (err) 1738 return err; 1739 tile_v = mlxsw_reg_mfde_fatal_cause_tile_v_get(mfde_pl); 1740 if (tile_v) { 1741 val = mlxsw_reg_mfde_fatal_cause_tile_index_get(mfde_pl); 1742 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1743 if (err) 1744 return err; 1745 } 1746 1747 return 0; 1748 } 1749 1750 static int 1751 mlxsw_core_health_fw_fatal_dump_fw_assert(const char *mfde_pl, 1752 struct devlink_fmsg *fmsg) 1753 { 1754 u32 val, tile_v; 1755 int err; 1756 1757 val = mlxsw_reg_mfde_fw_assert_var0_get(mfde_pl); 1758 err = devlink_fmsg_u32_pair_put(fmsg, "var0", val); 1759 if (err) 1760 return err; 1761 val = mlxsw_reg_mfde_fw_assert_var1_get(mfde_pl); 1762 err = devlink_fmsg_u32_pair_put(fmsg, "var1", val); 1763 if (err) 1764 return err; 1765 val = mlxsw_reg_mfde_fw_assert_var2_get(mfde_pl); 1766 err = devlink_fmsg_u32_pair_put(fmsg, "var2", val); 1767 if (err) 1768 return err; 1769 val = mlxsw_reg_mfde_fw_assert_var3_get(mfde_pl); 1770 err = devlink_fmsg_u32_pair_put(fmsg, "var3", val); 1771 if (err) 1772 return err; 1773 val = mlxsw_reg_mfde_fw_assert_var4_get(mfde_pl); 1774 err = devlink_fmsg_u32_pair_put(fmsg, "var4", val); 1775 if (err) 1776 return err; 1777 val = mlxsw_reg_mfde_fw_assert_existptr_get(mfde_pl); 1778 err = devlink_fmsg_u32_pair_put(fmsg, "existptr", val); 1779 if (err) 1780 return err; 1781 val = mlxsw_reg_mfde_fw_assert_callra_get(mfde_pl); 1782 err = devlink_fmsg_u32_pair_put(fmsg, "callra", val); 1783 if (err) 1784 return err; 1785 val = mlxsw_reg_mfde_fw_assert_oe_get(mfde_pl); 1786 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1787 if (err) 1788 return err; 1789 tile_v = mlxsw_reg_mfde_fw_assert_tile_v_get(mfde_pl); 1790 if (tile_v) { 1791 val = mlxsw_reg_mfde_fw_assert_tile_index_get(mfde_pl); 1792 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1793 if (err) 1794 return err; 1795 } 1796 val = mlxsw_reg_mfde_fw_assert_ext_synd_get(mfde_pl); 1797 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", val); 1798 if (err) 1799 return err; 1800 1801 return 0; 1802 } 1803 1804 static int 1805 mlxsw_core_health_fw_fatal_dump_kvd_im_stop(const char *mfde_pl, 1806 struct devlink_fmsg *fmsg) 1807 { 1808 u32 val; 1809 int err; 1810 1811 val = mlxsw_reg_mfde_kvd_im_stop_oe_get(mfde_pl); 1812 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1813 if (err) 1814 return err; 1815 val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl); 1816 return devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1817 } 1818 1819 static int 1820 mlxsw_core_health_fw_fatal_dump_crspace_to(const char *mfde_pl, 1821 struct devlink_fmsg *fmsg) 1822 { 1823 u32 val; 1824 int err; 1825 1826 val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl); 1827 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1828 if (err) 1829 return err; 1830 val = mlxsw_reg_mfde_crspace_to_oe_get(mfde_pl); 1831 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1832 if (err) 1833 return err; 1834 val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl); 1835 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1836 if (err) 1837 return err; 1838 val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl); 1839 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1840 if (err) 1841 return err; 1842 1843 return 0; 1844 } 1845 1846 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1847 struct devlink_fmsg *fmsg, void *priv_ctx, 1848 struct netlink_ext_ack *extack) 1849 { 1850 char *mfde_pl = priv_ctx; 1851 char *val_str; 1852 u8 event_id; 1853 u32 val; 1854 int err; 1855 1856 if (!priv_ctx) 1857 /* User-triggered dumps are not possible */ 1858 return -EOPNOTSUPP; 1859 1860 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1861 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1862 if (err) 1863 return err; 1864 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1865 if (err) 1866 return err; 1867 1868 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1869 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1870 if (err) 1871 return err; 1872 switch (event_id) { 1873 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1874 val_str = "CR space timeout"; 1875 break; 1876 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1877 val_str = "KVD insertion machine stopped"; 1878 break; 1879 case MLXSW_REG_MFDE_EVENT_ID_TEST: 1880 val_str = "Test"; 1881 break; 1882 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1883 val_str = "FW assert"; 1884 break; 1885 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1886 val_str = "Fatal cause"; 1887 break; 1888 default: 1889 val_str = NULL; 1890 } 1891 if (val_str) { 1892 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1893 if (err) 1894 return err; 1895 } 1896 1897 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1898 if (err) 1899 return err; 1900 1901 err = devlink_fmsg_arr_pair_nest_start(fmsg, "severity"); 1902 if (err) 1903 return err; 1904 1905 val = mlxsw_reg_mfde_severity_get(mfde_pl); 1906 err = devlink_fmsg_u8_pair_put(fmsg, "id", val); 1907 if (err) 1908 return err; 1909 switch (val) { 1910 case MLXSW_REG_MFDE_SEVERITY_FATL: 1911 val_str = "Fatal"; 1912 break; 1913 case MLXSW_REG_MFDE_SEVERITY_NRML: 1914 val_str = "Normal"; 1915 break; 1916 case MLXSW_REG_MFDE_SEVERITY_INTR: 1917 val_str = "Debug"; 1918 break; 1919 default: 1920 val_str = NULL; 1921 } 1922 if (val_str) { 1923 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1924 if (err) 1925 return err; 1926 } 1927 1928 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1929 if (err) 1930 return err; 1931 1932 val = mlxsw_reg_mfde_method_get(mfde_pl); 1933 switch (val) { 1934 case MLXSW_REG_MFDE_METHOD_QUERY: 1935 val_str = "query"; 1936 break; 1937 case MLXSW_REG_MFDE_METHOD_WRITE: 1938 val_str = "write"; 1939 break; 1940 default: 1941 val_str = NULL; 1942 } 1943 if (val_str) { 1944 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 1945 if (err) 1946 return err; 1947 } 1948 1949 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 1950 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 1951 if (err) 1952 return err; 1953 1954 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 1955 switch (val) { 1956 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 1957 val_str = "mad"; 1958 break; 1959 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 1960 val_str = "emad"; 1961 break; 1962 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 1963 val_str = "cmdif"; 1964 break; 1965 default: 1966 val_str = NULL; 1967 } 1968 if (val_str) { 1969 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 1970 if (err) 1971 return err; 1972 } 1973 1974 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 1975 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 1976 if (err) 1977 return err; 1978 1979 switch (event_id) { 1980 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1981 return mlxsw_core_health_fw_fatal_dump_crspace_to(mfde_pl, 1982 fmsg); 1983 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1984 return mlxsw_core_health_fw_fatal_dump_kvd_im_stop(mfde_pl, 1985 fmsg); 1986 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1987 return mlxsw_core_health_fw_fatal_dump_fw_assert(mfde_pl, fmsg); 1988 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1989 return mlxsw_core_health_fw_fatal_dump_fatal_cause(mfde_pl, 1990 fmsg); 1991 } 1992 1993 return 0; 1994 } 1995 1996 static int 1997 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 1998 struct netlink_ext_ack *extack) 1999 { 2000 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 2001 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2002 int err; 2003 2004 /* Read the register first to make sure no other bits are changed. */ 2005 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2006 if (err) 2007 return err; 2008 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 2009 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2010 } 2011 2012 static const struct devlink_health_reporter_ops 2013 mlxsw_core_health_fw_fatal_ops = { 2014 .name = "fw_fatal", 2015 .dump = mlxsw_core_health_fw_fatal_dump, 2016 .test = mlxsw_core_health_fw_fatal_test, 2017 }; 2018 2019 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 2020 bool enable) 2021 { 2022 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2023 int err; 2024 2025 /* Read the register first to make sure no other bits are changed. */ 2026 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2027 if (err) 2028 return err; 2029 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 2030 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2031 } 2032 2033 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 2034 { 2035 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2036 struct devlink_health_reporter *fw_fatal; 2037 int err; 2038 2039 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2040 return 0; 2041 2042 fw_fatal = devlink_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 2043 0, mlxsw_core); 2044 if (IS_ERR(fw_fatal)) { 2045 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 2046 return PTR_ERR(fw_fatal); 2047 } 2048 mlxsw_core->health.fw_fatal = fw_fatal; 2049 2050 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2051 if (err) 2052 goto err_trap_register; 2053 2054 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 2055 if (err) 2056 goto err_fw_fatal_config; 2057 2058 return 0; 2059 2060 err_fw_fatal_config: 2061 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2062 err_trap_register: 2063 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2064 return err; 2065 } 2066 2067 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 2068 { 2069 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2070 return; 2071 2072 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 2073 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2074 /* Make sure there is no more event work scheduled */ 2075 mlxsw_core_flush_owq(); 2076 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2077 } 2078 2079 static void mlxsw_core_irq_event_handler_init(struct mlxsw_core *mlxsw_core) 2080 { 2081 INIT_LIST_HEAD(&mlxsw_core->irq_event_handler_list); 2082 mutex_init(&mlxsw_core->irq_event_handler_lock); 2083 } 2084 2085 static void mlxsw_core_irq_event_handler_fini(struct mlxsw_core *mlxsw_core) 2086 { 2087 mutex_destroy(&mlxsw_core->irq_event_handler_lock); 2088 WARN_ON(!list_empty(&mlxsw_core->irq_event_handler_list)); 2089 } 2090 2091 static int 2092 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2093 const struct mlxsw_bus *mlxsw_bus, 2094 void *bus_priv, bool reload, 2095 struct devlink *devlink, 2096 struct netlink_ext_ack *extack) 2097 { 2098 const char *device_kind = mlxsw_bus_info->device_kind; 2099 struct mlxsw_core *mlxsw_core; 2100 struct mlxsw_driver *mlxsw_driver; 2101 size_t alloc_size; 2102 int err; 2103 2104 mlxsw_driver = mlxsw_core_driver_get(device_kind); 2105 if (!mlxsw_driver) 2106 return -EINVAL; 2107 2108 if (!reload) { 2109 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 2110 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 2111 mlxsw_bus_info->dev); 2112 if (!devlink) { 2113 err = -ENOMEM; 2114 goto err_devlink_alloc; 2115 } 2116 devl_lock(devlink); 2117 } 2118 2119 mlxsw_core = devlink_priv(devlink); 2120 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 2121 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 2122 mlxsw_core->driver = mlxsw_driver; 2123 mlxsw_core->bus = mlxsw_bus; 2124 mlxsw_core->bus_priv = bus_priv; 2125 mlxsw_core->bus_info = mlxsw_bus_info; 2126 mlxsw_core_irq_event_handler_init(mlxsw_core); 2127 2128 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, 2129 &mlxsw_core->res); 2130 if (err) 2131 goto err_bus_init; 2132 2133 if (mlxsw_driver->resources_register && !reload) { 2134 err = mlxsw_driver->resources_register(mlxsw_core); 2135 if (err) 2136 goto err_register_resources; 2137 } 2138 2139 err = mlxsw_ports_init(mlxsw_core, reload); 2140 if (err) 2141 goto err_ports_init; 2142 2143 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) && 2144 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 2145 alloc_size = sizeof(*mlxsw_core->lag.mapping) * 2146 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * 2147 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 2148 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 2149 if (!mlxsw_core->lag.mapping) { 2150 err = -ENOMEM; 2151 goto err_alloc_lag_mapping; 2152 } 2153 } 2154 2155 err = mlxsw_core_trap_groups_set(mlxsw_core); 2156 if (err) 2157 goto err_trap_groups_set; 2158 2159 err = mlxsw_emad_init(mlxsw_core); 2160 if (err) 2161 goto err_emad_init; 2162 2163 if (!reload) { 2164 err = mlxsw_core_params_register(mlxsw_core); 2165 if (err) 2166 goto err_register_params; 2167 } 2168 2169 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 2170 mlxsw_driver->fw_filename); 2171 if (err) 2172 goto err_fw_rev_validate; 2173 2174 err = mlxsw_linecards_init(mlxsw_core, mlxsw_bus_info); 2175 if (err) 2176 goto err_linecards_init; 2177 2178 err = mlxsw_core_health_init(mlxsw_core); 2179 if (err) 2180 goto err_health_init; 2181 2182 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 2183 if (err) 2184 goto err_hwmon_init; 2185 2186 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 2187 &mlxsw_core->thermal); 2188 if (err) 2189 goto err_thermal_init; 2190 2191 err = mlxsw_env_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->env); 2192 if (err) 2193 goto err_env_init; 2194 2195 if (mlxsw_driver->init) { 2196 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2197 if (err) 2198 goto err_driver_init; 2199 } 2200 2201 if (!reload) { 2202 devlink_set_features(devlink, DEVLINK_F_RELOAD); 2203 devl_unlock(devlink); 2204 devlink_register(devlink); 2205 } 2206 return 0; 2207 2208 err_driver_init: 2209 mlxsw_env_fini(mlxsw_core->env); 2210 err_env_init: 2211 mlxsw_thermal_fini(mlxsw_core->thermal); 2212 err_thermal_init: 2213 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2214 err_hwmon_init: 2215 mlxsw_core_health_fini(mlxsw_core); 2216 err_health_init: 2217 mlxsw_linecards_fini(mlxsw_core); 2218 err_linecards_init: 2219 err_fw_rev_validate: 2220 if (!reload) 2221 mlxsw_core_params_unregister(mlxsw_core); 2222 err_register_params: 2223 mlxsw_emad_fini(mlxsw_core); 2224 err_emad_init: 2225 err_trap_groups_set: 2226 kfree(mlxsw_core->lag.mapping); 2227 err_alloc_lag_mapping: 2228 mlxsw_ports_fini(mlxsw_core, reload); 2229 err_ports_init: 2230 if (!reload) 2231 devl_resources_unregister(devlink); 2232 err_register_resources: 2233 mlxsw_bus->fini(bus_priv); 2234 err_bus_init: 2235 mlxsw_core_irq_event_handler_fini(mlxsw_core); 2236 if (!reload) { 2237 devl_unlock(devlink); 2238 devlink_free(devlink); 2239 } 2240 err_devlink_alloc: 2241 return err; 2242 } 2243 2244 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2245 const struct mlxsw_bus *mlxsw_bus, 2246 void *bus_priv, bool reload, 2247 struct devlink *devlink, 2248 struct netlink_ext_ack *extack) 2249 { 2250 bool called_again = false; 2251 int err; 2252 2253 again: 2254 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2255 bus_priv, reload, 2256 devlink, extack); 2257 /* -EAGAIN is returned in case the FW was updated. FW needs 2258 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2259 * again. 2260 */ 2261 if (err == -EAGAIN && !called_again) { 2262 called_again = true; 2263 goto again; 2264 } 2265 2266 return err; 2267 } 2268 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2269 2270 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2271 bool reload) 2272 { 2273 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2274 2275 if (!reload) { 2276 devlink_unregister(devlink); 2277 devl_lock(devlink); 2278 } 2279 2280 if (devlink_is_reload_failed(devlink)) { 2281 if (!reload) 2282 /* Only the parts that were not de-initialized in the 2283 * failed reload attempt need to be de-initialized. 2284 */ 2285 goto reload_fail_deinit; 2286 else 2287 return; 2288 } 2289 2290 if (mlxsw_core->driver->fini) 2291 mlxsw_core->driver->fini(mlxsw_core); 2292 mlxsw_env_fini(mlxsw_core->env); 2293 mlxsw_thermal_fini(mlxsw_core->thermal); 2294 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2295 mlxsw_core_health_fini(mlxsw_core); 2296 mlxsw_linecards_fini(mlxsw_core); 2297 if (!reload) 2298 mlxsw_core_params_unregister(mlxsw_core); 2299 mlxsw_emad_fini(mlxsw_core); 2300 kfree(mlxsw_core->lag.mapping); 2301 mlxsw_ports_fini(mlxsw_core, reload); 2302 if (!reload) 2303 devl_resources_unregister(devlink); 2304 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2305 mlxsw_core_irq_event_handler_fini(mlxsw_core); 2306 if (!reload) { 2307 devl_unlock(devlink); 2308 devlink_free(devlink); 2309 } 2310 2311 return; 2312 2313 reload_fail_deinit: 2314 mlxsw_core_params_unregister(mlxsw_core); 2315 devl_resources_unregister(devlink); 2316 devl_unlock(devlink); 2317 devlink_free(devlink); 2318 } 2319 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2320 2321 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2322 const struct mlxsw_tx_info *tx_info) 2323 { 2324 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2325 tx_info); 2326 } 2327 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2328 2329 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2330 const struct mlxsw_tx_info *tx_info) 2331 { 2332 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2333 tx_info); 2334 } 2335 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2336 2337 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2338 struct sk_buff *skb, u16 local_port) 2339 { 2340 if (mlxsw_core->driver->ptp_transmitted) 2341 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2342 local_port); 2343 } 2344 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2345 2346 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2347 const struct mlxsw_rx_listener *rxl_b) 2348 { 2349 return (rxl_a->func == rxl_b->func && 2350 rxl_a->local_port == rxl_b->local_port && 2351 rxl_a->trap_id == rxl_b->trap_id && 2352 rxl_a->mirror_reason == rxl_b->mirror_reason); 2353 } 2354 2355 static struct mlxsw_rx_listener_item * 2356 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2357 const struct mlxsw_rx_listener *rxl) 2358 { 2359 struct mlxsw_rx_listener_item *rxl_item; 2360 2361 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2362 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2363 return rxl_item; 2364 } 2365 return NULL; 2366 } 2367 2368 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2369 const struct mlxsw_rx_listener *rxl, 2370 void *priv, bool enabled) 2371 { 2372 struct mlxsw_rx_listener_item *rxl_item; 2373 2374 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2375 if (rxl_item) 2376 return -EEXIST; 2377 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2378 if (!rxl_item) 2379 return -ENOMEM; 2380 rxl_item->rxl = *rxl; 2381 rxl_item->priv = priv; 2382 rxl_item->enabled = enabled; 2383 2384 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2385 return 0; 2386 } 2387 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2388 2389 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2390 const struct mlxsw_rx_listener *rxl) 2391 { 2392 struct mlxsw_rx_listener_item *rxl_item; 2393 2394 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2395 if (!rxl_item) 2396 return; 2397 list_del_rcu(&rxl_item->list); 2398 synchronize_rcu(); 2399 kfree(rxl_item); 2400 } 2401 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2402 2403 static void 2404 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2405 const struct mlxsw_rx_listener *rxl, 2406 bool enabled) 2407 { 2408 struct mlxsw_rx_listener_item *rxl_item; 2409 2410 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2411 if (WARN_ON(!rxl_item)) 2412 return; 2413 rxl_item->enabled = enabled; 2414 } 2415 2416 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u16 local_port, 2417 void *priv) 2418 { 2419 struct mlxsw_event_listener_item *event_listener_item = priv; 2420 struct mlxsw_core *mlxsw_core; 2421 struct mlxsw_reg_info reg; 2422 char *payload; 2423 char *reg_tlv; 2424 char *op_tlv; 2425 2426 mlxsw_core = event_listener_item->mlxsw_core; 2427 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2428 skb->data, skb->len); 2429 2430 mlxsw_emad_tlv_parse(skb); 2431 op_tlv = mlxsw_emad_op_tlv(skb); 2432 reg_tlv = mlxsw_emad_reg_tlv(skb); 2433 2434 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2435 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2436 payload = mlxsw_emad_reg_payload(reg_tlv); 2437 event_listener_item->el.func(®, payload, event_listener_item->priv); 2438 dev_kfree_skb(skb); 2439 } 2440 2441 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2442 const struct mlxsw_event_listener *el_b) 2443 { 2444 return (el_a->func == el_b->func && 2445 el_a->trap_id == el_b->trap_id); 2446 } 2447 2448 static struct mlxsw_event_listener_item * 2449 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2450 const struct mlxsw_event_listener *el) 2451 { 2452 struct mlxsw_event_listener_item *el_item; 2453 2454 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2455 if (__is_event_listener_equal(&el_item->el, el)) 2456 return el_item; 2457 } 2458 return NULL; 2459 } 2460 2461 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2462 const struct mlxsw_event_listener *el, 2463 void *priv) 2464 { 2465 int err; 2466 struct mlxsw_event_listener_item *el_item; 2467 const struct mlxsw_rx_listener rxl = { 2468 .func = mlxsw_core_event_listener_func, 2469 .local_port = MLXSW_PORT_DONT_CARE, 2470 .trap_id = el->trap_id, 2471 }; 2472 2473 el_item = __find_event_listener_item(mlxsw_core, el); 2474 if (el_item) 2475 return -EEXIST; 2476 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2477 if (!el_item) 2478 return -ENOMEM; 2479 el_item->mlxsw_core = mlxsw_core; 2480 el_item->el = *el; 2481 el_item->priv = priv; 2482 2483 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2484 if (err) 2485 goto err_rx_listener_register; 2486 2487 /* No reason to save item if we did not manage to register an RX 2488 * listener for it. 2489 */ 2490 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2491 2492 return 0; 2493 2494 err_rx_listener_register: 2495 kfree(el_item); 2496 return err; 2497 } 2498 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2499 2500 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2501 const struct mlxsw_event_listener *el) 2502 { 2503 struct mlxsw_event_listener_item *el_item; 2504 const struct mlxsw_rx_listener rxl = { 2505 .func = mlxsw_core_event_listener_func, 2506 .local_port = MLXSW_PORT_DONT_CARE, 2507 .trap_id = el->trap_id, 2508 }; 2509 2510 el_item = __find_event_listener_item(mlxsw_core, el); 2511 if (!el_item) 2512 return; 2513 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2514 list_del(&el_item->list); 2515 kfree(el_item); 2516 } 2517 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2518 2519 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2520 const struct mlxsw_listener *listener, 2521 void *priv, bool enabled) 2522 { 2523 if (listener->is_event) { 2524 WARN_ON(!enabled); 2525 return mlxsw_core_event_listener_register(mlxsw_core, 2526 &listener->event_listener, 2527 priv); 2528 } else { 2529 return mlxsw_core_rx_listener_register(mlxsw_core, 2530 &listener->rx_listener, 2531 priv, enabled); 2532 } 2533 } 2534 2535 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2536 const struct mlxsw_listener *listener, 2537 void *priv) 2538 { 2539 if (listener->is_event) 2540 mlxsw_core_event_listener_unregister(mlxsw_core, 2541 &listener->event_listener); 2542 else 2543 mlxsw_core_rx_listener_unregister(mlxsw_core, 2544 &listener->rx_listener); 2545 } 2546 2547 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2548 const struct mlxsw_listener *listener, void *priv) 2549 { 2550 enum mlxsw_reg_htgt_trap_group trap_group; 2551 enum mlxsw_reg_hpkt_action action; 2552 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2553 int err; 2554 2555 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2556 return 0; 2557 2558 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2559 listener->enabled_on_register); 2560 if (err) 2561 return err; 2562 2563 action = listener->enabled_on_register ? listener->en_action : 2564 listener->dis_action; 2565 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2566 listener->dis_trap_group; 2567 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2568 trap_group, listener->is_ctrl); 2569 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2570 if (err) 2571 goto err_trap_set; 2572 2573 return 0; 2574 2575 err_trap_set: 2576 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2577 return err; 2578 } 2579 EXPORT_SYMBOL(mlxsw_core_trap_register); 2580 2581 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2582 const struct mlxsw_listener *listener, 2583 void *priv) 2584 { 2585 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2586 2587 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2588 return; 2589 2590 if (!listener->is_event) { 2591 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2592 listener->trap_id, listener->dis_trap_group, 2593 listener->is_ctrl); 2594 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2595 } 2596 2597 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2598 } 2599 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2600 2601 int mlxsw_core_traps_register(struct mlxsw_core *mlxsw_core, 2602 const struct mlxsw_listener *listeners, 2603 size_t listeners_count, void *priv) 2604 { 2605 int i, err; 2606 2607 for (i = 0; i < listeners_count; i++) { 2608 err = mlxsw_core_trap_register(mlxsw_core, 2609 &listeners[i], 2610 priv); 2611 if (err) 2612 goto err_listener_register; 2613 } 2614 return 0; 2615 2616 err_listener_register: 2617 for (i--; i >= 0; i--) { 2618 mlxsw_core_trap_unregister(mlxsw_core, 2619 &listeners[i], 2620 priv); 2621 } 2622 return err; 2623 } 2624 EXPORT_SYMBOL(mlxsw_core_traps_register); 2625 2626 void mlxsw_core_traps_unregister(struct mlxsw_core *mlxsw_core, 2627 const struct mlxsw_listener *listeners, 2628 size_t listeners_count, void *priv) 2629 { 2630 int i; 2631 2632 for (i = 0; i < listeners_count; i++) { 2633 mlxsw_core_trap_unregister(mlxsw_core, 2634 &listeners[i], 2635 priv); 2636 } 2637 } 2638 EXPORT_SYMBOL(mlxsw_core_traps_unregister); 2639 2640 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2641 const struct mlxsw_listener *listener, 2642 bool enabled) 2643 { 2644 enum mlxsw_reg_htgt_trap_group trap_group; 2645 enum mlxsw_reg_hpkt_action action; 2646 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2647 int err; 2648 2649 /* Not supported for event listener */ 2650 if (WARN_ON(listener->is_event)) 2651 return -EINVAL; 2652 2653 action = enabled ? listener->en_action : listener->dis_action; 2654 trap_group = enabled ? listener->en_trap_group : 2655 listener->dis_trap_group; 2656 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2657 trap_group, listener->is_ctrl); 2658 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2659 if (err) 2660 return err; 2661 2662 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2663 enabled); 2664 return 0; 2665 } 2666 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2667 2668 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2669 { 2670 return atomic64_inc_return(&mlxsw_core->emad.tid); 2671 } 2672 2673 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2674 const struct mlxsw_reg_info *reg, 2675 char *payload, 2676 enum mlxsw_core_reg_access_type type, 2677 struct list_head *bulk_list, 2678 mlxsw_reg_trans_cb_t *cb, 2679 unsigned long cb_priv) 2680 { 2681 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2682 struct mlxsw_reg_trans *trans; 2683 int err; 2684 2685 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2686 if (!trans) 2687 return -ENOMEM; 2688 2689 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2690 bulk_list, cb, cb_priv, tid); 2691 if (err) { 2692 kfree_rcu(trans, rcu); 2693 return err; 2694 } 2695 return 0; 2696 } 2697 2698 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2699 const struct mlxsw_reg_info *reg, char *payload, 2700 struct list_head *bulk_list, 2701 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2702 { 2703 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2704 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2705 bulk_list, cb, cb_priv); 2706 } 2707 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2708 2709 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2710 const struct mlxsw_reg_info *reg, char *payload, 2711 struct list_head *bulk_list, 2712 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2713 { 2714 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2715 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2716 bulk_list, cb, cb_priv); 2717 } 2718 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2719 2720 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2721 2722 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2723 { 2724 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2725 struct mlxsw_core *mlxsw_core = trans->core; 2726 int err; 2727 2728 wait_for_completion(&trans->completion); 2729 cancel_delayed_work_sync(&trans->timeout_dw); 2730 err = trans->err; 2731 2732 if (trans->retries) 2733 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2734 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2735 if (err) { 2736 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2737 trans->tid, trans->reg->id, 2738 mlxsw_reg_id_str(trans->reg->id), 2739 mlxsw_core_reg_access_type_str(trans->type), 2740 trans->emad_status, 2741 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2742 2743 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2744 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2745 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2746 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2747 trans->emad_err_string ? trans->emad_err_string : ""); 2748 2749 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2750 trans->emad_status, err_string); 2751 2752 kfree(trans->emad_err_string); 2753 } 2754 2755 list_del(&trans->bulk_list); 2756 kfree_rcu(trans, rcu); 2757 return err; 2758 } 2759 2760 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2761 { 2762 struct mlxsw_reg_trans *trans; 2763 struct mlxsw_reg_trans *tmp; 2764 int sum_err = 0; 2765 int err; 2766 2767 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2768 err = mlxsw_reg_trans_wait(trans); 2769 if (err && sum_err == 0) 2770 sum_err = err; /* first error to be returned */ 2771 } 2772 return sum_err; 2773 } 2774 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2775 2776 struct mlxsw_core_irq_event_handler_item { 2777 struct list_head list; 2778 void (*cb)(struct mlxsw_core *mlxsw_core); 2779 }; 2780 2781 int mlxsw_core_irq_event_handler_register(struct mlxsw_core *mlxsw_core, 2782 mlxsw_irq_event_cb_t cb) 2783 { 2784 struct mlxsw_core_irq_event_handler_item *item; 2785 2786 item = kzalloc(sizeof(*item), GFP_KERNEL); 2787 if (!item) 2788 return -ENOMEM; 2789 item->cb = cb; 2790 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2791 list_add_tail(&item->list, &mlxsw_core->irq_event_handler_list); 2792 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2793 return 0; 2794 } 2795 EXPORT_SYMBOL(mlxsw_core_irq_event_handler_register); 2796 2797 void mlxsw_core_irq_event_handler_unregister(struct mlxsw_core *mlxsw_core, 2798 mlxsw_irq_event_cb_t cb) 2799 { 2800 struct mlxsw_core_irq_event_handler_item *item, *tmp; 2801 2802 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2803 list_for_each_entry_safe(item, tmp, 2804 &mlxsw_core->irq_event_handler_list, list) { 2805 if (item->cb == cb) { 2806 list_del(&item->list); 2807 kfree(item); 2808 } 2809 } 2810 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2811 } 2812 EXPORT_SYMBOL(mlxsw_core_irq_event_handler_unregister); 2813 2814 void mlxsw_core_irq_event_handlers_call(struct mlxsw_core *mlxsw_core) 2815 { 2816 struct mlxsw_core_irq_event_handler_item *item; 2817 2818 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2819 list_for_each_entry(item, &mlxsw_core->irq_event_handler_list, list) { 2820 if (item->cb) 2821 item->cb(mlxsw_core); 2822 } 2823 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2824 } 2825 EXPORT_SYMBOL(mlxsw_core_irq_event_handlers_call); 2826 2827 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2828 const struct mlxsw_reg_info *reg, 2829 char *payload, 2830 enum mlxsw_core_reg_access_type type) 2831 { 2832 enum mlxsw_emad_op_tlv_status status; 2833 int err, n_retry; 2834 bool reset_ok; 2835 char *in_mbox, *out_mbox, *tmp; 2836 2837 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2838 reg->id, mlxsw_reg_id_str(reg->id), 2839 mlxsw_core_reg_access_type_str(type)); 2840 2841 in_mbox = mlxsw_cmd_mbox_alloc(); 2842 if (!in_mbox) 2843 return -ENOMEM; 2844 2845 out_mbox = mlxsw_cmd_mbox_alloc(); 2846 if (!out_mbox) { 2847 err = -ENOMEM; 2848 goto free_in_mbox; 2849 } 2850 2851 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2852 mlxsw_core_tid_get(mlxsw_core)); 2853 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2854 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2855 2856 /* There is a special treatment needed for MRSR (reset) register. 2857 * The command interface will return error after the command 2858 * is executed, so tell the lower layer to expect it 2859 * and cope accordingly. 2860 */ 2861 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2862 2863 n_retry = 0; 2864 retry: 2865 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2866 if (!err) { 2867 err = mlxsw_emad_process_status(out_mbox, &status); 2868 if (err) { 2869 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2870 goto retry; 2871 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2872 status, mlxsw_emad_op_tlv_status_str(status)); 2873 } 2874 } 2875 2876 if (!err) 2877 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2878 reg->len); 2879 2880 mlxsw_cmd_mbox_free(out_mbox); 2881 free_in_mbox: 2882 mlxsw_cmd_mbox_free(in_mbox); 2883 if (err) 2884 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2885 reg->id, mlxsw_reg_id_str(reg->id), 2886 mlxsw_core_reg_access_type_str(type)); 2887 return err; 2888 } 2889 2890 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2891 char *payload, size_t payload_len, 2892 unsigned long cb_priv) 2893 { 2894 char *orig_payload = (char *) cb_priv; 2895 2896 memcpy(orig_payload, payload, payload_len); 2897 } 2898 2899 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2900 const struct mlxsw_reg_info *reg, 2901 char *payload, 2902 enum mlxsw_core_reg_access_type type) 2903 { 2904 LIST_HEAD(bulk_list); 2905 int err; 2906 2907 /* During initialization EMAD interface is not available to us, 2908 * so we default to command interface. We switch to EMAD interface 2909 * after setting the appropriate traps. 2910 */ 2911 if (!mlxsw_core->emad.use_emad) 2912 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2913 payload, type); 2914 2915 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 2916 payload, type, &bulk_list, 2917 mlxsw_core_reg_access_cb, 2918 (unsigned long) payload); 2919 if (err) 2920 return err; 2921 return mlxsw_reg_trans_bulk_wait(&bulk_list); 2922 } 2923 2924 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 2925 const struct mlxsw_reg_info *reg, char *payload) 2926 { 2927 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2928 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 2929 } 2930 EXPORT_SYMBOL(mlxsw_reg_query); 2931 2932 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 2933 const struct mlxsw_reg_info *reg, char *payload) 2934 { 2935 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2936 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 2937 } 2938 EXPORT_SYMBOL(mlxsw_reg_write); 2939 2940 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2941 struct mlxsw_rx_info *rx_info) 2942 { 2943 struct mlxsw_rx_listener_item *rxl_item; 2944 const struct mlxsw_rx_listener *rxl; 2945 u16 local_port; 2946 bool found = false; 2947 2948 if (rx_info->is_lag) { 2949 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 2950 __func__, rx_info->u.lag_id, 2951 rx_info->trap_id); 2952 /* Upper layer does not care if the skb came from LAG or not, 2953 * so just get the local_port for the lag port and push it up. 2954 */ 2955 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 2956 rx_info->u.lag_id, 2957 rx_info->lag_port_index); 2958 } else { 2959 local_port = rx_info->u.sys_port; 2960 } 2961 2962 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 2963 __func__, local_port, rx_info->trap_id); 2964 2965 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 2966 (local_port >= mlxsw_core->max_ports)) 2967 goto drop; 2968 2969 rcu_read_lock(); 2970 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 2971 rxl = &rxl_item->rxl; 2972 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 2973 rxl->local_port == local_port) && 2974 rxl->trap_id == rx_info->trap_id && 2975 rxl->mirror_reason == rx_info->mirror_reason) { 2976 if (rxl_item->enabled) 2977 found = true; 2978 break; 2979 } 2980 } 2981 if (!found) { 2982 rcu_read_unlock(); 2983 goto drop; 2984 } 2985 2986 rxl->func(skb, local_port, rxl_item->priv); 2987 rcu_read_unlock(); 2988 return; 2989 2990 drop: 2991 dev_kfree_skb(skb); 2992 } 2993 EXPORT_SYMBOL(mlxsw_core_skb_receive); 2994 2995 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 2996 u16 lag_id, u8 port_index) 2997 { 2998 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 2999 port_index; 3000 } 3001 3002 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 3003 u16 lag_id, u8 port_index, u16 local_port) 3004 { 3005 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3006 lag_id, port_index); 3007 3008 mlxsw_core->lag.mapping[index] = local_port; 3009 } 3010 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 3011 3012 u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 3013 u16 lag_id, u8 port_index) 3014 { 3015 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3016 lag_id, port_index); 3017 3018 return mlxsw_core->lag.mapping[index]; 3019 } 3020 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 3021 3022 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 3023 u16 lag_id, u16 local_port) 3024 { 3025 int i; 3026 3027 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 3028 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3029 lag_id, i); 3030 3031 if (mlxsw_core->lag.mapping[index] == local_port) 3032 mlxsw_core->lag.mapping[index] = 0; 3033 } 3034 } 3035 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 3036 3037 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 3038 enum mlxsw_res_id res_id) 3039 { 3040 return mlxsw_res_valid(&mlxsw_core->res, res_id); 3041 } 3042 EXPORT_SYMBOL(mlxsw_core_res_valid); 3043 3044 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 3045 enum mlxsw_res_id res_id) 3046 { 3047 return mlxsw_res_get(&mlxsw_core->res, res_id); 3048 } 3049 EXPORT_SYMBOL(mlxsw_core_res_get); 3050 3051 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3052 enum devlink_port_flavour flavour, 3053 u8 slot_index, u32 port_number, bool split, 3054 u32 split_port_subnumber, 3055 bool splittable, u32 lanes, 3056 const unsigned char *switch_id, 3057 unsigned char switch_id_len) 3058 { 3059 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3060 struct mlxsw_core_port *mlxsw_core_port = 3061 &mlxsw_core->ports[local_port]; 3062 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3063 struct devlink_port_attrs attrs = {}; 3064 int err; 3065 3066 attrs.split = split; 3067 attrs.lanes = lanes; 3068 attrs.splittable = splittable; 3069 attrs.flavour = flavour; 3070 attrs.phys.port_number = port_number; 3071 attrs.phys.split_subport_number = split_port_subnumber; 3072 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 3073 attrs.switch_id.id_len = switch_id_len; 3074 mlxsw_core_port->local_port = local_port; 3075 devlink_port_attrs_set(devlink_port, &attrs); 3076 if (slot_index) { 3077 struct mlxsw_linecard *linecard; 3078 3079 linecard = mlxsw_linecard_get(mlxsw_core->linecards, 3080 slot_index); 3081 mlxsw_core_port->linecard = linecard; 3082 devlink_port_linecard_set(devlink_port, 3083 linecard->devlink_linecard); 3084 } 3085 err = devl_port_register(devlink, devlink_port, local_port); 3086 if (err) 3087 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3088 return err; 3089 } 3090 3091 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3092 { 3093 struct mlxsw_core_port *mlxsw_core_port = 3094 &mlxsw_core->ports[local_port]; 3095 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3096 3097 devl_port_unregister(devlink_port); 3098 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3099 } 3100 3101 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3102 u8 slot_index, u32 port_number, bool split, 3103 u32 split_port_subnumber, 3104 bool splittable, u32 lanes, 3105 const unsigned char *switch_id, 3106 unsigned char switch_id_len) 3107 { 3108 int err; 3109 3110 err = __mlxsw_core_port_init(mlxsw_core, local_port, 3111 DEVLINK_PORT_FLAVOUR_PHYSICAL, slot_index, 3112 port_number, split, split_port_subnumber, 3113 splittable, lanes, 3114 switch_id, switch_id_len); 3115 if (err) 3116 return err; 3117 3118 atomic_inc(&mlxsw_core->active_ports_count); 3119 return 0; 3120 } 3121 EXPORT_SYMBOL(mlxsw_core_port_init); 3122 3123 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3124 { 3125 atomic_dec(&mlxsw_core->active_ports_count); 3126 3127 __mlxsw_core_port_fini(mlxsw_core, local_port); 3128 } 3129 EXPORT_SYMBOL(mlxsw_core_port_fini); 3130 3131 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 3132 void *port_driver_priv, 3133 const unsigned char *switch_id, 3134 unsigned char switch_id_len) 3135 { 3136 struct mlxsw_core_port *mlxsw_core_port = 3137 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 3138 int err; 3139 3140 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 3141 DEVLINK_PORT_FLAVOUR_CPU, 3142 0, 0, false, 0, false, 0, 3143 switch_id, switch_id_len); 3144 if (err) 3145 return err; 3146 3147 mlxsw_core_port->port_driver_priv = port_driver_priv; 3148 return 0; 3149 } 3150 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 3151 3152 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 3153 { 3154 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 3155 } 3156 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 3157 3158 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3159 void *port_driver_priv, struct net_device *dev) 3160 { 3161 struct mlxsw_core_port *mlxsw_core_port = 3162 &mlxsw_core->ports[local_port]; 3163 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3164 3165 mlxsw_core_port->port_driver_priv = port_driver_priv; 3166 devlink_port_type_eth_set(devlink_port, dev); 3167 } 3168 EXPORT_SYMBOL(mlxsw_core_port_eth_set); 3169 3170 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port, 3171 void *port_driver_priv) 3172 { 3173 struct mlxsw_core_port *mlxsw_core_port = 3174 &mlxsw_core->ports[local_port]; 3175 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3176 3177 mlxsw_core_port->port_driver_priv = port_driver_priv; 3178 devlink_port_type_clear(devlink_port); 3179 } 3180 EXPORT_SYMBOL(mlxsw_core_port_clear); 3181 3182 struct devlink_port * 3183 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 3184 u16 local_port) 3185 { 3186 struct mlxsw_core_port *mlxsw_core_port = 3187 &mlxsw_core->ports[local_port]; 3188 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3189 3190 return devlink_port; 3191 } 3192 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 3193 3194 struct mlxsw_linecard * 3195 mlxsw_core_port_linecard_get(struct mlxsw_core *mlxsw_core, 3196 u16 local_port) 3197 { 3198 struct mlxsw_core_port *mlxsw_core_port = 3199 &mlxsw_core->ports[local_port]; 3200 3201 return mlxsw_core_port->linecard; 3202 } 3203 3204 void mlxsw_core_ports_remove_selected(struct mlxsw_core *mlxsw_core, 3205 bool (*selector)(void *priv, u16 local_port), 3206 void *priv) 3207 { 3208 if (WARN_ON_ONCE(!mlxsw_core->driver->ports_remove_selected)) 3209 return; 3210 mlxsw_core->driver->ports_remove_selected(mlxsw_core, selector, priv); 3211 } 3212 3213 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 3214 { 3215 return mlxsw_core->env; 3216 } 3217 3218 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 3219 const char *buf, size_t size) 3220 { 3221 __be32 *m = (__be32 *) buf; 3222 int i; 3223 int count = size / sizeof(__be32); 3224 3225 for (i = count - 1; i >= 0; i--) 3226 if (m[i]) 3227 break; 3228 i++; 3229 count = i ? i : 1; 3230 for (i = 0; i < count; i += 4) 3231 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 3232 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 3233 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 3234 } 3235 3236 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 3237 u32 in_mod, bool out_mbox_direct, bool reset_ok, 3238 char *in_mbox, size_t in_mbox_size, 3239 char *out_mbox, size_t out_mbox_size) 3240 { 3241 u8 status; 3242 int err; 3243 3244 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 3245 if (!mlxsw_core->bus->cmd_exec) 3246 return -EOPNOTSUPP; 3247 3248 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3249 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 3250 if (in_mbox) { 3251 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 3252 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 3253 } 3254 3255 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 3256 opcode_mod, in_mod, out_mbox_direct, 3257 in_mbox, in_mbox_size, 3258 out_mbox, out_mbox_size, &status); 3259 3260 if (!err && out_mbox) { 3261 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 3262 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 3263 } 3264 3265 if (reset_ok && err == -EIO && 3266 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 3267 err = 0; 3268 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 3269 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 3270 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3271 in_mod, status, mlxsw_cmd_status_str(status)); 3272 } else if (err == -ETIMEDOUT) { 3273 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3274 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3275 in_mod); 3276 } 3277 3278 return err; 3279 } 3280 EXPORT_SYMBOL(mlxsw_cmd_exec); 3281 3282 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 3283 { 3284 return queue_delayed_work(mlxsw_wq, dwork, delay); 3285 } 3286 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 3287 3288 bool mlxsw_core_schedule_work(struct work_struct *work) 3289 { 3290 return queue_work(mlxsw_owq, work); 3291 } 3292 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3293 3294 void mlxsw_core_flush_owq(void) 3295 { 3296 flush_workqueue(mlxsw_owq); 3297 } 3298 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3299 3300 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3301 const struct mlxsw_config_profile *profile, 3302 u64 *p_single_size, u64 *p_double_size, 3303 u64 *p_linear_size) 3304 { 3305 struct mlxsw_driver *driver = mlxsw_core->driver; 3306 3307 if (!driver->kvd_sizes_get) 3308 return -EINVAL; 3309 3310 return driver->kvd_sizes_get(mlxsw_core, profile, 3311 p_single_size, p_double_size, 3312 p_linear_size); 3313 } 3314 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3315 3316 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3317 struct mlxsw_res *res) 3318 { 3319 int index, i; 3320 u64 data; 3321 u16 id; 3322 int err; 3323 3324 mlxsw_cmd_mbox_zero(mbox); 3325 3326 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3327 index++) { 3328 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3329 if (err) 3330 return err; 3331 3332 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3333 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3334 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3335 3336 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3337 return 0; 3338 3339 mlxsw_res_parse(res, id, data); 3340 } 3341 } 3342 3343 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3344 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3345 */ 3346 return -EIO; 3347 } 3348 EXPORT_SYMBOL(mlxsw_core_resources_query); 3349 3350 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3351 { 3352 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3353 } 3354 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3355 3356 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3357 { 3358 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3359 } 3360 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3361 3362 u32 mlxsw_core_read_utc_sec(struct mlxsw_core *mlxsw_core) 3363 { 3364 return mlxsw_core->bus->read_utc_sec(mlxsw_core->bus_priv); 3365 } 3366 EXPORT_SYMBOL(mlxsw_core_read_utc_sec); 3367 3368 u32 mlxsw_core_read_utc_nsec(struct mlxsw_core *mlxsw_core) 3369 { 3370 return mlxsw_core->bus->read_utc_nsec(mlxsw_core->bus_priv); 3371 } 3372 EXPORT_SYMBOL(mlxsw_core_read_utc_nsec); 3373 3374 bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core) 3375 { 3376 return mlxsw_core->driver->sdq_supports_cqe_v2; 3377 } 3378 EXPORT_SYMBOL(mlxsw_core_sdq_supports_cqe_v2); 3379 3380 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core) 3381 { 3382 mlxsw_core->emad.enable_string_tlv = true; 3383 } 3384 EXPORT_SYMBOL(mlxsw_core_emad_string_tlv_enable); 3385 3386 static int __init mlxsw_core_module_init(void) 3387 { 3388 int err; 3389 3390 err = mlxsw_linecard_driver_register(); 3391 if (err) 3392 return err; 3393 3394 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3395 if (!mlxsw_wq) { 3396 err = -ENOMEM; 3397 goto err_alloc_workqueue; 3398 } 3399 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3400 mlxsw_core_driver_name); 3401 if (!mlxsw_owq) { 3402 err = -ENOMEM; 3403 goto err_alloc_ordered_workqueue; 3404 } 3405 return 0; 3406 3407 err_alloc_ordered_workqueue: 3408 destroy_workqueue(mlxsw_wq); 3409 err_alloc_workqueue: 3410 mlxsw_linecard_driver_unregister(); 3411 return err; 3412 } 3413 3414 static void __exit mlxsw_core_module_exit(void) 3415 { 3416 destroy_workqueue(mlxsw_owq); 3417 destroy_workqueue(mlxsw_wq); 3418 mlxsw_linecard_driver_unregister(); 3419 } 3420 3421 module_init(mlxsw_core_module_init); 3422 module_exit(mlxsw_core_module_exit); 3423 3424 MODULE_LICENSE("Dual BSD/GPL"); 3425 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3426 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3427