1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u16 local_port; 51 struct mlxsw_linecard *linecard; 52 }; 53 54 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 55 { 56 return mlxsw_core_port->port_driver_priv; 57 } 58 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 59 60 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 61 { 62 return mlxsw_core_port->port_driver_priv != NULL; 63 } 64 65 struct mlxsw_core { 66 struct mlxsw_driver *driver; 67 const struct mlxsw_bus *bus; 68 void *bus_priv; 69 const struct mlxsw_bus_info *bus_info; 70 struct workqueue_struct *emad_wq; 71 struct list_head rx_listener_list; 72 struct list_head event_listener_list; 73 struct list_head irq_event_handler_list; 74 struct mutex irq_event_handler_lock; /* Locks access to handlers list */ 75 struct { 76 atomic64_t tid; 77 struct list_head trans_list; 78 spinlock_t trans_list_lock; /* protects trans_list writes */ 79 bool use_emad; 80 bool enable_string_tlv; 81 bool enable_latency_tlv; 82 } emad; 83 struct { 84 u16 *mapping; /* lag_id+port_index to local_port mapping */ 85 } lag; 86 struct mlxsw_res res; 87 struct mlxsw_hwmon *hwmon; 88 struct mlxsw_thermal *thermal; 89 struct mlxsw_linecards *linecards; 90 struct mlxsw_core_port *ports; 91 unsigned int max_ports; 92 atomic_t active_ports_count; 93 bool fw_flash_in_progress; 94 struct { 95 struct devlink_health_reporter *fw_fatal; 96 } health; 97 struct mlxsw_env *env; 98 unsigned long driver_priv[]; 99 /* driver_priv has to be always the last item */ 100 }; 101 102 struct mlxsw_linecards *mlxsw_core_linecards(struct mlxsw_core *mlxsw_core) 103 { 104 return mlxsw_core->linecards; 105 } 106 107 void mlxsw_core_linecards_set(struct mlxsw_core *mlxsw_core, 108 struct mlxsw_linecards *linecards) 109 { 110 mlxsw_core->linecards = linecards; 111 } 112 113 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 114 115 static u64 mlxsw_ports_occ_get(void *priv) 116 { 117 struct mlxsw_core *mlxsw_core = priv; 118 119 return atomic_read(&mlxsw_core->active_ports_count); 120 } 121 122 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 123 { 124 struct devlink *devlink = priv_to_devlink(mlxsw_core); 125 struct devlink_resource_size_params ports_num_params; 126 u32 max_ports; 127 128 max_ports = mlxsw_core->max_ports - 1; 129 devlink_resource_size_params_init(&ports_num_params, max_ports, 130 max_ports, 1, 131 DEVLINK_RESOURCE_UNIT_ENTRY); 132 133 return devl_resource_register(devlink, 134 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 135 max_ports, MLXSW_CORE_RESOURCE_PORTS, 136 DEVLINK_RESOURCE_ID_PARENT_TOP, 137 &ports_num_params); 138 } 139 140 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 141 { 142 struct devlink *devlink = priv_to_devlink(mlxsw_core); 143 int err; 144 145 /* Switch ports are numbered from 1 to queried value */ 146 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 147 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 148 MAX_SYSTEM_PORT) + 1; 149 else 150 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 151 152 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 153 sizeof(struct mlxsw_core_port), GFP_KERNEL); 154 if (!mlxsw_core->ports) 155 return -ENOMEM; 156 157 if (!reload) { 158 err = mlxsw_core_resources_ports_register(mlxsw_core); 159 if (err) 160 goto err_resources_ports_register; 161 } 162 atomic_set(&mlxsw_core->active_ports_count, 0); 163 devl_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 164 mlxsw_ports_occ_get, mlxsw_core); 165 166 return 0; 167 168 err_resources_ports_register: 169 kfree(mlxsw_core->ports); 170 return err; 171 } 172 173 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 174 { 175 struct devlink *devlink = priv_to_devlink(mlxsw_core); 176 177 devl_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 178 if (!reload) 179 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 180 181 kfree(mlxsw_core->ports); 182 } 183 184 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 185 { 186 return mlxsw_core->max_ports; 187 } 188 EXPORT_SYMBOL(mlxsw_core_max_ports); 189 190 int mlxsw_core_max_lag(struct mlxsw_core *mlxsw_core, u16 *p_max_lag) 191 { 192 struct mlxsw_driver *driver = mlxsw_core->driver; 193 194 if (driver->profile->used_max_lag) { 195 *p_max_lag = driver->profile->max_lag; 196 return 0; 197 } 198 199 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG)) 200 return -EIO; 201 202 *p_max_lag = MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG); 203 return 0; 204 } 205 EXPORT_SYMBOL(mlxsw_core_max_lag); 206 207 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 208 { 209 return mlxsw_core->driver_priv; 210 } 211 EXPORT_SYMBOL(mlxsw_core_driver_priv); 212 213 bool 214 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 215 const struct mlxsw_fw_rev *req_rev) 216 { 217 return rev->minor > req_rev->minor || 218 (rev->minor == req_rev->minor && 219 rev->subminor >= req_rev->subminor); 220 } 221 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 222 223 struct mlxsw_rx_listener_item { 224 struct list_head list; 225 struct mlxsw_rx_listener rxl; 226 void *priv; 227 bool enabled; 228 }; 229 230 struct mlxsw_event_listener_item { 231 struct list_head list; 232 struct mlxsw_core *mlxsw_core; 233 struct mlxsw_event_listener el; 234 void *priv; 235 }; 236 237 static const u8 mlxsw_core_trap_groups[] = { 238 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 239 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 240 }; 241 242 static int mlxsw_core_trap_groups_set(struct mlxsw_core *mlxsw_core) 243 { 244 char htgt_pl[MLXSW_REG_HTGT_LEN]; 245 int err; 246 int i; 247 248 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 249 return 0; 250 251 for (i = 0; i < ARRAY_SIZE(mlxsw_core_trap_groups); i++) { 252 mlxsw_reg_htgt_pack(htgt_pl, mlxsw_core_trap_groups[i], 253 MLXSW_REG_HTGT_INVALID_POLICER, 254 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 255 MLXSW_REG_HTGT_DEFAULT_TC); 256 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 257 if (err) 258 return err; 259 } 260 return 0; 261 } 262 263 /****************** 264 * EMAD processing 265 ******************/ 266 267 /* emad_eth_hdr_dmac 268 * Destination MAC in EMAD's Ethernet header. 269 * Must be set to 01:02:c9:00:00:01 270 */ 271 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 272 273 /* emad_eth_hdr_smac 274 * Source MAC in EMAD's Ethernet header. 275 * Must be set to 00:02:c9:01:02:03 276 */ 277 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 278 279 /* emad_eth_hdr_ethertype 280 * Ethertype in EMAD's Ethernet header. 281 * Must be set to 0x8932 282 */ 283 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 284 285 /* emad_eth_hdr_mlx_proto 286 * Mellanox protocol. 287 * Must be set to 0x0. 288 */ 289 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 290 291 /* emad_eth_hdr_ver 292 * Mellanox protocol version. 293 * Must be set to 0x0. 294 */ 295 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 296 297 /* emad_op_tlv_type 298 * Type of the TLV. 299 * Must be set to 0x1 (operation TLV). 300 */ 301 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 302 303 /* emad_op_tlv_len 304 * Length of the operation TLV in u32. 305 * Must be set to 0x4. 306 */ 307 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 308 309 /* emad_op_tlv_dr 310 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 311 * EMAD. DR TLV must follow. 312 * 313 * Note: Currently not supported and must not be set. 314 */ 315 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 316 317 /* emad_op_tlv_status 318 * Returned status in case of EMAD response. Must be set to 0 in case 319 * of EMAD request. 320 * 0x0 - success 321 * 0x1 - device is busy. Requester should retry 322 * 0x2 - Mellanox protocol version not supported 323 * 0x3 - unknown TLV 324 * 0x4 - register not supported 325 * 0x5 - operation class not supported 326 * 0x6 - EMAD method not supported 327 * 0x7 - bad parameter (e.g. port out of range) 328 * 0x8 - resource not available 329 * 0x9 - message receipt acknowledgment. Requester should retry 330 * 0x70 - internal error 331 */ 332 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 333 334 /* emad_op_tlv_register_id 335 * Register ID of register within register TLV. 336 */ 337 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 338 339 /* emad_op_tlv_r 340 * Response bit. Setting to 1 indicates Response, otherwise request. 341 */ 342 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 343 344 /* emad_op_tlv_method 345 * EMAD method type. 346 * 0x1 - query 347 * 0x2 - write 348 * 0x3 - send (currently not supported) 349 * 0x4 - event 350 */ 351 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 352 353 /* emad_op_tlv_class 354 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 355 */ 356 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 357 358 /* emad_op_tlv_tid 359 * EMAD transaction ID. Used for pairing request and response EMADs. 360 */ 361 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 362 363 /* emad_string_tlv_type 364 * Type of the TLV. 365 * Must be set to 0x2 (string TLV). 366 */ 367 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 368 369 /* emad_string_tlv_len 370 * Length of the string TLV in u32. 371 */ 372 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 373 374 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 375 376 /* emad_string_tlv_string 377 * String provided by the device's firmware in case of erroneous register access 378 */ 379 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 380 MLXSW_EMAD_STRING_TLV_STRING_LEN); 381 382 /* emad_latency_tlv_type 383 * Type of the TLV. 384 * Must be set to 0x4 (latency TLV). 385 */ 386 MLXSW_ITEM32(emad, latency_tlv, type, 0x00, 27, 5); 387 388 /* emad_latency_tlv_len 389 * Length of the latency TLV in u32. 390 */ 391 MLXSW_ITEM32(emad, latency_tlv, len, 0x00, 16, 11); 392 393 /* emad_latency_tlv_latency_time 394 * EMAD latency time in units of uSec. 395 */ 396 MLXSW_ITEM32(emad, latency_tlv, latency_time, 0x04, 0, 32); 397 398 /* emad_reg_tlv_type 399 * Type of the TLV. 400 * Must be set to 0x3 (register TLV). 401 */ 402 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 403 404 /* emad_reg_tlv_len 405 * Length of the operation TLV in u32. 406 */ 407 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 408 409 /* emad_end_tlv_type 410 * Type of the TLV. 411 * Must be set to 0x0 (end TLV). 412 */ 413 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 414 415 /* emad_end_tlv_len 416 * Length of the end TLV in u32. 417 * Must be set to 1. 418 */ 419 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 420 421 enum mlxsw_core_reg_access_type { 422 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 423 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 424 }; 425 426 static inline const char * 427 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 428 { 429 switch (type) { 430 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 431 return "query"; 432 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 433 return "write"; 434 } 435 BUG(); 436 } 437 438 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 439 { 440 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 441 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 442 } 443 444 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 445 const struct mlxsw_reg_info *reg, 446 char *payload) 447 { 448 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 449 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 450 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 451 } 452 453 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 454 { 455 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 456 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 457 } 458 459 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 460 const struct mlxsw_reg_info *reg, 461 enum mlxsw_core_reg_access_type type, 462 u64 tid) 463 { 464 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 465 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 466 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 467 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 468 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 469 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 470 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 471 mlxsw_emad_op_tlv_method_set(op_tlv, 472 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 473 else 474 mlxsw_emad_op_tlv_method_set(op_tlv, 475 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 476 mlxsw_emad_op_tlv_class_set(op_tlv, 477 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 478 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 479 } 480 481 static void mlxsw_emad_pack_latency_tlv(char *latency_tlv) 482 { 483 mlxsw_emad_latency_tlv_type_set(latency_tlv, MLXSW_EMAD_TLV_TYPE_LATENCY); 484 mlxsw_emad_latency_tlv_len_set(latency_tlv, MLXSW_EMAD_LATENCY_TLV_LEN); 485 } 486 487 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 488 { 489 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 490 491 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 492 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 493 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 494 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 495 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 496 497 skb_reset_mac_header(skb); 498 499 return 0; 500 } 501 502 static void mlxsw_emad_construct(const struct mlxsw_core *mlxsw_core, 503 struct sk_buff *skb, 504 const struct mlxsw_reg_info *reg, 505 char *payload, 506 enum mlxsw_core_reg_access_type type, u64 tid) 507 { 508 char *buf; 509 510 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 511 mlxsw_emad_pack_end_tlv(buf); 512 513 buf = skb_push(skb, reg->len + sizeof(u32)); 514 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 515 516 if (mlxsw_core->emad.enable_latency_tlv) { 517 buf = skb_push(skb, MLXSW_EMAD_LATENCY_TLV_LEN * sizeof(u32)); 518 mlxsw_emad_pack_latency_tlv(buf); 519 } 520 521 if (mlxsw_core->emad.enable_string_tlv) { 522 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 523 mlxsw_emad_pack_string_tlv(buf); 524 } 525 526 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 527 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 528 529 mlxsw_emad_construct_eth_hdr(skb); 530 } 531 532 struct mlxsw_emad_tlv_offsets { 533 u16 op_tlv; 534 u16 string_tlv; 535 u16 latency_tlv; 536 u16 reg_tlv; 537 }; 538 539 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 540 { 541 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 542 543 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 544 } 545 546 static bool mlxsw_emad_tlv_is_latency_tlv(const char *tlv) 547 { 548 u8 tlv_type = mlxsw_emad_latency_tlv_type_get(tlv); 549 550 return tlv_type == MLXSW_EMAD_TLV_TYPE_LATENCY; 551 } 552 553 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 554 { 555 struct mlxsw_emad_tlv_offsets *offsets = 556 (struct mlxsw_emad_tlv_offsets *) skb->cb; 557 558 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 559 offsets->string_tlv = 0; 560 offsets->latency_tlv = 0; 561 562 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 563 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 564 565 /* If string TLV is present, it must come after the operation TLV. */ 566 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 567 offsets->string_tlv = offsets->reg_tlv; 568 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 569 } 570 571 if (mlxsw_emad_tlv_is_latency_tlv(skb->data + offsets->reg_tlv)) { 572 offsets->latency_tlv = offsets->reg_tlv; 573 offsets->reg_tlv += MLXSW_EMAD_LATENCY_TLV_LEN * sizeof(u32); 574 } 575 } 576 577 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 578 { 579 struct mlxsw_emad_tlv_offsets *offsets = 580 (struct mlxsw_emad_tlv_offsets *) skb->cb; 581 582 return ((char *) (skb->data + offsets->op_tlv)); 583 } 584 585 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 586 { 587 struct mlxsw_emad_tlv_offsets *offsets = 588 (struct mlxsw_emad_tlv_offsets *) skb->cb; 589 590 if (!offsets->string_tlv) 591 return NULL; 592 593 return ((char *) (skb->data + offsets->string_tlv)); 594 } 595 596 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 597 { 598 struct mlxsw_emad_tlv_offsets *offsets = 599 (struct mlxsw_emad_tlv_offsets *) skb->cb; 600 601 return ((char *) (skb->data + offsets->reg_tlv)); 602 } 603 604 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 605 { 606 return ((char *) (reg_tlv + sizeof(u32))); 607 } 608 609 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 610 { 611 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 612 } 613 614 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 615 { 616 char *op_tlv; 617 618 op_tlv = mlxsw_emad_op_tlv(skb); 619 return mlxsw_emad_op_tlv_tid_get(op_tlv); 620 } 621 622 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 623 { 624 char *op_tlv; 625 626 op_tlv = mlxsw_emad_op_tlv(skb); 627 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 628 } 629 630 static int mlxsw_emad_process_status(char *op_tlv, 631 enum mlxsw_emad_op_tlv_status *p_status) 632 { 633 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 634 635 switch (*p_status) { 636 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 637 return 0; 638 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 639 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 640 return -EAGAIN; 641 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 642 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 643 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 644 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 645 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 646 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 647 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 648 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 649 default: 650 return -EIO; 651 } 652 } 653 654 static int 655 mlxsw_emad_process_status_skb(struct sk_buff *skb, 656 enum mlxsw_emad_op_tlv_status *p_status) 657 { 658 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 659 } 660 661 struct mlxsw_reg_trans { 662 struct list_head list; 663 struct list_head bulk_list; 664 struct mlxsw_core *core; 665 struct sk_buff *tx_skb; 666 struct mlxsw_tx_info tx_info; 667 struct delayed_work timeout_dw; 668 unsigned int retries; 669 u64 tid; 670 struct completion completion; 671 atomic_t active; 672 mlxsw_reg_trans_cb_t *cb; 673 unsigned long cb_priv; 674 const struct mlxsw_reg_info *reg; 675 enum mlxsw_core_reg_access_type type; 676 int err; 677 char *emad_err_string; 678 enum mlxsw_emad_op_tlv_status emad_status; 679 struct rcu_head rcu; 680 }; 681 682 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 683 struct mlxsw_reg_trans *trans) 684 { 685 char *string_tlv; 686 char *string; 687 688 string_tlv = mlxsw_emad_string_tlv(skb); 689 if (!string_tlv) 690 return; 691 692 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 693 GFP_ATOMIC); 694 if (!trans->emad_err_string) 695 return; 696 697 string = mlxsw_emad_string_tlv_string_data(string_tlv); 698 strscpy(trans->emad_err_string, string, 699 MLXSW_EMAD_STRING_TLV_STRING_LEN); 700 } 701 702 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 703 #define MLXSW_EMAD_TIMEOUT_MS 200 704 705 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 706 { 707 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 708 709 if (trans->core->fw_flash_in_progress) 710 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 711 712 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 713 timeout << trans->retries); 714 } 715 716 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 717 struct mlxsw_reg_trans *trans) 718 { 719 struct sk_buff *skb; 720 int err; 721 722 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 723 if (!skb) 724 return -ENOMEM; 725 726 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 727 skb->data + mlxsw_core->driver->txhdr_len, 728 skb->len - mlxsw_core->driver->txhdr_len); 729 730 atomic_set(&trans->active, 1); 731 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 732 if (err) { 733 dev_kfree_skb(skb); 734 return err; 735 } 736 mlxsw_emad_trans_timeout_schedule(trans); 737 return 0; 738 } 739 740 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 741 { 742 struct mlxsw_core *mlxsw_core = trans->core; 743 744 dev_kfree_skb(trans->tx_skb); 745 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 746 list_del_rcu(&trans->list); 747 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 748 trans->err = err; 749 complete(&trans->completion); 750 } 751 752 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 753 struct mlxsw_reg_trans *trans) 754 { 755 int err; 756 757 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 758 trans->retries++; 759 err = mlxsw_emad_transmit(trans->core, trans); 760 if (err == 0) 761 return; 762 763 if (!atomic_dec_and_test(&trans->active)) 764 return; 765 } else { 766 err = -EIO; 767 } 768 mlxsw_emad_trans_finish(trans, err); 769 } 770 771 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 772 { 773 struct mlxsw_reg_trans *trans = container_of(work, 774 struct mlxsw_reg_trans, 775 timeout_dw.work); 776 777 if (!atomic_dec_and_test(&trans->active)) 778 return; 779 780 mlxsw_emad_transmit_retry(trans->core, trans); 781 } 782 783 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 784 struct mlxsw_reg_trans *trans, 785 struct sk_buff *skb) 786 { 787 int err; 788 789 if (!atomic_dec_and_test(&trans->active)) 790 return; 791 792 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 793 if (err == -EAGAIN) { 794 mlxsw_emad_transmit_retry(mlxsw_core, trans); 795 } else { 796 if (err == 0) { 797 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 798 799 if (trans->cb) 800 trans->cb(mlxsw_core, 801 mlxsw_emad_reg_payload(reg_tlv), 802 trans->reg->len, trans->cb_priv); 803 } else { 804 mlxsw_emad_process_string_tlv(skb, trans); 805 } 806 mlxsw_emad_trans_finish(trans, err); 807 } 808 } 809 810 /* called with rcu read lock held */ 811 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, 812 void *priv) 813 { 814 struct mlxsw_core *mlxsw_core = priv; 815 struct mlxsw_reg_trans *trans; 816 817 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 818 skb->data, skb->len); 819 820 mlxsw_emad_tlv_parse(skb); 821 822 if (!mlxsw_emad_is_resp(skb)) 823 goto free_skb; 824 825 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 826 if (mlxsw_emad_get_tid(skb) == trans->tid) { 827 mlxsw_emad_process_response(mlxsw_core, trans, skb); 828 break; 829 } 830 } 831 832 free_skb: 833 dev_kfree_skb(skb); 834 } 835 836 static const struct mlxsw_listener mlxsw_emad_rx_listener = 837 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 838 EMAD, DISCARD); 839 840 static int mlxsw_emad_tlv_enable(struct mlxsw_core *mlxsw_core) 841 { 842 char mgir_pl[MLXSW_REG_MGIR_LEN]; 843 bool string_tlv, latency_tlv; 844 int err; 845 846 mlxsw_reg_mgir_pack(mgir_pl); 847 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 848 if (err) 849 return err; 850 851 string_tlv = mlxsw_reg_mgir_fw_info_string_tlv_get(mgir_pl); 852 mlxsw_core->emad.enable_string_tlv = string_tlv; 853 854 latency_tlv = mlxsw_reg_mgir_fw_info_latency_tlv_get(mgir_pl); 855 mlxsw_core->emad.enable_latency_tlv = latency_tlv; 856 857 return 0; 858 } 859 860 static void mlxsw_emad_tlv_disable(struct mlxsw_core *mlxsw_core) 861 { 862 mlxsw_core->emad.enable_latency_tlv = false; 863 mlxsw_core->emad.enable_string_tlv = false; 864 } 865 866 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 867 { 868 struct workqueue_struct *emad_wq; 869 u64 tid; 870 int err; 871 872 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 873 return 0; 874 875 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 876 if (!emad_wq) 877 return -ENOMEM; 878 mlxsw_core->emad_wq = emad_wq; 879 880 /* Set the upper 32 bits of the transaction ID field to a random 881 * number. This allows us to discard EMADs addressed to other 882 * devices. 883 */ 884 get_random_bytes(&tid, 4); 885 tid <<= 32; 886 atomic64_set(&mlxsw_core->emad.tid, tid); 887 888 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 889 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 890 891 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 892 mlxsw_core); 893 if (err) 894 goto err_trap_register; 895 896 err = mlxsw_emad_tlv_enable(mlxsw_core); 897 if (err) 898 goto err_emad_tlv_enable; 899 900 mlxsw_core->emad.use_emad = true; 901 902 return 0; 903 904 err_emad_tlv_enable: 905 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 906 mlxsw_core); 907 err_trap_register: 908 destroy_workqueue(mlxsw_core->emad_wq); 909 return err; 910 } 911 912 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 913 { 914 915 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 916 return; 917 918 mlxsw_core->emad.use_emad = false; 919 mlxsw_emad_tlv_disable(mlxsw_core); 920 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 921 mlxsw_core); 922 destroy_workqueue(mlxsw_core->emad_wq); 923 } 924 925 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 926 u16 reg_len) 927 { 928 struct sk_buff *skb; 929 u16 emad_len; 930 931 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 932 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 933 sizeof(u32) + mlxsw_core->driver->txhdr_len); 934 if (mlxsw_core->emad.enable_string_tlv) 935 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 936 if (mlxsw_core->emad.enable_latency_tlv) 937 emad_len += MLXSW_EMAD_LATENCY_TLV_LEN * sizeof(u32); 938 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 939 return NULL; 940 941 skb = netdev_alloc_skb(NULL, emad_len); 942 if (!skb) 943 return NULL; 944 memset(skb->data, 0, emad_len); 945 skb_reserve(skb, emad_len); 946 947 return skb; 948 } 949 950 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 951 const struct mlxsw_reg_info *reg, 952 char *payload, 953 enum mlxsw_core_reg_access_type type, 954 struct mlxsw_reg_trans *trans, 955 struct list_head *bulk_list, 956 mlxsw_reg_trans_cb_t *cb, 957 unsigned long cb_priv, u64 tid) 958 { 959 struct sk_buff *skb; 960 int err; 961 962 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 963 tid, reg->id, mlxsw_reg_id_str(reg->id), 964 mlxsw_core_reg_access_type_str(type)); 965 966 skb = mlxsw_emad_alloc(mlxsw_core, reg->len); 967 if (!skb) 968 return -ENOMEM; 969 970 list_add_tail(&trans->bulk_list, bulk_list); 971 trans->core = mlxsw_core; 972 trans->tx_skb = skb; 973 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 974 trans->tx_info.is_emad = true; 975 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 976 trans->tid = tid; 977 init_completion(&trans->completion); 978 trans->cb = cb; 979 trans->cb_priv = cb_priv; 980 trans->reg = reg; 981 trans->type = type; 982 983 mlxsw_emad_construct(mlxsw_core, skb, reg, payload, type, trans->tid); 984 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 985 986 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 987 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 988 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 989 err = mlxsw_emad_transmit(mlxsw_core, trans); 990 if (err) 991 goto err_out; 992 return 0; 993 994 err_out: 995 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 996 list_del_rcu(&trans->list); 997 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 998 list_del(&trans->bulk_list); 999 dev_kfree_skb(trans->tx_skb); 1000 return err; 1001 } 1002 1003 /***************** 1004 * Core functions 1005 *****************/ 1006 1007 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 1008 { 1009 spin_lock(&mlxsw_core_driver_list_lock); 1010 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 1011 spin_unlock(&mlxsw_core_driver_list_lock); 1012 return 0; 1013 } 1014 EXPORT_SYMBOL(mlxsw_core_driver_register); 1015 1016 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 1017 { 1018 spin_lock(&mlxsw_core_driver_list_lock); 1019 list_del(&mlxsw_driver->list); 1020 spin_unlock(&mlxsw_core_driver_list_lock); 1021 } 1022 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 1023 1024 static struct mlxsw_driver *__driver_find(const char *kind) 1025 { 1026 struct mlxsw_driver *mlxsw_driver; 1027 1028 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 1029 if (strcmp(mlxsw_driver->kind, kind) == 0) 1030 return mlxsw_driver; 1031 } 1032 return NULL; 1033 } 1034 1035 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 1036 { 1037 struct mlxsw_driver *mlxsw_driver; 1038 1039 spin_lock(&mlxsw_core_driver_list_lock); 1040 mlxsw_driver = __driver_find(kind); 1041 spin_unlock(&mlxsw_core_driver_list_lock); 1042 return mlxsw_driver; 1043 } 1044 1045 int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, 1046 struct mlxfw_dev *mlxfw_dev, 1047 const struct firmware *firmware, 1048 struct netlink_ext_ack *extack) 1049 { 1050 int err; 1051 1052 mlxsw_core->fw_flash_in_progress = true; 1053 err = mlxfw_firmware_flash(mlxfw_dev, firmware, extack); 1054 mlxsw_core->fw_flash_in_progress = false; 1055 1056 return err; 1057 } 1058 1059 struct mlxsw_core_fw_info { 1060 struct mlxfw_dev mlxfw_dev; 1061 struct mlxsw_core *mlxsw_core; 1062 }; 1063 1064 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 1065 u16 component_index, u32 *p_max_size, 1066 u8 *p_align_bits, u16 *p_max_write_size) 1067 { 1068 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1069 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1070 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1071 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 1072 int err; 1073 1074 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 1075 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 1076 if (err) 1077 return err; 1078 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 1079 1080 *p_align_bits = max_t(u8, *p_align_bits, 2); 1081 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 1082 return 0; 1083 } 1084 1085 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 1086 { 1087 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1088 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1089 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1090 char mcc_pl[MLXSW_REG_MCC_LEN]; 1091 u8 control_state; 1092 int err; 1093 1094 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 1095 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1096 if (err) 1097 return err; 1098 1099 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 1100 if (control_state != MLXFW_FSM_STATE_IDLE) 1101 return -EBUSY; 1102 1103 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 1104 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1105 } 1106 1107 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1108 u16 component_index, u32 component_size) 1109 { 1110 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1111 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1112 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1113 char mcc_pl[MLXSW_REG_MCC_LEN]; 1114 1115 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 1116 component_index, fwhandle, component_size); 1117 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1118 } 1119 1120 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1121 u8 *data, u16 size, u32 offset) 1122 { 1123 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1124 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1125 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1126 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1127 1128 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1129 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1130 } 1131 1132 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1133 u16 component_index) 1134 { 1135 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1136 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1137 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1138 char mcc_pl[MLXSW_REG_MCC_LEN]; 1139 1140 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1141 component_index, fwhandle, 0); 1142 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1143 } 1144 1145 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1146 { 1147 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1148 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1149 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1150 char mcc_pl[MLXSW_REG_MCC_LEN]; 1151 1152 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1153 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1154 } 1155 1156 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1157 enum mlxfw_fsm_state *fsm_state, 1158 enum mlxfw_fsm_state_err *fsm_state_err) 1159 { 1160 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1161 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1162 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1163 char mcc_pl[MLXSW_REG_MCC_LEN]; 1164 u8 control_state; 1165 u8 error_code; 1166 int err; 1167 1168 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1169 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1170 if (err) 1171 return err; 1172 1173 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1174 *fsm_state = control_state; 1175 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1176 return 0; 1177 } 1178 1179 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1180 { 1181 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1182 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1183 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1184 char mcc_pl[MLXSW_REG_MCC_LEN]; 1185 1186 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1187 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1188 } 1189 1190 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1191 { 1192 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1193 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1194 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1195 char mcc_pl[MLXSW_REG_MCC_LEN]; 1196 1197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1198 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1199 } 1200 1201 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1202 .component_query = mlxsw_core_fw_component_query, 1203 .fsm_lock = mlxsw_core_fw_fsm_lock, 1204 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1205 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1206 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1207 .fsm_activate = mlxsw_core_fw_fsm_activate, 1208 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1209 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1210 .fsm_release = mlxsw_core_fw_fsm_release, 1211 }; 1212 1213 static int mlxsw_core_dev_fw_flash(struct mlxsw_core *mlxsw_core, 1214 const struct firmware *firmware, 1215 struct netlink_ext_ack *extack) 1216 { 1217 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1218 .mlxfw_dev = { 1219 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1220 .psid = mlxsw_core->bus_info->psid, 1221 .psid_size = strlen(mlxsw_core->bus_info->psid), 1222 .devlink = priv_to_devlink(mlxsw_core), 1223 }, 1224 .mlxsw_core = mlxsw_core 1225 }; 1226 1227 return mlxsw_core_fw_flash(mlxsw_core, &mlxsw_core_fw_info.mlxfw_dev, 1228 firmware, extack); 1229 } 1230 1231 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1232 const struct mlxsw_bus_info *mlxsw_bus_info, 1233 const struct mlxsw_fw_rev *req_rev, 1234 const char *filename) 1235 { 1236 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1237 union devlink_param_value value; 1238 const struct firmware *firmware; 1239 int err; 1240 1241 /* Don't check if driver does not require it */ 1242 if (!req_rev || !filename) 1243 return 0; 1244 1245 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1246 err = devl_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1247 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1248 &value); 1249 if (err) 1250 return err; 1251 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1252 return 0; 1253 1254 /* Validate driver & FW are compatible */ 1255 if (rev->major != req_rev->major) { 1256 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1257 rev->major, req_rev->major); 1258 return -EINVAL; 1259 } 1260 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1261 return 0; 1262 1263 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1264 rev->major, rev->minor, rev->subminor, req_rev->major, 1265 req_rev->minor, req_rev->subminor); 1266 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1267 1268 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1269 if (err) { 1270 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1271 return err; 1272 } 1273 1274 err = mlxsw_core_dev_fw_flash(mlxsw_core, firmware, NULL); 1275 release_firmware(firmware); 1276 if (err) 1277 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1278 1279 /* On FW flash success, tell the caller FW reset is needed 1280 * if current FW supports it. 1281 */ 1282 if (rev->minor >= req_rev->can_reset_minor) 1283 return err ? err : -EAGAIN; 1284 else 1285 return 0; 1286 } 1287 1288 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1289 struct devlink_flash_update_params *params, 1290 struct netlink_ext_ack *extack) 1291 { 1292 return mlxsw_core_dev_fw_flash(mlxsw_core, params->fw, extack); 1293 } 1294 1295 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1296 union devlink_param_value val, 1297 struct netlink_ext_ack *extack) 1298 { 1299 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1300 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1301 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1302 return -EINVAL; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1309 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1310 mlxsw_core_devlink_param_fw_load_policy_validate), 1311 }; 1312 1313 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1314 { 1315 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1316 union devlink_param_value value; 1317 int err; 1318 1319 err = devl_params_register(devlink, mlxsw_core_fw_devlink_params, 1320 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1321 if (err) 1322 return err; 1323 1324 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1325 devl_param_driverinit_value_set(devlink, 1326 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1327 value); 1328 return 0; 1329 } 1330 1331 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1332 { 1333 devl_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1334 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1335 } 1336 1337 static void *__dl_port(struct devlink_port *devlink_port) 1338 { 1339 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1340 } 1341 1342 static int mlxsw_devlink_port_split(struct devlink *devlink, 1343 struct devlink_port *port, 1344 unsigned int count, 1345 struct netlink_ext_ack *extack) 1346 { 1347 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1348 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1349 1350 if (!mlxsw_core->driver->port_split) 1351 return -EOPNOTSUPP; 1352 return mlxsw_core->driver->port_split(mlxsw_core, 1353 mlxsw_core_port->local_port, 1354 count, extack); 1355 } 1356 1357 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1358 struct devlink_port *port, 1359 struct netlink_ext_ack *extack) 1360 { 1361 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1362 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1363 1364 if (!mlxsw_core->driver->port_unsplit) 1365 return -EOPNOTSUPP; 1366 return mlxsw_core->driver->port_unsplit(mlxsw_core, 1367 mlxsw_core_port->local_port, 1368 extack); 1369 } 1370 1371 static int 1372 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1373 unsigned int sb_index, u16 pool_index, 1374 struct devlink_sb_pool_info *pool_info) 1375 { 1376 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1377 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1378 1379 if (!mlxsw_driver->sb_pool_get) 1380 return -EOPNOTSUPP; 1381 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1382 pool_index, pool_info); 1383 } 1384 1385 static int 1386 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1387 unsigned int sb_index, u16 pool_index, u32 size, 1388 enum devlink_sb_threshold_type threshold_type, 1389 struct netlink_ext_ack *extack) 1390 { 1391 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1392 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1393 1394 if (!mlxsw_driver->sb_pool_set) 1395 return -EOPNOTSUPP; 1396 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1397 pool_index, size, threshold_type, 1398 extack); 1399 } 1400 1401 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1402 unsigned int sb_index, u16 pool_index, 1403 u32 *p_threshold) 1404 { 1405 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1406 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1407 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1408 1409 if (!mlxsw_driver->sb_port_pool_get || 1410 !mlxsw_core_port_check(mlxsw_core_port)) 1411 return -EOPNOTSUPP; 1412 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1413 pool_index, p_threshold); 1414 } 1415 1416 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1417 unsigned int sb_index, u16 pool_index, 1418 u32 threshold, 1419 struct netlink_ext_ack *extack) 1420 { 1421 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1422 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1423 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1424 1425 if (!mlxsw_driver->sb_port_pool_set || 1426 !mlxsw_core_port_check(mlxsw_core_port)) 1427 return -EOPNOTSUPP; 1428 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1429 pool_index, threshold, extack); 1430 } 1431 1432 static int 1433 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1434 unsigned int sb_index, u16 tc_index, 1435 enum devlink_sb_pool_type pool_type, 1436 u16 *p_pool_index, u32 *p_threshold) 1437 { 1438 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1439 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1440 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1441 1442 if (!mlxsw_driver->sb_tc_pool_bind_get || 1443 !mlxsw_core_port_check(mlxsw_core_port)) 1444 return -EOPNOTSUPP; 1445 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1446 tc_index, pool_type, 1447 p_pool_index, p_threshold); 1448 } 1449 1450 static int 1451 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1452 unsigned int sb_index, u16 tc_index, 1453 enum devlink_sb_pool_type pool_type, 1454 u16 pool_index, u32 threshold, 1455 struct netlink_ext_ack *extack) 1456 { 1457 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1458 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1459 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1460 1461 if (!mlxsw_driver->sb_tc_pool_bind_set || 1462 !mlxsw_core_port_check(mlxsw_core_port)) 1463 return -EOPNOTSUPP; 1464 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1465 tc_index, pool_type, 1466 pool_index, threshold, extack); 1467 } 1468 1469 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1470 unsigned int sb_index) 1471 { 1472 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1473 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1474 1475 if (!mlxsw_driver->sb_occ_snapshot) 1476 return -EOPNOTSUPP; 1477 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1478 } 1479 1480 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1481 unsigned int sb_index) 1482 { 1483 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1484 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1485 1486 if (!mlxsw_driver->sb_occ_max_clear) 1487 return -EOPNOTSUPP; 1488 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1489 } 1490 1491 static int 1492 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1493 unsigned int sb_index, u16 pool_index, 1494 u32 *p_cur, u32 *p_max) 1495 { 1496 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1497 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1498 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1499 1500 if (!mlxsw_driver->sb_occ_port_pool_get || 1501 !mlxsw_core_port_check(mlxsw_core_port)) 1502 return -EOPNOTSUPP; 1503 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1504 pool_index, p_cur, p_max); 1505 } 1506 1507 static int 1508 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1509 unsigned int sb_index, u16 tc_index, 1510 enum devlink_sb_pool_type pool_type, 1511 u32 *p_cur, u32 *p_max) 1512 { 1513 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1514 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1515 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1516 1517 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1518 !mlxsw_core_port_check(mlxsw_core_port)) 1519 return -EOPNOTSUPP; 1520 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1521 sb_index, tc_index, 1522 pool_type, p_cur, p_max); 1523 } 1524 1525 static int 1526 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1527 struct netlink_ext_ack *extack) 1528 { 1529 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1530 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1531 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1532 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1533 char buf[32]; 1534 int err; 1535 1536 mlxsw_reg_mgir_pack(mgir_pl); 1537 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1538 if (err) 1539 return err; 1540 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1541 &fw_minor, &fw_sub_minor); 1542 1543 sprintf(buf, "%X", hw_rev); 1544 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1545 if (err) 1546 return err; 1547 1548 err = devlink_info_version_fixed_put(req, 1549 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1550 fw_info_psid); 1551 if (err) 1552 return err; 1553 1554 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1555 err = devlink_info_version_running_put(req, "fw.version", buf); 1556 if (err) 1557 return err; 1558 1559 return devlink_info_version_running_put(req, 1560 DEVLINK_INFO_VERSION_GENERIC_FW, 1561 buf); 1562 } 1563 1564 static int 1565 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1566 bool netns_change, enum devlink_reload_action action, 1567 enum devlink_reload_limit limit, 1568 struct netlink_ext_ack *extack) 1569 { 1570 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1571 1572 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1573 return -EOPNOTSUPP; 1574 1575 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1576 return 0; 1577 } 1578 1579 static int 1580 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1581 enum devlink_reload_limit limit, u32 *actions_performed, 1582 struct netlink_ext_ack *extack) 1583 { 1584 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1585 int err; 1586 1587 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1588 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1589 err = mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1590 mlxsw_core->bus, 1591 mlxsw_core->bus_priv, true, 1592 devlink, extack); 1593 return err; 1594 } 1595 1596 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1597 struct devlink_flash_update_params *params, 1598 struct netlink_ext_ack *extack) 1599 { 1600 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1601 1602 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1603 } 1604 1605 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1606 const struct devlink_trap *trap, 1607 void *trap_ctx) 1608 { 1609 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1610 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1611 1612 if (!mlxsw_driver->trap_init) 1613 return -EOPNOTSUPP; 1614 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1615 } 1616 1617 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1618 const struct devlink_trap *trap, 1619 void *trap_ctx) 1620 { 1621 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1622 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1623 1624 if (!mlxsw_driver->trap_fini) 1625 return; 1626 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1627 } 1628 1629 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1630 const struct devlink_trap *trap, 1631 enum devlink_trap_action action, 1632 struct netlink_ext_ack *extack) 1633 { 1634 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1635 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1636 1637 if (!mlxsw_driver->trap_action_set) 1638 return -EOPNOTSUPP; 1639 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1640 } 1641 1642 static int 1643 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1644 const struct devlink_trap_group *group) 1645 { 1646 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1647 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1648 1649 if (!mlxsw_driver->trap_group_init) 1650 return -EOPNOTSUPP; 1651 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1652 } 1653 1654 static int 1655 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1656 const struct devlink_trap_group *group, 1657 const struct devlink_trap_policer *policer, 1658 struct netlink_ext_ack *extack) 1659 { 1660 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1661 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1662 1663 if (!mlxsw_driver->trap_group_set) 1664 return -EOPNOTSUPP; 1665 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1666 } 1667 1668 static int 1669 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1670 const struct devlink_trap_policer *policer) 1671 { 1672 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1673 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1674 1675 if (!mlxsw_driver->trap_policer_init) 1676 return -EOPNOTSUPP; 1677 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1678 } 1679 1680 static void 1681 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1682 const struct devlink_trap_policer *policer) 1683 { 1684 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1685 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1686 1687 if (!mlxsw_driver->trap_policer_fini) 1688 return; 1689 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1690 } 1691 1692 static int 1693 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1694 const struct devlink_trap_policer *policer, 1695 u64 rate, u64 burst, 1696 struct netlink_ext_ack *extack) 1697 { 1698 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1699 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1700 1701 if (!mlxsw_driver->trap_policer_set) 1702 return -EOPNOTSUPP; 1703 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1704 extack); 1705 } 1706 1707 static int 1708 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1709 const struct devlink_trap_policer *policer, 1710 u64 *p_drops) 1711 { 1712 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1713 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1714 1715 if (!mlxsw_driver->trap_policer_counter_get) 1716 return -EOPNOTSUPP; 1717 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1718 p_drops); 1719 } 1720 1721 static const struct devlink_ops mlxsw_devlink_ops = { 1722 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1723 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1724 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1725 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1726 .port_split = mlxsw_devlink_port_split, 1727 .port_unsplit = mlxsw_devlink_port_unsplit, 1728 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1729 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1730 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1731 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1732 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1733 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1734 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1735 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1736 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1737 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1738 .info_get = mlxsw_devlink_info_get, 1739 .flash_update = mlxsw_devlink_flash_update, 1740 .trap_init = mlxsw_devlink_trap_init, 1741 .trap_fini = mlxsw_devlink_trap_fini, 1742 .trap_action_set = mlxsw_devlink_trap_action_set, 1743 .trap_group_init = mlxsw_devlink_trap_group_init, 1744 .trap_group_set = mlxsw_devlink_trap_group_set, 1745 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1746 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1747 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1748 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1749 }; 1750 1751 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1752 { 1753 int err; 1754 1755 err = mlxsw_core_fw_params_register(mlxsw_core); 1756 if (err) 1757 return err; 1758 1759 if (mlxsw_core->driver->params_register) { 1760 err = mlxsw_core->driver->params_register(mlxsw_core); 1761 if (err) 1762 goto err_params_register; 1763 } 1764 return 0; 1765 1766 err_params_register: 1767 mlxsw_core_fw_params_unregister(mlxsw_core); 1768 return err; 1769 } 1770 1771 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1772 { 1773 mlxsw_core_fw_params_unregister(mlxsw_core); 1774 if (mlxsw_core->driver->params_register) 1775 mlxsw_core->driver->params_unregister(mlxsw_core); 1776 } 1777 1778 struct mlxsw_core_health_event { 1779 struct mlxsw_core *mlxsw_core; 1780 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1781 struct work_struct work; 1782 }; 1783 1784 static void mlxsw_core_health_event_work(struct work_struct *work) 1785 { 1786 struct mlxsw_core_health_event *event; 1787 struct mlxsw_core *mlxsw_core; 1788 1789 event = container_of(work, struct mlxsw_core_health_event, work); 1790 mlxsw_core = event->mlxsw_core; 1791 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1792 event->mfde_pl); 1793 kfree(event); 1794 } 1795 1796 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1797 char *mfde_pl, void *priv) 1798 { 1799 struct mlxsw_core_health_event *event; 1800 struct mlxsw_core *mlxsw_core = priv; 1801 1802 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1803 if (!event) 1804 return; 1805 event->mlxsw_core = mlxsw_core; 1806 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1807 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1808 mlxsw_core_schedule_work(&event->work); 1809 } 1810 1811 static const struct mlxsw_listener mlxsw_core_health_listener = 1812 MLXSW_CORE_EVENTL(mlxsw_core_health_listener_func, MFDE); 1813 1814 static int 1815 mlxsw_core_health_fw_fatal_dump_fatal_cause(const char *mfde_pl, 1816 struct devlink_fmsg *fmsg) 1817 { 1818 u32 val, tile_v; 1819 int err; 1820 1821 val = mlxsw_reg_mfde_fatal_cause_id_get(mfde_pl); 1822 err = devlink_fmsg_u32_pair_put(fmsg, "cause_id", val); 1823 if (err) 1824 return err; 1825 tile_v = mlxsw_reg_mfde_fatal_cause_tile_v_get(mfde_pl); 1826 if (tile_v) { 1827 val = mlxsw_reg_mfde_fatal_cause_tile_index_get(mfde_pl); 1828 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1829 if (err) 1830 return err; 1831 } 1832 1833 return 0; 1834 } 1835 1836 static int 1837 mlxsw_core_health_fw_fatal_dump_fw_assert(const char *mfde_pl, 1838 struct devlink_fmsg *fmsg) 1839 { 1840 u32 val, tile_v; 1841 int err; 1842 1843 val = mlxsw_reg_mfde_fw_assert_var0_get(mfde_pl); 1844 err = devlink_fmsg_u32_pair_put(fmsg, "var0", val); 1845 if (err) 1846 return err; 1847 val = mlxsw_reg_mfde_fw_assert_var1_get(mfde_pl); 1848 err = devlink_fmsg_u32_pair_put(fmsg, "var1", val); 1849 if (err) 1850 return err; 1851 val = mlxsw_reg_mfde_fw_assert_var2_get(mfde_pl); 1852 err = devlink_fmsg_u32_pair_put(fmsg, "var2", val); 1853 if (err) 1854 return err; 1855 val = mlxsw_reg_mfde_fw_assert_var3_get(mfde_pl); 1856 err = devlink_fmsg_u32_pair_put(fmsg, "var3", val); 1857 if (err) 1858 return err; 1859 val = mlxsw_reg_mfde_fw_assert_var4_get(mfde_pl); 1860 err = devlink_fmsg_u32_pair_put(fmsg, "var4", val); 1861 if (err) 1862 return err; 1863 val = mlxsw_reg_mfde_fw_assert_existptr_get(mfde_pl); 1864 err = devlink_fmsg_u32_pair_put(fmsg, "existptr", val); 1865 if (err) 1866 return err; 1867 val = mlxsw_reg_mfde_fw_assert_callra_get(mfde_pl); 1868 err = devlink_fmsg_u32_pair_put(fmsg, "callra", val); 1869 if (err) 1870 return err; 1871 val = mlxsw_reg_mfde_fw_assert_oe_get(mfde_pl); 1872 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1873 if (err) 1874 return err; 1875 tile_v = mlxsw_reg_mfde_fw_assert_tile_v_get(mfde_pl); 1876 if (tile_v) { 1877 val = mlxsw_reg_mfde_fw_assert_tile_index_get(mfde_pl); 1878 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1879 if (err) 1880 return err; 1881 } 1882 val = mlxsw_reg_mfde_fw_assert_ext_synd_get(mfde_pl); 1883 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", val); 1884 if (err) 1885 return err; 1886 1887 return 0; 1888 } 1889 1890 static int 1891 mlxsw_core_health_fw_fatal_dump_kvd_im_stop(const char *mfde_pl, 1892 struct devlink_fmsg *fmsg) 1893 { 1894 u32 val; 1895 int err; 1896 1897 val = mlxsw_reg_mfde_kvd_im_stop_oe_get(mfde_pl); 1898 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1899 if (err) 1900 return err; 1901 val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl); 1902 return devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1903 } 1904 1905 static int 1906 mlxsw_core_health_fw_fatal_dump_crspace_to(const char *mfde_pl, 1907 struct devlink_fmsg *fmsg) 1908 { 1909 u32 val; 1910 int err; 1911 1912 val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl); 1913 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1914 if (err) 1915 return err; 1916 val = mlxsw_reg_mfde_crspace_to_oe_get(mfde_pl); 1917 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1918 if (err) 1919 return err; 1920 val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl); 1921 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1922 if (err) 1923 return err; 1924 val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl); 1925 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1926 if (err) 1927 return err; 1928 1929 return 0; 1930 } 1931 1932 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1933 struct devlink_fmsg *fmsg, void *priv_ctx, 1934 struct netlink_ext_ack *extack) 1935 { 1936 char *mfde_pl = priv_ctx; 1937 char *val_str; 1938 u8 event_id; 1939 u32 val; 1940 int err; 1941 1942 if (!priv_ctx) 1943 /* User-triggered dumps are not possible */ 1944 return -EOPNOTSUPP; 1945 1946 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1947 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1948 if (err) 1949 return err; 1950 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1951 if (err) 1952 return err; 1953 1954 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1955 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1956 if (err) 1957 return err; 1958 switch (event_id) { 1959 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1960 val_str = "CR space timeout"; 1961 break; 1962 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1963 val_str = "KVD insertion machine stopped"; 1964 break; 1965 case MLXSW_REG_MFDE_EVENT_ID_TEST: 1966 val_str = "Test"; 1967 break; 1968 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1969 val_str = "FW assert"; 1970 break; 1971 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1972 val_str = "Fatal cause"; 1973 break; 1974 default: 1975 val_str = NULL; 1976 } 1977 if (val_str) { 1978 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1979 if (err) 1980 return err; 1981 } 1982 1983 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1984 if (err) 1985 return err; 1986 1987 err = devlink_fmsg_arr_pair_nest_start(fmsg, "severity"); 1988 if (err) 1989 return err; 1990 1991 val = mlxsw_reg_mfde_severity_get(mfde_pl); 1992 err = devlink_fmsg_u8_pair_put(fmsg, "id", val); 1993 if (err) 1994 return err; 1995 switch (val) { 1996 case MLXSW_REG_MFDE_SEVERITY_FATL: 1997 val_str = "Fatal"; 1998 break; 1999 case MLXSW_REG_MFDE_SEVERITY_NRML: 2000 val_str = "Normal"; 2001 break; 2002 case MLXSW_REG_MFDE_SEVERITY_INTR: 2003 val_str = "Debug"; 2004 break; 2005 default: 2006 val_str = NULL; 2007 } 2008 if (val_str) { 2009 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 2010 if (err) 2011 return err; 2012 } 2013 2014 err = devlink_fmsg_arr_pair_nest_end(fmsg); 2015 if (err) 2016 return err; 2017 2018 val = mlxsw_reg_mfde_method_get(mfde_pl); 2019 switch (val) { 2020 case MLXSW_REG_MFDE_METHOD_QUERY: 2021 val_str = "query"; 2022 break; 2023 case MLXSW_REG_MFDE_METHOD_WRITE: 2024 val_str = "write"; 2025 break; 2026 default: 2027 val_str = NULL; 2028 } 2029 if (val_str) { 2030 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 2031 if (err) 2032 return err; 2033 } 2034 2035 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 2036 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 2037 if (err) 2038 return err; 2039 2040 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 2041 switch (val) { 2042 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 2043 val_str = "mad"; 2044 break; 2045 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 2046 val_str = "emad"; 2047 break; 2048 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 2049 val_str = "cmdif"; 2050 break; 2051 default: 2052 val_str = NULL; 2053 } 2054 if (val_str) { 2055 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 2056 if (err) 2057 return err; 2058 } 2059 2060 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 2061 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 2062 if (err) 2063 return err; 2064 2065 switch (event_id) { 2066 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 2067 return mlxsw_core_health_fw_fatal_dump_crspace_to(mfde_pl, 2068 fmsg); 2069 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 2070 return mlxsw_core_health_fw_fatal_dump_kvd_im_stop(mfde_pl, 2071 fmsg); 2072 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 2073 return mlxsw_core_health_fw_fatal_dump_fw_assert(mfde_pl, fmsg); 2074 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 2075 return mlxsw_core_health_fw_fatal_dump_fatal_cause(mfde_pl, 2076 fmsg); 2077 } 2078 2079 return 0; 2080 } 2081 2082 static int 2083 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 2084 struct netlink_ext_ack *extack) 2085 { 2086 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 2087 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2088 int err; 2089 2090 /* Read the register first to make sure no other bits are changed. */ 2091 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2092 if (err) 2093 return err; 2094 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 2095 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2096 } 2097 2098 static const struct devlink_health_reporter_ops 2099 mlxsw_core_health_fw_fatal_ops = { 2100 .name = "fw_fatal", 2101 .dump = mlxsw_core_health_fw_fatal_dump, 2102 .test = mlxsw_core_health_fw_fatal_test, 2103 }; 2104 2105 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 2106 bool enable) 2107 { 2108 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2109 int err; 2110 2111 /* Read the register first to make sure no other bits are changed. */ 2112 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2113 if (err) 2114 return err; 2115 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 2116 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2117 } 2118 2119 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 2120 { 2121 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2122 struct devlink_health_reporter *fw_fatal; 2123 int err; 2124 2125 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2126 return 0; 2127 2128 fw_fatal = devl_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 2129 0, mlxsw_core); 2130 if (IS_ERR(fw_fatal)) { 2131 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 2132 return PTR_ERR(fw_fatal); 2133 } 2134 mlxsw_core->health.fw_fatal = fw_fatal; 2135 2136 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2137 if (err) 2138 goto err_trap_register; 2139 2140 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 2141 if (err) 2142 goto err_fw_fatal_config; 2143 2144 return 0; 2145 2146 err_fw_fatal_config: 2147 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2148 err_trap_register: 2149 devl_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2150 return err; 2151 } 2152 2153 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 2154 { 2155 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2156 return; 2157 2158 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 2159 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2160 /* Make sure there is no more event work scheduled */ 2161 mlxsw_core_flush_owq(); 2162 devl_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2163 } 2164 2165 static void mlxsw_core_irq_event_handler_init(struct mlxsw_core *mlxsw_core) 2166 { 2167 INIT_LIST_HEAD(&mlxsw_core->irq_event_handler_list); 2168 mutex_init(&mlxsw_core->irq_event_handler_lock); 2169 } 2170 2171 static void mlxsw_core_irq_event_handler_fini(struct mlxsw_core *mlxsw_core) 2172 { 2173 mutex_destroy(&mlxsw_core->irq_event_handler_lock); 2174 WARN_ON(!list_empty(&mlxsw_core->irq_event_handler_list)); 2175 } 2176 2177 static int 2178 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2179 const struct mlxsw_bus *mlxsw_bus, 2180 void *bus_priv, bool reload, 2181 struct devlink *devlink, 2182 struct netlink_ext_ack *extack) 2183 { 2184 const char *device_kind = mlxsw_bus_info->device_kind; 2185 struct mlxsw_core *mlxsw_core; 2186 struct mlxsw_driver *mlxsw_driver; 2187 size_t alloc_size; 2188 u16 max_lag; 2189 int err; 2190 2191 mlxsw_driver = mlxsw_core_driver_get(device_kind); 2192 if (!mlxsw_driver) 2193 return -EINVAL; 2194 2195 if (!reload) { 2196 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 2197 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 2198 mlxsw_bus_info->dev); 2199 if (!devlink) { 2200 err = -ENOMEM; 2201 goto err_devlink_alloc; 2202 } 2203 devl_lock(devlink); 2204 } 2205 2206 mlxsw_core = devlink_priv(devlink); 2207 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 2208 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 2209 mlxsw_core->driver = mlxsw_driver; 2210 mlxsw_core->bus = mlxsw_bus; 2211 mlxsw_core->bus_priv = bus_priv; 2212 mlxsw_core->bus_info = mlxsw_bus_info; 2213 mlxsw_core_irq_event_handler_init(mlxsw_core); 2214 2215 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, 2216 &mlxsw_core->res); 2217 if (err) 2218 goto err_bus_init; 2219 2220 if (mlxsw_driver->resources_register && !reload) { 2221 err = mlxsw_driver->resources_register(mlxsw_core); 2222 if (err) 2223 goto err_register_resources; 2224 } 2225 2226 err = mlxsw_ports_init(mlxsw_core, reload); 2227 if (err) 2228 goto err_ports_init; 2229 2230 err = mlxsw_core_max_lag(mlxsw_core, &max_lag); 2231 if (!err && MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 2232 alloc_size = sizeof(*mlxsw_core->lag.mapping) * max_lag * 2233 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 2234 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 2235 if (!mlxsw_core->lag.mapping) { 2236 err = -ENOMEM; 2237 goto err_alloc_lag_mapping; 2238 } 2239 } 2240 2241 err = mlxsw_core_trap_groups_set(mlxsw_core); 2242 if (err) 2243 goto err_trap_groups_set; 2244 2245 err = mlxsw_emad_init(mlxsw_core); 2246 if (err) 2247 goto err_emad_init; 2248 2249 if (!reload) { 2250 err = mlxsw_core_params_register(mlxsw_core); 2251 if (err) 2252 goto err_register_params; 2253 } 2254 2255 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 2256 mlxsw_driver->fw_filename); 2257 if (err) 2258 goto err_fw_rev_validate; 2259 2260 err = mlxsw_linecards_init(mlxsw_core, mlxsw_bus_info); 2261 if (err) 2262 goto err_linecards_init; 2263 2264 err = mlxsw_core_health_init(mlxsw_core); 2265 if (err) 2266 goto err_health_init; 2267 2268 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 2269 if (err) 2270 goto err_hwmon_init; 2271 2272 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 2273 &mlxsw_core->thermal); 2274 if (err) 2275 goto err_thermal_init; 2276 2277 err = mlxsw_env_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->env); 2278 if (err) 2279 goto err_env_init; 2280 2281 if (mlxsw_driver->init) { 2282 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2283 if (err) 2284 goto err_driver_init; 2285 } 2286 2287 if (!reload) { 2288 devl_unlock(devlink); 2289 devlink_register(devlink); 2290 } 2291 return 0; 2292 2293 err_driver_init: 2294 mlxsw_env_fini(mlxsw_core->env); 2295 err_env_init: 2296 mlxsw_thermal_fini(mlxsw_core->thermal); 2297 err_thermal_init: 2298 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2299 err_hwmon_init: 2300 mlxsw_core_health_fini(mlxsw_core); 2301 err_health_init: 2302 mlxsw_linecards_fini(mlxsw_core); 2303 err_linecards_init: 2304 err_fw_rev_validate: 2305 if (!reload) 2306 mlxsw_core_params_unregister(mlxsw_core); 2307 err_register_params: 2308 mlxsw_emad_fini(mlxsw_core); 2309 err_emad_init: 2310 err_trap_groups_set: 2311 kfree(mlxsw_core->lag.mapping); 2312 err_alloc_lag_mapping: 2313 mlxsw_ports_fini(mlxsw_core, reload); 2314 err_ports_init: 2315 if (!reload) 2316 devl_resources_unregister(devlink); 2317 err_register_resources: 2318 mlxsw_bus->fini(bus_priv); 2319 err_bus_init: 2320 mlxsw_core_irq_event_handler_fini(mlxsw_core); 2321 if (!reload) { 2322 devl_unlock(devlink); 2323 devlink_free(devlink); 2324 } 2325 err_devlink_alloc: 2326 return err; 2327 } 2328 2329 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2330 const struct mlxsw_bus *mlxsw_bus, 2331 void *bus_priv, bool reload, 2332 struct devlink *devlink, 2333 struct netlink_ext_ack *extack) 2334 { 2335 bool called_again = false; 2336 int err; 2337 2338 again: 2339 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2340 bus_priv, reload, 2341 devlink, extack); 2342 /* -EAGAIN is returned in case the FW was updated. FW needs 2343 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2344 * again. 2345 */ 2346 if (err == -EAGAIN && !called_again) { 2347 called_again = true; 2348 goto again; 2349 } 2350 2351 return err; 2352 } 2353 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2354 2355 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2356 bool reload) 2357 { 2358 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2359 2360 if (!reload) { 2361 devlink_unregister(devlink); 2362 devl_lock(devlink); 2363 } 2364 2365 if (devlink_is_reload_failed(devlink)) { 2366 if (!reload) 2367 /* Only the parts that were not de-initialized in the 2368 * failed reload attempt need to be de-initialized. 2369 */ 2370 goto reload_fail_deinit; 2371 else 2372 return; 2373 } 2374 2375 if (mlxsw_core->driver->fini) 2376 mlxsw_core->driver->fini(mlxsw_core); 2377 mlxsw_env_fini(mlxsw_core->env); 2378 mlxsw_thermal_fini(mlxsw_core->thermal); 2379 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2380 mlxsw_core_health_fini(mlxsw_core); 2381 mlxsw_linecards_fini(mlxsw_core); 2382 if (!reload) 2383 mlxsw_core_params_unregister(mlxsw_core); 2384 mlxsw_emad_fini(mlxsw_core); 2385 kfree(mlxsw_core->lag.mapping); 2386 mlxsw_ports_fini(mlxsw_core, reload); 2387 if (!reload) 2388 devl_resources_unregister(devlink); 2389 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2390 mlxsw_core_irq_event_handler_fini(mlxsw_core); 2391 if (!reload) { 2392 devl_unlock(devlink); 2393 devlink_free(devlink); 2394 } 2395 2396 return; 2397 2398 reload_fail_deinit: 2399 mlxsw_core_params_unregister(mlxsw_core); 2400 devl_resources_unregister(devlink); 2401 devl_unlock(devlink); 2402 devlink_free(devlink); 2403 } 2404 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2405 2406 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2407 const struct mlxsw_tx_info *tx_info) 2408 { 2409 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2410 tx_info); 2411 } 2412 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2413 2414 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2415 const struct mlxsw_tx_info *tx_info) 2416 { 2417 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2418 tx_info); 2419 } 2420 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2421 2422 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2423 struct sk_buff *skb, u16 local_port) 2424 { 2425 if (mlxsw_core->driver->ptp_transmitted) 2426 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2427 local_port); 2428 } 2429 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2430 2431 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2432 const struct mlxsw_rx_listener *rxl_b) 2433 { 2434 return (rxl_a->func == rxl_b->func && 2435 rxl_a->local_port == rxl_b->local_port && 2436 rxl_a->trap_id == rxl_b->trap_id && 2437 rxl_a->mirror_reason == rxl_b->mirror_reason); 2438 } 2439 2440 static struct mlxsw_rx_listener_item * 2441 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2442 const struct mlxsw_rx_listener *rxl) 2443 { 2444 struct mlxsw_rx_listener_item *rxl_item; 2445 2446 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2447 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2448 return rxl_item; 2449 } 2450 return NULL; 2451 } 2452 2453 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2454 const struct mlxsw_rx_listener *rxl, 2455 void *priv, bool enabled) 2456 { 2457 struct mlxsw_rx_listener_item *rxl_item; 2458 2459 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2460 if (rxl_item) 2461 return -EEXIST; 2462 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2463 if (!rxl_item) 2464 return -ENOMEM; 2465 rxl_item->rxl = *rxl; 2466 rxl_item->priv = priv; 2467 rxl_item->enabled = enabled; 2468 2469 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2470 return 0; 2471 } 2472 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2473 2474 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2475 const struct mlxsw_rx_listener *rxl) 2476 { 2477 struct mlxsw_rx_listener_item *rxl_item; 2478 2479 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2480 if (!rxl_item) 2481 return; 2482 list_del_rcu(&rxl_item->list); 2483 synchronize_rcu(); 2484 kfree(rxl_item); 2485 } 2486 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2487 2488 static void 2489 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2490 const struct mlxsw_rx_listener *rxl, 2491 bool enabled) 2492 { 2493 struct mlxsw_rx_listener_item *rxl_item; 2494 2495 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2496 if (WARN_ON(!rxl_item)) 2497 return; 2498 rxl_item->enabled = enabled; 2499 } 2500 2501 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u16 local_port, 2502 void *priv) 2503 { 2504 struct mlxsw_event_listener_item *event_listener_item = priv; 2505 struct mlxsw_core *mlxsw_core; 2506 struct mlxsw_reg_info reg; 2507 char *payload; 2508 char *reg_tlv; 2509 char *op_tlv; 2510 2511 mlxsw_core = event_listener_item->mlxsw_core; 2512 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2513 skb->data, skb->len); 2514 2515 mlxsw_emad_tlv_parse(skb); 2516 op_tlv = mlxsw_emad_op_tlv(skb); 2517 reg_tlv = mlxsw_emad_reg_tlv(skb); 2518 2519 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2520 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2521 payload = mlxsw_emad_reg_payload(reg_tlv); 2522 event_listener_item->el.func(®, payload, event_listener_item->priv); 2523 dev_kfree_skb(skb); 2524 } 2525 2526 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2527 const struct mlxsw_event_listener *el_b) 2528 { 2529 return (el_a->func == el_b->func && 2530 el_a->trap_id == el_b->trap_id); 2531 } 2532 2533 static struct mlxsw_event_listener_item * 2534 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2535 const struct mlxsw_event_listener *el) 2536 { 2537 struct mlxsw_event_listener_item *el_item; 2538 2539 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2540 if (__is_event_listener_equal(&el_item->el, el)) 2541 return el_item; 2542 } 2543 return NULL; 2544 } 2545 2546 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2547 const struct mlxsw_event_listener *el, 2548 void *priv) 2549 { 2550 int err; 2551 struct mlxsw_event_listener_item *el_item; 2552 const struct mlxsw_rx_listener rxl = { 2553 .func = mlxsw_core_event_listener_func, 2554 .local_port = MLXSW_PORT_DONT_CARE, 2555 .trap_id = el->trap_id, 2556 }; 2557 2558 el_item = __find_event_listener_item(mlxsw_core, el); 2559 if (el_item) 2560 return -EEXIST; 2561 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2562 if (!el_item) 2563 return -ENOMEM; 2564 el_item->mlxsw_core = mlxsw_core; 2565 el_item->el = *el; 2566 el_item->priv = priv; 2567 2568 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2569 if (err) 2570 goto err_rx_listener_register; 2571 2572 /* No reason to save item if we did not manage to register an RX 2573 * listener for it. 2574 */ 2575 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2576 2577 return 0; 2578 2579 err_rx_listener_register: 2580 kfree(el_item); 2581 return err; 2582 } 2583 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2584 2585 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2586 const struct mlxsw_event_listener *el) 2587 { 2588 struct mlxsw_event_listener_item *el_item; 2589 const struct mlxsw_rx_listener rxl = { 2590 .func = mlxsw_core_event_listener_func, 2591 .local_port = MLXSW_PORT_DONT_CARE, 2592 .trap_id = el->trap_id, 2593 }; 2594 2595 el_item = __find_event_listener_item(mlxsw_core, el); 2596 if (!el_item) 2597 return; 2598 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2599 list_del(&el_item->list); 2600 kfree(el_item); 2601 } 2602 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2603 2604 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2605 const struct mlxsw_listener *listener, 2606 void *priv, bool enabled) 2607 { 2608 if (listener->is_event) { 2609 WARN_ON(!enabled); 2610 return mlxsw_core_event_listener_register(mlxsw_core, 2611 &listener->event_listener, 2612 priv); 2613 } else { 2614 return mlxsw_core_rx_listener_register(mlxsw_core, 2615 &listener->rx_listener, 2616 priv, enabled); 2617 } 2618 } 2619 2620 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2621 const struct mlxsw_listener *listener, 2622 void *priv) 2623 { 2624 if (listener->is_event) 2625 mlxsw_core_event_listener_unregister(mlxsw_core, 2626 &listener->event_listener); 2627 else 2628 mlxsw_core_rx_listener_unregister(mlxsw_core, 2629 &listener->rx_listener); 2630 } 2631 2632 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2633 const struct mlxsw_listener *listener, void *priv) 2634 { 2635 enum mlxsw_reg_htgt_trap_group trap_group; 2636 enum mlxsw_reg_hpkt_action action; 2637 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2638 int err; 2639 2640 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2641 return 0; 2642 2643 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2644 listener->enabled_on_register); 2645 if (err) 2646 return err; 2647 2648 action = listener->enabled_on_register ? listener->en_action : 2649 listener->dis_action; 2650 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2651 listener->dis_trap_group; 2652 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2653 trap_group, listener->is_ctrl); 2654 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2655 if (err) 2656 goto err_trap_set; 2657 2658 return 0; 2659 2660 err_trap_set: 2661 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2662 return err; 2663 } 2664 EXPORT_SYMBOL(mlxsw_core_trap_register); 2665 2666 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2667 const struct mlxsw_listener *listener, 2668 void *priv) 2669 { 2670 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2671 2672 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2673 return; 2674 2675 if (!listener->is_event) { 2676 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2677 listener->trap_id, listener->dis_trap_group, 2678 listener->is_ctrl); 2679 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2680 } 2681 2682 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2683 } 2684 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2685 2686 int mlxsw_core_traps_register(struct mlxsw_core *mlxsw_core, 2687 const struct mlxsw_listener *listeners, 2688 size_t listeners_count, void *priv) 2689 { 2690 int i, err; 2691 2692 for (i = 0; i < listeners_count; i++) { 2693 err = mlxsw_core_trap_register(mlxsw_core, 2694 &listeners[i], 2695 priv); 2696 if (err) 2697 goto err_listener_register; 2698 } 2699 return 0; 2700 2701 err_listener_register: 2702 for (i--; i >= 0; i--) { 2703 mlxsw_core_trap_unregister(mlxsw_core, 2704 &listeners[i], 2705 priv); 2706 } 2707 return err; 2708 } 2709 EXPORT_SYMBOL(mlxsw_core_traps_register); 2710 2711 void mlxsw_core_traps_unregister(struct mlxsw_core *mlxsw_core, 2712 const struct mlxsw_listener *listeners, 2713 size_t listeners_count, void *priv) 2714 { 2715 int i; 2716 2717 for (i = 0; i < listeners_count; i++) { 2718 mlxsw_core_trap_unregister(mlxsw_core, 2719 &listeners[i], 2720 priv); 2721 } 2722 } 2723 EXPORT_SYMBOL(mlxsw_core_traps_unregister); 2724 2725 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2726 const struct mlxsw_listener *listener, 2727 bool enabled) 2728 { 2729 enum mlxsw_reg_htgt_trap_group trap_group; 2730 enum mlxsw_reg_hpkt_action action; 2731 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2732 int err; 2733 2734 /* Not supported for event listener */ 2735 if (WARN_ON(listener->is_event)) 2736 return -EINVAL; 2737 2738 action = enabled ? listener->en_action : listener->dis_action; 2739 trap_group = enabled ? listener->en_trap_group : 2740 listener->dis_trap_group; 2741 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2742 trap_group, listener->is_ctrl); 2743 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2744 if (err) 2745 return err; 2746 2747 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2748 enabled); 2749 return 0; 2750 } 2751 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2752 2753 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2754 { 2755 return atomic64_inc_return(&mlxsw_core->emad.tid); 2756 } 2757 2758 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2759 const struct mlxsw_reg_info *reg, 2760 char *payload, 2761 enum mlxsw_core_reg_access_type type, 2762 struct list_head *bulk_list, 2763 mlxsw_reg_trans_cb_t *cb, 2764 unsigned long cb_priv) 2765 { 2766 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2767 struct mlxsw_reg_trans *trans; 2768 int err; 2769 2770 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2771 if (!trans) 2772 return -ENOMEM; 2773 2774 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2775 bulk_list, cb, cb_priv, tid); 2776 if (err) { 2777 kfree_rcu(trans, rcu); 2778 return err; 2779 } 2780 return 0; 2781 } 2782 2783 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2784 const struct mlxsw_reg_info *reg, char *payload, 2785 struct list_head *bulk_list, 2786 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2787 { 2788 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2789 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2790 bulk_list, cb, cb_priv); 2791 } 2792 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2793 2794 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2795 const struct mlxsw_reg_info *reg, char *payload, 2796 struct list_head *bulk_list, 2797 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2798 { 2799 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2800 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2801 bulk_list, cb, cb_priv); 2802 } 2803 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2804 2805 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2806 2807 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2808 { 2809 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2810 struct mlxsw_core *mlxsw_core = trans->core; 2811 int err; 2812 2813 wait_for_completion(&trans->completion); 2814 cancel_delayed_work_sync(&trans->timeout_dw); 2815 err = trans->err; 2816 2817 if (trans->retries) 2818 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2819 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2820 if (err) { 2821 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2822 trans->tid, trans->reg->id, 2823 mlxsw_reg_id_str(trans->reg->id), 2824 mlxsw_core_reg_access_type_str(trans->type), 2825 trans->emad_status, 2826 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2827 2828 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2829 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2830 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2831 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2832 trans->emad_err_string ? trans->emad_err_string : ""); 2833 2834 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2835 trans->emad_status, err_string); 2836 2837 kfree(trans->emad_err_string); 2838 } 2839 2840 list_del(&trans->bulk_list); 2841 kfree_rcu(trans, rcu); 2842 return err; 2843 } 2844 2845 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2846 { 2847 struct mlxsw_reg_trans *trans; 2848 struct mlxsw_reg_trans *tmp; 2849 int sum_err = 0; 2850 int err; 2851 2852 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2853 err = mlxsw_reg_trans_wait(trans); 2854 if (err && sum_err == 0) 2855 sum_err = err; /* first error to be returned */ 2856 } 2857 return sum_err; 2858 } 2859 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2860 2861 struct mlxsw_core_irq_event_handler_item { 2862 struct list_head list; 2863 void (*cb)(struct mlxsw_core *mlxsw_core); 2864 }; 2865 2866 int mlxsw_core_irq_event_handler_register(struct mlxsw_core *mlxsw_core, 2867 mlxsw_irq_event_cb_t cb) 2868 { 2869 struct mlxsw_core_irq_event_handler_item *item; 2870 2871 item = kzalloc(sizeof(*item), GFP_KERNEL); 2872 if (!item) 2873 return -ENOMEM; 2874 item->cb = cb; 2875 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2876 list_add_tail(&item->list, &mlxsw_core->irq_event_handler_list); 2877 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2878 return 0; 2879 } 2880 EXPORT_SYMBOL(mlxsw_core_irq_event_handler_register); 2881 2882 void mlxsw_core_irq_event_handler_unregister(struct mlxsw_core *mlxsw_core, 2883 mlxsw_irq_event_cb_t cb) 2884 { 2885 struct mlxsw_core_irq_event_handler_item *item, *tmp; 2886 2887 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2888 list_for_each_entry_safe(item, tmp, 2889 &mlxsw_core->irq_event_handler_list, list) { 2890 if (item->cb == cb) { 2891 list_del(&item->list); 2892 kfree(item); 2893 } 2894 } 2895 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2896 } 2897 EXPORT_SYMBOL(mlxsw_core_irq_event_handler_unregister); 2898 2899 void mlxsw_core_irq_event_handlers_call(struct mlxsw_core *mlxsw_core) 2900 { 2901 struct mlxsw_core_irq_event_handler_item *item; 2902 2903 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2904 list_for_each_entry(item, &mlxsw_core->irq_event_handler_list, list) { 2905 if (item->cb) 2906 item->cb(mlxsw_core); 2907 } 2908 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2909 } 2910 EXPORT_SYMBOL(mlxsw_core_irq_event_handlers_call); 2911 2912 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2913 const struct mlxsw_reg_info *reg, 2914 char *payload, 2915 enum mlxsw_core_reg_access_type type) 2916 { 2917 enum mlxsw_emad_op_tlv_status status; 2918 int err, n_retry; 2919 bool reset_ok; 2920 char *in_mbox, *out_mbox, *tmp; 2921 2922 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2923 reg->id, mlxsw_reg_id_str(reg->id), 2924 mlxsw_core_reg_access_type_str(type)); 2925 2926 in_mbox = mlxsw_cmd_mbox_alloc(); 2927 if (!in_mbox) 2928 return -ENOMEM; 2929 2930 out_mbox = mlxsw_cmd_mbox_alloc(); 2931 if (!out_mbox) { 2932 err = -ENOMEM; 2933 goto free_in_mbox; 2934 } 2935 2936 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2937 mlxsw_core_tid_get(mlxsw_core)); 2938 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2939 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2940 2941 /* There is a special treatment needed for MRSR (reset) register. 2942 * The command interface will return error after the command 2943 * is executed, so tell the lower layer to expect it 2944 * and cope accordingly. 2945 */ 2946 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2947 2948 n_retry = 0; 2949 retry: 2950 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2951 if (!err) { 2952 err = mlxsw_emad_process_status(out_mbox, &status); 2953 if (err) { 2954 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2955 goto retry; 2956 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2957 status, mlxsw_emad_op_tlv_status_str(status)); 2958 } 2959 } 2960 2961 if (!err) 2962 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2963 reg->len); 2964 2965 mlxsw_cmd_mbox_free(out_mbox); 2966 free_in_mbox: 2967 mlxsw_cmd_mbox_free(in_mbox); 2968 if (err) 2969 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2970 reg->id, mlxsw_reg_id_str(reg->id), 2971 mlxsw_core_reg_access_type_str(type)); 2972 return err; 2973 } 2974 2975 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2976 char *payload, size_t payload_len, 2977 unsigned long cb_priv) 2978 { 2979 char *orig_payload = (char *) cb_priv; 2980 2981 memcpy(orig_payload, payload, payload_len); 2982 } 2983 2984 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2985 const struct mlxsw_reg_info *reg, 2986 char *payload, 2987 enum mlxsw_core_reg_access_type type) 2988 { 2989 LIST_HEAD(bulk_list); 2990 int err; 2991 2992 /* During initialization EMAD interface is not available to us, 2993 * so we default to command interface. We switch to EMAD interface 2994 * after setting the appropriate traps. 2995 */ 2996 if (!mlxsw_core->emad.use_emad) 2997 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2998 payload, type); 2999 3000 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 3001 payload, type, &bulk_list, 3002 mlxsw_core_reg_access_cb, 3003 (unsigned long) payload); 3004 if (err) 3005 return err; 3006 return mlxsw_reg_trans_bulk_wait(&bulk_list); 3007 } 3008 3009 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 3010 const struct mlxsw_reg_info *reg, char *payload) 3011 { 3012 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 3013 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 3014 } 3015 EXPORT_SYMBOL(mlxsw_reg_query); 3016 3017 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 3018 const struct mlxsw_reg_info *reg, char *payload) 3019 { 3020 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 3021 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 3022 } 3023 EXPORT_SYMBOL(mlxsw_reg_write); 3024 3025 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 3026 struct mlxsw_rx_info *rx_info) 3027 { 3028 struct mlxsw_rx_listener_item *rxl_item; 3029 const struct mlxsw_rx_listener *rxl; 3030 u16 local_port; 3031 bool found = false; 3032 3033 if (rx_info->is_lag) { 3034 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 3035 __func__, rx_info->u.lag_id, 3036 rx_info->trap_id); 3037 /* Upper layer does not care if the skb came from LAG or not, 3038 * so just get the local_port for the lag port and push it up. 3039 */ 3040 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 3041 rx_info->u.lag_id, 3042 rx_info->lag_port_index); 3043 } else { 3044 local_port = rx_info->u.sys_port; 3045 } 3046 3047 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 3048 __func__, local_port, rx_info->trap_id); 3049 3050 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 3051 (local_port >= mlxsw_core->max_ports)) 3052 goto drop; 3053 3054 rcu_read_lock(); 3055 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 3056 rxl = &rxl_item->rxl; 3057 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 3058 rxl->local_port == local_port) && 3059 rxl->trap_id == rx_info->trap_id && 3060 rxl->mirror_reason == rx_info->mirror_reason) { 3061 if (rxl_item->enabled) 3062 found = true; 3063 break; 3064 } 3065 } 3066 if (!found) { 3067 rcu_read_unlock(); 3068 goto drop; 3069 } 3070 3071 rxl->func(skb, local_port, rxl_item->priv); 3072 rcu_read_unlock(); 3073 return; 3074 3075 drop: 3076 dev_kfree_skb(skb); 3077 } 3078 EXPORT_SYMBOL(mlxsw_core_skb_receive); 3079 3080 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 3081 u16 lag_id, u8 port_index) 3082 { 3083 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 3084 port_index; 3085 } 3086 3087 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 3088 u16 lag_id, u8 port_index, u16 local_port) 3089 { 3090 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3091 lag_id, port_index); 3092 3093 mlxsw_core->lag.mapping[index] = local_port; 3094 } 3095 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 3096 3097 u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 3098 u16 lag_id, u8 port_index) 3099 { 3100 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3101 lag_id, port_index); 3102 3103 return mlxsw_core->lag.mapping[index]; 3104 } 3105 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 3106 3107 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 3108 u16 lag_id, u16 local_port) 3109 { 3110 int i; 3111 3112 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 3113 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3114 lag_id, i); 3115 3116 if (mlxsw_core->lag.mapping[index] == local_port) 3117 mlxsw_core->lag.mapping[index] = 0; 3118 } 3119 } 3120 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 3121 3122 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 3123 enum mlxsw_res_id res_id) 3124 { 3125 return mlxsw_res_valid(&mlxsw_core->res, res_id); 3126 } 3127 EXPORT_SYMBOL(mlxsw_core_res_valid); 3128 3129 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 3130 enum mlxsw_res_id res_id) 3131 { 3132 return mlxsw_res_get(&mlxsw_core->res, res_id); 3133 } 3134 EXPORT_SYMBOL(mlxsw_core_res_get); 3135 3136 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3137 enum devlink_port_flavour flavour, 3138 u8 slot_index, u32 port_number, bool split, 3139 u32 split_port_subnumber, 3140 bool splittable, u32 lanes, 3141 const unsigned char *switch_id, 3142 unsigned char switch_id_len) 3143 { 3144 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3145 struct mlxsw_core_port *mlxsw_core_port = 3146 &mlxsw_core->ports[local_port]; 3147 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3148 struct devlink_port_attrs attrs = {}; 3149 int err; 3150 3151 attrs.split = split; 3152 attrs.lanes = lanes; 3153 attrs.splittable = splittable; 3154 attrs.flavour = flavour; 3155 attrs.phys.port_number = port_number; 3156 attrs.phys.split_subport_number = split_port_subnumber; 3157 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 3158 attrs.switch_id.id_len = switch_id_len; 3159 mlxsw_core_port->local_port = local_port; 3160 devlink_port_attrs_set(devlink_port, &attrs); 3161 if (slot_index) { 3162 struct mlxsw_linecard *linecard; 3163 3164 linecard = mlxsw_linecard_get(mlxsw_core->linecards, 3165 slot_index); 3166 mlxsw_core_port->linecard = linecard; 3167 devlink_port_linecard_set(devlink_port, 3168 linecard->devlink_linecard); 3169 } 3170 err = devl_port_register(devlink, devlink_port, local_port); 3171 if (err) 3172 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3173 return err; 3174 } 3175 3176 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3177 { 3178 struct mlxsw_core_port *mlxsw_core_port = 3179 &mlxsw_core->ports[local_port]; 3180 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3181 3182 devl_port_unregister(devlink_port); 3183 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3184 } 3185 3186 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3187 u8 slot_index, u32 port_number, bool split, 3188 u32 split_port_subnumber, 3189 bool splittable, u32 lanes, 3190 const unsigned char *switch_id, 3191 unsigned char switch_id_len) 3192 { 3193 int err; 3194 3195 err = __mlxsw_core_port_init(mlxsw_core, local_port, 3196 DEVLINK_PORT_FLAVOUR_PHYSICAL, slot_index, 3197 port_number, split, split_port_subnumber, 3198 splittable, lanes, 3199 switch_id, switch_id_len); 3200 if (err) 3201 return err; 3202 3203 atomic_inc(&mlxsw_core->active_ports_count); 3204 return 0; 3205 } 3206 EXPORT_SYMBOL(mlxsw_core_port_init); 3207 3208 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3209 { 3210 atomic_dec(&mlxsw_core->active_ports_count); 3211 3212 __mlxsw_core_port_fini(mlxsw_core, local_port); 3213 } 3214 EXPORT_SYMBOL(mlxsw_core_port_fini); 3215 3216 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 3217 void *port_driver_priv, 3218 const unsigned char *switch_id, 3219 unsigned char switch_id_len) 3220 { 3221 struct mlxsw_core_port *mlxsw_core_port = 3222 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 3223 int err; 3224 3225 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 3226 DEVLINK_PORT_FLAVOUR_CPU, 3227 0, 0, false, 0, false, 0, 3228 switch_id, switch_id_len); 3229 if (err) 3230 return err; 3231 3232 mlxsw_core_port->port_driver_priv = port_driver_priv; 3233 return 0; 3234 } 3235 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 3236 3237 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 3238 { 3239 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 3240 } 3241 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 3242 3243 void mlxsw_core_port_netdev_link(struct mlxsw_core *mlxsw_core, u16 local_port, 3244 void *port_driver_priv, struct net_device *dev) 3245 { 3246 struct mlxsw_core_port *mlxsw_core_port = 3247 &mlxsw_core->ports[local_port]; 3248 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3249 3250 mlxsw_core_port->port_driver_priv = port_driver_priv; 3251 SET_NETDEV_DEVLINK_PORT(dev, devlink_port); 3252 } 3253 EXPORT_SYMBOL(mlxsw_core_port_netdev_link); 3254 3255 struct devlink_port * 3256 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 3257 u16 local_port) 3258 { 3259 struct mlxsw_core_port *mlxsw_core_port = 3260 &mlxsw_core->ports[local_port]; 3261 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3262 3263 return devlink_port; 3264 } 3265 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 3266 3267 struct mlxsw_linecard * 3268 mlxsw_core_port_linecard_get(struct mlxsw_core *mlxsw_core, 3269 u16 local_port) 3270 { 3271 struct mlxsw_core_port *mlxsw_core_port = 3272 &mlxsw_core->ports[local_port]; 3273 3274 return mlxsw_core_port->linecard; 3275 } 3276 3277 void mlxsw_core_ports_remove_selected(struct mlxsw_core *mlxsw_core, 3278 bool (*selector)(void *priv, u16 local_port), 3279 void *priv) 3280 { 3281 if (WARN_ON_ONCE(!mlxsw_core->driver->ports_remove_selected)) 3282 return; 3283 mlxsw_core->driver->ports_remove_selected(mlxsw_core, selector, priv); 3284 } 3285 3286 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 3287 { 3288 return mlxsw_core->env; 3289 } 3290 3291 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 3292 const char *buf, size_t size) 3293 { 3294 __be32 *m = (__be32 *) buf; 3295 int i; 3296 int count = size / sizeof(__be32); 3297 3298 for (i = count - 1; i >= 0; i--) 3299 if (m[i]) 3300 break; 3301 i++; 3302 count = i ? i : 1; 3303 for (i = 0; i < count; i += 4) 3304 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 3305 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 3306 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 3307 } 3308 3309 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 3310 u32 in_mod, bool out_mbox_direct, bool reset_ok, 3311 char *in_mbox, size_t in_mbox_size, 3312 char *out_mbox, size_t out_mbox_size) 3313 { 3314 u8 status; 3315 int err; 3316 3317 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 3318 if (!mlxsw_core->bus->cmd_exec) 3319 return -EOPNOTSUPP; 3320 3321 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3322 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 3323 if (in_mbox) { 3324 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 3325 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 3326 } 3327 3328 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 3329 opcode_mod, in_mod, out_mbox_direct, 3330 in_mbox, in_mbox_size, 3331 out_mbox, out_mbox_size, &status); 3332 3333 if (!err && out_mbox) { 3334 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 3335 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 3336 } 3337 3338 if (reset_ok && err == -EIO && 3339 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 3340 err = 0; 3341 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 3342 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 3343 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3344 in_mod, status, mlxsw_cmd_status_str(status)); 3345 } else if (err == -ETIMEDOUT) { 3346 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3347 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3348 in_mod); 3349 } 3350 3351 return err; 3352 } 3353 EXPORT_SYMBOL(mlxsw_cmd_exec); 3354 3355 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 3356 { 3357 return queue_delayed_work(mlxsw_wq, dwork, delay); 3358 } 3359 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 3360 3361 bool mlxsw_core_schedule_work(struct work_struct *work) 3362 { 3363 return queue_work(mlxsw_owq, work); 3364 } 3365 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3366 3367 void mlxsw_core_flush_owq(void) 3368 { 3369 flush_workqueue(mlxsw_owq); 3370 } 3371 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3372 3373 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3374 const struct mlxsw_config_profile *profile, 3375 u64 *p_single_size, u64 *p_double_size, 3376 u64 *p_linear_size) 3377 { 3378 struct mlxsw_driver *driver = mlxsw_core->driver; 3379 3380 if (!driver->kvd_sizes_get) 3381 return -EINVAL; 3382 3383 return driver->kvd_sizes_get(mlxsw_core, profile, 3384 p_single_size, p_double_size, 3385 p_linear_size); 3386 } 3387 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3388 3389 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3390 struct mlxsw_res *res) 3391 { 3392 int index, i; 3393 u64 data; 3394 u16 id; 3395 int err; 3396 3397 mlxsw_cmd_mbox_zero(mbox); 3398 3399 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3400 index++) { 3401 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3402 if (err) 3403 return err; 3404 3405 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3406 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3407 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3408 3409 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3410 return 0; 3411 3412 mlxsw_res_parse(res, id, data); 3413 } 3414 } 3415 3416 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3417 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3418 */ 3419 return -EIO; 3420 } 3421 EXPORT_SYMBOL(mlxsw_core_resources_query); 3422 3423 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3424 { 3425 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3426 } 3427 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3428 3429 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3430 { 3431 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3432 } 3433 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3434 3435 u32 mlxsw_core_read_utc_sec(struct mlxsw_core *mlxsw_core) 3436 { 3437 return mlxsw_core->bus->read_utc_sec(mlxsw_core->bus_priv); 3438 } 3439 EXPORT_SYMBOL(mlxsw_core_read_utc_sec); 3440 3441 u32 mlxsw_core_read_utc_nsec(struct mlxsw_core *mlxsw_core) 3442 { 3443 return mlxsw_core->bus->read_utc_nsec(mlxsw_core->bus_priv); 3444 } 3445 EXPORT_SYMBOL(mlxsw_core_read_utc_nsec); 3446 3447 bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core) 3448 { 3449 return mlxsw_core->driver->sdq_supports_cqe_v2; 3450 } 3451 EXPORT_SYMBOL(mlxsw_core_sdq_supports_cqe_v2); 3452 3453 static int __init mlxsw_core_module_init(void) 3454 { 3455 int err; 3456 3457 err = mlxsw_linecard_driver_register(); 3458 if (err) 3459 return err; 3460 3461 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3462 if (!mlxsw_wq) { 3463 err = -ENOMEM; 3464 goto err_alloc_workqueue; 3465 } 3466 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3467 mlxsw_core_driver_name); 3468 if (!mlxsw_owq) { 3469 err = -ENOMEM; 3470 goto err_alloc_ordered_workqueue; 3471 } 3472 return 0; 3473 3474 err_alloc_ordered_workqueue: 3475 destroy_workqueue(mlxsw_wq); 3476 err_alloc_workqueue: 3477 mlxsw_linecard_driver_unregister(); 3478 return err; 3479 } 3480 3481 static void __exit mlxsw_core_module_exit(void) 3482 { 3483 destroy_workqueue(mlxsw_owq); 3484 destroy_workqueue(mlxsw_wq); 3485 mlxsw_linecard_driver_unregister(); 3486 } 3487 3488 module_init(mlxsw_core_module_init); 3489 module_exit(mlxsw_core_module_exit); 3490 3491 MODULE_LICENSE("Dual BSD/GPL"); 3492 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3493 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3494