1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u16 local_port; 51 }; 52 53 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 54 { 55 return mlxsw_core_port->port_driver_priv; 56 } 57 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 58 59 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 60 { 61 return mlxsw_core_port->port_driver_priv != NULL; 62 } 63 64 struct mlxsw_core { 65 struct mlxsw_driver *driver; 66 const struct mlxsw_bus *bus; 67 void *bus_priv; 68 const struct mlxsw_bus_info *bus_info; 69 struct workqueue_struct *emad_wq; 70 struct list_head rx_listener_list; 71 struct list_head event_listener_list; 72 struct { 73 atomic64_t tid; 74 struct list_head trans_list; 75 spinlock_t trans_list_lock; /* protects trans_list writes */ 76 bool use_emad; 77 bool enable_string_tlv; 78 } emad; 79 struct { 80 u16 *mapping; /* lag_id+port_index to local_port mapping */ 81 } lag; 82 struct mlxsw_res res; 83 struct mlxsw_hwmon *hwmon; 84 struct mlxsw_thermal *thermal; 85 struct mlxsw_core_port *ports; 86 unsigned int max_ports; 87 atomic_t active_ports_count; 88 bool fw_flash_in_progress; 89 struct { 90 struct devlink_health_reporter *fw_fatal; 91 } health; 92 struct mlxsw_env *env; 93 unsigned long driver_priv[]; 94 /* driver_priv has to be always the last item */ 95 }; 96 97 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 98 99 static u64 mlxsw_ports_occ_get(void *priv) 100 { 101 struct mlxsw_core *mlxsw_core = priv; 102 103 return atomic_read(&mlxsw_core->active_ports_count); 104 } 105 106 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 107 { 108 struct devlink *devlink = priv_to_devlink(mlxsw_core); 109 struct devlink_resource_size_params ports_num_params; 110 u32 max_ports; 111 112 max_ports = mlxsw_core->max_ports - 1; 113 devlink_resource_size_params_init(&ports_num_params, max_ports, 114 max_ports, 1, 115 DEVLINK_RESOURCE_UNIT_ENTRY); 116 117 return devlink_resource_register(devlink, 118 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 119 max_ports, MLXSW_CORE_RESOURCE_PORTS, 120 DEVLINK_RESOURCE_ID_PARENT_TOP, 121 &ports_num_params); 122 } 123 124 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 125 { 126 struct devlink *devlink = priv_to_devlink(mlxsw_core); 127 int err; 128 129 /* Switch ports are numbered from 1 to queried value */ 130 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 131 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 132 MAX_SYSTEM_PORT) + 1; 133 else 134 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 135 136 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 137 sizeof(struct mlxsw_core_port), GFP_KERNEL); 138 if (!mlxsw_core->ports) 139 return -ENOMEM; 140 141 if (!reload) { 142 err = mlxsw_core_resources_ports_register(mlxsw_core); 143 if (err) 144 goto err_resources_ports_register; 145 } 146 atomic_set(&mlxsw_core->active_ports_count, 0); 147 devlink_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 148 mlxsw_ports_occ_get, mlxsw_core); 149 150 return 0; 151 152 err_resources_ports_register: 153 kfree(mlxsw_core->ports); 154 return err; 155 } 156 157 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 158 { 159 struct devlink *devlink = priv_to_devlink(mlxsw_core); 160 161 devlink_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 162 if (!reload) 163 devlink_resources_unregister(priv_to_devlink(mlxsw_core)); 164 165 kfree(mlxsw_core->ports); 166 } 167 168 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 169 { 170 return mlxsw_core->max_ports; 171 } 172 EXPORT_SYMBOL(mlxsw_core_max_ports); 173 174 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 175 { 176 return mlxsw_core->driver_priv; 177 } 178 EXPORT_SYMBOL(mlxsw_core_driver_priv); 179 180 bool mlxsw_core_res_query_enabled(const struct mlxsw_core *mlxsw_core) 181 { 182 return mlxsw_core->driver->res_query_enabled; 183 } 184 EXPORT_SYMBOL(mlxsw_core_res_query_enabled); 185 186 bool mlxsw_core_temp_warn_enabled(const struct mlxsw_core *mlxsw_core) 187 { 188 return mlxsw_core->driver->temp_warn_enabled; 189 } 190 191 bool 192 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 193 const struct mlxsw_fw_rev *req_rev) 194 { 195 return rev->minor > req_rev->minor || 196 (rev->minor == req_rev->minor && 197 rev->subminor >= req_rev->subminor); 198 } 199 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 200 201 struct mlxsw_rx_listener_item { 202 struct list_head list; 203 struct mlxsw_rx_listener rxl; 204 void *priv; 205 bool enabled; 206 }; 207 208 struct mlxsw_event_listener_item { 209 struct list_head list; 210 struct mlxsw_core *mlxsw_core; 211 struct mlxsw_event_listener el; 212 void *priv; 213 }; 214 215 /****************** 216 * EMAD processing 217 ******************/ 218 219 /* emad_eth_hdr_dmac 220 * Destination MAC in EMAD's Ethernet header. 221 * Must be set to 01:02:c9:00:00:01 222 */ 223 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 224 225 /* emad_eth_hdr_smac 226 * Source MAC in EMAD's Ethernet header. 227 * Must be set to 00:02:c9:01:02:03 228 */ 229 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 230 231 /* emad_eth_hdr_ethertype 232 * Ethertype in EMAD's Ethernet header. 233 * Must be set to 0x8932 234 */ 235 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 236 237 /* emad_eth_hdr_mlx_proto 238 * Mellanox protocol. 239 * Must be set to 0x0. 240 */ 241 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 242 243 /* emad_eth_hdr_ver 244 * Mellanox protocol version. 245 * Must be set to 0x0. 246 */ 247 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 248 249 /* emad_op_tlv_type 250 * Type of the TLV. 251 * Must be set to 0x1 (operation TLV). 252 */ 253 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 254 255 /* emad_op_tlv_len 256 * Length of the operation TLV in u32. 257 * Must be set to 0x4. 258 */ 259 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 260 261 /* emad_op_tlv_dr 262 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 263 * EMAD. DR TLV must follow. 264 * 265 * Note: Currently not supported and must not be set. 266 */ 267 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 268 269 /* emad_op_tlv_status 270 * Returned status in case of EMAD response. Must be set to 0 in case 271 * of EMAD request. 272 * 0x0 - success 273 * 0x1 - device is busy. Requester should retry 274 * 0x2 - Mellanox protocol version not supported 275 * 0x3 - unknown TLV 276 * 0x4 - register not supported 277 * 0x5 - operation class not supported 278 * 0x6 - EMAD method not supported 279 * 0x7 - bad parameter (e.g. port out of range) 280 * 0x8 - resource not available 281 * 0x9 - message receipt acknowledgment. Requester should retry 282 * 0x70 - internal error 283 */ 284 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 285 286 /* emad_op_tlv_register_id 287 * Register ID of register within register TLV. 288 */ 289 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 290 291 /* emad_op_tlv_r 292 * Response bit. Setting to 1 indicates Response, otherwise request. 293 */ 294 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 295 296 /* emad_op_tlv_method 297 * EMAD method type. 298 * 0x1 - query 299 * 0x2 - write 300 * 0x3 - send (currently not supported) 301 * 0x4 - event 302 */ 303 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 304 305 /* emad_op_tlv_class 306 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 307 */ 308 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 309 310 /* emad_op_tlv_tid 311 * EMAD transaction ID. Used for pairing request and response EMADs. 312 */ 313 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 314 315 /* emad_string_tlv_type 316 * Type of the TLV. 317 * Must be set to 0x2 (string TLV). 318 */ 319 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 320 321 /* emad_string_tlv_len 322 * Length of the string TLV in u32. 323 */ 324 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 325 326 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 327 328 /* emad_string_tlv_string 329 * String provided by the device's firmware in case of erroneous register access 330 */ 331 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 332 MLXSW_EMAD_STRING_TLV_STRING_LEN); 333 334 /* emad_reg_tlv_type 335 * Type of the TLV. 336 * Must be set to 0x3 (register TLV). 337 */ 338 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 339 340 /* emad_reg_tlv_len 341 * Length of the operation TLV in u32. 342 */ 343 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 344 345 /* emad_end_tlv_type 346 * Type of the TLV. 347 * Must be set to 0x0 (end TLV). 348 */ 349 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 350 351 /* emad_end_tlv_len 352 * Length of the end TLV in u32. 353 * Must be set to 1. 354 */ 355 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 356 357 enum mlxsw_core_reg_access_type { 358 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 359 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 360 }; 361 362 static inline const char * 363 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 364 { 365 switch (type) { 366 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 367 return "query"; 368 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 369 return "write"; 370 } 371 BUG(); 372 } 373 374 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 375 { 376 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 377 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 378 } 379 380 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 381 const struct mlxsw_reg_info *reg, 382 char *payload) 383 { 384 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 385 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 386 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 387 } 388 389 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 390 { 391 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 392 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 393 } 394 395 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 396 const struct mlxsw_reg_info *reg, 397 enum mlxsw_core_reg_access_type type, 398 u64 tid) 399 { 400 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 401 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 402 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 403 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 404 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 405 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 406 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 407 mlxsw_emad_op_tlv_method_set(op_tlv, 408 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 409 else 410 mlxsw_emad_op_tlv_method_set(op_tlv, 411 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 412 mlxsw_emad_op_tlv_class_set(op_tlv, 413 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 414 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 415 } 416 417 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 418 { 419 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 420 421 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 422 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 423 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 424 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 425 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 426 427 skb_reset_mac_header(skb); 428 429 return 0; 430 } 431 432 static void mlxsw_emad_construct(struct sk_buff *skb, 433 const struct mlxsw_reg_info *reg, 434 char *payload, 435 enum mlxsw_core_reg_access_type type, 436 u64 tid, bool enable_string_tlv) 437 { 438 char *buf; 439 440 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 441 mlxsw_emad_pack_end_tlv(buf); 442 443 buf = skb_push(skb, reg->len + sizeof(u32)); 444 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 445 446 if (enable_string_tlv) { 447 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 448 mlxsw_emad_pack_string_tlv(buf); 449 } 450 451 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 452 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 453 454 mlxsw_emad_construct_eth_hdr(skb); 455 } 456 457 struct mlxsw_emad_tlv_offsets { 458 u16 op_tlv; 459 u16 string_tlv; 460 u16 reg_tlv; 461 }; 462 463 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 464 { 465 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 466 467 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 468 } 469 470 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 471 { 472 struct mlxsw_emad_tlv_offsets *offsets = 473 (struct mlxsw_emad_tlv_offsets *) skb->cb; 474 475 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 476 offsets->string_tlv = 0; 477 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 478 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 479 480 /* If string TLV is present, it must come after the operation TLV. */ 481 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 482 offsets->string_tlv = offsets->reg_tlv; 483 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 484 } 485 } 486 487 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 488 { 489 struct mlxsw_emad_tlv_offsets *offsets = 490 (struct mlxsw_emad_tlv_offsets *) skb->cb; 491 492 return ((char *) (skb->data + offsets->op_tlv)); 493 } 494 495 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 496 { 497 struct mlxsw_emad_tlv_offsets *offsets = 498 (struct mlxsw_emad_tlv_offsets *) skb->cb; 499 500 if (!offsets->string_tlv) 501 return NULL; 502 503 return ((char *) (skb->data + offsets->string_tlv)); 504 } 505 506 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 507 { 508 struct mlxsw_emad_tlv_offsets *offsets = 509 (struct mlxsw_emad_tlv_offsets *) skb->cb; 510 511 return ((char *) (skb->data + offsets->reg_tlv)); 512 } 513 514 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 515 { 516 return ((char *) (reg_tlv + sizeof(u32))); 517 } 518 519 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 520 { 521 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 522 } 523 524 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 525 { 526 char *op_tlv; 527 528 op_tlv = mlxsw_emad_op_tlv(skb); 529 return mlxsw_emad_op_tlv_tid_get(op_tlv); 530 } 531 532 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 533 { 534 char *op_tlv; 535 536 op_tlv = mlxsw_emad_op_tlv(skb); 537 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 538 } 539 540 static int mlxsw_emad_process_status(char *op_tlv, 541 enum mlxsw_emad_op_tlv_status *p_status) 542 { 543 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 544 545 switch (*p_status) { 546 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 547 return 0; 548 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 549 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 550 return -EAGAIN; 551 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 552 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 553 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 554 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 555 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 556 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 557 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 558 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 559 default: 560 return -EIO; 561 } 562 } 563 564 static int 565 mlxsw_emad_process_status_skb(struct sk_buff *skb, 566 enum mlxsw_emad_op_tlv_status *p_status) 567 { 568 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 569 } 570 571 struct mlxsw_reg_trans { 572 struct list_head list; 573 struct list_head bulk_list; 574 struct mlxsw_core *core; 575 struct sk_buff *tx_skb; 576 struct mlxsw_tx_info tx_info; 577 struct delayed_work timeout_dw; 578 unsigned int retries; 579 u64 tid; 580 struct completion completion; 581 atomic_t active; 582 mlxsw_reg_trans_cb_t *cb; 583 unsigned long cb_priv; 584 const struct mlxsw_reg_info *reg; 585 enum mlxsw_core_reg_access_type type; 586 int err; 587 char *emad_err_string; 588 enum mlxsw_emad_op_tlv_status emad_status; 589 struct rcu_head rcu; 590 }; 591 592 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 593 struct mlxsw_reg_trans *trans) 594 { 595 char *string_tlv; 596 char *string; 597 598 string_tlv = mlxsw_emad_string_tlv(skb); 599 if (!string_tlv) 600 return; 601 602 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 603 GFP_ATOMIC); 604 if (!trans->emad_err_string) 605 return; 606 607 string = mlxsw_emad_string_tlv_string_data(string_tlv); 608 strlcpy(trans->emad_err_string, string, 609 MLXSW_EMAD_STRING_TLV_STRING_LEN); 610 } 611 612 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 613 #define MLXSW_EMAD_TIMEOUT_MS 200 614 615 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 616 { 617 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 618 619 if (trans->core->fw_flash_in_progress) 620 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 621 622 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 623 timeout << trans->retries); 624 } 625 626 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 627 struct mlxsw_reg_trans *trans) 628 { 629 struct sk_buff *skb; 630 int err; 631 632 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 633 if (!skb) 634 return -ENOMEM; 635 636 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 637 skb->data + mlxsw_core->driver->txhdr_len, 638 skb->len - mlxsw_core->driver->txhdr_len); 639 640 atomic_set(&trans->active, 1); 641 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 642 if (err) { 643 dev_kfree_skb(skb); 644 return err; 645 } 646 mlxsw_emad_trans_timeout_schedule(trans); 647 return 0; 648 } 649 650 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 651 { 652 struct mlxsw_core *mlxsw_core = trans->core; 653 654 dev_kfree_skb(trans->tx_skb); 655 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 656 list_del_rcu(&trans->list); 657 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 658 trans->err = err; 659 complete(&trans->completion); 660 } 661 662 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 663 struct mlxsw_reg_trans *trans) 664 { 665 int err; 666 667 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 668 trans->retries++; 669 err = mlxsw_emad_transmit(trans->core, trans); 670 if (err == 0) 671 return; 672 673 if (!atomic_dec_and_test(&trans->active)) 674 return; 675 } else { 676 err = -EIO; 677 } 678 mlxsw_emad_trans_finish(trans, err); 679 } 680 681 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 682 { 683 struct mlxsw_reg_trans *trans = container_of(work, 684 struct mlxsw_reg_trans, 685 timeout_dw.work); 686 687 if (!atomic_dec_and_test(&trans->active)) 688 return; 689 690 mlxsw_emad_transmit_retry(trans->core, trans); 691 } 692 693 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 694 struct mlxsw_reg_trans *trans, 695 struct sk_buff *skb) 696 { 697 int err; 698 699 if (!atomic_dec_and_test(&trans->active)) 700 return; 701 702 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 703 if (err == -EAGAIN) { 704 mlxsw_emad_transmit_retry(mlxsw_core, trans); 705 } else { 706 if (err == 0) { 707 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 708 709 if (trans->cb) 710 trans->cb(mlxsw_core, 711 mlxsw_emad_reg_payload(reg_tlv), 712 trans->reg->len, trans->cb_priv); 713 } else { 714 mlxsw_emad_process_string_tlv(skb, trans); 715 } 716 mlxsw_emad_trans_finish(trans, err); 717 } 718 } 719 720 /* called with rcu read lock held */ 721 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, 722 void *priv) 723 { 724 struct mlxsw_core *mlxsw_core = priv; 725 struct mlxsw_reg_trans *trans; 726 727 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 728 skb->data, skb->len); 729 730 mlxsw_emad_tlv_parse(skb); 731 732 if (!mlxsw_emad_is_resp(skb)) 733 goto free_skb; 734 735 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 736 if (mlxsw_emad_get_tid(skb) == trans->tid) { 737 mlxsw_emad_process_response(mlxsw_core, trans, skb); 738 break; 739 } 740 } 741 742 free_skb: 743 dev_kfree_skb(skb); 744 } 745 746 static const struct mlxsw_listener mlxsw_emad_rx_listener = 747 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 748 EMAD, DISCARD); 749 750 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 751 { 752 struct workqueue_struct *emad_wq; 753 u64 tid; 754 int err; 755 756 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 757 return 0; 758 759 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 760 if (!emad_wq) 761 return -ENOMEM; 762 mlxsw_core->emad_wq = emad_wq; 763 764 /* Set the upper 32 bits of the transaction ID field to a random 765 * number. This allows us to discard EMADs addressed to other 766 * devices. 767 */ 768 get_random_bytes(&tid, 4); 769 tid <<= 32; 770 atomic64_set(&mlxsw_core->emad.tid, tid); 771 772 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 773 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 774 775 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 776 mlxsw_core); 777 if (err) 778 goto err_trap_register; 779 780 err = mlxsw_core->driver->basic_trap_groups_set(mlxsw_core); 781 if (err) 782 goto err_emad_trap_set; 783 mlxsw_core->emad.use_emad = true; 784 785 return 0; 786 787 err_emad_trap_set: 788 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 789 mlxsw_core); 790 err_trap_register: 791 destroy_workqueue(mlxsw_core->emad_wq); 792 return err; 793 } 794 795 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 796 { 797 798 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 799 return; 800 801 mlxsw_core->emad.use_emad = false; 802 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 803 mlxsw_core); 804 destroy_workqueue(mlxsw_core->emad_wq); 805 } 806 807 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 808 u16 reg_len, bool enable_string_tlv) 809 { 810 struct sk_buff *skb; 811 u16 emad_len; 812 813 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 814 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 815 sizeof(u32) + mlxsw_core->driver->txhdr_len); 816 if (enable_string_tlv) 817 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 818 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 819 return NULL; 820 821 skb = netdev_alloc_skb(NULL, emad_len); 822 if (!skb) 823 return NULL; 824 memset(skb->data, 0, emad_len); 825 skb_reserve(skb, emad_len); 826 827 return skb; 828 } 829 830 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 831 const struct mlxsw_reg_info *reg, 832 char *payload, 833 enum mlxsw_core_reg_access_type type, 834 struct mlxsw_reg_trans *trans, 835 struct list_head *bulk_list, 836 mlxsw_reg_trans_cb_t *cb, 837 unsigned long cb_priv, u64 tid) 838 { 839 bool enable_string_tlv; 840 struct sk_buff *skb; 841 int err; 842 843 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 844 tid, reg->id, mlxsw_reg_id_str(reg->id), 845 mlxsw_core_reg_access_type_str(type)); 846 847 /* Since this can be changed during emad_reg_access, read it once and 848 * use the value all the way. 849 */ 850 enable_string_tlv = mlxsw_core->emad.enable_string_tlv; 851 852 skb = mlxsw_emad_alloc(mlxsw_core, reg->len, enable_string_tlv); 853 if (!skb) 854 return -ENOMEM; 855 856 list_add_tail(&trans->bulk_list, bulk_list); 857 trans->core = mlxsw_core; 858 trans->tx_skb = skb; 859 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 860 trans->tx_info.is_emad = true; 861 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 862 trans->tid = tid; 863 init_completion(&trans->completion); 864 trans->cb = cb; 865 trans->cb_priv = cb_priv; 866 trans->reg = reg; 867 trans->type = type; 868 869 mlxsw_emad_construct(skb, reg, payload, type, trans->tid, 870 enable_string_tlv); 871 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 872 873 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 874 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 875 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 876 err = mlxsw_emad_transmit(mlxsw_core, trans); 877 if (err) 878 goto err_out; 879 return 0; 880 881 err_out: 882 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 883 list_del_rcu(&trans->list); 884 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 885 list_del(&trans->bulk_list); 886 dev_kfree_skb(trans->tx_skb); 887 return err; 888 } 889 890 /***************** 891 * Core functions 892 *****************/ 893 894 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 895 { 896 spin_lock(&mlxsw_core_driver_list_lock); 897 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 898 spin_unlock(&mlxsw_core_driver_list_lock); 899 return 0; 900 } 901 EXPORT_SYMBOL(mlxsw_core_driver_register); 902 903 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 904 { 905 spin_lock(&mlxsw_core_driver_list_lock); 906 list_del(&mlxsw_driver->list); 907 spin_unlock(&mlxsw_core_driver_list_lock); 908 } 909 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 910 911 static struct mlxsw_driver *__driver_find(const char *kind) 912 { 913 struct mlxsw_driver *mlxsw_driver; 914 915 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 916 if (strcmp(mlxsw_driver->kind, kind) == 0) 917 return mlxsw_driver; 918 } 919 return NULL; 920 } 921 922 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 923 { 924 struct mlxsw_driver *mlxsw_driver; 925 926 spin_lock(&mlxsw_core_driver_list_lock); 927 mlxsw_driver = __driver_find(kind); 928 spin_unlock(&mlxsw_core_driver_list_lock); 929 return mlxsw_driver; 930 } 931 932 struct mlxsw_core_fw_info { 933 struct mlxfw_dev mlxfw_dev; 934 struct mlxsw_core *mlxsw_core; 935 }; 936 937 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 938 u16 component_index, u32 *p_max_size, 939 u8 *p_align_bits, u16 *p_max_write_size) 940 { 941 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 942 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 943 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 944 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 945 int err; 946 947 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 948 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 949 if (err) 950 return err; 951 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 952 953 *p_align_bits = max_t(u8, *p_align_bits, 2); 954 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 955 return 0; 956 } 957 958 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 959 { 960 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 961 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 962 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 963 char mcc_pl[MLXSW_REG_MCC_LEN]; 964 u8 control_state; 965 int err; 966 967 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 968 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 969 if (err) 970 return err; 971 972 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 973 if (control_state != MLXFW_FSM_STATE_IDLE) 974 return -EBUSY; 975 976 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 977 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 978 } 979 980 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 981 u16 component_index, u32 component_size) 982 { 983 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 984 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 985 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 986 char mcc_pl[MLXSW_REG_MCC_LEN]; 987 988 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 989 component_index, fwhandle, component_size); 990 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 991 } 992 993 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 994 u8 *data, u16 size, u32 offset) 995 { 996 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 997 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 998 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 999 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1000 1001 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1002 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1003 } 1004 1005 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1006 u16 component_index) 1007 { 1008 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1009 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1010 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1011 char mcc_pl[MLXSW_REG_MCC_LEN]; 1012 1013 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1014 component_index, fwhandle, 0); 1015 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1016 } 1017 1018 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1019 { 1020 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1021 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1022 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1023 char mcc_pl[MLXSW_REG_MCC_LEN]; 1024 1025 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1026 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1027 } 1028 1029 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1030 enum mlxfw_fsm_state *fsm_state, 1031 enum mlxfw_fsm_state_err *fsm_state_err) 1032 { 1033 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1034 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1035 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1036 char mcc_pl[MLXSW_REG_MCC_LEN]; 1037 u8 control_state; 1038 u8 error_code; 1039 int err; 1040 1041 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1042 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1043 if (err) 1044 return err; 1045 1046 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1047 *fsm_state = control_state; 1048 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1049 return 0; 1050 } 1051 1052 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1053 { 1054 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1055 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1056 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1057 char mcc_pl[MLXSW_REG_MCC_LEN]; 1058 1059 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1060 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1061 } 1062 1063 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1064 { 1065 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1066 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1067 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1068 char mcc_pl[MLXSW_REG_MCC_LEN]; 1069 1070 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1071 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1072 } 1073 1074 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1075 .component_query = mlxsw_core_fw_component_query, 1076 .fsm_lock = mlxsw_core_fw_fsm_lock, 1077 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1078 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1079 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1080 .fsm_activate = mlxsw_core_fw_fsm_activate, 1081 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1082 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1083 .fsm_release = mlxsw_core_fw_fsm_release, 1084 }; 1085 1086 static int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, const struct firmware *firmware, 1087 struct netlink_ext_ack *extack) 1088 { 1089 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1090 .mlxfw_dev = { 1091 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1092 .psid = mlxsw_core->bus_info->psid, 1093 .psid_size = strlen(mlxsw_core->bus_info->psid), 1094 .devlink = priv_to_devlink(mlxsw_core), 1095 }, 1096 .mlxsw_core = mlxsw_core 1097 }; 1098 int err; 1099 1100 mlxsw_core->fw_flash_in_progress = true; 1101 err = mlxfw_firmware_flash(&mlxsw_core_fw_info.mlxfw_dev, firmware, extack); 1102 mlxsw_core->fw_flash_in_progress = false; 1103 1104 return err; 1105 } 1106 1107 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1108 const struct mlxsw_bus_info *mlxsw_bus_info, 1109 const struct mlxsw_fw_rev *req_rev, 1110 const char *filename) 1111 { 1112 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1113 union devlink_param_value value; 1114 const struct firmware *firmware; 1115 int err; 1116 1117 /* Don't check if driver does not require it */ 1118 if (!req_rev || !filename) 1119 return 0; 1120 1121 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1122 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1123 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1124 &value); 1125 if (err) 1126 return err; 1127 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1128 return 0; 1129 1130 /* Validate driver & FW are compatible */ 1131 if (rev->major != req_rev->major) { 1132 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1133 rev->major, req_rev->major); 1134 return -EINVAL; 1135 } 1136 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1137 return 0; 1138 1139 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1140 rev->major, rev->minor, rev->subminor, req_rev->major, 1141 req_rev->minor, req_rev->subminor); 1142 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1143 1144 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1145 if (err) { 1146 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1147 return err; 1148 } 1149 1150 err = mlxsw_core_fw_flash(mlxsw_core, firmware, NULL); 1151 release_firmware(firmware); 1152 if (err) 1153 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1154 1155 /* On FW flash success, tell the caller FW reset is needed 1156 * if current FW supports it. 1157 */ 1158 if (rev->minor >= req_rev->can_reset_minor) 1159 return err ? err : -EAGAIN; 1160 else 1161 return 0; 1162 } 1163 1164 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1165 struct devlink_flash_update_params *params, 1166 struct netlink_ext_ack *extack) 1167 { 1168 return mlxsw_core_fw_flash(mlxsw_core, params->fw, extack); 1169 } 1170 1171 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1172 union devlink_param_value val, 1173 struct netlink_ext_ack *extack) 1174 { 1175 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1176 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1177 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1178 return -EINVAL; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1185 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1186 mlxsw_core_devlink_param_fw_load_policy_validate), 1187 }; 1188 1189 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1190 { 1191 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1192 union devlink_param_value value; 1193 int err; 1194 1195 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1196 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1197 if (err) 1198 return err; 1199 1200 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1201 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1202 return 0; 1203 } 1204 1205 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1206 { 1207 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1208 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1209 } 1210 1211 static int mlxsw_devlink_port_split(struct devlink *devlink, 1212 unsigned int port_index, 1213 unsigned int count, 1214 struct netlink_ext_ack *extack) 1215 { 1216 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1217 1218 if (port_index >= mlxsw_core->max_ports) { 1219 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1220 return -EINVAL; 1221 } 1222 if (!mlxsw_core->driver->port_split) 1223 return -EOPNOTSUPP; 1224 return mlxsw_core->driver->port_split(mlxsw_core, port_index, count, 1225 extack); 1226 } 1227 1228 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1229 unsigned int port_index, 1230 struct netlink_ext_ack *extack) 1231 { 1232 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1233 1234 if (port_index >= mlxsw_core->max_ports) { 1235 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1236 return -EINVAL; 1237 } 1238 if (!mlxsw_core->driver->port_unsplit) 1239 return -EOPNOTSUPP; 1240 return mlxsw_core->driver->port_unsplit(mlxsw_core, port_index, 1241 extack); 1242 } 1243 1244 static int 1245 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1246 unsigned int sb_index, u16 pool_index, 1247 struct devlink_sb_pool_info *pool_info) 1248 { 1249 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1250 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1251 1252 if (!mlxsw_driver->sb_pool_get) 1253 return -EOPNOTSUPP; 1254 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1255 pool_index, pool_info); 1256 } 1257 1258 static int 1259 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1260 unsigned int sb_index, u16 pool_index, u32 size, 1261 enum devlink_sb_threshold_type threshold_type, 1262 struct netlink_ext_ack *extack) 1263 { 1264 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1265 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1266 1267 if (!mlxsw_driver->sb_pool_set) 1268 return -EOPNOTSUPP; 1269 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1270 pool_index, size, threshold_type, 1271 extack); 1272 } 1273 1274 static void *__dl_port(struct devlink_port *devlink_port) 1275 { 1276 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1277 } 1278 1279 static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port, 1280 enum devlink_port_type port_type) 1281 { 1282 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1283 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1284 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1285 1286 if (!mlxsw_driver->port_type_set) 1287 return -EOPNOTSUPP; 1288 1289 return mlxsw_driver->port_type_set(mlxsw_core, 1290 mlxsw_core_port->local_port, 1291 port_type); 1292 } 1293 1294 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1295 unsigned int sb_index, u16 pool_index, 1296 u32 *p_threshold) 1297 { 1298 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1299 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1300 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1301 1302 if (!mlxsw_driver->sb_port_pool_get || 1303 !mlxsw_core_port_check(mlxsw_core_port)) 1304 return -EOPNOTSUPP; 1305 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1306 pool_index, p_threshold); 1307 } 1308 1309 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1310 unsigned int sb_index, u16 pool_index, 1311 u32 threshold, 1312 struct netlink_ext_ack *extack) 1313 { 1314 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1315 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1316 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1317 1318 if (!mlxsw_driver->sb_port_pool_set || 1319 !mlxsw_core_port_check(mlxsw_core_port)) 1320 return -EOPNOTSUPP; 1321 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1322 pool_index, threshold, extack); 1323 } 1324 1325 static int 1326 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1327 unsigned int sb_index, u16 tc_index, 1328 enum devlink_sb_pool_type pool_type, 1329 u16 *p_pool_index, u32 *p_threshold) 1330 { 1331 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1332 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1333 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1334 1335 if (!mlxsw_driver->sb_tc_pool_bind_get || 1336 !mlxsw_core_port_check(mlxsw_core_port)) 1337 return -EOPNOTSUPP; 1338 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1339 tc_index, pool_type, 1340 p_pool_index, p_threshold); 1341 } 1342 1343 static int 1344 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1345 unsigned int sb_index, u16 tc_index, 1346 enum devlink_sb_pool_type pool_type, 1347 u16 pool_index, u32 threshold, 1348 struct netlink_ext_ack *extack) 1349 { 1350 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1351 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1352 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1353 1354 if (!mlxsw_driver->sb_tc_pool_bind_set || 1355 !mlxsw_core_port_check(mlxsw_core_port)) 1356 return -EOPNOTSUPP; 1357 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1358 tc_index, pool_type, 1359 pool_index, threshold, extack); 1360 } 1361 1362 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1363 unsigned int sb_index) 1364 { 1365 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1366 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1367 1368 if (!mlxsw_driver->sb_occ_snapshot) 1369 return -EOPNOTSUPP; 1370 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1371 } 1372 1373 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1374 unsigned int sb_index) 1375 { 1376 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1377 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1378 1379 if (!mlxsw_driver->sb_occ_max_clear) 1380 return -EOPNOTSUPP; 1381 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1382 } 1383 1384 static int 1385 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1386 unsigned int sb_index, u16 pool_index, 1387 u32 *p_cur, u32 *p_max) 1388 { 1389 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1390 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1391 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1392 1393 if (!mlxsw_driver->sb_occ_port_pool_get || 1394 !mlxsw_core_port_check(mlxsw_core_port)) 1395 return -EOPNOTSUPP; 1396 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1397 pool_index, p_cur, p_max); 1398 } 1399 1400 static int 1401 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1402 unsigned int sb_index, u16 tc_index, 1403 enum devlink_sb_pool_type pool_type, 1404 u32 *p_cur, u32 *p_max) 1405 { 1406 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1407 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1408 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1409 1410 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1411 !mlxsw_core_port_check(mlxsw_core_port)) 1412 return -EOPNOTSUPP; 1413 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1414 sb_index, tc_index, 1415 pool_type, p_cur, p_max); 1416 } 1417 1418 static int 1419 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1420 struct netlink_ext_ack *extack) 1421 { 1422 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1423 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1424 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1425 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1426 char buf[32]; 1427 int err; 1428 1429 err = devlink_info_driver_name_put(req, 1430 mlxsw_core->bus_info->device_kind); 1431 if (err) 1432 return err; 1433 1434 mlxsw_reg_mgir_pack(mgir_pl); 1435 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1436 if (err) 1437 return err; 1438 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1439 &fw_minor, &fw_sub_minor); 1440 1441 sprintf(buf, "%X", hw_rev); 1442 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1443 if (err) 1444 return err; 1445 1446 err = devlink_info_version_fixed_put(req, 1447 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1448 fw_info_psid); 1449 if (err) 1450 return err; 1451 1452 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1453 err = devlink_info_version_running_put(req, "fw.version", buf); 1454 if (err) 1455 return err; 1456 1457 return devlink_info_version_running_put(req, 1458 DEVLINK_INFO_VERSION_GENERIC_FW, 1459 buf); 1460 } 1461 1462 static int 1463 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1464 bool netns_change, enum devlink_reload_action action, 1465 enum devlink_reload_limit limit, 1466 struct netlink_ext_ack *extack) 1467 { 1468 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1469 1470 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1471 return -EOPNOTSUPP; 1472 1473 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1474 return 0; 1475 } 1476 1477 static int 1478 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1479 enum devlink_reload_limit limit, u32 *actions_performed, 1480 struct netlink_ext_ack *extack) 1481 { 1482 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1483 1484 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1485 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1486 return mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1487 mlxsw_core->bus, 1488 mlxsw_core->bus_priv, true, 1489 devlink, extack); 1490 } 1491 1492 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1493 struct devlink_flash_update_params *params, 1494 struct netlink_ext_ack *extack) 1495 { 1496 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1497 1498 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1499 } 1500 1501 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1502 const struct devlink_trap *trap, 1503 void *trap_ctx) 1504 { 1505 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1506 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1507 1508 if (!mlxsw_driver->trap_init) 1509 return -EOPNOTSUPP; 1510 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1511 } 1512 1513 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1514 const struct devlink_trap *trap, 1515 void *trap_ctx) 1516 { 1517 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1518 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1519 1520 if (!mlxsw_driver->trap_fini) 1521 return; 1522 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1523 } 1524 1525 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1526 const struct devlink_trap *trap, 1527 enum devlink_trap_action action, 1528 struct netlink_ext_ack *extack) 1529 { 1530 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1531 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1532 1533 if (!mlxsw_driver->trap_action_set) 1534 return -EOPNOTSUPP; 1535 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1536 } 1537 1538 static int 1539 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1540 const struct devlink_trap_group *group) 1541 { 1542 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1543 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1544 1545 if (!mlxsw_driver->trap_group_init) 1546 return -EOPNOTSUPP; 1547 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1548 } 1549 1550 static int 1551 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1552 const struct devlink_trap_group *group, 1553 const struct devlink_trap_policer *policer, 1554 struct netlink_ext_ack *extack) 1555 { 1556 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1557 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1558 1559 if (!mlxsw_driver->trap_group_set) 1560 return -EOPNOTSUPP; 1561 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1562 } 1563 1564 static int 1565 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1566 const struct devlink_trap_policer *policer) 1567 { 1568 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1569 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1570 1571 if (!mlxsw_driver->trap_policer_init) 1572 return -EOPNOTSUPP; 1573 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1574 } 1575 1576 static void 1577 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1578 const struct devlink_trap_policer *policer) 1579 { 1580 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1581 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1582 1583 if (!mlxsw_driver->trap_policer_fini) 1584 return; 1585 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1586 } 1587 1588 static int 1589 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1590 const struct devlink_trap_policer *policer, 1591 u64 rate, u64 burst, 1592 struct netlink_ext_ack *extack) 1593 { 1594 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1595 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1596 1597 if (!mlxsw_driver->trap_policer_set) 1598 return -EOPNOTSUPP; 1599 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1600 extack); 1601 } 1602 1603 static int 1604 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1605 const struct devlink_trap_policer *policer, 1606 u64 *p_drops) 1607 { 1608 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1609 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1610 1611 if (!mlxsw_driver->trap_policer_counter_get) 1612 return -EOPNOTSUPP; 1613 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1614 p_drops); 1615 } 1616 1617 static const struct devlink_ops mlxsw_devlink_ops = { 1618 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1619 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1620 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1621 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1622 .port_type_set = mlxsw_devlink_port_type_set, 1623 .port_split = mlxsw_devlink_port_split, 1624 .port_unsplit = mlxsw_devlink_port_unsplit, 1625 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1626 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1627 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1628 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1629 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1630 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1631 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1632 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1633 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1634 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1635 .info_get = mlxsw_devlink_info_get, 1636 .flash_update = mlxsw_devlink_flash_update, 1637 .trap_init = mlxsw_devlink_trap_init, 1638 .trap_fini = mlxsw_devlink_trap_fini, 1639 .trap_action_set = mlxsw_devlink_trap_action_set, 1640 .trap_group_init = mlxsw_devlink_trap_group_init, 1641 .trap_group_set = mlxsw_devlink_trap_group_set, 1642 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1643 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1644 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1645 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1646 }; 1647 1648 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1649 { 1650 int err; 1651 1652 err = mlxsw_core_fw_params_register(mlxsw_core); 1653 if (err) 1654 return err; 1655 1656 if (mlxsw_core->driver->params_register) { 1657 err = mlxsw_core->driver->params_register(mlxsw_core); 1658 if (err) 1659 goto err_params_register; 1660 } 1661 return 0; 1662 1663 err_params_register: 1664 mlxsw_core_fw_params_unregister(mlxsw_core); 1665 return err; 1666 } 1667 1668 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1669 { 1670 mlxsw_core_fw_params_unregister(mlxsw_core); 1671 if (mlxsw_core->driver->params_register) 1672 mlxsw_core->driver->params_unregister(mlxsw_core); 1673 } 1674 1675 struct mlxsw_core_health_event { 1676 struct mlxsw_core *mlxsw_core; 1677 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1678 struct work_struct work; 1679 }; 1680 1681 static void mlxsw_core_health_event_work(struct work_struct *work) 1682 { 1683 struct mlxsw_core_health_event *event; 1684 struct mlxsw_core *mlxsw_core; 1685 1686 event = container_of(work, struct mlxsw_core_health_event, work); 1687 mlxsw_core = event->mlxsw_core; 1688 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1689 event->mfde_pl); 1690 kfree(event); 1691 } 1692 1693 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1694 char *mfde_pl, void *priv) 1695 { 1696 struct mlxsw_core_health_event *event; 1697 struct mlxsw_core *mlxsw_core = priv; 1698 1699 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1700 if (!event) 1701 return; 1702 event->mlxsw_core = mlxsw_core; 1703 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1704 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1705 mlxsw_core_schedule_work(&event->work); 1706 } 1707 1708 static const struct mlxsw_listener mlxsw_core_health_listener = 1709 MLXSW_EVENTL(mlxsw_core_health_listener_func, MFDE, MFDE); 1710 1711 static int 1712 mlxsw_core_health_fw_fatal_dump_fatal_cause(const char *mfde_pl, 1713 struct devlink_fmsg *fmsg) 1714 { 1715 u32 val, tile_v; 1716 int err; 1717 1718 val = mlxsw_reg_mfde_fatal_cause_id_get(mfde_pl); 1719 err = devlink_fmsg_u32_pair_put(fmsg, "cause_id", val); 1720 if (err) 1721 return err; 1722 tile_v = mlxsw_reg_mfde_fatal_cause_tile_v_get(mfde_pl); 1723 if (tile_v) { 1724 val = mlxsw_reg_mfde_fatal_cause_tile_index_get(mfde_pl); 1725 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1726 if (err) 1727 return err; 1728 } 1729 1730 return 0; 1731 } 1732 1733 static int 1734 mlxsw_core_health_fw_fatal_dump_fw_assert(const char *mfde_pl, 1735 struct devlink_fmsg *fmsg) 1736 { 1737 u32 val, tile_v; 1738 int err; 1739 1740 val = mlxsw_reg_mfde_fw_assert_var0_get(mfde_pl); 1741 err = devlink_fmsg_u32_pair_put(fmsg, "var0", val); 1742 if (err) 1743 return err; 1744 val = mlxsw_reg_mfde_fw_assert_var1_get(mfde_pl); 1745 err = devlink_fmsg_u32_pair_put(fmsg, "var1", val); 1746 if (err) 1747 return err; 1748 val = mlxsw_reg_mfde_fw_assert_var2_get(mfde_pl); 1749 err = devlink_fmsg_u32_pair_put(fmsg, "var2", val); 1750 if (err) 1751 return err; 1752 val = mlxsw_reg_mfde_fw_assert_var3_get(mfde_pl); 1753 err = devlink_fmsg_u32_pair_put(fmsg, "var3", val); 1754 if (err) 1755 return err; 1756 val = mlxsw_reg_mfde_fw_assert_var4_get(mfde_pl); 1757 err = devlink_fmsg_u32_pair_put(fmsg, "var4", val); 1758 if (err) 1759 return err; 1760 val = mlxsw_reg_mfde_fw_assert_existptr_get(mfde_pl); 1761 err = devlink_fmsg_u32_pair_put(fmsg, "existptr", val); 1762 if (err) 1763 return err; 1764 val = mlxsw_reg_mfde_fw_assert_callra_get(mfde_pl); 1765 err = devlink_fmsg_u32_pair_put(fmsg, "callra", val); 1766 if (err) 1767 return err; 1768 val = mlxsw_reg_mfde_fw_assert_oe_get(mfde_pl); 1769 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1770 if (err) 1771 return err; 1772 tile_v = mlxsw_reg_mfde_fw_assert_tile_v_get(mfde_pl); 1773 if (tile_v) { 1774 val = mlxsw_reg_mfde_fw_assert_tile_index_get(mfde_pl); 1775 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1776 if (err) 1777 return err; 1778 } 1779 val = mlxsw_reg_mfde_fw_assert_ext_synd_get(mfde_pl); 1780 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", val); 1781 if (err) 1782 return err; 1783 1784 return 0; 1785 } 1786 1787 static int 1788 mlxsw_core_health_fw_fatal_dump_kvd_im_stop(const char *mfde_pl, 1789 struct devlink_fmsg *fmsg) 1790 { 1791 u32 val; 1792 int err; 1793 1794 val = mlxsw_reg_mfde_kvd_im_stop_oe_get(mfde_pl); 1795 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1796 if (err) 1797 return err; 1798 val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl); 1799 return devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1800 } 1801 1802 static int 1803 mlxsw_core_health_fw_fatal_dump_crspace_to(const char *mfde_pl, 1804 struct devlink_fmsg *fmsg) 1805 { 1806 u32 val; 1807 int err; 1808 1809 val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl); 1810 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1811 if (err) 1812 return err; 1813 val = mlxsw_reg_mfde_crspace_to_oe_get(mfde_pl); 1814 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1815 if (err) 1816 return err; 1817 val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl); 1818 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1819 if (err) 1820 return err; 1821 val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl); 1822 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1823 if (err) 1824 return err; 1825 1826 return 0; 1827 } 1828 1829 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1830 struct devlink_fmsg *fmsg, void *priv_ctx, 1831 struct netlink_ext_ack *extack) 1832 { 1833 char *mfde_pl = priv_ctx; 1834 char *val_str; 1835 u8 event_id; 1836 u32 val; 1837 int err; 1838 1839 if (!priv_ctx) 1840 /* User-triggered dumps are not possible */ 1841 return -EOPNOTSUPP; 1842 1843 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1844 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1845 if (err) 1846 return err; 1847 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1848 if (err) 1849 return err; 1850 1851 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1852 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1853 if (err) 1854 return err; 1855 switch (event_id) { 1856 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1857 val_str = "CR space timeout"; 1858 break; 1859 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1860 val_str = "KVD insertion machine stopped"; 1861 break; 1862 case MLXSW_REG_MFDE_EVENT_ID_TEST: 1863 val_str = "Test"; 1864 break; 1865 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1866 val_str = "FW assert"; 1867 break; 1868 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1869 val_str = "Fatal cause"; 1870 break; 1871 default: 1872 val_str = NULL; 1873 } 1874 if (val_str) { 1875 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1876 if (err) 1877 return err; 1878 } 1879 1880 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1881 if (err) 1882 return err; 1883 1884 err = devlink_fmsg_arr_pair_nest_start(fmsg, "severity"); 1885 if (err) 1886 return err; 1887 1888 val = mlxsw_reg_mfde_severity_get(mfde_pl); 1889 err = devlink_fmsg_u8_pair_put(fmsg, "id", val); 1890 if (err) 1891 return err; 1892 switch (val) { 1893 case MLXSW_REG_MFDE_SEVERITY_FATL: 1894 val_str = "Fatal"; 1895 break; 1896 case MLXSW_REG_MFDE_SEVERITY_NRML: 1897 val_str = "Normal"; 1898 break; 1899 case MLXSW_REG_MFDE_SEVERITY_INTR: 1900 val_str = "Debug"; 1901 break; 1902 default: 1903 val_str = NULL; 1904 } 1905 if (val_str) { 1906 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1907 if (err) 1908 return err; 1909 } 1910 1911 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1912 if (err) 1913 return err; 1914 1915 val = mlxsw_reg_mfde_method_get(mfde_pl); 1916 switch (val) { 1917 case MLXSW_REG_MFDE_METHOD_QUERY: 1918 val_str = "query"; 1919 break; 1920 case MLXSW_REG_MFDE_METHOD_WRITE: 1921 val_str = "write"; 1922 break; 1923 default: 1924 val_str = NULL; 1925 } 1926 if (val_str) { 1927 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 1928 if (err) 1929 return err; 1930 } 1931 1932 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 1933 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 1934 if (err) 1935 return err; 1936 1937 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 1938 switch (val) { 1939 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 1940 val_str = "mad"; 1941 break; 1942 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 1943 val_str = "emad"; 1944 break; 1945 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 1946 val_str = "cmdif"; 1947 break; 1948 default: 1949 val_str = NULL; 1950 } 1951 if (val_str) { 1952 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 1953 if (err) 1954 return err; 1955 } 1956 1957 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 1958 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 1959 if (err) 1960 return err; 1961 1962 switch (event_id) { 1963 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1964 return mlxsw_core_health_fw_fatal_dump_crspace_to(mfde_pl, 1965 fmsg); 1966 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1967 return mlxsw_core_health_fw_fatal_dump_kvd_im_stop(mfde_pl, 1968 fmsg); 1969 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1970 return mlxsw_core_health_fw_fatal_dump_fw_assert(mfde_pl, fmsg); 1971 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1972 return mlxsw_core_health_fw_fatal_dump_fatal_cause(mfde_pl, 1973 fmsg); 1974 } 1975 1976 return 0; 1977 } 1978 1979 static int 1980 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 1981 struct netlink_ext_ack *extack) 1982 { 1983 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 1984 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 1985 int err; 1986 1987 /* Read the register first to make sure no other bits are changed. */ 1988 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1989 if (err) 1990 return err; 1991 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 1992 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1993 } 1994 1995 static const struct devlink_health_reporter_ops 1996 mlxsw_core_health_fw_fatal_ops = { 1997 .name = "fw_fatal", 1998 .dump = mlxsw_core_health_fw_fatal_dump, 1999 .test = mlxsw_core_health_fw_fatal_test, 2000 }; 2001 2002 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 2003 bool enable) 2004 { 2005 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2006 int err; 2007 2008 /* Read the register first to make sure no other bits are changed. */ 2009 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2010 if (err) 2011 return err; 2012 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 2013 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2014 } 2015 2016 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 2017 { 2018 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2019 struct devlink_health_reporter *fw_fatal; 2020 int err; 2021 2022 if (!mlxsw_core->driver->fw_fatal_enabled) 2023 return 0; 2024 2025 fw_fatal = devlink_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 2026 0, mlxsw_core); 2027 if (IS_ERR(fw_fatal)) { 2028 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 2029 return PTR_ERR(fw_fatal); 2030 } 2031 mlxsw_core->health.fw_fatal = fw_fatal; 2032 2033 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2034 if (err) 2035 goto err_trap_register; 2036 2037 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 2038 if (err) 2039 goto err_fw_fatal_config; 2040 2041 return 0; 2042 2043 err_fw_fatal_config: 2044 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2045 err_trap_register: 2046 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2047 return err; 2048 } 2049 2050 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 2051 { 2052 if (!mlxsw_core->driver->fw_fatal_enabled) 2053 return; 2054 2055 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 2056 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2057 /* Make sure there is no more event work scheduled */ 2058 mlxsw_core_flush_owq(); 2059 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2060 } 2061 2062 static int 2063 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2064 const struct mlxsw_bus *mlxsw_bus, 2065 void *bus_priv, bool reload, 2066 struct devlink *devlink, 2067 struct netlink_ext_ack *extack) 2068 { 2069 const char *device_kind = mlxsw_bus_info->device_kind; 2070 struct mlxsw_core *mlxsw_core; 2071 struct mlxsw_driver *mlxsw_driver; 2072 struct mlxsw_res *res; 2073 size_t alloc_size; 2074 int err; 2075 2076 mlxsw_driver = mlxsw_core_driver_get(device_kind); 2077 if (!mlxsw_driver) 2078 return -EINVAL; 2079 2080 if (!reload) { 2081 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 2082 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 2083 mlxsw_bus_info->dev); 2084 if (!devlink) { 2085 err = -ENOMEM; 2086 goto err_devlink_alloc; 2087 } 2088 } 2089 2090 mlxsw_core = devlink_priv(devlink); 2091 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 2092 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 2093 mlxsw_core->driver = mlxsw_driver; 2094 mlxsw_core->bus = mlxsw_bus; 2095 mlxsw_core->bus_priv = bus_priv; 2096 mlxsw_core->bus_info = mlxsw_bus_info; 2097 2098 res = mlxsw_driver->res_query_enabled ? &mlxsw_core->res : NULL; 2099 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, res); 2100 if (err) 2101 goto err_bus_init; 2102 2103 if (mlxsw_driver->resources_register && !reload) { 2104 err = mlxsw_driver->resources_register(mlxsw_core); 2105 if (err) 2106 goto err_register_resources; 2107 } 2108 2109 err = mlxsw_ports_init(mlxsw_core, reload); 2110 if (err) 2111 goto err_ports_init; 2112 2113 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) && 2114 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 2115 alloc_size = sizeof(*mlxsw_core->lag.mapping) * 2116 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * 2117 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 2118 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 2119 if (!mlxsw_core->lag.mapping) { 2120 err = -ENOMEM; 2121 goto err_alloc_lag_mapping; 2122 } 2123 } 2124 2125 err = mlxsw_emad_init(mlxsw_core); 2126 if (err) 2127 goto err_emad_init; 2128 2129 if (!reload) { 2130 err = mlxsw_core_params_register(mlxsw_core); 2131 if (err) 2132 goto err_register_params; 2133 } 2134 2135 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 2136 mlxsw_driver->fw_filename); 2137 if (err) 2138 goto err_fw_rev_validate; 2139 2140 err = mlxsw_core_health_init(mlxsw_core); 2141 if (err) 2142 goto err_health_init; 2143 2144 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 2145 if (err) 2146 goto err_hwmon_init; 2147 2148 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 2149 &mlxsw_core->thermal); 2150 if (err) 2151 goto err_thermal_init; 2152 2153 err = mlxsw_env_init(mlxsw_core, &mlxsw_core->env); 2154 if (err) 2155 goto err_env_init; 2156 2157 if (mlxsw_driver->init) { 2158 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2159 if (err) 2160 goto err_driver_init; 2161 } 2162 2163 if (!reload) { 2164 devlink_set_features(devlink, DEVLINK_F_RELOAD); 2165 devlink_register(devlink); 2166 } 2167 return 0; 2168 2169 err_driver_init: 2170 mlxsw_env_fini(mlxsw_core->env); 2171 err_env_init: 2172 mlxsw_thermal_fini(mlxsw_core->thermal); 2173 err_thermal_init: 2174 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2175 err_hwmon_init: 2176 mlxsw_core_health_fini(mlxsw_core); 2177 err_health_init: 2178 err_fw_rev_validate: 2179 if (!reload) 2180 mlxsw_core_params_unregister(mlxsw_core); 2181 err_register_params: 2182 mlxsw_emad_fini(mlxsw_core); 2183 err_emad_init: 2184 kfree(mlxsw_core->lag.mapping); 2185 err_alloc_lag_mapping: 2186 mlxsw_ports_fini(mlxsw_core, reload); 2187 err_ports_init: 2188 if (!reload) 2189 devlink_resources_unregister(devlink); 2190 err_register_resources: 2191 mlxsw_bus->fini(bus_priv); 2192 err_bus_init: 2193 if (!reload) 2194 devlink_free(devlink); 2195 err_devlink_alloc: 2196 return err; 2197 } 2198 2199 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2200 const struct mlxsw_bus *mlxsw_bus, 2201 void *bus_priv, bool reload, 2202 struct devlink *devlink, 2203 struct netlink_ext_ack *extack) 2204 { 2205 bool called_again = false; 2206 int err; 2207 2208 again: 2209 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2210 bus_priv, reload, 2211 devlink, extack); 2212 /* -EAGAIN is returned in case the FW was updated. FW needs 2213 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2214 * again. 2215 */ 2216 if (err == -EAGAIN && !called_again) { 2217 called_again = true; 2218 goto again; 2219 } 2220 2221 return err; 2222 } 2223 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2224 2225 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2226 bool reload) 2227 { 2228 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2229 2230 if (!reload) 2231 devlink_unregister(devlink); 2232 2233 if (devlink_is_reload_failed(devlink)) { 2234 if (!reload) 2235 /* Only the parts that were not de-initialized in the 2236 * failed reload attempt need to be de-initialized. 2237 */ 2238 goto reload_fail_deinit; 2239 else 2240 return; 2241 } 2242 2243 if (mlxsw_core->driver->fini) 2244 mlxsw_core->driver->fini(mlxsw_core); 2245 mlxsw_env_fini(mlxsw_core->env); 2246 mlxsw_thermal_fini(mlxsw_core->thermal); 2247 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2248 mlxsw_core_health_fini(mlxsw_core); 2249 if (!reload) 2250 mlxsw_core_params_unregister(mlxsw_core); 2251 mlxsw_emad_fini(mlxsw_core); 2252 kfree(mlxsw_core->lag.mapping); 2253 mlxsw_ports_fini(mlxsw_core, reload); 2254 if (!reload) 2255 devlink_resources_unregister(devlink); 2256 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2257 if (!reload) 2258 devlink_free(devlink); 2259 2260 return; 2261 2262 reload_fail_deinit: 2263 mlxsw_core_params_unregister(mlxsw_core); 2264 devlink_resources_unregister(devlink); 2265 devlink_free(devlink); 2266 } 2267 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2268 2269 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2270 const struct mlxsw_tx_info *tx_info) 2271 { 2272 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2273 tx_info); 2274 } 2275 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2276 2277 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2278 const struct mlxsw_tx_info *tx_info) 2279 { 2280 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2281 tx_info); 2282 } 2283 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2284 2285 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2286 struct sk_buff *skb, u16 local_port) 2287 { 2288 if (mlxsw_core->driver->ptp_transmitted) 2289 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2290 local_port); 2291 } 2292 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2293 2294 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2295 const struct mlxsw_rx_listener *rxl_b) 2296 { 2297 return (rxl_a->func == rxl_b->func && 2298 rxl_a->local_port == rxl_b->local_port && 2299 rxl_a->trap_id == rxl_b->trap_id && 2300 rxl_a->mirror_reason == rxl_b->mirror_reason); 2301 } 2302 2303 static struct mlxsw_rx_listener_item * 2304 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2305 const struct mlxsw_rx_listener *rxl) 2306 { 2307 struct mlxsw_rx_listener_item *rxl_item; 2308 2309 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2310 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2311 return rxl_item; 2312 } 2313 return NULL; 2314 } 2315 2316 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2317 const struct mlxsw_rx_listener *rxl, 2318 void *priv, bool enabled) 2319 { 2320 struct mlxsw_rx_listener_item *rxl_item; 2321 2322 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2323 if (rxl_item) 2324 return -EEXIST; 2325 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2326 if (!rxl_item) 2327 return -ENOMEM; 2328 rxl_item->rxl = *rxl; 2329 rxl_item->priv = priv; 2330 rxl_item->enabled = enabled; 2331 2332 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2333 return 0; 2334 } 2335 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2336 2337 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2338 const struct mlxsw_rx_listener *rxl) 2339 { 2340 struct mlxsw_rx_listener_item *rxl_item; 2341 2342 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2343 if (!rxl_item) 2344 return; 2345 list_del_rcu(&rxl_item->list); 2346 synchronize_rcu(); 2347 kfree(rxl_item); 2348 } 2349 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2350 2351 static void 2352 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2353 const struct mlxsw_rx_listener *rxl, 2354 bool enabled) 2355 { 2356 struct mlxsw_rx_listener_item *rxl_item; 2357 2358 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2359 if (WARN_ON(!rxl_item)) 2360 return; 2361 rxl_item->enabled = enabled; 2362 } 2363 2364 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u16 local_port, 2365 void *priv) 2366 { 2367 struct mlxsw_event_listener_item *event_listener_item = priv; 2368 struct mlxsw_core *mlxsw_core; 2369 struct mlxsw_reg_info reg; 2370 char *payload; 2371 char *reg_tlv; 2372 char *op_tlv; 2373 2374 mlxsw_core = event_listener_item->mlxsw_core; 2375 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2376 skb->data, skb->len); 2377 2378 mlxsw_emad_tlv_parse(skb); 2379 op_tlv = mlxsw_emad_op_tlv(skb); 2380 reg_tlv = mlxsw_emad_reg_tlv(skb); 2381 2382 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2383 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2384 payload = mlxsw_emad_reg_payload(reg_tlv); 2385 event_listener_item->el.func(®, payload, event_listener_item->priv); 2386 dev_kfree_skb(skb); 2387 } 2388 2389 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2390 const struct mlxsw_event_listener *el_b) 2391 { 2392 return (el_a->func == el_b->func && 2393 el_a->trap_id == el_b->trap_id); 2394 } 2395 2396 static struct mlxsw_event_listener_item * 2397 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2398 const struct mlxsw_event_listener *el) 2399 { 2400 struct mlxsw_event_listener_item *el_item; 2401 2402 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2403 if (__is_event_listener_equal(&el_item->el, el)) 2404 return el_item; 2405 } 2406 return NULL; 2407 } 2408 2409 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2410 const struct mlxsw_event_listener *el, 2411 void *priv) 2412 { 2413 int err; 2414 struct mlxsw_event_listener_item *el_item; 2415 const struct mlxsw_rx_listener rxl = { 2416 .func = mlxsw_core_event_listener_func, 2417 .local_port = MLXSW_PORT_DONT_CARE, 2418 .trap_id = el->trap_id, 2419 }; 2420 2421 el_item = __find_event_listener_item(mlxsw_core, el); 2422 if (el_item) 2423 return -EEXIST; 2424 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2425 if (!el_item) 2426 return -ENOMEM; 2427 el_item->mlxsw_core = mlxsw_core; 2428 el_item->el = *el; 2429 el_item->priv = priv; 2430 2431 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2432 if (err) 2433 goto err_rx_listener_register; 2434 2435 /* No reason to save item if we did not manage to register an RX 2436 * listener for it. 2437 */ 2438 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2439 2440 return 0; 2441 2442 err_rx_listener_register: 2443 kfree(el_item); 2444 return err; 2445 } 2446 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2447 2448 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2449 const struct mlxsw_event_listener *el) 2450 { 2451 struct mlxsw_event_listener_item *el_item; 2452 const struct mlxsw_rx_listener rxl = { 2453 .func = mlxsw_core_event_listener_func, 2454 .local_port = MLXSW_PORT_DONT_CARE, 2455 .trap_id = el->trap_id, 2456 }; 2457 2458 el_item = __find_event_listener_item(mlxsw_core, el); 2459 if (!el_item) 2460 return; 2461 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2462 list_del(&el_item->list); 2463 kfree(el_item); 2464 } 2465 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2466 2467 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2468 const struct mlxsw_listener *listener, 2469 void *priv, bool enabled) 2470 { 2471 if (listener->is_event) { 2472 WARN_ON(!enabled); 2473 return mlxsw_core_event_listener_register(mlxsw_core, 2474 &listener->event_listener, 2475 priv); 2476 } else { 2477 return mlxsw_core_rx_listener_register(mlxsw_core, 2478 &listener->rx_listener, 2479 priv, enabled); 2480 } 2481 } 2482 2483 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2484 const struct mlxsw_listener *listener, 2485 void *priv) 2486 { 2487 if (listener->is_event) 2488 mlxsw_core_event_listener_unregister(mlxsw_core, 2489 &listener->event_listener); 2490 else 2491 mlxsw_core_rx_listener_unregister(mlxsw_core, 2492 &listener->rx_listener); 2493 } 2494 2495 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2496 const struct mlxsw_listener *listener, void *priv) 2497 { 2498 enum mlxsw_reg_htgt_trap_group trap_group; 2499 enum mlxsw_reg_hpkt_action action; 2500 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2501 int err; 2502 2503 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2504 listener->enabled_on_register); 2505 if (err) 2506 return err; 2507 2508 action = listener->enabled_on_register ? listener->en_action : 2509 listener->dis_action; 2510 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2511 listener->dis_trap_group; 2512 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2513 trap_group, listener->is_ctrl); 2514 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2515 if (err) 2516 goto err_trap_set; 2517 2518 return 0; 2519 2520 err_trap_set: 2521 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2522 return err; 2523 } 2524 EXPORT_SYMBOL(mlxsw_core_trap_register); 2525 2526 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2527 const struct mlxsw_listener *listener, 2528 void *priv) 2529 { 2530 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2531 2532 if (!listener->is_event) { 2533 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2534 listener->trap_id, listener->dis_trap_group, 2535 listener->is_ctrl); 2536 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2537 } 2538 2539 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2540 } 2541 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2542 2543 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2544 const struct mlxsw_listener *listener, 2545 bool enabled) 2546 { 2547 enum mlxsw_reg_htgt_trap_group trap_group; 2548 enum mlxsw_reg_hpkt_action action; 2549 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2550 int err; 2551 2552 /* Not supported for event listener */ 2553 if (WARN_ON(listener->is_event)) 2554 return -EINVAL; 2555 2556 action = enabled ? listener->en_action : listener->dis_action; 2557 trap_group = enabled ? listener->en_trap_group : 2558 listener->dis_trap_group; 2559 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2560 trap_group, listener->is_ctrl); 2561 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2562 if (err) 2563 return err; 2564 2565 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2566 enabled); 2567 return 0; 2568 } 2569 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2570 2571 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2572 { 2573 return atomic64_inc_return(&mlxsw_core->emad.tid); 2574 } 2575 2576 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2577 const struct mlxsw_reg_info *reg, 2578 char *payload, 2579 enum mlxsw_core_reg_access_type type, 2580 struct list_head *bulk_list, 2581 mlxsw_reg_trans_cb_t *cb, 2582 unsigned long cb_priv) 2583 { 2584 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2585 struct mlxsw_reg_trans *trans; 2586 int err; 2587 2588 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2589 if (!trans) 2590 return -ENOMEM; 2591 2592 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2593 bulk_list, cb, cb_priv, tid); 2594 if (err) { 2595 kfree_rcu(trans, rcu); 2596 return err; 2597 } 2598 return 0; 2599 } 2600 2601 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2602 const struct mlxsw_reg_info *reg, char *payload, 2603 struct list_head *bulk_list, 2604 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2605 { 2606 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2607 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2608 bulk_list, cb, cb_priv); 2609 } 2610 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2611 2612 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2613 const struct mlxsw_reg_info *reg, char *payload, 2614 struct list_head *bulk_list, 2615 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2616 { 2617 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2618 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2619 bulk_list, cb, cb_priv); 2620 } 2621 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2622 2623 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2624 2625 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2626 { 2627 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2628 struct mlxsw_core *mlxsw_core = trans->core; 2629 int err; 2630 2631 wait_for_completion(&trans->completion); 2632 cancel_delayed_work_sync(&trans->timeout_dw); 2633 err = trans->err; 2634 2635 if (trans->retries) 2636 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2637 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2638 if (err) { 2639 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2640 trans->tid, trans->reg->id, 2641 mlxsw_reg_id_str(trans->reg->id), 2642 mlxsw_core_reg_access_type_str(trans->type), 2643 trans->emad_status, 2644 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2645 2646 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2647 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2648 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2649 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2650 trans->emad_err_string ? trans->emad_err_string : ""); 2651 2652 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2653 trans->emad_status, err_string); 2654 2655 kfree(trans->emad_err_string); 2656 } 2657 2658 list_del(&trans->bulk_list); 2659 kfree_rcu(trans, rcu); 2660 return err; 2661 } 2662 2663 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2664 { 2665 struct mlxsw_reg_trans *trans; 2666 struct mlxsw_reg_trans *tmp; 2667 int sum_err = 0; 2668 int err; 2669 2670 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2671 err = mlxsw_reg_trans_wait(trans); 2672 if (err && sum_err == 0) 2673 sum_err = err; /* first error to be returned */ 2674 } 2675 return sum_err; 2676 } 2677 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2678 2679 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2680 const struct mlxsw_reg_info *reg, 2681 char *payload, 2682 enum mlxsw_core_reg_access_type type) 2683 { 2684 enum mlxsw_emad_op_tlv_status status; 2685 int err, n_retry; 2686 bool reset_ok; 2687 char *in_mbox, *out_mbox, *tmp; 2688 2689 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2690 reg->id, mlxsw_reg_id_str(reg->id), 2691 mlxsw_core_reg_access_type_str(type)); 2692 2693 in_mbox = mlxsw_cmd_mbox_alloc(); 2694 if (!in_mbox) 2695 return -ENOMEM; 2696 2697 out_mbox = mlxsw_cmd_mbox_alloc(); 2698 if (!out_mbox) { 2699 err = -ENOMEM; 2700 goto free_in_mbox; 2701 } 2702 2703 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2704 mlxsw_core_tid_get(mlxsw_core)); 2705 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2706 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2707 2708 /* There is a special treatment needed for MRSR (reset) register. 2709 * The command interface will return error after the command 2710 * is executed, so tell the lower layer to expect it 2711 * and cope accordingly. 2712 */ 2713 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2714 2715 n_retry = 0; 2716 retry: 2717 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2718 if (!err) { 2719 err = mlxsw_emad_process_status(out_mbox, &status); 2720 if (err) { 2721 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2722 goto retry; 2723 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2724 status, mlxsw_emad_op_tlv_status_str(status)); 2725 } 2726 } 2727 2728 if (!err) 2729 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2730 reg->len); 2731 2732 mlxsw_cmd_mbox_free(out_mbox); 2733 free_in_mbox: 2734 mlxsw_cmd_mbox_free(in_mbox); 2735 if (err) 2736 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2737 reg->id, mlxsw_reg_id_str(reg->id), 2738 mlxsw_core_reg_access_type_str(type)); 2739 return err; 2740 } 2741 2742 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2743 char *payload, size_t payload_len, 2744 unsigned long cb_priv) 2745 { 2746 char *orig_payload = (char *) cb_priv; 2747 2748 memcpy(orig_payload, payload, payload_len); 2749 } 2750 2751 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2752 const struct mlxsw_reg_info *reg, 2753 char *payload, 2754 enum mlxsw_core_reg_access_type type) 2755 { 2756 LIST_HEAD(bulk_list); 2757 int err; 2758 2759 /* During initialization EMAD interface is not available to us, 2760 * so we default to command interface. We switch to EMAD interface 2761 * after setting the appropriate traps. 2762 */ 2763 if (!mlxsw_core->emad.use_emad) 2764 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2765 payload, type); 2766 2767 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 2768 payload, type, &bulk_list, 2769 mlxsw_core_reg_access_cb, 2770 (unsigned long) payload); 2771 if (err) 2772 return err; 2773 return mlxsw_reg_trans_bulk_wait(&bulk_list); 2774 } 2775 2776 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 2777 const struct mlxsw_reg_info *reg, char *payload) 2778 { 2779 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2780 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 2781 } 2782 EXPORT_SYMBOL(mlxsw_reg_query); 2783 2784 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 2785 const struct mlxsw_reg_info *reg, char *payload) 2786 { 2787 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2788 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 2789 } 2790 EXPORT_SYMBOL(mlxsw_reg_write); 2791 2792 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2793 struct mlxsw_rx_info *rx_info) 2794 { 2795 struct mlxsw_rx_listener_item *rxl_item; 2796 const struct mlxsw_rx_listener *rxl; 2797 u16 local_port; 2798 bool found = false; 2799 2800 if (rx_info->is_lag) { 2801 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 2802 __func__, rx_info->u.lag_id, 2803 rx_info->trap_id); 2804 /* Upper layer does not care if the skb came from LAG or not, 2805 * so just get the local_port for the lag port and push it up. 2806 */ 2807 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 2808 rx_info->u.lag_id, 2809 rx_info->lag_port_index); 2810 } else { 2811 local_port = rx_info->u.sys_port; 2812 } 2813 2814 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 2815 __func__, local_port, rx_info->trap_id); 2816 2817 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 2818 (local_port >= mlxsw_core->max_ports)) 2819 goto drop; 2820 2821 rcu_read_lock(); 2822 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 2823 rxl = &rxl_item->rxl; 2824 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 2825 rxl->local_port == local_port) && 2826 rxl->trap_id == rx_info->trap_id && 2827 rxl->mirror_reason == rx_info->mirror_reason) { 2828 if (rxl_item->enabled) 2829 found = true; 2830 break; 2831 } 2832 } 2833 if (!found) { 2834 rcu_read_unlock(); 2835 goto drop; 2836 } 2837 2838 rxl->func(skb, local_port, rxl_item->priv); 2839 rcu_read_unlock(); 2840 return; 2841 2842 drop: 2843 dev_kfree_skb(skb); 2844 } 2845 EXPORT_SYMBOL(mlxsw_core_skb_receive); 2846 2847 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 2848 u16 lag_id, u8 port_index) 2849 { 2850 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 2851 port_index; 2852 } 2853 2854 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 2855 u16 lag_id, u8 port_index, u16 local_port) 2856 { 2857 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2858 lag_id, port_index); 2859 2860 mlxsw_core->lag.mapping[index] = local_port; 2861 } 2862 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 2863 2864 u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 2865 u16 lag_id, u8 port_index) 2866 { 2867 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2868 lag_id, port_index); 2869 2870 return mlxsw_core->lag.mapping[index]; 2871 } 2872 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 2873 2874 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 2875 u16 lag_id, u16 local_port) 2876 { 2877 int i; 2878 2879 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 2880 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2881 lag_id, i); 2882 2883 if (mlxsw_core->lag.mapping[index] == local_port) 2884 mlxsw_core->lag.mapping[index] = 0; 2885 } 2886 } 2887 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 2888 2889 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 2890 enum mlxsw_res_id res_id) 2891 { 2892 return mlxsw_res_valid(&mlxsw_core->res, res_id); 2893 } 2894 EXPORT_SYMBOL(mlxsw_core_res_valid); 2895 2896 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 2897 enum mlxsw_res_id res_id) 2898 { 2899 return mlxsw_res_get(&mlxsw_core->res, res_id); 2900 } 2901 EXPORT_SYMBOL(mlxsw_core_res_get); 2902 2903 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 2904 enum devlink_port_flavour flavour, 2905 u32 port_number, bool split, 2906 u32 split_port_subnumber, 2907 bool splittable, u32 lanes, 2908 const unsigned char *switch_id, 2909 unsigned char switch_id_len) 2910 { 2911 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2912 struct mlxsw_core_port *mlxsw_core_port = 2913 &mlxsw_core->ports[local_port]; 2914 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2915 struct devlink_port_attrs attrs = {}; 2916 int err; 2917 2918 attrs.split = split; 2919 attrs.lanes = lanes; 2920 attrs.splittable = splittable; 2921 attrs.flavour = flavour; 2922 attrs.phys.port_number = port_number; 2923 attrs.phys.split_subport_number = split_port_subnumber; 2924 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 2925 attrs.switch_id.id_len = switch_id_len; 2926 mlxsw_core_port->local_port = local_port; 2927 devlink_port_attrs_set(devlink_port, &attrs); 2928 err = devlink_port_register(devlink, devlink_port, local_port); 2929 if (err) 2930 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2931 return err; 2932 } 2933 2934 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 2935 { 2936 struct mlxsw_core_port *mlxsw_core_port = 2937 &mlxsw_core->ports[local_port]; 2938 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2939 2940 devlink_port_unregister(devlink_port); 2941 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2942 } 2943 2944 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 2945 u32 port_number, bool split, 2946 u32 split_port_subnumber, 2947 bool splittable, u32 lanes, 2948 const unsigned char *switch_id, 2949 unsigned char switch_id_len) 2950 { 2951 int err; 2952 2953 err = __mlxsw_core_port_init(mlxsw_core, local_port, 2954 DEVLINK_PORT_FLAVOUR_PHYSICAL, 2955 port_number, split, split_port_subnumber, 2956 splittable, lanes, 2957 switch_id, switch_id_len); 2958 if (err) 2959 return err; 2960 2961 atomic_inc(&mlxsw_core->active_ports_count); 2962 return 0; 2963 } 2964 EXPORT_SYMBOL(mlxsw_core_port_init); 2965 2966 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 2967 { 2968 atomic_dec(&mlxsw_core->active_ports_count); 2969 2970 __mlxsw_core_port_fini(mlxsw_core, local_port); 2971 } 2972 EXPORT_SYMBOL(mlxsw_core_port_fini); 2973 2974 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 2975 void *port_driver_priv, 2976 const unsigned char *switch_id, 2977 unsigned char switch_id_len) 2978 { 2979 struct mlxsw_core_port *mlxsw_core_port = 2980 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 2981 int err; 2982 2983 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 2984 DEVLINK_PORT_FLAVOUR_CPU, 2985 0, false, 0, false, 0, 2986 switch_id, switch_id_len); 2987 if (err) 2988 return err; 2989 2990 mlxsw_core_port->port_driver_priv = port_driver_priv; 2991 return 0; 2992 } 2993 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 2994 2995 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 2996 { 2997 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 2998 } 2999 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 3000 3001 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3002 void *port_driver_priv, struct net_device *dev) 3003 { 3004 struct mlxsw_core_port *mlxsw_core_port = 3005 &mlxsw_core->ports[local_port]; 3006 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3007 3008 mlxsw_core_port->port_driver_priv = port_driver_priv; 3009 devlink_port_type_eth_set(devlink_port, dev); 3010 } 3011 EXPORT_SYMBOL(mlxsw_core_port_eth_set); 3012 3013 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3014 void *port_driver_priv) 3015 { 3016 struct mlxsw_core_port *mlxsw_core_port = 3017 &mlxsw_core->ports[local_port]; 3018 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3019 3020 mlxsw_core_port->port_driver_priv = port_driver_priv; 3021 devlink_port_type_ib_set(devlink_port, NULL); 3022 } 3023 EXPORT_SYMBOL(mlxsw_core_port_ib_set); 3024 3025 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port, 3026 void *port_driver_priv) 3027 { 3028 struct mlxsw_core_port *mlxsw_core_port = 3029 &mlxsw_core->ports[local_port]; 3030 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3031 3032 mlxsw_core_port->port_driver_priv = port_driver_priv; 3033 devlink_port_type_clear(devlink_port); 3034 } 3035 EXPORT_SYMBOL(mlxsw_core_port_clear); 3036 3037 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 3038 u16 local_port) 3039 { 3040 struct mlxsw_core_port *mlxsw_core_port = 3041 &mlxsw_core->ports[local_port]; 3042 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3043 3044 return devlink_port->type; 3045 } 3046 EXPORT_SYMBOL(mlxsw_core_port_type_get); 3047 3048 3049 struct devlink_port * 3050 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 3051 u16 local_port) 3052 { 3053 struct mlxsw_core_port *mlxsw_core_port = 3054 &mlxsw_core->ports[local_port]; 3055 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3056 3057 return devlink_port; 3058 } 3059 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 3060 3061 bool mlxsw_core_port_is_xm(const struct mlxsw_core *mlxsw_core, u16 local_port) 3062 { 3063 const struct mlxsw_bus_info *bus_info = mlxsw_core->bus_info; 3064 int i; 3065 3066 for (i = 0; i < bus_info->xm_local_ports_count; i++) 3067 if (bus_info->xm_local_ports[i] == local_port) 3068 return true; 3069 return false; 3070 } 3071 EXPORT_SYMBOL(mlxsw_core_port_is_xm); 3072 3073 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 3074 { 3075 return mlxsw_core->env; 3076 } 3077 3078 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 3079 const char *buf, size_t size) 3080 { 3081 __be32 *m = (__be32 *) buf; 3082 int i; 3083 int count = size / sizeof(__be32); 3084 3085 for (i = count - 1; i >= 0; i--) 3086 if (m[i]) 3087 break; 3088 i++; 3089 count = i ? i : 1; 3090 for (i = 0; i < count; i += 4) 3091 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 3092 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 3093 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 3094 } 3095 3096 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 3097 u32 in_mod, bool out_mbox_direct, bool reset_ok, 3098 char *in_mbox, size_t in_mbox_size, 3099 char *out_mbox, size_t out_mbox_size) 3100 { 3101 u8 status; 3102 int err; 3103 3104 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 3105 if (!mlxsw_core->bus->cmd_exec) 3106 return -EOPNOTSUPP; 3107 3108 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3109 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 3110 if (in_mbox) { 3111 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 3112 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 3113 } 3114 3115 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 3116 opcode_mod, in_mod, out_mbox_direct, 3117 in_mbox, in_mbox_size, 3118 out_mbox, out_mbox_size, &status); 3119 3120 if (!err && out_mbox) { 3121 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 3122 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 3123 } 3124 3125 if (reset_ok && err == -EIO && 3126 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 3127 err = 0; 3128 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 3129 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 3130 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3131 in_mod, status, mlxsw_cmd_status_str(status)); 3132 } else if (err == -ETIMEDOUT) { 3133 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3134 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3135 in_mod); 3136 } 3137 3138 return err; 3139 } 3140 EXPORT_SYMBOL(mlxsw_cmd_exec); 3141 3142 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 3143 { 3144 return queue_delayed_work(mlxsw_wq, dwork, delay); 3145 } 3146 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 3147 3148 bool mlxsw_core_schedule_work(struct work_struct *work) 3149 { 3150 return queue_work(mlxsw_owq, work); 3151 } 3152 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3153 3154 void mlxsw_core_flush_owq(void) 3155 { 3156 flush_workqueue(mlxsw_owq); 3157 } 3158 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3159 3160 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3161 const struct mlxsw_config_profile *profile, 3162 u64 *p_single_size, u64 *p_double_size, 3163 u64 *p_linear_size) 3164 { 3165 struct mlxsw_driver *driver = mlxsw_core->driver; 3166 3167 if (!driver->kvd_sizes_get) 3168 return -EINVAL; 3169 3170 return driver->kvd_sizes_get(mlxsw_core, profile, 3171 p_single_size, p_double_size, 3172 p_linear_size); 3173 } 3174 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3175 3176 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3177 struct mlxsw_res *res) 3178 { 3179 int index, i; 3180 u64 data; 3181 u16 id; 3182 int err; 3183 3184 if (!res) 3185 return 0; 3186 3187 mlxsw_cmd_mbox_zero(mbox); 3188 3189 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3190 index++) { 3191 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3192 if (err) 3193 return err; 3194 3195 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3196 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3197 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3198 3199 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3200 return 0; 3201 3202 mlxsw_res_parse(res, id, data); 3203 } 3204 } 3205 3206 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3207 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3208 */ 3209 return -EIO; 3210 } 3211 EXPORT_SYMBOL(mlxsw_core_resources_query); 3212 3213 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3214 { 3215 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3216 } 3217 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3218 3219 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3220 { 3221 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3222 } 3223 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3224 3225 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core) 3226 { 3227 mlxsw_core->emad.enable_string_tlv = true; 3228 } 3229 EXPORT_SYMBOL(mlxsw_core_emad_string_tlv_enable); 3230 3231 static int __init mlxsw_core_module_init(void) 3232 { 3233 int err; 3234 3235 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3236 if (!mlxsw_wq) 3237 return -ENOMEM; 3238 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3239 mlxsw_core_driver_name); 3240 if (!mlxsw_owq) { 3241 err = -ENOMEM; 3242 goto err_alloc_ordered_workqueue; 3243 } 3244 return 0; 3245 3246 err_alloc_ordered_workqueue: 3247 destroy_workqueue(mlxsw_wq); 3248 return err; 3249 } 3250 3251 static void __exit mlxsw_core_module_exit(void) 3252 { 3253 destroy_workqueue(mlxsw_owq); 3254 destroy_workqueue(mlxsw_wq); 3255 } 3256 3257 module_init(mlxsw_core_module_init); 3258 module_exit(mlxsw_core_module_exit); 3259 3260 MODULE_LICENSE("Dual BSD/GPL"); 3261 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3262 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3263