1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u16 local_port; 51 struct mlxsw_linecard *linecard; 52 }; 53 54 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 55 { 56 return mlxsw_core_port->port_driver_priv; 57 } 58 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 59 60 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 61 { 62 return mlxsw_core_port->port_driver_priv != NULL; 63 } 64 65 struct mlxsw_core { 66 struct mlxsw_driver *driver; 67 const struct mlxsw_bus *bus; 68 void *bus_priv; 69 const struct mlxsw_bus_info *bus_info; 70 struct workqueue_struct *emad_wq; 71 struct list_head rx_listener_list; 72 struct list_head event_listener_list; 73 struct { 74 atomic64_t tid; 75 struct list_head trans_list; 76 spinlock_t trans_list_lock; /* protects trans_list writes */ 77 bool use_emad; 78 bool enable_string_tlv; 79 } emad; 80 struct { 81 u16 *mapping; /* lag_id+port_index to local_port mapping */ 82 } lag; 83 struct mlxsw_res res; 84 struct mlxsw_hwmon *hwmon; 85 struct mlxsw_thermal *thermal; 86 struct mlxsw_linecards *linecards; 87 struct mlxsw_core_port *ports; 88 unsigned int max_ports; 89 atomic_t active_ports_count; 90 bool fw_flash_in_progress; 91 struct { 92 struct devlink_health_reporter *fw_fatal; 93 } health; 94 struct mlxsw_env *env; 95 unsigned long driver_priv[]; 96 /* driver_priv has to be always the last item */ 97 }; 98 99 struct mlxsw_linecards *mlxsw_core_linecards(struct mlxsw_core *mlxsw_core) 100 { 101 return mlxsw_core->linecards; 102 } 103 104 void mlxsw_core_linecards_set(struct mlxsw_core *mlxsw_core, 105 struct mlxsw_linecards *linecards) 106 { 107 mlxsw_core->linecards = linecards; 108 } 109 110 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 111 112 static u64 mlxsw_ports_occ_get(void *priv) 113 { 114 struct mlxsw_core *mlxsw_core = priv; 115 116 return atomic_read(&mlxsw_core->active_ports_count); 117 } 118 119 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 120 { 121 struct devlink *devlink = priv_to_devlink(mlxsw_core); 122 struct devlink_resource_size_params ports_num_params; 123 u32 max_ports; 124 125 max_ports = mlxsw_core->max_ports - 1; 126 devlink_resource_size_params_init(&ports_num_params, max_ports, 127 max_ports, 1, 128 DEVLINK_RESOURCE_UNIT_ENTRY); 129 130 return devl_resource_register(devlink, 131 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 132 max_ports, MLXSW_CORE_RESOURCE_PORTS, 133 DEVLINK_RESOURCE_ID_PARENT_TOP, 134 &ports_num_params); 135 } 136 137 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 138 { 139 struct devlink *devlink = priv_to_devlink(mlxsw_core); 140 int err; 141 142 /* Switch ports are numbered from 1 to queried value */ 143 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 144 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 145 MAX_SYSTEM_PORT) + 1; 146 else 147 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 148 149 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 150 sizeof(struct mlxsw_core_port), GFP_KERNEL); 151 if (!mlxsw_core->ports) 152 return -ENOMEM; 153 154 if (!reload) { 155 err = mlxsw_core_resources_ports_register(mlxsw_core); 156 if (err) 157 goto err_resources_ports_register; 158 } 159 atomic_set(&mlxsw_core->active_ports_count, 0); 160 devl_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 161 mlxsw_ports_occ_get, mlxsw_core); 162 163 return 0; 164 165 err_resources_ports_register: 166 kfree(mlxsw_core->ports); 167 return err; 168 } 169 170 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 171 { 172 struct devlink *devlink = priv_to_devlink(mlxsw_core); 173 174 devl_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 175 if (!reload) 176 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 177 178 kfree(mlxsw_core->ports); 179 } 180 181 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 182 { 183 return mlxsw_core->max_ports; 184 } 185 EXPORT_SYMBOL(mlxsw_core_max_ports); 186 187 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 188 { 189 return mlxsw_core->driver_priv; 190 } 191 EXPORT_SYMBOL(mlxsw_core_driver_priv); 192 193 bool 194 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 195 const struct mlxsw_fw_rev *req_rev) 196 { 197 return rev->minor > req_rev->minor || 198 (rev->minor == req_rev->minor && 199 rev->subminor >= req_rev->subminor); 200 } 201 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 202 203 struct mlxsw_rx_listener_item { 204 struct list_head list; 205 struct mlxsw_rx_listener rxl; 206 void *priv; 207 bool enabled; 208 }; 209 210 struct mlxsw_event_listener_item { 211 struct list_head list; 212 struct mlxsw_core *mlxsw_core; 213 struct mlxsw_event_listener el; 214 void *priv; 215 }; 216 217 static const u8 mlxsw_core_trap_groups[] = { 218 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 219 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 220 }; 221 222 static int mlxsw_core_trap_groups_set(struct mlxsw_core *mlxsw_core) 223 { 224 char htgt_pl[MLXSW_REG_HTGT_LEN]; 225 int err; 226 int i; 227 228 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 229 return 0; 230 231 for (i = 0; i < ARRAY_SIZE(mlxsw_core_trap_groups); i++) { 232 mlxsw_reg_htgt_pack(htgt_pl, mlxsw_core_trap_groups[i], 233 MLXSW_REG_HTGT_INVALID_POLICER, 234 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 235 MLXSW_REG_HTGT_DEFAULT_TC); 236 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 237 if (err) 238 return err; 239 } 240 return 0; 241 } 242 243 /****************** 244 * EMAD processing 245 ******************/ 246 247 /* emad_eth_hdr_dmac 248 * Destination MAC in EMAD's Ethernet header. 249 * Must be set to 01:02:c9:00:00:01 250 */ 251 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 252 253 /* emad_eth_hdr_smac 254 * Source MAC in EMAD's Ethernet header. 255 * Must be set to 00:02:c9:01:02:03 256 */ 257 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 258 259 /* emad_eth_hdr_ethertype 260 * Ethertype in EMAD's Ethernet header. 261 * Must be set to 0x8932 262 */ 263 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 264 265 /* emad_eth_hdr_mlx_proto 266 * Mellanox protocol. 267 * Must be set to 0x0. 268 */ 269 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 270 271 /* emad_eth_hdr_ver 272 * Mellanox protocol version. 273 * Must be set to 0x0. 274 */ 275 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 276 277 /* emad_op_tlv_type 278 * Type of the TLV. 279 * Must be set to 0x1 (operation TLV). 280 */ 281 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 282 283 /* emad_op_tlv_len 284 * Length of the operation TLV in u32. 285 * Must be set to 0x4. 286 */ 287 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 288 289 /* emad_op_tlv_dr 290 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 291 * EMAD. DR TLV must follow. 292 * 293 * Note: Currently not supported and must not be set. 294 */ 295 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 296 297 /* emad_op_tlv_status 298 * Returned status in case of EMAD response. Must be set to 0 in case 299 * of EMAD request. 300 * 0x0 - success 301 * 0x1 - device is busy. Requester should retry 302 * 0x2 - Mellanox protocol version not supported 303 * 0x3 - unknown TLV 304 * 0x4 - register not supported 305 * 0x5 - operation class not supported 306 * 0x6 - EMAD method not supported 307 * 0x7 - bad parameter (e.g. port out of range) 308 * 0x8 - resource not available 309 * 0x9 - message receipt acknowledgment. Requester should retry 310 * 0x70 - internal error 311 */ 312 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 313 314 /* emad_op_tlv_register_id 315 * Register ID of register within register TLV. 316 */ 317 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 318 319 /* emad_op_tlv_r 320 * Response bit. Setting to 1 indicates Response, otherwise request. 321 */ 322 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 323 324 /* emad_op_tlv_method 325 * EMAD method type. 326 * 0x1 - query 327 * 0x2 - write 328 * 0x3 - send (currently not supported) 329 * 0x4 - event 330 */ 331 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 332 333 /* emad_op_tlv_class 334 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 335 */ 336 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 337 338 /* emad_op_tlv_tid 339 * EMAD transaction ID. Used for pairing request and response EMADs. 340 */ 341 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 342 343 /* emad_string_tlv_type 344 * Type of the TLV. 345 * Must be set to 0x2 (string TLV). 346 */ 347 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 348 349 /* emad_string_tlv_len 350 * Length of the string TLV in u32. 351 */ 352 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 353 354 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 355 356 /* emad_string_tlv_string 357 * String provided by the device's firmware in case of erroneous register access 358 */ 359 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 360 MLXSW_EMAD_STRING_TLV_STRING_LEN); 361 362 /* emad_reg_tlv_type 363 * Type of the TLV. 364 * Must be set to 0x3 (register TLV). 365 */ 366 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 367 368 /* emad_reg_tlv_len 369 * Length of the operation TLV in u32. 370 */ 371 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 372 373 /* emad_end_tlv_type 374 * Type of the TLV. 375 * Must be set to 0x0 (end TLV). 376 */ 377 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 378 379 /* emad_end_tlv_len 380 * Length of the end TLV in u32. 381 * Must be set to 1. 382 */ 383 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 384 385 enum mlxsw_core_reg_access_type { 386 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 387 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 388 }; 389 390 static inline const char * 391 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 392 { 393 switch (type) { 394 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 395 return "query"; 396 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 397 return "write"; 398 } 399 BUG(); 400 } 401 402 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 403 { 404 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 405 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 406 } 407 408 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 409 const struct mlxsw_reg_info *reg, 410 char *payload) 411 { 412 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 413 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 414 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 415 } 416 417 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 418 { 419 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 420 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 421 } 422 423 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 424 const struct mlxsw_reg_info *reg, 425 enum mlxsw_core_reg_access_type type, 426 u64 tid) 427 { 428 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 429 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 430 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 431 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 432 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 433 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 434 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 435 mlxsw_emad_op_tlv_method_set(op_tlv, 436 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 437 else 438 mlxsw_emad_op_tlv_method_set(op_tlv, 439 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 440 mlxsw_emad_op_tlv_class_set(op_tlv, 441 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 442 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 443 } 444 445 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 446 { 447 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 448 449 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 450 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 451 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 452 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 453 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 454 455 skb_reset_mac_header(skb); 456 457 return 0; 458 } 459 460 static void mlxsw_emad_construct(struct sk_buff *skb, 461 const struct mlxsw_reg_info *reg, 462 char *payload, 463 enum mlxsw_core_reg_access_type type, 464 u64 tid, bool enable_string_tlv) 465 { 466 char *buf; 467 468 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 469 mlxsw_emad_pack_end_tlv(buf); 470 471 buf = skb_push(skb, reg->len + sizeof(u32)); 472 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 473 474 if (enable_string_tlv) { 475 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 476 mlxsw_emad_pack_string_tlv(buf); 477 } 478 479 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 480 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 481 482 mlxsw_emad_construct_eth_hdr(skb); 483 } 484 485 struct mlxsw_emad_tlv_offsets { 486 u16 op_tlv; 487 u16 string_tlv; 488 u16 reg_tlv; 489 }; 490 491 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 492 { 493 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 494 495 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 496 } 497 498 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 499 { 500 struct mlxsw_emad_tlv_offsets *offsets = 501 (struct mlxsw_emad_tlv_offsets *) skb->cb; 502 503 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 504 offsets->string_tlv = 0; 505 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 506 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 507 508 /* If string TLV is present, it must come after the operation TLV. */ 509 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 510 offsets->string_tlv = offsets->reg_tlv; 511 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 512 } 513 } 514 515 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 516 { 517 struct mlxsw_emad_tlv_offsets *offsets = 518 (struct mlxsw_emad_tlv_offsets *) skb->cb; 519 520 return ((char *) (skb->data + offsets->op_tlv)); 521 } 522 523 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 524 { 525 struct mlxsw_emad_tlv_offsets *offsets = 526 (struct mlxsw_emad_tlv_offsets *) skb->cb; 527 528 if (!offsets->string_tlv) 529 return NULL; 530 531 return ((char *) (skb->data + offsets->string_tlv)); 532 } 533 534 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 535 { 536 struct mlxsw_emad_tlv_offsets *offsets = 537 (struct mlxsw_emad_tlv_offsets *) skb->cb; 538 539 return ((char *) (skb->data + offsets->reg_tlv)); 540 } 541 542 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 543 { 544 return ((char *) (reg_tlv + sizeof(u32))); 545 } 546 547 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 548 { 549 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 550 } 551 552 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 553 { 554 char *op_tlv; 555 556 op_tlv = mlxsw_emad_op_tlv(skb); 557 return mlxsw_emad_op_tlv_tid_get(op_tlv); 558 } 559 560 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 561 { 562 char *op_tlv; 563 564 op_tlv = mlxsw_emad_op_tlv(skb); 565 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 566 } 567 568 static int mlxsw_emad_process_status(char *op_tlv, 569 enum mlxsw_emad_op_tlv_status *p_status) 570 { 571 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 572 573 switch (*p_status) { 574 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 575 return 0; 576 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 577 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 578 return -EAGAIN; 579 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 580 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 581 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 582 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 583 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 584 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 585 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 586 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 587 default: 588 return -EIO; 589 } 590 } 591 592 static int 593 mlxsw_emad_process_status_skb(struct sk_buff *skb, 594 enum mlxsw_emad_op_tlv_status *p_status) 595 { 596 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 597 } 598 599 struct mlxsw_reg_trans { 600 struct list_head list; 601 struct list_head bulk_list; 602 struct mlxsw_core *core; 603 struct sk_buff *tx_skb; 604 struct mlxsw_tx_info tx_info; 605 struct delayed_work timeout_dw; 606 unsigned int retries; 607 u64 tid; 608 struct completion completion; 609 atomic_t active; 610 mlxsw_reg_trans_cb_t *cb; 611 unsigned long cb_priv; 612 const struct mlxsw_reg_info *reg; 613 enum mlxsw_core_reg_access_type type; 614 int err; 615 char *emad_err_string; 616 enum mlxsw_emad_op_tlv_status emad_status; 617 struct rcu_head rcu; 618 }; 619 620 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 621 struct mlxsw_reg_trans *trans) 622 { 623 char *string_tlv; 624 char *string; 625 626 string_tlv = mlxsw_emad_string_tlv(skb); 627 if (!string_tlv) 628 return; 629 630 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 631 GFP_ATOMIC); 632 if (!trans->emad_err_string) 633 return; 634 635 string = mlxsw_emad_string_tlv_string_data(string_tlv); 636 strlcpy(trans->emad_err_string, string, 637 MLXSW_EMAD_STRING_TLV_STRING_LEN); 638 } 639 640 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 641 #define MLXSW_EMAD_TIMEOUT_MS 200 642 643 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 644 { 645 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 646 647 if (trans->core->fw_flash_in_progress) 648 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 649 650 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 651 timeout << trans->retries); 652 } 653 654 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 655 struct mlxsw_reg_trans *trans) 656 { 657 struct sk_buff *skb; 658 int err; 659 660 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 661 if (!skb) 662 return -ENOMEM; 663 664 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 665 skb->data + mlxsw_core->driver->txhdr_len, 666 skb->len - mlxsw_core->driver->txhdr_len); 667 668 atomic_set(&trans->active, 1); 669 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 670 if (err) { 671 dev_kfree_skb(skb); 672 return err; 673 } 674 mlxsw_emad_trans_timeout_schedule(trans); 675 return 0; 676 } 677 678 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 679 { 680 struct mlxsw_core *mlxsw_core = trans->core; 681 682 dev_kfree_skb(trans->tx_skb); 683 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 684 list_del_rcu(&trans->list); 685 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 686 trans->err = err; 687 complete(&trans->completion); 688 } 689 690 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 691 struct mlxsw_reg_trans *trans) 692 { 693 int err; 694 695 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 696 trans->retries++; 697 err = mlxsw_emad_transmit(trans->core, trans); 698 if (err == 0) 699 return; 700 701 if (!atomic_dec_and_test(&trans->active)) 702 return; 703 } else { 704 err = -EIO; 705 } 706 mlxsw_emad_trans_finish(trans, err); 707 } 708 709 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 710 { 711 struct mlxsw_reg_trans *trans = container_of(work, 712 struct mlxsw_reg_trans, 713 timeout_dw.work); 714 715 if (!atomic_dec_and_test(&trans->active)) 716 return; 717 718 mlxsw_emad_transmit_retry(trans->core, trans); 719 } 720 721 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 722 struct mlxsw_reg_trans *trans, 723 struct sk_buff *skb) 724 { 725 int err; 726 727 if (!atomic_dec_and_test(&trans->active)) 728 return; 729 730 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 731 if (err == -EAGAIN) { 732 mlxsw_emad_transmit_retry(mlxsw_core, trans); 733 } else { 734 if (err == 0) { 735 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 736 737 if (trans->cb) 738 trans->cb(mlxsw_core, 739 mlxsw_emad_reg_payload(reg_tlv), 740 trans->reg->len, trans->cb_priv); 741 } else { 742 mlxsw_emad_process_string_tlv(skb, trans); 743 } 744 mlxsw_emad_trans_finish(trans, err); 745 } 746 } 747 748 /* called with rcu read lock held */ 749 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, 750 void *priv) 751 { 752 struct mlxsw_core *mlxsw_core = priv; 753 struct mlxsw_reg_trans *trans; 754 755 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 756 skb->data, skb->len); 757 758 mlxsw_emad_tlv_parse(skb); 759 760 if (!mlxsw_emad_is_resp(skb)) 761 goto free_skb; 762 763 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 764 if (mlxsw_emad_get_tid(skb) == trans->tid) { 765 mlxsw_emad_process_response(mlxsw_core, trans, skb); 766 break; 767 } 768 } 769 770 free_skb: 771 dev_kfree_skb(skb); 772 } 773 774 static const struct mlxsw_listener mlxsw_emad_rx_listener = 775 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 776 EMAD, DISCARD); 777 778 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 779 { 780 struct workqueue_struct *emad_wq; 781 u64 tid; 782 int err; 783 784 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 785 return 0; 786 787 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 788 if (!emad_wq) 789 return -ENOMEM; 790 mlxsw_core->emad_wq = emad_wq; 791 792 /* Set the upper 32 bits of the transaction ID field to a random 793 * number. This allows us to discard EMADs addressed to other 794 * devices. 795 */ 796 get_random_bytes(&tid, 4); 797 tid <<= 32; 798 atomic64_set(&mlxsw_core->emad.tid, tid); 799 800 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 801 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 802 803 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 804 mlxsw_core); 805 if (err) 806 goto err_trap_register; 807 808 mlxsw_core->emad.use_emad = true; 809 810 return 0; 811 812 err_trap_register: 813 destroy_workqueue(mlxsw_core->emad_wq); 814 return err; 815 } 816 817 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 818 { 819 820 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 821 return; 822 823 mlxsw_core->emad.use_emad = false; 824 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 825 mlxsw_core); 826 destroy_workqueue(mlxsw_core->emad_wq); 827 } 828 829 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 830 u16 reg_len, bool enable_string_tlv) 831 { 832 struct sk_buff *skb; 833 u16 emad_len; 834 835 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 836 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 837 sizeof(u32) + mlxsw_core->driver->txhdr_len); 838 if (enable_string_tlv) 839 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 840 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 841 return NULL; 842 843 skb = netdev_alloc_skb(NULL, emad_len); 844 if (!skb) 845 return NULL; 846 memset(skb->data, 0, emad_len); 847 skb_reserve(skb, emad_len); 848 849 return skb; 850 } 851 852 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 853 const struct mlxsw_reg_info *reg, 854 char *payload, 855 enum mlxsw_core_reg_access_type type, 856 struct mlxsw_reg_trans *trans, 857 struct list_head *bulk_list, 858 mlxsw_reg_trans_cb_t *cb, 859 unsigned long cb_priv, u64 tid) 860 { 861 bool enable_string_tlv; 862 struct sk_buff *skb; 863 int err; 864 865 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 866 tid, reg->id, mlxsw_reg_id_str(reg->id), 867 mlxsw_core_reg_access_type_str(type)); 868 869 /* Since this can be changed during emad_reg_access, read it once and 870 * use the value all the way. 871 */ 872 enable_string_tlv = mlxsw_core->emad.enable_string_tlv; 873 874 skb = mlxsw_emad_alloc(mlxsw_core, reg->len, enable_string_tlv); 875 if (!skb) 876 return -ENOMEM; 877 878 list_add_tail(&trans->bulk_list, bulk_list); 879 trans->core = mlxsw_core; 880 trans->tx_skb = skb; 881 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 882 trans->tx_info.is_emad = true; 883 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 884 trans->tid = tid; 885 init_completion(&trans->completion); 886 trans->cb = cb; 887 trans->cb_priv = cb_priv; 888 trans->reg = reg; 889 trans->type = type; 890 891 mlxsw_emad_construct(skb, reg, payload, type, trans->tid, 892 enable_string_tlv); 893 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 894 895 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 896 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 897 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 898 err = mlxsw_emad_transmit(mlxsw_core, trans); 899 if (err) 900 goto err_out; 901 return 0; 902 903 err_out: 904 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 905 list_del_rcu(&trans->list); 906 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 907 list_del(&trans->bulk_list); 908 dev_kfree_skb(trans->tx_skb); 909 return err; 910 } 911 912 /***************** 913 * Core functions 914 *****************/ 915 916 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 917 { 918 spin_lock(&mlxsw_core_driver_list_lock); 919 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 920 spin_unlock(&mlxsw_core_driver_list_lock); 921 return 0; 922 } 923 EXPORT_SYMBOL(mlxsw_core_driver_register); 924 925 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 926 { 927 spin_lock(&mlxsw_core_driver_list_lock); 928 list_del(&mlxsw_driver->list); 929 spin_unlock(&mlxsw_core_driver_list_lock); 930 } 931 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 932 933 static struct mlxsw_driver *__driver_find(const char *kind) 934 { 935 struct mlxsw_driver *mlxsw_driver; 936 937 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 938 if (strcmp(mlxsw_driver->kind, kind) == 0) 939 return mlxsw_driver; 940 } 941 return NULL; 942 } 943 944 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 945 { 946 struct mlxsw_driver *mlxsw_driver; 947 948 spin_lock(&mlxsw_core_driver_list_lock); 949 mlxsw_driver = __driver_find(kind); 950 spin_unlock(&mlxsw_core_driver_list_lock); 951 return mlxsw_driver; 952 } 953 954 struct mlxsw_core_fw_info { 955 struct mlxfw_dev mlxfw_dev; 956 struct mlxsw_core *mlxsw_core; 957 }; 958 959 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 960 u16 component_index, u32 *p_max_size, 961 u8 *p_align_bits, u16 *p_max_write_size) 962 { 963 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 964 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 965 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 966 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 967 int err; 968 969 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 970 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 971 if (err) 972 return err; 973 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 974 975 *p_align_bits = max_t(u8, *p_align_bits, 2); 976 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 977 return 0; 978 } 979 980 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 981 { 982 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 983 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 984 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 985 char mcc_pl[MLXSW_REG_MCC_LEN]; 986 u8 control_state; 987 int err; 988 989 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 990 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 991 if (err) 992 return err; 993 994 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 995 if (control_state != MLXFW_FSM_STATE_IDLE) 996 return -EBUSY; 997 998 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 999 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1000 } 1001 1002 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1003 u16 component_index, u32 component_size) 1004 { 1005 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1006 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1007 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1008 char mcc_pl[MLXSW_REG_MCC_LEN]; 1009 1010 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 1011 component_index, fwhandle, component_size); 1012 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1013 } 1014 1015 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1016 u8 *data, u16 size, u32 offset) 1017 { 1018 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1019 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1020 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1021 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1022 1023 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1024 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1025 } 1026 1027 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1028 u16 component_index) 1029 { 1030 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1031 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1032 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1033 char mcc_pl[MLXSW_REG_MCC_LEN]; 1034 1035 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1036 component_index, fwhandle, 0); 1037 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1038 } 1039 1040 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1041 { 1042 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1043 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1044 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1045 char mcc_pl[MLXSW_REG_MCC_LEN]; 1046 1047 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1048 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1049 } 1050 1051 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1052 enum mlxfw_fsm_state *fsm_state, 1053 enum mlxfw_fsm_state_err *fsm_state_err) 1054 { 1055 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1056 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1057 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1058 char mcc_pl[MLXSW_REG_MCC_LEN]; 1059 u8 control_state; 1060 u8 error_code; 1061 int err; 1062 1063 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1064 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1065 if (err) 1066 return err; 1067 1068 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1069 *fsm_state = control_state; 1070 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1071 return 0; 1072 } 1073 1074 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1075 { 1076 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1077 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1078 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1079 char mcc_pl[MLXSW_REG_MCC_LEN]; 1080 1081 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1082 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1083 } 1084 1085 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1086 { 1087 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1088 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1089 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1090 char mcc_pl[MLXSW_REG_MCC_LEN]; 1091 1092 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1093 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1094 } 1095 1096 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1097 .component_query = mlxsw_core_fw_component_query, 1098 .fsm_lock = mlxsw_core_fw_fsm_lock, 1099 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1100 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1101 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1102 .fsm_activate = mlxsw_core_fw_fsm_activate, 1103 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1104 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1105 .fsm_release = mlxsw_core_fw_fsm_release, 1106 }; 1107 1108 static int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, const struct firmware *firmware, 1109 struct netlink_ext_ack *extack) 1110 { 1111 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1112 .mlxfw_dev = { 1113 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1114 .psid = mlxsw_core->bus_info->psid, 1115 .psid_size = strlen(mlxsw_core->bus_info->psid), 1116 .devlink = priv_to_devlink(mlxsw_core), 1117 }, 1118 .mlxsw_core = mlxsw_core 1119 }; 1120 int err; 1121 1122 mlxsw_core->fw_flash_in_progress = true; 1123 err = mlxfw_firmware_flash(&mlxsw_core_fw_info.mlxfw_dev, firmware, extack); 1124 mlxsw_core->fw_flash_in_progress = false; 1125 1126 return err; 1127 } 1128 1129 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1130 const struct mlxsw_bus_info *mlxsw_bus_info, 1131 const struct mlxsw_fw_rev *req_rev, 1132 const char *filename) 1133 { 1134 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1135 union devlink_param_value value; 1136 const struct firmware *firmware; 1137 int err; 1138 1139 /* Don't check if driver does not require it */ 1140 if (!req_rev || !filename) 1141 return 0; 1142 1143 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1144 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1145 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1146 &value); 1147 if (err) 1148 return err; 1149 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1150 return 0; 1151 1152 /* Validate driver & FW are compatible */ 1153 if (rev->major != req_rev->major) { 1154 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1155 rev->major, req_rev->major); 1156 return -EINVAL; 1157 } 1158 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1159 return 0; 1160 1161 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1162 rev->major, rev->minor, rev->subminor, req_rev->major, 1163 req_rev->minor, req_rev->subminor); 1164 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1165 1166 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1167 if (err) { 1168 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1169 return err; 1170 } 1171 1172 err = mlxsw_core_fw_flash(mlxsw_core, firmware, NULL); 1173 release_firmware(firmware); 1174 if (err) 1175 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1176 1177 /* On FW flash success, tell the caller FW reset is needed 1178 * if current FW supports it. 1179 */ 1180 if (rev->minor >= req_rev->can_reset_minor) 1181 return err ? err : -EAGAIN; 1182 else 1183 return 0; 1184 } 1185 1186 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1187 struct devlink_flash_update_params *params, 1188 struct netlink_ext_ack *extack) 1189 { 1190 return mlxsw_core_fw_flash(mlxsw_core, params->fw, extack); 1191 } 1192 1193 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1194 union devlink_param_value val, 1195 struct netlink_ext_ack *extack) 1196 { 1197 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1198 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1199 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1200 return -EINVAL; 1201 } 1202 1203 return 0; 1204 } 1205 1206 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1207 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1208 mlxsw_core_devlink_param_fw_load_policy_validate), 1209 }; 1210 1211 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1212 { 1213 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1214 union devlink_param_value value; 1215 int err; 1216 1217 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1218 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1219 if (err) 1220 return err; 1221 1222 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1223 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1224 return 0; 1225 } 1226 1227 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1228 { 1229 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1230 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1231 } 1232 1233 static void *__dl_port(struct devlink_port *devlink_port) 1234 { 1235 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1236 } 1237 1238 static int mlxsw_devlink_port_split(struct devlink *devlink, 1239 struct devlink_port *port, 1240 unsigned int count, 1241 struct netlink_ext_ack *extack) 1242 { 1243 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1244 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1245 1246 if (!mlxsw_core->driver->port_split) 1247 return -EOPNOTSUPP; 1248 return mlxsw_core->driver->port_split(mlxsw_core, 1249 mlxsw_core_port->local_port, 1250 count, extack); 1251 } 1252 1253 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1254 struct devlink_port *port, 1255 struct netlink_ext_ack *extack) 1256 { 1257 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1258 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1259 1260 if (!mlxsw_core->driver->port_unsplit) 1261 return -EOPNOTSUPP; 1262 return mlxsw_core->driver->port_unsplit(mlxsw_core, 1263 mlxsw_core_port->local_port, 1264 extack); 1265 } 1266 1267 static int 1268 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1269 unsigned int sb_index, u16 pool_index, 1270 struct devlink_sb_pool_info *pool_info) 1271 { 1272 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1273 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1274 1275 if (!mlxsw_driver->sb_pool_get) 1276 return -EOPNOTSUPP; 1277 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1278 pool_index, pool_info); 1279 } 1280 1281 static int 1282 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1283 unsigned int sb_index, u16 pool_index, u32 size, 1284 enum devlink_sb_threshold_type threshold_type, 1285 struct netlink_ext_ack *extack) 1286 { 1287 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1288 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1289 1290 if (!mlxsw_driver->sb_pool_set) 1291 return -EOPNOTSUPP; 1292 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1293 pool_index, size, threshold_type, 1294 extack); 1295 } 1296 1297 static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port, 1298 enum devlink_port_type port_type) 1299 { 1300 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1301 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1302 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1303 1304 if (!mlxsw_driver->port_type_set) 1305 return -EOPNOTSUPP; 1306 1307 return mlxsw_driver->port_type_set(mlxsw_core, 1308 mlxsw_core_port->local_port, 1309 port_type); 1310 } 1311 1312 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1313 unsigned int sb_index, u16 pool_index, 1314 u32 *p_threshold) 1315 { 1316 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1317 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1318 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1319 1320 if (!mlxsw_driver->sb_port_pool_get || 1321 !mlxsw_core_port_check(mlxsw_core_port)) 1322 return -EOPNOTSUPP; 1323 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1324 pool_index, p_threshold); 1325 } 1326 1327 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1328 unsigned int sb_index, u16 pool_index, 1329 u32 threshold, 1330 struct netlink_ext_ack *extack) 1331 { 1332 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1333 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1334 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1335 1336 if (!mlxsw_driver->sb_port_pool_set || 1337 !mlxsw_core_port_check(mlxsw_core_port)) 1338 return -EOPNOTSUPP; 1339 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1340 pool_index, threshold, extack); 1341 } 1342 1343 static int 1344 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1345 unsigned int sb_index, u16 tc_index, 1346 enum devlink_sb_pool_type pool_type, 1347 u16 *p_pool_index, u32 *p_threshold) 1348 { 1349 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1350 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1351 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1352 1353 if (!mlxsw_driver->sb_tc_pool_bind_get || 1354 !mlxsw_core_port_check(mlxsw_core_port)) 1355 return -EOPNOTSUPP; 1356 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1357 tc_index, pool_type, 1358 p_pool_index, p_threshold); 1359 } 1360 1361 static int 1362 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1363 unsigned int sb_index, u16 tc_index, 1364 enum devlink_sb_pool_type pool_type, 1365 u16 pool_index, u32 threshold, 1366 struct netlink_ext_ack *extack) 1367 { 1368 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1369 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1370 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1371 1372 if (!mlxsw_driver->sb_tc_pool_bind_set || 1373 !mlxsw_core_port_check(mlxsw_core_port)) 1374 return -EOPNOTSUPP; 1375 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1376 tc_index, pool_type, 1377 pool_index, threshold, extack); 1378 } 1379 1380 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1381 unsigned int sb_index) 1382 { 1383 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1384 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1385 1386 if (!mlxsw_driver->sb_occ_snapshot) 1387 return -EOPNOTSUPP; 1388 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1389 } 1390 1391 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1392 unsigned int sb_index) 1393 { 1394 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1395 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1396 1397 if (!mlxsw_driver->sb_occ_max_clear) 1398 return -EOPNOTSUPP; 1399 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1400 } 1401 1402 static int 1403 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1404 unsigned int sb_index, u16 pool_index, 1405 u32 *p_cur, u32 *p_max) 1406 { 1407 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1408 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1409 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1410 1411 if (!mlxsw_driver->sb_occ_port_pool_get || 1412 !mlxsw_core_port_check(mlxsw_core_port)) 1413 return -EOPNOTSUPP; 1414 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1415 pool_index, p_cur, p_max); 1416 } 1417 1418 static int 1419 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1420 unsigned int sb_index, u16 tc_index, 1421 enum devlink_sb_pool_type pool_type, 1422 u32 *p_cur, u32 *p_max) 1423 { 1424 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1425 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1426 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1427 1428 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1429 !mlxsw_core_port_check(mlxsw_core_port)) 1430 return -EOPNOTSUPP; 1431 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1432 sb_index, tc_index, 1433 pool_type, p_cur, p_max); 1434 } 1435 1436 static int 1437 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1438 struct netlink_ext_ack *extack) 1439 { 1440 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1441 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1442 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1443 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1444 char buf[32]; 1445 int err; 1446 1447 err = devlink_info_driver_name_put(req, 1448 mlxsw_core->bus_info->device_kind); 1449 if (err) 1450 return err; 1451 1452 mlxsw_reg_mgir_pack(mgir_pl); 1453 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1454 if (err) 1455 return err; 1456 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1457 &fw_minor, &fw_sub_minor); 1458 1459 sprintf(buf, "%X", hw_rev); 1460 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1461 if (err) 1462 return err; 1463 1464 err = devlink_info_version_fixed_put(req, 1465 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1466 fw_info_psid); 1467 if (err) 1468 return err; 1469 1470 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1471 err = devlink_info_version_running_put(req, "fw.version", buf); 1472 if (err) 1473 return err; 1474 1475 return devlink_info_version_running_put(req, 1476 DEVLINK_INFO_VERSION_GENERIC_FW, 1477 buf); 1478 } 1479 1480 static int 1481 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1482 bool netns_change, enum devlink_reload_action action, 1483 enum devlink_reload_limit limit, 1484 struct netlink_ext_ack *extack) 1485 { 1486 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1487 1488 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1489 return -EOPNOTSUPP; 1490 1491 devl_lock(devlink); 1492 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1493 devl_unlock(devlink); 1494 return 0; 1495 } 1496 1497 static int 1498 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1499 enum devlink_reload_limit limit, u32 *actions_performed, 1500 struct netlink_ext_ack *extack) 1501 { 1502 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1503 int err; 1504 1505 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1506 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1507 devl_lock(devlink); 1508 err = mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1509 mlxsw_core->bus, 1510 mlxsw_core->bus_priv, true, 1511 devlink, extack); 1512 devl_unlock(devlink); 1513 return err; 1514 } 1515 1516 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1517 struct devlink_flash_update_params *params, 1518 struct netlink_ext_ack *extack) 1519 { 1520 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1521 1522 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1523 } 1524 1525 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1526 const struct devlink_trap *trap, 1527 void *trap_ctx) 1528 { 1529 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1530 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1531 1532 if (!mlxsw_driver->trap_init) 1533 return -EOPNOTSUPP; 1534 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1535 } 1536 1537 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1538 const struct devlink_trap *trap, 1539 void *trap_ctx) 1540 { 1541 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1542 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1543 1544 if (!mlxsw_driver->trap_fini) 1545 return; 1546 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1547 } 1548 1549 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1550 const struct devlink_trap *trap, 1551 enum devlink_trap_action action, 1552 struct netlink_ext_ack *extack) 1553 { 1554 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1555 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1556 1557 if (!mlxsw_driver->trap_action_set) 1558 return -EOPNOTSUPP; 1559 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1560 } 1561 1562 static int 1563 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1564 const struct devlink_trap_group *group) 1565 { 1566 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1567 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1568 1569 if (!mlxsw_driver->trap_group_init) 1570 return -EOPNOTSUPP; 1571 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1572 } 1573 1574 static int 1575 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1576 const struct devlink_trap_group *group, 1577 const struct devlink_trap_policer *policer, 1578 struct netlink_ext_ack *extack) 1579 { 1580 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1581 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1582 1583 if (!mlxsw_driver->trap_group_set) 1584 return -EOPNOTSUPP; 1585 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1586 } 1587 1588 static int 1589 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1590 const struct devlink_trap_policer *policer) 1591 { 1592 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1593 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1594 1595 if (!mlxsw_driver->trap_policer_init) 1596 return -EOPNOTSUPP; 1597 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1598 } 1599 1600 static void 1601 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1602 const struct devlink_trap_policer *policer) 1603 { 1604 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1605 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1606 1607 if (!mlxsw_driver->trap_policer_fini) 1608 return; 1609 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1610 } 1611 1612 static int 1613 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1614 const struct devlink_trap_policer *policer, 1615 u64 rate, u64 burst, 1616 struct netlink_ext_ack *extack) 1617 { 1618 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1619 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1620 1621 if (!mlxsw_driver->trap_policer_set) 1622 return -EOPNOTSUPP; 1623 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1624 extack); 1625 } 1626 1627 static int 1628 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1629 const struct devlink_trap_policer *policer, 1630 u64 *p_drops) 1631 { 1632 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1633 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1634 1635 if (!mlxsw_driver->trap_policer_counter_get) 1636 return -EOPNOTSUPP; 1637 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1638 p_drops); 1639 } 1640 1641 static const struct devlink_ops mlxsw_devlink_ops = { 1642 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1643 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1644 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1645 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1646 .port_type_set = mlxsw_devlink_port_type_set, 1647 .port_split = mlxsw_devlink_port_split, 1648 .port_unsplit = mlxsw_devlink_port_unsplit, 1649 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1650 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1651 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1652 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1653 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1654 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1655 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1656 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1657 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1658 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1659 .info_get = mlxsw_devlink_info_get, 1660 .flash_update = mlxsw_devlink_flash_update, 1661 .trap_init = mlxsw_devlink_trap_init, 1662 .trap_fini = mlxsw_devlink_trap_fini, 1663 .trap_action_set = mlxsw_devlink_trap_action_set, 1664 .trap_group_init = mlxsw_devlink_trap_group_init, 1665 .trap_group_set = mlxsw_devlink_trap_group_set, 1666 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1667 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1668 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1669 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1670 }; 1671 1672 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1673 { 1674 int err; 1675 1676 err = mlxsw_core_fw_params_register(mlxsw_core); 1677 if (err) 1678 return err; 1679 1680 if (mlxsw_core->driver->params_register) { 1681 err = mlxsw_core->driver->params_register(mlxsw_core); 1682 if (err) 1683 goto err_params_register; 1684 } 1685 return 0; 1686 1687 err_params_register: 1688 mlxsw_core_fw_params_unregister(mlxsw_core); 1689 return err; 1690 } 1691 1692 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1693 { 1694 mlxsw_core_fw_params_unregister(mlxsw_core); 1695 if (mlxsw_core->driver->params_register) 1696 mlxsw_core->driver->params_unregister(mlxsw_core); 1697 } 1698 1699 struct mlxsw_core_health_event { 1700 struct mlxsw_core *mlxsw_core; 1701 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1702 struct work_struct work; 1703 }; 1704 1705 static void mlxsw_core_health_event_work(struct work_struct *work) 1706 { 1707 struct mlxsw_core_health_event *event; 1708 struct mlxsw_core *mlxsw_core; 1709 1710 event = container_of(work, struct mlxsw_core_health_event, work); 1711 mlxsw_core = event->mlxsw_core; 1712 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1713 event->mfde_pl); 1714 kfree(event); 1715 } 1716 1717 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1718 char *mfde_pl, void *priv) 1719 { 1720 struct mlxsw_core_health_event *event; 1721 struct mlxsw_core *mlxsw_core = priv; 1722 1723 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1724 if (!event) 1725 return; 1726 event->mlxsw_core = mlxsw_core; 1727 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1728 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1729 mlxsw_core_schedule_work(&event->work); 1730 } 1731 1732 static const struct mlxsw_listener mlxsw_core_health_listener = 1733 MLXSW_CORE_EVENTL(mlxsw_core_health_listener_func, MFDE); 1734 1735 static int 1736 mlxsw_core_health_fw_fatal_dump_fatal_cause(const char *mfde_pl, 1737 struct devlink_fmsg *fmsg) 1738 { 1739 u32 val, tile_v; 1740 int err; 1741 1742 val = mlxsw_reg_mfde_fatal_cause_id_get(mfde_pl); 1743 err = devlink_fmsg_u32_pair_put(fmsg, "cause_id", val); 1744 if (err) 1745 return err; 1746 tile_v = mlxsw_reg_mfde_fatal_cause_tile_v_get(mfde_pl); 1747 if (tile_v) { 1748 val = mlxsw_reg_mfde_fatal_cause_tile_index_get(mfde_pl); 1749 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1750 if (err) 1751 return err; 1752 } 1753 1754 return 0; 1755 } 1756 1757 static int 1758 mlxsw_core_health_fw_fatal_dump_fw_assert(const char *mfde_pl, 1759 struct devlink_fmsg *fmsg) 1760 { 1761 u32 val, tile_v; 1762 int err; 1763 1764 val = mlxsw_reg_mfde_fw_assert_var0_get(mfde_pl); 1765 err = devlink_fmsg_u32_pair_put(fmsg, "var0", val); 1766 if (err) 1767 return err; 1768 val = mlxsw_reg_mfde_fw_assert_var1_get(mfde_pl); 1769 err = devlink_fmsg_u32_pair_put(fmsg, "var1", val); 1770 if (err) 1771 return err; 1772 val = mlxsw_reg_mfde_fw_assert_var2_get(mfde_pl); 1773 err = devlink_fmsg_u32_pair_put(fmsg, "var2", val); 1774 if (err) 1775 return err; 1776 val = mlxsw_reg_mfde_fw_assert_var3_get(mfde_pl); 1777 err = devlink_fmsg_u32_pair_put(fmsg, "var3", val); 1778 if (err) 1779 return err; 1780 val = mlxsw_reg_mfde_fw_assert_var4_get(mfde_pl); 1781 err = devlink_fmsg_u32_pair_put(fmsg, "var4", val); 1782 if (err) 1783 return err; 1784 val = mlxsw_reg_mfde_fw_assert_existptr_get(mfde_pl); 1785 err = devlink_fmsg_u32_pair_put(fmsg, "existptr", val); 1786 if (err) 1787 return err; 1788 val = mlxsw_reg_mfde_fw_assert_callra_get(mfde_pl); 1789 err = devlink_fmsg_u32_pair_put(fmsg, "callra", val); 1790 if (err) 1791 return err; 1792 val = mlxsw_reg_mfde_fw_assert_oe_get(mfde_pl); 1793 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1794 if (err) 1795 return err; 1796 tile_v = mlxsw_reg_mfde_fw_assert_tile_v_get(mfde_pl); 1797 if (tile_v) { 1798 val = mlxsw_reg_mfde_fw_assert_tile_index_get(mfde_pl); 1799 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1800 if (err) 1801 return err; 1802 } 1803 val = mlxsw_reg_mfde_fw_assert_ext_synd_get(mfde_pl); 1804 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", val); 1805 if (err) 1806 return err; 1807 1808 return 0; 1809 } 1810 1811 static int 1812 mlxsw_core_health_fw_fatal_dump_kvd_im_stop(const char *mfde_pl, 1813 struct devlink_fmsg *fmsg) 1814 { 1815 u32 val; 1816 int err; 1817 1818 val = mlxsw_reg_mfde_kvd_im_stop_oe_get(mfde_pl); 1819 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1820 if (err) 1821 return err; 1822 val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl); 1823 return devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1824 } 1825 1826 static int 1827 mlxsw_core_health_fw_fatal_dump_crspace_to(const char *mfde_pl, 1828 struct devlink_fmsg *fmsg) 1829 { 1830 u32 val; 1831 int err; 1832 1833 val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl); 1834 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1835 if (err) 1836 return err; 1837 val = mlxsw_reg_mfde_crspace_to_oe_get(mfde_pl); 1838 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1839 if (err) 1840 return err; 1841 val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl); 1842 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1843 if (err) 1844 return err; 1845 val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl); 1846 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1847 if (err) 1848 return err; 1849 1850 return 0; 1851 } 1852 1853 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1854 struct devlink_fmsg *fmsg, void *priv_ctx, 1855 struct netlink_ext_ack *extack) 1856 { 1857 char *mfde_pl = priv_ctx; 1858 char *val_str; 1859 u8 event_id; 1860 u32 val; 1861 int err; 1862 1863 if (!priv_ctx) 1864 /* User-triggered dumps are not possible */ 1865 return -EOPNOTSUPP; 1866 1867 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1868 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1869 if (err) 1870 return err; 1871 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1872 if (err) 1873 return err; 1874 1875 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1876 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1877 if (err) 1878 return err; 1879 switch (event_id) { 1880 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1881 val_str = "CR space timeout"; 1882 break; 1883 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1884 val_str = "KVD insertion machine stopped"; 1885 break; 1886 case MLXSW_REG_MFDE_EVENT_ID_TEST: 1887 val_str = "Test"; 1888 break; 1889 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1890 val_str = "FW assert"; 1891 break; 1892 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1893 val_str = "Fatal cause"; 1894 break; 1895 default: 1896 val_str = NULL; 1897 } 1898 if (val_str) { 1899 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1900 if (err) 1901 return err; 1902 } 1903 1904 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1905 if (err) 1906 return err; 1907 1908 err = devlink_fmsg_arr_pair_nest_start(fmsg, "severity"); 1909 if (err) 1910 return err; 1911 1912 val = mlxsw_reg_mfde_severity_get(mfde_pl); 1913 err = devlink_fmsg_u8_pair_put(fmsg, "id", val); 1914 if (err) 1915 return err; 1916 switch (val) { 1917 case MLXSW_REG_MFDE_SEVERITY_FATL: 1918 val_str = "Fatal"; 1919 break; 1920 case MLXSW_REG_MFDE_SEVERITY_NRML: 1921 val_str = "Normal"; 1922 break; 1923 case MLXSW_REG_MFDE_SEVERITY_INTR: 1924 val_str = "Debug"; 1925 break; 1926 default: 1927 val_str = NULL; 1928 } 1929 if (val_str) { 1930 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1931 if (err) 1932 return err; 1933 } 1934 1935 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1936 if (err) 1937 return err; 1938 1939 val = mlxsw_reg_mfde_method_get(mfde_pl); 1940 switch (val) { 1941 case MLXSW_REG_MFDE_METHOD_QUERY: 1942 val_str = "query"; 1943 break; 1944 case MLXSW_REG_MFDE_METHOD_WRITE: 1945 val_str = "write"; 1946 break; 1947 default: 1948 val_str = NULL; 1949 } 1950 if (val_str) { 1951 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 1952 if (err) 1953 return err; 1954 } 1955 1956 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 1957 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 1958 if (err) 1959 return err; 1960 1961 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 1962 switch (val) { 1963 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 1964 val_str = "mad"; 1965 break; 1966 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 1967 val_str = "emad"; 1968 break; 1969 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 1970 val_str = "cmdif"; 1971 break; 1972 default: 1973 val_str = NULL; 1974 } 1975 if (val_str) { 1976 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 1977 if (err) 1978 return err; 1979 } 1980 1981 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 1982 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 1983 if (err) 1984 return err; 1985 1986 switch (event_id) { 1987 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1988 return mlxsw_core_health_fw_fatal_dump_crspace_to(mfde_pl, 1989 fmsg); 1990 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1991 return mlxsw_core_health_fw_fatal_dump_kvd_im_stop(mfde_pl, 1992 fmsg); 1993 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1994 return mlxsw_core_health_fw_fatal_dump_fw_assert(mfde_pl, fmsg); 1995 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1996 return mlxsw_core_health_fw_fatal_dump_fatal_cause(mfde_pl, 1997 fmsg); 1998 } 1999 2000 return 0; 2001 } 2002 2003 static int 2004 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 2005 struct netlink_ext_ack *extack) 2006 { 2007 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 2008 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2009 int err; 2010 2011 /* Read the register first to make sure no other bits are changed. */ 2012 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2013 if (err) 2014 return err; 2015 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 2016 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2017 } 2018 2019 static const struct devlink_health_reporter_ops 2020 mlxsw_core_health_fw_fatal_ops = { 2021 .name = "fw_fatal", 2022 .dump = mlxsw_core_health_fw_fatal_dump, 2023 .test = mlxsw_core_health_fw_fatal_test, 2024 }; 2025 2026 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 2027 bool enable) 2028 { 2029 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2030 int err; 2031 2032 /* Read the register first to make sure no other bits are changed. */ 2033 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2034 if (err) 2035 return err; 2036 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 2037 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2038 } 2039 2040 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 2041 { 2042 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2043 struct devlink_health_reporter *fw_fatal; 2044 int err; 2045 2046 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2047 return 0; 2048 2049 fw_fatal = devlink_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 2050 0, mlxsw_core); 2051 if (IS_ERR(fw_fatal)) { 2052 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 2053 return PTR_ERR(fw_fatal); 2054 } 2055 mlxsw_core->health.fw_fatal = fw_fatal; 2056 2057 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2058 if (err) 2059 goto err_trap_register; 2060 2061 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 2062 if (err) 2063 goto err_fw_fatal_config; 2064 2065 return 0; 2066 2067 err_fw_fatal_config: 2068 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2069 err_trap_register: 2070 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2071 return err; 2072 } 2073 2074 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 2075 { 2076 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2077 return; 2078 2079 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 2080 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2081 /* Make sure there is no more event work scheduled */ 2082 mlxsw_core_flush_owq(); 2083 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2084 } 2085 2086 static int 2087 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2088 const struct mlxsw_bus *mlxsw_bus, 2089 void *bus_priv, bool reload, 2090 struct devlink *devlink, 2091 struct netlink_ext_ack *extack) 2092 { 2093 const char *device_kind = mlxsw_bus_info->device_kind; 2094 struct mlxsw_core *mlxsw_core; 2095 struct mlxsw_driver *mlxsw_driver; 2096 size_t alloc_size; 2097 int err; 2098 2099 mlxsw_driver = mlxsw_core_driver_get(device_kind); 2100 if (!mlxsw_driver) 2101 return -EINVAL; 2102 2103 if (!reload) { 2104 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 2105 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 2106 mlxsw_bus_info->dev); 2107 if (!devlink) { 2108 err = -ENOMEM; 2109 goto err_devlink_alloc; 2110 } 2111 devl_lock(devlink); 2112 } 2113 2114 mlxsw_core = devlink_priv(devlink); 2115 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 2116 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 2117 mlxsw_core->driver = mlxsw_driver; 2118 mlxsw_core->bus = mlxsw_bus; 2119 mlxsw_core->bus_priv = bus_priv; 2120 mlxsw_core->bus_info = mlxsw_bus_info; 2121 2122 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, 2123 &mlxsw_core->res); 2124 if (err) 2125 goto err_bus_init; 2126 2127 if (mlxsw_driver->resources_register && !reload) { 2128 err = mlxsw_driver->resources_register(mlxsw_core); 2129 if (err) 2130 goto err_register_resources; 2131 } 2132 2133 err = mlxsw_ports_init(mlxsw_core, reload); 2134 if (err) 2135 goto err_ports_init; 2136 2137 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) && 2138 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 2139 alloc_size = sizeof(*mlxsw_core->lag.mapping) * 2140 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * 2141 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 2142 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 2143 if (!mlxsw_core->lag.mapping) { 2144 err = -ENOMEM; 2145 goto err_alloc_lag_mapping; 2146 } 2147 } 2148 2149 err = mlxsw_core_trap_groups_set(mlxsw_core); 2150 if (err) 2151 goto err_trap_groups_set; 2152 2153 err = mlxsw_emad_init(mlxsw_core); 2154 if (err) 2155 goto err_emad_init; 2156 2157 if (!reload) { 2158 err = mlxsw_core_params_register(mlxsw_core); 2159 if (err) 2160 goto err_register_params; 2161 } 2162 2163 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 2164 mlxsw_driver->fw_filename); 2165 if (err) 2166 goto err_fw_rev_validate; 2167 2168 err = mlxsw_linecards_init(mlxsw_core, mlxsw_bus_info); 2169 if (err) 2170 goto err_linecards_init; 2171 2172 err = mlxsw_core_health_init(mlxsw_core); 2173 if (err) 2174 goto err_health_init; 2175 2176 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 2177 if (err) 2178 goto err_hwmon_init; 2179 2180 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 2181 &mlxsw_core->thermal); 2182 if (err) 2183 goto err_thermal_init; 2184 2185 err = mlxsw_env_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->env); 2186 if (err) 2187 goto err_env_init; 2188 2189 if (mlxsw_driver->init) { 2190 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2191 if (err) 2192 goto err_driver_init; 2193 } 2194 2195 if (!reload) { 2196 devlink_set_features(devlink, DEVLINK_F_RELOAD); 2197 devl_unlock(devlink); 2198 devlink_register(devlink); 2199 } 2200 return 0; 2201 2202 err_driver_init: 2203 mlxsw_env_fini(mlxsw_core->env); 2204 err_env_init: 2205 mlxsw_thermal_fini(mlxsw_core->thermal); 2206 err_thermal_init: 2207 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2208 err_hwmon_init: 2209 mlxsw_core_health_fini(mlxsw_core); 2210 err_health_init: 2211 mlxsw_linecards_fini(mlxsw_core); 2212 err_linecards_init: 2213 err_fw_rev_validate: 2214 if (!reload) 2215 mlxsw_core_params_unregister(mlxsw_core); 2216 err_register_params: 2217 mlxsw_emad_fini(mlxsw_core); 2218 err_emad_init: 2219 err_trap_groups_set: 2220 kfree(mlxsw_core->lag.mapping); 2221 err_alloc_lag_mapping: 2222 mlxsw_ports_fini(mlxsw_core, reload); 2223 err_ports_init: 2224 if (!reload) 2225 devl_resources_unregister(devlink); 2226 err_register_resources: 2227 mlxsw_bus->fini(bus_priv); 2228 err_bus_init: 2229 if (!reload) { 2230 devl_unlock(devlink); 2231 devlink_free(devlink); 2232 } 2233 err_devlink_alloc: 2234 return err; 2235 } 2236 2237 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2238 const struct mlxsw_bus *mlxsw_bus, 2239 void *bus_priv, bool reload, 2240 struct devlink *devlink, 2241 struct netlink_ext_ack *extack) 2242 { 2243 bool called_again = false; 2244 int err; 2245 2246 again: 2247 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2248 bus_priv, reload, 2249 devlink, extack); 2250 /* -EAGAIN is returned in case the FW was updated. FW needs 2251 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2252 * again. 2253 */ 2254 if (err == -EAGAIN && !called_again) { 2255 called_again = true; 2256 goto again; 2257 } 2258 2259 return err; 2260 } 2261 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2262 2263 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2264 bool reload) 2265 { 2266 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2267 2268 if (!reload) { 2269 devlink_unregister(devlink); 2270 devl_lock(devlink); 2271 } 2272 2273 if (devlink_is_reload_failed(devlink)) { 2274 if (!reload) 2275 /* Only the parts that were not de-initialized in the 2276 * failed reload attempt need to be de-initialized. 2277 */ 2278 goto reload_fail_deinit; 2279 else 2280 return; 2281 } 2282 2283 if (mlxsw_core->driver->fini) 2284 mlxsw_core->driver->fini(mlxsw_core); 2285 mlxsw_env_fini(mlxsw_core->env); 2286 mlxsw_thermal_fini(mlxsw_core->thermal); 2287 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2288 mlxsw_core_health_fini(mlxsw_core); 2289 mlxsw_linecards_fini(mlxsw_core); 2290 if (!reload) 2291 mlxsw_core_params_unregister(mlxsw_core); 2292 mlxsw_emad_fini(mlxsw_core); 2293 kfree(mlxsw_core->lag.mapping); 2294 mlxsw_ports_fini(mlxsw_core, reload); 2295 if (!reload) 2296 devl_resources_unregister(devlink); 2297 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2298 if (!reload) { 2299 devlink_free(devlink); 2300 devl_unlock(devlink); 2301 } 2302 2303 return; 2304 2305 reload_fail_deinit: 2306 mlxsw_core_params_unregister(mlxsw_core); 2307 devl_resources_unregister(devlink); 2308 devlink_free(devlink); 2309 devl_unlock(devlink); 2310 } 2311 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2312 2313 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2314 const struct mlxsw_tx_info *tx_info) 2315 { 2316 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2317 tx_info); 2318 } 2319 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2320 2321 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2322 const struct mlxsw_tx_info *tx_info) 2323 { 2324 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2325 tx_info); 2326 } 2327 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2328 2329 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2330 struct sk_buff *skb, u16 local_port) 2331 { 2332 if (mlxsw_core->driver->ptp_transmitted) 2333 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2334 local_port); 2335 } 2336 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2337 2338 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2339 const struct mlxsw_rx_listener *rxl_b) 2340 { 2341 return (rxl_a->func == rxl_b->func && 2342 rxl_a->local_port == rxl_b->local_port && 2343 rxl_a->trap_id == rxl_b->trap_id && 2344 rxl_a->mirror_reason == rxl_b->mirror_reason); 2345 } 2346 2347 static struct mlxsw_rx_listener_item * 2348 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2349 const struct mlxsw_rx_listener *rxl) 2350 { 2351 struct mlxsw_rx_listener_item *rxl_item; 2352 2353 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2354 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2355 return rxl_item; 2356 } 2357 return NULL; 2358 } 2359 2360 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2361 const struct mlxsw_rx_listener *rxl, 2362 void *priv, bool enabled) 2363 { 2364 struct mlxsw_rx_listener_item *rxl_item; 2365 2366 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2367 if (rxl_item) 2368 return -EEXIST; 2369 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2370 if (!rxl_item) 2371 return -ENOMEM; 2372 rxl_item->rxl = *rxl; 2373 rxl_item->priv = priv; 2374 rxl_item->enabled = enabled; 2375 2376 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2377 return 0; 2378 } 2379 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2380 2381 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2382 const struct mlxsw_rx_listener *rxl) 2383 { 2384 struct mlxsw_rx_listener_item *rxl_item; 2385 2386 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2387 if (!rxl_item) 2388 return; 2389 list_del_rcu(&rxl_item->list); 2390 synchronize_rcu(); 2391 kfree(rxl_item); 2392 } 2393 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2394 2395 static void 2396 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2397 const struct mlxsw_rx_listener *rxl, 2398 bool enabled) 2399 { 2400 struct mlxsw_rx_listener_item *rxl_item; 2401 2402 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2403 if (WARN_ON(!rxl_item)) 2404 return; 2405 rxl_item->enabled = enabled; 2406 } 2407 2408 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u16 local_port, 2409 void *priv) 2410 { 2411 struct mlxsw_event_listener_item *event_listener_item = priv; 2412 struct mlxsw_core *mlxsw_core; 2413 struct mlxsw_reg_info reg; 2414 char *payload; 2415 char *reg_tlv; 2416 char *op_tlv; 2417 2418 mlxsw_core = event_listener_item->mlxsw_core; 2419 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2420 skb->data, skb->len); 2421 2422 mlxsw_emad_tlv_parse(skb); 2423 op_tlv = mlxsw_emad_op_tlv(skb); 2424 reg_tlv = mlxsw_emad_reg_tlv(skb); 2425 2426 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2427 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2428 payload = mlxsw_emad_reg_payload(reg_tlv); 2429 event_listener_item->el.func(®, payload, event_listener_item->priv); 2430 dev_kfree_skb(skb); 2431 } 2432 2433 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2434 const struct mlxsw_event_listener *el_b) 2435 { 2436 return (el_a->func == el_b->func && 2437 el_a->trap_id == el_b->trap_id); 2438 } 2439 2440 static struct mlxsw_event_listener_item * 2441 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2442 const struct mlxsw_event_listener *el) 2443 { 2444 struct mlxsw_event_listener_item *el_item; 2445 2446 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2447 if (__is_event_listener_equal(&el_item->el, el)) 2448 return el_item; 2449 } 2450 return NULL; 2451 } 2452 2453 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2454 const struct mlxsw_event_listener *el, 2455 void *priv) 2456 { 2457 int err; 2458 struct mlxsw_event_listener_item *el_item; 2459 const struct mlxsw_rx_listener rxl = { 2460 .func = mlxsw_core_event_listener_func, 2461 .local_port = MLXSW_PORT_DONT_CARE, 2462 .trap_id = el->trap_id, 2463 }; 2464 2465 el_item = __find_event_listener_item(mlxsw_core, el); 2466 if (el_item) 2467 return -EEXIST; 2468 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2469 if (!el_item) 2470 return -ENOMEM; 2471 el_item->mlxsw_core = mlxsw_core; 2472 el_item->el = *el; 2473 el_item->priv = priv; 2474 2475 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2476 if (err) 2477 goto err_rx_listener_register; 2478 2479 /* No reason to save item if we did not manage to register an RX 2480 * listener for it. 2481 */ 2482 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2483 2484 return 0; 2485 2486 err_rx_listener_register: 2487 kfree(el_item); 2488 return err; 2489 } 2490 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2491 2492 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2493 const struct mlxsw_event_listener *el) 2494 { 2495 struct mlxsw_event_listener_item *el_item; 2496 const struct mlxsw_rx_listener rxl = { 2497 .func = mlxsw_core_event_listener_func, 2498 .local_port = MLXSW_PORT_DONT_CARE, 2499 .trap_id = el->trap_id, 2500 }; 2501 2502 el_item = __find_event_listener_item(mlxsw_core, el); 2503 if (!el_item) 2504 return; 2505 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2506 list_del(&el_item->list); 2507 kfree(el_item); 2508 } 2509 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2510 2511 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2512 const struct mlxsw_listener *listener, 2513 void *priv, bool enabled) 2514 { 2515 if (listener->is_event) { 2516 WARN_ON(!enabled); 2517 return mlxsw_core_event_listener_register(mlxsw_core, 2518 &listener->event_listener, 2519 priv); 2520 } else { 2521 return mlxsw_core_rx_listener_register(mlxsw_core, 2522 &listener->rx_listener, 2523 priv, enabled); 2524 } 2525 } 2526 2527 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2528 const struct mlxsw_listener *listener, 2529 void *priv) 2530 { 2531 if (listener->is_event) 2532 mlxsw_core_event_listener_unregister(mlxsw_core, 2533 &listener->event_listener); 2534 else 2535 mlxsw_core_rx_listener_unregister(mlxsw_core, 2536 &listener->rx_listener); 2537 } 2538 2539 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2540 const struct mlxsw_listener *listener, void *priv) 2541 { 2542 enum mlxsw_reg_htgt_trap_group trap_group; 2543 enum mlxsw_reg_hpkt_action action; 2544 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2545 int err; 2546 2547 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2548 return 0; 2549 2550 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2551 listener->enabled_on_register); 2552 if (err) 2553 return err; 2554 2555 action = listener->enabled_on_register ? listener->en_action : 2556 listener->dis_action; 2557 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2558 listener->dis_trap_group; 2559 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2560 trap_group, listener->is_ctrl); 2561 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2562 if (err) 2563 goto err_trap_set; 2564 2565 return 0; 2566 2567 err_trap_set: 2568 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2569 return err; 2570 } 2571 EXPORT_SYMBOL(mlxsw_core_trap_register); 2572 2573 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2574 const struct mlxsw_listener *listener, 2575 void *priv) 2576 { 2577 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2578 2579 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2580 return; 2581 2582 if (!listener->is_event) { 2583 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2584 listener->trap_id, listener->dis_trap_group, 2585 listener->is_ctrl); 2586 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2587 } 2588 2589 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2590 } 2591 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2592 2593 int mlxsw_core_traps_register(struct mlxsw_core *mlxsw_core, 2594 const struct mlxsw_listener *listeners, 2595 size_t listeners_count, void *priv) 2596 { 2597 int i, err; 2598 2599 for (i = 0; i < listeners_count; i++) { 2600 err = mlxsw_core_trap_register(mlxsw_core, 2601 &listeners[i], 2602 priv); 2603 if (err) 2604 goto err_listener_register; 2605 } 2606 return 0; 2607 2608 err_listener_register: 2609 for (i--; i >= 0; i--) { 2610 mlxsw_core_trap_unregister(mlxsw_core, 2611 &listeners[i], 2612 priv); 2613 } 2614 return err; 2615 } 2616 EXPORT_SYMBOL(mlxsw_core_traps_register); 2617 2618 void mlxsw_core_traps_unregister(struct mlxsw_core *mlxsw_core, 2619 const struct mlxsw_listener *listeners, 2620 size_t listeners_count, void *priv) 2621 { 2622 int i; 2623 2624 for (i = 0; i < listeners_count; i++) { 2625 mlxsw_core_trap_unregister(mlxsw_core, 2626 &listeners[i], 2627 priv); 2628 } 2629 } 2630 EXPORT_SYMBOL(mlxsw_core_traps_unregister); 2631 2632 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2633 const struct mlxsw_listener *listener, 2634 bool enabled) 2635 { 2636 enum mlxsw_reg_htgt_trap_group trap_group; 2637 enum mlxsw_reg_hpkt_action action; 2638 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2639 int err; 2640 2641 /* Not supported for event listener */ 2642 if (WARN_ON(listener->is_event)) 2643 return -EINVAL; 2644 2645 action = enabled ? listener->en_action : listener->dis_action; 2646 trap_group = enabled ? listener->en_trap_group : 2647 listener->dis_trap_group; 2648 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2649 trap_group, listener->is_ctrl); 2650 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2651 if (err) 2652 return err; 2653 2654 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2655 enabled); 2656 return 0; 2657 } 2658 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2659 2660 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2661 { 2662 return atomic64_inc_return(&mlxsw_core->emad.tid); 2663 } 2664 2665 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2666 const struct mlxsw_reg_info *reg, 2667 char *payload, 2668 enum mlxsw_core_reg_access_type type, 2669 struct list_head *bulk_list, 2670 mlxsw_reg_trans_cb_t *cb, 2671 unsigned long cb_priv) 2672 { 2673 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2674 struct mlxsw_reg_trans *trans; 2675 int err; 2676 2677 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2678 if (!trans) 2679 return -ENOMEM; 2680 2681 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2682 bulk_list, cb, cb_priv, tid); 2683 if (err) { 2684 kfree_rcu(trans, rcu); 2685 return err; 2686 } 2687 return 0; 2688 } 2689 2690 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2691 const struct mlxsw_reg_info *reg, char *payload, 2692 struct list_head *bulk_list, 2693 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2694 { 2695 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2696 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2697 bulk_list, cb, cb_priv); 2698 } 2699 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2700 2701 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2702 const struct mlxsw_reg_info *reg, char *payload, 2703 struct list_head *bulk_list, 2704 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2705 { 2706 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2707 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2708 bulk_list, cb, cb_priv); 2709 } 2710 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2711 2712 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2713 2714 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2715 { 2716 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2717 struct mlxsw_core *mlxsw_core = trans->core; 2718 int err; 2719 2720 wait_for_completion(&trans->completion); 2721 cancel_delayed_work_sync(&trans->timeout_dw); 2722 err = trans->err; 2723 2724 if (trans->retries) 2725 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2726 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2727 if (err) { 2728 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2729 trans->tid, trans->reg->id, 2730 mlxsw_reg_id_str(trans->reg->id), 2731 mlxsw_core_reg_access_type_str(trans->type), 2732 trans->emad_status, 2733 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2734 2735 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2736 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2737 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2738 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2739 trans->emad_err_string ? trans->emad_err_string : ""); 2740 2741 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2742 trans->emad_status, err_string); 2743 2744 kfree(trans->emad_err_string); 2745 } 2746 2747 list_del(&trans->bulk_list); 2748 kfree_rcu(trans, rcu); 2749 return err; 2750 } 2751 2752 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2753 { 2754 struct mlxsw_reg_trans *trans; 2755 struct mlxsw_reg_trans *tmp; 2756 int sum_err = 0; 2757 int err; 2758 2759 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2760 err = mlxsw_reg_trans_wait(trans); 2761 if (err && sum_err == 0) 2762 sum_err = err; /* first error to be returned */ 2763 } 2764 return sum_err; 2765 } 2766 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2767 2768 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2769 const struct mlxsw_reg_info *reg, 2770 char *payload, 2771 enum mlxsw_core_reg_access_type type) 2772 { 2773 enum mlxsw_emad_op_tlv_status status; 2774 int err, n_retry; 2775 bool reset_ok; 2776 char *in_mbox, *out_mbox, *tmp; 2777 2778 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2779 reg->id, mlxsw_reg_id_str(reg->id), 2780 mlxsw_core_reg_access_type_str(type)); 2781 2782 in_mbox = mlxsw_cmd_mbox_alloc(); 2783 if (!in_mbox) 2784 return -ENOMEM; 2785 2786 out_mbox = mlxsw_cmd_mbox_alloc(); 2787 if (!out_mbox) { 2788 err = -ENOMEM; 2789 goto free_in_mbox; 2790 } 2791 2792 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2793 mlxsw_core_tid_get(mlxsw_core)); 2794 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2795 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2796 2797 /* There is a special treatment needed for MRSR (reset) register. 2798 * The command interface will return error after the command 2799 * is executed, so tell the lower layer to expect it 2800 * and cope accordingly. 2801 */ 2802 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2803 2804 n_retry = 0; 2805 retry: 2806 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2807 if (!err) { 2808 err = mlxsw_emad_process_status(out_mbox, &status); 2809 if (err) { 2810 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2811 goto retry; 2812 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2813 status, mlxsw_emad_op_tlv_status_str(status)); 2814 } 2815 } 2816 2817 if (!err) 2818 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2819 reg->len); 2820 2821 mlxsw_cmd_mbox_free(out_mbox); 2822 free_in_mbox: 2823 mlxsw_cmd_mbox_free(in_mbox); 2824 if (err) 2825 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2826 reg->id, mlxsw_reg_id_str(reg->id), 2827 mlxsw_core_reg_access_type_str(type)); 2828 return err; 2829 } 2830 2831 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2832 char *payload, size_t payload_len, 2833 unsigned long cb_priv) 2834 { 2835 char *orig_payload = (char *) cb_priv; 2836 2837 memcpy(orig_payload, payload, payload_len); 2838 } 2839 2840 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2841 const struct mlxsw_reg_info *reg, 2842 char *payload, 2843 enum mlxsw_core_reg_access_type type) 2844 { 2845 LIST_HEAD(bulk_list); 2846 int err; 2847 2848 /* During initialization EMAD interface is not available to us, 2849 * so we default to command interface. We switch to EMAD interface 2850 * after setting the appropriate traps. 2851 */ 2852 if (!mlxsw_core->emad.use_emad) 2853 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2854 payload, type); 2855 2856 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 2857 payload, type, &bulk_list, 2858 mlxsw_core_reg_access_cb, 2859 (unsigned long) payload); 2860 if (err) 2861 return err; 2862 return mlxsw_reg_trans_bulk_wait(&bulk_list); 2863 } 2864 2865 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 2866 const struct mlxsw_reg_info *reg, char *payload) 2867 { 2868 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2869 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 2870 } 2871 EXPORT_SYMBOL(mlxsw_reg_query); 2872 2873 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 2874 const struct mlxsw_reg_info *reg, char *payload) 2875 { 2876 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2877 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 2878 } 2879 EXPORT_SYMBOL(mlxsw_reg_write); 2880 2881 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2882 struct mlxsw_rx_info *rx_info) 2883 { 2884 struct mlxsw_rx_listener_item *rxl_item; 2885 const struct mlxsw_rx_listener *rxl; 2886 u16 local_port; 2887 bool found = false; 2888 2889 if (rx_info->is_lag) { 2890 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 2891 __func__, rx_info->u.lag_id, 2892 rx_info->trap_id); 2893 /* Upper layer does not care if the skb came from LAG or not, 2894 * so just get the local_port for the lag port and push it up. 2895 */ 2896 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 2897 rx_info->u.lag_id, 2898 rx_info->lag_port_index); 2899 } else { 2900 local_port = rx_info->u.sys_port; 2901 } 2902 2903 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 2904 __func__, local_port, rx_info->trap_id); 2905 2906 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 2907 (local_port >= mlxsw_core->max_ports)) 2908 goto drop; 2909 2910 rcu_read_lock(); 2911 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 2912 rxl = &rxl_item->rxl; 2913 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 2914 rxl->local_port == local_port) && 2915 rxl->trap_id == rx_info->trap_id && 2916 rxl->mirror_reason == rx_info->mirror_reason) { 2917 if (rxl_item->enabled) 2918 found = true; 2919 break; 2920 } 2921 } 2922 if (!found) { 2923 rcu_read_unlock(); 2924 goto drop; 2925 } 2926 2927 rxl->func(skb, local_port, rxl_item->priv); 2928 rcu_read_unlock(); 2929 return; 2930 2931 drop: 2932 dev_kfree_skb(skb); 2933 } 2934 EXPORT_SYMBOL(mlxsw_core_skb_receive); 2935 2936 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 2937 u16 lag_id, u8 port_index) 2938 { 2939 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 2940 port_index; 2941 } 2942 2943 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 2944 u16 lag_id, u8 port_index, u16 local_port) 2945 { 2946 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2947 lag_id, port_index); 2948 2949 mlxsw_core->lag.mapping[index] = local_port; 2950 } 2951 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 2952 2953 u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 2954 u16 lag_id, u8 port_index) 2955 { 2956 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2957 lag_id, port_index); 2958 2959 return mlxsw_core->lag.mapping[index]; 2960 } 2961 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 2962 2963 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 2964 u16 lag_id, u16 local_port) 2965 { 2966 int i; 2967 2968 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 2969 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2970 lag_id, i); 2971 2972 if (mlxsw_core->lag.mapping[index] == local_port) 2973 mlxsw_core->lag.mapping[index] = 0; 2974 } 2975 } 2976 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 2977 2978 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 2979 enum mlxsw_res_id res_id) 2980 { 2981 return mlxsw_res_valid(&mlxsw_core->res, res_id); 2982 } 2983 EXPORT_SYMBOL(mlxsw_core_res_valid); 2984 2985 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 2986 enum mlxsw_res_id res_id) 2987 { 2988 return mlxsw_res_get(&mlxsw_core->res, res_id); 2989 } 2990 EXPORT_SYMBOL(mlxsw_core_res_get); 2991 2992 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 2993 enum devlink_port_flavour flavour, 2994 u8 slot_index, u32 port_number, bool split, 2995 u32 split_port_subnumber, 2996 bool splittable, u32 lanes, 2997 const unsigned char *switch_id, 2998 unsigned char switch_id_len) 2999 { 3000 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3001 struct mlxsw_core_port *mlxsw_core_port = 3002 &mlxsw_core->ports[local_port]; 3003 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3004 struct devlink_port_attrs attrs = {}; 3005 int err; 3006 3007 attrs.split = split; 3008 attrs.lanes = lanes; 3009 attrs.splittable = splittable; 3010 attrs.flavour = flavour; 3011 attrs.phys.port_number = port_number; 3012 attrs.phys.split_subport_number = split_port_subnumber; 3013 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 3014 attrs.switch_id.id_len = switch_id_len; 3015 mlxsw_core_port->local_port = local_port; 3016 devlink_port_attrs_set(devlink_port, &attrs); 3017 if (slot_index) { 3018 struct mlxsw_linecard *linecard; 3019 3020 linecard = mlxsw_linecard_get(mlxsw_core->linecards, 3021 slot_index); 3022 mlxsw_core_port->linecard = linecard; 3023 devlink_port_linecard_set(devlink_port, 3024 linecard->devlink_linecard); 3025 } 3026 err = devl_port_register(devlink, devlink_port, local_port); 3027 if (err) 3028 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3029 return err; 3030 } 3031 3032 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3033 { 3034 struct mlxsw_core_port *mlxsw_core_port = 3035 &mlxsw_core->ports[local_port]; 3036 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3037 3038 devl_port_unregister(devlink_port); 3039 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3040 } 3041 3042 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3043 u8 slot_index, u32 port_number, bool split, 3044 u32 split_port_subnumber, 3045 bool splittable, u32 lanes, 3046 const unsigned char *switch_id, 3047 unsigned char switch_id_len) 3048 { 3049 int err; 3050 3051 err = __mlxsw_core_port_init(mlxsw_core, local_port, 3052 DEVLINK_PORT_FLAVOUR_PHYSICAL, slot_index, 3053 port_number, split, split_port_subnumber, 3054 splittable, lanes, 3055 switch_id, switch_id_len); 3056 if (err) 3057 return err; 3058 3059 atomic_inc(&mlxsw_core->active_ports_count); 3060 return 0; 3061 } 3062 EXPORT_SYMBOL(mlxsw_core_port_init); 3063 3064 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3065 { 3066 atomic_dec(&mlxsw_core->active_ports_count); 3067 3068 __mlxsw_core_port_fini(mlxsw_core, local_port); 3069 } 3070 EXPORT_SYMBOL(mlxsw_core_port_fini); 3071 3072 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 3073 void *port_driver_priv, 3074 const unsigned char *switch_id, 3075 unsigned char switch_id_len) 3076 { 3077 struct mlxsw_core_port *mlxsw_core_port = 3078 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 3079 int err; 3080 3081 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 3082 DEVLINK_PORT_FLAVOUR_CPU, 3083 0, 0, false, 0, false, 0, 3084 switch_id, switch_id_len); 3085 if (err) 3086 return err; 3087 3088 mlxsw_core_port->port_driver_priv = port_driver_priv; 3089 return 0; 3090 } 3091 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 3092 3093 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 3094 { 3095 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 3096 } 3097 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 3098 3099 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3100 void *port_driver_priv, struct net_device *dev) 3101 { 3102 struct mlxsw_core_port *mlxsw_core_port = 3103 &mlxsw_core->ports[local_port]; 3104 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3105 3106 mlxsw_core_port->port_driver_priv = port_driver_priv; 3107 devlink_port_type_eth_set(devlink_port, dev); 3108 } 3109 EXPORT_SYMBOL(mlxsw_core_port_eth_set); 3110 3111 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3112 void *port_driver_priv) 3113 { 3114 struct mlxsw_core_port *mlxsw_core_port = 3115 &mlxsw_core->ports[local_port]; 3116 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3117 3118 mlxsw_core_port->port_driver_priv = port_driver_priv; 3119 devlink_port_type_ib_set(devlink_port, NULL); 3120 } 3121 EXPORT_SYMBOL(mlxsw_core_port_ib_set); 3122 3123 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port, 3124 void *port_driver_priv) 3125 { 3126 struct mlxsw_core_port *mlxsw_core_port = 3127 &mlxsw_core->ports[local_port]; 3128 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3129 3130 mlxsw_core_port->port_driver_priv = port_driver_priv; 3131 devlink_port_type_clear(devlink_port); 3132 } 3133 EXPORT_SYMBOL(mlxsw_core_port_clear); 3134 3135 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 3136 u16 local_port) 3137 { 3138 struct mlxsw_core_port *mlxsw_core_port = 3139 &mlxsw_core->ports[local_port]; 3140 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3141 3142 return devlink_port->type; 3143 } 3144 EXPORT_SYMBOL(mlxsw_core_port_type_get); 3145 3146 3147 struct devlink_port * 3148 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 3149 u16 local_port) 3150 { 3151 struct mlxsw_core_port *mlxsw_core_port = 3152 &mlxsw_core->ports[local_port]; 3153 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3154 3155 return devlink_port; 3156 } 3157 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 3158 3159 struct mlxsw_linecard * 3160 mlxsw_core_port_linecard_get(struct mlxsw_core *mlxsw_core, 3161 u16 local_port) 3162 { 3163 struct mlxsw_core_port *mlxsw_core_port = 3164 &mlxsw_core->ports[local_port]; 3165 3166 return mlxsw_core_port->linecard; 3167 } 3168 3169 void mlxsw_core_ports_remove_selected(struct mlxsw_core *mlxsw_core, 3170 bool (*selector)(void *priv, u16 local_port), 3171 void *priv) 3172 { 3173 if (WARN_ON_ONCE(!mlxsw_core->driver->ports_remove_selected)) 3174 return; 3175 mlxsw_core->driver->ports_remove_selected(mlxsw_core, selector, priv); 3176 } 3177 3178 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 3179 { 3180 return mlxsw_core->env; 3181 } 3182 3183 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 3184 const char *buf, size_t size) 3185 { 3186 __be32 *m = (__be32 *) buf; 3187 int i; 3188 int count = size / sizeof(__be32); 3189 3190 for (i = count - 1; i >= 0; i--) 3191 if (m[i]) 3192 break; 3193 i++; 3194 count = i ? i : 1; 3195 for (i = 0; i < count; i += 4) 3196 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 3197 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 3198 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 3199 } 3200 3201 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 3202 u32 in_mod, bool out_mbox_direct, bool reset_ok, 3203 char *in_mbox, size_t in_mbox_size, 3204 char *out_mbox, size_t out_mbox_size) 3205 { 3206 u8 status; 3207 int err; 3208 3209 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 3210 if (!mlxsw_core->bus->cmd_exec) 3211 return -EOPNOTSUPP; 3212 3213 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3214 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 3215 if (in_mbox) { 3216 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 3217 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 3218 } 3219 3220 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 3221 opcode_mod, in_mod, out_mbox_direct, 3222 in_mbox, in_mbox_size, 3223 out_mbox, out_mbox_size, &status); 3224 3225 if (!err && out_mbox) { 3226 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 3227 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 3228 } 3229 3230 if (reset_ok && err == -EIO && 3231 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 3232 err = 0; 3233 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 3234 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 3235 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3236 in_mod, status, mlxsw_cmd_status_str(status)); 3237 } else if (err == -ETIMEDOUT) { 3238 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3239 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3240 in_mod); 3241 } 3242 3243 return err; 3244 } 3245 EXPORT_SYMBOL(mlxsw_cmd_exec); 3246 3247 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 3248 { 3249 return queue_delayed_work(mlxsw_wq, dwork, delay); 3250 } 3251 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 3252 3253 bool mlxsw_core_schedule_work(struct work_struct *work) 3254 { 3255 return queue_work(mlxsw_owq, work); 3256 } 3257 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3258 3259 void mlxsw_core_flush_owq(void) 3260 { 3261 flush_workqueue(mlxsw_owq); 3262 } 3263 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3264 3265 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3266 const struct mlxsw_config_profile *profile, 3267 u64 *p_single_size, u64 *p_double_size, 3268 u64 *p_linear_size) 3269 { 3270 struct mlxsw_driver *driver = mlxsw_core->driver; 3271 3272 if (!driver->kvd_sizes_get) 3273 return -EINVAL; 3274 3275 return driver->kvd_sizes_get(mlxsw_core, profile, 3276 p_single_size, p_double_size, 3277 p_linear_size); 3278 } 3279 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3280 3281 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3282 struct mlxsw_res *res) 3283 { 3284 int index, i; 3285 u64 data; 3286 u16 id; 3287 int err; 3288 3289 mlxsw_cmd_mbox_zero(mbox); 3290 3291 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3292 index++) { 3293 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3294 if (err) 3295 return err; 3296 3297 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3298 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3299 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3300 3301 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3302 return 0; 3303 3304 mlxsw_res_parse(res, id, data); 3305 } 3306 } 3307 3308 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3309 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3310 */ 3311 return -EIO; 3312 } 3313 EXPORT_SYMBOL(mlxsw_core_resources_query); 3314 3315 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3316 { 3317 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3318 } 3319 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3320 3321 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3322 { 3323 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3324 } 3325 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3326 3327 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core) 3328 { 3329 mlxsw_core->emad.enable_string_tlv = true; 3330 } 3331 EXPORT_SYMBOL(mlxsw_core_emad_string_tlv_enable); 3332 3333 static int __init mlxsw_core_module_init(void) 3334 { 3335 int err; 3336 3337 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3338 if (!mlxsw_wq) 3339 return -ENOMEM; 3340 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3341 mlxsw_core_driver_name); 3342 if (!mlxsw_owq) { 3343 err = -ENOMEM; 3344 goto err_alloc_ordered_workqueue; 3345 } 3346 return 0; 3347 3348 err_alloc_ordered_workqueue: 3349 destroy_workqueue(mlxsw_wq); 3350 return err; 3351 } 3352 3353 static void __exit mlxsw_core_module_exit(void) 3354 { 3355 destroy_workqueue(mlxsw_owq); 3356 destroy_workqueue(mlxsw_wq); 3357 } 3358 3359 module_init(mlxsw_core_module_init); 3360 module_exit(mlxsw_core_module_exit); 3361 3362 MODULE_LICENSE("Dual BSD/GPL"); 3363 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3364 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3365