1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/cmd.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the names of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _MLXSW_CMD_H 37 #define _MLXSW_CMD_H 38 39 #include "item.h" 40 41 #define MLXSW_CMD_MBOX_SIZE 4096 42 43 static inline char *mlxsw_cmd_mbox_alloc(void) 44 { 45 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 46 } 47 48 static inline void mlxsw_cmd_mbox_free(char *mbox) 49 { 50 kfree(mbox); 51 } 52 53 static inline void mlxsw_cmd_mbox_zero(char *mbox) 54 { 55 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 56 } 57 58 struct mlxsw_core; 59 60 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 61 u32 in_mod, bool out_mbox_direct, bool reset_ok, 62 char *in_mbox, size_t in_mbox_size, 63 char *out_mbox, size_t out_mbox_size); 64 65 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 66 u8 opcode_mod, u32 in_mod, char *in_mbox, 67 size_t in_mbox_size) 68 { 69 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 70 false, in_mbox, in_mbox_size, NULL, 0); 71 } 72 73 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 74 u8 opcode_mod, u32 in_mod, 75 bool out_mbox_direct, 76 char *out_mbox, size_t out_mbox_size) 77 { 78 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 79 out_mbox_direct, false, NULL, 0, 80 out_mbox, out_mbox_size); 81 } 82 83 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 84 u8 opcode_mod, u32 in_mod) 85 { 86 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 87 false, NULL, 0, NULL, 0); 88 } 89 90 enum mlxsw_cmd_opcode { 91 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 92 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 93 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 94 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 95 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 96 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 97 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 98 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 99 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 100 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 101 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 102 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 103 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 104 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 105 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 106 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 107 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 108 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, 109 }; 110 111 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 112 { 113 switch (opcode) { 114 case MLXSW_CMD_OPCODE_QUERY_FW: 115 return "QUERY_FW"; 116 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 117 return "QUERY_BOARDINFO"; 118 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 119 return "QUERY_AQ_CAP"; 120 case MLXSW_CMD_OPCODE_MAP_FA: 121 return "MAP_FA"; 122 case MLXSW_CMD_OPCODE_UNMAP_FA: 123 return "UNMAP_FA"; 124 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 125 return "CONFIG_PROFILE"; 126 case MLXSW_CMD_OPCODE_ACCESS_REG: 127 return "ACCESS_REG"; 128 case MLXSW_CMD_OPCODE_SW2HW_DQ: 129 return "SW2HW_DQ"; 130 case MLXSW_CMD_OPCODE_HW2SW_DQ: 131 return "HW2SW_DQ"; 132 case MLXSW_CMD_OPCODE_2ERR_DQ: 133 return "2ERR_DQ"; 134 case MLXSW_CMD_OPCODE_QUERY_DQ: 135 return "QUERY_DQ"; 136 case MLXSW_CMD_OPCODE_SW2HW_CQ: 137 return "SW2HW_CQ"; 138 case MLXSW_CMD_OPCODE_HW2SW_CQ: 139 return "HW2SW_CQ"; 140 case MLXSW_CMD_OPCODE_QUERY_CQ: 141 return "QUERY_CQ"; 142 case MLXSW_CMD_OPCODE_SW2HW_EQ: 143 return "SW2HW_EQ"; 144 case MLXSW_CMD_OPCODE_HW2SW_EQ: 145 return "HW2SW_EQ"; 146 case MLXSW_CMD_OPCODE_QUERY_EQ: 147 return "QUERY_EQ"; 148 case MLXSW_CMD_OPCODE_QUERY_RESOURCES: 149 return "QUERY_RESOURCES"; 150 default: 151 return "*UNKNOWN*"; 152 } 153 } 154 155 enum mlxsw_cmd_status { 156 /* Command execution succeeded. */ 157 MLXSW_CMD_STATUS_OK = 0x00, 158 /* Internal error (e.g. bus error) occurred while processing command. */ 159 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 160 /* Operation/command not supported or opcode modifier not supported. */ 161 MLXSW_CMD_STATUS_BAD_OP = 0x02, 162 /* Parameter not supported, parameter out of range. */ 163 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 164 /* System was not enabled or bad system state. */ 165 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 166 /* Attempt to access reserved or unallocated resource, or resource in 167 * inappropriate ownership. 168 */ 169 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 170 /* Requested resource is currently executing a command. */ 171 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 172 /* Required capability exceeds device limits. */ 173 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 174 /* Resource is not in the appropriate state or ownership. */ 175 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 176 /* Index out of range (might be beyond table size or attempt to 177 * access a reserved resource). 178 */ 179 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 180 /* NVMEM checksum/CRC failed. */ 181 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 182 /* Device is currently running reset */ 183 MLXSW_CMD_STATUS_RUNNING_RESET = 0x26, 184 /* Bad management packet (silently discarded). */ 185 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 186 }; 187 188 static inline const char *mlxsw_cmd_status_str(u8 status) 189 { 190 switch (status) { 191 case MLXSW_CMD_STATUS_OK: 192 return "OK"; 193 case MLXSW_CMD_STATUS_INTERNAL_ERR: 194 return "INTERNAL_ERR"; 195 case MLXSW_CMD_STATUS_BAD_OP: 196 return "BAD_OP"; 197 case MLXSW_CMD_STATUS_BAD_PARAM: 198 return "BAD_PARAM"; 199 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 200 return "BAD_SYS_STATE"; 201 case MLXSW_CMD_STATUS_BAD_RESOURCE: 202 return "BAD_RESOURCE"; 203 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 204 return "RESOURCE_BUSY"; 205 case MLXSW_CMD_STATUS_EXCEED_LIM: 206 return "EXCEED_LIM"; 207 case MLXSW_CMD_STATUS_BAD_RES_STATE: 208 return "BAD_RES_STATE"; 209 case MLXSW_CMD_STATUS_BAD_INDEX: 210 return "BAD_INDEX"; 211 case MLXSW_CMD_STATUS_BAD_NVMEM: 212 return "BAD_NVMEM"; 213 case MLXSW_CMD_STATUS_RUNNING_RESET: 214 return "RUNNING_RESET"; 215 case MLXSW_CMD_STATUS_BAD_PKT: 216 return "BAD_PKT"; 217 default: 218 return "*UNKNOWN*"; 219 } 220 } 221 222 /* QUERY_FW - Query Firmware 223 * ------------------------- 224 * OpMod == 0, INMmod == 0 225 * ----------------------- 226 * The QUERY_FW command retrieves information related to firmware, command 227 * interface version and the amount of resources that should be allocated to 228 * the firmware. 229 */ 230 231 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 232 char *out_mbox) 233 { 234 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 235 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 236 } 237 238 /* cmd_mbox_query_fw_fw_pages 239 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 240 */ 241 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 242 243 /* cmd_mbox_query_fw_fw_rev_major 244 * Firmware Revision - Major 245 */ 246 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 247 248 /* cmd_mbox_query_fw_fw_rev_subminor 249 * Firmware Sub-minor version (Patch level) 250 */ 251 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 252 253 /* cmd_mbox_query_fw_fw_rev_minor 254 * Firmware Revision - Minor 255 */ 256 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 257 258 /* cmd_mbox_query_fw_core_clk 259 * Internal Clock Frequency (in MHz) 260 */ 261 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 262 263 /* cmd_mbox_query_fw_cmd_interface_rev 264 * Command Interface Interpreter Revision ID. This number is bumped up 265 * every time a non-backward-compatible change is done for the command 266 * interface. The current cmd_interface_rev is 1. 267 */ 268 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 269 270 /* cmd_mbox_query_fw_dt 271 * If set, Debug Trace is supported 272 */ 273 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 274 275 /* cmd_mbox_query_fw_api_version 276 * Indicates the version of the API, to enable software querying 277 * for compatibility. The current api_version is 1. 278 */ 279 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 280 281 /* cmd_mbox_query_fw_fw_hour 282 * Firmware timestamp - hour 283 */ 284 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 285 286 /* cmd_mbox_query_fw_fw_minutes 287 * Firmware timestamp - minutes 288 */ 289 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 290 291 /* cmd_mbox_query_fw_fw_seconds 292 * Firmware timestamp - seconds 293 */ 294 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 295 296 /* cmd_mbox_query_fw_fw_year 297 * Firmware timestamp - year 298 */ 299 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 300 301 /* cmd_mbox_query_fw_fw_month 302 * Firmware timestamp - month 303 */ 304 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 305 306 /* cmd_mbox_query_fw_fw_day 307 * Firmware timestamp - day 308 */ 309 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 310 311 /* cmd_mbox_query_fw_clr_int_base_offset 312 * Clear Interrupt register's offset from clr_int_bar register 313 * in PCI address space. 314 */ 315 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 316 317 /* cmd_mbox_query_fw_clr_int_bar 318 * PCI base address register (BAR) where clr_int register is located. 319 * 00 - BAR 0-1 (64 bit BAR) 320 */ 321 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 322 323 /* cmd_mbox_query_fw_error_buf_offset 324 * Read Only buffer for internal error reports of offset 325 * from error_buf_bar register in PCI address space). 326 */ 327 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 328 329 /* cmd_mbox_query_fw_error_buf_size 330 * Internal error buffer size in DWORDs 331 */ 332 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 333 334 /* cmd_mbox_query_fw_error_int_bar 335 * PCI base address register (BAR) where error buffer 336 * register is located. 337 * 00 - BAR 0-1 (64 bit BAR) 338 */ 339 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 340 341 /* cmd_mbox_query_fw_doorbell_page_offset 342 * Offset of the doorbell page 343 */ 344 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 345 346 /* cmd_mbox_query_fw_doorbell_page_bar 347 * PCI base address register (BAR) of the doorbell page 348 * 00 - BAR 0-1 (64 bit BAR) 349 */ 350 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 351 352 /* QUERY_BOARDINFO - Query Board Information 353 * ----------------------------------------- 354 * OpMod == 0 (N/A), INMmod == 0 (N/A) 355 * ----------------------------------- 356 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 357 */ 358 359 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 360 char *out_mbox) 361 { 362 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 363 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 364 } 365 366 /* cmd_mbox_boardinfo_intapin 367 * When PCIe interrupt messages are being used, this value is used for clearing 368 * an interrupt. When using MSI-X, this register is not used. 369 */ 370 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 371 372 /* cmd_mbox_boardinfo_vsd_vendor_id 373 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 374 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 375 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 376 * format and encoding as long as they use their assigned vsd_vendor_id. 377 */ 378 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 379 380 /* cmd_mbox_boardinfo_vsd 381 * Vendor Specific Data. The VSD string that is burnt to the Flash 382 * with the firmware. 383 */ 384 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 385 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 386 387 /* cmd_mbox_boardinfo_psid 388 * The PSID field is a 16-ascii (byte) character string which acts as 389 * the board ID. The PSID format is used in conjunction with 390 * Mellanox vsd_vendor_id (15B3h). 391 */ 392 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 393 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 394 395 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 396 * ----------------------------------------------------- 397 * OpMod == 0 (N/A), INMmod == 0 (N/A) 398 * ----------------------------------- 399 * The QUERY_AQ_CAP command returns the device asynchronous queues 400 * capabilities supported. 401 */ 402 403 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 404 char *out_mbox) 405 { 406 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 407 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 408 } 409 410 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 411 * Log (base 2) of max WQEs allowed on SDQ. 412 */ 413 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 414 415 /* cmd_mbox_query_aq_cap_max_num_sdqs 416 * Maximum number of SDQs. 417 */ 418 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 419 420 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 421 * Log (base 2) of max WQEs allowed on RDQ. 422 */ 423 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 424 425 /* cmd_mbox_query_aq_cap_max_num_rdqs 426 * Maximum number of RDQs. 427 */ 428 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 429 430 /* cmd_mbox_query_aq_cap_log_max_cq_sz 431 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. 432 */ 433 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 434 435 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz 436 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. 437 */ 438 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); 439 440 /* cmd_mbox_query_aq_cap_max_num_cqs 441 * Maximum number of CQs. 442 */ 443 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 444 445 /* cmd_mbox_query_aq_cap_log_max_eq_sz 446 * Log (base 2) of max EQEs allowed on EQ. 447 */ 448 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 449 450 /* cmd_mbox_query_aq_cap_max_num_eqs 451 * Maximum number of EQs. 452 */ 453 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 454 455 /* cmd_mbox_query_aq_cap_max_sg_sq 456 * The maximum S/G list elements in an DSQ. DSQ must not contain 457 * more S/G entries than indicated here. 458 */ 459 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 460 461 /* cmd_mbox_query_aq_cap_ 462 * The maximum S/G list elements in an DRQ. DRQ must not contain 463 * more S/G entries than indicated here. 464 */ 465 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 466 467 /* MAP_FA - Map Firmware Area 468 * -------------------------- 469 * OpMod == 0 (N/A), INMmod == Number of VPM entries 470 * ------------------------------------------------- 471 * The MAP_FA command passes physical pages to the switch. These pages 472 * are used to store the device firmware. MAP_FA can be executed multiple 473 * times until all the firmware area is mapped (the size that should be 474 * mapped is retrieved through the QUERY_FW command). All required pages 475 * must be mapped to finish the initialization phase. Physical memory 476 * passed in this command must be pinned. 477 */ 478 479 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 480 481 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 482 char *in_mbox, u32 vpm_entries_count) 483 { 484 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 485 0, vpm_entries_count, 486 in_mbox, MLXSW_CMD_MBOX_SIZE); 487 } 488 489 /* cmd_mbox_map_fa_pa 490 * Physical Address. 491 */ 492 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 493 494 /* cmd_mbox_map_fa_log2size 495 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 496 * that starts at PA_L/H. 497 */ 498 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 499 500 /* UNMAP_FA - Unmap Firmware Area 501 * ------------------------------ 502 * OpMod == 0 (N/A), INMmod == 0 (N/A) 503 * ----------------------------------- 504 * The UNMAP_FA command unload the firmware and unmaps all the 505 * firmware area. After this command is completed the device will not access 506 * the pages that were mapped to the firmware area. After executing UNMAP_FA 507 * command, software reset must be done prior to execution of MAP_FW command. 508 */ 509 510 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 511 { 512 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 513 } 514 515 /* QUERY_RESOURCES - Query chip resources 516 * -------------------------------------- 517 * OpMod == 0 (N/A) , INMmod is index 518 * ---------------------------------- 519 * The QUERY_RESOURCES command retrieves information related to chip resources 520 * by resource ID. Every command returns 32 entries. INmod is being use as base. 521 * for example, index 1 will return entries 32-63. When the tables end and there 522 * are no more sources in the table, will return resource id 0xFFF to indicate 523 * it. 524 */ 525 526 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff 527 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 528 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 529 530 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, 531 char *out_mbox, int index) 532 { 533 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES, 534 0, index, false, out_mbox, 535 MLXSW_CMD_MBOX_SIZE); 536 } 537 538 /* cmd_mbox_query_resource_id 539 * The resource id. 0xFFFF indicates table's end. 540 */ 541 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); 542 543 /* cmd_mbox_query_resource_data 544 * The resource 545 */ 546 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, 547 0x00, 0, 40, 0x8, 0, false); 548 549 /* CONFIG_PROFILE (Set) - Configure Switch Profile 550 * ------------------------------ 551 * OpMod == 1 (Set), INMmod == 0 (N/A) 552 * ----------------------------------- 553 * The CONFIG_PROFILE command sets the switch profile. The command can be 554 * executed on the device only once at startup in order to allocate and 555 * configure all switch resources and prepare it for operational mode. 556 * It is not possible to change the device profile after the chip is 557 * in operational mode. 558 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 559 * state therefore it is required to perform software reset to the device 560 * following an unsuccessful completion of the command. It is required 561 * to perform software reset to the device to change an existing profile. 562 */ 563 564 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 565 char *in_mbox) 566 { 567 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 568 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 569 } 570 571 /* cmd_mbox_config_profile_set_max_vepa_channels 572 * Capability bit. Setting a bit to 1 configures the profile 573 * according to the mailbox contents. 574 */ 575 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 576 577 /* cmd_mbox_config_profile_set_max_lag 578 * Capability bit. Setting a bit to 1 configures the profile 579 * according to the mailbox contents. 580 */ 581 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 582 583 /* cmd_mbox_config_profile_set_max_port_per_lag 584 * Capability bit. Setting a bit to 1 configures the profile 585 * according to the mailbox contents. 586 */ 587 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 588 589 /* cmd_mbox_config_profile_set_max_mid 590 * Capability bit. Setting a bit to 1 configures the profile 591 * according to the mailbox contents. 592 */ 593 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 594 595 /* cmd_mbox_config_profile_set_max_pgt 596 * Capability bit. Setting a bit to 1 configures the profile 597 * according to the mailbox contents. 598 */ 599 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 600 601 /* cmd_mbox_config_profile_set_max_system_port 602 * Capability bit. Setting a bit to 1 configures the profile 603 * according to the mailbox contents. 604 */ 605 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 606 607 /* cmd_mbox_config_profile_set_max_vlan_groups 608 * Capability bit. Setting a bit to 1 configures the profile 609 * according to the mailbox contents. 610 */ 611 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 612 613 /* cmd_mbox_config_profile_set_max_regions 614 * Capability bit. Setting a bit to 1 configures the profile 615 * according to the mailbox contents. 616 */ 617 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 618 619 /* cmd_mbox_config_profile_set_flood_mode 620 * Capability bit. Setting a bit to 1 configures the profile 621 * according to the mailbox contents. 622 */ 623 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 624 625 /* cmd_mbox_config_profile_set_max_flood_tables 626 * Capability bit. Setting a bit to 1 configures the profile 627 * according to the mailbox contents. 628 */ 629 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 630 631 /* cmd_mbox_config_profile_set_max_ib_mc 632 * Capability bit. Setting a bit to 1 configures the profile 633 * according to the mailbox contents. 634 */ 635 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 636 637 /* cmd_mbox_config_profile_set_max_pkey 638 * Capability bit. Setting a bit to 1 configures the profile 639 * according to the mailbox contents. 640 */ 641 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 642 643 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 644 * Capability bit. Setting a bit to 1 configures the profile 645 * according to the mailbox contents. 646 */ 647 MLXSW_ITEM32(cmd_mbox, config_profile, 648 set_adaptive_routing_group_cap, 0x0C, 14, 1); 649 650 /* cmd_mbox_config_profile_set_ar_sec 651 * Capability bit. Setting a bit to 1 configures the profile 652 * according to the mailbox contents. 653 */ 654 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 655 656 /* cmd_mbox_config_set_kvd_linear_size 657 * Capability bit. Setting a bit to 1 configures the profile 658 * according to the mailbox contents. 659 */ 660 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); 661 662 /* cmd_mbox_config_set_kvd_hash_single_size 663 * Capability bit. Setting a bit to 1 configures the profile 664 * according to the mailbox contents. 665 */ 666 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); 667 668 /* cmd_mbox_config_set_kvd_hash_double_size 669 * Capability bit. Setting a bit to 1 configures the profile 670 * according to the mailbox contents. 671 */ 672 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 673 674 /* cmd_mbox_config_set_cqe_version 675 * Capability bit. Setting a bit to 1 configures the profile 676 * according to the mailbox contents. 677 */ 678 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); 679 680 /* cmd_mbox_config_profile_max_vepa_channels 681 * Maximum number of VEPA channels per port (0 through 16) 682 * 0 - multi-channel VEPA is disabled 683 */ 684 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 685 686 /* cmd_mbox_config_profile_max_lag 687 * Maximum number of LAG IDs requested. 688 */ 689 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 690 691 /* cmd_mbox_config_profile_max_port_per_lag 692 * Maximum number of ports per LAG requested. 693 */ 694 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 695 696 /* cmd_mbox_config_profile_max_mid 697 * Maximum Multicast IDs. 698 * Multicast IDs are allocated from 0 to max_mid-1 699 */ 700 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 701 702 /* cmd_mbox_config_profile_max_pgt 703 * Maximum records in the Port Group Table per Switch Partition. 704 * Port Group Table indexes are from 0 to max_pgt-1 705 */ 706 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 707 708 /* cmd_mbox_config_profile_max_system_port 709 * The maximum number of system ports that can be allocated. 710 */ 711 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 712 713 /* cmd_mbox_config_profile_max_vlan_groups 714 * Maximum number VLAN Groups for VLAN binding. 715 */ 716 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 717 718 /* cmd_mbox_config_profile_max_regions 719 * Maximum number of TCAM Regions. 720 */ 721 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 722 723 /* cmd_mbox_config_profile_max_flood_tables 724 * Maximum number of single-entry flooding tables. Different flooding tables 725 * can be associated with different packet types. 726 */ 727 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 728 729 /* cmd_mbox_config_profile_max_vid_flood_tables 730 * Maximum number of per-vid flooding tables. Flooding tables are associated 731 * to the different packet types for the different switch partitions. 732 * Table size is 4K entries covering all VID space. 733 */ 734 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 735 736 /* cmd_mbox_config_profile_flood_mode 737 * Flooding mode to use. 738 * 0-2 - Backward compatible modes for SwitchX devices. 739 * 3 - Mixed mode, where: 740 * max_flood_tables indicates the number of single-entry tables. 741 * max_vid_flood_tables indicates the number of per-VID tables. 742 * max_fid_offset_flood_tables indicates the number of FID-offset tables. 743 * max_fid_flood_tables indicates the number of per-FID tables. 744 */ 745 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2); 746 747 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 748 * Maximum number of FID-offset flooding tables. 749 */ 750 MLXSW_ITEM32(cmd_mbox, config_profile, 751 max_fid_offset_flood_tables, 0x34, 24, 4); 752 753 /* cmd_mbox_config_profile_fid_offset_flood_table_size 754 * The size (number of entries) of each FID-offset flood table. 755 */ 756 MLXSW_ITEM32(cmd_mbox, config_profile, 757 fid_offset_flood_table_size, 0x34, 0, 16); 758 759 /* cmd_mbox_config_profile_max_fid_flood_tables 760 * Maximum number of per-FID flooding tables. 761 * 762 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 763 * FID value 4K and higher. 764 */ 765 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 766 767 /* cmd_mbox_config_profile_fid_flood_table_size 768 * The size (number of entries) of each per-FID table. 769 */ 770 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 771 772 /* cmd_mbox_config_profile_max_ib_mc 773 * Maximum number of multicast FDB records for InfiniBand 774 * FDB (in 512 chunks) per InfiniBand switch partition. 775 */ 776 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 777 778 /* cmd_mbox_config_profile_max_pkey 779 * Maximum per port PKEY table size (for PKEY enforcement) 780 */ 781 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 782 783 /* cmd_mbox_config_profile_ar_sec 784 * Primary/secondary capability 785 * Describes the number of adaptive routing sub-groups 786 * 0 - disable primary/secondary (single group) 787 * 1 - enable primary/secondary (2 sub-groups) 788 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 789 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 790 */ 791 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 792 793 /* cmd_mbox_config_profile_adaptive_routing_group_cap 794 * Adaptive Routing Group Capability. Indicates the number of AR groups 795 * supported. Note that when Primary/secondary is enabled, each 796 * primary/secondary couple consumes 2 adaptive routing entries. 797 */ 798 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 799 800 /* cmd_mbox_config_profile_arn 801 * Adaptive Routing Notification Enable 802 * Not supported in SwitchX, SwitchX-2 803 */ 804 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 805 806 /* cmd_mbox_config_kvd_linear_size 807 * KVD Linear Size 808 * Valid for Spectrum only 809 * Allowed values are 128*N where N=0 or higher 810 */ 811 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); 812 813 /* cmd_mbox_config_kvd_hash_single_size 814 * KVD Hash single-entries size 815 * Valid for Spectrum only 816 * Allowed values are 128*N where N=0 or higher 817 * Must be greater or equal to cap_min_kvd_hash_single_size 818 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 819 */ 820 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); 821 822 /* cmd_mbox_config_kvd_hash_double_size 823 * KVD Hash double-entries size (units of single-size entries) 824 * Valid for Spectrum only 825 * Allowed values are 128*N where N=0 or higher 826 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size 827 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 828 */ 829 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); 830 831 /* cmd_mbox_config_profile_swid_config_mask 832 * Modify Switch Partition Configuration mask. When set, the configu- 833 * ration value for the Switch Partition are taken from the mailbox. 834 * When clear, the current configuration values are used. 835 * Bit 0 - set type 836 * Bit 1 - properties 837 * Other - reserved 838 */ 839 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 840 0x60, 24, 8, 0x08, 0x00, false); 841 842 /* cmd_mbox_config_profile_swid_config_type 843 * Switch Partition type. 844 * 0000 - disabled (Switch Partition does not exist) 845 * 0001 - InfiniBand 846 * 0010 - Ethernet 847 * 1000 - router port (SwitchX-2 only) 848 * Other - reserved 849 */ 850 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 851 0x60, 20, 4, 0x08, 0x00, false); 852 853 /* cmd_mbox_config_profile_swid_config_properties 854 * Switch Partition properties. 855 */ 856 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 857 0x60, 0, 8, 0x08, 0x00, false); 858 859 /* cmd_mbox_config_profile_cqe_version 860 * CQE version: 861 * 0: CQE version is 0 862 * 1: CQE version is either 1 or 2 863 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. 864 */ 865 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); 866 867 /* ACCESS_REG - Access EMAD Supported Register 868 * ---------------------------------- 869 * OpMod == 0 (N/A), INMmod == 0 (N/A) 870 * ------------------------------------- 871 * The ACCESS_REG command supports accessing device registers. This access 872 * is mainly used for bootstrapping. 873 */ 874 875 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 876 bool reset_ok, 877 char *in_mbox, char *out_mbox) 878 { 879 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 880 0, 0, false, reset_ok, 881 in_mbox, MLXSW_CMD_MBOX_SIZE, 882 out_mbox, MLXSW_CMD_MBOX_SIZE); 883 } 884 885 /* SW2HW_DQ - Software to Hardware DQ 886 * ---------------------------------- 887 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 888 * INMmod == DQ number 889 * ---------------------------------------------- 890 * The SW2HW_DQ command transitions a descriptor queue from software to 891 * hardware ownership. The command enables posting WQEs and ringing DoorBells 892 * on the descriptor queue. 893 */ 894 895 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 896 char *in_mbox, u32 dq_number, 897 u8 opcode_mod) 898 { 899 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 900 opcode_mod, dq_number, 901 in_mbox, MLXSW_CMD_MBOX_SIZE); 902 } 903 904 enum { 905 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 906 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 907 }; 908 909 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 910 char *in_mbox, u32 dq_number) 911 { 912 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 913 MLXSW_CMD_OPCODE_MOD_SDQ); 914 } 915 916 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 917 char *in_mbox, u32 dq_number) 918 { 919 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 920 MLXSW_CMD_OPCODE_MOD_RDQ); 921 } 922 923 /* cmd_mbox_sw2hw_dq_cq 924 * Number of the CQ that this Descriptor Queue reports completions to. 925 */ 926 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 927 928 /* cmd_mbox_sw2hw_dq_sdq_tclass 929 * SDQ: CPU Egress TClass 930 * RDQ: Reserved 931 */ 932 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 933 934 /* cmd_mbox_sw2hw_dq_log2_dq_sz 935 * Log (base 2) of the Descriptor Queue size in 4KB pages. 936 */ 937 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 938 939 /* cmd_mbox_sw2hw_dq_pa 940 * Physical Address. 941 */ 942 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 943 944 /* HW2SW_DQ - Hardware to Software DQ 945 * ---------------------------------- 946 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 947 * INMmod == DQ number 948 * ---------------------------------------------- 949 * The HW2SW_DQ command transitions a descriptor queue from hardware to 950 * software ownership. Incoming packets on the DQ are silently discarded, 951 * SW should not post descriptors on nonoperational DQs. 952 */ 953 954 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 955 u32 dq_number, u8 opcode_mod) 956 { 957 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 958 opcode_mod, dq_number); 959 } 960 961 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 962 u32 dq_number) 963 { 964 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 965 MLXSW_CMD_OPCODE_MOD_SDQ); 966 } 967 968 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 969 u32 dq_number) 970 { 971 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 972 MLXSW_CMD_OPCODE_MOD_RDQ); 973 } 974 975 /* 2ERR_DQ - To Error DQ 976 * --------------------- 977 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 978 * INMmod == DQ number 979 * ---------------------------------------------- 980 * The 2ERR_DQ command transitions the DQ into the error state from the state 981 * in which it has been. While the command is executed, some in-process 982 * descriptors may complete. Once the DQ transitions into the error state, 983 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 984 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 985 * When the command is completed successfully, the DQ is already in 986 * the error state. 987 */ 988 989 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 990 u32 dq_number, u8 opcode_mod) 991 { 992 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 993 opcode_mod, dq_number); 994 } 995 996 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 997 u32 dq_number) 998 { 999 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1000 MLXSW_CMD_OPCODE_MOD_SDQ); 1001 } 1002 1003 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 1004 u32 dq_number) 1005 { 1006 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1007 MLXSW_CMD_OPCODE_MOD_RDQ); 1008 } 1009 1010 /* QUERY_DQ - Query DQ 1011 * --------------------- 1012 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1013 * INMmod == DQ number 1014 * ---------------------------------------------- 1015 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 1016 * 1017 * Note: Output mailbox has the same format as SW2HW_DQ. 1018 */ 1019 1020 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 1021 char *out_mbox, u32 dq_number, 1022 u8 opcode_mod) 1023 { 1024 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1025 opcode_mod, dq_number, false, 1026 out_mbox, MLXSW_CMD_MBOX_SIZE); 1027 } 1028 1029 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 1030 char *out_mbox, u32 dq_number) 1031 { 1032 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1033 MLXSW_CMD_OPCODE_MOD_SDQ); 1034 } 1035 1036 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 1037 char *out_mbox, u32 dq_number) 1038 { 1039 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1040 MLXSW_CMD_OPCODE_MOD_RDQ); 1041 } 1042 1043 /* SW2HW_CQ - Software to Hardware CQ 1044 * ---------------------------------- 1045 * OpMod == 0 (N/A), INMmod == CQ number 1046 * ------------------------------------- 1047 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 1048 * to hardware. The command takes the CQ context entry from the input mailbox 1049 * and stores it in the CQC in the ownership of the hardware. The command fails 1050 * if the requested CQC entry is already in the ownership of the hardware. 1051 */ 1052 1053 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 1054 char *in_mbox, u32 cq_number) 1055 { 1056 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 1057 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1058 } 1059 1060 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { 1061 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, 1062 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, 1063 }; 1064 1065 /* cmd_mbox_sw2hw_cq_cqe_ver 1066 * CQE Version. 1067 */ 1068 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); 1069 1070 /* cmd_mbox_sw2hw_cq_c_eqn 1071 * Event Queue this CQ reports completion events to. 1072 */ 1073 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 1074 1075 /* cmd_mbox_sw2hw_cq_st 1076 * Event delivery state machine 1077 * 0x0 - FIRED 1078 * 0x1 - ARMED (Request for Notification) 1079 */ 1080 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 1081 1082 /* cmd_mbox_sw2hw_cq_log_cq_size 1083 * Log (base 2) of the CQ size (in entries). 1084 */ 1085 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 1086 1087 /* cmd_mbox_sw2hw_cq_producer_counter 1088 * Producer Counter. The counter is incremented for each CQE that is 1089 * written by the HW to the CQ. 1090 * Maintained by HW (valid for the QUERY_CQ command only) 1091 */ 1092 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 1093 1094 /* cmd_mbox_sw2hw_cq_pa 1095 * Physical Address. 1096 */ 1097 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1098 1099 /* HW2SW_CQ - Hardware to Software CQ 1100 * ---------------------------------- 1101 * OpMod == 0 (N/A), INMmod == CQ number 1102 * ------------------------------------- 1103 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1104 * to software. The CQC entry is invalidated as a result of this command. 1105 */ 1106 1107 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1108 u32 cq_number) 1109 { 1110 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1111 0, cq_number); 1112 } 1113 1114 /* QUERY_CQ - Query CQ 1115 * ---------------------------------- 1116 * OpMod == 0 (N/A), INMmod == CQ number 1117 * ------------------------------------- 1118 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1119 * The command stores the snapshot in the output mailbox in the software format. 1120 * Note that the CQ context state and values are not affected by the QUERY_CQ 1121 * command. The QUERY_CQ command is for debug purposes only. 1122 * 1123 * Note: Output mailbox has the same format as SW2HW_CQ. 1124 */ 1125 1126 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1127 char *out_mbox, u32 cq_number) 1128 { 1129 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1130 0, cq_number, false, 1131 out_mbox, MLXSW_CMD_MBOX_SIZE); 1132 } 1133 1134 /* SW2HW_EQ - Software to Hardware EQ 1135 * ---------------------------------- 1136 * OpMod == 0 (N/A), INMmod == EQ number 1137 * ------------------------------------- 1138 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1139 * to hardware. The command takes the EQ context entry from the input mailbox 1140 * and stores it in the EQC in the ownership of the hardware. The command fails 1141 * if the requested EQC entry is already in the ownership of the hardware. 1142 */ 1143 1144 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1145 char *in_mbox, u32 eq_number) 1146 { 1147 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1148 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1149 } 1150 1151 /* cmd_mbox_sw2hw_eq_int_msix 1152 * When set, MSI-X cycles will be generated by this EQ. 1153 * When cleared, an interrupt will be generated by this EQ. 1154 */ 1155 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1156 1157 /* cmd_mbox_sw2hw_eq_st 1158 * Event delivery state machine 1159 * 0x0 - FIRED 1160 * 0x1 - ARMED (Request for Notification) 1161 * 0x11 - Always ARMED 1162 * other - reserved 1163 */ 1164 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1165 1166 /* cmd_mbox_sw2hw_eq_log_eq_size 1167 * Log (base 2) of the EQ size (in entries). 1168 */ 1169 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1170 1171 /* cmd_mbox_sw2hw_eq_producer_counter 1172 * Producer Counter. The counter is incremented for each EQE that is written 1173 * by the HW to the EQ. 1174 * Maintained by HW (valid for the QUERY_EQ command only) 1175 */ 1176 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1177 1178 /* cmd_mbox_sw2hw_eq_pa 1179 * Physical Address. 1180 */ 1181 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1182 1183 /* HW2SW_EQ - Hardware to Software EQ 1184 * ---------------------------------- 1185 * OpMod == 0 (N/A), INMmod == EQ number 1186 * ------------------------------------- 1187 */ 1188 1189 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1190 u32 eq_number) 1191 { 1192 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1193 0, eq_number); 1194 } 1195 1196 /* QUERY_EQ - Query EQ 1197 * ---------------------------------- 1198 * OpMod == 0 (N/A), INMmod == EQ number 1199 * ------------------------------------- 1200 * 1201 * Note: Output mailbox has the same format as SW2HW_EQ. 1202 */ 1203 1204 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1205 char *out_mbox, u32 eq_number) 1206 { 1207 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1208 0, eq_number, false, 1209 out_mbox, MLXSW_CMD_MBOX_SIZE); 1210 } 1211 1212 #endif 1213