1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_CMD_H 5 #define _MLXSW_CMD_H 6 7 #include "item.h" 8 9 #define MLXSW_CMD_MBOX_SIZE 4096 10 11 static inline char *mlxsw_cmd_mbox_alloc(void) 12 { 13 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 14 } 15 16 static inline void mlxsw_cmd_mbox_free(char *mbox) 17 { 18 kfree(mbox); 19 } 20 21 static inline void mlxsw_cmd_mbox_zero(char *mbox) 22 { 23 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 24 } 25 26 struct mlxsw_core; 27 28 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 29 u32 in_mod, bool out_mbox_direct, bool reset_ok, 30 char *in_mbox, size_t in_mbox_size, 31 char *out_mbox, size_t out_mbox_size); 32 33 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 34 u8 opcode_mod, u32 in_mod, char *in_mbox, 35 size_t in_mbox_size) 36 { 37 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 38 false, in_mbox, in_mbox_size, NULL, 0); 39 } 40 41 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 42 u8 opcode_mod, u32 in_mod, 43 bool out_mbox_direct, 44 char *out_mbox, size_t out_mbox_size) 45 { 46 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 47 out_mbox_direct, false, NULL, 0, 48 out_mbox, out_mbox_size); 49 } 50 51 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 52 u8 opcode_mod, u32 in_mod) 53 { 54 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 55 false, NULL, 0, NULL, 0); 56 } 57 58 enum mlxsw_cmd_opcode { 59 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 60 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 61 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 62 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 63 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 64 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 65 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 66 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 67 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 68 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 69 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 70 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 71 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 72 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 73 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 74 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 75 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 76 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, 77 }; 78 79 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 80 { 81 switch (opcode) { 82 case MLXSW_CMD_OPCODE_QUERY_FW: 83 return "QUERY_FW"; 84 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 85 return "QUERY_BOARDINFO"; 86 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 87 return "QUERY_AQ_CAP"; 88 case MLXSW_CMD_OPCODE_MAP_FA: 89 return "MAP_FA"; 90 case MLXSW_CMD_OPCODE_UNMAP_FA: 91 return "UNMAP_FA"; 92 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 93 return "CONFIG_PROFILE"; 94 case MLXSW_CMD_OPCODE_ACCESS_REG: 95 return "ACCESS_REG"; 96 case MLXSW_CMD_OPCODE_SW2HW_DQ: 97 return "SW2HW_DQ"; 98 case MLXSW_CMD_OPCODE_HW2SW_DQ: 99 return "HW2SW_DQ"; 100 case MLXSW_CMD_OPCODE_2ERR_DQ: 101 return "2ERR_DQ"; 102 case MLXSW_CMD_OPCODE_QUERY_DQ: 103 return "QUERY_DQ"; 104 case MLXSW_CMD_OPCODE_SW2HW_CQ: 105 return "SW2HW_CQ"; 106 case MLXSW_CMD_OPCODE_HW2SW_CQ: 107 return "HW2SW_CQ"; 108 case MLXSW_CMD_OPCODE_QUERY_CQ: 109 return "QUERY_CQ"; 110 case MLXSW_CMD_OPCODE_SW2HW_EQ: 111 return "SW2HW_EQ"; 112 case MLXSW_CMD_OPCODE_HW2SW_EQ: 113 return "HW2SW_EQ"; 114 case MLXSW_CMD_OPCODE_QUERY_EQ: 115 return "QUERY_EQ"; 116 case MLXSW_CMD_OPCODE_QUERY_RESOURCES: 117 return "QUERY_RESOURCES"; 118 default: 119 return "*UNKNOWN*"; 120 } 121 } 122 123 enum mlxsw_cmd_status { 124 /* Command execution succeeded. */ 125 MLXSW_CMD_STATUS_OK = 0x00, 126 /* Internal error (e.g. bus error) occurred while processing command. */ 127 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 128 /* Operation/command not supported or opcode modifier not supported. */ 129 MLXSW_CMD_STATUS_BAD_OP = 0x02, 130 /* Parameter not supported, parameter out of range. */ 131 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 132 /* System was not enabled or bad system state. */ 133 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 134 /* Attempt to access reserved or unallocated resource, or resource in 135 * inappropriate ownership. 136 */ 137 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 138 /* Requested resource is currently executing a command. */ 139 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 140 /* Required capability exceeds device limits. */ 141 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 142 /* Resource is not in the appropriate state or ownership. */ 143 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 144 /* Index out of range (might be beyond table size or attempt to 145 * access a reserved resource). 146 */ 147 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 148 /* NVMEM checksum/CRC failed. */ 149 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 150 /* Device is currently running reset */ 151 MLXSW_CMD_STATUS_RUNNING_RESET = 0x26, 152 /* Bad management packet (silently discarded). */ 153 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 154 }; 155 156 static inline const char *mlxsw_cmd_status_str(u8 status) 157 { 158 switch (status) { 159 case MLXSW_CMD_STATUS_OK: 160 return "OK"; 161 case MLXSW_CMD_STATUS_INTERNAL_ERR: 162 return "INTERNAL_ERR"; 163 case MLXSW_CMD_STATUS_BAD_OP: 164 return "BAD_OP"; 165 case MLXSW_CMD_STATUS_BAD_PARAM: 166 return "BAD_PARAM"; 167 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 168 return "BAD_SYS_STATE"; 169 case MLXSW_CMD_STATUS_BAD_RESOURCE: 170 return "BAD_RESOURCE"; 171 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 172 return "RESOURCE_BUSY"; 173 case MLXSW_CMD_STATUS_EXCEED_LIM: 174 return "EXCEED_LIM"; 175 case MLXSW_CMD_STATUS_BAD_RES_STATE: 176 return "BAD_RES_STATE"; 177 case MLXSW_CMD_STATUS_BAD_INDEX: 178 return "BAD_INDEX"; 179 case MLXSW_CMD_STATUS_BAD_NVMEM: 180 return "BAD_NVMEM"; 181 case MLXSW_CMD_STATUS_RUNNING_RESET: 182 return "RUNNING_RESET"; 183 case MLXSW_CMD_STATUS_BAD_PKT: 184 return "BAD_PKT"; 185 default: 186 return "*UNKNOWN*"; 187 } 188 } 189 190 /* QUERY_FW - Query Firmware 191 * ------------------------- 192 * OpMod == 0, INMmod == 0 193 * ----------------------- 194 * The QUERY_FW command retrieves information related to firmware, command 195 * interface version and the amount of resources that should be allocated to 196 * the firmware. 197 */ 198 199 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 200 char *out_mbox) 201 { 202 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 203 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 204 } 205 206 /* cmd_mbox_query_fw_fw_pages 207 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 208 */ 209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 210 211 /* cmd_mbox_query_fw_fw_rev_major 212 * Firmware Revision - Major 213 */ 214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 215 216 /* cmd_mbox_query_fw_fw_rev_subminor 217 * Firmware Sub-minor version (Patch level) 218 */ 219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 220 221 /* cmd_mbox_query_fw_fw_rev_minor 222 * Firmware Revision - Minor 223 */ 224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 225 226 /* cmd_mbox_query_fw_core_clk 227 * Internal Clock Frequency (in MHz) 228 */ 229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 230 231 /* cmd_mbox_query_fw_cmd_interface_rev 232 * Command Interface Interpreter Revision ID. This number is bumped up 233 * every time a non-backward-compatible change is done for the command 234 * interface. The current cmd_interface_rev is 1. 235 */ 236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 237 238 /* cmd_mbox_query_fw_dt 239 * If set, Debug Trace is supported 240 */ 241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 242 243 /* cmd_mbox_query_fw_api_version 244 * Indicates the version of the API, to enable software querying 245 * for compatibility. The current api_version is 1. 246 */ 247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 248 249 /* cmd_mbox_query_fw_fw_hour 250 * Firmware timestamp - hour 251 */ 252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 253 254 /* cmd_mbox_query_fw_fw_minutes 255 * Firmware timestamp - minutes 256 */ 257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 258 259 /* cmd_mbox_query_fw_fw_seconds 260 * Firmware timestamp - seconds 261 */ 262 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 263 264 /* cmd_mbox_query_fw_fw_year 265 * Firmware timestamp - year 266 */ 267 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 268 269 /* cmd_mbox_query_fw_fw_month 270 * Firmware timestamp - month 271 */ 272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 273 274 /* cmd_mbox_query_fw_fw_day 275 * Firmware timestamp - day 276 */ 277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 278 279 /* cmd_mbox_query_fw_clr_int_base_offset 280 * Clear Interrupt register's offset from clr_int_bar register 281 * in PCI address space. 282 */ 283 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 284 285 /* cmd_mbox_query_fw_clr_int_bar 286 * PCI base address register (BAR) where clr_int register is located. 287 * 00 - BAR 0-1 (64 bit BAR) 288 */ 289 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 290 291 /* cmd_mbox_query_fw_error_buf_offset 292 * Read Only buffer for internal error reports of offset 293 * from error_buf_bar register in PCI address space). 294 */ 295 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 296 297 /* cmd_mbox_query_fw_error_buf_size 298 * Internal error buffer size in DWORDs 299 */ 300 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 301 302 /* cmd_mbox_query_fw_error_int_bar 303 * PCI base address register (BAR) where error buffer 304 * register is located. 305 * 00 - BAR 0-1 (64 bit BAR) 306 */ 307 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 308 309 /* cmd_mbox_query_fw_doorbell_page_offset 310 * Offset of the doorbell page 311 */ 312 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 313 314 /* cmd_mbox_query_fw_doorbell_page_bar 315 * PCI base address register (BAR) of the doorbell page 316 * 00 - BAR 0-1 (64 bit BAR) 317 */ 318 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 319 320 /* cmd_mbox_query_fw_free_running_clock_offset 321 * The offset of the free running clock page 322 */ 323 MLXSW_ITEM64(cmd_mbox, query_fw, free_running_clock_offset, 0x50, 0, 64); 324 325 /* cmd_mbox_query_fw_fr_rn_clk_bar 326 * PCI base address register (BAR) of the free running clock page 327 * 0: BAR 0 328 * 1: 64 bit BAR 329 */ 330 MLXSW_ITEM32(cmd_mbox, query_fw, fr_rn_clk_bar, 0x58, 30, 2); 331 332 /* cmd_mbox_query_fw_utc_sec_offset 333 * The offset of the UTC_Sec page 334 */ 335 MLXSW_ITEM64(cmd_mbox, query_fw, utc_sec_offset, 0x70, 0, 64); 336 337 /* cmd_mbox_query_fw_utc_sec_bar 338 * PCI base address register (BAR) of the UTC_Sec page 339 * 0: BAR 0 340 * 1: 64 bit BAR 341 * Reserved on SwitchX/-2, Switch-IB/2, Spectrum-1 342 */ 343 MLXSW_ITEM32(cmd_mbox, query_fw, utc_sec_bar, 0x78, 30, 2); 344 345 /* cmd_mbox_query_fw_utc_nsec_offset 346 * The offset of the UTC_nSec page 347 */ 348 MLXSW_ITEM64(cmd_mbox, query_fw, utc_nsec_offset, 0x80, 0, 64); 349 350 /* cmd_mbox_query_fw_utc_nsec_bar 351 * PCI base address register (BAR) of the UTC_nSec page 352 * 0: BAR 0 353 * 1: 64 bit BAR 354 * Reserved on SwitchX/-2, Switch-IB/2, Spectrum-1 355 */ 356 MLXSW_ITEM32(cmd_mbox, query_fw, utc_nsec_bar, 0x88, 30, 2); 357 358 /* QUERY_BOARDINFO - Query Board Information 359 * ----------------------------------------- 360 * OpMod == 0 (N/A), INMmod == 0 (N/A) 361 * ----------------------------------- 362 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 363 */ 364 365 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 366 char *out_mbox) 367 { 368 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 369 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 370 } 371 372 /* cmd_mbox_boardinfo_intapin 373 * When PCIe interrupt messages are being used, this value is used for clearing 374 * an interrupt. When using MSI-X, this register is not used. 375 */ 376 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 377 378 /* cmd_mbox_boardinfo_vsd_vendor_id 379 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 380 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 381 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 382 * format and encoding as long as they use their assigned vsd_vendor_id. 383 */ 384 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 385 386 /* cmd_mbox_boardinfo_vsd 387 * Vendor Specific Data. The VSD string that is burnt to the Flash 388 * with the firmware. 389 */ 390 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 391 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 392 393 /* cmd_mbox_boardinfo_psid 394 * The PSID field is a 16-ascii (byte) character string which acts as 395 * the board ID. The PSID format is used in conjunction with 396 * Mellanox vsd_vendor_id (15B3h). 397 */ 398 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 399 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 400 401 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 402 * ----------------------------------------------------- 403 * OpMod == 0 (N/A), INMmod == 0 (N/A) 404 * ----------------------------------- 405 * The QUERY_AQ_CAP command returns the device asynchronous queues 406 * capabilities supported. 407 */ 408 409 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 410 char *out_mbox) 411 { 412 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 413 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 414 } 415 416 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 417 * Log (base 2) of max WQEs allowed on SDQ. 418 */ 419 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 420 421 /* cmd_mbox_query_aq_cap_max_num_sdqs 422 * Maximum number of SDQs. 423 */ 424 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 425 426 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 427 * Log (base 2) of max WQEs allowed on RDQ. 428 */ 429 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 430 431 /* cmd_mbox_query_aq_cap_max_num_rdqs 432 * Maximum number of RDQs. 433 */ 434 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 435 436 /* cmd_mbox_query_aq_cap_log_max_cq_sz 437 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. 438 */ 439 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 440 441 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz 442 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. 443 */ 444 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); 445 446 /* cmd_mbox_query_aq_cap_max_num_cqs 447 * Maximum number of CQs. 448 */ 449 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 450 451 /* cmd_mbox_query_aq_cap_log_max_eq_sz 452 * Log (base 2) of max EQEs allowed on EQ. 453 */ 454 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 455 456 /* cmd_mbox_query_aq_cap_max_num_eqs 457 * Maximum number of EQs. 458 */ 459 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 460 461 /* cmd_mbox_query_aq_cap_max_sg_sq 462 * The maximum S/G list elements in an DSQ. DSQ must not contain 463 * more S/G entries than indicated here. 464 */ 465 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 466 467 /* cmd_mbox_query_aq_cap_ 468 * The maximum S/G list elements in an DRQ. DRQ must not contain 469 * more S/G entries than indicated here. 470 */ 471 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 472 473 /* MAP_FA - Map Firmware Area 474 * -------------------------- 475 * OpMod == 0 (N/A), INMmod == Number of VPM entries 476 * ------------------------------------------------- 477 * The MAP_FA command passes physical pages to the switch. These pages 478 * are used to store the device firmware. MAP_FA can be executed multiple 479 * times until all the firmware area is mapped (the size that should be 480 * mapped is retrieved through the QUERY_FW command). All required pages 481 * must be mapped to finish the initialization phase. Physical memory 482 * passed in this command must be pinned. 483 */ 484 485 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 486 487 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 488 char *in_mbox, u32 vpm_entries_count) 489 { 490 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 491 0, vpm_entries_count, 492 in_mbox, MLXSW_CMD_MBOX_SIZE); 493 } 494 495 /* cmd_mbox_map_fa_pa 496 * Physical Address. 497 */ 498 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 499 500 /* cmd_mbox_map_fa_log2size 501 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 502 * that starts at PA_L/H. 503 */ 504 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 505 506 /* UNMAP_FA - Unmap Firmware Area 507 * ------------------------------ 508 * OpMod == 0 (N/A), INMmod == 0 (N/A) 509 * ----------------------------------- 510 * The UNMAP_FA command unload the firmware and unmaps all the 511 * firmware area. After this command is completed the device will not access 512 * the pages that were mapped to the firmware area. After executing UNMAP_FA 513 * command, software reset must be done prior to execution of MAP_FW command. 514 */ 515 516 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 517 { 518 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 519 } 520 521 /* QUERY_RESOURCES - Query chip resources 522 * -------------------------------------- 523 * OpMod == 0 (N/A) , INMmod is index 524 * ---------------------------------- 525 * The QUERY_RESOURCES command retrieves information related to chip resources 526 * by resource ID. Every command returns 32 entries. INmod is being use as base. 527 * for example, index 1 will return entries 32-63. When the tables end and there 528 * are no more sources in the table, will return resource id 0xFFF to indicate 529 * it. 530 */ 531 532 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff 533 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 534 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 535 536 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, 537 char *out_mbox, int index) 538 { 539 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES, 540 0, index, false, out_mbox, 541 MLXSW_CMD_MBOX_SIZE); 542 } 543 544 /* cmd_mbox_query_resource_id 545 * The resource id. 0xFFFF indicates table's end. 546 */ 547 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); 548 549 /* cmd_mbox_query_resource_data 550 * The resource 551 */ 552 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, 553 0x00, 0, 40, 0x8, 0, false); 554 555 /* CONFIG_PROFILE (Set) - Configure Switch Profile 556 * ------------------------------ 557 * OpMod == 1 (Set), INMmod == 0 (N/A) 558 * ----------------------------------- 559 * The CONFIG_PROFILE command sets the switch profile. The command can be 560 * executed on the device only once at startup in order to allocate and 561 * configure all switch resources and prepare it for operational mode. 562 * It is not possible to change the device profile after the chip is 563 * in operational mode. 564 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 565 * state therefore it is required to perform software reset to the device 566 * following an unsuccessful completion of the command. It is required 567 * to perform software reset to the device to change an existing profile. 568 */ 569 570 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 571 char *in_mbox) 572 { 573 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 574 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 575 } 576 577 /* cmd_mbox_config_profile_set_max_vepa_channels 578 * Capability bit. Setting a bit to 1 configures the profile 579 * according to the mailbox contents. 580 */ 581 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 582 583 /* cmd_mbox_config_profile_set_max_lag 584 * Capability bit. Setting a bit to 1 configures the profile 585 * according to the mailbox contents. 586 */ 587 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 588 589 /* cmd_mbox_config_profile_set_max_port_per_lag 590 * Capability bit. Setting a bit to 1 configures the profile 591 * according to the mailbox contents. 592 */ 593 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 594 595 /* cmd_mbox_config_profile_set_max_mid 596 * Capability bit. Setting a bit to 1 configures the profile 597 * according to the mailbox contents. 598 */ 599 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 600 601 /* cmd_mbox_config_profile_set_max_pgt 602 * Capability bit. Setting a bit to 1 configures the profile 603 * according to the mailbox contents. 604 */ 605 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 606 607 /* cmd_mbox_config_profile_set_max_system_port 608 * Capability bit. Setting a bit to 1 configures the profile 609 * according to the mailbox contents. 610 */ 611 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 612 613 /* cmd_mbox_config_profile_set_max_vlan_groups 614 * Capability bit. Setting a bit to 1 configures the profile 615 * according to the mailbox contents. 616 */ 617 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 618 619 /* cmd_mbox_config_profile_set_max_regions 620 * Capability bit. Setting a bit to 1 configures the profile 621 * according to the mailbox contents. 622 */ 623 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 624 625 /* cmd_mbox_config_profile_set_flood_mode 626 * Capability bit. Setting a bit to 1 configures the profile 627 * according to the mailbox contents. 628 */ 629 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 630 631 /* cmd_mbox_config_profile_set_max_flood_tables 632 * Capability bit. Setting a bit to 1 configures the profile 633 * according to the mailbox contents. 634 */ 635 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 636 637 /* cmd_mbox_config_profile_set_max_ib_mc 638 * Capability bit. Setting a bit to 1 configures the profile 639 * according to the mailbox contents. 640 */ 641 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 642 643 /* cmd_mbox_config_profile_set_max_pkey 644 * Capability bit. Setting a bit to 1 configures the profile 645 * according to the mailbox contents. 646 */ 647 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 648 649 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 650 * Capability bit. Setting a bit to 1 configures the profile 651 * according to the mailbox contents. 652 */ 653 MLXSW_ITEM32(cmd_mbox, config_profile, 654 set_adaptive_routing_group_cap, 0x0C, 14, 1); 655 656 /* cmd_mbox_config_profile_set_ar_sec 657 * Capability bit. Setting a bit to 1 configures the profile 658 * according to the mailbox contents. 659 */ 660 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 661 662 /* cmd_mbox_config_set_ubridge 663 * Capability bit. Setting a bit to 1 configures the profile 664 * according to the mailbox contents. 665 */ 666 MLXSW_ITEM32(cmd_mbox, config_profile, set_ubridge, 0x0C, 22, 1); 667 668 /* cmd_mbox_config_set_kvd_linear_size 669 * Capability bit. Setting a bit to 1 configures the profile 670 * according to the mailbox contents. 671 */ 672 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); 673 674 /* cmd_mbox_config_set_kvd_hash_single_size 675 * Capability bit. Setting a bit to 1 configures the profile 676 * according to the mailbox contents. 677 */ 678 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); 679 680 /* cmd_mbox_config_set_kvd_hash_double_size 681 * Capability bit. Setting a bit to 1 configures the profile 682 * according to the mailbox contents. 683 */ 684 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 685 686 /* cmd_mbox_config_set_cqe_version 687 * Capability bit. Setting a bit to 1 configures the profile 688 * according to the mailbox contents. 689 */ 690 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); 691 692 /* cmd_mbox_config_set_cqe_time_stamp_type 693 * Capability bit. Setting a bit to 1 configures the profile 694 * according to the mailbox contents. 695 */ 696 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_time_stamp_type, 0x08, 2, 1); 697 698 /* cmd_mbox_config_profile_max_vepa_channels 699 * Maximum number of VEPA channels per port (0 through 16) 700 * 0 - multi-channel VEPA is disabled 701 */ 702 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 703 704 /* cmd_mbox_config_profile_max_lag 705 * Maximum number of LAG IDs requested. 706 */ 707 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 708 709 /* cmd_mbox_config_profile_max_port_per_lag 710 * Maximum number of ports per LAG requested. 711 */ 712 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 713 714 /* cmd_mbox_config_profile_max_mid 715 * Maximum Multicast IDs. 716 * Multicast IDs are allocated from 0 to max_mid-1 717 */ 718 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 719 720 /* cmd_mbox_config_profile_max_pgt 721 * Maximum records in the Port Group Table per Switch Partition. 722 * Port Group Table indexes are from 0 to max_pgt-1 723 */ 724 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 725 726 /* cmd_mbox_config_profile_max_system_port 727 * The maximum number of system ports that can be allocated. 728 */ 729 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 730 731 /* cmd_mbox_config_profile_max_vlan_groups 732 * Maximum number VLAN Groups for VLAN binding. 733 */ 734 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 735 736 /* cmd_mbox_config_profile_max_regions 737 * Maximum number of TCAM Regions. 738 */ 739 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 740 741 /* cmd_mbox_config_profile_max_flood_tables 742 * Maximum number of single-entry flooding tables. Different flooding tables 743 * can be associated with different packet types. 744 */ 745 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 746 747 /* cmd_mbox_config_profile_max_vid_flood_tables 748 * Maximum number of per-vid flooding tables. Flooding tables are associated 749 * to the different packet types for the different switch partitions. 750 * Table size is 4K entries covering all VID space. 751 */ 752 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 753 754 enum mlxsw_cmd_mbox_config_profile_flood_mode { 755 /* Mixed mode, where: 756 * max_flood_tables indicates the number of single-entry tables. 757 * max_vid_flood_tables indicates the number of per-VID tables. 758 * max_fid_offset_flood_tables indicates the number of FID-offset 759 * tables. max_fid_flood_tables indicates the number of per-FID tables. 760 * Reserved when unified bridge model is used. 761 */ 762 MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_MIXED = 3, 763 /* Controlled flood tables. Reserved when legacy bridge model is 764 * used. 765 */ 766 MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED = 4, 767 }; 768 769 /* cmd_mbox_config_profile_flood_mode 770 * Flooding mode to use. 771 */ 772 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 3); 773 774 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 775 * Maximum number of FID-offset flooding tables. 776 */ 777 MLXSW_ITEM32(cmd_mbox, config_profile, 778 max_fid_offset_flood_tables, 0x34, 24, 4); 779 780 /* cmd_mbox_config_profile_fid_offset_flood_table_size 781 * The size (number of entries) of each FID-offset flood table. 782 */ 783 MLXSW_ITEM32(cmd_mbox, config_profile, 784 fid_offset_flood_table_size, 0x34, 0, 16); 785 786 /* cmd_mbox_config_profile_max_fid_flood_tables 787 * Maximum number of per-FID flooding tables. 788 * 789 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 790 * FID value 4K and higher. 791 */ 792 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 793 794 /* cmd_mbox_config_profile_fid_flood_table_size 795 * The size (number of entries) of each per-FID table. 796 */ 797 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 798 799 /* cmd_mbox_config_profile_max_ib_mc 800 * Maximum number of multicast FDB records for InfiniBand 801 * FDB (in 512 chunks) per InfiniBand switch partition. 802 */ 803 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 804 805 /* cmd_mbox_config_profile_max_pkey 806 * Maximum per port PKEY table size (for PKEY enforcement) 807 */ 808 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 809 810 /* cmd_mbox_config_profile_ar_sec 811 * Primary/secondary capability 812 * Describes the number of adaptive routing sub-groups 813 * 0 - disable primary/secondary (single group) 814 * 1 - enable primary/secondary (2 sub-groups) 815 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 816 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 817 */ 818 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 819 820 /* cmd_mbox_config_profile_adaptive_routing_group_cap 821 * Adaptive Routing Group Capability. Indicates the number of AR groups 822 * supported. Note that when Primary/secondary is enabled, each 823 * primary/secondary couple consumes 2 adaptive routing entries. 824 */ 825 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 826 827 /* cmd_mbox_config_profile_arn 828 * Adaptive Routing Notification Enable 829 * Not supported in SwitchX, SwitchX-2 830 */ 831 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 832 833 /* cmd_mbox_config_profile_ubridge 834 * Unified Bridge 835 * 0 - non unified bridge 836 * 1 - unified bridge 837 */ 838 MLXSW_ITEM32(cmd_mbox, config_profile, ubridge, 0x50, 4, 1); 839 840 /* cmd_mbox_config_kvd_linear_size 841 * KVD Linear Size 842 * Valid for Spectrum only 843 * Allowed values are 128*N where N=0 or higher 844 */ 845 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); 846 847 /* cmd_mbox_config_kvd_hash_single_size 848 * KVD Hash single-entries size 849 * Valid for Spectrum only 850 * Allowed values are 128*N where N=0 or higher 851 * Must be greater or equal to cap_min_kvd_hash_single_size 852 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 853 */ 854 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); 855 856 /* cmd_mbox_config_kvd_hash_double_size 857 * KVD Hash double-entries size (units of single-size entries) 858 * Valid for Spectrum only 859 * Allowed values are 128*N where N=0 or higher 860 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size 861 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 862 */ 863 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); 864 865 /* cmd_mbox_config_profile_swid_config_mask 866 * Modify Switch Partition Configuration mask. When set, the configu- 867 * ration value for the Switch Partition are taken from the mailbox. 868 * When clear, the current configuration values are used. 869 * Bit 0 - set type 870 * Bit 1 - properties 871 * Other - reserved 872 */ 873 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 874 0x60, 24, 8, 0x08, 0x00, false); 875 876 /* cmd_mbox_config_profile_swid_config_type 877 * Switch Partition type. 878 * 0000 - disabled (Switch Partition does not exist) 879 * 0001 - InfiniBand 880 * 0010 - Ethernet 881 * 1000 - router port (SwitchX-2 only) 882 * Other - reserved 883 */ 884 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 885 0x60, 20, 4, 0x08, 0x00, false); 886 887 /* cmd_mbox_config_profile_swid_config_properties 888 * Switch Partition properties. 889 */ 890 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 891 0x60, 0, 8, 0x08, 0x00, false); 892 893 enum mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type { 894 /* uSec - 1.024uSec (default). Only bits 15:0 are valid. */ 895 MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_USEC, 896 /* FRC - Free Running Clock, units of 1nSec. 897 * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1. 898 */ 899 MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_FRC, 900 /* UTC. time_stamp[37:30] = Sec, time_stamp[29:0] = nSec. 901 * Reserved when SwitchX/2, Switch-IB/2 and Spectrum-1. 902 */ 903 MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 904 }; 905 906 /* cmd_mbox_config_profile_cqe_time_stamp_type 907 * CQE time_stamp_type for non-mirror-packets. 908 * Configured if set_cqe_time_stamp_type is set. 909 * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1. 910 */ 911 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_time_stamp_type, 0xB0, 8, 2); 912 913 /* cmd_mbox_config_profile_cqe_version 914 * CQE version: 915 * 0: CQE version is 0 916 * 1: CQE version is either 1 or 2 917 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. 918 */ 919 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); 920 921 /* ACCESS_REG - Access EMAD Supported Register 922 * ---------------------------------- 923 * OpMod == 0 (N/A), INMmod == 0 (N/A) 924 * ------------------------------------- 925 * The ACCESS_REG command supports accessing device registers. This access 926 * is mainly used for bootstrapping. 927 */ 928 929 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 930 bool reset_ok, 931 char *in_mbox, char *out_mbox) 932 { 933 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 934 0, 0, false, reset_ok, 935 in_mbox, MLXSW_CMD_MBOX_SIZE, 936 out_mbox, MLXSW_CMD_MBOX_SIZE); 937 } 938 939 /* SW2HW_DQ - Software to Hardware DQ 940 * ---------------------------------- 941 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 942 * INMmod == DQ number 943 * ---------------------------------------------- 944 * The SW2HW_DQ command transitions a descriptor queue from software to 945 * hardware ownership. The command enables posting WQEs and ringing DoorBells 946 * on the descriptor queue. 947 */ 948 949 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 950 char *in_mbox, u32 dq_number, 951 u8 opcode_mod) 952 { 953 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 954 opcode_mod, dq_number, 955 in_mbox, MLXSW_CMD_MBOX_SIZE); 956 } 957 958 enum { 959 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 960 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 961 }; 962 963 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 964 char *in_mbox, u32 dq_number) 965 { 966 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 967 MLXSW_CMD_OPCODE_MOD_SDQ); 968 } 969 970 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 971 char *in_mbox, u32 dq_number) 972 { 973 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 974 MLXSW_CMD_OPCODE_MOD_RDQ); 975 } 976 977 /* cmd_mbox_sw2hw_dq_cq 978 * Number of the CQ that this Descriptor Queue reports completions to. 979 */ 980 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 981 982 enum mlxsw_cmd_mbox_sw2hw_dq_sdq_lp { 983 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE, 984 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE, 985 }; 986 987 /* cmd_mbox_sw2hw_dq_sdq_lp 988 * SDQ local Processing 989 * 0: local processing by wqe.lp 990 * 1: local processing (ignoring wqe.lp) 991 */ 992 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_lp, 0x00, 23, 1); 993 994 /* cmd_mbox_sw2hw_dq_sdq_tclass 995 * SDQ: CPU Egress TClass 996 * RDQ: Reserved 997 */ 998 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 999 1000 /* cmd_mbox_sw2hw_dq_log2_dq_sz 1001 * Log (base 2) of the Descriptor Queue size in 4KB pages. 1002 */ 1003 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 1004 1005 /* cmd_mbox_sw2hw_dq_pa 1006 * Physical Address. 1007 */ 1008 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 1009 1010 /* HW2SW_DQ - Hardware to Software DQ 1011 * ---------------------------------- 1012 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1013 * INMmod == DQ number 1014 * ---------------------------------------------- 1015 * The HW2SW_DQ command transitions a descriptor queue from hardware to 1016 * software ownership. Incoming packets on the DQ are silently discarded, 1017 * SW should not post descriptors on nonoperational DQs. 1018 */ 1019 1020 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 1021 u32 dq_number, u8 opcode_mod) 1022 { 1023 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 1024 opcode_mod, dq_number); 1025 } 1026 1027 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 1028 u32 dq_number) 1029 { 1030 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 1031 MLXSW_CMD_OPCODE_MOD_SDQ); 1032 } 1033 1034 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 1035 u32 dq_number) 1036 { 1037 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 1038 MLXSW_CMD_OPCODE_MOD_RDQ); 1039 } 1040 1041 /* 2ERR_DQ - To Error DQ 1042 * --------------------- 1043 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1044 * INMmod == DQ number 1045 * ---------------------------------------------- 1046 * The 2ERR_DQ command transitions the DQ into the error state from the state 1047 * in which it has been. While the command is executed, some in-process 1048 * descriptors may complete. Once the DQ transitions into the error state, 1049 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 1050 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 1051 * When the command is completed successfully, the DQ is already in 1052 * the error state. 1053 */ 1054 1055 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 1056 u32 dq_number, u8 opcode_mod) 1057 { 1058 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1059 opcode_mod, dq_number); 1060 } 1061 1062 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 1063 u32 dq_number) 1064 { 1065 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1066 MLXSW_CMD_OPCODE_MOD_SDQ); 1067 } 1068 1069 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 1070 u32 dq_number) 1071 { 1072 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1073 MLXSW_CMD_OPCODE_MOD_RDQ); 1074 } 1075 1076 /* QUERY_DQ - Query DQ 1077 * --------------------- 1078 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1079 * INMmod == DQ number 1080 * ---------------------------------------------- 1081 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 1082 * 1083 * Note: Output mailbox has the same format as SW2HW_DQ. 1084 */ 1085 1086 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 1087 char *out_mbox, u32 dq_number, 1088 u8 opcode_mod) 1089 { 1090 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1091 opcode_mod, dq_number, false, 1092 out_mbox, MLXSW_CMD_MBOX_SIZE); 1093 } 1094 1095 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 1096 char *out_mbox, u32 dq_number) 1097 { 1098 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1099 MLXSW_CMD_OPCODE_MOD_SDQ); 1100 } 1101 1102 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 1103 char *out_mbox, u32 dq_number) 1104 { 1105 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1106 MLXSW_CMD_OPCODE_MOD_RDQ); 1107 } 1108 1109 /* SW2HW_CQ - Software to Hardware CQ 1110 * ---------------------------------- 1111 * OpMod == 0 (N/A), INMmod == CQ number 1112 * ------------------------------------- 1113 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 1114 * to hardware. The command takes the CQ context entry from the input mailbox 1115 * and stores it in the CQC in the ownership of the hardware. The command fails 1116 * if the requested CQC entry is already in the ownership of the hardware. 1117 */ 1118 1119 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 1120 char *in_mbox, u32 cq_number) 1121 { 1122 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 1123 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1124 } 1125 1126 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { 1127 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, 1128 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, 1129 }; 1130 1131 /* cmd_mbox_sw2hw_cq_cqe_ver 1132 * CQE Version. 1133 */ 1134 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); 1135 1136 /* cmd_mbox_sw2hw_cq_c_eqn 1137 * Event Queue this CQ reports completion events to. 1138 */ 1139 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 1140 1141 /* cmd_mbox_sw2hw_cq_st 1142 * Event delivery state machine 1143 * 0x0 - FIRED 1144 * 0x1 - ARMED (Request for Notification) 1145 */ 1146 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 1147 1148 /* cmd_mbox_sw2hw_cq_log_cq_size 1149 * Log (base 2) of the CQ size (in entries). 1150 */ 1151 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 1152 1153 /* cmd_mbox_sw2hw_cq_producer_counter 1154 * Producer Counter. The counter is incremented for each CQE that is 1155 * written by the HW to the CQ. 1156 * Maintained by HW (valid for the QUERY_CQ command only) 1157 */ 1158 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 1159 1160 /* cmd_mbox_sw2hw_cq_pa 1161 * Physical Address. 1162 */ 1163 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1164 1165 /* HW2SW_CQ - Hardware to Software CQ 1166 * ---------------------------------- 1167 * OpMod == 0 (N/A), INMmod == CQ number 1168 * ------------------------------------- 1169 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1170 * to software. The CQC entry is invalidated as a result of this command. 1171 */ 1172 1173 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1174 u32 cq_number) 1175 { 1176 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1177 0, cq_number); 1178 } 1179 1180 /* QUERY_CQ - Query CQ 1181 * ---------------------------------- 1182 * OpMod == 0 (N/A), INMmod == CQ number 1183 * ------------------------------------- 1184 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1185 * The command stores the snapshot in the output mailbox in the software format. 1186 * Note that the CQ context state and values are not affected by the QUERY_CQ 1187 * command. The QUERY_CQ command is for debug purposes only. 1188 * 1189 * Note: Output mailbox has the same format as SW2HW_CQ. 1190 */ 1191 1192 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1193 char *out_mbox, u32 cq_number) 1194 { 1195 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1196 0, cq_number, false, 1197 out_mbox, MLXSW_CMD_MBOX_SIZE); 1198 } 1199 1200 /* SW2HW_EQ - Software to Hardware EQ 1201 * ---------------------------------- 1202 * OpMod == 0 (N/A), INMmod == EQ number 1203 * ------------------------------------- 1204 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1205 * to hardware. The command takes the EQ context entry from the input mailbox 1206 * and stores it in the EQC in the ownership of the hardware. The command fails 1207 * if the requested EQC entry is already in the ownership of the hardware. 1208 */ 1209 1210 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1211 char *in_mbox, u32 eq_number) 1212 { 1213 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1214 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1215 } 1216 1217 /* cmd_mbox_sw2hw_eq_int_msix 1218 * When set, MSI-X cycles will be generated by this EQ. 1219 * When cleared, an interrupt will be generated by this EQ. 1220 */ 1221 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1222 1223 /* cmd_mbox_sw2hw_eq_st 1224 * Event delivery state machine 1225 * 0x0 - FIRED 1226 * 0x1 - ARMED (Request for Notification) 1227 * 0x11 - Always ARMED 1228 * other - reserved 1229 */ 1230 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1231 1232 /* cmd_mbox_sw2hw_eq_log_eq_size 1233 * Log (base 2) of the EQ size (in entries). 1234 */ 1235 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1236 1237 /* cmd_mbox_sw2hw_eq_producer_counter 1238 * Producer Counter. The counter is incremented for each EQE that is written 1239 * by the HW to the EQ. 1240 * Maintained by HW (valid for the QUERY_EQ command only) 1241 */ 1242 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1243 1244 /* cmd_mbox_sw2hw_eq_pa 1245 * Physical Address. 1246 */ 1247 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1248 1249 /* HW2SW_EQ - Hardware to Software EQ 1250 * ---------------------------------- 1251 * OpMod == 0 (N/A), INMmod == EQ number 1252 * ------------------------------------- 1253 */ 1254 1255 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1256 u32 eq_number) 1257 { 1258 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1259 0, eq_number); 1260 } 1261 1262 /* QUERY_EQ - Query EQ 1263 * ---------------------------------- 1264 * OpMod == 0 (N/A), INMmod == EQ number 1265 * ------------------------------------- 1266 * 1267 * Note: Output mailbox has the same format as SW2HW_EQ. 1268 */ 1269 1270 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1271 char *out_mbox, u32 eq_number) 1272 { 1273 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1274 0, eq_number, false, 1275 out_mbox, MLXSW_CMD_MBOX_SIZE); 1276 } 1277 1278 #endif 1279