1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/cmd.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the names of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _MLXSW_CMD_H 37 #define _MLXSW_CMD_H 38 39 #include "item.h" 40 41 #define MLXSW_CMD_MBOX_SIZE 4096 42 43 static inline char *mlxsw_cmd_mbox_alloc(void) 44 { 45 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 46 } 47 48 static inline void mlxsw_cmd_mbox_free(char *mbox) 49 { 50 kfree(mbox); 51 } 52 53 static inline void mlxsw_cmd_mbox_zero(char *mbox) 54 { 55 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 56 } 57 58 struct mlxsw_core; 59 60 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 61 u32 in_mod, bool out_mbox_direct, 62 char *in_mbox, size_t in_mbox_size, 63 char *out_mbox, size_t out_mbox_size); 64 65 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 66 u8 opcode_mod, u32 in_mod, char *in_mbox, 67 size_t in_mbox_size) 68 { 69 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 70 in_mbox, in_mbox_size, NULL, 0); 71 } 72 73 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 74 u8 opcode_mod, u32 in_mod, 75 bool out_mbox_direct, 76 char *out_mbox, size_t out_mbox_size) 77 { 78 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 79 out_mbox_direct, NULL, 0, 80 out_mbox, out_mbox_size); 81 } 82 83 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 84 u8 opcode_mod, u32 in_mod) 85 { 86 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 87 NULL, 0, NULL, 0); 88 } 89 90 enum mlxsw_cmd_opcode { 91 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 92 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 93 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 94 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 95 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 96 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 97 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 98 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 99 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 100 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 101 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 102 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 103 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 104 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 105 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 106 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 107 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 108 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, 109 }; 110 111 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 112 { 113 switch (opcode) { 114 case MLXSW_CMD_OPCODE_QUERY_FW: 115 return "QUERY_FW"; 116 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 117 return "QUERY_BOARDINFO"; 118 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 119 return "QUERY_AQ_CAP"; 120 case MLXSW_CMD_OPCODE_MAP_FA: 121 return "MAP_FA"; 122 case MLXSW_CMD_OPCODE_UNMAP_FA: 123 return "UNMAP_FA"; 124 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 125 return "CONFIG_PROFILE"; 126 case MLXSW_CMD_OPCODE_ACCESS_REG: 127 return "ACCESS_REG"; 128 case MLXSW_CMD_OPCODE_SW2HW_DQ: 129 return "SW2HW_DQ"; 130 case MLXSW_CMD_OPCODE_HW2SW_DQ: 131 return "HW2SW_DQ"; 132 case MLXSW_CMD_OPCODE_2ERR_DQ: 133 return "2ERR_DQ"; 134 case MLXSW_CMD_OPCODE_QUERY_DQ: 135 return "QUERY_DQ"; 136 case MLXSW_CMD_OPCODE_SW2HW_CQ: 137 return "SW2HW_CQ"; 138 case MLXSW_CMD_OPCODE_HW2SW_CQ: 139 return "HW2SW_CQ"; 140 case MLXSW_CMD_OPCODE_QUERY_CQ: 141 return "QUERY_CQ"; 142 case MLXSW_CMD_OPCODE_SW2HW_EQ: 143 return "SW2HW_EQ"; 144 case MLXSW_CMD_OPCODE_HW2SW_EQ: 145 return "HW2SW_EQ"; 146 case MLXSW_CMD_OPCODE_QUERY_EQ: 147 return "QUERY_EQ"; 148 case MLXSW_CMD_OPCODE_QUERY_RESOURCES: 149 return "QUERY_RESOURCES"; 150 default: 151 return "*UNKNOWN*"; 152 } 153 } 154 155 enum mlxsw_cmd_status { 156 /* Command execution succeeded. */ 157 MLXSW_CMD_STATUS_OK = 0x00, 158 /* Internal error (e.g. bus error) occurred while processing command. */ 159 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 160 /* Operation/command not supported or opcode modifier not supported. */ 161 MLXSW_CMD_STATUS_BAD_OP = 0x02, 162 /* Parameter not supported, parameter out of range. */ 163 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 164 /* System was not enabled or bad system state. */ 165 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 166 /* Attempt to access reserved or unallocated resource, or resource in 167 * inappropriate ownership. 168 */ 169 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 170 /* Requested resource is currently executing a command. */ 171 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 172 /* Required capability exceeds device limits. */ 173 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 174 /* Resource is not in the appropriate state or ownership. */ 175 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 176 /* Index out of range (might be beyond table size or attempt to 177 * access a reserved resource). 178 */ 179 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 180 /* NVMEM checksum/CRC failed. */ 181 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 182 /* Bad management packet (silently discarded). */ 183 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 184 }; 185 186 static inline const char *mlxsw_cmd_status_str(u8 status) 187 { 188 switch (status) { 189 case MLXSW_CMD_STATUS_OK: 190 return "OK"; 191 case MLXSW_CMD_STATUS_INTERNAL_ERR: 192 return "INTERNAL_ERR"; 193 case MLXSW_CMD_STATUS_BAD_OP: 194 return "BAD_OP"; 195 case MLXSW_CMD_STATUS_BAD_PARAM: 196 return "BAD_PARAM"; 197 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 198 return "BAD_SYS_STATE"; 199 case MLXSW_CMD_STATUS_BAD_RESOURCE: 200 return "BAD_RESOURCE"; 201 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 202 return "RESOURCE_BUSY"; 203 case MLXSW_CMD_STATUS_EXCEED_LIM: 204 return "EXCEED_LIM"; 205 case MLXSW_CMD_STATUS_BAD_RES_STATE: 206 return "BAD_RES_STATE"; 207 case MLXSW_CMD_STATUS_BAD_INDEX: 208 return "BAD_INDEX"; 209 case MLXSW_CMD_STATUS_BAD_NVMEM: 210 return "BAD_NVMEM"; 211 case MLXSW_CMD_STATUS_BAD_PKT: 212 return "BAD_PKT"; 213 default: 214 return "*UNKNOWN*"; 215 } 216 } 217 218 /* QUERY_FW - Query Firmware 219 * ------------------------- 220 * OpMod == 0, INMmod == 0 221 * ----------------------- 222 * The QUERY_FW command retrieves information related to firmware, command 223 * interface version and the amount of resources that should be allocated to 224 * the firmware. 225 */ 226 227 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 228 char *out_mbox) 229 { 230 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 231 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 232 } 233 234 /* cmd_mbox_query_fw_fw_pages 235 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 236 */ 237 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 238 239 /* cmd_mbox_query_fw_fw_rev_major 240 * Firmware Revision - Major 241 */ 242 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 243 244 /* cmd_mbox_query_fw_fw_rev_subminor 245 * Firmware Sub-minor version (Patch level) 246 */ 247 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 248 249 /* cmd_mbox_query_fw_fw_rev_minor 250 * Firmware Revision - Minor 251 */ 252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 253 254 /* cmd_mbox_query_fw_core_clk 255 * Internal Clock Frequency (in MHz) 256 */ 257 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 258 259 /* cmd_mbox_query_fw_cmd_interface_rev 260 * Command Interface Interpreter Revision ID. This number is bumped up 261 * every time a non-backward-compatible change is done for the command 262 * interface. The current cmd_interface_rev is 1. 263 */ 264 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 265 266 /* cmd_mbox_query_fw_dt 267 * If set, Debug Trace is supported 268 */ 269 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 270 271 /* cmd_mbox_query_fw_api_version 272 * Indicates the version of the API, to enable software querying 273 * for compatibility. The current api_version is 1. 274 */ 275 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 276 277 /* cmd_mbox_query_fw_fw_hour 278 * Firmware timestamp - hour 279 */ 280 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 281 282 /* cmd_mbox_query_fw_fw_minutes 283 * Firmware timestamp - minutes 284 */ 285 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 286 287 /* cmd_mbox_query_fw_fw_seconds 288 * Firmware timestamp - seconds 289 */ 290 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 291 292 /* cmd_mbox_query_fw_fw_year 293 * Firmware timestamp - year 294 */ 295 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 296 297 /* cmd_mbox_query_fw_fw_month 298 * Firmware timestamp - month 299 */ 300 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 301 302 /* cmd_mbox_query_fw_fw_day 303 * Firmware timestamp - day 304 */ 305 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 306 307 /* cmd_mbox_query_fw_clr_int_base_offset 308 * Clear Interrupt register's offset from clr_int_bar register 309 * in PCI address space. 310 */ 311 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 312 313 /* cmd_mbox_query_fw_clr_int_bar 314 * PCI base address register (BAR) where clr_int register is located. 315 * 00 - BAR 0-1 (64 bit BAR) 316 */ 317 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 318 319 /* cmd_mbox_query_fw_error_buf_offset 320 * Read Only buffer for internal error reports of offset 321 * from error_buf_bar register in PCI address space). 322 */ 323 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 324 325 /* cmd_mbox_query_fw_error_buf_size 326 * Internal error buffer size in DWORDs 327 */ 328 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 329 330 /* cmd_mbox_query_fw_error_int_bar 331 * PCI base address register (BAR) where error buffer 332 * register is located. 333 * 00 - BAR 0-1 (64 bit BAR) 334 */ 335 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 336 337 /* cmd_mbox_query_fw_doorbell_page_offset 338 * Offset of the doorbell page 339 */ 340 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 341 342 /* cmd_mbox_query_fw_doorbell_page_bar 343 * PCI base address register (BAR) of the doorbell page 344 * 00 - BAR 0-1 (64 bit BAR) 345 */ 346 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 347 348 /* QUERY_BOARDINFO - Query Board Information 349 * ----------------------------------------- 350 * OpMod == 0 (N/A), INMmod == 0 (N/A) 351 * ----------------------------------- 352 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 353 */ 354 355 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 356 char *out_mbox) 357 { 358 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 359 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 360 } 361 362 /* cmd_mbox_boardinfo_intapin 363 * When PCIe interrupt messages are being used, this value is used for clearing 364 * an interrupt. When using MSI-X, this register is not used. 365 */ 366 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 367 368 /* cmd_mbox_boardinfo_vsd_vendor_id 369 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 370 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 371 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 372 * format and encoding as long as they use their assigned vsd_vendor_id. 373 */ 374 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 375 376 /* cmd_mbox_boardinfo_vsd 377 * Vendor Specific Data. The VSD string that is burnt to the Flash 378 * with the firmware. 379 */ 380 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 381 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 382 383 /* cmd_mbox_boardinfo_psid 384 * The PSID field is a 16-ascii (byte) character string which acts as 385 * the board ID. The PSID format is used in conjunction with 386 * Mellanox vsd_vendor_id (15B3h). 387 */ 388 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 389 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 390 391 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 392 * ----------------------------------------------------- 393 * OpMod == 0 (N/A), INMmod == 0 (N/A) 394 * ----------------------------------- 395 * The QUERY_AQ_CAP command returns the device asynchronous queues 396 * capabilities supported. 397 */ 398 399 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 400 char *out_mbox) 401 { 402 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 403 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 404 } 405 406 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 407 * Log (base 2) of max WQEs allowed on SDQ. 408 */ 409 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 410 411 /* cmd_mbox_query_aq_cap_max_num_sdqs 412 * Maximum number of SDQs. 413 */ 414 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 415 416 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 417 * Log (base 2) of max WQEs allowed on RDQ. 418 */ 419 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 420 421 /* cmd_mbox_query_aq_cap_max_num_rdqs 422 * Maximum number of RDQs. 423 */ 424 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 425 426 /* cmd_mbox_query_aq_cap_log_max_cq_sz 427 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. 428 */ 429 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 430 431 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz 432 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. 433 */ 434 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); 435 436 /* cmd_mbox_query_aq_cap_max_num_cqs 437 * Maximum number of CQs. 438 */ 439 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 440 441 /* cmd_mbox_query_aq_cap_log_max_eq_sz 442 * Log (base 2) of max EQEs allowed on EQ. 443 */ 444 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 445 446 /* cmd_mbox_query_aq_cap_max_num_eqs 447 * Maximum number of EQs. 448 */ 449 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 450 451 /* cmd_mbox_query_aq_cap_max_sg_sq 452 * The maximum S/G list elements in an DSQ. DSQ must not contain 453 * more S/G entries than indicated here. 454 */ 455 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 456 457 /* cmd_mbox_query_aq_cap_ 458 * The maximum S/G list elements in an DRQ. DRQ must not contain 459 * more S/G entries than indicated here. 460 */ 461 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 462 463 /* MAP_FA - Map Firmware Area 464 * -------------------------- 465 * OpMod == 0 (N/A), INMmod == Number of VPM entries 466 * ------------------------------------------------- 467 * The MAP_FA command passes physical pages to the switch. These pages 468 * are used to store the device firmware. MAP_FA can be executed multiple 469 * times until all the firmware area is mapped (the size that should be 470 * mapped is retrieved through the QUERY_FW command). All required pages 471 * must be mapped to finish the initialization phase. Physical memory 472 * passed in this command must be pinned. 473 */ 474 475 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 476 477 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 478 char *in_mbox, u32 vpm_entries_count) 479 { 480 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 481 0, vpm_entries_count, 482 in_mbox, MLXSW_CMD_MBOX_SIZE); 483 } 484 485 /* cmd_mbox_map_fa_pa 486 * Physical Address. 487 */ 488 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 489 490 /* cmd_mbox_map_fa_log2size 491 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 492 * that starts at PA_L/H. 493 */ 494 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 495 496 /* UNMAP_FA - Unmap Firmware Area 497 * ------------------------------ 498 * OpMod == 0 (N/A), INMmod == 0 (N/A) 499 * ----------------------------------- 500 * The UNMAP_FA command unload the firmware and unmaps all the 501 * firmware area. After this command is completed the device will not access 502 * the pages that were mapped to the firmware area. After executing UNMAP_FA 503 * command, software reset must be done prior to execution of MAP_FW command. 504 */ 505 506 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 507 { 508 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 509 } 510 511 /* QUERY_RESOURCES - Query chip resources 512 * -------------------------------------- 513 * OpMod == 0 (N/A) , INMmod is index 514 * ---------------------------------- 515 * The QUERY_RESOURCES command retrieves information related to chip resources 516 * by resource ID. Every command returns 32 entries. INmod is being use as base. 517 * for example, index 1 will return entries 32-63. When the tables end and there 518 * are no more sources in the table, will return resource id 0xFFF to indicate 519 * it. 520 */ 521 522 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff 523 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 524 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 525 526 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, 527 char *out_mbox, int index) 528 { 529 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES, 530 0, index, false, out_mbox, 531 MLXSW_CMD_MBOX_SIZE); 532 } 533 534 /* cmd_mbox_query_resource_id 535 * The resource id. 0xFFFF indicates table's end. 536 */ 537 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); 538 539 /* cmd_mbox_query_resource_data 540 * The resource 541 */ 542 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, 543 0x00, 0, 40, 0x8, 0, false); 544 545 /* CONFIG_PROFILE (Set) - Configure Switch Profile 546 * ------------------------------ 547 * OpMod == 1 (Set), INMmod == 0 (N/A) 548 * ----------------------------------- 549 * The CONFIG_PROFILE command sets the switch profile. The command can be 550 * executed on the device only once at startup in order to allocate and 551 * configure all switch resources and prepare it for operational mode. 552 * It is not possible to change the device profile after the chip is 553 * in operational mode. 554 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 555 * state therefore it is required to perform software reset to the device 556 * following an unsuccessful completion of the command. It is required 557 * to perform software reset to the device to change an existing profile. 558 */ 559 560 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 561 char *in_mbox) 562 { 563 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 564 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 565 } 566 567 /* cmd_mbox_config_profile_set_max_vepa_channels 568 * Capability bit. Setting a bit to 1 configures the profile 569 * according to the mailbox contents. 570 */ 571 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 572 573 /* cmd_mbox_config_profile_set_max_lag 574 * Capability bit. Setting a bit to 1 configures the profile 575 * according to the mailbox contents. 576 */ 577 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 578 579 /* cmd_mbox_config_profile_set_max_port_per_lag 580 * Capability bit. Setting a bit to 1 configures the profile 581 * according to the mailbox contents. 582 */ 583 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 584 585 /* cmd_mbox_config_profile_set_max_mid 586 * Capability bit. Setting a bit to 1 configures the profile 587 * according to the mailbox contents. 588 */ 589 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 590 591 /* cmd_mbox_config_profile_set_max_pgt 592 * Capability bit. Setting a bit to 1 configures the profile 593 * according to the mailbox contents. 594 */ 595 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 596 597 /* cmd_mbox_config_profile_set_max_system_port 598 * Capability bit. Setting a bit to 1 configures the profile 599 * according to the mailbox contents. 600 */ 601 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 602 603 /* cmd_mbox_config_profile_set_max_vlan_groups 604 * Capability bit. Setting a bit to 1 configures the profile 605 * according to the mailbox contents. 606 */ 607 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 608 609 /* cmd_mbox_config_profile_set_max_regions 610 * Capability bit. Setting a bit to 1 configures the profile 611 * according to the mailbox contents. 612 */ 613 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 614 615 /* cmd_mbox_config_profile_set_flood_mode 616 * Capability bit. Setting a bit to 1 configures the profile 617 * according to the mailbox contents. 618 */ 619 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 620 621 /* cmd_mbox_config_profile_set_max_flood_tables 622 * Capability bit. Setting a bit to 1 configures the profile 623 * according to the mailbox contents. 624 */ 625 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 626 627 /* cmd_mbox_config_profile_set_max_ib_mc 628 * Capability bit. Setting a bit to 1 configures the profile 629 * according to the mailbox contents. 630 */ 631 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 632 633 /* cmd_mbox_config_profile_set_max_pkey 634 * Capability bit. Setting a bit to 1 configures the profile 635 * according to the mailbox contents. 636 */ 637 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 638 639 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 640 * Capability bit. Setting a bit to 1 configures the profile 641 * according to the mailbox contents. 642 */ 643 MLXSW_ITEM32(cmd_mbox, config_profile, 644 set_adaptive_routing_group_cap, 0x0C, 14, 1); 645 646 /* cmd_mbox_config_profile_set_ar_sec 647 * Capability bit. Setting a bit to 1 configures the profile 648 * according to the mailbox contents. 649 */ 650 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 651 652 /* cmd_mbox_config_set_kvd_linear_size 653 * Capability bit. Setting a bit to 1 configures the profile 654 * according to the mailbox contents. 655 */ 656 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); 657 658 /* cmd_mbox_config_set_kvd_hash_single_size 659 * Capability bit. Setting a bit to 1 configures the profile 660 * according to the mailbox contents. 661 */ 662 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); 663 664 /* cmd_mbox_config_set_kvd_hash_double_size 665 * Capability bit. Setting a bit to 1 configures the profile 666 * according to the mailbox contents. 667 */ 668 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 669 670 /* cmd_mbox_config_set_cqe_version 671 * Capability bit. Setting a bit to 1 configures the profile 672 * according to the mailbox contents. 673 */ 674 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); 675 676 /* cmd_mbox_config_profile_max_vepa_channels 677 * Maximum number of VEPA channels per port (0 through 16) 678 * 0 - multi-channel VEPA is disabled 679 */ 680 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 681 682 /* cmd_mbox_config_profile_max_lag 683 * Maximum number of LAG IDs requested. 684 */ 685 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 686 687 /* cmd_mbox_config_profile_max_port_per_lag 688 * Maximum number of ports per LAG requested. 689 */ 690 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 691 692 /* cmd_mbox_config_profile_max_mid 693 * Maximum Multicast IDs. 694 * Multicast IDs are allocated from 0 to max_mid-1 695 */ 696 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 697 698 /* cmd_mbox_config_profile_max_pgt 699 * Maximum records in the Port Group Table per Switch Partition. 700 * Port Group Table indexes are from 0 to max_pgt-1 701 */ 702 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 703 704 /* cmd_mbox_config_profile_max_system_port 705 * The maximum number of system ports that can be allocated. 706 */ 707 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 708 709 /* cmd_mbox_config_profile_max_vlan_groups 710 * Maximum number VLAN Groups for VLAN binding. 711 */ 712 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 713 714 /* cmd_mbox_config_profile_max_regions 715 * Maximum number of TCAM Regions. 716 */ 717 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 718 719 /* cmd_mbox_config_profile_max_flood_tables 720 * Maximum number of single-entry flooding tables. Different flooding tables 721 * can be associated with different packet types. 722 */ 723 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 724 725 /* cmd_mbox_config_profile_max_vid_flood_tables 726 * Maximum number of per-vid flooding tables. Flooding tables are associated 727 * to the different packet types for the different switch partitions. 728 * Table size is 4K entries covering all VID space. 729 */ 730 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 731 732 /* cmd_mbox_config_profile_flood_mode 733 * Flooding mode to use. 734 * 0-2 - Backward compatible modes for SwitchX devices. 735 * 3 - Mixed mode, where: 736 * max_flood_tables indicates the number of single-entry tables. 737 * max_vid_flood_tables indicates the number of per-VID tables. 738 * max_fid_offset_flood_tables indicates the number of FID-offset tables. 739 * max_fid_flood_tables indicates the number of per-FID tables. 740 */ 741 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2); 742 743 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 744 * Maximum number of FID-offset flooding tables. 745 */ 746 MLXSW_ITEM32(cmd_mbox, config_profile, 747 max_fid_offset_flood_tables, 0x34, 24, 4); 748 749 /* cmd_mbox_config_profile_fid_offset_flood_table_size 750 * The size (number of entries) of each FID-offset flood table. 751 */ 752 MLXSW_ITEM32(cmd_mbox, config_profile, 753 fid_offset_flood_table_size, 0x34, 0, 16); 754 755 /* cmd_mbox_config_profile_max_fid_flood_tables 756 * Maximum number of per-FID flooding tables. 757 * 758 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 759 * FID value 4K and higher. 760 */ 761 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 762 763 /* cmd_mbox_config_profile_fid_flood_table_size 764 * The size (number of entries) of each per-FID table. 765 */ 766 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 767 768 /* cmd_mbox_config_profile_max_ib_mc 769 * Maximum number of multicast FDB records for InfiniBand 770 * FDB (in 512 chunks) per InfiniBand switch partition. 771 */ 772 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 773 774 /* cmd_mbox_config_profile_max_pkey 775 * Maximum per port PKEY table size (for PKEY enforcement) 776 */ 777 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 778 779 /* cmd_mbox_config_profile_ar_sec 780 * Primary/secondary capability 781 * Describes the number of adaptive routing sub-groups 782 * 0 - disable primary/secondary (single group) 783 * 1 - enable primary/secondary (2 sub-groups) 784 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 785 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 786 */ 787 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 788 789 /* cmd_mbox_config_profile_adaptive_routing_group_cap 790 * Adaptive Routing Group Capability. Indicates the number of AR groups 791 * supported. Note that when Primary/secondary is enabled, each 792 * primary/secondary couple consumes 2 adaptive routing entries. 793 */ 794 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 795 796 /* cmd_mbox_config_profile_arn 797 * Adaptive Routing Notification Enable 798 * Not supported in SwitchX, SwitchX-2 799 */ 800 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 801 802 /* cmd_mbox_config_kvd_linear_size 803 * KVD Linear Size 804 * Valid for Spectrum only 805 * Allowed values are 128*N where N=0 or higher 806 */ 807 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); 808 809 /* cmd_mbox_config_kvd_hash_single_size 810 * KVD Hash single-entries size 811 * Valid for Spectrum only 812 * Allowed values are 128*N where N=0 or higher 813 * Must be greater or equal to cap_min_kvd_hash_single_size 814 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 815 */ 816 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); 817 818 /* cmd_mbox_config_kvd_hash_double_size 819 * KVD Hash double-entries size (units of single-size entries) 820 * Valid for Spectrum only 821 * Allowed values are 128*N where N=0 or higher 822 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size 823 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 824 */ 825 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); 826 827 /* cmd_mbox_config_profile_swid_config_mask 828 * Modify Switch Partition Configuration mask. When set, the configu- 829 * ration value for the Switch Partition are taken from the mailbox. 830 * When clear, the current configuration values are used. 831 * Bit 0 - set type 832 * Bit 1 - properties 833 * Other - reserved 834 */ 835 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 836 0x60, 24, 8, 0x08, 0x00, false); 837 838 /* cmd_mbox_config_profile_swid_config_type 839 * Switch Partition type. 840 * 0000 - disabled (Switch Partition does not exist) 841 * 0001 - InfiniBand 842 * 0010 - Ethernet 843 * 1000 - router port (SwitchX-2 only) 844 * Other - reserved 845 */ 846 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 847 0x60, 20, 4, 0x08, 0x00, false); 848 849 /* cmd_mbox_config_profile_swid_config_properties 850 * Switch Partition properties. 851 */ 852 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 853 0x60, 0, 8, 0x08, 0x00, false); 854 855 /* cmd_mbox_config_profile_cqe_version 856 * CQE version: 857 * 0: CQE version is 0 858 * 1: CQE version is either 1 or 2 859 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. 860 */ 861 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); 862 863 /* ACCESS_REG - Access EMAD Supported Register 864 * ---------------------------------- 865 * OpMod == 0 (N/A), INMmod == 0 (N/A) 866 * ------------------------------------- 867 * The ACCESS_REG command supports accessing device registers. This access 868 * is mainly used for bootstrapping. 869 */ 870 871 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 872 char *in_mbox, char *out_mbox) 873 { 874 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 875 0, 0, false, in_mbox, MLXSW_CMD_MBOX_SIZE, 876 out_mbox, MLXSW_CMD_MBOX_SIZE); 877 } 878 879 /* SW2HW_DQ - Software to Hardware DQ 880 * ---------------------------------- 881 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 882 * INMmod == DQ number 883 * ---------------------------------------------- 884 * The SW2HW_DQ command transitions a descriptor queue from software to 885 * hardware ownership. The command enables posting WQEs and ringing DoorBells 886 * on the descriptor queue. 887 */ 888 889 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 890 char *in_mbox, u32 dq_number, 891 u8 opcode_mod) 892 { 893 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 894 opcode_mod, dq_number, 895 in_mbox, MLXSW_CMD_MBOX_SIZE); 896 } 897 898 enum { 899 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 900 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 901 }; 902 903 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 904 char *in_mbox, u32 dq_number) 905 { 906 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 907 MLXSW_CMD_OPCODE_MOD_SDQ); 908 } 909 910 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 911 char *in_mbox, u32 dq_number) 912 { 913 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 914 MLXSW_CMD_OPCODE_MOD_RDQ); 915 } 916 917 /* cmd_mbox_sw2hw_dq_cq 918 * Number of the CQ that this Descriptor Queue reports completions to. 919 */ 920 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 921 922 /* cmd_mbox_sw2hw_dq_sdq_tclass 923 * SDQ: CPU Egress TClass 924 * RDQ: Reserved 925 */ 926 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 927 928 /* cmd_mbox_sw2hw_dq_log2_dq_sz 929 * Log (base 2) of the Descriptor Queue size in 4KB pages. 930 */ 931 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 932 933 /* cmd_mbox_sw2hw_dq_pa 934 * Physical Address. 935 */ 936 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 937 938 /* HW2SW_DQ - Hardware to Software DQ 939 * ---------------------------------- 940 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 941 * INMmod == DQ number 942 * ---------------------------------------------- 943 * The HW2SW_DQ command transitions a descriptor queue from hardware to 944 * software ownership. Incoming packets on the DQ are silently discarded, 945 * SW should not post descriptors on nonoperational DQs. 946 */ 947 948 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 949 u32 dq_number, u8 opcode_mod) 950 { 951 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 952 opcode_mod, dq_number); 953 } 954 955 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 956 u32 dq_number) 957 { 958 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 959 MLXSW_CMD_OPCODE_MOD_SDQ); 960 } 961 962 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 963 u32 dq_number) 964 { 965 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 966 MLXSW_CMD_OPCODE_MOD_RDQ); 967 } 968 969 /* 2ERR_DQ - To Error DQ 970 * --------------------- 971 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 972 * INMmod == DQ number 973 * ---------------------------------------------- 974 * The 2ERR_DQ command transitions the DQ into the error state from the state 975 * in which it has been. While the command is executed, some in-process 976 * descriptors may complete. Once the DQ transitions into the error state, 977 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 978 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 979 * When the command is completed successfully, the DQ is already in 980 * the error state. 981 */ 982 983 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 984 u32 dq_number, u8 opcode_mod) 985 { 986 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 987 opcode_mod, dq_number); 988 } 989 990 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 991 u32 dq_number) 992 { 993 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 994 MLXSW_CMD_OPCODE_MOD_SDQ); 995 } 996 997 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 998 u32 dq_number) 999 { 1000 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1001 MLXSW_CMD_OPCODE_MOD_RDQ); 1002 } 1003 1004 /* QUERY_DQ - Query DQ 1005 * --------------------- 1006 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1007 * INMmod == DQ number 1008 * ---------------------------------------------- 1009 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 1010 * 1011 * Note: Output mailbox has the same format as SW2HW_DQ. 1012 */ 1013 1014 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 1015 char *out_mbox, u32 dq_number, 1016 u8 opcode_mod) 1017 { 1018 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1019 opcode_mod, dq_number, false, 1020 out_mbox, MLXSW_CMD_MBOX_SIZE); 1021 } 1022 1023 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 1024 char *out_mbox, u32 dq_number) 1025 { 1026 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1027 MLXSW_CMD_OPCODE_MOD_SDQ); 1028 } 1029 1030 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 1031 char *out_mbox, u32 dq_number) 1032 { 1033 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1034 MLXSW_CMD_OPCODE_MOD_RDQ); 1035 } 1036 1037 /* SW2HW_CQ - Software to Hardware CQ 1038 * ---------------------------------- 1039 * OpMod == 0 (N/A), INMmod == CQ number 1040 * ------------------------------------- 1041 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 1042 * to hardware. The command takes the CQ context entry from the input mailbox 1043 * and stores it in the CQC in the ownership of the hardware. The command fails 1044 * if the requested CQC entry is already in the ownership of the hardware. 1045 */ 1046 1047 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 1048 char *in_mbox, u32 cq_number) 1049 { 1050 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 1051 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1052 } 1053 1054 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { 1055 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, 1056 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, 1057 }; 1058 1059 /* cmd_mbox_sw2hw_cq_cqe_ver 1060 * CQE Version. 1061 */ 1062 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); 1063 1064 /* cmd_mbox_sw2hw_cq_c_eqn 1065 * Event Queue this CQ reports completion events to. 1066 */ 1067 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 1068 1069 /* cmd_mbox_sw2hw_cq_st 1070 * Event delivery state machine 1071 * 0x0 - FIRED 1072 * 0x1 - ARMED (Request for Notification) 1073 */ 1074 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 1075 1076 /* cmd_mbox_sw2hw_cq_log_cq_size 1077 * Log (base 2) of the CQ size (in entries). 1078 */ 1079 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 1080 1081 /* cmd_mbox_sw2hw_cq_producer_counter 1082 * Producer Counter. The counter is incremented for each CQE that is 1083 * written by the HW to the CQ. 1084 * Maintained by HW (valid for the QUERY_CQ command only) 1085 */ 1086 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 1087 1088 /* cmd_mbox_sw2hw_cq_pa 1089 * Physical Address. 1090 */ 1091 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1092 1093 /* HW2SW_CQ - Hardware to Software CQ 1094 * ---------------------------------- 1095 * OpMod == 0 (N/A), INMmod == CQ number 1096 * ------------------------------------- 1097 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1098 * to software. The CQC entry is invalidated as a result of this command. 1099 */ 1100 1101 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1102 u32 cq_number) 1103 { 1104 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1105 0, cq_number); 1106 } 1107 1108 /* QUERY_CQ - Query CQ 1109 * ---------------------------------- 1110 * OpMod == 0 (N/A), INMmod == CQ number 1111 * ------------------------------------- 1112 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1113 * The command stores the snapshot in the output mailbox in the software format. 1114 * Note that the CQ context state and values are not affected by the QUERY_CQ 1115 * command. The QUERY_CQ command is for debug purposes only. 1116 * 1117 * Note: Output mailbox has the same format as SW2HW_CQ. 1118 */ 1119 1120 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1121 char *out_mbox, u32 cq_number) 1122 { 1123 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1124 0, cq_number, false, 1125 out_mbox, MLXSW_CMD_MBOX_SIZE); 1126 } 1127 1128 /* SW2HW_EQ - Software to Hardware EQ 1129 * ---------------------------------- 1130 * OpMod == 0 (N/A), INMmod == EQ number 1131 * ------------------------------------- 1132 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1133 * to hardware. The command takes the EQ context entry from the input mailbox 1134 * and stores it in the EQC in the ownership of the hardware. The command fails 1135 * if the requested EQC entry is already in the ownership of the hardware. 1136 */ 1137 1138 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1139 char *in_mbox, u32 eq_number) 1140 { 1141 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1142 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1143 } 1144 1145 /* cmd_mbox_sw2hw_eq_int_msix 1146 * When set, MSI-X cycles will be generated by this EQ. 1147 * When cleared, an interrupt will be generated by this EQ. 1148 */ 1149 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1150 1151 /* cmd_mbox_sw2hw_eq_st 1152 * Event delivery state machine 1153 * 0x0 - FIRED 1154 * 0x1 - ARMED (Request for Notification) 1155 * 0x11 - Always ARMED 1156 * other - reserved 1157 */ 1158 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1159 1160 /* cmd_mbox_sw2hw_eq_log_eq_size 1161 * Log (base 2) of the EQ size (in entries). 1162 */ 1163 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1164 1165 /* cmd_mbox_sw2hw_eq_producer_counter 1166 * Producer Counter. The counter is incremented for each EQE that is written 1167 * by the HW to the EQ. 1168 * Maintained by HW (valid for the QUERY_EQ command only) 1169 */ 1170 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1171 1172 /* cmd_mbox_sw2hw_eq_pa 1173 * Physical Address. 1174 */ 1175 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1176 1177 /* HW2SW_EQ - Hardware to Software EQ 1178 * ---------------------------------- 1179 * OpMod == 0 (N/A), INMmod == EQ number 1180 * ------------------------------------- 1181 */ 1182 1183 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1184 u32 eq_number) 1185 { 1186 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1187 0, eq_number); 1188 } 1189 1190 /* QUERY_EQ - Query EQ 1191 * ---------------------------------- 1192 * OpMod == 0 (N/A), INMmod == EQ number 1193 * ------------------------------------- 1194 * 1195 * Note: Output mailbox has the same format as SW2HW_EQ. 1196 */ 1197 1198 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1199 char *out_mbox, u32 eq_number) 1200 { 1201 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1202 0, eq_number, false, 1203 out_mbox, MLXSW_CMD_MBOX_SIZE); 1204 } 1205 1206 #endif 1207