1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_CMD_H 5 #define _MLXSW_CMD_H 6 7 #include "item.h" 8 9 #define MLXSW_CMD_MBOX_SIZE 4096 10 11 static inline char *mlxsw_cmd_mbox_alloc(void) 12 { 13 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 14 } 15 16 static inline void mlxsw_cmd_mbox_free(char *mbox) 17 { 18 kfree(mbox); 19 } 20 21 static inline void mlxsw_cmd_mbox_zero(char *mbox) 22 { 23 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 24 } 25 26 struct mlxsw_core; 27 28 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 29 u32 in_mod, bool out_mbox_direct, bool reset_ok, 30 char *in_mbox, size_t in_mbox_size, 31 char *out_mbox, size_t out_mbox_size); 32 33 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 34 u8 opcode_mod, u32 in_mod, char *in_mbox, 35 size_t in_mbox_size) 36 { 37 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 38 false, in_mbox, in_mbox_size, NULL, 0); 39 } 40 41 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 42 u8 opcode_mod, u32 in_mod, 43 bool out_mbox_direct, 44 char *out_mbox, size_t out_mbox_size) 45 { 46 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 47 out_mbox_direct, false, NULL, 0, 48 out_mbox, out_mbox_size); 49 } 50 51 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 52 u8 opcode_mod, u32 in_mod) 53 { 54 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 55 false, NULL, 0, NULL, 0); 56 } 57 58 enum mlxsw_cmd_opcode { 59 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 60 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 61 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 62 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 63 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 64 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 65 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 66 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 67 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 68 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 69 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 70 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 71 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 72 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 73 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 74 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 75 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 76 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, 77 }; 78 79 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 80 { 81 switch (opcode) { 82 case MLXSW_CMD_OPCODE_QUERY_FW: 83 return "QUERY_FW"; 84 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 85 return "QUERY_BOARDINFO"; 86 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 87 return "QUERY_AQ_CAP"; 88 case MLXSW_CMD_OPCODE_MAP_FA: 89 return "MAP_FA"; 90 case MLXSW_CMD_OPCODE_UNMAP_FA: 91 return "UNMAP_FA"; 92 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 93 return "CONFIG_PROFILE"; 94 case MLXSW_CMD_OPCODE_ACCESS_REG: 95 return "ACCESS_REG"; 96 case MLXSW_CMD_OPCODE_SW2HW_DQ: 97 return "SW2HW_DQ"; 98 case MLXSW_CMD_OPCODE_HW2SW_DQ: 99 return "HW2SW_DQ"; 100 case MLXSW_CMD_OPCODE_2ERR_DQ: 101 return "2ERR_DQ"; 102 case MLXSW_CMD_OPCODE_QUERY_DQ: 103 return "QUERY_DQ"; 104 case MLXSW_CMD_OPCODE_SW2HW_CQ: 105 return "SW2HW_CQ"; 106 case MLXSW_CMD_OPCODE_HW2SW_CQ: 107 return "HW2SW_CQ"; 108 case MLXSW_CMD_OPCODE_QUERY_CQ: 109 return "QUERY_CQ"; 110 case MLXSW_CMD_OPCODE_SW2HW_EQ: 111 return "SW2HW_EQ"; 112 case MLXSW_CMD_OPCODE_HW2SW_EQ: 113 return "HW2SW_EQ"; 114 case MLXSW_CMD_OPCODE_QUERY_EQ: 115 return "QUERY_EQ"; 116 case MLXSW_CMD_OPCODE_QUERY_RESOURCES: 117 return "QUERY_RESOURCES"; 118 default: 119 return "*UNKNOWN*"; 120 } 121 } 122 123 enum mlxsw_cmd_status { 124 /* Command execution succeeded. */ 125 MLXSW_CMD_STATUS_OK = 0x00, 126 /* Internal error (e.g. bus error) occurred while processing command. */ 127 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 128 /* Operation/command not supported or opcode modifier not supported. */ 129 MLXSW_CMD_STATUS_BAD_OP = 0x02, 130 /* Parameter not supported, parameter out of range. */ 131 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 132 /* System was not enabled or bad system state. */ 133 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 134 /* Attempt to access reserved or unallocated resource, or resource in 135 * inappropriate ownership. 136 */ 137 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 138 /* Requested resource is currently executing a command. */ 139 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 140 /* Required capability exceeds device limits. */ 141 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 142 /* Resource is not in the appropriate state or ownership. */ 143 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 144 /* Index out of range (might be beyond table size or attempt to 145 * access a reserved resource). 146 */ 147 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 148 /* NVMEM checksum/CRC failed. */ 149 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 150 /* Device is currently running reset */ 151 MLXSW_CMD_STATUS_RUNNING_RESET = 0x26, 152 /* Bad management packet (silently discarded). */ 153 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 154 }; 155 156 static inline const char *mlxsw_cmd_status_str(u8 status) 157 { 158 switch (status) { 159 case MLXSW_CMD_STATUS_OK: 160 return "OK"; 161 case MLXSW_CMD_STATUS_INTERNAL_ERR: 162 return "INTERNAL_ERR"; 163 case MLXSW_CMD_STATUS_BAD_OP: 164 return "BAD_OP"; 165 case MLXSW_CMD_STATUS_BAD_PARAM: 166 return "BAD_PARAM"; 167 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 168 return "BAD_SYS_STATE"; 169 case MLXSW_CMD_STATUS_BAD_RESOURCE: 170 return "BAD_RESOURCE"; 171 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 172 return "RESOURCE_BUSY"; 173 case MLXSW_CMD_STATUS_EXCEED_LIM: 174 return "EXCEED_LIM"; 175 case MLXSW_CMD_STATUS_BAD_RES_STATE: 176 return "BAD_RES_STATE"; 177 case MLXSW_CMD_STATUS_BAD_INDEX: 178 return "BAD_INDEX"; 179 case MLXSW_CMD_STATUS_BAD_NVMEM: 180 return "BAD_NVMEM"; 181 case MLXSW_CMD_STATUS_RUNNING_RESET: 182 return "RUNNING_RESET"; 183 case MLXSW_CMD_STATUS_BAD_PKT: 184 return "BAD_PKT"; 185 default: 186 return "*UNKNOWN*"; 187 } 188 } 189 190 /* QUERY_FW - Query Firmware 191 * ------------------------- 192 * OpMod == 0, INMmod == 0 193 * ----------------------- 194 * The QUERY_FW command retrieves information related to firmware, command 195 * interface version and the amount of resources that should be allocated to 196 * the firmware. 197 */ 198 199 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 200 char *out_mbox) 201 { 202 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 203 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 204 } 205 206 /* cmd_mbox_query_fw_fw_pages 207 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 208 */ 209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 210 211 /* cmd_mbox_query_fw_fw_rev_major 212 * Firmware Revision - Major 213 */ 214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 215 216 /* cmd_mbox_query_fw_fw_rev_subminor 217 * Firmware Sub-minor version (Patch level) 218 */ 219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 220 221 /* cmd_mbox_query_fw_fw_rev_minor 222 * Firmware Revision - Minor 223 */ 224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 225 226 /* cmd_mbox_query_fw_core_clk 227 * Internal Clock Frequency (in MHz) 228 */ 229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 230 231 /* cmd_mbox_query_fw_cmd_interface_rev 232 * Command Interface Interpreter Revision ID. This number is bumped up 233 * every time a non-backward-compatible change is done for the command 234 * interface. The current cmd_interface_rev is 1. 235 */ 236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 237 238 /* cmd_mbox_query_fw_dt 239 * If set, Debug Trace is supported 240 */ 241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 242 243 /* cmd_mbox_query_fw_api_version 244 * Indicates the version of the API, to enable software querying 245 * for compatibility. The current api_version is 1. 246 */ 247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 248 249 /* cmd_mbox_query_fw_fw_hour 250 * Firmware timestamp - hour 251 */ 252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 253 254 /* cmd_mbox_query_fw_fw_minutes 255 * Firmware timestamp - minutes 256 */ 257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 258 259 /* cmd_mbox_query_fw_fw_seconds 260 * Firmware timestamp - seconds 261 */ 262 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 263 264 /* cmd_mbox_query_fw_fw_year 265 * Firmware timestamp - year 266 */ 267 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 268 269 /* cmd_mbox_query_fw_fw_month 270 * Firmware timestamp - month 271 */ 272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 273 274 /* cmd_mbox_query_fw_fw_day 275 * Firmware timestamp - day 276 */ 277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 278 279 /* cmd_mbox_query_fw_clr_int_base_offset 280 * Clear Interrupt register's offset from clr_int_bar register 281 * in PCI address space. 282 */ 283 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 284 285 /* cmd_mbox_query_fw_clr_int_bar 286 * PCI base address register (BAR) where clr_int register is located. 287 * 00 - BAR 0-1 (64 bit BAR) 288 */ 289 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 290 291 /* cmd_mbox_query_fw_error_buf_offset 292 * Read Only buffer for internal error reports of offset 293 * from error_buf_bar register in PCI address space). 294 */ 295 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 296 297 /* cmd_mbox_query_fw_error_buf_size 298 * Internal error buffer size in DWORDs 299 */ 300 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 301 302 /* cmd_mbox_query_fw_error_int_bar 303 * PCI base address register (BAR) where error buffer 304 * register is located. 305 * 00 - BAR 0-1 (64 bit BAR) 306 */ 307 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 308 309 /* cmd_mbox_query_fw_doorbell_page_offset 310 * Offset of the doorbell page 311 */ 312 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 313 314 /* cmd_mbox_query_fw_doorbell_page_bar 315 * PCI base address register (BAR) of the doorbell page 316 * 00 - BAR 0-1 (64 bit BAR) 317 */ 318 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 319 320 /* QUERY_BOARDINFO - Query Board Information 321 * ----------------------------------------- 322 * OpMod == 0 (N/A), INMmod == 0 (N/A) 323 * ----------------------------------- 324 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 325 */ 326 327 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 328 char *out_mbox) 329 { 330 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 331 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 332 } 333 334 /* cmd_mbox_boardinfo_intapin 335 * When PCIe interrupt messages are being used, this value is used for clearing 336 * an interrupt. When using MSI-X, this register is not used. 337 */ 338 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 339 340 /* cmd_mbox_boardinfo_vsd_vendor_id 341 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 342 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 343 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 344 * format and encoding as long as they use their assigned vsd_vendor_id. 345 */ 346 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 347 348 /* cmd_mbox_boardinfo_vsd 349 * Vendor Specific Data. The VSD string that is burnt to the Flash 350 * with the firmware. 351 */ 352 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 353 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 354 355 /* cmd_mbox_boardinfo_psid 356 * The PSID field is a 16-ascii (byte) character string which acts as 357 * the board ID. The PSID format is used in conjunction with 358 * Mellanox vsd_vendor_id (15B3h). 359 */ 360 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 361 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 362 363 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 364 * ----------------------------------------------------- 365 * OpMod == 0 (N/A), INMmod == 0 (N/A) 366 * ----------------------------------- 367 * The QUERY_AQ_CAP command returns the device asynchronous queues 368 * capabilities supported. 369 */ 370 371 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 372 char *out_mbox) 373 { 374 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 375 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 376 } 377 378 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 379 * Log (base 2) of max WQEs allowed on SDQ. 380 */ 381 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 382 383 /* cmd_mbox_query_aq_cap_max_num_sdqs 384 * Maximum number of SDQs. 385 */ 386 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 387 388 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 389 * Log (base 2) of max WQEs allowed on RDQ. 390 */ 391 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 392 393 /* cmd_mbox_query_aq_cap_max_num_rdqs 394 * Maximum number of RDQs. 395 */ 396 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 397 398 /* cmd_mbox_query_aq_cap_log_max_cq_sz 399 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. 400 */ 401 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 402 403 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz 404 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. 405 */ 406 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); 407 408 /* cmd_mbox_query_aq_cap_max_num_cqs 409 * Maximum number of CQs. 410 */ 411 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 412 413 /* cmd_mbox_query_aq_cap_log_max_eq_sz 414 * Log (base 2) of max EQEs allowed on EQ. 415 */ 416 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 417 418 /* cmd_mbox_query_aq_cap_max_num_eqs 419 * Maximum number of EQs. 420 */ 421 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 422 423 /* cmd_mbox_query_aq_cap_max_sg_sq 424 * The maximum S/G list elements in an DSQ. DSQ must not contain 425 * more S/G entries than indicated here. 426 */ 427 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 428 429 /* cmd_mbox_query_aq_cap_ 430 * The maximum S/G list elements in an DRQ. DRQ must not contain 431 * more S/G entries than indicated here. 432 */ 433 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 434 435 /* MAP_FA - Map Firmware Area 436 * -------------------------- 437 * OpMod == 0 (N/A), INMmod == Number of VPM entries 438 * ------------------------------------------------- 439 * The MAP_FA command passes physical pages to the switch. These pages 440 * are used to store the device firmware. MAP_FA can be executed multiple 441 * times until all the firmware area is mapped (the size that should be 442 * mapped is retrieved through the QUERY_FW command). All required pages 443 * must be mapped to finish the initialization phase. Physical memory 444 * passed in this command must be pinned. 445 */ 446 447 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 448 449 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 450 char *in_mbox, u32 vpm_entries_count) 451 { 452 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 453 0, vpm_entries_count, 454 in_mbox, MLXSW_CMD_MBOX_SIZE); 455 } 456 457 /* cmd_mbox_map_fa_pa 458 * Physical Address. 459 */ 460 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 461 462 /* cmd_mbox_map_fa_log2size 463 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 464 * that starts at PA_L/H. 465 */ 466 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 467 468 /* UNMAP_FA - Unmap Firmware Area 469 * ------------------------------ 470 * OpMod == 0 (N/A), INMmod == 0 (N/A) 471 * ----------------------------------- 472 * The UNMAP_FA command unload the firmware and unmaps all the 473 * firmware area. After this command is completed the device will not access 474 * the pages that were mapped to the firmware area. After executing UNMAP_FA 475 * command, software reset must be done prior to execution of MAP_FW command. 476 */ 477 478 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 479 { 480 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 481 } 482 483 /* QUERY_RESOURCES - Query chip resources 484 * -------------------------------------- 485 * OpMod == 0 (N/A) , INMmod is index 486 * ---------------------------------- 487 * The QUERY_RESOURCES command retrieves information related to chip resources 488 * by resource ID. Every command returns 32 entries. INmod is being use as base. 489 * for example, index 1 will return entries 32-63. When the tables end and there 490 * are no more sources in the table, will return resource id 0xFFF to indicate 491 * it. 492 */ 493 494 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff 495 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 496 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 497 498 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, 499 char *out_mbox, int index) 500 { 501 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES, 502 0, index, false, out_mbox, 503 MLXSW_CMD_MBOX_SIZE); 504 } 505 506 /* cmd_mbox_query_resource_id 507 * The resource id. 0xFFFF indicates table's end. 508 */ 509 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); 510 511 /* cmd_mbox_query_resource_data 512 * The resource 513 */ 514 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, 515 0x00, 0, 40, 0x8, 0, false); 516 517 /* CONFIG_PROFILE (Set) - Configure Switch Profile 518 * ------------------------------ 519 * OpMod == 1 (Set), INMmod == 0 (N/A) 520 * ----------------------------------- 521 * The CONFIG_PROFILE command sets the switch profile. The command can be 522 * executed on the device only once at startup in order to allocate and 523 * configure all switch resources and prepare it for operational mode. 524 * It is not possible to change the device profile after the chip is 525 * in operational mode. 526 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 527 * state therefore it is required to perform software reset to the device 528 * following an unsuccessful completion of the command. It is required 529 * to perform software reset to the device to change an existing profile. 530 */ 531 532 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 533 char *in_mbox) 534 { 535 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 536 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 537 } 538 539 /* cmd_mbox_config_profile_set_max_vepa_channels 540 * Capability bit. Setting a bit to 1 configures the profile 541 * according to the mailbox contents. 542 */ 543 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 544 545 /* cmd_mbox_config_profile_set_max_lag 546 * Capability bit. Setting a bit to 1 configures the profile 547 * according to the mailbox contents. 548 */ 549 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 550 551 /* cmd_mbox_config_profile_set_max_port_per_lag 552 * Capability bit. Setting a bit to 1 configures the profile 553 * according to the mailbox contents. 554 */ 555 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 556 557 /* cmd_mbox_config_profile_set_max_mid 558 * Capability bit. Setting a bit to 1 configures the profile 559 * according to the mailbox contents. 560 */ 561 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 562 563 /* cmd_mbox_config_profile_set_max_pgt 564 * Capability bit. Setting a bit to 1 configures the profile 565 * according to the mailbox contents. 566 */ 567 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 568 569 /* cmd_mbox_config_profile_set_max_system_port 570 * Capability bit. Setting a bit to 1 configures the profile 571 * according to the mailbox contents. 572 */ 573 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 574 575 /* cmd_mbox_config_profile_set_max_vlan_groups 576 * Capability bit. Setting a bit to 1 configures the profile 577 * according to the mailbox contents. 578 */ 579 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 580 581 /* cmd_mbox_config_profile_set_max_regions 582 * Capability bit. Setting a bit to 1 configures the profile 583 * according to the mailbox contents. 584 */ 585 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 586 587 /* cmd_mbox_config_profile_set_flood_mode 588 * Capability bit. Setting a bit to 1 configures the profile 589 * according to the mailbox contents. 590 */ 591 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 592 593 /* cmd_mbox_config_profile_set_max_flood_tables 594 * Capability bit. Setting a bit to 1 configures the profile 595 * according to the mailbox contents. 596 */ 597 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 598 599 /* cmd_mbox_config_profile_set_max_ib_mc 600 * Capability bit. Setting a bit to 1 configures the profile 601 * according to the mailbox contents. 602 */ 603 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 604 605 /* cmd_mbox_config_profile_set_max_pkey 606 * Capability bit. Setting a bit to 1 configures the profile 607 * according to the mailbox contents. 608 */ 609 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 610 611 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 612 * Capability bit. Setting a bit to 1 configures the profile 613 * according to the mailbox contents. 614 */ 615 MLXSW_ITEM32(cmd_mbox, config_profile, 616 set_adaptive_routing_group_cap, 0x0C, 14, 1); 617 618 /* cmd_mbox_config_profile_set_ar_sec 619 * Capability bit. Setting a bit to 1 configures the profile 620 * according to the mailbox contents. 621 */ 622 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 623 624 /* cmd_mbox_config_set_kvd_linear_size 625 * Capability bit. Setting a bit to 1 configures the profile 626 * according to the mailbox contents. 627 */ 628 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); 629 630 /* cmd_mbox_config_set_kvd_hash_single_size 631 * Capability bit. Setting a bit to 1 configures the profile 632 * according to the mailbox contents. 633 */ 634 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); 635 636 /* cmd_mbox_config_set_kvd_hash_double_size 637 * Capability bit. Setting a bit to 1 configures the profile 638 * according to the mailbox contents. 639 */ 640 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 641 642 /* cmd_mbox_config_set_cqe_version 643 * Capability bit. Setting a bit to 1 configures the profile 644 * according to the mailbox contents. 645 */ 646 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); 647 648 /* cmd_mbox_config_profile_max_vepa_channels 649 * Maximum number of VEPA channels per port (0 through 16) 650 * 0 - multi-channel VEPA is disabled 651 */ 652 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 653 654 /* cmd_mbox_config_profile_max_lag 655 * Maximum number of LAG IDs requested. 656 */ 657 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 658 659 /* cmd_mbox_config_profile_max_port_per_lag 660 * Maximum number of ports per LAG requested. 661 */ 662 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 663 664 /* cmd_mbox_config_profile_max_mid 665 * Maximum Multicast IDs. 666 * Multicast IDs are allocated from 0 to max_mid-1 667 */ 668 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 669 670 /* cmd_mbox_config_profile_max_pgt 671 * Maximum records in the Port Group Table per Switch Partition. 672 * Port Group Table indexes are from 0 to max_pgt-1 673 */ 674 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 675 676 /* cmd_mbox_config_profile_max_system_port 677 * The maximum number of system ports that can be allocated. 678 */ 679 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 680 681 /* cmd_mbox_config_profile_max_vlan_groups 682 * Maximum number VLAN Groups for VLAN binding. 683 */ 684 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 685 686 /* cmd_mbox_config_profile_max_regions 687 * Maximum number of TCAM Regions. 688 */ 689 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 690 691 /* cmd_mbox_config_profile_max_flood_tables 692 * Maximum number of single-entry flooding tables. Different flooding tables 693 * can be associated with different packet types. 694 */ 695 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 696 697 /* cmd_mbox_config_profile_max_vid_flood_tables 698 * Maximum number of per-vid flooding tables. Flooding tables are associated 699 * to the different packet types for the different switch partitions. 700 * Table size is 4K entries covering all VID space. 701 */ 702 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 703 704 /* cmd_mbox_config_profile_flood_mode 705 * Flooding mode to use. 706 * 0-2 - Backward compatible modes for SwitchX devices. 707 * 3 - Mixed mode, where: 708 * max_flood_tables indicates the number of single-entry tables. 709 * max_vid_flood_tables indicates the number of per-VID tables. 710 * max_fid_offset_flood_tables indicates the number of FID-offset tables. 711 * max_fid_flood_tables indicates the number of per-FID tables. 712 */ 713 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2); 714 715 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 716 * Maximum number of FID-offset flooding tables. 717 */ 718 MLXSW_ITEM32(cmd_mbox, config_profile, 719 max_fid_offset_flood_tables, 0x34, 24, 4); 720 721 /* cmd_mbox_config_profile_fid_offset_flood_table_size 722 * The size (number of entries) of each FID-offset flood table. 723 */ 724 MLXSW_ITEM32(cmd_mbox, config_profile, 725 fid_offset_flood_table_size, 0x34, 0, 16); 726 727 /* cmd_mbox_config_profile_max_fid_flood_tables 728 * Maximum number of per-FID flooding tables. 729 * 730 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 731 * FID value 4K and higher. 732 */ 733 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 734 735 /* cmd_mbox_config_profile_fid_flood_table_size 736 * The size (number of entries) of each per-FID table. 737 */ 738 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 739 740 /* cmd_mbox_config_profile_max_ib_mc 741 * Maximum number of multicast FDB records for InfiniBand 742 * FDB (in 512 chunks) per InfiniBand switch partition. 743 */ 744 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 745 746 /* cmd_mbox_config_profile_max_pkey 747 * Maximum per port PKEY table size (for PKEY enforcement) 748 */ 749 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 750 751 /* cmd_mbox_config_profile_ar_sec 752 * Primary/secondary capability 753 * Describes the number of adaptive routing sub-groups 754 * 0 - disable primary/secondary (single group) 755 * 1 - enable primary/secondary (2 sub-groups) 756 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 757 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 758 */ 759 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 760 761 /* cmd_mbox_config_profile_adaptive_routing_group_cap 762 * Adaptive Routing Group Capability. Indicates the number of AR groups 763 * supported. Note that when Primary/secondary is enabled, each 764 * primary/secondary couple consumes 2 adaptive routing entries. 765 */ 766 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 767 768 /* cmd_mbox_config_profile_arn 769 * Adaptive Routing Notification Enable 770 * Not supported in SwitchX, SwitchX-2 771 */ 772 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 773 774 /* cmd_mbox_config_kvd_linear_size 775 * KVD Linear Size 776 * Valid for Spectrum only 777 * Allowed values are 128*N where N=0 or higher 778 */ 779 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); 780 781 /* cmd_mbox_config_kvd_hash_single_size 782 * KVD Hash single-entries size 783 * Valid for Spectrum only 784 * Allowed values are 128*N where N=0 or higher 785 * Must be greater or equal to cap_min_kvd_hash_single_size 786 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 787 */ 788 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); 789 790 /* cmd_mbox_config_kvd_hash_double_size 791 * KVD Hash double-entries size (units of single-size entries) 792 * Valid for Spectrum only 793 * Allowed values are 128*N where N=0 or higher 794 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size 795 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 796 */ 797 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); 798 799 /* cmd_mbox_config_profile_swid_config_mask 800 * Modify Switch Partition Configuration mask. When set, the configu- 801 * ration value for the Switch Partition are taken from the mailbox. 802 * When clear, the current configuration values are used. 803 * Bit 0 - set type 804 * Bit 1 - properties 805 * Other - reserved 806 */ 807 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 808 0x60, 24, 8, 0x08, 0x00, false); 809 810 /* cmd_mbox_config_profile_swid_config_type 811 * Switch Partition type. 812 * 0000 - disabled (Switch Partition does not exist) 813 * 0001 - InfiniBand 814 * 0010 - Ethernet 815 * 1000 - router port (SwitchX-2 only) 816 * Other - reserved 817 */ 818 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 819 0x60, 20, 4, 0x08, 0x00, false); 820 821 /* cmd_mbox_config_profile_swid_config_properties 822 * Switch Partition properties. 823 */ 824 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 825 0x60, 0, 8, 0x08, 0x00, false); 826 827 /* cmd_mbox_config_profile_cqe_version 828 * CQE version: 829 * 0: CQE version is 0 830 * 1: CQE version is either 1 or 2 831 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. 832 */ 833 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); 834 835 /* ACCESS_REG - Access EMAD Supported Register 836 * ---------------------------------- 837 * OpMod == 0 (N/A), INMmod == 0 (N/A) 838 * ------------------------------------- 839 * The ACCESS_REG command supports accessing device registers. This access 840 * is mainly used for bootstrapping. 841 */ 842 843 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 844 bool reset_ok, 845 char *in_mbox, char *out_mbox) 846 { 847 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 848 0, 0, false, reset_ok, 849 in_mbox, MLXSW_CMD_MBOX_SIZE, 850 out_mbox, MLXSW_CMD_MBOX_SIZE); 851 } 852 853 /* SW2HW_DQ - Software to Hardware DQ 854 * ---------------------------------- 855 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 856 * INMmod == DQ number 857 * ---------------------------------------------- 858 * The SW2HW_DQ command transitions a descriptor queue from software to 859 * hardware ownership. The command enables posting WQEs and ringing DoorBells 860 * on the descriptor queue. 861 */ 862 863 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 864 char *in_mbox, u32 dq_number, 865 u8 opcode_mod) 866 { 867 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 868 opcode_mod, dq_number, 869 in_mbox, MLXSW_CMD_MBOX_SIZE); 870 } 871 872 enum { 873 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 874 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 875 }; 876 877 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 878 char *in_mbox, u32 dq_number) 879 { 880 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 881 MLXSW_CMD_OPCODE_MOD_SDQ); 882 } 883 884 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 885 char *in_mbox, u32 dq_number) 886 { 887 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 888 MLXSW_CMD_OPCODE_MOD_RDQ); 889 } 890 891 /* cmd_mbox_sw2hw_dq_cq 892 * Number of the CQ that this Descriptor Queue reports completions to. 893 */ 894 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 895 896 /* cmd_mbox_sw2hw_dq_sdq_tclass 897 * SDQ: CPU Egress TClass 898 * RDQ: Reserved 899 */ 900 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 901 902 /* cmd_mbox_sw2hw_dq_log2_dq_sz 903 * Log (base 2) of the Descriptor Queue size in 4KB pages. 904 */ 905 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 906 907 /* cmd_mbox_sw2hw_dq_pa 908 * Physical Address. 909 */ 910 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 911 912 /* HW2SW_DQ - Hardware to Software DQ 913 * ---------------------------------- 914 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 915 * INMmod == DQ number 916 * ---------------------------------------------- 917 * The HW2SW_DQ command transitions a descriptor queue from hardware to 918 * software ownership. Incoming packets on the DQ are silently discarded, 919 * SW should not post descriptors on nonoperational DQs. 920 */ 921 922 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 923 u32 dq_number, u8 opcode_mod) 924 { 925 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 926 opcode_mod, dq_number); 927 } 928 929 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 930 u32 dq_number) 931 { 932 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 933 MLXSW_CMD_OPCODE_MOD_SDQ); 934 } 935 936 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 937 u32 dq_number) 938 { 939 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 940 MLXSW_CMD_OPCODE_MOD_RDQ); 941 } 942 943 /* 2ERR_DQ - To Error DQ 944 * --------------------- 945 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 946 * INMmod == DQ number 947 * ---------------------------------------------- 948 * The 2ERR_DQ command transitions the DQ into the error state from the state 949 * in which it has been. While the command is executed, some in-process 950 * descriptors may complete. Once the DQ transitions into the error state, 951 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 952 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 953 * When the command is completed successfully, the DQ is already in 954 * the error state. 955 */ 956 957 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 958 u32 dq_number, u8 opcode_mod) 959 { 960 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 961 opcode_mod, dq_number); 962 } 963 964 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 965 u32 dq_number) 966 { 967 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 968 MLXSW_CMD_OPCODE_MOD_SDQ); 969 } 970 971 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 972 u32 dq_number) 973 { 974 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 975 MLXSW_CMD_OPCODE_MOD_RDQ); 976 } 977 978 /* QUERY_DQ - Query DQ 979 * --------------------- 980 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 981 * INMmod == DQ number 982 * ---------------------------------------------- 983 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 984 * 985 * Note: Output mailbox has the same format as SW2HW_DQ. 986 */ 987 988 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 989 char *out_mbox, u32 dq_number, 990 u8 opcode_mod) 991 { 992 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 993 opcode_mod, dq_number, false, 994 out_mbox, MLXSW_CMD_MBOX_SIZE); 995 } 996 997 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 998 char *out_mbox, u32 dq_number) 999 { 1000 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1001 MLXSW_CMD_OPCODE_MOD_SDQ); 1002 } 1003 1004 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 1005 char *out_mbox, u32 dq_number) 1006 { 1007 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1008 MLXSW_CMD_OPCODE_MOD_RDQ); 1009 } 1010 1011 /* SW2HW_CQ - Software to Hardware CQ 1012 * ---------------------------------- 1013 * OpMod == 0 (N/A), INMmod == CQ number 1014 * ------------------------------------- 1015 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 1016 * to hardware. The command takes the CQ context entry from the input mailbox 1017 * and stores it in the CQC in the ownership of the hardware. The command fails 1018 * if the requested CQC entry is already in the ownership of the hardware. 1019 */ 1020 1021 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 1022 char *in_mbox, u32 cq_number) 1023 { 1024 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 1025 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1026 } 1027 1028 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { 1029 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, 1030 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, 1031 }; 1032 1033 /* cmd_mbox_sw2hw_cq_cqe_ver 1034 * CQE Version. 1035 */ 1036 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); 1037 1038 /* cmd_mbox_sw2hw_cq_c_eqn 1039 * Event Queue this CQ reports completion events to. 1040 */ 1041 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 1042 1043 /* cmd_mbox_sw2hw_cq_st 1044 * Event delivery state machine 1045 * 0x0 - FIRED 1046 * 0x1 - ARMED (Request for Notification) 1047 */ 1048 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 1049 1050 /* cmd_mbox_sw2hw_cq_log_cq_size 1051 * Log (base 2) of the CQ size (in entries). 1052 */ 1053 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 1054 1055 /* cmd_mbox_sw2hw_cq_producer_counter 1056 * Producer Counter. The counter is incremented for each CQE that is 1057 * written by the HW to the CQ. 1058 * Maintained by HW (valid for the QUERY_CQ command only) 1059 */ 1060 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 1061 1062 /* cmd_mbox_sw2hw_cq_pa 1063 * Physical Address. 1064 */ 1065 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1066 1067 /* HW2SW_CQ - Hardware to Software CQ 1068 * ---------------------------------- 1069 * OpMod == 0 (N/A), INMmod == CQ number 1070 * ------------------------------------- 1071 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1072 * to software. The CQC entry is invalidated as a result of this command. 1073 */ 1074 1075 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1076 u32 cq_number) 1077 { 1078 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1079 0, cq_number); 1080 } 1081 1082 /* QUERY_CQ - Query CQ 1083 * ---------------------------------- 1084 * OpMod == 0 (N/A), INMmod == CQ number 1085 * ------------------------------------- 1086 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1087 * The command stores the snapshot in the output mailbox in the software format. 1088 * Note that the CQ context state and values are not affected by the QUERY_CQ 1089 * command. The QUERY_CQ command is for debug purposes only. 1090 * 1091 * Note: Output mailbox has the same format as SW2HW_CQ. 1092 */ 1093 1094 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1095 char *out_mbox, u32 cq_number) 1096 { 1097 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1098 0, cq_number, false, 1099 out_mbox, MLXSW_CMD_MBOX_SIZE); 1100 } 1101 1102 /* SW2HW_EQ - Software to Hardware EQ 1103 * ---------------------------------- 1104 * OpMod == 0 (N/A), INMmod == EQ number 1105 * ------------------------------------- 1106 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1107 * to hardware. The command takes the EQ context entry from the input mailbox 1108 * and stores it in the EQC in the ownership of the hardware. The command fails 1109 * if the requested EQC entry is already in the ownership of the hardware. 1110 */ 1111 1112 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1113 char *in_mbox, u32 eq_number) 1114 { 1115 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1116 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1117 } 1118 1119 /* cmd_mbox_sw2hw_eq_int_msix 1120 * When set, MSI-X cycles will be generated by this EQ. 1121 * When cleared, an interrupt will be generated by this EQ. 1122 */ 1123 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1124 1125 /* cmd_mbox_sw2hw_eq_st 1126 * Event delivery state machine 1127 * 0x0 - FIRED 1128 * 0x1 - ARMED (Request for Notification) 1129 * 0x11 - Always ARMED 1130 * other - reserved 1131 */ 1132 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1133 1134 /* cmd_mbox_sw2hw_eq_log_eq_size 1135 * Log (base 2) of the EQ size (in entries). 1136 */ 1137 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1138 1139 /* cmd_mbox_sw2hw_eq_producer_counter 1140 * Producer Counter. The counter is incremented for each EQE that is written 1141 * by the HW to the EQ. 1142 * Maintained by HW (valid for the QUERY_EQ command only) 1143 */ 1144 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1145 1146 /* cmd_mbox_sw2hw_eq_pa 1147 * Physical Address. 1148 */ 1149 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1150 1151 /* HW2SW_EQ - Hardware to Software EQ 1152 * ---------------------------------- 1153 * OpMod == 0 (N/A), INMmod == EQ number 1154 * ------------------------------------- 1155 */ 1156 1157 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1158 u32 eq_number) 1159 { 1160 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1161 0, eq_number); 1162 } 1163 1164 /* QUERY_EQ - Query EQ 1165 * ---------------------------------- 1166 * OpMod == 0 (N/A), INMmod == EQ number 1167 * ------------------------------------- 1168 * 1169 * Note: Output mailbox has the same format as SW2HW_EQ. 1170 */ 1171 1172 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1173 char *out_mbox, u32 eq_number) 1174 { 1175 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1176 0, eq_number, false, 1177 out_mbox, MLXSW_CMD_MBOX_SIZE); 1178 } 1179 1180 #endif 1181