1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_CMD_H 5 #define _MLXSW_CMD_H 6 7 #include "item.h" 8 9 #define MLXSW_CMD_MBOX_SIZE 4096 10 11 static inline char *mlxsw_cmd_mbox_alloc(void) 12 { 13 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 14 } 15 16 static inline void mlxsw_cmd_mbox_free(char *mbox) 17 { 18 kfree(mbox); 19 } 20 21 static inline void mlxsw_cmd_mbox_zero(char *mbox) 22 { 23 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 24 } 25 26 struct mlxsw_core; 27 28 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 29 u32 in_mod, bool out_mbox_direct, bool reset_ok, 30 char *in_mbox, size_t in_mbox_size, 31 char *out_mbox, size_t out_mbox_size); 32 33 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 34 u8 opcode_mod, u32 in_mod, char *in_mbox, 35 size_t in_mbox_size) 36 { 37 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 38 false, in_mbox, in_mbox_size, NULL, 0); 39 } 40 41 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 42 u8 opcode_mod, u32 in_mod, 43 bool out_mbox_direct, 44 char *out_mbox, size_t out_mbox_size) 45 { 46 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 47 out_mbox_direct, false, NULL, 0, 48 out_mbox, out_mbox_size); 49 } 50 51 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 52 u8 opcode_mod, u32 in_mod) 53 { 54 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 55 false, NULL, 0, NULL, 0); 56 } 57 58 enum mlxsw_cmd_opcode { 59 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 60 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 61 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 62 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 63 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 64 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 65 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 66 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 67 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 68 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 69 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 70 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 71 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 72 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 73 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 74 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 75 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 76 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, 77 }; 78 79 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 80 { 81 switch (opcode) { 82 case MLXSW_CMD_OPCODE_QUERY_FW: 83 return "QUERY_FW"; 84 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 85 return "QUERY_BOARDINFO"; 86 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 87 return "QUERY_AQ_CAP"; 88 case MLXSW_CMD_OPCODE_MAP_FA: 89 return "MAP_FA"; 90 case MLXSW_CMD_OPCODE_UNMAP_FA: 91 return "UNMAP_FA"; 92 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 93 return "CONFIG_PROFILE"; 94 case MLXSW_CMD_OPCODE_ACCESS_REG: 95 return "ACCESS_REG"; 96 case MLXSW_CMD_OPCODE_SW2HW_DQ: 97 return "SW2HW_DQ"; 98 case MLXSW_CMD_OPCODE_HW2SW_DQ: 99 return "HW2SW_DQ"; 100 case MLXSW_CMD_OPCODE_2ERR_DQ: 101 return "2ERR_DQ"; 102 case MLXSW_CMD_OPCODE_QUERY_DQ: 103 return "QUERY_DQ"; 104 case MLXSW_CMD_OPCODE_SW2HW_CQ: 105 return "SW2HW_CQ"; 106 case MLXSW_CMD_OPCODE_HW2SW_CQ: 107 return "HW2SW_CQ"; 108 case MLXSW_CMD_OPCODE_QUERY_CQ: 109 return "QUERY_CQ"; 110 case MLXSW_CMD_OPCODE_SW2HW_EQ: 111 return "SW2HW_EQ"; 112 case MLXSW_CMD_OPCODE_HW2SW_EQ: 113 return "HW2SW_EQ"; 114 case MLXSW_CMD_OPCODE_QUERY_EQ: 115 return "QUERY_EQ"; 116 case MLXSW_CMD_OPCODE_QUERY_RESOURCES: 117 return "QUERY_RESOURCES"; 118 default: 119 return "*UNKNOWN*"; 120 } 121 } 122 123 enum mlxsw_cmd_status { 124 /* Command execution succeeded. */ 125 MLXSW_CMD_STATUS_OK = 0x00, 126 /* Internal error (e.g. bus error) occurred while processing command. */ 127 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 128 /* Operation/command not supported or opcode modifier not supported. */ 129 MLXSW_CMD_STATUS_BAD_OP = 0x02, 130 /* Parameter not supported, parameter out of range. */ 131 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 132 /* System was not enabled or bad system state. */ 133 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 134 /* Attempt to access reserved or unallocated resource, or resource in 135 * inappropriate ownership. 136 */ 137 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 138 /* Requested resource is currently executing a command. */ 139 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 140 /* Required capability exceeds device limits. */ 141 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 142 /* Resource is not in the appropriate state or ownership. */ 143 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 144 /* Index out of range (might be beyond table size or attempt to 145 * access a reserved resource). 146 */ 147 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 148 /* NVMEM checksum/CRC failed. */ 149 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 150 /* Device is currently running reset */ 151 MLXSW_CMD_STATUS_RUNNING_RESET = 0x26, 152 /* Bad management packet (silently discarded). */ 153 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 154 }; 155 156 static inline const char *mlxsw_cmd_status_str(u8 status) 157 { 158 switch (status) { 159 case MLXSW_CMD_STATUS_OK: 160 return "OK"; 161 case MLXSW_CMD_STATUS_INTERNAL_ERR: 162 return "INTERNAL_ERR"; 163 case MLXSW_CMD_STATUS_BAD_OP: 164 return "BAD_OP"; 165 case MLXSW_CMD_STATUS_BAD_PARAM: 166 return "BAD_PARAM"; 167 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 168 return "BAD_SYS_STATE"; 169 case MLXSW_CMD_STATUS_BAD_RESOURCE: 170 return "BAD_RESOURCE"; 171 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 172 return "RESOURCE_BUSY"; 173 case MLXSW_CMD_STATUS_EXCEED_LIM: 174 return "EXCEED_LIM"; 175 case MLXSW_CMD_STATUS_BAD_RES_STATE: 176 return "BAD_RES_STATE"; 177 case MLXSW_CMD_STATUS_BAD_INDEX: 178 return "BAD_INDEX"; 179 case MLXSW_CMD_STATUS_BAD_NVMEM: 180 return "BAD_NVMEM"; 181 case MLXSW_CMD_STATUS_RUNNING_RESET: 182 return "RUNNING_RESET"; 183 case MLXSW_CMD_STATUS_BAD_PKT: 184 return "BAD_PKT"; 185 default: 186 return "*UNKNOWN*"; 187 } 188 } 189 190 /* QUERY_FW - Query Firmware 191 * ------------------------- 192 * OpMod == 0, INMmod == 0 193 * ----------------------- 194 * The QUERY_FW command retrieves information related to firmware, command 195 * interface version and the amount of resources that should be allocated to 196 * the firmware. 197 */ 198 199 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 200 char *out_mbox) 201 { 202 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 203 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 204 } 205 206 /* cmd_mbox_query_fw_fw_pages 207 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 208 */ 209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 210 211 /* cmd_mbox_query_fw_fw_rev_major 212 * Firmware Revision - Major 213 */ 214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 215 216 /* cmd_mbox_query_fw_fw_rev_subminor 217 * Firmware Sub-minor version (Patch level) 218 */ 219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 220 221 /* cmd_mbox_query_fw_fw_rev_minor 222 * Firmware Revision - Minor 223 */ 224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 225 226 /* cmd_mbox_query_fw_core_clk 227 * Internal Clock Frequency (in MHz) 228 */ 229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 230 231 /* cmd_mbox_query_fw_cmd_interface_rev 232 * Command Interface Interpreter Revision ID. This number is bumped up 233 * every time a non-backward-compatible change is done for the command 234 * interface. The current cmd_interface_rev is 1. 235 */ 236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 237 238 /* cmd_mbox_query_fw_dt 239 * If set, Debug Trace is supported 240 */ 241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 242 243 /* cmd_mbox_query_fw_api_version 244 * Indicates the version of the API, to enable software querying 245 * for compatibility. The current api_version is 1. 246 */ 247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 248 249 /* cmd_mbox_query_fw_fw_hour 250 * Firmware timestamp - hour 251 */ 252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 253 254 /* cmd_mbox_query_fw_fw_minutes 255 * Firmware timestamp - minutes 256 */ 257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 258 259 /* cmd_mbox_query_fw_fw_seconds 260 * Firmware timestamp - seconds 261 */ 262 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 263 264 /* cmd_mbox_query_fw_fw_year 265 * Firmware timestamp - year 266 */ 267 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 268 269 /* cmd_mbox_query_fw_fw_month 270 * Firmware timestamp - month 271 */ 272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 273 274 /* cmd_mbox_query_fw_fw_day 275 * Firmware timestamp - day 276 */ 277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 278 279 /* cmd_mbox_query_fw_clr_int_base_offset 280 * Clear Interrupt register's offset from clr_int_bar register 281 * in PCI address space. 282 */ 283 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 284 285 /* cmd_mbox_query_fw_clr_int_bar 286 * PCI base address register (BAR) where clr_int register is located. 287 * 00 - BAR 0-1 (64 bit BAR) 288 */ 289 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 290 291 /* cmd_mbox_query_fw_error_buf_offset 292 * Read Only buffer for internal error reports of offset 293 * from error_buf_bar register in PCI address space). 294 */ 295 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 296 297 /* cmd_mbox_query_fw_error_buf_size 298 * Internal error buffer size in DWORDs 299 */ 300 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 301 302 /* cmd_mbox_query_fw_error_int_bar 303 * PCI base address register (BAR) where error buffer 304 * register is located. 305 * 00 - BAR 0-1 (64 bit BAR) 306 */ 307 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 308 309 /* cmd_mbox_query_fw_doorbell_page_offset 310 * Offset of the doorbell page 311 */ 312 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 313 314 /* cmd_mbox_query_fw_doorbell_page_bar 315 * PCI base address register (BAR) of the doorbell page 316 * 00 - BAR 0-1 (64 bit BAR) 317 */ 318 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 319 320 /* cmd_mbox_query_fw_free_running_clock_offset 321 * The offset of the free running clock page 322 */ 323 MLXSW_ITEM64(cmd_mbox, query_fw, free_running_clock_offset, 0x50, 0, 64); 324 325 /* cmd_mbox_query_fw_fr_rn_clk_bar 326 * PCI base address register (BAR) of the free running clock page 327 * 0: BAR 0 328 * 1: 64 bit BAR 329 */ 330 MLXSW_ITEM32(cmd_mbox, query_fw, fr_rn_clk_bar, 0x58, 30, 2); 331 332 /* QUERY_BOARDINFO - Query Board Information 333 * ----------------------------------------- 334 * OpMod == 0 (N/A), INMmod == 0 (N/A) 335 * ----------------------------------- 336 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 337 */ 338 339 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 340 char *out_mbox) 341 { 342 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 343 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 344 } 345 346 /* cmd_mbox_xm_num_local_ports 347 * Number of local_ports connected to the xm. 348 * Each local port is a 4x 349 * Spectrum-2/3: 25G 350 * Spectrum-4: 50G 351 */ 352 MLXSW_ITEM32(cmd_mbox, boardinfo, xm_num_local_ports, 0x00, 4, 3); 353 354 /* cmd_mbox_xm_exists 355 * An XM (eXtanded Mezanine, e.g. used for the XLT) is connected on the board. 356 */ 357 MLXSW_ITEM32(cmd_mbox, boardinfo, xm_exists, 0x00, 0, 1); 358 359 /* cmd_mbox_xm_local_port_entry 360 */ 361 MLXSW_ITEM_BIT_ARRAY(cmd_mbox, boardinfo, xm_local_port_entry, 0x04, 4, 8); 362 363 /* cmd_mbox_boardinfo_intapin 364 * When PCIe interrupt messages are being used, this value is used for clearing 365 * an interrupt. When using MSI-X, this register is not used. 366 */ 367 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 368 369 /* cmd_mbox_boardinfo_vsd_vendor_id 370 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 371 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 372 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 373 * format and encoding as long as they use their assigned vsd_vendor_id. 374 */ 375 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 376 377 /* cmd_mbox_boardinfo_vsd 378 * Vendor Specific Data. The VSD string that is burnt to the Flash 379 * with the firmware. 380 */ 381 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 382 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 383 384 /* cmd_mbox_boardinfo_psid 385 * The PSID field is a 16-ascii (byte) character string which acts as 386 * the board ID. The PSID format is used in conjunction with 387 * Mellanox vsd_vendor_id (15B3h). 388 */ 389 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 390 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 391 392 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 393 * ----------------------------------------------------- 394 * OpMod == 0 (N/A), INMmod == 0 (N/A) 395 * ----------------------------------- 396 * The QUERY_AQ_CAP command returns the device asynchronous queues 397 * capabilities supported. 398 */ 399 400 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 401 char *out_mbox) 402 { 403 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 404 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 405 } 406 407 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 408 * Log (base 2) of max WQEs allowed on SDQ. 409 */ 410 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 411 412 /* cmd_mbox_query_aq_cap_max_num_sdqs 413 * Maximum number of SDQs. 414 */ 415 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 416 417 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 418 * Log (base 2) of max WQEs allowed on RDQ. 419 */ 420 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 421 422 /* cmd_mbox_query_aq_cap_max_num_rdqs 423 * Maximum number of RDQs. 424 */ 425 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 426 427 /* cmd_mbox_query_aq_cap_log_max_cq_sz 428 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. 429 */ 430 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 431 432 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz 433 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. 434 */ 435 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); 436 437 /* cmd_mbox_query_aq_cap_max_num_cqs 438 * Maximum number of CQs. 439 */ 440 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 441 442 /* cmd_mbox_query_aq_cap_log_max_eq_sz 443 * Log (base 2) of max EQEs allowed on EQ. 444 */ 445 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 446 447 /* cmd_mbox_query_aq_cap_max_num_eqs 448 * Maximum number of EQs. 449 */ 450 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 451 452 /* cmd_mbox_query_aq_cap_max_sg_sq 453 * The maximum S/G list elements in an DSQ. DSQ must not contain 454 * more S/G entries than indicated here. 455 */ 456 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 457 458 /* cmd_mbox_query_aq_cap_ 459 * The maximum S/G list elements in an DRQ. DRQ must not contain 460 * more S/G entries than indicated here. 461 */ 462 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 463 464 /* MAP_FA - Map Firmware Area 465 * -------------------------- 466 * OpMod == 0 (N/A), INMmod == Number of VPM entries 467 * ------------------------------------------------- 468 * The MAP_FA command passes physical pages to the switch. These pages 469 * are used to store the device firmware. MAP_FA can be executed multiple 470 * times until all the firmware area is mapped (the size that should be 471 * mapped is retrieved through the QUERY_FW command). All required pages 472 * must be mapped to finish the initialization phase. Physical memory 473 * passed in this command must be pinned. 474 */ 475 476 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 477 478 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 479 char *in_mbox, u32 vpm_entries_count) 480 { 481 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 482 0, vpm_entries_count, 483 in_mbox, MLXSW_CMD_MBOX_SIZE); 484 } 485 486 /* cmd_mbox_map_fa_pa 487 * Physical Address. 488 */ 489 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 490 491 /* cmd_mbox_map_fa_log2size 492 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 493 * that starts at PA_L/H. 494 */ 495 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 496 497 /* UNMAP_FA - Unmap Firmware Area 498 * ------------------------------ 499 * OpMod == 0 (N/A), INMmod == 0 (N/A) 500 * ----------------------------------- 501 * The UNMAP_FA command unload the firmware and unmaps all the 502 * firmware area. After this command is completed the device will not access 503 * the pages that were mapped to the firmware area. After executing UNMAP_FA 504 * command, software reset must be done prior to execution of MAP_FW command. 505 */ 506 507 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 508 { 509 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 510 } 511 512 /* QUERY_RESOURCES - Query chip resources 513 * -------------------------------------- 514 * OpMod == 0 (N/A) , INMmod is index 515 * ---------------------------------- 516 * The QUERY_RESOURCES command retrieves information related to chip resources 517 * by resource ID. Every command returns 32 entries. INmod is being use as base. 518 * for example, index 1 will return entries 32-63. When the tables end and there 519 * are no more sources in the table, will return resource id 0xFFF to indicate 520 * it. 521 */ 522 523 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff 524 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 525 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 526 527 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, 528 char *out_mbox, int index) 529 { 530 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES, 531 0, index, false, out_mbox, 532 MLXSW_CMD_MBOX_SIZE); 533 } 534 535 /* cmd_mbox_query_resource_id 536 * The resource id. 0xFFFF indicates table's end. 537 */ 538 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); 539 540 /* cmd_mbox_query_resource_data 541 * The resource 542 */ 543 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, 544 0x00, 0, 40, 0x8, 0, false); 545 546 /* CONFIG_PROFILE (Set) - Configure Switch Profile 547 * ------------------------------ 548 * OpMod == 1 (Set), INMmod == 0 (N/A) 549 * ----------------------------------- 550 * The CONFIG_PROFILE command sets the switch profile. The command can be 551 * executed on the device only once at startup in order to allocate and 552 * configure all switch resources and prepare it for operational mode. 553 * It is not possible to change the device profile after the chip is 554 * in operational mode. 555 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 556 * state therefore it is required to perform software reset to the device 557 * following an unsuccessful completion of the command. It is required 558 * to perform software reset to the device to change an existing profile. 559 */ 560 561 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 562 char *in_mbox) 563 { 564 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 565 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 566 } 567 568 /* cmd_mbox_config_profile_set_max_vepa_channels 569 * Capability bit. Setting a bit to 1 configures the profile 570 * according to the mailbox contents. 571 */ 572 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 573 574 /* cmd_mbox_config_profile_set_max_lag 575 * Capability bit. Setting a bit to 1 configures the profile 576 * according to the mailbox contents. 577 */ 578 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 579 580 /* cmd_mbox_config_profile_set_max_port_per_lag 581 * Capability bit. Setting a bit to 1 configures the profile 582 * according to the mailbox contents. 583 */ 584 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 585 586 /* cmd_mbox_config_profile_set_max_mid 587 * Capability bit. Setting a bit to 1 configures the profile 588 * according to the mailbox contents. 589 */ 590 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 591 592 /* cmd_mbox_config_profile_set_max_pgt 593 * Capability bit. Setting a bit to 1 configures the profile 594 * according to the mailbox contents. 595 */ 596 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 597 598 /* cmd_mbox_config_profile_set_max_system_port 599 * Capability bit. Setting a bit to 1 configures the profile 600 * according to the mailbox contents. 601 */ 602 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 603 604 /* cmd_mbox_config_profile_set_max_vlan_groups 605 * Capability bit. Setting a bit to 1 configures the profile 606 * according to the mailbox contents. 607 */ 608 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 609 610 /* cmd_mbox_config_profile_set_max_regions 611 * Capability bit. Setting a bit to 1 configures the profile 612 * according to the mailbox contents. 613 */ 614 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 615 616 /* cmd_mbox_config_profile_set_flood_mode 617 * Capability bit. Setting a bit to 1 configures the profile 618 * according to the mailbox contents. 619 */ 620 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 621 622 /* cmd_mbox_config_profile_set_max_flood_tables 623 * Capability bit. Setting a bit to 1 configures the profile 624 * according to the mailbox contents. 625 */ 626 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 627 628 /* cmd_mbox_config_profile_set_max_ib_mc 629 * Capability bit. Setting a bit to 1 configures the profile 630 * according to the mailbox contents. 631 */ 632 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 633 634 /* cmd_mbox_config_profile_set_max_pkey 635 * Capability bit. Setting a bit to 1 configures the profile 636 * according to the mailbox contents. 637 */ 638 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 639 640 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 641 * Capability bit. Setting a bit to 1 configures the profile 642 * according to the mailbox contents. 643 */ 644 MLXSW_ITEM32(cmd_mbox, config_profile, 645 set_adaptive_routing_group_cap, 0x0C, 14, 1); 646 647 /* cmd_mbox_config_profile_set_ar_sec 648 * Capability bit. Setting a bit to 1 configures the profile 649 * according to the mailbox contents. 650 */ 651 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 652 653 /* cmd_mbox_config_set_kvd_linear_size 654 * Capability bit. Setting a bit to 1 configures the profile 655 * according to the mailbox contents. 656 */ 657 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); 658 659 /* cmd_mbox_config_set_kvd_hash_single_size 660 * Capability bit. Setting a bit to 1 configures the profile 661 * according to the mailbox contents. 662 */ 663 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); 664 665 /* cmd_mbox_config_set_kvd_hash_double_size 666 * Capability bit. Setting a bit to 1 configures the profile 667 * according to the mailbox contents. 668 */ 669 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 670 671 /* cmd_mbox_config_set_cqe_version 672 * Capability bit. Setting a bit to 1 configures the profile 673 * according to the mailbox contents. 674 */ 675 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); 676 677 /* cmd_mbox_config_set_kvh_xlt_cache_mode 678 * Capability bit. Setting a bit to 1 configures the profile 679 * according to the mailbox contents. 680 */ 681 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvh_xlt_cache_mode, 0x08, 3, 1); 682 683 /* cmd_mbox_config_profile_max_vepa_channels 684 * Maximum number of VEPA channels per port (0 through 16) 685 * 0 - multi-channel VEPA is disabled 686 */ 687 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 688 689 /* cmd_mbox_config_profile_max_lag 690 * Maximum number of LAG IDs requested. 691 */ 692 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 693 694 /* cmd_mbox_config_profile_max_port_per_lag 695 * Maximum number of ports per LAG requested. 696 */ 697 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 698 699 /* cmd_mbox_config_profile_max_mid 700 * Maximum Multicast IDs. 701 * Multicast IDs are allocated from 0 to max_mid-1 702 */ 703 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 704 705 /* cmd_mbox_config_profile_max_pgt 706 * Maximum records in the Port Group Table per Switch Partition. 707 * Port Group Table indexes are from 0 to max_pgt-1 708 */ 709 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 710 711 /* cmd_mbox_config_profile_max_system_port 712 * The maximum number of system ports that can be allocated. 713 */ 714 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 715 716 /* cmd_mbox_config_profile_max_vlan_groups 717 * Maximum number VLAN Groups for VLAN binding. 718 */ 719 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 720 721 /* cmd_mbox_config_profile_max_regions 722 * Maximum number of TCAM Regions. 723 */ 724 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 725 726 /* cmd_mbox_config_profile_max_flood_tables 727 * Maximum number of single-entry flooding tables. Different flooding tables 728 * can be associated with different packet types. 729 */ 730 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 731 732 /* cmd_mbox_config_profile_max_vid_flood_tables 733 * Maximum number of per-vid flooding tables. Flooding tables are associated 734 * to the different packet types for the different switch partitions. 735 * Table size is 4K entries covering all VID space. 736 */ 737 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 738 739 /* cmd_mbox_config_profile_flood_mode 740 * Flooding mode to use. 741 * 0-2 - Backward compatible modes for SwitchX devices. 742 * 3 - Mixed mode, where: 743 * max_flood_tables indicates the number of single-entry tables. 744 * max_vid_flood_tables indicates the number of per-VID tables. 745 * max_fid_offset_flood_tables indicates the number of FID-offset tables. 746 * max_fid_flood_tables indicates the number of per-FID tables. 747 */ 748 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2); 749 750 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 751 * Maximum number of FID-offset flooding tables. 752 */ 753 MLXSW_ITEM32(cmd_mbox, config_profile, 754 max_fid_offset_flood_tables, 0x34, 24, 4); 755 756 /* cmd_mbox_config_profile_fid_offset_flood_table_size 757 * The size (number of entries) of each FID-offset flood table. 758 */ 759 MLXSW_ITEM32(cmd_mbox, config_profile, 760 fid_offset_flood_table_size, 0x34, 0, 16); 761 762 /* cmd_mbox_config_profile_max_fid_flood_tables 763 * Maximum number of per-FID flooding tables. 764 * 765 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 766 * FID value 4K and higher. 767 */ 768 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 769 770 /* cmd_mbox_config_profile_fid_flood_table_size 771 * The size (number of entries) of each per-FID table. 772 */ 773 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 774 775 /* cmd_mbox_config_profile_max_ib_mc 776 * Maximum number of multicast FDB records for InfiniBand 777 * FDB (in 512 chunks) per InfiniBand switch partition. 778 */ 779 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 780 781 /* cmd_mbox_config_profile_max_pkey 782 * Maximum per port PKEY table size (for PKEY enforcement) 783 */ 784 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 785 786 /* cmd_mbox_config_profile_ar_sec 787 * Primary/secondary capability 788 * Describes the number of adaptive routing sub-groups 789 * 0 - disable primary/secondary (single group) 790 * 1 - enable primary/secondary (2 sub-groups) 791 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 792 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 793 */ 794 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 795 796 /* cmd_mbox_config_profile_adaptive_routing_group_cap 797 * Adaptive Routing Group Capability. Indicates the number of AR groups 798 * supported. Note that when Primary/secondary is enabled, each 799 * primary/secondary couple consumes 2 adaptive routing entries. 800 */ 801 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 802 803 /* cmd_mbox_config_profile_arn 804 * Adaptive Routing Notification Enable 805 * Not supported in SwitchX, SwitchX-2 806 */ 807 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 808 809 /* cmd_mbox_config_profile_kvh_xlt_cache_mode 810 * KVH XLT cache mode: 811 * 0 - XLT can use all KVH as best-effort 812 * 1 - XLT cache uses 1/2 KVH 813 */ 814 MLXSW_ITEM32(cmd_mbox, config_profile, kvh_xlt_cache_mode, 0x50, 8, 4); 815 816 /* cmd_mbox_config_kvd_linear_size 817 * KVD Linear Size 818 * Valid for Spectrum only 819 * Allowed values are 128*N where N=0 or higher 820 */ 821 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); 822 823 /* cmd_mbox_config_kvd_hash_single_size 824 * KVD Hash single-entries size 825 * Valid for Spectrum only 826 * Allowed values are 128*N where N=0 or higher 827 * Must be greater or equal to cap_min_kvd_hash_single_size 828 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 829 */ 830 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); 831 832 /* cmd_mbox_config_kvd_hash_double_size 833 * KVD Hash double-entries size (units of single-size entries) 834 * Valid for Spectrum only 835 * Allowed values are 128*N where N=0 or higher 836 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size 837 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 838 */ 839 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); 840 841 /* cmd_mbox_config_profile_swid_config_mask 842 * Modify Switch Partition Configuration mask. When set, the configu- 843 * ration value for the Switch Partition are taken from the mailbox. 844 * When clear, the current configuration values are used. 845 * Bit 0 - set type 846 * Bit 1 - properties 847 * Other - reserved 848 */ 849 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 850 0x60, 24, 8, 0x08, 0x00, false); 851 852 /* cmd_mbox_config_profile_swid_config_type 853 * Switch Partition type. 854 * 0000 - disabled (Switch Partition does not exist) 855 * 0001 - InfiniBand 856 * 0010 - Ethernet 857 * 1000 - router port (SwitchX-2 only) 858 * Other - reserved 859 */ 860 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 861 0x60, 20, 4, 0x08, 0x00, false); 862 863 /* cmd_mbox_config_profile_swid_config_properties 864 * Switch Partition properties. 865 */ 866 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 867 0x60, 0, 8, 0x08, 0x00, false); 868 869 /* cmd_mbox_config_profile_cqe_version 870 * CQE version: 871 * 0: CQE version is 0 872 * 1: CQE version is either 1 or 2 873 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. 874 */ 875 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); 876 877 /* ACCESS_REG - Access EMAD Supported Register 878 * ---------------------------------- 879 * OpMod == 0 (N/A), INMmod == 0 (N/A) 880 * ------------------------------------- 881 * The ACCESS_REG command supports accessing device registers. This access 882 * is mainly used for bootstrapping. 883 */ 884 885 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 886 bool reset_ok, 887 char *in_mbox, char *out_mbox) 888 { 889 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 890 0, 0, false, reset_ok, 891 in_mbox, MLXSW_CMD_MBOX_SIZE, 892 out_mbox, MLXSW_CMD_MBOX_SIZE); 893 } 894 895 /* SW2HW_DQ - Software to Hardware DQ 896 * ---------------------------------- 897 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 898 * INMmod == DQ number 899 * ---------------------------------------------- 900 * The SW2HW_DQ command transitions a descriptor queue from software to 901 * hardware ownership. The command enables posting WQEs and ringing DoorBells 902 * on the descriptor queue. 903 */ 904 905 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 906 char *in_mbox, u32 dq_number, 907 u8 opcode_mod) 908 { 909 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 910 opcode_mod, dq_number, 911 in_mbox, MLXSW_CMD_MBOX_SIZE); 912 } 913 914 enum { 915 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 916 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 917 }; 918 919 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 920 char *in_mbox, u32 dq_number) 921 { 922 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 923 MLXSW_CMD_OPCODE_MOD_SDQ); 924 } 925 926 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 927 char *in_mbox, u32 dq_number) 928 { 929 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 930 MLXSW_CMD_OPCODE_MOD_RDQ); 931 } 932 933 /* cmd_mbox_sw2hw_dq_cq 934 * Number of the CQ that this Descriptor Queue reports completions to. 935 */ 936 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 937 938 /* cmd_mbox_sw2hw_dq_sdq_tclass 939 * SDQ: CPU Egress TClass 940 * RDQ: Reserved 941 */ 942 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 943 944 /* cmd_mbox_sw2hw_dq_log2_dq_sz 945 * Log (base 2) of the Descriptor Queue size in 4KB pages. 946 */ 947 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 948 949 /* cmd_mbox_sw2hw_dq_pa 950 * Physical Address. 951 */ 952 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 953 954 /* HW2SW_DQ - Hardware to Software DQ 955 * ---------------------------------- 956 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 957 * INMmod == DQ number 958 * ---------------------------------------------- 959 * The HW2SW_DQ command transitions a descriptor queue from hardware to 960 * software ownership. Incoming packets on the DQ are silently discarded, 961 * SW should not post descriptors on nonoperational DQs. 962 */ 963 964 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 965 u32 dq_number, u8 opcode_mod) 966 { 967 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 968 opcode_mod, dq_number); 969 } 970 971 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 972 u32 dq_number) 973 { 974 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 975 MLXSW_CMD_OPCODE_MOD_SDQ); 976 } 977 978 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 979 u32 dq_number) 980 { 981 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 982 MLXSW_CMD_OPCODE_MOD_RDQ); 983 } 984 985 /* 2ERR_DQ - To Error DQ 986 * --------------------- 987 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 988 * INMmod == DQ number 989 * ---------------------------------------------- 990 * The 2ERR_DQ command transitions the DQ into the error state from the state 991 * in which it has been. While the command is executed, some in-process 992 * descriptors may complete. Once the DQ transitions into the error state, 993 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 994 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 995 * When the command is completed successfully, the DQ is already in 996 * the error state. 997 */ 998 999 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 1000 u32 dq_number, u8 opcode_mod) 1001 { 1002 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1003 opcode_mod, dq_number); 1004 } 1005 1006 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 1007 u32 dq_number) 1008 { 1009 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1010 MLXSW_CMD_OPCODE_MOD_SDQ); 1011 } 1012 1013 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 1014 u32 dq_number) 1015 { 1016 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1017 MLXSW_CMD_OPCODE_MOD_RDQ); 1018 } 1019 1020 /* QUERY_DQ - Query DQ 1021 * --------------------- 1022 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1023 * INMmod == DQ number 1024 * ---------------------------------------------- 1025 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 1026 * 1027 * Note: Output mailbox has the same format as SW2HW_DQ. 1028 */ 1029 1030 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 1031 char *out_mbox, u32 dq_number, 1032 u8 opcode_mod) 1033 { 1034 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1035 opcode_mod, dq_number, false, 1036 out_mbox, MLXSW_CMD_MBOX_SIZE); 1037 } 1038 1039 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 1040 char *out_mbox, u32 dq_number) 1041 { 1042 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1043 MLXSW_CMD_OPCODE_MOD_SDQ); 1044 } 1045 1046 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 1047 char *out_mbox, u32 dq_number) 1048 { 1049 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1050 MLXSW_CMD_OPCODE_MOD_RDQ); 1051 } 1052 1053 /* SW2HW_CQ - Software to Hardware CQ 1054 * ---------------------------------- 1055 * OpMod == 0 (N/A), INMmod == CQ number 1056 * ------------------------------------- 1057 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 1058 * to hardware. The command takes the CQ context entry from the input mailbox 1059 * and stores it in the CQC in the ownership of the hardware. The command fails 1060 * if the requested CQC entry is already in the ownership of the hardware. 1061 */ 1062 1063 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 1064 char *in_mbox, u32 cq_number) 1065 { 1066 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 1067 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1068 } 1069 1070 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { 1071 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, 1072 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, 1073 }; 1074 1075 /* cmd_mbox_sw2hw_cq_cqe_ver 1076 * CQE Version. 1077 */ 1078 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); 1079 1080 /* cmd_mbox_sw2hw_cq_c_eqn 1081 * Event Queue this CQ reports completion events to. 1082 */ 1083 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 1084 1085 /* cmd_mbox_sw2hw_cq_st 1086 * Event delivery state machine 1087 * 0x0 - FIRED 1088 * 0x1 - ARMED (Request for Notification) 1089 */ 1090 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 1091 1092 /* cmd_mbox_sw2hw_cq_log_cq_size 1093 * Log (base 2) of the CQ size (in entries). 1094 */ 1095 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 1096 1097 /* cmd_mbox_sw2hw_cq_producer_counter 1098 * Producer Counter. The counter is incremented for each CQE that is 1099 * written by the HW to the CQ. 1100 * Maintained by HW (valid for the QUERY_CQ command only) 1101 */ 1102 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 1103 1104 /* cmd_mbox_sw2hw_cq_pa 1105 * Physical Address. 1106 */ 1107 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1108 1109 /* HW2SW_CQ - Hardware to Software CQ 1110 * ---------------------------------- 1111 * OpMod == 0 (N/A), INMmod == CQ number 1112 * ------------------------------------- 1113 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1114 * to software. The CQC entry is invalidated as a result of this command. 1115 */ 1116 1117 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1118 u32 cq_number) 1119 { 1120 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1121 0, cq_number); 1122 } 1123 1124 /* QUERY_CQ - Query CQ 1125 * ---------------------------------- 1126 * OpMod == 0 (N/A), INMmod == CQ number 1127 * ------------------------------------- 1128 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1129 * The command stores the snapshot in the output mailbox in the software format. 1130 * Note that the CQ context state and values are not affected by the QUERY_CQ 1131 * command. The QUERY_CQ command is for debug purposes only. 1132 * 1133 * Note: Output mailbox has the same format as SW2HW_CQ. 1134 */ 1135 1136 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1137 char *out_mbox, u32 cq_number) 1138 { 1139 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1140 0, cq_number, false, 1141 out_mbox, MLXSW_CMD_MBOX_SIZE); 1142 } 1143 1144 /* SW2HW_EQ - Software to Hardware EQ 1145 * ---------------------------------- 1146 * OpMod == 0 (N/A), INMmod == EQ number 1147 * ------------------------------------- 1148 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1149 * to hardware. The command takes the EQ context entry from the input mailbox 1150 * and stores it in the EQC in the ownership of the hardware. The command fails 1151 * if the requested EQC entry is already in the ownership of the hardware. 1152 */ 1153 1154 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1155 char *in_mbox, u32 eq_number) 1156 { 1157 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1158 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1159 } 1160 1161 /* cmd_mbox_sw2hw_eq_int_msix 1162 * When set, MSI-X cycles will be generated by this EQ. 1163 * When cleared, an interrupt will be generated by this EQ. 1164 */ 1165 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1166 1167 /* cmd_mbox_sw2hw_eq_st 1168 * Event delivery state machine 1169 * 0x0 - FIRED 1170 * 0x1 - ARMED (Request for Notification) 1171 * 0x11 - Always ARMED 1172 * other - reserved 1173 */ 1174 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1175 1176 /* cmd_mbox_sw2hw_eq_log_eq_size 1177 * Log (base 2) of the EQ size (in entries). 1178 */ 1179 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1180 1181 /* cmd_mbox_sw2hw_eq_producer_counter 1182 * Producer Counter. The counter is incremented for each EQE that is written 1183 * by the HW to the EQ. 1184 * Maintained by HW (valid for the QUERY_EQ command only) 1185 */ 1186 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1187 1188 /* cmd_mbox_sw2hw_eq_pa 1189 * Physical Address. 1190 */ 1191 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1192 1193 /* HW2SW_EQ - Hardware to Software EQ 1194 * ---------------------------------- 1195 * OpMod == 0 (N/A), INMmod == EQ number 1196 * ------------------------------------- 1197 */ 1198 1199 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1200 u32 eq_number) 1201 { 1202 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1203 0, eq_number); 1204 } 1205 1206 /* QUERY_EQ - Query EQ 1207 * ---------------------------------- 1208 * OpMod == 0 (N/A), INMmod == EQ number 1209 * ------------------------------------- 1210 * 1211 * Note: Output mailbox has the same format as SW2HW_EQ. 1212 */ 1213 1214 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1215 char *out_mbox, u32 eq_number) 1216 { 1217 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1218 0, eq_number, false, 1219 out_mbox, MLXSW_CMD_MBOX_SIZE); 1220 } 1221 1222 #endif 1223