1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_CMD_H 5 #define _MLXSW_CMD_H 6 7 #include "item.h" 8 9 #define MLXSW_CMD_MBOX_SIZE 4096 10 11 static inline char *mlxsw_cmd_mbox_alloc(void) 12 { 13 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 14 } 15 16 static inline void mlxsw_cmd_mbox_free(char *mbox) 17 { 18 kfree(mbox); 19 } 20 21 static inline void mlxsw_cmd_mbox_zero(char *mbox) 22 { 23 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 24 } 25 26 struct mlxsw_core; 27 28 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 29 u32 in_mod, bool out_mbox_direct, bool reset_ok, 30 char *in_mbox, size_t in_mbox_size, 31 char *out_mbox, size_t out_mbox_size); 32 33 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 34 u8 opcode_mod, u32 in_mod, char *in_mbox, 35 size_t in_mbox_size) 36 { 37 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 38 false, in_mbox, in_mbox_size, NULL, 0); 39 } 40 41 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 42 u8 opcode_mod, u32 in_mod, 43 bool out_mbox_direct, 44 char *out_mbox, size_t out_mbox_size) 45 { 46 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 47 out_mbox_direct, false, NULL, 0, 48 out_mbox, out_mbox_size); 49 } 50 51 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 52 u8 opcode_mod, u32 in_mod) 53 { 54 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 55 false, NULL, 0, NULL, 0); 56 } 57 58 enum mlxsw_cmd_opcode { 59 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 60 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 61 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 62 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 63 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 64 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 65 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 66 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 67 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 68 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 69 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 70 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 71 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 72 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 73 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 74 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 75 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 76 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, 77 }; 78 79 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 80 { 81 switch (opcode) { 82 case MLXSW_CMD_OPCODE_QUERY_FW: 83 return "QUERY_FW"; 84 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 85 return "QUERY_BOARDINFO"; 86 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 87 return "QUERY_AQ_CAP"; 88 case MLXSW_CMD_OPCODE_MAP_FA: 89 return "MAP_FA"; 90 case MLXSW_CMD_OPCODE_UNMAP_FA: 91 return "UNMAP_FA"; 92 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 93 return "CONFIG_PROFILE"; 94 case MLXSW_CMD_OPCODE_ACCESS_REG: 95 return "ACCESS_REG"; 96 case MLXSW_CMD_OPCODE_SW2HW_DQ: 97 return "SW2HW_DQ"; 98 case MLXSW_CMD_OPCODE_HW2SW_DQ: 99 return "HW2SW_DQ"; 100 case MLXSW_CMD_OPCODE_2ERR_DQ: 101 return "2ERR_DQ"; 102 case MLXSW_CMD_OPCODE_QUERY_DQ: 103 return "QUERY_DQ"; 104 case MLXSW_CMD_OPCODE_SW2HW_CQ: 105 return "SW2HW_CQ"; 106 case MLXSW_CMD_OPCODE_HW2SW_CQ: 107 return "HW2SW_CQ"; 108 case MLXSW_CMD_OPCODE_QUERY_CQ: 109 return "QUERY_CQ"; 110 case MLXSW_CMD_OPCODE_SW2HW_EQ: 111 return "SW2HW_EQ"; 112 case MLXSW_CMD_OPCODE_HW2SW_EQ: 113 return "HW2SW_EQ"; 114 case MLXSW_CMD_OPCODE_QUERY_EQ: 115 return "QUERY_EQ"; 116 case MLXSW_CMD_OPCODE_QUERY_RESOURCES: 117 return "QUERY_RESOURCES"; 118 default: 119 return "*UNKNOWN*"; 120 } 121 } 122 123 enum mlxsw_cmd_status { 124 /* Command execution succeeded. */ 125 MLXSW_CMD_STATUS_OK = 0x00, 126 /* Internal error (e.g. bus error) occurred while processing command. */ 127 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 128 /* Operation/command not supported or opcode modifier not supported. */ 129 MLXSW_CMD_STATUS_BAD_OP = 0x02, 130 /* Parameter not supported, parameter out of range. */ 131 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 132 /* System was not enabled or bad system state. */ 133 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 134 /* Attempt to access reserved or unallocated resource, or resource in 135 * inappropriate ownership. 136 */ 137 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 138 /* Requested resource is currently executing a command. */ 139 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 140 /* Required capability exceeds device limits. */ 141 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 142 /* Resource is not in the appropriate state or ownership. */ 143 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 144 /* Index out of range (might be beyond table size or attempt to 145 * access a reserved resource). 146 */ 147 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 148 /* NVMEM checksum/CRC failed. */ 149 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 150 /* Device is currently running reset */ 151 MLXSW_CMD_STATUS_RUNNING_RESET = 0x26, 152 /* Bad management packet (silently discarded). */ 153 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 154 }; 155 156 static inline const char *mlxsw_cmd_status_str(u8 status) 157 { 158 switch (status) { 159 case MLXSW_CMD_STATUS_OK: 160 return "OK"; 161 case MLXSW_CMD_STATUS_INTERNAL_ERR: 162 return "INTERNAL_ERR"; 163 case MLXSW_CMD_STATUS_BAD_OP: 164 return "BAD_OP"; 165 case MLXSW_CMD_STATUS_BAD_PARAM: 166 return "BAD_PARAM"; 167 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 168 return "BAD_SYS_STATE"; 169 case MLXSW_CMD_STATUS_BAD_RESOURCE: 170 return "BAD_RESOURCE"; 171 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 172 return "RESOURCE_BUSY"; 173 case MLXSW_CMD_STATUS_EXCEED_LIM: 174 return "EXCEED_LIM"; 175 case MLXSW_CMD_STATUS_BAD_RES_STATE: 176 return "BAD_RES_STATE"; 177 case MLXSW_CMD_STATUS_BAD_INDEX: 178 return "BAD_INDEX"; 179 case MLXSW_CMD_STATUS_BAD_NVMEM: 180 return "BAD_NVMEM"; 181 case MLXSW_CMD_STATUS_RUNNING_RESET: 182 return "RUNNING_RESET"; 183 case MLXSW_CMD_STATUS_BAD_PKT: 184 return "BAD_PKT"; 185 default: 186 return "*UNKNOWN*"; 187 } 188 } 189 190 /* QUERY_FW - Query Firmware 191 * ------------------------- 192 * OpMod == 0, INMmod == 0 193 * ----------------------- 194 * The QUERY_FW command retrieves information related to firmware, command 195 * interface version and the amount of resources that should be allocated to 196 * the firmware. 197 */ 198 199 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 200 char *out_mbox) 201 { 202 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 203 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 204 } 205 206 /* cmd_mbox_query_fw_fw_pages 207 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 208 */ 209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 210 211 /* cmd_mbox_query_fw_fw_rev_major 212 * Firmware Revision - Major 213 */ 214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 215 216 /* cmd_mbox_query_fw_fw_rev_subminor 217 * Firmware Sub-minor version (Patch level) 218 */ 219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 220 221 /* cmd_mbox_query_fw_fw_rev_minor 222 * Firmware Revision - Minor 223 */ 224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 225 226 /* cmd_mbox_query_fw_core_clk 227 * Internal Clock Frequency (in MHz) 228 */ 229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 230 231 /* cmd_mbox_query_fw_cmd_interface_rev 232 * Command Interface Interpreter Revision ID. This number is bumped up 233 * every time a non-backward-compatible change is done for the command 234 * interface. The current cmd_interface_rev is 1. 235 */ 236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 237 238 /* cmd_mbox_query_fw_dt 239 * If set, Debug Trace is supported 240 */ 241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 242 243 /* cmd_mbox_query_fw_api_version 244 * Indicates the version of the API, to enable software querying 245 * for compatibility. The current api_version is 1. 246 */ 247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 248 249 /* cmd_mbox_query_fw_fw_hour 250 * Firmware timestamp - hour 251 */ 252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 253 254 /* cmd_mbox_query_fw_fw_minutes 255 * Firmware timestamp - minutes 256 */ 257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 258 259 /* cmd_mbox_query_fw_fw_seconds 260 * Firmware timestamp - seconds 261 */ 262 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 263 264 /* cmd_mbox_query_fw_fw_year 265 * Firmware timestamp - year 266 */ 267 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 268 269 /* cmd_mbox_query_fw_fw_month 270 * Firmware timestamp - month 271 */ 272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 273 274 /* cmd_mbox_query_fw_fw_day 275 * Firmware timestamp - day 276 */ 277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 278 279 /* cmd_mbox_query_fw_clr_int_base_offset 280 * Clear Interrupt register's offset from clr_int_bar register 281 * in PCI address space. 282 */ 283 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 284 285 /* cmd_mbox_query_fw_clr_int_bar 286 * PCI base address register (BAR) where clr_int register is located. 287 * 00 - BAR 0-1 (64 bit BAR) 288 */ 289 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 290 291 /* cmd_mbox_query_fw_error_buf_offset 292 * Read Only buffer for internal error reports of offset 293 * from error_buf_bar register in PCI address space). 294 */ 295 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 296 297 /* cmd_mbox_query_fw_error_buf_size 298 * Internal error buffer size in DWORDs 299 */ 300 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 301 302 /* cmd_mbox_query_fw_error_int_bar 303 * PCI base address register (BAR) where error buffer 304 * register is located. 305 * 00 - BAR 0-1 (64 bit BAR) 306 */ 307 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 308 309 /* cmd_mbox_query_fw_doorbell_page_offset 310 * Offset of the doorbell page 311 */ 312 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 313 314 /* cmd_mbox_query_fw_doorbell_page_bar 315 * PCI base address register (BAR) of the doorbell page 316 * 00 - BAR 0-1 (64 bit BAR) 317 */ 318 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 319 320 /* cmd_mbox_query_fw_free_running_clock_offset 321 * The offset of the free running clock page 322 */ 323 MLXSW_ITEM64(cmd_mbox, query_fw, free_running_clock_offset, 0x50, 0, 64); 324 325 /* cmd_mbox_query_fw_fr_rn_clk_bar 326 * PCI base address register (BAR) of the free running clock page 327 * 0: BAR 0 328 * 1: 64 bit BAR 329 */ 330 MLXSW_ITEM32(cmd_mbox, query_fw, fr_rn_clk_bar, 0x58, 30, 2); 331 332 /* cmd_mbox_query_fw_utc_sec_offset 333 * The offset of the UTC_Sec page 334 */ 335 MLXSW_ITEM64(cmd_mbox, query_fw, utc_sec_offset, 0x70, 0, 64); 336 337 /* cmd_mbox_query_fw_utc_sec_bar 338 * PCI base address register (BAR) of the UTC_Sec page 339 * 0: BAR 0 340 * 1: 64 bit BAR 341 * Reserved on SwitchX/-2, Switch-IB/2, Spectrum-1 342 */ 343 MLXSW_ITEM32(cmd_mbox, query_fw, utc_sec_bar, 0x78, 30, 2); 344 345 /* cmd_mbox_query_fw_utc_nsec_offset 346 * The offset of the UTC_nSec page 347 */ 348 MLXSW_ITEM64(cmd_mbox, query_fw, utc_nsec_offset, 0x80, 0, 64); 349 350 /* cmd_mbox_query_fw_utc_nsec_bar 351 * PCI base address register (BAR) of the UTC_nSec page 352 * 0: BAR 0 353 * 1: 64 bit BAR 354 * Reserved on SwitchX/-2, Switch-IB/2, Spectrum-1 355 */ 356 MLXSW_ITEM32(cmd_mbox, query_fw, utc_nsec_bar, 0x88, 30, 2); 357 358 /* QUERY_BOARDINFO - Query Board Information 359 * ----------------------------------------- 360 * OpMod == 0 (N/A), INMmod == 0 (N/A) 361 * ----------------------------------- 362 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 363 */ 364 365 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 366 char *out_mbox) 367 { 368 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 369 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 370 } 371 372 /* cmd_mbox_boardinfo_intapin 373 * When PCIe interrupt messages are being used, this value is used for clearing 374 * an interrupt. When using MSI-X, this register is not used. 375 */ 376 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 377 378 /* cmd_mbox_boardinfo_vsd_vendor_id 379 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 380 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 381 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 382 * format and encoding as long as they use their assigned vsd_vendor_id. 383 */ 384 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 385 386 /* cmd_mbox_boardinfo_vsd 387 * Vendor Specific Data. The VSD string that is burnt to the Flash 388 * with the firmware. 389 */ 390 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 391 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 392 393 /* cmd_mbox_boardinfo_psid 394 * The PSID field is a 16-ascii (byte) character string which acts as 395 * the board ID. The PSID format is used in conjunction with 396 * Mellanox vsd_vendor_id (15B3h). 397 */ 398 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 399 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 400 401 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 402 * ----------------------------------------------------- 403 * OpMod == 0 (N/A), INMmod == 0 (N/A) 404 * ----------------------------------- 405 * The QUERY_AQ_CAP command returns the device asynchronous queues 406 * capabilities supported. 407 */ 408 409 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 410 char *out_mbox) 411 { 412 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 413 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 414 } 415 416 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 417 * Log (base 2) of max WQEs allowed on SDQ. 418 */ 419 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 420 421 /* cmd_mbox_query_aq_cap_max_num_sdqs 422 * Maximum number of SDQs. 423 */ 424 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 425 426 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 427 * Log (base 2) of max WQEs allowed on RDQ. 428 */ 429 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 430 431 /* cmd_mbox_query_aq_cap_max_num_rdqs 432 * Maximum number of RDQs. 433 */ 434 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 435 436 /* cmd_mbox_query_aq_cap_log_max_cq_sz 437 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. 438 */ 439 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 440 441 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz 442 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. 443 */ 444 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); 445 446 /* cmd_mbox_query_aq_cap_max_num_cqs 447 * Maximum number of CQs. 448 */ 449 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 450 451 /* cmd_mbox_query_aq_cap_log_max_eq_sz 452 * Log (base 2) of max EQEs allowed on EQ. 453 */ 454 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 455 456 /* cmd_mbox_query_aq_cap_max_num_eqs 457 * Maximum number of EQs. 458 */ 459 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 460 461 /* cmd_mbox_query_aq_cap_max_sg_sq 462 * The maximum S/G list elements in an DSQ. DSQ must not contain 463 * more S/G entries than indicated here. 464 */ 465 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 466 467 /* cmd_mbox_query_aq_cap_ 468 * The maximum S/G list elements in an DRQ. DRQ must not contain 469 * more S/G entries than indicated here. 470 */ 471 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 472 473 /* MAP_FA - Map Firmware Area 474 * -------------------------- 475 * OpMod == 0 (N/A), INMmod == Number of VPM entries 476 * ------------------------------------------------- 477 * The MAP_FA command passes physical pages to the switch. These pages 478 * are used to store the device firmware. MAP_FA can be executed multiple 479 * times until all the firmware area is mapped (the size that should be 480 * mapped is retrieved through the QUERY_FW command). All required pages 481 * must be mapped to finish the initialization phase. Physical memory 482 * passed in this command must be pinned. 483 */ 484 485 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 486 487 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 488 char *in_mbox, u32 vpm_entries_count) 489 { 490 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 491 0, vpm_entries_count, 492 in_mbox, MLXSW_CMD_MBOX_SIZE); 493 } 494 495 /* cmd_mbox_map_fa_pa 496 * Physical Address. 497 */ 498 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 499 500 /* cmd_mbox_map_fa_log2size 501 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 502 * that starts at PA_L/H. 503 */ 504 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 505 506 /* UNMAP_FA - Unmap Firmware Area 507 * ------------------------------ 508 * OpMod == 0 (N/A), INMmod == 0 (N/A) 509 * ----------------------------------- 510 * The UNMAP_FA command unload the firmware and unmaps all the 511 * firmware area. After this command is completed the device will not access 512 * the pages that were mapped to the firmware area. After executing UNMAP_FA 513 * command, software reset must be done prior to execution of MAP_FW command. 514 */ 515 516 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 517 { 518 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 519 } 520 521 /* QUERY_RESOURCES - Query chip resources 522 * -------------------------------------- 523 * OpMod == 0 (N/A) , INMmod is index 524 * ---------------------------------- 525 * The QUERY_RESOURCES command retrieves information related to chip resources 526 * by resource ID. Every command returns 32 entries. INmod is being use as base. 527 * for example, index 1 will return entries 32-63. When the tables end and there 528 * are no more sources in the table, will return resource id 0xFFF to indicate 529 * it. 530 */ 531 532 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff 533 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 534 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 535 536 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, 537 char *out_mbox, int index) 538 { 539 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES, 540 0, index, false, out_mbox, 541 MLXSW_CMD_MBOX_SIZE); 542 } 543 544 /* cmd_mbox_query_resource_id 545 * The resource id. 0xFFFF indicates table's end. 546 */ 547 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); 548 549 /* cmd_mbox_query_resource_data 550 * The resource 551 */ 552 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, 553 0x00, 0, 40, 0x8, 0, false); 554 555 /* CONFIG_PROFILE (Set) - Configure Switch Profile 556 * ------------------------------ 557 * OpMod == 1 (Set), INMmod == 0 (N/A) 558 * ----------------------------------- 559 * The CONFIG_PROFILE command sets the switch profile. The command can be 560 * executed on the device only once at startup in order to allocate and 561 * configure all switch resources and prepare it for operational mode. 562 * It is not possible to change the device profile after the chip is 563 * in operational mode. 564 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 565 * state therefore it is required to perform software reset to the device 566 * following an unsuccessful completion of the command. It is required 567 * to perform software reset to the device to change an existing profile. 568 */ 569 570 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 571 char *in_mbox) 572 { 573 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 574 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 575 } 576 577 /* cmd_mbox_config_profile_set_max_vepa_channels 578 * Capability bit. Setting a bit to 1 configures the profile 579 * according to the mailbox contents. 580 */ 581 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 582 583 /* cmd_mbox_config_profile_set_max_lag 584 * Capability bit. Setting a bit to 1 configures the profile 585 * according to the mailbox contents. 586 */ 587 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 588 589 /* cmd_mbox_config_profile_set_max_port_per_lag 590 * Capability bit. Setting a bit to 1 configures the profile 591 * according to the mailbox contents. 592 */ 593 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 594 595 /* cmd_mbox_config_profile_set_max_mid 596 * Capability bit. Setting a bit to 1 configures the profile 597 * according to the mailbox contents. 598 */ 599 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 600 601 /* cmd_mbox_config_profile_set_max_pgt 602 * Capability bit. Setting a bit to 1 configures the profile 603 * according to the mailbox contents. 604 */ 605 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 606 607 /* cmd_mbox_config_profile_set_max_system_port 608 * Capability bit. Setting a bit to 1 configures the profile 609 * according to the mailbox contents. 610 */ 611 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 612 613 /* cmd_mbox_config_profile_set_max_vlan_groups 614 * Capability bit. Setting a bit to 1 configures the profile 615 * according to the mailbox contents. 616 */ 617 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 618 619 /* cmd_mbox_config_profile_set_max_regions 620 * Capability bit. Setting a bit to 1 configures the profile 621 * according to the mailbox contents. 622 */ 623 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 624 625 /* cmd_mbox_config_profile_set_flood_mode 626 * Capability bit. Setting a bit to 1 configures the profile 627 * according to the mailbox contents. 628 */ 629 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 630 631 /* cmd_mbox_config_profile_set_max_flood_tables 632 * Capability bit. Setting a bit to 1 configures the profile 633 * according to the mailbox contents. 634 */ 635 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 636 637 /* cmd_mbox_config_profile_set_max_ib_mc 638 * Capability bit. Setting a bit to 1 configures the profile 639 * according to the mailbox contents. 640 */ 641 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 642 643 /* cmd_mbox_config_profile_set_max_pkey 644 * Capability bit. Setting a bit to 1 configures the profile 645 * according to the mailbox contents. 646 */ 647 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 648 649 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 650 * Capability bit. Setting a bit to 1 configures the profile 651 * according to the mailbox contents. 652 */ 653 MLXSW_ITEM32(cmd_mbox, config_profile, 654 set_adaptive_routing_group_cap, 0x0C, 14, 1); 655 656 /* cmd_mbox_config_profile_set_ar_sec 657 * Capability bit. Setting a bit to 1 configures the profile 658 * according to the mailbox contents. 659 */ 660 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 661 662 /* cmd_mbox_config_set_ubridge 663 * Capability bit. Setting a bit to 1 configures the profile 664 * according to the mailbox contents. 665 */ 666 MLXSW_ITEM32(cmd_mbox, config_profile, set_ubridge, 0x0C, 22, 1); 667 668 /* cmd_mbox_config_set_kvd_linear_size 669 * Capability bit. Setting a bit to 1 configures the profile 670 * according to the mailbox contents. 671 */ 672 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); 673 674 /* cmd_mbox_config_set_kvd_hash_single_size 675 * Capability bit. Setting a bit to 1 configures the profile 676 * according to the mailbox contents. 677 */ 678 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); 679 680 /* cmd_mbox_config_set_kvd_hash_double_size 681 * Capability bit. Setting a bit to 1 configures the profile 682 * according to the mailbox contents. 683 */ 684 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 685 686 /* cmd_mbox_config_set_cqe_version 687 * Capability bit. Setting a bit to 1 configures the profile 688 * according to the mailbox contents. 689 */ 690 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); 691 692 /* cmd_mbox_config_set_cqe_time_stamp_type 693 * Capability bit. Setting a bit to 1 configures the profile 694 * according to the mailbox contents. 695 */ 696 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_time_stamp_type, 0x08, 2, 1); 697 698 /* cmd_mbox_config_profile_max_vepa_channels 699 * Maximum number of VEPA channels per port (0 through 16) 700 * 0 - multi-channel VEPA is disabled 701 */ 702 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 703 704 /* cmd_mbox_config_profile_max_lag 705 * Maximum number of LAG IDs requested. 706 * Reserved when Spectrum-1/2/3, supported from Spectrum-4 and above. 707 * For Spectrum-4, firmware sets 128 for values between 1-128 and 256 for values 708 * between 129-256. 709 */ 710 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 711 712 /* cmd_mbox_config_profile_max_port_per_lag 713 * Maximum number of ports per LAG requested. 714 */ 715 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 716 717 /* cmd_mbox_config_profile_max_mid 718 * Maximum Multicast IDs. 719 * Multicast IDs are allocated from 0 to max_mid-1 720 */ 721 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 722 723 /* cmd_mbox_config_profile_max_pgt 724 * Maximum records in the Port Group Table per Switch Partition. 725 * Port Group Table indexes are from 0 to max_pgt-1 726 */ 727 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 728 729 /* cmd_mbox_config_profile_max_system_port 730 * The maximum number of system ports that can be allocated. 731 */ 732 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 733 734 /* cmd_mbox_config_profile_max_vlan_groups 735 * Maximum number VLAN Groups for VLAN binding. 736 */ 737 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 738 739 /* cmd_mbox_config_profile_max_regions 740 * Maximum number of TCAM Regions. 741 */ 742 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 743 744 /* cmd_mbox_config_profile_max_flood_tables 745 * Maximum number of single-entry flooding tables. Different flooding tables 746 * can be associated with different packet types. 747 */ 748 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 749 750 /* cmd_mbox_config_profile_max_vid_flood_tables 751 * Maximum number of per-vid flooding tables. Flooding tables are associated 752 * to the different packet types for the different switch partitions. 753 * Table size is 4K entries covering all VID space. 754 */ 755 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 756 757 enum mlxsw_cmd_mbox_config_profile_flood_mode { 758 /* Mixed mode, where: 759 * max_flood_tables indicates the number of single-entry tables. 760 * max_vid_flood_tables indicates the number of per-VID tables. 761 * max_fid_offset_flood_tables indicates the number of FID-offset 762 * tables. max_fid_flood_tables indicates the number of per-FID tables. 763 * Reserved when unified bridge model is used. 764 */ 765 MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_MIXED = 3, 766 /* Controlled flood tables. Reserved when legacy bridge model is 767 * used. 768 */ 769 MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED = 4, 770 }; 771 772 /* cmd_mbox_config_profile_flood_mode 773 * Flooding mode to use. 774 */ 775 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 3); 776 777 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 778 * Maximum number of FID-offset flooding tables. 779 */ 780 MLXSW_ITEM32(cmd_mbox, config_profile, 781 max_fid_offset_flood_tables, 0x34, 24, 4); 782 783 /* cmd_mbox_config_profile_fid_offset_flood_table_size 784 * The size (number of entries) of each FID-offset flood table. 785 */ 786 MLXSW_ITEM32(cmd_mbox, config_profile, 787 fid_offset_flood_table_size, 0x34, 0, 16); 788 789 /* cmd_mbox_config_profile_max_fid_flood_tables 790 * Maximum number of per-FID flooding tables. 791 * 792 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 793 * FID value 4K and higher. 794 */ 795 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 796 797 /* cmd_mbox_config_profile_fid_flood_table_size 798 * The size (number of entries) of each per-FID table. 799 */ 800 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 801 802 /* cmd_mbox_config_profile_max_ib_mc 803 * Maximum number of multicast FDB records for InfiniBand 804 * FDB (in 512 chunks) per InfiniBand switch partition. 805 */ 806 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 807 808 /* cmd_mbox_config_profile_max_pkey 809 * Maximum per port PKEY table size (for PKEY enforcement) 810 */ 811 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 812 813 /* cmd_mbox_config_profile_ar_sec 814 * Primary/secondary capability 815 * Describes the number of adaptive routing sub-groups 816 * 0 - disable primary/secondary (single group) 817 * 1 - enable primary/secondary (2 sub-groups) 818 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 819 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 820 */ 821 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 822 823 /* cmd_mbox_config_profile_adaptive_routing_group_cap 824 * Adaptive Routing Group Capability. Indicates the number of AR groups 825 * supported. Note that when Primary/secondary is enabled, each 826 * primary/secondary couple consumes 2 adaptive routing entries. 827 */ 828 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 829 830 /* cmd_mbox_config_profile_arn 831 * Adaptive Routing Notification Enable 832 * Not supported in SwitchX, SwitchX-2 833 */ 834 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 835 836 /* cmd_mbox_config_profile_ubridge 837 * Unified Bridge 838 * 0 - non unified bridge 839 * 1 - unified bridge 840 */ 841 MLXSW_ITEM32(cmd_mbox, config_profile, ubridge, 0x50, 4, 1); 842 843 /* cmd_mbox_config_kvd_linear_size 844 * KVD Linear Size 845 * Valid for Spectrum only 846 * Allowed values are 128*N where N=0 or higher 847 */ 848 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); 849 850 /* cmd_mbox_config_kvd_hash_single_size 851 * KVD Hash single-entries size 852 * Valid for Spectrum only 853 * Allowed values are 128*N where N=0 or higher 854 * Must be greater or equal to cap_min_kvd_hash_single_size 855 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 856 */ 857 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); 858 859 /* cmd_mbox_config_kvd_hash_double_size 860 * KVD Hash double-entries size (units of single-size entries) 861 * Valid for Spectrum only 862 * Allowed values are 128*N where N=0 or higher 863 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size 864 * Must be smaller or equal to cap_kvd_size - kvd_linear_size 865 */ 866 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); 867 868 /* cmd_mbox_config_profile_swid_config_mask 869 * Modify Switch Partition Configuration mask. When set, the configu- 870 * ration value for the Switch Partition are taken from the mailbox. 871 * When clear, the current configuration values are used. 872 * Bit 0 - set type 873 * Bit 1 - properties 874 * Other - reserved 875 */ 876 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 877 0x60, 24, 8, 0x08, 0x00, false); 878 879 /* cmd_mbox_config_profile_swid_config_type 880 * Switch Partition type. 881 * 0000 - disabled (Switch Partition does not exist) 882 * 0001 - InfiniBand 883 * 0010 - Ethernet 884 * 1000 - router port (SwitchX-2 only) 885 * Other - reserved 886 */ 887 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 888 0x60, 20, 4, 0x08, 0x00, false); 889 890 /* cmd_mbox_config_profile_swid_config_properties 891 * Switch Partition properties. 892 */ 893 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 894 0x60, 0, 8, 0x08, 0x00, false); 895 896 enum mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type { 897 /* uSec - 1.024uSec (default). Only bits 15:0 are valid. */ 898 MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_USEC, 899 /* FRC - Free Running Clock, units of 1nSec. 900 * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1. 901 */ 902 MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_FRC, 903 /* UTC. time_stamp[37:30] = Sec, time_stamp[29:0] = nSec. 904 * Reserved when SwitchX/2, Switch-IB/2 and Spectrum-1. 905 */ 906 MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 907 }; 908 909 /* cmd_mbox_config_profile_cqe_time_stamp_type 910 * CQE time_stamp_type for non-mirror-packets. 911 * Configured if set_cqe_time_stamp_type is set. 912 * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1. 913 */ 914 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_time_stamp_type, 0xB0, 8, 2); 915 916 /* cmd_mbox_config_profile_cqe_version 917 * CQE version: 918 * 0: CQE version is 0 919 * 1: CQE version is either 1 or 2 920 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. 921 */ 922 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); 923 924 /* ACCESS_REG - Access EMAD Supported Register 925 * ---------------------------------- 926 * OpMod == 0 (N/A), INMmod == 0 (N/A) 927 * ------------------------------------- 928 * The ACCESS_REG command supports accessing device registers. This access 929 * is mainly used for bootstrapping. 930 */ 931 932 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 933 bool reset_ok, 934 char *in_mbox, char *out_mbox) 935 { 936 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 937 0, 0, false, reset_ok, 938 in_mbox, MLXSW_CMD_MBOX_SIZE, 939 out_mbox, MLXSW_CMD_MBOX_SIZE); 940 } 941 942 /* SW2HW_DQ - Software to Hardware DQ 943 * ---------------------------------- 944 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 945 * INMmod == DQ number 946 * ---------------------------------------------- 947 * The SW2HW_DQ command transitions a descriptor queue from software to 948 * hardware ownership. The command enables posting WQEs and ringing DoorBells 949 * on the descriptor queue. 950 */ 951 952 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 953 char *in_mbox, u32 dq_number, 954 u8 opcode_mod) 955 { 956 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 957 opcode_mod, dq_number, 958 in_mbox, MLXSW_CMD_MBOX_SIZE); 959 } 960 961 enum { 962 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 963 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 964 }; 965 966 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 967 char *in_mbox, u32 dq_number) 968 { 969 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 970 MLXSW_CMD_OPCODE_MOD_SDQ); 971 } 972 973 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 974 char *in_mbox, u32 dq_number) 975 { 976 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 977 MLXSW_CMD_OPCODE_MOD_RDQ); 978 } 979 980 /* cmd_mbox_sw2hw_dq_cq 981 * Number of the CQ that this Descriptor Queue reports completions to. 982 */ 983 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 984 985 enum mlxsw_cmd_mbox_sw2hw_dq_sdq_lp { 986 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE, 987 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE, 988 }; 989 990 /* cmd_mbox_sw2hw_dq_sdq_lp 991 * SDQ local Processing 992 * 0: local processing by wqe.lp 993 * 1: local processing (ignoring wqe.lp) 994 */ 995 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_lp, 0x00, 23, 1); 996 997 /* cmd_mbox_sw2hw_dq_sdq_tclass 998 * SDQ: CPU Egress TClass 999 * RDQ: Reserved 1000 */ 1001 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 1002 1003 /* cmd_mbox_sw2hw_dq_log2_dq_sz 1004 * Log (base 2) of the Descriptor Queue size in 4KB pages. 1005 */ 1006 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 1007 1008 /* cmd_mbox_sw2hw_dq_pa 1009 * Physical Address. 1010 */ 1011 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 1012 1013 /* HW2SW_DQ - Hardware to Software DQ 1014 * ---------------------------------- 1015 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1016 * INMmod == DQ number 1017 * ---------------------------------------------- 1018 * The HW2SW_DQ command transitions a descriptor queue from hardware to 1019 * software ownership. Incoming packets on the DQ are silently discarded, 1020 * SW should not post descriptors on nonoperational DQs. 1021 */ 1022 1023 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 1024 u32 dq_number, u8 opcode_mod) 1025 { 1026 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 1027 opcode_mod, dq_number); 1028 } 1029 1030 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 1031 u32 dq_number) 1032 { 1033 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 1034 MLXSW_CMD_OPCODE_MOD_SDQ); 1035 } 1036 1037 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 1038 u32 dq_number) 1039 { 1040 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 1041 MLXSW_CMD_OPCODE_MOD_RDQ); 1042 } 1043 1044 /* 2ERR_DQ - To Error DQ 1045 * --------------------- 1046 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1047 * INMmod == DQ number 1048 * ---------------------------------------------- 1049 * The 2ERR_DQ command transitions the DQ into the error state from the state 1050 * in which it has been. While the command is executed, some in-process 1051 * descriptors may complete. Once the DQ transitions into the error state, 1052 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 1053 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 1054 * When the command is completed successfully, the DQ is already in 1055 * the error state. 1056 */ 1057 1058 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 1059 u32 dq_number, u8 opcode_mod) 1060 { 1061 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1062 opcode_mod, dq_number); 1063 } 1064 1065 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 1066 u32 dq_number) 1067 { 1068 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1069 MLXSW_CMD_OPCODE_MOD_SDQ); 1070 } 1071 1072 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 1073 u32 dq_number) 1074 { 1075 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 1076 MLXSW_CMD_OPCODE_MOD_RDQ); 1077 } 1078 1079 /* QUERY_DQ - Query DQ 1080 * --------------------- 1081 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 1082 * INMmod == DQ number 1083 * ---------------------------------------------- 1084 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 1085 * 1086 * Note: Output mailbox has the same format as SW2HW_DQ. 1087 */ 1088 1089 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 1090 char *out_mbox, u32 dq_number, 1091 u8 opcode_mod) 1092 { 1093 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 1094 opcode_mod, dq_number, false, 1095 out_mbox, MLXSW_CMD_MBOX_SIZE); 1096 } 1097 1098 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 1099 char *out_mbox, u32 dq_number) 1100 { 1101 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1102 MLXSW_CMD_OPCODE_MOD_SDQ); 1103 } 1104 1105 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 1106 char *out_mbox, u32 dq_number) 1107 { 1108 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 1109 MLXSW_CMD_OPCODE_MOD_RDQ); 1110 } 1111 1112 /* SW2HW_CQ - Software to Hardware CQ 1113 * ---------------------------------- 1114 * OpMod == 0 (N/A), INMmod == CQ number 1115 * ------------------------------------- 1116 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 1117 * to hardware. The command takes the CQ context entry from the input mailbox 1118 * and stores it in the CQC in the ownership of the hardware. The command fails 1119 * if the requested CQC entry is already in the ownership of the hardware. 1120 */ 1121 1122 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 1123 char *in_mbox, u32 cq_number) 1124 { 1125 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 1126 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1127 } 1128 1129 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { 1130 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, 1131 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, 1132 }; 1133 1134 /* cmd_mbox_sw2hw_cq_cqe_ver 1135 * CQE Version. 1136 */ 1137 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); 1138 1139 /* cmd_mbox_sw2hw_cq_c_eqn 1140 * Event Queue this CQ reports completion events to. 1141 */ 1142 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 1143 1144 /* cmd_mbox_sw2hw_cq_st 1145 * Event delivery state machine 1146 * 0x0 - FIRED 1147 * 0x1 - ARMED (Request for Notification) 1148 */ 1149 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 1150 1151 /* cmd_mbox_sw2hw_cq_log_cq_size 1152 * Log (base 2) of the CQ size (in entries). 1153 */ 1154 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 1155 1156 /* cmd_mbox_sw2hw_cq_producer_counter 1157 * Producer Counter. The counter is incremented for each CQE that is 1158 * written by the HW to the CQ. 1159 * Maintained by HW (valid for the QUERY_CQ command only) 1160 */ 1161 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 1162 1163 /* cmd_mbox_sw2hw_cq_pa 1164 * Physical Address. 1165 */ 1166 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1167 1168 /* HW2SW_CQ - Hardware to Software CQ 1169 * ---------------------------------- 1170 * OpMod == 0 (N/A), INMmod == CQ number 1171 * ------------------------------------- 1172 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1173 * to software. The CQC entry is invalidated as a result of this command. 1174 */ 1175 1176 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1177 u32 cq_number) 1178 { 1179 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1180 0, cq_number); 1181 } 1182 1183 /* QUERY_CQ - Query CQ 1184 * ---------------------------------- 1185 * OpMod == 0 (N/A), INMmod == CQ number 1186 * ------------------------------------- 1187 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1188 * The command stores the snapshot in the output mailbox in the software format. 1189 * Note that the CQ context state and values are not affected by the QUERY_CQ 1190 * command. The QUERY_CQ command is for debug purposes only. 1191 * 1192 * Note: Output mailbox has the same format as SW2HW_CQ. 1193 */ 1194 1195 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1196 char *out_mbox, u32 cq_number) 1197 { 1198 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1199 0, cq_number, false, 1200 out_mbox, MLXSW_CMD_MBOX_SIZE); 1201 } 1202 1203 /* SW2HW_EQ - Software to Hardware EQ 1204 * ---------------------------------- 1205 * OpMod == 0 (N/A), INMmod == EQ number 1206 * ------------------------------------- 1207 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1208 * to hardware. The command takes the EQ context entry from the input mailbox 1209 * and stores it in the EQC in the ownership of the hardware. The command fails 1210 * if the requested EQC entry is already in the ownership of the hardware. 1211 */ 1212 1213 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1214 char *in_mbox, u32 eq_number) 1215 { 1216 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1217 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1218 } 1219 1220 /* cmd_mbox_sw2hw_eq_int_msix 1221 * When set, MSI-X cycles will be generated by this EQ. 1222 * When cleared, an interrupt will be generated by this EQ. 1223 */ 1224 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1225 1226 /* cmd_mbox_sw2hw_eq_st 1227 * Event delivery state machine 1228 * 0x0 - FIRED 1229 * 0x1 - ARMED (Request for Notification) 1230 * 0x11 - Always ARMED 1231 * other - reserved 1232 */ 1233 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1234 1235 /* cmd_mbox_sw2hw_eq_log_eq_size 1236 * Log (base 2) of the EQ size (in entries). 1237 */ 1238 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1239 1240 /* cmd_mbox_sw2hw_eq_producer_counter 1241 * Producer Counter. The counter is incremented for each EQE that is written 1242 * by the HW to the EQ. 1243 * Maintained by HW (valid for the QUERY_EQ command only) 1244 */ 1245 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1246 1247 /* cmd_mbox_sw2hw_eq_pa 1248 * Physical Address. 1249 */ 1250 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1251 1252 /* HW2SW_EQ - Hardware to Software EQ 1253 * ---------------------------------- 1254 * OpMod == 0 (N/A), INMmod == EQ number 1255 * ------------------------------------- 1256 */ 1257 1258 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1259 u32 eq_number) 1260 { 1261 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1262 0, eq_number); 1263 } 1264 1265 /* QUERY_EQ - Query EQ 1266 * ---------------------------------- 1267 * OpMod == 0 (N/A), INMmod == EQ number 1268 * ------------------------------------- 1269 * 1270 * Note: Output mailbox has the same format as SW2HW_EQ. 1271 */ 1272 1273 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1274 char *out_mbox, u32 eq_number) 1275 { 1276 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1277 0, eq_number, false, 1278 out_mbox, MLXSW_CMD_MBOX_SIZE); 1279 } 1280 1281 #endif 1282