1f92e1869SDavid Thompson /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2f92e1869SDavid Thompson 3f92e1869SDavid Thompson /* Header file for Mellanox BlueField GigE register defines 4f92e1869SDavid Thompson * 5f92e1869SDavid Thompson * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES 6f92e1869SDavid Thompson */ 7f92e1869SDavid Thompson 8f92e1869SDavid Thompson #ifndef __MLXBF_GIGE_REGS_H__ 9f92e1869SDavid Thompson #define __MLXBF_GIGE_REGS_H__ 10f92e1869SDavid Thompson 113a1a274eSDavid Thompson #define MLXBF_GIGE_VERSION 0x0000 123a1a274eSDavid Thompson #define MLXBF_GIGE_VERSION_BF2 0x0 13*2321d69fSDavid Thompson #define MLXBF_GIGE_VERSION_BF3 0x1 14f92e1869SDavid Thompson #define MLXBF_GIGE_STATUS 0x0010 15f92e1869SDavid Thompson #define MLXBF_GIGE_STATUS_READY BIT(0) 16f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS 0x0028 17f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0) 18f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_RX_MAC_ERROR BIT(1) 19f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_RX_TRN_ERROR BIT(2) 20f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_SW_ACCESS_ERROR BIT(3) 21f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_SW_CONFIG_ERROR BIT(4) 22f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_TX_PI_CI_EXCEED_WQ_SIZE BIT(5) 23f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_TX_SMALL_FRAME_SIZE BIT(6) 24f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_TX_CHECKSUM_INPUTS BIT(7) 25f92e1869SDavid Thompson #define MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR BIT(8) 26f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN 0x0030 27f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0) 28f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_RX_MAC_ERROR BIT(1) 29f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_RX_TRN_ERROR BIT(2) 30f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR BIT(3) 31f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR BIT(4) 32f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE BIT(5) 33f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE BIT(6) 34f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS BIT(7) 35f92e1869SDavid Thompson #define MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR BIT(8) 36f92e1869SDavid Thompson #define MLXBF_GIGE_INT_MASK 0x0038 37f92e1869SDavid Thompson #define MLXBF_GIGE_INT_MASK_RX_RECEIVE_PACKET BIT(0) 38f92e1869SDavid Thompson #define MLXBF_GIGE_CONTROL 0x0040 39f92e1869SDavid Thompson #define MLXBF_GIGE_CONTROL_PORT_EN BIT(0) 40f92e1869SDavid Thompson #define MLXBF_GIGE_CONTROL_MAC_ID_RANGE_EN BIT(1) 41f92e1869SDavid Thompson #define MLXBF_GIGE_CONTROL_EN_SPECIFIC_MAC BIT(4) 42f92e1869SDavid Thompson #define MLXBF_GIGE_CONTROL_CLEAN_PORT_EN BIT(31) 43f92e1869SDavid Thompson #define MLXBF_GIGE_RX_WQ_BASE 0x0200 44f92e1869SDavid Thompson #define MLXBF_GIGE_RX_WQE_SIZE_LOG2 0x0208 45f92e1869SDavid Thompson #define MLXBF_GIGE_RX_WQE_SIZE_LOG2_RESET_VAL 7 46f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQ_BASE 0x0210 47f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQ_BASE 0x0218 48f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQ_SIZE_LOG2 0x0220 49f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQ_SIZE_LOG2_RESET_VAL 7 50f92e1869SDavid Thompson #define MLXBF_GIGE_TX_CI_UPDATE_ADDRESS 0x0228 51f92e1869SDavid Thompson #define MLXBF_GIGE_RX_WQE_PI 0x0230 52f92e1869SDavid Thompson #define MLXBF_GIGE_TX_PRODUCER_INDEX 0x0238 53f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER 0x0240 54f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_STRIDE 0x0008 55f92e1869SDavid Thompson #define MLXBF_GIGE_RX_DIN_DROP_COUNTER 0x0260 56f92e1869SDavid Thompson #define MLXBF_GIGE_TX_CONSUMER_INDEX 0x0310 57f92e1869SDavid Thompson #define MLXBF_GIGE_TX_CONTROL 0x0318 58f92e1869SDavid Thompson #define MLXBF_GIGE_TX_CONTROL_GRACEFUL_STOP BIT(0) 59f92e1869SDavid Thompson #define MLXBF_GIGE_TX_STATUS 0x0388 60f92e1869SDavid Thompson #define MLXBF_GIGE_TX_STATUS_DATA_FIFO_FULL BIT(1) 61f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START 0x0520 62f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END 0x0528 63f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC 0x0540 64f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN BIT(0) 65f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS 0x0548 66f92e1869SDavid Thompson #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN BIT(0) 67f92e1869SDavid Thompson #define MLXBF_GIGE_RX_PASS_COUNTER_ALL 0x0550 68f92e1869SDavid Thompson #define MLXBF_GIGE_RX_DISC_COUNTER_ALL 0x0560 69f92e1869SDavid Thompson #define MLXBF_GIGE_RX 0x0578 70f92e1869SDavid Thompson #define MLXBF_GIGE_RX_STRIP_CRC_EN BIT(1) 71f92e1869SDavid Thompson #define MLXBF_GIGE_RX_DMA 0x0580 72f92e1869SDavid Thompson #define MLXBF_GIGE_RX_DMA_EN BIT(0) 73f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_PACKET_CI 0x05b0 74f92e1869SDavid Thompson #define MLXBF_GIGE_MAC_CFG 0x05e8 75f92e1869SDavid Thompson 76f92e1869SDavid Thompson /* NOTE: MLXBF_GIGE_MAC_CFG is the last defined register offset, 77f92e1869SDavid Thompson * so use that plus size of single register to derive total size 78f92e1869SDavid Thompson */ 79f92e1869SDavid Thompson #define MLXBF_GIGE_MMIO_REG_SZ (MLXBF_GIGE_MAC_CFG + 8) 80f92e1869SDavid Thompson 81f92e1869SDavid Thompson #endif /* !defined(__MLXBF_GIGE_REGS_H__) */ 82