1*2321d69fSDavid Thompson /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2*2321d69fSDavid Thompson 3*2321d69fSDavid Thompson /* MDIO support for Mellanox Gigabit Ethernet driver 4*2321d69fSDavid Thompson * 5*2321d69fSDavid Thompson * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED. 6*2321d69fSDavid Thompson * 7*2321d69fSDavid Thompson * This software product is a proprietary product of NVIDIA CORPORATION & 8*2321d69fSDavid Thompson * AFFILIATES (the "Company") and all right, title, and interest in and to the 9*2321d69fSDavid Thompson * software product, including all associated intellectual property rights, are 10*2321d69fSDavid Thompson * and shall remain exclusively with the Company. 11*2321d69fSDavid Thompson * 12*2321d69fSDavid Thompson * This software product is governed by the End User License Agreement 13*2321d69fSDavid Thompson * provided with the software product. 14*2321d69fSDavid Thompson */ 15*2321d69fSDavid Thompson 16*2321d69fSDavid Thompson #ifndef __MLXBF_GIGE_MDIO_BF3_H__ 17*2321d69fSDavid Thompson #define __MLXBF_GIGE_MDIO_BF3_H__ 18*2321d69fSDavid Thompson 19*2321d69fSDavid Thompson #include <linux/bitfield.h> 20*2321d69fSDavid Thompson 21*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_OFFSET 0x80 22*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_DATA_READ 0x8c 23*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_REG0 0x100 24*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_REG1 0x104 25*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_REG2 0x108 26*2321d69fSDavid Thompson 27*2321d69fSDavid Thompson /* MDIO GW register bits */ 28*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_ST1_MASK GENMASK(1, 1) 29*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_OPCODE_MASK GENMASK(3, 2) 30*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_PARTAD_MASK GENMASK(8, 4) 31*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_DEVAD_MASK GENMASK(13, 9) 32*2321d69fSDavid Thompson /* For BlueField-3, this field is only used for mdio write */ 33*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_DATA_MASK GENMASK(29, 14) 34*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30) 35*2321d69fSDavid Thompson 36*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK GENMASK(15, 0) 37*2321d69fSDavid Thompson 38*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_ST1_SHIFT 1 39*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT 2 40*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT 4 41*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT 9 42*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_DATA_SHIFT 14 43*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT 30 44*2321d69fSDavid Thompson 45*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT 0 46*2321d69fSDavid Thompson 47*2321d69fSDavid Thompson /* MDIO config register bits */ 48*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0) 49*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(2, 2) 50*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(7, 0) 51*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(7, 0) 52*2321d69fSDavid Thompson #define MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(15, 8) 53*2321d69fSDavid Thompson 54*2321d69fSDavid Thompson #endif /* __MLXBF_GIGE_MDIO_BF3_H__ */ 55