1*2321d69fSDavid Thompson /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2*2321d69fSDavid Thompson 3*2321d69fSDavid Thompson /* MDIO support for Mellanox Gigabit Ethernet driver 4*2321d69fSDavid Thompson * 5*2321d69fSDavid Thompson * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED. 6*2321d69fSDavid Thompson * 7*2321d69fSDavid Thompson * This software product is a proprietary product of NVIDIA CORPORATION & 8*2321d69fSDavid Thompson * AFFILIATES (the "Company") and all right, title, and interest in and to the 9*2321d69fSDavid Thompson * software product, including all associated intellectual property rights, are 10*2321d69fSDavid Thompson * and shall remain exclusively with the Company. 11*2321d69fSDavid Thompson * 12*2321d69fSDavid Thompson * This software product is governed by the End User License Agreement 13*2321d69fSDavid Thompson * provided with the software product. 14*2321d69fSDavid Thompson */ 15*2321d69fSDavid Thompson 16*2321d69fSDavid Thompson #ifndef __MLXBF_GIGE_MDIO_BF2_H__ 17*2321d69fSDavid Thompson #define __MLXBF_GIGE_MDIO_BF2_H__ 18*2321d69fSDavid Thompson 19*2321d69fSDavid Thompson #include <linux/bitfield.h> 20*2321d69fSDavid Thompson 21*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_OFFSET 0x0 22*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_OFFSET 0x4 23*2321d69fSDavid Thompson 24*2321d69fSDavid Thompson /* MDIO GW register bits */ 25*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_AD_MASK GENMASK(15, 0) 26*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_DEVAD_MASK GENMASK(20, 16) 27*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_PARTAD_MASK GENMASK(25, 21) 28*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_OPCODE_MASK GENMASK(27, 26) 29*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_ST1_MASK GENMASK(28, 28) 30*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_BUSY_MASK GENMASK(30, 30) 31*2321d69fSDavid Thompson 32*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_AD_SHIFT 0 33*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT 16 34*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT 21 35*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT 26 36*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_ST1_SHIFT 28 37*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT 30 38*2321d69fSDavid Thompson 39*2321d69fSDavid Thompson /* MDIO config register bits */ 40*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0) 41*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK GENMASK(2, 2) 42*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK GENMASK(4, 4) 43*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(15, 8) 44*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(23, 16) 45*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK GENMASK(31, 24) 46*2321d69fSDavid Thompson 47*2321d69fSDavid Thompson #define MLXBF2_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \ 48*2321d69fSDavid Thompson FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \ 49*2321d69fSDavid Thompson FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \ 50*2321d69fSDavid Thompson FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \ 51*2321d69fSDavid Thompson FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13)) 52*2321d69fSDavid Thompson 53*2321d69fSDavid Thompson #endif /* __MLXBF_GIGE_MDIO_BF2_H__ */ 54