1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
2 
3 /* Header file for Gigabit Ethernet driver for Mellanox BlueField SoC
4  * - this file contains software data structures and any chip-specific
5  *   data structures (e.g. TX WQE format) that are memory resident.
6  *
7  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
8  */
9 
10 #ifndef __MLXBF_GIGE_H__
11 #define __MLXBF_GIGE_H__
12 
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/irqreturn.h>
15 #include <linux/netdevice.h>
16 #include <linux/irq.h>
17 #include <linux/phy.h>
18 
19 /* The silicon design supports a maximum RX ring size of
20  * 32K entries. Based on current testing this maximum size
21  * is not required to be supported.  Instead the RX ring
22  * will be capped at a realistic value of 1024 entries.
23  */
24 #define MLXBF_GIGE_MIN_RXQ_SZ     32
25 #define MLXBF_GIGE_MAX_RXQ_SZ     1024
26 #define MLXBF_GIGE_DEFAULT_RXQ_SZ 128
27 
28 #define MLXBF_GIGE_MIN_TXQ_SZ     4
29 #define MLXBF_GIGE_MAX_TXQ_SZ     256
30 #define MLXBF_GIGE_DEFAULT_TXQ_SZ 128
31 
32 #define MLXBF_GIGE_DEFAULT_BUF_SZ 2048
33 
34 #define MLXBF_GIGE_DMA_PAGE_SZ    4096
35 #define MLXBF_GIGE_DMA_PAGE_SHIFT 12
36 
37 /* There are four individual MAC RX filters. Currently
38  * two of them are being used: one for the broadcast MAC
39  * (index 0) and one for local MAC (index 1)
40  */
41 #define MLXBF_GIGE_BCAST_MAC_FILTER_IDX 0
42 #define MLXBF_GIGE_LOCAL_MAC_FILTER_IDX 1
43 
44 /* Define for broadcast MAC literal */
45 #define BCAST_MAC_ADDR 0xFFFFFFFFFFFF
46 
47 /* There are three individual interrupts:
48  *   1) Errors, "OOB" interrupt line
49  *   2) Receive Packet, "OOB_LLU" interrupt line
50  *   3) LLU and PLU Events, "OOB_PLU" interrupt line
51  */
52 #define MLXBF_GIGE_ERROR_INTR_IDX       0
53 #define MLXBF_GIGE_RECEIVE_PKT_INTR_IDX 1
54 #define MLXBF_GIGE_LLU_PLU_INTR_IDX     2
55 
56 struct mlxbf_gige_stats {
57 	u64 hw_access_errors;
58 	u64 tx_invalid_checksums;
59 	u64 tx_small_frames;
60 	u64 tx_index_errors;
61 	u64 sw_config_errors;
62 	u64 sw_access_errors;
63 	u64 rx_truncate_errors;
64 	u64 rx_mac_errors;
65 	u64 rx_din_dropped_pkts;
66 	u64 tx_fifo_full;
67 	u64 rx_filter_passed_pkts;
68 	u64 rx_filter_discard_pkts;
69 };
70 
71 struct mlxbf_gige_reg_param {
72 	u32 mask;
73 	u32 shift;
74 };
75 
76 struct mlxbf_gige_mdio_gw {
77 	u32 gw_address;
78 	u32 read_data_address;
79 	struct mlxbf_gige_reg_param busy;
80 	struct mlxbf_gige_reg_param write_data;
81 	struct mlxbf_gige_reg_param read_data;
82 	struct mlxbf_gige_reg_param devad;
83 	struct mlxbf_gige_reg_param partad;
84 	struct mlxbf_gige_reg_param opcode;
85 	struct mlxbf_gige_reg_param st1;
86 };
87 
88 struct mlxbf_gige_link_cfg {
89 	void (*set_phy_link_mode)(struct phy_device *phydev);
90 	void (*adjust_link)(struct net_device *netdev);
91 	phy_interface_t phy_mode;
92 };
93 
94 struct mlxbf_gige {
95 	void __iomem *base;
96 	void __iomem *llu_base;
97 	void __iomem *plu_base;
98 	struct device *dev;
99 	struct net_device *netdev;
100 	struct platform_device *pdev;
101 	void __iomem *mdio_io;
102 	void __iomem *clk_io;
103 	struct mii_bus *mdiobus;
104 	spinlock_t lock;      /* for packet processing indices */
105 	u16 rx_q_entries;
106 	u16 tx_q_entries;
107 	u64 *tx_wqe_base;
108 	dma_addr_t tx_wqe_base_dma;
109 	u64 *tx_wqe_next;
110 	u64 *tx_cc;
111 	dma_addr_t tx_cc_dma;
112 	dma_addr_t *rx_wqe_base;
113 	dma_addr_t rx_wqe_base_dma;
114 	u64 *rx_cqe_base;
115 	dma_addr_t rx_cqe_base_dma;
116 	u16 tx_pi;
117 	u16 prev_tx_ci;
118 	struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ];
119 	struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ];
120 	int error_irq;
121 	int rx_irq;
122 	int llu_plu_irq;
123 	int phy_irq;
124 	int hw_phy_irq;
125 	bool promisc_enabled;
126 	u8 valid_polarity;
127 	struct napi_struct napi;
128 	struct mlxbf_gige_stats stats;
129 	u8 hw_version;
130 	struct mlxbf_gige_mdio_gw *mdio_gw;
131 	int prev_speed;
132 };
133 
134 /* Rx Work Queue Element definitions */
135 #define MLXBF_GIGE_RX_WQE_SZ                   8
136 
137 /* Rx Completion Queue Element definitions */
138 #define MLXBF_GIGE_RX_CQE_SZ                   8
139 #define MLXBF_GIGE_RX_CQE_PKT_LEN_MASK         GENMASK(10, 0)
140 #define MLXBF_GIGE_RX_CQE_VALID_MASK           GENMASK(11, 11)
141 #define MLXBF_GIGE_RX_CQE_PKT_STATUS_MASK      GENMASK(15, 12)
142 #define MLXBF_GIGE_RX_CQE_PKT_STATUS_MAC_ERR   GENMASK(12, 12)
143 #define MLXBF_GIGE_RX_CQE_PKT_STATUS_TRUNCATED GENMASK(13, 13)
144 #define MLXBF_GIGE_RX_CQE_CHKSUM_MASK          GENMASK(31, 16)
145 
146 /* Tx Work Queue Element definitions */
147 #define MLXBF_GIGE_TX_WQE_SZ_QWORDS            2
148 #define MLXBF_GIGE_TX_WQE_SZ                   16
149 #define MLXBF_GIGE_TX_WQE_PKT_LEN_MASK         GENMASK(10, 0)
150 #define MLXBF_GIGE_TX_WQE_UPDATE_MASK          GENMASK(31, 31)
151 #define MLXBF_GIGE_TX_WQE_CHKSUM_LEN_MASK      GENMASK(42, 32)
152 #define MLXBF_GIGE_TX_WQE_CHKSUM_START_MASK    GENMASK(55, 48)
153 #define MLXBF_GIGE_TX_WQE_CHKSUM_OFFSET_MASK   GENMASK(63, 56)
154 
155 /* Macro to return packet length of specified TX WQE */
156 #define MLXBF_GIGE_TX_WQE_PKT_LEN(tx_wqe_addr) \
157 	(*((tx_wqe_addr) + 1) & MLXBF_GIGE_TX_WQE_PKT_LEN_MASK)
158 
159 /* Tx Completion Count */
160 #define MLXBF_GIGE_TX_CC_SZ                    8
161 
162 /* List of resources in ACPI table */
163 enum mlxbf_gige_res {
164 	MLXBF_GIGE_RES_MAC,
165 	MLXBF_GIGE_RES_MDIO9,
166 	MLXBF_GIGE_RES_GPIO0,
167 	MLXBF_GIGE_RES_LLU,
168 	MLXBF_GIGE_RES_PLU,
169 	MLXBF_GIGE_RES_CLK
170 };
171 
172 /* Version of register data returned by mlxbf_gige_get_regs() */
173 #define MLXBF_GIGE_REGS_VERSION 1
174 
175 int mlxbf_gige_mdio_probe(struct platform_device *pdev,
176 			  struct mlxbf_gige *priv);
177 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv);
178 irqreturn_t mlxbf_gige_mdio_handle_phy_interrupt(int irq, void *dev_id);
179 void mlxbf_gige_mdio_enable_phy_int(struct mlxbf_gige *priv);
180 
181 void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv,
182 				  unsigned int index, u64 dmac);
183 void mlxbf_gige_get_mac_rx_filter(struct mlxbf_gige *priv,
184 				  unsigned int index, u64 *dmac);
185 void mlxbf_gige_enable_promisc(struct mlxbf_gige *priv);
186 void mlxbf_gige_disable_promisc(struct mlxbf_gige *priv);
187 int mlxbf_gige_rx_init(struct mlxbf_gige *priv);
188 void mlxbf_gige_rx_deinit(struct mlxbf_gige *priv);
189 int mlxbf_gige_tx_init(struct mlxbf_gige *priv);
190 void mlxbf_gige_tx_deinit(struct mlxbf_gige *priv);
191 bool mlxbf_gige_handle_tx_complete(struct mlxbf_gige *priv);
192 netdev_tx_t mlxbf_gige_start_xmit(struct sk_buff *skb,
193 				  struct net_device *netdev);
194 struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv,
195 				     unsigned int map_len,
196 				     dma_addr_t *buf_dma,
197 				     enum dma_data_direction dir);
198 int mlxbf_gige_request_irqs(struct mlxbf_gige *priv);
199 void mlxbf_gige_free_irqs(struct mlxbf_gige *priv);
200 int mlxbf_gige_poll(struct napi_struct *napi, int budget);
201 extern const struct ethtool_ops mlxbf_gige_ethtool_ops;
202 void mlxbf_gige_update_tx_wqe_next(struct mlxbf_gige *priv);
203 
204 #endif /* !defined(__MLXBF_GIGE_H__) */
205