1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2019, Mellanox Technologies */ 3 4 #ifndef _DR_TYPES_ 5 #define _DR_TYPES_ 6 7 #include <linux/mlx5/vport.h> 8 #include <linux/refcount.h> 9 #include "fs_core.h" 10 #include "wq.h" 11 #include "lib/mlx5.h" 12 #include "mlx5_ifc_dr.h" 13 #include "mlx5dr.h" 14 15 #define DR_RULE_MAX_STES 18 16 #define DR_ACTION_MAX_STES 5 17 #define DR_STE_SVLAN 0x1 18 #define DR_STE_CVLAN 0x2 19 #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) 20 #define DR_NUM_OF_FLEX_PARSERS 8 21 #define DR_STE_MAX_FLEX_0_ID 3 22 #define DR_STE_MAX_FLEX_1_ID 7 23 24 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 25 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 26 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 27 28 static inline bool dr_is_flex_parser_0_id(u8 parser_id) 29 { 30 return parser_id <= DR_STE_MAX_FLEX_0_ID; 31 } 32 33 static inline bool dr_is_flex_parser_1_id(u8 parser_id) 34 { 35 return parser_id > DR_STE_MAX_FLEX_0_ID; 36 } 37 38 enum mlx5dr_icm_chunk_size { 39 DR_CHUNK_SIZE_1, 40 DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 41 DR_CHUNK_SIZE_2, 42 DR_CHUNK_SIZE_4, 43 DR_CHUNK_SIZE_8, 44 DR_CHUNK_SIZE_16, 45 DR_CHUNK_SIZE_32, 46 DR_CHUNK_SIZE_64, 47 DR_CHUNK_SIZE_128, 48 DR_CHUNK_SIZE_256, 49 DR_CHUNK_SIZE_512, 50 DR_CHUNK_SIZE_1K, 51 DR_CHUNK_SIZE_2K, 52 DR_CHUNK_SIZE_4K, 53 DR_CHUNK_SIZE_8K, 54 DR_CHUNK_SIZE_16K, 55 DR_CHUNK_SIZE_32K, 56 DR_CHUNK_SIZE_64K, 57 DR_CHUNK_SIZE_128K, 58 DR_CHUNK_SIZE_256K, 59 DR_CHUNK_SIZE_512K, 60 DR_CHUNK_SIZE_1024K, 61 DR_CHUNK_SIZE_2048K, 62 DR_CHUNK_SIZE_MAX, 63 }; 64 65 enum mlx5dr_icm_type { 66 DR_ICM_TYPE_STE, 67 DR_ICM_TYPE_MODIFY_ACTION, 68 }; 69 70 static inline enum mlx5dr_icm_chunk_size 71 mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 72 { 73 chunk += 2; 74 if (chunk < DR_CHUNK_SIZE_MAX) 75 return chunk; 76 77 return DR_CHUNK_SIZE_MAX; 78 } 79 80 enum { 81 DR_STE_SIZE = 64, 82 DR_STE_SIZE_CTRL = 32, 83 DR_STE_SIZE_TAG = 16, 84 DR_STE_SIZE_MASK = 16, 85 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 86 }; 87 88 enum mlx5dr_ste_ctx_action_cap { 89 DR_STE_CTX_ACTION_CAP_NONE = 0, 90 DR_STE_CTX_ACTION_CAP_TX_POP = 1 << 0, 91 DR_STE_CTX_ACTION_CAP_RX_PUSH = 1 << 1, 92 DR_STE_CTX_ACTION_CAP_RX_ENCAP = 1 << 2, 93 }; 94 95 enum { 96 DR_MODIFY_ACTION_SIZE = 8, 97 }; 98 99 enum mlx5dr_matcher_criteria { 100 DR_MATCHER_CRITERIA_EMPTY = 0, 101 DR_MATCHER_CRITERIA_OUTER = 1 << 0, 102 DR_MATCHER_CRITERIA_MISC = 1 << 1, 103 DR_MATCHER_CRITERIA_INNER = 1 << 2, 104 DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 105 DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 106 DR_MATCHER_CRITERIA_MISC4 = 1 << 5, 107 DR_MATCHER_CRITERIA_MAX = 1 << 6, 108 }; 109 110 enum mlx5dr_action_type { 111 DR_ACTION_TYP_TNL_L2_TO_L2, 112 DR_ACTION_TYP_L2_TO_TNL_L2, 113 DR_ACTION_TYP_TNL_L3_TO_L2, 114 DR_ACTION_TYP_L2_TO_TNL_L3, 115 DR_ACTION_TYP_DROP, 116 DR_ACTION_TYP_QP, 117 DR_ACTION_TYP_FT, 118 DR_ACTION_TYP_CTR, 119 DR_ACTION_TYP_TAG, 120 DR_ACTION_TYP_MODIFY_HDR, 121 DR_ACTION_TYP_VPORT, 122 DR_ACTION_TYP_POP_VLAN, 123 DR_ACTION_TYP_PUSH_VLAN, 124 DR_ACTION_TYP_INSERT_HDR, 125 DR_ACTION_TYP_REMOVE_HDR, 126 DR_ACTION_TYP_SAMPLER, 127 DR_ACTION_TYP_MAX, 128 }; 129 130 enum mlx5dr_ipv { 131 DR_RULE_IPV4, 132 DR_RULE_IPV6, 133 DR_RULE_IPV_MAX, 134 }; 135 136 struct mlx5dr_icm_pool; 137 struct mlx5dr_icm_chunk; 138 struct mlx5dr_icm_buddy_mem; 139 struct mlx5dr_ste_htbl; 140 struct mlx5dr_match_param; 141 struct mlx5dr_cmd_caps; 142 struct mlx5dr_rule_rx_tx; 143 struct mlx5dr_matcher_rx_tx; 144 struct mlx5dr_ste_ctx; 145 146 struct mlx5dr_ste { 147 u8 *hw_ste; 148 /* refcount: indicates the num of rules that using this ste */ 149 u32 refcount; 150 151 /* attached to the miss_list head at each htbl entry */ 152 struct list_head miss_list_node; 153 154 /* this ste is member of htbl */ 155 struct mlx5dr_ste_htbl *htbl; 156 157 struct mlx5dr_ste_htbl *next_htbl; 158 159 /* The rule this STE belongs to */ 160 struct mlx5dr_rule_rx_tx *rule_rx_tx; 161 162 /* this ste is part of a rule, located in ste's chain */ 163 u8 ste_chain_location; 164 }; 165 166 struct mlx5dr_ste_htbl_ctrl { 167 /* total number of valid entries belonging to this hash table. This 168 * includes the non collision and collision entries 169 */ 170 unsigned int num_of_valid_entries; 171 172 /* total number of collisions entries attached to this table */ 173 unsigned int num_of_collisions; 174 }; 175 176 struct mlx5dr_ste_htbl { 177 u16 lu_type; 178 u16 byte_mask; 179 u32 refcount; 180 struct mlx5dr_icm_chunk *chunk; 181 struct mlx5dr_ste *ste_arr; 182 u8 *hw_ste_arr; 183 184 struct list_head *miss_list; 185 186 enum mlx5dr_icm_chunk_size chunk_size; 187 struct mlx5dr_ste *pointing_ste; 188 189 struct mlx5dr_ste_htbl_ctrl ctrl; 190 }; 191 192 struct mlx5dr_ste_send_info { 193 struct mlx5dr_ste *ste; 194 struct list_head send_list; 195 u16 size; 196 u16 offset; 197 u8 data_cont[DR_STE_SIZE]; 198 u8 *data; 199 }; 200 201 void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 202 u16 offset, u8 *data, 203 struct mlx5dr_ste_send_info *ste_info, 204 struct list_head *send_list, 205 bool copy_data); 206 207 struct mlx5dr_ste_build { 208 u8 inner:1; 209 u8 rx:1; 210 u8 vhca_id_valid:1; 211 struct mlx5dr_domain *dmn; 212 struct mlx5dr_cmd_caps *caps; 213 u16 lu_type; 214 u16 byte_mask; 215 u8 bit_mask[DR_STE_SIZE_MASK]; 216 int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 217 struct mlx5dr_ste_build *sb, 218 u8 *tag); 219 }; 220 221 struct mlx5dr_ste_htbl * 222 mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 223 enum mlx5dr_icm_chunk_size chunk_size, 224 u16 lu_type, u16 byte_mask); 225 226 int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 227 228 static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 229 { 230 htbl->refcount--; 231 if (!htbl->refcount) 232 mlx5dr_ste_htbl_free(htbl); 233 } 234 235 static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 236 { 237 htbl->refcount++; 238 } 239 240 /* STE utils */ 241 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 242 void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, 243 u8 *hw_ste, u64 miss_addr); 244 void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, 245 u8 *hw_ste, u64 icm_addr, u32 ht_size); 246 void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, 247 u8 *hw_ste, 248 struct mlx5dr_ste_htbl *next_htbl); 249 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 250 bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 251 u8 ste_location); 252 u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 253 u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 254 struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 255 256 #define MLX5DR_MAX_VLANS 2 257 258 struct mlx5dr_ste_actions_attr { 259 u32 modify_index; 260 u16 modify_actions; 261 u32 decap_index; 262 u16 decap_actions; 263 u8 decap_with_vlan:1; 264 u64 final_icm_addr; 265 u32 flow_tag; 266 u32 ctr_id; 267 u16 gvmi; 268 u16 hit_gvmi; 269 struct { 270 u32 id; 271 u32 size; 272 u8 param_0; 273 u8 param_1; 274 } reformat; 275 struct { 276 int count; 277 u32 headers[MLX5DR_MAX_VLANS]; 278 } vlans; 279 }; 280 281 void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, 282 struct mlx5dr_domain *dmn, 283 u8 *action_type_set, 284 u8 *last_ste, 285 struct mlx5dr_ste_actions_attr *attr, 286 u32 *added_stes); 287 void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, 288 struct mlx5dr_domain *dmn, 289 u8 *action_type_set, 290 u8 *last_ste, 291 struct mlx5dr_ste_actions_attr *attr, 292 u32 *added_stes); 293 294 void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, 295 __be64 *hw_action, 296 u8 hw_field, 297 u8 shifter, 298 u8 length, 299 u32 data); 300 void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, 301 __be64 *hw_action, 302 u8 hw_field, 303 u8 shifter, 304 u8 length, 305 u32 data); 306 void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, 307 __be64 *hw_action, 308 u8 dst_hw_field, 309 u8 dst_shifter, 310 u8 dst_len, 311 u8 src_hw_field, 312 u8 src_shifter); 313 int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, 314 void *data, 315 u32 data_sz, 316 u8 *hw_action, 317 u32 hw_action_sz, 318 u16 *used_hw_action_num); 319 320 const struct mlx5dr_ste_action_modify_field * 321 mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field); 322 323 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); 324 void mlx5dr_ste_free(struct mlx5dr_ste *ste, 325 struct mlx5dr_matcher *matcher, 326 struct mlx5dr_matcher_rx_tx *nic_matcher); 327 static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 328 struct mlx5dr_matcher *matcher, 329 struct mlx5dr_matcher_rx_tx *nic_matcher) 330 { 331 ste->refcount--; 332 if (!ste->refcount) 333 mlx5dr_ste_free(ste, matcher, nic_matcher); 334 } 335 336 /* initial as 0, increased only when ste appears in a new rule */ 337 static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 338 { 339 ste->refcount++; 340 } 341 342 static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste) 343 { 344 return !ste->refcount; 345 } 346 347 bool mlx5dr_ste_equal_tag(void *src, void *dst); 348 int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 349 struct mlx5dr_matcher_rx_tx *nic_matcher, 350 struct mlx5dr_ste *ste, 351 u8 *cur_hw_ste, 352 enum mlx5dr_icm_chunk_size log_table_size); 353 354 /* STE build functions */ 355 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 356 u8 match_criteria, 357 struct mlx5dr_match_param *mask, 358 struct mlx5dr_match_param *value); 359 int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 360 struct mlx5dr_matcher_rx_tx *nic_matcher, 361 struct mlx5dr_match_param *value, 362 u8 *ste_arr); 363 void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, 364 struct mlx5dr_ste_build *builder, 365 struct mlx5dr_match_param *mask, 366 bool inner, bool rx); 367 void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, 368 struct mlx5dr_ste_build *sb, 369 struct mlx5dr_match_param *mask, 370 bool inner, bool rx); 371 void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, 372 struct mlx5dr_ste_build *sb, 373 struct mlx5dr_match_param *mask, 374 bool inner, bool rx); 375 void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, 376 struct mlx5dr_ste_build *sb, 377 struct mlx5dr_match_param *mask, 378 bool inner, bool rx); 379 void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, 380 struct mlx5dr_ste_build *sb, 381 struct mlx5dr_match_param *mask, 382 bool inner, bool rx); 383 void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, 384 struct mlx5dr_ste_build *sb, 385 struct mlx5dr_match_param *mask, 386 bool inner, bool rx); 387 void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, 388 struct mlx5dr_ste_build *sb, 389 struct mlx5dr_match_param *mask, 390 bool inner, bool rx); 391 void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, 392 struct mlx5dr_ste_build *sb, 393 struct mlx5dr_match_param *mask, 394 bool inner, bool rx); 395 void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, 396 struct mlx5dr_ste_build *sb, 397 struct mlx5dr_match_param *mask, 398 bool inner, bool rx); 399 void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, 400 struct mlx5dr_ste_build *sb, 401 struct mlx5dr_match_param *mask, 402 bool inner, bool rx); 403 void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, 404 struct mlx5dr_ste_build *sb, 405 struct mlx5dr_match_param *mask, 406 bool inner, bool rx); 407 void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, 408 struct mlx5dr_ste_build *sb, 409 struct mlx5dr_match_param *mask, 410 bool inner, bool rx); 411 void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, 412 struct mlx5dr_ste_build *sb, 413 struct mlx5dr_match_param *mask, 414 bool inner, bool rx); 415 void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx, 416 struct mlx5dr_ste_build *sb, 417 struct mlx5dr_match_param *mask, 418 struct mlx5dr_cmd_caps *caps, 419 bool inner, bool rx); 420 void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx, 421 struct mlx5dr_ste_build *sb, 422 struct mlx5dr_match_param *mask, 423 struct mlx5dr_cmd_caps *caps, 424 bool inner, bool rx); 425 void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, 426 struct mlx5dr_ste_build *sb, 427 struct mlx5dr_match_param *mask, 428 struct mlx5dr_cmd_caps *caps, 429 bool inner, bool rx); 430 void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, 431 struct mlx5dr_ste_build *sb, 432 struct mlx5dr_match_param *mask, 433 bool inner, bool rx); 434 void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, 435 struct mlx5dr_ste_build *sb, 436 struct mlx5dr_match_param *mask, 437 bool inner, bool rx); 438 void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, 439 struct mlx5dr_ste_build *sb, 440 struct mlx5dr_match_param *mask, 441 struct mlx5dr_cmd_caps *caps, 442 bool inner, bool rx); 443 void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx, 444 struct mlx5dr_ste_build *sb, 445 struct mlx5dr_match_param *mask, 446 bool inner, bool rx); 447 void mlx5dr_ste_build_tnl_gtpu_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 448 struct mlx5dr_ste_build *sb, 449 struct mlx5dr_match_param *mask, 450 struct mlx5dr_cmd_caps *caps, 451 bool inner, bool rx); 452 void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 453 struct mlx5dr_ste_build *sb, 454 struct mlx5dr_match_param *mask, 455 struct mlx5dr_cmd_caps *caps, 456 bool inner, bool rx); 457 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, 458 struct mlx5dr_ste_build *sb, 459 struct mlx5dr_match_param *mask, 460 bool inner, bool rx); 461 void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, 462 struct mlx5dr_ste_build *sb, 463 struct mlx5dr_match_param *mask, 464 bool inner, bool rx); 465 void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, 466 struct mlx5dr_ste_build *sb, 467 struct mlx5dr_match_param *mask, 468 bool inner, bool rx); 469 void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, 470 struct mlx5dr_ste_build *sb, 471 struct mlx5dr_match_param *mask, 472 struct mlx5dr_domain *dmn, 473 bool inner, bool rx); 474 void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 475 struct mlx5dr_ste_build *sb, 476 struct mlx5dr_match_param *mask, 477 bool inner, bool rx); 478 void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 479 struct mlx5dr_ste_build *sb, 480 struct mlx5dr_match_param *mask, 481 bool inner, bool rx); 482 void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 483 484 /* Actions utils */ 485 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 486 struct mlx5dr_matcher_rx_tx *nic_matcher, 487 struct mlx5dr_action *actions[], 488 u32 num_actions, 489 u8 *ste_arr, 490 u32 *new_hw_ste_arr_sz); 491 492 struct mlx5dr_match_spec { 493 u32 smac_47_16; /* Source MAC address of incoming packet */ 494 /* Incoming packet Ethertype - this is the Ethertype 495 * following the last VLAN tag of the packet 496 */ 497 u32 ethertype:16; 498 u32 smac_15_0:16; /* Source MAC address of incoming packet */ 499 u32 dmac_47_16; /* Destination MAC address of incoming packet */ 500 /* VLAN ID of first VLAN tag in the incoming packet. 501 * Valid only when cvlan_tag==1 or svlan_tag==1 502 */ 503 u32 first_vid:12; 504 /* CFI bit of first VLAN tag in the incoming packet. 505 * Valid only when cvlan_tag==1 or svlan_tag==1 506 */ 507 u32 first_cfi:1; 508 /* Priority of first VLAN tag in the incoming packet. 509 * Valid only when cvlan_tag==1 or svlan_tag==1 510 */ 511 u32 first_prio:3; 512 u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 513 /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 514 * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 515 */ 516 u32 tcp_flags:9; 517 u32 ip_version:4; /* IP version */ 518 u32 frag:1; /* Packet is an IP fragment */ 519 /* The first vlan in the packet is s-vlan (0x8a88). 520 * cvlan_tag and svlan_tag cannot be set together 521 */ 522 u32 svlan_tag:1; 523 /* The first vlan in the packet is c-vlan (0x8100). 524 * cvlan_tag and svlan_tag cannot be set together 525 */ 526 u32 cvlan_tag:1; 527 /* Explicit Congestion Notification derived from 528 * Traffic Class/TOS field of IPv6/v4 529 */ 530 u32 ip_ecn:2; 531 /* Differentiated Services Code Point derived from 532 * Traffic Class/TOS field of IPv6/v4 533 */ 534 u32 ip_dscp:6; 535 u32 ip_protocol:8; /* IP protocol */ 536 /* TCP destination port. 537 * tcp and udp sport/dport are mutually exclusive 538 */ 539 u32 tcp_dport:16; 540 /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 541 u32 tcp_sport:16; 542 u32 ttl_hoplimit:8; 543 u32 reserved:24; 544 /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 545 u32 udp_dport:16; 546 /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 547 u32 udp_sport:16; 548 /* IPv6 source address of incoming packets 549 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 550 * This field should be qualified by an appropriate ethertype 551 */ 552 u32 src_ip_127_96; 553 /* IPv6 source address of incoming packets 554 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 555 * This field should be qualified by an appropriate ethertype 556 */ 557 u32 src_ip_95_64; 558 /* IPv6 source address of incoming packets 559 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 560 * This field should be qualified by an appropriate ethertype 561 */ 562 u32 src_ip_63_32; 563 /* IPv6 source address of incoming packets 564 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 565 * This field should be qualified by an appropriate ethertype 566 */ 567 u32 src_ip_31_0; 568 /* IPv6 destination address of incoming packets 569 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 570 * This field should be qualified by an appropriate ethertype 571 */ 572 u32 dst_ip_127_96; 573 /* IPv6 destination address of incoming packets 574 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 575 * This field should be qualified by an appropriate ethertype 576 */ 577 u32 dst_ip_95_64; 578 /* IPv6 destination address of incoming packets 579 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 580 * This field should be qualified by an appropriate ethertype 581 */ 582 u32 dst_ip_63_32; 583 /* IPv6 destination address of incoming packets 584 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 585 * This field should be qualified by an appropriate ethertype 586 */ 587 u32 dst_ip_31_0; 588 }; 589 590 struct mlx5dr_match_misc { 591 u32 source_sqn:24; /* Source SQN */ 592 u32 source_vhca_port:4; 593 /* used with GRE, sequence number exist when gre_s_present == 1 */ 594 u32 gre_s_present:1; 595 /* used with GRE, key exist when gre_k_present == 1 */ 596 u32 gre_k_present:1; 597 u32 reserved_auto1:1; 598 /* used with GRE, checksum exist when gre_c_present == 1 */ 599 u32 gre_c_present:1; 600 /* Source port.;0xffff determines wire port */ 601 u32 source_port:16; 602 u32 source_eswitch_owner_vhca_id:16; 603 /* VLAN ID of first VLAN tag the inner header of the incoming packet. 604 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 605 */ 606 u32 inner_second_vid:12; 607 /* CFI bit of first VLAN tag in the inner header of the incoming packet. 608 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 609 */ 610 u32 inner_second_cfi:1; 611 /* Priority of second VLAN tag in the inner header of the incoming packet. 612 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 613 */ 614 u32 inner_second_prio:3; 615 /* VLAN ID of first VLAN tag the outer header of the incoming packet. 616 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 617 */ 618 u32 outer_second_vid:12; 619 /* CFI bit of first VLAN tag in the outer header of the incoming packet. 620 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 621 */ 622 u32 outer_second_cfi:1; 623 /* Priority of second VLAN tag in the outer header of the incoming packet. 624 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 625 */ 626 u32 outer_second_prio:3; 627 u32 gre_protocol:16; /* GRE Protocol (outer) */ 628 u32 reserved_auto3:12; 629 /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 630 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 631 */ 632 u32 inner_second_svlan_tag:1; 633 /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 634 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 635 */ 636 u32 outer_second_svlan_tag:1; 637 /* The second vlan in the inner header of the packet is c-vlan (0x8100). 638 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 639 */ 640 u32 inner_second_cvlan_tag:1; 641 /* The second vlan in the outer header of the packet is c-vlan (0x8100). 642 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 643 */ 644 u32 outer_second_cvlan_tag:1; 645 u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 646 u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 647 u32 reserved_auto4:8; 648 u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 649 u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 650 u32 reserved_auto5:7; 651 u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 652 u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 653 u32 reserved_auto6:12; 654 u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 655 u32 reserved_auto7:12; 656 u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 657 u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 658 u32 reserved_auto8:10; 659 u32 bth_dst_qp:24; /* Destination QP in BTH header */ 660 u32 reserved_auto9:8; 661 u8 reserved_auto10[20]; 662 }; 663 664 struct mlx5dr_match_misc2 { 665 u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 666 u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 667 u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 668 u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 669 u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 670 u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 671 u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 672 u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 673 u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 674 u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 675 u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 676 u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 677 u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 678 u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 679 u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 680 u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 681 u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 682 u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 683 u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 684 u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 685 u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 686 u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 687 u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 688 u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 689 u32 metadata_reg_a; /* metadata_reg_a */ 690 u8 reserved_auto2[12]; 691 }; 692 693 struct mlx5dr_match_misc3 { 694 u32 inner_tcp_seq_num; 695 u32 outer_tcp_seq_num; 696 u32 inner_tcp_ack_num; 697 u32 outer_tcp_ack_num; 698 u32 outer_vxlan_gpe_vni:24; 699 u32 reserved_auto1:8; 700 u32 reserved_auto2:16; 701 u32 outer_vxlan_gpe_flags:8; 702 u32 outer_vxlan_gpe_next_protocol:8; 703 u32 icmpv4_header_data; 704 u32 icmpv6_header_data; 705 u8 icmpv6_code; 706 u8 icmpv6_type; 707 u8 icmpv4_code; 708 u8 icmpv4_type; 709 u32 geneve_tlv_option_0_data; 710 u8 gtpu_msg_flags; 711 u8 gtpu_msg_type; 712 u32 gtpu_teid; 713 u32 gtpu_dw_2; 714 u32 gtpu_first_ext_dw_0; 715 u32 gtpu_dw_0; 716 }; 717 718 struct mlx5dr_match_misc4 { 719 u32 prog_sample_field_value_0; 720 u32 prog_sample_field_id_0; 721 u32 prog_sample_field_value_1; 722 u32 prog_sample_field_id_1; 723 u32 prog_sample_field_value_2; 724 u32 prog_sample_field_id_2; 725 u32 prog_sample_field_value_3; 726 u32 prog_sample_field_id_3; 727 }; 728 729 struct mlx5dr_match_param { 730 struct mlx5dr_match_spec outer; 731 struct mlx5dr_match_misc misc; 732 struct mlx5dr_match_spec inner; 733 struct mlx5dr_match_misc2 misc2; 734 struct mlx5dr_match_misc3 misc3; 735 struct mlx5dr_match_misc4 misc4; 736 }; 737 738 #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 739 (_misc3)->icmpv4_code || \ 740 (_misc3)->icmpv4_header_data) 741 742 struct mlx5dr_esw_caps { 743 u64 drop_icm_address_rx; 744 u64 drop_icm_address_tx; 745 u64 uplink_icm_address_rx; 746 u64 uplink_icm_address_tx; 747 u8 sw_owner:1; 748 u8 sw_owner_v2:1; 749 }; 750 751 struct mlx5dr_cmd_vport_cap { 752 u16 vport_gvmi; 753 u16 vhca_gvmi; 754 u16 num; 755 u64 icm_address_rx; 756 u64 icm_address_tx; 757 }; 758 759 struct mlx5dr_roce_cap { 760 u8 roce_en:1; 761 u8 fl_rc_qp_when_roce_disabled:1; 762 u8 fl_rc_qp_when_roce_enabled:1; 763 }; 764 765 struct mlx5dr_vports { 766 struct mlx5dr_cmd_vport_cap esw_manager_caps; 767 struct xarray vports_caps_xa; 768 }; 769 770 struct mlx5dr_cmd_caps { 771 u16 gvmi; 772 u64 nic_rx_drop_address; 773 u64 nic_tx_drop_address; 774 u64 nic_tx_allow_address; 775 u64 esw_rx_drop_address; 776 u64 esw_tx_drop_address; 777 u32 log_icm_size; 778 u64 hdr_modify_icm_addr; 779 u32 flex_protocols; 780 u8 flex_parser_id_icmp_dw0; 781 u8 flex_parser_id_icmp_dw1; 782 u8 flex_parser_id_icmpv6_dw0; 783 u8 flex_parser_id_icmpv6_dw1; 784 u8 flex_parser_id_geneve_tlv_option_0; 785 u8 flex_parser_id_mpls_over_gre; 786 u8 flex_parser_id_mpls_over_udp; 787 u8 flex_parser_id_gtpu_dw_0; 788 u8 flex_parser_id_gtpu_teid; 789 u8 flex_parser_id_gtpu_dw_2; 790 u8 flex_parser_id_gtpu_first_ext_dw_0; 791 u8 max_ft_level; 792 u16 roce_min_src_udp; 793 u8 sw_format_ver; 794 bool eswitch_manager; 795 bool rx_sw_owner; 796 bool tx_sw_owner; 797 bool fdb_sw_owner; 798 u8 rx_sw_owner_v2:1; 799 u8 tx_sw_owner_v2:1; 800 u8 fdb_sw_owner_v2:1; 801 struct mlx5dr_esw_caps esw_caps; 802 struct mlx5dr_vports vports; 803 bool prio_tag_required; 804 struct mlx5dr_roce_cap roce_caps; 805 u8 is_ecpf:1; 806 u8 isolate_vl_tc:1; 807 }; 808 809 enum mlx5dr_domain_nic_type { 810 DR_DOMAIN_NIC_TYPE_RX, 811 DR_DOMAIN_NIC_TYPE_TX, 812 }; 813 814 struct mlx5dr_domain_rx_tx { 815 u64 drop_icm_addr; 816 u64 default_icm_addr; 817 enum mlx5dr_domain_nic_type type; 818 struct mutex mutex; /* protect rx/tx domain */ 819 }; 820 821 struct mlx5dr_domain_info { 822 bool supp_sw_steering; 823 u32 max_inline_size; 824 u32 max_send_wr; 825 u32 max_log_sw_icm_sz; 826 u32 max_log_action_icm_sz; 827 struct mlx5dr_domain_rx_tx rx; 828 struct mlx5dr_domain_rx_tx tx; 829 struct mlx5dr_cmd_caps caps; 830 }; 831 832 struct mlx5dr_domain { 833 struct mlx5dr_domain *peer_dmn; 834 struct mlx5_core_dev *mdev; 835 u32 pdn; 836 struct mlx5_uars_page *uar; 837 enum mlx5dr_domain_type type; 838 refcount_t refcount; 839 struct mlx5dr_icm_pool *ste_icm_pool; 840 struct mlx5dr_icm_pool *action_icm_pool; 841 struct mlx5dr_send_ring *send_ring; 842 struct mlx5dr_domain_info info; 843 struct xarray csum_fts_xa; 844 struct mlx5dr_ste_ctx *ste_ctx; 845 }; 846 847 struct mlx5dr_table_rx_tx { 848 struct mlx5dr_ste_htbl *s_anchor; 849 struct mlx5dr_domain_rx_tx *nic_dmn; 850 u64 default_icm_addr; 851 }; 852 853 struct mlx5dr_table { 854 struct mlx5dr_domain *dmn; 855 struct mlx5dr_table_rx_tx rx; 856 struct mlx5dr_table_rx_tx tx; 857 u32 level; 858 u32 table_type; 859 u32 table_id; 860 u32 flags; 861 struct list_head matcher_list; 862 struct mlx5dr_action *miss_action; 863 refcount_t refcount; 864 }; 865 866 struct mlx5dr_matcher_rx_tx { 867 struct mlx5dr_ste_htbl *s_htbl; 868 struct mlx5dr_ste_htbl *e_anchor; 869 struct mlx5dr_ste_build *ste_builder; 870 struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 871 [DR_RULE_IPV_MAX] 872 [DR_RULE_MAX_STES]; 873 u8 num_of_builders; 874 u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 875 u64 default_icm_addr; 876 struct mlx5dr_table_rx_tx *nic_tbl; 877 }; 878 879 struct mlx5dr_matcher { 880 struct mlx5dr_table *tbl; 881 struct mlx5dr_matcher_rx_tx rx; 882 struct mlx5dr_matcher_rx_tx tx; 883 struct list_head matcher_list; 884 u32 prio; 885 struct mlx5dr_match_param mask; 886 u8 match_criteria; 887 refcount_t refcount; 888 struct mlx5dv_flow_matcher *dv_matcher; 889 }; 890 891 struct mlx5dr_ste_action_modify_field { 892 u16 hw_field; 893 u8 start; 894 u8 end; 895 u8 l3_type; 896 u8 l4_type; 897 }; 898 899 struct mlx5dr_action_rewrite { 900 struct mlx5dr_domain *dmn; 901 struct mlx5dr_icm_chunk *chunk; 902 u8 *data; 903 u16 num_of_actions; 904 u32 index; 905 u8 allow_rx:1; 906 u8 allow_tx:1; 907 u8 modify_ttl:1; 908 }; 909 910 struct mlx5dr_action_reformat { 911 struct mlx5dr_domain *dmn; 912 u32 id; 913 u32 size; 914 u8 param_0; 915 u8 param_1; 916 }; 917 918 struct mlx5dr_action_sampler { 919 struct mlx5dr_domain *dmn; 920 u64 rx_icm_addr; 921 u64 tx_icm_addr; 922 u32 sampler_id; 923 }; 924 925 struct mlx5dr_action_dest_tbl { 926 u8 is_fw_tbl:1; 927 union { 928 struct mlx5dr_table *tbl; 929 struct { 930 struct mlx5dr_domain *dmn; 931 u32 id; 932 u32 group_id; 933 enum fs_flow_table_type type; 934 u64 rx_icm_addr; 935 u64 tx_icm_addr; 936 struct mlx5dr_action **ref_actions; 937 u32 num_of_ref_actions; 938 } fw_tbl; 939 }; 940 }; 941 942 struct mlx5dr_action_ctr { 943 u32 ctr_id; 944 u32 offset; 945 }; 946 947 struct mlx5dr_action_vport { 948 struct mlx5dr_domain *dmn; 949 struct mlx5dr_cmd_vport_cap *caps; 950 }; 951 952 struct mlx5dr_action_push_vlan { 953 u32 vlan_hdr; /* tpid_pcp_dei_vid */ 954 }; 955 956 struct mlx5dr_action_flow_tag { 957 u32 flow_tag; 958 }; 959 960 struct mlx5dr_action { 961 enum mlx5dr_action_type action_type; 962 refcount_t refcount; 963 964 union { 965 void *data; 966 struct mlx5dr_action_rewrite *rewrite; 967 struct mlx5dr_action_reformat *reformat; 968 struct mlx5dr_action_sampler *sampler; 969 struct mlx5dr_action_dest_tbl *dest_tbl; 970 struct mlx5dr_action_ctr *ctr; 971 struct mlx5dr_action_vport *vport; 972 struct mlx5dr_action_push_vlan *push_vlan; 973 struct mlx5dr_action_flow_tag *flow_tag; 974 }; 975 }; 976 977 enum mlx5dr_connect_type { 978 CONNECT_HIT = 1, 979 CONNECT_MISS = 2, 980 }; 981 982 struct mlx5dr_htbl_connect_info { 983 enum mlx5dr_connect_type type; 984 union { 985 struct mlx5dr_ste_htbl *hit_next_htbl; 986 u64 miss_icm_addr; 987 }; 988 }; 989 990 struct mlx5dr_rule_rx_tx { 991 struct mlx5dr_matcher_rx_tx *nic_matcher; 992 struct mlx5dr_ste *last_rule_ste; 993 }; 994 995 struct mlx5dr_rule { 996 struct mlx5dr_matcher *matcher; 997 struct mlx5dr_rule_rx_tx rx; 998 struct mlx5dr_rule_rx_tx tx; 999 struct list_head rule_actions_list; 1000 u32 flow_source; 1001 }; 1002 1003 void mlx5dr_rule_set_last_member(struct mlx5dr_rule_rx_tx *nic_rule, 1004 struct mlx5dr_ste *ste, 1005 bool force); 1006 int mlx5dr_rule_get_reverse_rule_members(struct mlx5dr_ste **ste_arr, 1007 struct mlx5dr_ste *curr_ste, 1008 int *num_of_stes); 1009 1010 struct mlx5dr_icm_chunk { 1011 struct mlx5dr_icm_buddy_mem *buddy_mem; 1012 struct list_head chunk_list; 1013 u32 rkey; 1014 u32 num_of_entries; 1015 u32 byte_size; 1016 u64 icm_addr; 1017 u64 mr_addr; 1018 1019 /* indicates the index of this chunk in the whole memory, 1020 * used for deleting the chunk from the buddy 1021 */ 1022 unsigned int seg; 1023 1024 /* Memory optimisation */ 1025 struct mlx5dr_ste *ste_arr; 1026 u8 *hw_ste_arr; 1027 struct list_head *miss_list; 1028 }; 1029 1030 static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn) 1031 { 1032 mutex_lock(&nic_dmn->mutex); 1033 } 1034 1035 static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn) 1036 { 1037 mutex_unlock(&nic_dmn->mutex); 1038 } 1039 1040 static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn) 1041 { 1042 mlx5dr_domain_nic_lock(&dmn->info.rx); 1043 mlx5dr_domain_nic_lock(&dmn->info.tx); 1044 } 1045 1046 static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn) 1047 { 1048 mlx5dr_domain_nic_unlock(&dmn->info.tx); 1049 mlx5dr_domain_nic_unlock(&dmn->info.rx); 1050 } 1051 1052 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 1053 struct mlx5dr_matcher_rx_tx *nic_matcher, 1054 enum mlx5dr_ipv outer_ipv, 1055 enum mlx5dr_ipv inner_ipv); 1056 1057 static inline int 1058 mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type) 1059 { 1060 if (icm_type == DR_ICM_TYPE_STE) 1061 return DR_STE_SIZE; 1062 1063 return DR_MODIFY_ACTION_SIZE; 1064 } 1065 1066 static inline u32 1067 mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 1068 { 1069 return 1 << chunk_size; 1070 } 1071 1072 static inline int 1073 mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 1074 enum mlx5dr_icm_type icm_type) 1075 { 1076 int num_of_entries; 1077 int entry_size; 1078 1079 entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type); 1080 num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 1081 1082 return entry_size * num_of_entries; 1083 } 1084 1085 static inline int 1086 mlx5dr_ste_htbl_increase_threshold(struct mlx5dr_ste_htbl *htbl) 1087 { 1088 int num_of_entries = 1089 mlx5dr_icm_pool_chunk_size_to_entries(htbl->chunk_size); 1090 1091 /* Threshold is 50%, one is added to table of size 1 */ 1092 return (num_of_entries + 1) / 2; 1093 } 1094 1095 static inline bool 1096 mlx5dr_ste_htbl_may_grow(struct mlx5dr_ste_htbl *htbl) 1097 { 1098 if (htbl->chunk_size == DR_CHUNK_SIZE_MAX - 1 || !htbl->byte_mask) 1099 return false; 1100 1101 return true; 1102 } 1103 1104 struct mlx5dr_cmd_vport_cap * 1105 mlx5dr_domain_get_vport_cap(struct mlx5dr_domain *dmn, u16 vport); 1106 1107 struct mlx5dr_cmd_query_flow_table_details { 1108 u8 status; 1109 u8 level; 1110 u64 sw_owner_icm_root_1; 1111 u64 sw_owner_icm_root_0; 1112 }; 1113 1114 struct mlx5dr_cmd_create_flow_table_attr { 1115 u32 table_type; 1116 u64 icm_addr_rx; 1117 u64 icm_addr_tx; 1118 u8 level; 1119 bool sw_owner; 1120 bool term_tbl; 1121 bool decap_en; 1122 bool reformat_en; 1123 }; 1124 1125 /* internal API functions */ 1126 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 1127 struct mlx5dr_cmd_caps *caps); 1128 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 1129 bool other_vport, u16 vport_number, 1130 u64 *icm_address_rx, 1131 u64 *icm_address_tx); 1132 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 1133 bool other_vport, u16 vport_number, u16 *gvmi); 1134 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 1135 struct mlx5dr_esw_caps *caps); 1136 int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev, 1137 u32 sampler_id, 1138 u64 *rx_icm_addr, 1139 u64 *tx_icm_addr); 1140 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 1141 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 1142 u32 table_type, 1143 u32 table_id, 1144 u32 group_id, 1145 u32 modify_header_id, 1146 u16 vport_id); 1147 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 1148 u32 table_type, 1149 u32 table_id); 1150 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 1151 u32 table_type, 1152 u8 num_of_actions, 1153 u64 *actions, 1154 u32 *modify_header_id); 1155 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 1156 u32 modify_header_id); 1157 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 1158 u32 table_type, 1159 u32 table_id, 1160 u32 *group_id); 1161 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 1162 u32 table_type, 1163 u32 table_id, 1164 u32 group_id); 1165 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 1166 struct mlx5dr_cmd_create_flow_table_attr *attr, 1167 u64 *fdb_rx_icm_addr, 1168 u32 *table_id); 1169 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 1170 u32 table_id, 1171 u32 table_type); 1172 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 1173 enum fs_flow_table_type type, 1174 u32 table_id, 1175 struct mlx5dr_cmd_query_flow_table_details *output); 1176 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 1177 enum mlx5_reformat_ctx_type rt, 1178 u8 reformat_param_0, 1179 u8 reformat_param_1, 1180 size_t reformat_size, 1181 void *reformat_data, 1182 u32 *reformat_id); 1183 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 1184 u32 reformat_id); 1185 1186 struct mlx5dr_cmd_gid_attr { 1187 u8 gid[16]; 1188 u8 mac[6]; 1189 u32 roce_ver; 1190 }; 1191 1192 struct mlx5dr_cmd_qp_create_attr { 1193 u32 page_id; 1194 u32 pdn; 1195 u32 cqn; 1196 u32 pm_state; 1197 u32 service_type; 1198 u32 buff_umem_id; 1199 u32 db_umem_id; 1200 u32 sq_wqe_cnt; 1201 u32 rq_wqe_cnt; 1202 u32 rq_wqe_shift; 1203 u8 isolate_vl_tc:1; 1204 }; 1205 1206 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 1207 u16 index, struct mlx5dr_cmd_gid_attr *attr); 1208 1209 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 1210 enum mlx5dr_icm_type icm_type); 1211 void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 1212 1213 struct mlx5dr_icm_chunk * 1214 mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 1215 enum mlx5dr_icm_chunk_size chunk_size); 1216 void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 1217 1218 void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, 1219 u8 *hw_ste_p, u32 ste_size); 1220 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 1221 struct mlx5dr_domain_rx_tx *nic_dmn, 1222 struct mlx5dr_ste_htbl *htbl, 1223 struct mlx5dr_htbl_connect_info *connect_info, 1224 bool update_hw_ste); 1225 void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, 1226 u16 gvmi, 1227 enum mlx5dr_domain_nic_type nic_type, 1228 struct mlx5dr_ste_htbl *htbl, 1229 u8 *formatted_ste, 1230 struct mlx5dr_htbl_connect_info *connect_info); 1231 void mlx5dr_ste_copy_param(u8 match_criteria, 1232 struct mlx5dr_match_param *set_param, 1233 struct mlx5dr_match_parameters *mask, 1234 bool clear); 1235 1236 struct mlx5dr_qp { 1237 struct mlx5_core_dev *mdev; 1238 struct mlx5_wq_qp wq; 1239 struct mlx5_uars_page *uar; 1240 struct mlx5_wq_ctrl wq_ctrl; 1241 u32 qpn; 1242 struct { 1243 unsigned int pc; 1244 unsigned int cc; 1245 unsigned int size; 1246 unsigned int *wqe_head; 1247 unsigned int wqe_cnt; 1248 } sq; 1249 struct { 1250 unsigned int pc; 1251 unsigned int cc; 1252 unsigned int size; 1253 unsigned int wqe_cnt; 1254 } rq; 1255 int max_inline_data; 1256 }; 1257 1258 struct mlx5dr_cq { 1259 struct mlx5_core_dev *mdev; 1260 struct mlx5_cqwq wq; 1261 struct mlx5_wq_ctrl wq_ctrl; 1262 struct mlx5_core_cq mcq; 1263 struct mlx5dr_qp *qp; 1264 }; 1265 1266 struct mlx5dr_mr { 1267 struct mlx5_core_dev *mdev; 1268 u32 mkey; 1269 dma_addr_t dma_addr; 1270 void *addr; 1271 size_t size; 1272 }; 1273 1274 #define MAX_SEND_CQE 64 1275 #define MIN_READ_SYNC 64 1276 1277 struct mlx5dr_send_ring { 1278 struct mlx5dr_cq *cq; 1279 struct mlx5dr_qp *qp; 1280 struct mlx5dr_mr *mr; 1281 /* How much wqes are waiting for completion */ 1282 u32 pending_wqe; 1283 /* Signal request per this trash hold value */ 1284 u16 signal_th; 1285 /* Each post_send_size less than max_post_send_size */ 1286 u32 max_post_send_size; 1287 /* manage the send queue */ 1288 u32 tx_head; 1289 void *buf; 1290 u32 buf_size; 1291 u8 sync_buff[MIN_READ_SYNC]; 1292 struct mlx5dr_mr *sync_mr; 1293 spinlock_t lock; /* Protect the data path of the send ring */ 1294 bool err_state; /* send_ring is not usable in err state */ 1295 }; 1296 1297 int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 1298 void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 1299 struct mlx5dr_send_ring *send_ring); 1300 int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 1301 int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 1302 struct mlx5dr_ste *ste, 1303 u8 *data, 1304 u16 size, 1305 u16 offset); 1306 int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 1307 struct mlx5dr_ste_htbl *htbl, 1308 u8 *formatted_ste, u8 *mask); 1309 int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 1310 struct mlx5dr_ste_htbl *htbl, 1311 u8 *ste_init_data, 1312 bool update_hw_ste); 1313 int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 1314 struct mlx5dr_action *action); 1315 1316 struct mlx5dr_cmd_ft_info { 1317 u32 id; 1318 u16 vport; 1319 enum fs_flow_table_type type; 1320 }; 1321 1322 struct mlx5dr_cmd_flow_destination_hw_info { 1323 enum mlx5_flow_destination_type type; 1324 union { 1325 u32 tir_num; 1326 u32 ft_num; 1327 u32 ft_id; 1328 u32 counter_id; 1329 u32 sampler_id; 1330 struct { 1331 u16 num; 1332 u16 vhca_id; 1333 u32 reformat_id; 1334 u8 flags; 1335 } vport; 1336 }; 1337 }; 1338 1339 struct mlx5dr_cmd_fte_info { 1340 u32 dests_size; 1341 u32 index; 1342 struct mlx5_flow_context flow_context; 1343 u32 *val; 1344 struct mlx5_flow_act action; 1345 struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 1346 bool ignore_flow_level; 1347 }; 1348 1349 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 1350 int opmod, int modify_mask, 1351 struct mlx5dr_cmd_ft_info *ft, 1352 u32 group_id, 1353 struct mlx5dr_cmd_fte_info *fte); 1354 1355 bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps); 1356 1357 struct mlx5dr_fw_recalc_cs_ft { 1358 u64 rx_icm_addr; 1359 u32 table_id; 1360 u32 group_id; 1361 u32 modify_hdr_id; 1362 }; 1363 1364 struct mlx5dr_fw_recalc_cs_ft * 1365 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u16 vport_num); 1366 void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 1367 struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 1368 int mlx5dr_domain_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 1369 u16 vport_num, 1370 u64 *rx_icm_addr); 1371 int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 1372 struct mlx5dr_cmd_flow_destination_hw_info *dest, 1373 int num_dest, 1374 bool reformat_req, 1375 u32 *tbl_id, 1376 u32 *group_id, 1377 bool ignore_flow_level); 1378 void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 1379 u32 group_id); 1380 #endif /* _DR_TYPES_H_ */ 1381