1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2019, Mellanox Technologies */ 3 4 #ifndef _DR_TYPES_ 5 #define _DR_TYPES_ 6 7 #include <linux/mlx5/driver.h> 8 #include <linux/refcount.h> 9 #include "fs_core.h" 10 #include "wq.h" 11 #include "lib/mlx5.h" 12 #include "mlx5_ifc_dr.h" 13 #include "mlx5dr.h" 14 15 #define DR_RULE_MAX_STES 18 16 #define DR_ACTION_MAX_STES 5 17 #define WIRE_PORT 0xFFFF 18 #define DR_STE_SVLAN 0x1 19 #define DR_STE_CVLAN 0x2 20 #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) 21 #define DR_NUM_OF_FLEX_PARSERS 8 22 #define DR_STE_MAX_FLEX_0_ID 3 23 #define DR_STE_MAX_FLEX_1_ID 7 24 25 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 26 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 27 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 28 29 static inline bool dr_is_flex_parser_0_id(u8 parser_id) 30 { 31 return parser_id <= DR_STE_MAX_FLEX_0_ID; 32 } 33 34 static inline bool dr_is_flex_parser_1_id(u8 parser_id) 35 { 36 return parser_id > DR_STE_MAX_FLEX_0_ID; 37 } 38 39 enum mlx5dr_icm_chunk_size { 40 DR_CHUNK_SIZE_1, 41 DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 42 DR_CHUNK_SIZE_2, 43 DR_CHUNK_SIZE_4, 44 DR_CHUNK_SIZE_8, 45 DR_CHUNK_SIZE_16, 46 DR_CHUNK_SIZE_32, 47 DR_CHUNK_SIZE_64, 48 DR_CHUNK_SIZE_128, 49 DR_CHUNK_SIZE_256, 50 DR_CHUNK_SIZE_512, 51 DR_CHUNK_SIZE_1K, 52 DR_CHUNK_SIZE_2K, 53 DR_CHUNK_SIZE_4K, 54 DR_CHUNK_SIZE_8K, 55 DR_CHUNK_SIZE_16K, 56 DR_CHUNK_SIZE_32K, 57 DR_CHUNK_SIZE_64K, 58 DR_CHUNK_SIZE_128K, 59 DR_CHUNK_SIZE_256K, 60 DR_CHUNK_SIZE_512K, 61 DR_CHUNK_SIZE_1024K, 62 DR_CHUNK_SIZE_2048K, 63 DR_CHUNK_SIZE_MAX, 64 }; 65 66 enum mlx5dr_icm_type { 67 DR_ICM_TYPE_STE, 68 DR_ICM_TYPE_MODIFY_ACTION, 69 }; 70 71 static inline enum mlx5dr_icm_chunk_size 72 mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 73 { 74 chunk += 2; 75 if (chunk < DR_CHUNK_SIZE_MAX) 76 return chunk; 77 78 return DR_CHUNK_SIZE_MAX; 79 } 80 81 enum { 82 DR_STE_SIZE = 64, 83 DR_STE_SIZE_CTRL = 32, 84 DR_STE_SIZE_TAG = 16, 85 DR_STE_SIZE_MASK = 16, 86 }; 87 88 enum { 89 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 90 }; 91 92 enum mlx5dr_ste_ctx_action_cap { 93 DR_STE_CTX_ACTION_CAP_NONE = 0, 94 DR_STE_CTX_ACTION_CAP_RX_ENCAP = 1 << 0, 95 }; 96 97 enum { 98 DR_MODIFY_ACTION_SIZE = 8, 99 }; 100 101 enum mlx5dr_matcher_criteria { 102 DR_MATCHER_CRITERIA_EMPTY = 0, 103 DR_MATCHER_CRITERIA_OUTER = 1 << 0, 104 DR_MATCHER_CRITERIA_MISC = 1 << 1, 105 DR_MATCHER_CRITERIA_INNER = 1 << 2, 106 DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 107 DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 108 DR_MATCHER_CRITERIA_MISC4 = 1 << 5, 109 DR_MATCHER_CRITERIA_MAX = 1 << 6, 110 }; 111 112 enum mlx5dr_action_type { 113 DR_ACTION_TYP_TNL_L2_TO_L2, 114 DR_ACTION_TYP_L2_TO_TNL_L2, 115 DR_ACTION_TYP_TNL_L3_TO_L2, 116 DR_ACTION_TYP_L2_TO_TNL_L3, 117 DR_ACTION_TYP_DROP, 118 DR_ACTION_TYP_QP, 119 DR_ACTION_TYP_FT, 120 DR_ACTION_TYP_CTR, 121 DR_ACTION_TYP_TAG, 122 DR_ACTION_TYP_MODIFY_HDR, 123 DR_ACTION_TYP_VPORT, 124 DR_ACTION_TYP_POP_VLAN, 125 DR_ACTION_TYP_PUSH_VLAN, 126 DR_ACTION_TYP_INSERT_HDR, 127 DR_ACTION_TYP_SAMPLER, 128 DR_ACTION_TYP_MAX, 129 }; 130 131 enum mlx5dr_ipv { 132 DR_RULE_IPV4, 133 DR_RULE_IPV6, 134 DR_RULE_IPV_MAX, 135 }; 136 137 struct mlx5dr_icm_pool; 138 struct mlx5dr_icm_chunk; 139 struct mlx5dr_icm_buddy_mem; 140 struct mlx5dr_ste_htbl; 141 struct mlx5dr_match_param; 142 struct mlx5dr_cmd_caps; 143 struct mlx5dr_matcher_rx_tx; 144 struct mlx5dr_ste_ctx; 145 146 struct mlx5dr_ste { 147 u8 *hw_ste; 148 /* refcount: indicates the num of rules that using this ste */ 149 u32 refcount; 150 151 /* attached to the miss_list head at each htbl entry */ 152 struct list_head miss_list_node; 153 154 /* each rule member that uses this ste attached here */ 155 struct list_head rule_list; 156 157 /* this ste is member of htbl */ 158 struct mlx5dr_ste_htbl *htbl; 159 160 struct mlx5dr_ste_htbl *next_htbl; 161 162 /* this ste is part of a rule, located in ste's chain */ 163 u8 ste_chain_location; 164 }; 165 166 struct mlx5dr_ste_htbl_ctrl { 167 /* total number of valid entries belonging to this hash table. This 168 * includes the non collision and collision entries 169 */ 170 unsigned int num_of_valid_entries; 171 172 /* total number of collisions entries attached to this table */ 173 unsigned int num_of_collisions; 174 unsigned int increase_threshold; 175 u8 may_grow:1; 176 }; 177 178 struct mlx5dr_ste_htbl { 179 u16 lu_type; 180 u16 byte_mask; 181 u32 refcount; 182 struct mlx5dr_icm_chunk *chunk; 183 struct mlx5dr_ste *ste_arr; 184 u8 *hw_ste_arr; 185 186 struct list_head *miss_list; 187 188 enum mlx5dr_icm_chunk_size chunk_size; 189 struct mlx5dr_ste *pointing_ste; 190 191 struct mlx5dr_ste_htbl_ctrl ctrl; 192 }; 193 194 struct mlx5dr_ste_send_info { 195 struct mlx5dr_ste *ste; 196 struct list_head send_list; 197 u16 size; 198 u16 offset; 199 u8 data_cont[DR_STE_SIZE]; 200 u8 *data; 201 }; 202 203 void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 204 u16 offset, u8 *data, 205 struct mlx5dr_ste_send_info *ste_info, 206 struct list_head *send_list, 207 bool copy_data); 208 209 struct mlx5dr_ste_build { 210 u8 inner:1; 211 u8 rx:1; 212 u8 vhca_id_valid:1; 213 struct mlx5dr_domain *dmn; 214 struct mlx5dr_cmd_caps *caps; 215 u16 lu_type; 216 u16 byte_mask; 217 u8 bit_mask[DR_STE_SIZE_MASK]; 218 int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 219 struct mlx5dr_ste_build *sb, 220 u8 *tag); 221 }; 222 223 struct mlx5dr_ste_htbl * 224 mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 225 enum mlx5dr_icm_chunk_size chunk_size, 226 u16 lu_type, u16 byte_mask); 227 228 int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 229 230 static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 231 { 232 htbl->refcount--; 233 if (!htbl->refcount) 234 mlx5dr_ste_htbl_free(htbl); 235 } 236 237 static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 238 { 239 htbl->refcount++; 240 } 241 242 /* STE utils */ 243 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 244 void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, 245 u8 *hw_ste, u64 miss_addr); 246 void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, 247 u8 *hw_ste, u64 icm_addr, u32 ht_size); 248 void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, 249 u8 *hw_ste, 250 struct mlx5dr_ste_htbl *next_htbl); 251 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 252 bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 253 u8 ste_location); 254 u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 255 u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 256 struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 257 258 #define MLX5DR_MAX_VLANS 2 259 260 struct mlx5dr_ste_actions_attr { 261 u32 modify_index; 262 u16 modify_actions; 263 u32 decap_index; 264 u16 decap_actions; 265 u8 decap_with_vlan:1; 266 u64 final_icm_addr; 267 u32 flow_tag; 268 u32 ctr_id; 269 u16 gvmi; 270 u16 hit_gvmi; 271 struct { 272 u32 id; 273 u32 size; 274 u8 param_0; 275 u8 param_1; 276 } reformat; 277 struct { 278 int count; 279 u32 headers[MLX5DR_MAX_VLANS]; 280 } vlans; 281 }; 282 283 void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, 284 struct mlx5dr_domain *dmn, 285 u8 *action_type_set, 286 u8 *last_ste, 287 struct mlx5dr_ste_actions_attr *attr, 288 u32 *added_stes); 289 void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, 290 struct mlx5dr_domain *dmn, 291 u8 *action_type_set, 292 u8 *last_ste, 293 struct mlx5dr_ste_actions_attr *attr, 294 u32 *added_stes); 295 296 void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, 297 __be64 *hw_action, 298 u8 hw_field, 299 u8 shifter, 300 u8 length, 301 u32 data); 302 void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, 303 __be64 *hw_action, 304 u8 hw_field, 305 u8 shifter, 306 u8 length, 307 u32 data); 308 void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, 309 __be64 *hw_action, 310 u8 dst_hw_field, 311 u8 dst_shifter, 312 u8 dst_len, 313 u8 src_hw_field, 314 u8 src_shifter); 315 int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, 316 void *data, 317 u32 data_sz, 318 u8 *hw_action, 319 u32 hw_action_sz, 320 u16 *used_hw_action_num); 321 322 const struct mlx5dr_ste_action_modify_field * 323 mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field); 324 325 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); 326 void mlx5dr_ste_free(struct mlx5dr_ste *ste, 327 struct mlx5dr_matcher *matcher, 328 struct mlx5dr_matcher_rx_tx *nic_matcher); 329 static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 330 struct mlx5dr_matcher *matcher, 331 struct mlx5dr_matcher_rx_tx *nic_matcher) 332 { 333 ste->refcount--; 334 if (!ste->refcount) 335 mlx5dr_ste_free(ste, matcher, nic_matcher); 336 } 337 338 /* initial as 0, increased only when ste appears in a new rule */ 339 static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 340 { 341 ste->refcount++; 342 } 343 344 static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste) 345 { 346 return !ste->refcount; 347 } 348 349 bool mlx5dr_ste_equal_tag(void *src, void *dst); 350 int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 351 struct mlx5dr_matcher_rx_tx *nic_matcher, 352 struct mlx5dr_ste *ste, 353 u8 *cur_hw_ste, 354 enum mlx5dr_icm_chunk_size log_table_size); 355 356 /* STE build functions */ 357 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 358 u8 match_criteria, 359 struct mlx5dr_match_param *mask, 360 struct mlx5dr_match_param *value); 361 int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 362 struct mlx5dr_matcher_rx_tx *nic_matcher, 363 struct mlx5dr_match_param *value, 364 u8 *ste_arr); 365 void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, 366 struct mlx5dr_ste_build *builder, 367 struct mlx5dr_match_param *mask, 368 bool inner, bool rx); 369 void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, 370 struct mlx5dr_ste_build *sb, 371 struct mlx5dr_match_param *mask, 372 bool inner, bool rx); 373 void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, 374 struct mlx5dr_ste_build *sb, 375 struct mlx5dr_match_param *mask, 376 bool inner, bool rx); 377 void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, 378 struct mlx5dr_ste_build *sb, 379 struct mlx5dr_match_param *mask, 380 bool inner, bool rx); 381 void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, 382 struct mlx5dr_ste_build *sb, 383 struct mlx5dr_match_param *mask, 384 bool inner, bool rx); 385 void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, 386 struct mlx5dr_ste_build *sb, 387 struct mlx5dr_match_param *mask, 388 bool inner, bool rx); 389 void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, 390 struct mlx5dr_ste_build *sb, 391 struct mlx5dr_match_param *mask, 392 bool inner, bool rx); 393 void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, 394 struct mlx5dr_ste_build *sb, 395 struct mlx5dr_match_param *mask, 396 bool inner, bool rx); 397 void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, 398 struct mlx5dr_ste_build *sb, 399 struct mlx5dr_match_param *mask, 400 bool inner, bool rx); 401 void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, 402 struct mlx5dr_ste_build *sb, 403 struct mlx5dr_match_param *mask, 404 bool inner, bool rx); 405 void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, 406 struct mlx5dr_ste_build *sb, 407 struct mlx5dr_match_param *mask, 408 bool inner, bool rx); 409 void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, 410 struct mlx5dr_ste_build *sb, 411 struct mlx5dr_match_param *mask, 412 bool inner, bool rx); 413 void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, 414 struct mlx5dr_ste_build *sb, 415 struct mlx5dr_match_param *mask, 416 bool inner, bool rx); 417 void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx, 418 struct mlx5dr_ste_build *sb, 419 struct mlx5dr_match_param *mask, 420 struct mlx5dr_cmd_caps *caps, 421 bool inner, bool rx); 422 void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx, 423 struct mlx5dr_ste_build *sb, 424 struct mlx5dr_match_param *mask, 425 struct mlx5dr_cmd_caps *caps, 426 bool inner, bool rx); 427 void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, 428 struct mlx5dr_ste_build *sb, 429 struct mlx5dr_match_param *mask, 430 struct mlx5dr_cmd_caps *caps, 431 bool inner, bool rx); 432 void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, 433 struct mlx5dr_ste_build *sb, 434 struct mlx5dr_match_param *mask, 435 bool inner, bool rx); 436 void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, 437 struct mlx5dr_ste_build *sb, 438 struct mlx5dr_match_param *mask, 439 bool inner, bool rx); 440 void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, 441 struct mlx5dr_ste_build *sb, 442 struct mlx5dr_match_param *mask, 443 struct mlx5dr_cmd_caps *caps, 444 bool inner, bool rx); 445 void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx, 446 struct mlx5dr_ste_build *sb, 447 struct mlx5dr_match_param *mask, 448 bool inner, bool rx); 449 void mlx5dr_ste_build_tnl_gtpu_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 450 struct mlx5dr_ste_build *sb, 451 struct mlx5dr_match_param *mask, 452 struct mlx5dr_cmd_caps *caps, 453 bool inner, bool rx); 454 void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 455 struct mlx5dr_ste_build *sb, 456 struct mlx5dr_match_param *mask, 457 struct mlx5dr_cmd_caps *caps, 458 bool inner, bool rx); 459 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, 460 struct mlx5dr_ste_build *sb, 461 struct mlx5dr_match_param *mask, 462 bool inner, bool rx); 463 void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, 464 struct mlx5dr_ste_build *sb, 465 struct mlx5dr_match_param *mask, 466 bool inner, bool rx); 467 void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, 468 struct mlx5dr_ste_build *sb, 469 struct mlx5dr_match_param *mask, 470 bool inner, bool rx); 471 void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, 472 struct mlx5dr_ste_build *sb, 473 struct mlx5dr_match_param *mask, 474 struct mlx5dr_domain *dmn, 475 bool inner, bool rx); 476 void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 477 struct mlx5dr_ste_build *sb, 478 struct mlx5dr_match_param *mask, 479 bool inner, bool rx); 480 void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 481 struct mlx5dr_ste_build *sb, 482 struct mlx5dr_match_param *mask, 483 bool inner, bool rx); 484 void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 485 486 /* Actions utils */ 487 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 488 struct mlx5dr_matcher_rx_tx *nic_matcher, 489 struct mlx5dr_action *actions[], 490 u32 num_actions, 491 u8 *ste_arr, 492 u32 *new_hw_ste_arr_sz); 493 494 struct mlx5dr_match_spec { 495 u32 smac_47_16; /* Source MAC address of incoming packet */ 496 /* Incoming packet Ethertype - this is the Ethertype 497 * following the last VLAN tag of the packet 498 */ 499 u32 ethertype:16; 500 u32 smac_15_0:16; /* Source MAC address of incoming packet */ 501 u32 dmac_47_16; /* Destination MAC address of incoming packet */ 502 /* VLAN ID of first VLAN tag in the incoming packet. 503 * Valid only when cvlan_tag==1 or svlan_tag==1 504 */ 505 u32 first_vid:12; 506 /* CFI bit of first VLAN tag in the incoming packet. 507 * Valid only when cvlan_tag==1 or svlan_tag==1 508 */ 509 u32 first_cfi:1; 510 /* Priority of first VLAN tag in the incoming packet. 511 * Valid only when cvlan_tag==1 or svlan_tag==1 512 */ 513 u32 first_prio:3; 514 u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 515 /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 516 * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 517 */ 518 u32 tcp_flags:9; 519 u32 ip_version:4; /* IP version */ 520 u32 frag:1; /* Packet is an IP fragment */ 521 /* The first vlan in the packet is s-vlan (0x8a88). 522 * cvlan_tag and svlan_tag cannot be set together 523 */ 524 u32 svlan_tag:1; 525 /* The first vlan in the packet is c-vlan (0x8100). 526 * cvlan_tag and svlan_tag cannot be set together 527 */ 528 u32 cvlan_tag:1; 529 /* Explicit Congestion Notification derived from 530 * Traffic Class/TOS field of IPv6/v4 531 */ 532 u32 ip_ecn:2; 533 /* Differentiated Services Code Point derived from 534 * Traffic Class/TOS field of IPv6/v4 535 */ 536 u32 ip_dscp:6; 537 u32 ip_protocol:8; /* IP protocol */ 538 /* TCP destination port. 539 * tcp and udp sport/dport are mutually exclusive 540 */ 541 u32 tcp_dport:16; 542 /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 543 u32 tcp_sport:16; 544 u32 ttl_hoplimit:8; 545 u32 reserved:24; 546 /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 547 u32 udp_dport:16; 548 /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 549 u32 udp_sport:16; 550 /* IPv6 source address of incoming packets 551 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 552 * This field should be qualified by an appropriate ethertype 553 */ 554 u32 src_ip_127_96; 555 /* IPv6 source address of incoming packets 556 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 557 * This field should be qualified by an appropriate ethertype 558 */ 559 u32 src_ip_95_64; 560 /* IPv6 source address of incoming packets 561 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 562 * This field should be qualified by an appropriate ethertype 563 */ 564 u32 src_ip_63_32; 565 /* IPv6 source address of incoming packets 566 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 567 * This field should be qualified by an appropriate ethertype 568 */ 569 u32 src_ip_31_0; 570 /* IPv6 destination address of incoming packets 571 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 572 * This field should be qualified by an appropriate ethertype 573 */ 574 u32 dst_ip_127_96; 575 /* IPv6 destination address of incoming packets 576 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 577 * This field should be qualified by an appropriate ethertype 578 */ 579 u32 dst_ip_95_64; 580 /* IPv6 destination address of incoming packets 581 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 582 * This field should be qualified by an appropriate ethertype 583 */ 584 u32 dst_ip_63_32; 585 /* IPv6 destination address of incoming packets 586 * For IPv4 address use bits 31:0 (rest of the bits are reserved) 587 * This field should be qualified by an appropriate ethertype 588 */ 589 u32 dst_ip_31_0; 590 }; 591 592 struct mlx5dr_match_misc { 593 u32 source_sqn:24; /* Source SQN */ 594 u32 source_vhca_port:4; 595 /* used with GRE, sequence number exist when gre_s_present == 1 */ 596 u32 gre_s_present:1; 597 /* used with GRE, key exist when gre_k_present == 1 */ 598 u32 gre_k_present:1; 599 u32 reserved_auto1:1; 600 /* used with GRE, checksum exist when gre_c_present == 1 */ 601 u32 gre_c_present:1; 602 /* Source port.;0xffff determines wire port */ 603 u32 source_port:16; 604 u32 source_eswitch_owner_vhca_id:16; 605 /* VLAN ID of first VLAN tag the inner header of the incoming packet. 606 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 607 */ 608 u32 inner_second_vid:12; 609 /* CFI bit of first VLAN tag in the inner header of the incoming packet. 610 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 611 */ 612 u32 inner_second_cfi:1; 613 /* Priority of second VLAN tag in the inner header of the incoming packet. 614 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 615 */ 616 u32 inner_second_prio:3; 617 /* VLAN ID of first VLAN tag the outer header of the incoming packet. 618 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 619 */ 620 u32 outer_second_vid:12; 621 /* CFI bit of first VLAN tag in the outer header of the incoming packet. 622 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 623 */ 624 u32 outer_second_cfi:1; 625 /* Priority of second VLAN tag in the outer header of the incoming packet. 626 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 627 */ 628 u32 outer_second_prio:3; 629 u32 gre_protocol:16; /* GRE Protocol (outer) */ 630 u32 reserved_auto3:12; 631 /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 632 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 633 */ 634 u32 inner_second_svlan_tag:1; 635 /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 636 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 637 */ 638 u32 outer_second_svlan_tag:1; 639 /* The second vlan in the inner header of the packet is c-vlan (0x8100). 640 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 641 */ 642 u32 inner_second_cvlan_tag:1; 643 /* The second vlan in the outer header of the packet is c-vlan (0x8100). 644 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 645 */ 646 u32 outer_second_cvlan_tag:1; 647 u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 648 u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 649 u32 reserved_auto4:8; 650 u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 651 u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 652 u32 reserved_auto5:7; 653 u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 654 u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 655 u32 reserved_auto6:12; 656 u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 657 u32 reserved_auto7:12; 658 u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 659 u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 660 u32 reserved_auto8:10; 661 u32 bth_dst_qp:24; /* Destination QP in BTH header */ 662 u32 reserved_auto9:8; 663 u8 reserved_auto10[20]; 664 }; 665 666 struct mlx5dr_match_misc2 { 667 u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 668 u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 669 u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 670 u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 671 u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 672 u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 673 u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 674 u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 675 u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 676 u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 677 u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 678 u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 679 u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 680 u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 681 u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 682 u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 683 u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 684 u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 685 u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 686 u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 687 u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 688 u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 689 u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 690 u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 691 u32 metadata_reg_a; /* metadata_reg_a */ 692 u8 reserved_auto2[12]; 693 }; 694 695 struct mlx5dr_match_misc3 { 696 u32 inner_tcp_seq_num; 697 u32 outer_tcp_seq_num; 698 u32 inner_tcp_ack_num; 699 u32 outer_tcp_ack_num; 700 u32 outer_vxlan_gpe_vni:24; 701 u32 reserved_auto1:8; 702 u32 reserved_auto2:16; 703 u32 outer_vxlan_gpe_flags:8; 704 u32 outer_vxlan_gpe_next_protocol:8; 705 u32 icmpv4_header_data; 706 u32 icmpv6_header_data; 707 u8 icmpv6_code; 708 u8 icmpv6_type; 709 u8 icmpv4_code; 710 u8 icmpv4_type; 711 u32 geneve_tlv_option_0_data; 712 u8 gtpu_msg_flags; 713 u8 gtpu_msg_type; 714 u32 gtpu_teid; 715 u32 gtpu_dw_2; 716 u32 gtpu_first_ext_dw_0; 717 u32 gtpu_dw_0; 718 }; 719 720 struct mlx5dr_match_misc4 { 721 u32 prog_sample_field_value_0; 722 u32 prog_sample_field_id_0; 723 u32 prog_sample_field_value_1; 724 u32 prog_sample_field_id_1; 725 u32 prog_sample_field_value_2; 726 u32 prog_sample_field_id_2; 727 u32 prog_sample_field_value_3; 728 u32 prog_sample_field_id_3; 729 }; 730 731 struct mlx5dr_match_param { 732 struct mlx5dr_match_spec outer; 733 struct mlx5dr_match_misc misc; 734 struct mlx5dr_match_spec inner; 735 struct mlx5dr_match_misc2 misc2; 736 struct mlx5dr_match_misc3 misc3; 737 struct mlx5dr_match_misc4 misc4; 738 }; 739 740 #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 741 (_misc3)->icmpv4_code || \ 742 (_misc3)->icmpv4_header_data) 743 744 struct mlx5dr_esw_caps { 745 u64 drop_icm_address_rx; 746 u64 drop_icm_address_tx; 747 u64 uplink_icm_address_rx; 748 u64 uplink_icm_address_tx; 749 u8 sw_owner:1; 750 u8 sw_owner_v2:1; 751 }; 752 753 struct mlx5dr_cmd_vport_cap { 754 u16 vport_gvmi; 755 u16 vhca_gvmi; 756 u64 icm_address_rx; 757 u64 icm_address_tx; 758 u32 num; 759 }; 760 761 struct mlx5dr_roce_cap { 762 u8 roce_en:1; 763 u8 fl_rc_qp_when_roce_disabled:1; 764 u8 fl_rc_qp_when_roce_enabled:1; 765 }; 766 767 struct mlx5dr_cmd_caps { 768 u16 gvmi; 769 u64 nic_rx_drop_address; 770 u64 nic_tx_drop_address; 771 u64 nic_tx_allow_address; 772 u64 esw_rx_drop_address; 773 u64 esw_tx_drop_address; 774 u32 log_icm_size; 775 u64 hdr_modify_icm_addr; 776 u32 flex_protocols; 777 u8 flex_parser_id_icmp_dw0; 778 u8 flex_parser_id_icmp_dw1; 779 u8 flex_parser_id_icmpv6_dw0; 780 u8 flex_parser_id_icmpv6_dw1; 781 u8 flex_parser_id_geneve_tlv_option_0; 782 u8 flex_parser_id_mpls_over_gre; 783 u8 flex_parser_id_mpls_over_udp; 784 u8 flex_parser_id_gtpu_dw_0; 785 u8 flex_parser_id_gtpu_teid; 786 u8 flex_parser_id_gtpu_dw_2; 787 u8 flex_parser_id_gtpu_first_ext_dw_0; 788 u8 max_ft_level; 789 u16 roce_min_src_udp; 790 u8 num_esw_ports; 791 u8 sw_format_ver; 792 bool eswitch_manager; 793 bool rx_sw_owner; 794 bool tx_sw_owner; 795 bool fdb_sw_owner; 796 u8 rx_sw_owner_v2:1; 797 u8 tx_sw_owner_v2:1; 798 u8 fdb_sw_owner_v2:1; 799 u32 num_vports; 800 struct mlx5dr_esw_caps esw_caps; 801 struct mlx5dr_cmd_vport_cap *vports_caps; 802 bool prio_tag_required; 803 struct mlx5dr_roce_cap roce_caps; 804 u8 isolate_vl_tc:1; 805 }; 806 807 struct mlx5dr_domain_rx_tx { 808 u64 drop_icm_addr; 809 u64 default_icm_addr; 810 enum mlx5dr_ste_entry_type ste_type; 811 struct mutex mutex; /* protect rx/tx domain */ 812 }; 813 814 struct mlx5dr_domain_info { 815 bool supp_sw_steering; 816 u32 max_inline_size; 817 u32 max_send_wr; 818 u32 max_log_sw_icm_sz; 819 u32 max_log_action_icm_sz; 820 struct mlx5dr_domain_rx_tx rx; 821 struct mlx5dr_domain_rx_tx tx; 822 struct mlx5dr_cmd_caps caps; 823 }; 824 825 struct mlx5dr_domain_cache { 826 struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft; 827 }; 828 829 struct mlx5dr_domain { 830 struct mlx5dr_domain *peer_dmn; 831 struct mlx5_core_dev *mdev; 832 u32 pdn; 833 struct mlx5_uars_page *uar; 834 enum mlx5dr_domain_type type; 835 refcount_t refcount; 836 struct mlx5dr_icm_pool *ste_icm_pool; 837 struct mlx5dr_icm_pool *action_icm_pool; 838 struct mlx5dr_send_ring *send_ring; 839 struct mlx5dr_domain_info info; 840 struct mlx5dr_domain_cache cache; 841 struct mlx5dr_ste_ctx *ste_ctx; 842 }; 843 844 struct mlx5dr_table_rx_tx { 845 struct mlx5dr_ste_htbl *s_anchor; 846 struct mlx5dr_domain_rx_tx *nic_dmn; 847 u64 default_icm_addr; 848 }; 849 850 struct mlx5dr_table { 851 struct mlx5dr_domain *dmn; 852 struct mlx5dr_table_rx_tx rx; 853 struct mlx5dr_table_rx_tx tx; 854 u32 level; 855 u32 table_type; 856 u32 table_id; 857 u32 flags; 858 struct list_head matcher_list; 859 struct mlx5dr_action *miss_action; 860 refcount_t refcount; 861 }; 862 863 struct mlx5dr_matcher_rx_tx { 864 struct mlx5dr_ste_htbl *s_htbl; 865 struct mlx5dr_ste_htbl *e_anchor; 866 struct mlx5dr_ste_build *ste_builder; 867 struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 868 [DR_RULE_IPV_MAX] 869 [DR_RULE_MAX_STES]; 870 u8 num_of_builders; 871 u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 872 u64 default_icm_addr; 873 struct mlx5dr_table_rx_tx *nic_tbl; 874 }; 875 876 struct mlx5dr_matcher { 877 struct mlx5dr_table *tbl; 878 struct mlx5dr_matcher_rx_tx rx; 879 struct mlx5dr_matcher_rx_tx tx; 880 struct list_head matcher_list; 881 u32 prio; 882 struct mlx5dr_match_param mask; 883 u8 match_criteria; 884 refcount_t refcount; 885 struct mlx5dv_flow_matcher *dv_matcher; 886 }; 887 888 struct mlx5dr_rule_member { 889 struct mlx5dr_ste *ste; 890 /* attached to mlx5dr_rule via this */ 891 struct list_head list; 892 /* attached to mlx5dr_ste via this */ 893 struct list_head use_ste_list; 894 }; 895 896 struct mlx5dr_ste_action_modify_field { 897 u16 hw_field; 898 u8 start; 899 u8 end; 900 u8 l3_type; 901 u8 l4_type; 902 }; 903 904 struct mlx5dr_action_rewrite { 905 struct mlx5dr_domain *dmn; 906 struct mlx5dr_icm_chunk *chunk; 907 u8 *data; 908 u16 num_of_actions; 909 u32 index; 910 u8 allow_rx:1; 911 u8 allow_tx:1; 912 u8 modify_ttl:1; 913 }; 914 915 struct mlx5dr_action_reformat { 916 struct mlx5dr_domain *dmn; 917 u32 id; 918 u32 size; 919 u8 param_0; 920 u8 param_1; 921 }; 922 923 struct mlx5dr_action_sampler { 924 struct mlx5dr_domain *dmn; 925 u64 rx_icm_addr; 926 u64 tx_icm_addr; 927 u32 sampler_id; 928 }; 929 930 struct mlx5dr_action_dest_tbl { 931 u8 is_fw_tbl:1; 932 union { 933 struct mlx5dr_table *tbl; 934 struct { 935 struct mlx5dr_domain *dmn; 936 u32 id; 937 u32 group_id; 938 enum fs_flow_table_type type; 939 u64 rx_icm_addr; 940 u64 tx_icm_addr; 941 struct mlx5dr_action **ref_actions; 942 u32 num_of_ref_actions; 943 } fw_tbl; 944 }; 945 }; 946 947 struct mlx5dr_action_ctr { 948 u32 ctr_id; 949 u32 offeset; 950 }; 951 952 struct mlx5dr_action_vport { 953 struct mlx5dr_domain *dmn; 954 struct mlx5dr_cmd_vport_cap *caps; 955 }; 956 957 struct mlx5dr_action_push_vlan { 958 u32 vlan_hdr; /* tpid_pcp_dei_vid */ 959 }; 960 961 struct mlx5dr_action_flow_tag { 962 u32 flow_tag; 963 }; 964 965 struct mlx5dr_action { 966 enum mlx5dr_action_type action_type; 967 refcount_t refcount; 968 969 union { 970 void *data; 971 struct mlx5dr_action_rewrite *rewrite; 972 struct mlx5dr_action_reformat *reformat; 973 struct mlx5dr_action_sampler *sampler; 974 struct mlx5dr_action_dest_tbl *dest_tbl; 975 struct mlx5dr_action_ctr *ctr; 976 struct mlx5dr_action_vport *vport; 977 struct mlx5dr_action_push_vlan *push_vlan; 978 struct mlx5dr_action_flow_tag *flow_tag; 979 }; 980 }; 981 982 enum mlx5dr_connect_type { 983 CONNECT_HIT = 1, 984 CONNECT_MISS = 2, 985 }; 986 987 struct mlx5dr_htbl_connect_info { 988 enum mlx5dr_connect_type type; 989 union { 990 struct mlx5dr_ste_htbl *hit_next_htbl; 991 u64 miss_icm_addr; 992 }; 993 }; 994 995 struct mlx5dr_rule_rx_tx { 996 struct list_head rule_members_list; 997 struct mlx5dr_matcher_rx_tx *nic_matcher; 998 }; 999 1000 struct mlx5dr_rule { 1001 struct mlx5dr_matcher *matcher; 1002 struct mlx5dr_rule_rx_tx rx; 1003 struct mlx5dr_rule_rx_tx tx; 1004 struct list_head rule_actions_list; 1005 u32 flow_source; 1006 }; 1007 1008 void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste, 1009 struct mlx5dr_ste *ste); 1010 1011 struct mlx5dr_icm_chunk { 1012 struct mlx5dr_icm_buddy_mem *buddy_mem; 1013 struct list_head chunk_list; 1014 u32 rkey; 1015 u32 num_of_entries; 1016 u32 byte_size; 1017 u64 icm_addr; 1018 u64 mr_addr; 1019 1020 /* indicates the index of this chunk in the whole memory, 1021 * used for deleting the chunk from the buddy 1022 */ 1023 unsigned int seg; 1024 1025 /* Memory optimisation */ 1026 struct mlx5dr_ste *ste_arr; 1027 u8 *hw_ste_arr; 1028 struct list_head *miss_list; 1029 }; 1030 1031 static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn) 1032 { 1033 mutex_lock(&nic_dmn->mutex); 1034 } 1035 1036 static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn) 1037 { 1038 mutex_unlock(&nic_dmn->mutex); 1039 } 1040 1041 static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn) 1042 { 1043 mlx5dr_domain_nic_lock(&dmn->info.rx); 1044 mlx5dr_domain_nic_lock(&dmn->info.tx); 1045 } 1046 1047 static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn) 1048 { 1049 mlx5dr_domain_nic_unlock(&dmn->info.tx); 1050 mlx5dr_domain_nic_unlock(&dmn->info.rx); 1051 } 1052 1053 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 1054 struct mlx5dr_matcher_rx_tx *nic_matcher, 1055 enum mlx5dr_ipv outer_ipv, 1056 enum mlx5dr_ipv inner_ipv); 1057 1058 static inline int 1059 mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type) 1060 { 1061 if (icm_type == DR_ICM_TYPE_STE) 1062 return DR_STE_SIZE; 1063 1064 return DR_MODIFY_ACTION_SIZE; 1065 } 1066 1067 static inline u32 1068 mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 1069 { 1070 return 1 << chunk_size; 1071 } 1072 1073 static inline int 1074 mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 1075 enum mlx5dr_icm_type icm_type) 1076 { 1077 int num_of_entries; 1078 int entry_size; 1079 1080 entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type); 1081 num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 1082 1083 return entry_size * num_of_entries; 1084 } 1085 1086 static inline struct mlx5dr_cmd_vport_cap * 1087 mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport) 1088 { 1089 if (!caps->vports_caps || 1090 (vport >= caps->num_vports && vport != WIRE_PORT)) 1091 return NULL; 1092 1093 if (vport == WIRE_PORT) 1094 vport = caps->num_vports; 1095 1096 return &caps->vports_caps[vport]; 1097 } 1098 1099 struct mlx5dr_cmd_query_flow_table_details { 1100 u8 status; 1101 u8 level; 1102 u64 sw_owner_icm_root_1; 1103 u64 sw_owner_icm_root_0; 1104 }; 1105 1106 struct mlx5dr_cmd_create_flow_table_attr { 1107 u32 table_type; 1108 u64 icm_addr_rx; 1109 u64 icm_addr_tx; 1110 u8 level; 1111 bool sw_owner; 1112 bool term_tbl; 1113 bool decap_en; 1114 bool reformat_en; 1115 }; 1116 1117 /* internal API functions */ 1118 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 1119 struct mlx5dr_cmd_caps *caps); 1120 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 1121 bool other_vport, u16 vport_number, 1122 u64 *icm_address_rx, 1123 u64 *icm_address_tx); 1124 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 1125 bool other_vport, u16 vport_number, u16 *gvmi); 1126 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 1127 struct mlx5dr_esw_caps *caps); 1128 int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev, 1129 u32 sampler_id, 1130 u64 *rx_icm_addr, 1131 u64 *tx_icm_addr); 1132 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 1133 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 1134 u32 table_type, 1135 u32 table_id, 1136 u32 group_id, 1137 u32 modify_header_id, 1138 u32 vport_id); 1139 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 1140 u32 table_type, 1141 u32 table_id); 1142 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 1143 u32 table_type, 1144 u8 num_of_actions, 1145 u64 *actions, 1146 u32 *modify_header_id); 1147 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 1148 u32 modify_header_id); 1149 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 1150 u32 table_type, 1151 u32 table_id, 1152 u32 *group_id); 1153 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 1154 u32 table_type, 1155 u32 table_id, 1156 u32 group_id); 1157 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 1158 struct mlx5dr_cmd_create_flow_table_attr *attr, 1159 u64 *fdb_rx_icm_addr, 1160 u32 *table_id); 1161 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 1162 u32 table_id, 1163 u32 table_type); 1164 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 1165 enum fs_flow_table_type type, 1166 u32 table_id, 1167 struct mlx5dr_cmd_query_flow_table_details *output); 1168 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 1169 enum mlx5_reformat_ctx_type rt, 1170 u8 reformat_param_0, 1171 u8 reformat_param_1, 1172 size_t reformat_size, 1173 void *reformat_data, 1174 u32 *reformat_id); 1175 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 1176 u32 reformat_id); 1177 1178 struct mlx5dr_cmd_gid_attr { 1179 u8 gid[16]; 1180 u8 mac[6]; 1181 u32 roce_ver; 1182 }; 1183 1184 struct mlx5dr_cmd_qp_create_attr { 1185 u32 page_id; 1186 u32 pdn; 1187 u32 cqn; 1188 u32 pm_state; 1189 u32 service_type; 1190 u32 buff_umem_id; 1191 u32 db_umem_id; 1192 u32 sq_wqe_cnt; 1193 u32 rq_wqe_cnt; 1194 u32 rq_wqe_shift; 1195 u8 isolate_vl_tc:1; 1196 }; 1197 1198 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 1199 u16 index, struct mlx5dr_cmd_gid_attr *attr); 1200 1201 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 1202 enum mlx5dr_icm_type icm_type); 1203 void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 1204 1205 struct mlx5dr_icm_chunk * 1206 mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 1207 enum mlx5dr_icm_chunk_size chunk_size); 1208 void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 1209 1210 void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, 1211 u8 *hw_ste_p, u32 ste_size); 1212 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 1213 struct mlx5dr_domain_rx_tx *nic_dmn, 1214 struct mlx5dr_ste_htbl *htbl, 1215 struct mlx5dr_htbl_connect_info *connect_info, 1216 bool update_hw_ste); 1217 void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, 1218 u16 gvmi, 1219 struct mlx5dr_domain_rx_tx *nic_dmn, 1220 struct mlx5dr_ste_htbl *htbl, 1221 u8 *formatted_ste, 1222 struct mlx5dr_htbl_connect_info *connect_info); 1223 void mlx5dr_ste_copy_param(u8 match_criteria, 1224 struct mlx5dr_match_param *set_param, 1225 struct mlx5dr_match_parameters *mask); 1226 1227 struct mlx5dr_qp { 1228 struct mlx5_core_dev *mdev; 1229 struct mlx5_wq_qp wq; 1230 struct mlx5_uars_page *uar; 1231 struct mlx5_wq_ctrl wq_ctrl; 1232 u32 qpn; 1233 struct { 1234 unsigned int pc; 1235 unsigned int cc; 1236 unsigned int size; 1237 unsigned int *wqe_head; 1238 unsigned int wqe_cnt; 1239 } sq; 1240 struct { 1241 unsigned int pc; 1242 unsigned int cc; 1243 unsigned int size; 1244 unsigned int wqe_cnt; 1245 } rq; 1246 int max_inline_data; 1247 }; 1248 1249 struct mlx5dr_cq { 1250 struct mlx5_core_dev *mdev; 1251 struct mlx5_cqwq wq; 1252 struct mlx5_wq_ctrl wq_ctrl; 1253 struct mlx5_core_cq mcq; 1254 struct mlx5dr_qp *qp; 1255 }; 1256 1257 struct mlx5dr_mr { 1258 struct mlx5_core_dev *mdev; 1259 struct mlx5_core_mkey mkey; 1260 dma_addr_t dma_addr; 1261 void *addr; 1262 size_t size; 1263 }; 1264 1265 #define MAX_SEND_CQE 64 1266 #define MIN_READ_SYNC 64 1267 1268 struct mlx5dr_send_ring { 1269 struct mlx5dr_cq *cq; 1270 struct mlx5dr_qp *qp; 1271 struct mlx5dr_mr *mr; 1272 /* How much wqes are waiting for completion */ 1273 u32 pending_wqe; 1274 /* Signal request per this trash hold value */ 1275 u16 signal_th; 1276 /* Each post_send_size less than max_post_send_size */ 1277 u32 max_post_send_size; 1278 /* manage the send queue */ 1279 u32 tx_head; 1280 void *buf; 1281 u32 buf_size; 1282 u8 sync_buff[MIN_READ_SYNC]; 1283 struct mlx5dr_mr *sync_mr; 1284 spinlock_t lock; /* Protect the data path of the send ring */ 1285 }; 1286 1287 int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 1288 void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 1289 struct mlx5dr_send_ring *send_ring); 1290 int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 1291 int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 1292 struct mlx5dr_ste *ste, 1293 u8 *data, 1294 u16 size, 1295 u16 offset); 1296 int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 1297 struct mlx5dr_ste_htbl *htbl, 1298 u8 *formatted_ste, u8 *mask); 1299 int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 1300 struct mlx5dr_ste_htbl *htbl, 1301 u8 *ste_init_data, 1302 bool update_hw_ste); 1303 int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 1304 struct mlx5dr_action *action); 1305 1306 struct mlx5dr_cmd_ft_info { 1307 u32 id; 1308 u16 vport; 1309 enum fs_flow_table_type type; 1310 }; 1311 1312 struct mlx5dr_cmd_flow_destination_hw_info { 1313 enum mlx5_flow_destination_type type; 1314 union { 1315 u32 tir_num; 1316 u32 ft_num; 1317 u32 ft_id; 1318 u32 counter_id; 1319 u32 sampler_id; 1320 struct { 1321 u16 num; 1322 u16 vhca_id; 1323 u32 reformat_id; 1324 u8 flags; 1325 } vport; 1326 }; 1327 }; 1328 1329 struct mlx5dr_cmd_fte_info { 1330 u32 dests_size; 1331 u32 index; 1332 struct mlx5_flow_context flow_context; 1333 u32 *val; 1334 struct mlx5_flow_act action; 1335 struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 1336 }; 1337 1338 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 1339 int opmod, int modify_mask, 1340 struct mlx5dr_cmd_ft_info *ft, 1341 u32 group_id, 1342 struct mlx5dr_cmd_fte_info *fte); 1343 1344 bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps); 1345 1346 struct mlx5dr_fw_recalc_cs_ft { 1347 u64 rx_icm_addr; 1348 u32 table_id; 1349 u32 group_id; 1350 u32 modify_hdr_id; 1351 }; 1352 1353 struct mlx5dr_fw_recalc_cs_ft * 1354 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num); 1355 void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 1356 struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 1357 int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 1358 u32 vport_num, 1359 u64 *rx_icm_addr); 1360 int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 1361 struct mlx5dr_cmd_flow_destination_hw_info *dest, 1362 int num_dest, 1363 bool reformat_req, 1364 u32 *tbl_id, 1365 u32 *group_id); 1366 void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 1367 u32 group_id); 1368 #endif /* _DR_TYPES_H_ */ 1369