114c32fd1SAlex Vesker /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 214c32fd1SAlex Vesker /* Copyright (c) 2019, Mellanox Technologies */ 314c32fd1SAlex Vesker 414c32fd1SAlex Vesker #ifndef _DR_TYPES_ 514c32fd1SAlex Vesker #define _DR_TYPES_ 614c32fd1SAlex Vesker 714c32fd1SAlex Vesker #include <linux/mlx5/driver.h> 814c32fd1SAlex Vesker #include <linux/refcount.h> 914c32fd1SAlex Vesker #include "fs_core.h" 1014c32fd1SAlex Vesker #include "wq.h" 1114c32fd1SAlex Vesker #include "lib/mlx5.h" 1214c32fd1SAlex Vesker #include "mlx5_ifc_dr.h" 1314c32fd1SAlex Vesker #include "mlx5dr.h" 1414c32fd1SAlex Vesker 153442e033SYevgeny Kliteynik #define DR_RULE_MAX_STES 18 1614c32fd1SAlex Vesker #define DR_ACTION_MAX_STES 5 1714c32fd1SAlex Vesker #define WIRE_PORT 0xFFFF 1814c32fd1SAlex Vesker #define DR_STE_SVLAN 0x1 1914c32fd1SAlex Vesker #define DR_STE_CVLAN 0x2 20699d531fSMuhammad Sammar #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) 21160e9cb3SYevgeny Kliteynik #define DR_NUM_OF_FLEX_PARSERS 8 22160e9cb3SYevgeny Kliteynik #define DR_STE_MAX_FLEX_0_ID 3 23160e9cb3SYevgeny Kliteynik #define DR_STE_MAX_FLEX_1_ID 7 2414c32fd1SAlex Vesker 2514c32fd1SAlex Vesker #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 2614c32fd1SAlex Vesker #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 2714c32fd1SAlex Vesker #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 2814c32fd1SAlex Vesker 29df9dd15aSYevgeny Kliteynik static inline bool dr_is_flex_parser_0_id(u8 parser_id) 30df9dd15aSYevgeny Kliteynik { 31df9dd15aSYevgeny Kliteynik return parser_id <= DR_STE_MAX_FLEX_0_ID; 32df9dd15aSYevgeny Kliteynik } 33df9dd15aSYevgeny Kliteynik 34df9dd15aSYevgeny Kliteynik static inline bool dr_is_flex_parser_1_id(u8 parser_id) 35df9dd15aSYevgeny Kliteynik { 36df9dd15aSYevgeny Kliteynik return parser_id > DR_STE_MAX_FLEX_0_ID; 37df9dd15aSYevgeny Kliteynik } 38df9dd15aSYevgeny Kliteynik 3914c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size { 4014c32fd1SAlex Vesker DR_CHUNK_SIZE_1, 4114c32fd1SAlex Vesker DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 4214c32fd1SAlex Vesker DR_CHUNK_SIZE_2, 4314c32fd1SAlex Vesker DR_CHUNK_SIZE_4, 4414c32fd1SAlex Vesker DR_CHUNK_SIZE_8, 4514c32fd1SAlex Vesker DR_CHUNK_SIZE_16, 4614c32fd1SAlex Vesker DR_CHUNK_SIZE_32, 4714c32fd1SAlex Vesker DR_CHUNK_SIZE_64, 4814c32fd1SAlex Vesker DR_CHUNK_SIZE_128, 4914c32fd1SAlex Vesker DR_CHUNK_SIZE_256, 5014c32fd1SAlex Vesker DR_CHUNK_SIZE_512, 5114c32fd1SAlex Vesker DR_CHUNK_SIZE_1K, 5214c32fd1SAlex Vesker DR_CHUNK_SIZE_2K, 5314c32fd1SAlex Vesker DR_CHUNK_SIZE_4K, 5414c32fd1SAlex Vesker DR_CHUNK_SIZE_8K, 5514c32fd1SAlex Vesker DR_CHUNK_SIZE_16K, 5614c32fd1SAlex Vesker DR_CHUNK_SIZE_32K, 5714c32fd1SAlex Vesker DR_CHUNK_SIZE_64K, 5814c32fd1SAlex Vesker DR_CHUNK_SIZE_128K, 5914c32fd1SAlex Vesker DR_CHUNK_SIZE_256K, 6014c32fd1SAlex Vesker DR_CHUNK_SIZE_512K, 6114c32fd1SAlex Vesker DR_CHUNK_SIZE_1024K, 6214c32fd1SAlex Vesker DR_CHUNK_SIZE_2048K, 6314c32fd1SAlex Vesker DR_CHUNK_SIZE_MAX, 6414c32fd1SAlex Vesker }; 6514c32fd1SAlex Vesker 6614c32fd1SAlex Vesker enum mlx5dr_icm_type { 6714c32fd1SAlex Vesker DR_ICM_TYPE_STE, 6814c32fd1SAlex Vesker DR_ICM_TYPE_MODIFY_ACTION, 6914c32fd1SAlex Vesker }; 7014c32fd1SAlex Vesker 7114c32fd1SAlex Vesker static inline enum mlx5dr_icm_chunk_size 7214c32fd1SAlex Vesker mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 7314c32fd1SAlex Vesker { 7414c32fd1SAlex Vesker chunk += 2; 7514c32fd1SAlex Vesker if (chunk < DR_CHUNK_SIZE_MAX) 7614c32fd1SAlex Vesker return chunk; 7714c32fd1SAlex Vesker 7814c32fd1SAlex Vesker return DR_CHUNK_SIZE_MAX; 7914c32fd1SAlex Vesker } 8014c32fd1SAlex Vesker 8114c32fd1SAlex Vesker enum { 8214c32fd1SAlex Vesker DR_STE_SIZE = 64, 8314c32fd1SAlex Vesker DR_STE_SIZE_CTRL = 32, 8414c32fd1SAlex Vesker DR_STE_SIZE_TAG = 16, 8514c32fd1SAlex Vesker DR_STE_SIZE_MASK = 16, 8614c32fd1SAlex Vesker DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 8714c32fd1SAlex Vesker }; 8814c32fd1SAlex Vesker 89d7418b4eSYevgeny Kliteynik enum mlx5dr_ste_ctx_action_cap { 90d7418b4eSYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_NONE = 0, 912de40f68SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_TX_POP = 1 << 0, 922de40f68SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_RX_PUSH = 1 << 1, 932de40f68SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_RX_ENCAP = 1 << 2, 94d7418b4eSYevgeny Kliteynik }; 95d7418b4eSYevgeny Kliteynik 9614c32fd1SAlex Vesker enum { 9714c32fd1SAlex Vesker DR_MODIFY_ACTION_SIZE = 8, 9814c32fd1SAlex Vesker }; 9914c32fd1SAlex Vesker 10014c32fd1SAlex Vesker enum mlx5dr_matcher_criteria { 10114c32fd1SAlex Vesker DR_MATCHER_CRITERIA_EMPTY = 0, 10214c32fd1SAlex Vesker DR_MATCHER_CRITERIA_OUTER = 1 << 0, 10314c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC = 1 << 1, 10414c32fd1SAlex Vesker DR_MATCHER_CRITERIA_INNER = 1 << 2, 10514c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 10614c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 107160e9cb3SYevgeny Kliteynik DR_MATCHER_CRITERIA_MISC4 = 1 << 5, 108160e9cb3SYevgeny Kliteynik DR_MATCHER_CRITERIA_MAX = 1 << 6, 10914c32fd1SAlex Vesker }; 11014c32fd1SAlex Vesker 11114c32fd1SAlex Vesker enum mlx5dr_action_type { 11214c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L2_TO_L2, 11314c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L2, 11414c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L3_TO_L2, 11514c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L3, 11614c32fd1SAlex Vesker DR_ACTION_TYP_DROP, 11714c32fd1SAlex Vesker DR_ACTION_TYP_QP, 11814c32fd1SAlex Vesker DR_ACTION_TYP_FT, 11914c32fd1SAlex Vesker DR_ACTION_TYP_CTR, 12014c32fd1SAlex Vesker DR_ACTION_TYP_TAG, 12114c32fd1SAlex Vesker DR_ACTION_TYP_MODIFY_HDR, 12214c32fd1SAlex Vesker DR_ACTION_TYP_VPORT, 12314c32fd1SAlex Vesker DR_ACTION_TYP_POP_VLAN, 12414c32fd1SAlex Vesker DR_ACTION_TYP_PUSH_VLAN, 1257ea9b398SYevgeny Kliteynik DR_ACTION_TYP_INSERT_HDR, 1260139145fSYevgeny Kliteynik DR_ACTION_TYP_REMOVE_HDR, 1271ab6dc35SYevgeny Kliteynik DR_ACTION_TYP_SAMPLER, 12814c32fd1SAlex Vesker DR_ACTION_TYP_MAX, 12914c32fd1SAlex Vesker }; 13014c32fd1SAlex Vesker 131667f2646SAlex Vesker enum mlx5dr_ipv { 132667f2646SAlex Vesker DR_RULE_IPV4, 133667f2646SAlex Vesker DR_RULE_IPV6, 134667f2646SAlex Vesker DR_RULE_IPV_MAX, 135667f2646SAlex Vesker }; 136667f2646SAlex Vesker 13714c32fd1SAlex Vesker struct mlx5dr_icm_pool; 13814c32fd1SAlex Vesker struct mlx5dr_icm_chunk; 139a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem; 14014c32fd1SAlex Vesker struct mlx5dr_ste_htbl; 14114c32fd1SAlex Vesker struct mlx5dr_match_param; 14214c32fd1SAlex Vesker struct mlx5dr_cmd_caps; 1438a015baeSYevgeny Kliteynik struct mlx5dr_rule_rx_tx; 14414c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx; 1455212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx; 14614c32fd1SAlex Vesker 14714c32fd1SAlex Vesker struct mlx5dr_ste { 14814c32fd1SAlex Vesker u8 *hw_ste; 14914c32fd1SAlex Vesker /* refcount: indicates the num of rules that using this ste */ 1504ce380caSYevgeny Kliteynik u32 refcount; 15114c32fd1SAlex Vesker 15214c32fd1SAlex Vesker /* attached to the miss_list head at each htbl entry */ 15314c32fd1SAlex Vesker struct list_head miss_list_node; 15414c32fd1SAlex Vesker 15514c32fd1SAlex Vesker /* this ste is member of htbl */ 15614c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl; 15714c32fd1SAlex Vesker 15814c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl; 15914c32fd1SAlex Vesker 1608a015baeSYevgeny Kliteynik /* The rule this STE belongs to */ 1618a015baeSYevgeny Kliteynik struct mlx5dr_rule_rx_tx *rule_rx_tx; 1628a015baeSYevgeny Kliteynik 16314c32fd1SAlex Vesker /* this ste is part of a rule, located in ste's chain */ 16414c32fd1SAlex Vesker u8 ste_chain_location; 16514c32fd1SAlex Vesker }; 16614c32fd1SAlex Vesker 16714c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl { 16814c32fd1SAlex Vesker /* total number of valid entries belonging to this hash table. This 16914c32fd1SAlex Vesker * includes the non collision and collision entries 17014c32fd1SAlex Vesker */ 17114c32fd1SAlex Vesker unsigned int num_of_valid_entries; 17214c32fd1SAlex Vesker 17314c32fd1SAlex Vesker /* total number of collisions entries attached to this table */ 17414c32fd1SAlex Vesker unsigned int num_of_collisions; 17514c32fd1SAlex Vesker }; 17614c32fd1SAlex Vesker 17714c32fd1SAlex Vesker struct mlx5dr_ste_htbl { 178dd2d3c8dSYevgeny Kliteynik u16 lu_type; 17914c32fd1SAlex Vesker u16 byte_mask; 1804ce380caSYevgeny Kliteynik u32 refcount; 18114c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 18214c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 18314c32fd1SAlex Vesker u8 *hw_ste_arr; 18414c32fd1SAlex Vesker 18514c32fd1SAlex Vesker struct list_head *miss_list; 18614c32fd1SAlex Vesker 18714c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size; 18814c32fd1SAlex Vesker struct mlx5dr_ste *pointing_ste; 18914c32fd1SAlex Vesker 19014c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl ctrl; 19114c32fd1SAlex Vesker }; 19214c32fd1SAlex Vesker 19314c32fd1SAlex Vesker struct mlx5dr_ste_send_info { 19414c32fd1SAlex Vesker struct mlx5dr_ste *ste; 19514c32fd1SAlex Vesker struct list_head send_list; 19614c32fd1SAlex Vesker u16 size; 19714c32fd1SAlex Vesker u16 offset; 19814c32fd1SAlex Vesker u8 data_cont[DR_STE_SIZE]; 19914c32fd1SAlex Vesker u8 *data; 20014c32fd1SAlex Vesker }; 20114c32fd1SAlex Vesker 20214c32fd1SAlex Vesker void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 20314c32fd1SAlex Vesker u16 offset, u8 *data, 20414c32fd1SAlex Vesker struct mlx5dr_ste_send_info *ste_info, 20514c32fd1SAlex Vesker struct list_head *send_list, 20614c32fd1SAlex Vesker bool copy_data); 20714c32fd1SAlex Vesker 20814c32fd1SAlex Vesker struct mlx5dr_ste_build { 20914c32fd1SAlex Vesker u8 inner:1; 21014c32fd1SAlex Vesker u8 rx:1; 211640bdb1fSAlaa Hleihel u8 vhca_id_valid:1; 212640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn; 21314c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps; 214dd2d3c8dSYevgeny Kliteynik u16 lu_type; 21514c32fd1SAlex Vesker u16 byte_mask; 21614c32fd1SAlex Vesker u8 bit_mask[DR_STE_SIZE_MASK]; 21714c32fd1SAlex Vesker int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 21814c32fd1SAlex Vesker struct mlx5dr_ste_build *sb, 219e6b69bf3SYevgeny Kliteynik u8 *tag); 22014c32fd1SAlex Vesker }; 22114c32fd1SAlex Vesker 22214c32fd1SAlex Vesker struct mlx5dr_ste_htbl * 22314c32fd1SAlex Vesker mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 22414c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size, 225dd2d3c8dSYevgeny Kliteynik u16 lu_type, u16 byte_mask); 22614c32fd1SAlex Vesker 22714c32fd1SAlex Vesker int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 22814c32fd1SAlex Vesker 22914c32fd1SAlex Vesker static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 23014c32fd1SAlex Vesker { 2314ce380caSYevgeny Kliteynik htbl->refcount--; 2324ce380caSYevgeny Kliteynik if (!htbl->refcount) 23314c32fd1SAlex Vesker mlx5dr_ste_htbl_free(htbl); 23414c32fd1SAlex Vesker } 23514c32fd1SAlex Vesker 23614c32fd1SAlex Vesker static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 23714c32fd1SAlex Vesker { 2384ce380caSYevgeny Kliteynik htbl->refcount++; 23914c32fd1SAlex Vesker } 24014c32fd1SAlex Vesker 24114c32fd1SAlex Vesker /* STE utils */ 24214c32fd1SAlex Vesker u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 2436b93b400SYevgeny Kliteynik void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, 2446b93b400SYevgeny Kliteynik u8 *hw_ste, u64 miss_addr); 2456b93b400SYevgeny Kliteynik void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, 2466b93b400SYevgeny Kliteynik u8 *hw_ste, u64 icm_addr, u32 ht_size); 2476b93b400SYevgeny Kliteynik void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, 2486b93b400SYevgeny Kliteynik u8 *hw_ste, 2496b93b400SYevgeny Kliteynik struct mlx5dr_ste_htbl *next_htbl); 25014c32fd1SAlex Vesker void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 25114c32fd1SAlex Vesker bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 25214c32fd1SAlex Vesker u8 ste_location); 25314c32fd1SAlex Vesker u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 25414c32fd1SAlex Vesker u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 25514c32fd1SAlex Vesker struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 25614c32fd1SAlex Vesker 25764c78942SYevgeny Kliteynik #define MLX5DR_MAX_VLANS 2 25864c78942SYevgeny Kliteynik 25964c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr { 26064c78942SYevgeny Kliteynik u32 modify_index; 26164c78942SYevgeny Kliteynik u16 modify_actions; 26264c78942SYevgeny Kliteynik u32 decap_index; 26364c78942SYevgeny Kliteynik u16 decap_actions; 26464c78942SYevgeny Kliteynik u8 decap_with_vlan:1; 26564c78942SYevgeny Kliteynik u64 final_icm_addr; 26664c78942SYevgeny Kliteynik u32 flow_tag; 26764c78942SYevgeny Kliteynik u32 ctr_id; 26864c78942SYevgeny Kliteynik u16 gvmi; 26964c78942SYevgeny Kliteynik u16 hit_gvmi; 2707ea9b398SYevgeny Kliteynik struct { 2717ea9b398SYevgeny Kliteynik u32 id; 2727ea9b398SYevgeny Kliteynik u32 size; 2737ea9b398SYevgeny Kliteynik u8 param_0; 2747ea9b398SYevgeny Kliteynik u8 param_1; 2757ea9b398SYevgeny Kliteynik } reformat; 27664c78942SYevgeny Kliteynik struct { 27764c78942SYevgeny Kliteynik int count; 27864c78942SYevgeny Kliteynik u32 headers[MLX5DR_MAX_VLANS]; 27964c78942SYevgeny Kliteynik } vlans; 28064c78942SYevgeny Kliteynik }; 28164c78942SYevgeny Kliteynik 2826b93b400SYevgeny Kliteynik void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, 2836b93b400SYevgeny Kliteynik struct mlx5dr_domain *dmn, 28464c78942SYevgeny Kliteynik u8 *action_type_set, 28564c78942SYevgeny Kliteynik u8 *last_ste, 28664c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 28764c78942SYevgeny Kliteynik u32 *added_stes); 2886b93b400SYevgeny Kliteynik void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, 2896b93b400SYevgeny Kliteynik struct mlx5dr_domain *dmn, 29064c78942SYevgeny Kliteynik u8 *action_type_set, 29164c78942SYevgeny Kliteynik u8 *last_ste, 29264c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 29364c78942SYevgeny Kliteynik u32 *added_stes); 29464c78942SYevgeny Kliteynik 2954781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, 2964781df92SYevgeny Kliteynik __be64 *hw_action, 2974781df92SYevgeny Kliteynik u8 hw_field, 2984781df92SYevgeny Kliteynik u8 shifter, 2994781df92SYevgeny Kliteynik u8 length, 3004781df92SYevgeny Kliteynik u32 data); 3014781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, 3024781df92SYevgeny Kliteynik __be64 *hw_action, 3034781df92SYevgeny Kliteynik u8 hw_field, 3044781df92SYevgeny Kliteynik u8 shifter, 3054781df92SYevgeny Kliteynik u8 length, 3064781df92SYevgeny Kliteynik u32 data); 3074781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, 3084781df92SYevgeny Kliteynik __be64 *hw_action, 3094781df92SYevgeny Kliteynik u8 dst_hw_field, 3104781df92SYevgeny Kliteynik u8 dst_shifter, 3114781df92SYevgeny Kliteynik u8 dst_len, 3124781df92SYevgeny Kliteynik u8 src_hw_field, 3134781df92SYevgeny Kliteynik u8 src_shifter); 3144781df92SYevgeny Kliteynik int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, 3154781df92SYevgeny Kliteynik void *data, 3164781df92SYevgeny Kliteynik u32 data_sz, 3174781df92SYevgeny Kliteynik u8 *hw_action, 3184781df92SYevgeny Kliteynik u32 hw_action_sz, 3194781df92SYevgeny Kliteynik u16 *used_hw_action_num); 3204781df92SYevgeny Kliteynik 3214781df92SYevgeny Kliteynik const struct mlx5dr_ste_action_modify_field * 3224781df92SYevgeny Kliteynik mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field); 3234781df92SYevgeny Kliteynik 3245212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); 32514c32fd1SAlex Vesker void mlx5dr_ste_free(struct mlx5dr_ste *ste, 32614c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 32714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher); 32814c32fd1SAlex Vesker static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 32914c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 33014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher) 33114c32fd1SAlex Vesker { 3324ce380caSYevgeny Kliteynik ste->refcount--; 3334ce380caSYevgeny Kliteynik if (!ste->refcount) 33414c32fd1SAlex Vesker mlx5dr_ste_free(ste, matcher, nic_matcher); 33514c32fd1SAlex Vesker } 33614c32fd1SAlex Vesker 33714c32fd1SAlex Vesker /* initial as 0, increased only when ste appears in a new rule */ 33814c32fd1SAlex Vesker static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 33914c32fd1SAlex Vesker { 3404ce380caSYevgeny Kliteynik ste->refcount++; 34114c32fd1SAlex Vesker } 34214c32fd1SAlex Vesker 34397ffd895SYevgeny Kliteynik static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste) 34497ffd895SYevgeny Kliteynik { 34597ffd895SYevgeny Kliteynik return !ste->refcount; 34697ffd895SYevgeny Kliteynik } 34797ffd895SYevgeny Kliteynik 34814c32fd1SAlex Vesker bool mlx5dr_ste_equal_tag(void *src, void *dst); 34914c32fd1SAlex Vesker int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 35014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 35114c32fd1SAlex Vesker struct mlx5dr_ste *ste, 35214c32fd1SAlex Vesker u8 *cur_hw_ste, 35314c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size log_table_size); 35414c32fd1SAlex Vesker 35514c32fd1SAlex Vesker /* STE build functions */ 35614c32fd1SAlex Vesker int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 35714c32fd1SAlex Vesker u8 match_criteria, 35814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 35914c32fd1SAlex Vesker struct mlx5dr_match_param *value); 36014c32fd1SAlex Vesker int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 36114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 36214c32fd1SAlex Vesker struct mlx5dr_match_param *value, 36314c32fd1SAlex Vesker u8 *ste_arr); 3645212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, 3655212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *builder, 36614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 36714c32fd1SAlex Vesker bool inner, bool rx); 3685212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, 3695212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37114c32fd1SAlex Vesker bool inner, bool rx); 3725212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, 3735212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37514c32fd1SAlex Vesker bool inner, bool rx); 3765212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, 3775212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37914c32fd1SAlex Vesker bool inner, bool rx); 3805212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, 3815212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 38214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 38314c32fd1SAlex Vesker bool inner, bool rx); 3845212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, 3855212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 38614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 38714c32fd1SAlex Vesker bool inner, bool rx); 3885212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, 3895212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39114c32fd1SAlex Vesker bool inner, bool rx); 3925212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, 3935212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39514c32fd1SAlex Vesker bool inner, bool rx); 3965212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, 3975212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39914c32fd1SAlex Vesker bool inner, bool rx); 4005212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, 4015212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 40214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 40314c32fd1SAlex Vesker bool inner, bool rx); 4045212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, 4055212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 40614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 40714c32fd1SAlex Vesker bool inner, bool rx); 4085212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, 4095212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 41114c32fd1SAlex Vesker bool inner, bool rx); 4125212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, 4135212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 41514c32fd1SAlex Vesker bool inner, bool rx); 41635ba005dSYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx, 41735ba005dSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41835ba005dSYevgeny Kliteynik struct mlx5dr_match_param *mask, 41935ba005dSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 42035ba005dSYevgeny Kliteynik bool inner, bool rx); 42135ba005dSYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx, 42235ba005dSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 42335ba005dSYevgeny Kliteynik struct mlx5dr_match_param *mask, 42435ba005dSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 42535ba005dSYevgeny Kliteynik bool inner, bool rx); 4264923938dSYevgeny Kliteynik void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, 4275212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 42814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 42914c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps, 43014c32fd1SAlex Vesker bool inner, bool rx); 4315212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, 4325212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43314c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 43414c32fd1SAlex Vesker bool inner, bool rx); 4355212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, 4365212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 437b6d12238SYevgeny Kliteynik struct mlx5dr_match_param *mask, 438b6d12238SYevgeny Kliteynik bool inner, bool rx); 4393442e033SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, 4403442e033SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 4413442e033SYevgeny Kliteynik struct mlx5dr_match_param *mask, 4423442e033SYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 4433442e033SYevgeny Kliteynik bool inner, bool rx); 444df9dd15aSYevgeny Kliteynik void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx, 445df9dd15aSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 446df9dd15aSYevgeny Kliteynik struct mlx5dr_match_param *mask, 447df9dd15aSYevgeny Kliteynik bool inner, bool rx); 448df9dd15aSYevgeny Kliteynik void mlx5dr_ste_build_tnl_gtpu_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 449df9dd15aSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 450df9dd15aSYevgeny Kliteynik struct mlx5dr_match_param *mask, 451df9dd15aSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 452df9dd15aSYevgeny Kliteynik bool inner, bool rx); 453df9dd15aSYevgeny Kliteynik void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 454df9dd15aSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 455df9dd15aSYevgeny Kliteynik struct mlx5dr_match_param *mask, 456df9dd15aSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 457df9dd15aSYevgeny Kliteynik bool inner, bool rx); 4585212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, 4595212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 46014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 46114c32fd1SAlex Vesker bool inner, bool rx); 4625212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, 4635212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 46414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 46514c32fd1SAlex Vesker bool inner, bool rx); 4665212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, 4675212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 46814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 46914c32fd1SAlex Vesker bool inner, bool rx); 4705212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, 4715212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 47214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 473640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn, 47414c32fd1SAlex Vesker bool inner, bool rx); 475160e9cb3SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 476160e9cb3SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 477160e9cb3SYevgeny Kliteynik struct mlx5dr_match_param *mask, 478160e9cb3SYevgeny Kliteynik bool inner, bool rx); 479160e9cb3SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 480160e9cb3SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 481160e9cb3SYevgeny Kliteynik struct mlx5dr_match_param *mask, 482160e9cb3SYevgeny Kliteynik bool inner, bool rx); 48314c32fd1SAlex Vesker void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 48414c32fd1SAlex Vesker 48514c32fd1SAlex Vesker /* Actions utils */ 48614c32fd1SAlex Vesker int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 48714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 48814c32fd1SAlex Vesker struct mlx5dr_action *actions[], 48914c32fd1SAlex Vesker u32 num_actions, 49014c32fd1SAlex Vesker u8 *ste_arr, 49114c32fd1SAlex Vesker u32 *new_hw_ste_arr_sz); 49214c32fd1SAlex Vesker 49314c32fd1SAlex Vesker struct mlx5dr_match_spec { 49414c32fd1SAlex Vesker u32 smac_47_16; /* Source MAC address of incoming packet */ 49514c32fd1SAlex Vesker /* Incoming packet Ethertype - this is the Ethertype 49614c32fd1SAlex Vesker * following the last VLAN tag of the packet 49714c32fd1SAlex Vesker */ 49814c32fd1SAlex Vesker u32 ethertype:16; 49914c32fd1SAlex Vesker u32 smac_15_0:16; /* Source MAC address of incoming packet */ 50014c32fd1SAlex Vesker u32 dmac_47_16; /* Destination MAC address of incoming packet */ 50114c32fd1SAlex Vesker /* VLAN ID of first VLAN tag in the incoming packet. 50214c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 50314c32fd1SAlex Vesker */ 50414c32fd1SAlex Vesker u32 first_vid:12; 50514c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the incoming packet. 50614c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 50714c32fd1SAlex Vesker */ 50814c32fd1SAlex Vesker u32 first_cfi:1; 50914c32fd1SAlex Vesker /* Priority of first VLAN tag in the incoming packet. 51014c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 51114c32fd1SAlex Vesker */ 51214c32fd1SAlex Vesker u32 first_prio:3; 51314c32fd1SAlex Vesker u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 51414c32fd1SAlex Vesker /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 51514c32fd1SAlex Vesker * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 51614c32fd1SAlex Vesker */ 51714c32fd1SAlex Vesker u32 tcp_flags:9; 51814c32fd1SAlex Vesker u32 ip_version:4; /* IP version */ 51914c32fd1SAlex Vesker u32 frag:1; /* Packet is an IP fragment */ 52014c32fd1SAlex Vesker /* The first vlan in the packet is s-vlan (0x8a88). 52114c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 52214c32fd1SAlex Vesker */ 52314c32fd1SAlex Vesker u32 svlan_tag:1; 52414c32fd1SAlex Vesker /* The first vlan in the packet is c-vlan (0x8100). 52514c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 52614c32fd1SAlex Vesker */ 52714c32fd1SAlex Vesker u32 cvlan_tag:1; 52814c32fd1SAlex Vesker /* Explicit Congestion Notification derived from 52914c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 53014c32fd1SAlex Vesker */ 53114c32fd1SAlex Vesker u32 ip_ecn:2; 53214c32fd1SAlex Vesker /* Differentiated Services Code Point derived from 53314c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 53414c32fd1SAlex Vesker */ 53514c32fd1SAlex Vesker u32 ip_dscp:6; 53614c32fd1SAlex Vesker u32 ip_protocol:8; /* IP protocol */ 53714c32fd1SAlex Vesker /* TCP destination port. 53814c32fd1SAlex Vesker * tcp and udp sport/dport are mutually exclusive 53914c32fd1SAlex Vesker */ 54014c32fd1SAlex Vesker u32 tcp_dport:16; 54114c32fd1SAlex Vesker /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 54214c32fd1SAlex Vesker u32 tcp_sport:16; 54314c32fd1SAlex Vesker u32 ttl_hoplimit:8; 54414c32fd1SAlex Vesker u32 reserved:24; 54514c32fd1SAlex Vesker /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 54614c32fd1SAlex Vesker u32 udp_dport:16; 54714c32fd1SAlex Vesker /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 54814c32fd1SAlex Vesker u32 udp_sport:16; 54914c32fd1SAlex Vesker /* IPv6 source address of incoming packets 55014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 55114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 55214c32fd1SAlex Vesker */ 55314c32fd1SAlex Vesker u32 src_ip_127_96; 55414c32fd1SAlex Vesker /* IPv6 source address of incoming packets 55514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 55614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 55714c32fd1SAlex Vesker */ 55814c32fd1SAlex Vesker u32 src_ip_95_64; 55914c32fd1SAlex Vesker /* IPv6 source address of incoming packets 56014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 56114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 56214c32fd1SAlex Vesker */ 56314c32fd1SAlex Vesker u32 src_ip_63_32; 56414c32fd1SAlex Vesker /* IPv6 source address of incoming packets 56514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 56614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 56714c32fd1SAlex Vesker */ 56814c32fd1SAlex Vesker u32 src_ip_31_0; 56914c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 57014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 57114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 57214c32fd1SAlex Vesker */ 57314c32fd1SAlex Vesker u32 dst_ip_127_96; 57414c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 57514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 57614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 57714c32fd1SAlex Vesker */ 57814c32fd1SAlex Vesker u32 dst_ip_95_64; 57914c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 58014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 58114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 58214c32fd1SAlex Vesker */ 58314c32fd1SAlex Vesker u32 dst_ip_63_32; 58414c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 58514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 58614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 58714c32fd1SAlex Vesker */ 58814c32fd1SAlex Vesker u32 dst_ip_31_0; 58914c32fd1SAlex Vesker }; 59014c32fd1SAlex Vesker 59114c32fd1SAlex Vesker struct mlx5dr_match_misc { 59214c32fd1SAlex Vesker u32 source_sqn:24; /* Source SQN */ 59314c32fd1SAlex Vesker u32 source_vhca_port:4; 59414c32fd1SAlex Vesker /* used with GRE, sequence number exist when gre_s_present == 1 */ 59514c32fd1SAlex Vesker u32 gre_s_present:1; 59614c32fd1SAlex Vesker /* used with GRE, key exist when gre_k_present == 1 */ 59714c32fd1SAlex Vesker u32 gre_k_present:1; 59814c32fd1SAlex Vesker u32 reserved_auto1:1; 59914c32fd1SAlex Vesker /* used with GRE, checksum exist when gre_c_present == 1 */ 60014c32fd1SAlex Vesker u32 gre_c_present:1; 60114c32fd1SAlex Vesker /* Source port.;0xffff determines wire port */ 60214c32fd1SAlex Vesker u32 source_port:16; 603640bdb1fSAlaa Hleihel u32 source_eswitch_owner_vhca_id:16; 60414c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the inner header of the incoming packet. 60514c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 60614c32fd1SAlex Vesker */ 60714c32fd1SAlex Vesker u32 inner_second_vid:12; 60814c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the inner header of the incoming packet. 60914c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 61014c32fd1SAlex Vesker */ 61114c32fd1SAlex Vesker u32 inner_second_cfi:1; 61214c32fd1SAlex Vesker /* Priority of second VLAN tag in the inner header of the incoming packet. 61314c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 61414c32fd1SAlex Vesker */ 61514c32fd1SAlex Vesker u32 inner_second_prio:3; 61614c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the outer header of the incoming packet. 61714c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 61814c32fd1SAlex Vesker */ 61914c32fd1SAlex Vesker u32 outer_second_vid:12; 62014c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the outer header of the incoming packet. 62114c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 62214c32fd1SAlex Vesker */ 62314c32fd1SAlex Vesker u32 outer_second_cfi:1; 62414c32fd1SAlex Vesker /* Priority of second VLAN tag in the outer header of the incoming packet. 62514c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 62614c32fd1SAlex Vesker */ 62714c32fd1SAlex Vesker u32 outer_second_prio:3; 62814c32fd1SAlex Vesker u32 gre_protocol:16; /* GRE Protocol (outer) */ 62914c32fd1SAlex Vesker u32 reserved_auto3:12; 63014c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 63114c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 63214c32fd1SAlex Vesker */ 63314c32fd1SAlex Vesker u32 inner_second_svlan_tag:1; 63414c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 63514c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 63614c32fd1SAlex Vesker */ 63714c32fd1SAlex Vesker u32 outer_second_svlan_tag:1; 63814c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is c-vlan (0x8100). 63914c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 64014c32fd1SAlex Vesker */ 64114c32fd1SAlex Vesker u32 inner_second_cvlan_tag:1; 64214c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is c-vlan (0x8100). 64314c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 64414c32fd1SAlex Vesker */ 64514c32fd1SAlex Vesker u32 outer_second_cvlan_tag:1; 64614c32fd1SAlex Vesker u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 64714c32fd1SAlex Vesker u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 64814c32fd1SAlex Vesker u32 reserved_auto4:8; 64914c32fd1SAlex Vesker u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 65014c32fd1SAlex Vesker u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 65114c32fd1SAlex Vesker u32 reserved_auto5:7; 65214c32fd1SAlex Vesker u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 65314c32fd1SAlex Vesker u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 65414c32fd1SAlex Vesker u32 reserved_auto6:12; 65514c32fd1SAlex Vesker u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 65614c32fd1SAlex Vesker u32 reserved_auto7:12; 65714c32fd1SAlex Vesker u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 65814c32fd1SAlex Vesker u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 65914c32fd1SAlex Vesker u32 reserved_auto8:10; 66014c32fd1SAlex Vesker u32 bth_dst_qp:24; /* Destination QP in BTH header */ 66114c32fd1SAlex Vesker u32 reserved_auto9:8; 66214c32fd1SAlex Vesker u8 reserved_auto10[20]; 66314c32fd1SAlex Vesker }; 66414c32fd1SAlex Vesker 66514c32fd1SAlex Vesker struct mlx5dr_match_misc2 { 66614c32fd1SAlex Vesker u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 66714c32fd1SAlex Vesker u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 66814c32fd1SAlex Vesker u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 66914c32fd1SAlex Vesker u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 67014c32fd1SAlex Vesker u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 67114c32fd1SAlex Vesker u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 67214c32fd1SAlex Vesker u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 67314c32fd1SAlex Vesker u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 67414c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 67514c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 67614c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 67714c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 67814c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 67914c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 68014c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 68114c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 68214c32fd1SAlex Vesker u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 68314c32fd1SAlex Vesker u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 68414c32fd1SAlex Vesker u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 68514c32fd1SAlex Vesker u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 68614c32fd1SAlex Vesker u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 68714c32fd1SAlex Vesker u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 68814c32fd1SAlex Vesker u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 68914c32fd1SAlex Vesker u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 69014c32fd1SAlex Vesker u32 metadata_reg_a; /* metadata_reg_a */ 691356d411cSRaed Salem u8 reserved_auto2[12]; 69214c32fd1SAlex Vesker }; 69314c32fd1SAlex Vesker 69414c32fd1SAlex Vesker struct mlx5dr_match_misc3 { 69514c32fd1SAlex Vesker u32 inner_tcp_seq_num; 69614c32fd1SAlex Vesker u32 outer_tcp_seq_num; 69714c32fd1SAlex Vesker u32 inner_tcp_ack_num; 69814c32fd1SAlex Vesker u32 outer_tcp_ack_num; 69914c32fd1SAlex Vesker u32 outer_vxlan_gpe_vni:24; 70014c32fd1SAlex Vesker u32 reserved_auto1:8; 70114c32fd1SAlex Vesker u32 reserved_auto2:16; 70214c32fd1SAlex Vesker u32 outer_vxlan_gpe_flags:8; 70314c32fd1SAlex Vesker u32 outer_vxlan_gpe_next_protocol:8; 70414c32fd1SAlex Vesker u32 icmpv4_header_data; 70514c32fd1SAlex Vesker u32 icmpv6_header_data; 70640ca842cSYevgeny Kliteynik u8 icmpv6_code; 70740ca842cSYevgeny Kliteynik u8 icmpv6_type; 70840ca842cSYevgeny Kliteynik u8 icmpv4_code; 70940ca842cSYevgeny Kliteynik u8 icmpv4_type; 7103442e033SYevgeny Kliteynik u32 geneve_tlv_option_0_data; 711df9dd15aSYevgeny Kliteynik u8 gtpu_msg_flags; 712df9dd15aSYevgeny Kliteynik u8 gtpu_msg_type; 713df9dd15aSYevgeny Kliteynik u32 gtpu_teid; 714df9dd15aSYevgeny Kliteynik u32 gtpu_dw_2; 715df9dd15aSYevgeny Kliteynik u32 gtpu_first_ext_dw_0; 716df9dd15aSYevgeny Kliteynik u32 gtpu_dw_0; 71714c32fd1SAlex Vesker }; 71814c32fd1SAlex Vesker 719160e9cb3SYevgeny Kliteynik struct mlx5dr_match_misc4 { 720160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_0; 721160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_0; 722160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_1; 723160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_1; 724160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_2; 725160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_2; 726160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_3; 727160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_3; 728160e9cb3SYevgeny Kliteynik }; 729160e9cb3SYevgeny Kliteynik 73014c32fd1SAlex Vesker struct mlx5dr_match_param { 73114c32fd1SAlex Vesker struct mlx5dr_match_spec outer; 73214c32fd1SAlex Vesker struct mlx5dr_match_misc misc; 73314c32fd1SAlex Vesker struct mlx5dr_match_spec inner; 73414c32fd1SAlex Vesker struct mlx5dr_match_misc2 misc2; 73514c32fd1SAlex Vesker struct mlx5dr_match_misc3 misc3; 736160e9cb3SYevgeny Kliteynik struct mlx5dr_match_misc4 misc4; 73714c32fd1SAlex Vesker }; 73814c32fd1SAlex Vesker 739de1facafSYevgeny Kliteynik #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 74014c32fd1SAlex Vesker (_misc3)->icmpv4_code || \ 74114c32fd1SAlex Vesker (_misc3)->icmpv4_header_data) 74214c32fd1SAlex Vesker 74314c32fd1SAlex Vesker struct mlx5dr_esw_caps { 74414c32fd1SAlex Vesker u64 drop_icm_address_rx; 74514c32fd1SAlex Vesker u64 drop_icm_address_tx; 74614c32fd1SAlex Vesker u64 uplink_icm_address_rx; 74714c32fd1SAlex Vesker u64 uplink_icm_address_tx; 74864f45c0fSYevgeny Kliteynik u8 sw_owner:1; 74964f45c0fSYevgeny Kliteynik u8 sw_owner_v2:1; 75014c32fd1SAlex Vesker }; 75114c32fd1SAlex Vesker 75214c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap { 75314c32fd1SAlex Vesker u16 vport_gvmi; 75414c32fd1SAlex Vesker u16 vhca_gvmi; 755*f9f93bd5SYevgeny Kliteynik u16 num; 75614c32fd1SAlex Vesker u64 icm_address_rx; 75714c32fd1SAlex Vesker u64 icm_address_tx; 75814c32fd1SAlex Vesker }; 75914c32fd1SAlex Vesker 7607304d603SYevgeny Kliteynik struct mlx5dr_roce_cap { 7617304d603SYevgeny Kliteynik u8 roce_en:1; 7627304d603SYevgeny Kliteynik u8 fl_rc_qp_when_roce_disabled:1; 7637304d603SYevgeny Kliteynik u8 fl_rc_qp_when_roce_enabled:1; 7647304d603SYevgeny Kliteynik }; 7657304d603SYevgeny Kliteynik 76614c32fd1SAlex Vesker struct mlx5dr_cmd_caps { 76714c32fd1SAlex Vesker u16 gvmi; 76814c32fd1SAlex Vesker u64 nic_rx_drop_address; 76914c32fd1SAlex Vesker u64 nic_tx_drop_address; 77014c32fd1SAlex Vesker u64 nic_tx_allow_address; 77114c32fd1SAlex Vesker u64 esw_rx_drop_address; 77214c32fd1SAlex Vesker u64 esw_tx_drop_address; 77314c32fd1SAlex Vesker u32 log_icm_size; 77414c32fd1SAlex Vesker u64 hdr_modify_icm_addr; 77514c32fd1SAlex Vesker u32 flex_protocols; 77614c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw0; 77714c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw1; 77814c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw0; 77914c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw1; 7803442e033SYevgeny Kliteynik u8 flex_parser_id_geneve_tlv_option_0; 78135ba005dSYevgeny Kliteynik u8 flex_parser_id_mpls_over_gre; 78235ba005dSYevgeny Kliteynik u8 flex_parser_id_mpls_over_udp; 783df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_dw_0; 784df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_teid; 785df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_dw_2; 786df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_first_ext_dw_0; 78714c32fd1SAlex Vesker u8 max_ft_level; 78814c32fd1SAlex Vesker u16 roce_min_src_udp; 78914c32fd1SAlex Vesker u8 num_esw_ports; 790d421e466SYevgeny Kliteynik u8 sw_format_ver; 79114c32fd1SAlex Vesker bool eswitch_manager; 79214c32fd1SAlex Vesker bool rx_sw_owner; 79314c32fd1SAlex Vesker bool tx_sw_owner; 79414c32fd1SAlex Vesker bool fdb_sw_owner; 79564f45c0fSYevgeny Kliteynik u8 rx_sw_owner_v2:1; 79664f45c0fSYevgeny Kliteynik u8 tx_sw_owner_v2:1; 79764f45c0fSYevgeny Kliteynik u8 fdb_sw_owner_v2:1; 79814c32fd1SAlex Vesker u32 num_vports; 79914c32fd1SAlex Vesker struct mlx5dr_esw_caps esw_caps; 80014c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *vports_caps; 80114c32fd1SAlex Vesker bool prio_tag_required; 8027304d603SYevgeny Kliteynik struct mlx5dr_roce_cap roce_caps; 803aeacb52aSYevgeny Kliteynik u8 isolate_vl_tc:1; 80414c32fd1SAlex Vesker }; 80514c32fd1SAlex Vesker 80646f2a8aeSYevgeny Kliteynik enum mlx5dr_domain_nic_type { 80746f2a8aeSYevgeny Kliteynik DR_DOMAIN_NIC_TYPE_RX, 80846f2a8aeSYevgeny Kliteynik DR_DOMAIN_NIC_TYPE_TX, 80946f2a8aeSYevgeny Kliteynik }; 81046f2a8aeSYevgeny Kliteynik 81114c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx { 81214c32fd1SAlex Vesker u64 drop_icm_addr; 81314c32fd1SAlex Vesker u64 default_icm_addr; 81446f2a8aeSYevgeny Kliteynik enum mlx5dr_domain_nic_type type; 815ed03a418SAlex Vesker struct mutex mutex; /* protect rx/tx domain */ 81614c32fd1SAlex Vesker }; 81714c32fd1SAlex Vesker 81814c32fd1SAlex Vesker struct mlx5dr_domain_info { 81914c32fd1SAlex Vesker bool supp_sw_steering; 82014c32fd1SAlex Vesker u32 max_inline_size; 82114c32fd1SAlex Vesker u32 max_send_wr; 82214c32fd1SAlex Vesker u32 max_log_sw_icm_sz; 82314c32fd1SAlex Vesker u32 max_log_action_icm_sz; 82414c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx rx; 82514c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx tx; 82614c32fd1SAlex Vesker struct mlx5dr_cmd_caps caps; 82714c32fd1SAlex Vesker }; 82814c32fd1SAlex Vesker 82914c32fd1SAlex Vesker struct mlx5dr_domain_cache { 83014c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft; 83114c32fd1SAlex Vesker }; 83214c32fd1SAlex Vesker 83314c32fd1SAlex Vesker struct mlx5dr_domain { 83414c32fd1SAlex Vesker struct mlx5dr_domain *peer_dmn; 83514c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 83614c32fd1SAlex Vesker u32 pdn; 83714c32fd1SAlex Vesker struct mlx5_uars_page *uar; 83814c32fd1SAlex Vesker enum mlx5dr_domain_type type; 83914c32fd1SAlex Vesker refcount_t refcount; 84014c32fd1SAlex Vesker struct mlx5dr_icm_pool *ste_icm_pool; 84114c32fd1SAlex Vesker struct mlx5dr_icm_pool *action_icm_pool; 84214c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring; 84314c32fd1SAlex Vesker struct mlx5dr_domain_info info; 84414c32fd1SAlex Vesker struct mlx5dr_domain_cache cache; 8455212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *ste_ctx; 84614c32fd1SAlex Vesker }; 84714c32fd1SAlex Vesker 84814c32fd1SAlex Vesker struct mlx5dr_table_rx_tx { 84914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_anchor; 85014c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn; 85114c32fd1SAlex Vesker u64 default_icm_addr; 85214c32fd1SAlex Vesker }; 85314c32fd1SAlex Vesker 85414c32fd1SAlex Vesker struct mlx5dr_table { 85514c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 85614c32fd1SAlex Vesker struct mlx5dr_table_rx_tx rx; 85714c32fd1SAlex Vesker struct mlx5dr_table_rx_tx tx; 85814c32fd1SAlex Vesker u32 level; 85914c32fd1SAlex Vesker u32 table_type; 86014c32fd1SAlex Vesker u32 table_id; 861988fd6b3SErez Shitrit u32 flags; 86214c32fd1SAlex Vesker struct list_head matcher_list; 86314c32fd1SAlex Vesker struct mlx5dr_action *miss_action; 86414c32fd1SAlex Vesker refcount_t refcount; 86514c32fd1SAlex Vesker }; 86614c32fd1SAlex Vesker 86714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx { 86814c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_htbl; 86914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *e_anchor; 87014c32fd1SAlex Vesker struct mlx5dr_ste_build *ste_builder; 871667f2646SAlex Vesker struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 872667f2646SAlex Vesker [DR_RULE_IPV_MAX] 873667f2646SAlex Vesker [DR_RULE_MAX_STES]; 87414c32fd1SAlex Vesker u8 num_of_builders; 875667f2646SAlex Vesker u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 87614c32fd1SAlex Vesker u64 default_icm_addr; 87714c32fd1SAlex Vesker struct mlx5dr_table_rx_tx *nic_tbl; 87814c32fd1SAlex Vesker }; 87914c32fd1SAlex Vesker 88014c32fd1SAlex Vesker struct mlx5dr_matcher { 88114c32fd1SAlex Vesker struct mlx5dr_table *tbl; 88214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx rx; 88314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx tx; 88414c32fd1SAlex Vesker struct list_head matcher_list; 885f6409299SHamdan Igbaria u32 prio; 88614c32fd1SAlex Vesker struct mlx5dr_match_param mask; 88714c32fd1SAlex Vesker u8 match_criteria; 88814c32fd1SAlex Vesker refcount_t refcount; 88914c32fd1SAlex Vesker struct mlx5dv_flow_matcher *dv_matcher; 89014c32fd1SAlex Vesker }; 89114c32fd1SAlex Vesker 8924781df92SYevgeny Kliteynik struct mlx5dr_ste_action_modify_field { 8934781df92SYevgeny Kliteynik u16 hw_field; 8944781df92SYevgeny Kliteynik u8 start; 8954781df92SYevgeny Kliteynik u8 end; 8964781df92SYevgeny Kliteynik u8 l3_type; 8974781df92SYevgeny Kliteynik u8 l4_type; 8984781df92SYevgeny Kliteynik }; 8994781df92SYevgeny Kliteynik 9009dac2966SJianbo Liu struct mlx5dr_action_rewrite { 90114c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 90214c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 90314c32fd1SAlex Vesker u8 *data; 90414c32fd1SAlex Vesker u16 num_of_actions; 90514c32fd1SAlex Vesker u32 index; 90614c32fd1SAlex Vesker u8 allow_rx:1; 90714c32fd1SAlex Vesker u8 allow_tx:1; 90814c32fd1SAlex Vesker u8 modify_ttl:1; 9099dac2966SJianbo Liu }; 9109dac2966SJianbo Liu 9119dac2966SJianbo Liu struct mlx5dr_action_reformat { 91214c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 9137ea9b398SYevgeny Kliteynik u32 id; 9147ea9b398SYevgeny Kliteynik u32 size; 9157ea9b398SYevgeny Kliteynik u8 param_0; 9167ea9b398SYevgeny Kliteynik u8 param_1; 9179dac2966SJianbo Liu }; 9189dac2966SJianbo Liu 9191ab6dc35SYevgeny Kliteynik struct mlx5dr_action_sampler { 9201ab6dc35SYevgeny Kliteynik struct mlx5dr_domain *dmn; 9211ab6dc35SYevgeny Kliteynik u64 rx_icm_addr; 9221ab6dc35SYevgeny Kliteynik u64 tx_icm_addr; 9231ab6dc35SYevgeny Kliteynik u32 sampler_id; 9241ab6dc35SYevgeny Kliteynik }; 9251ab6dc35SYevgeny Kliteynik 9269dac2966SJianbo Liu struct mlx5dr_action_dest_tbl { 92714c32fd1SAlex Vesker u8 is_fw_tbl:1; 92814c32fd1SAlex Vesker union { 92914c32fd1SAlex Vesker struct mlx5dr_table *tbl; 93014c32fd1SAlex Vesker struct { 931aec292eeSAlex Vesker struct mlx5dr_domain *dmn; 932aec292eeSAlex Vesker u32 id; 933b8853c96SAlex Vesker u32 group_id; 934aec292eeSAlex Vesker enum fs_flow_table_type type; 93514c32fd1SAlex Vesker u64 rx_icm_addr; 93614c32fd1SAlex Vesker u64 tx_icm_addr; 937b8853c96SAlex Vesker struct mlx5dr_action **ref_actions; 938b8853c96SAlex Vesker u32 num_of_ref_actions; 93914c32fd1SAlex Vesker } fw_tbl; 94014c32fd1SAlex Vesker }; 9419dac2966SJianbo Liu }; 9429dac2966SJianbo Liu 9439dac2966SJianbo Liu struct mlx5dr_action_ctr { 94414c32fd1SAlex Vesker u32 ctr_id; 94514c32fd1SAlex Vesker u32 offeset; 9469dac2966SJianbo Liu }; 9479dac2966SJianbo Liu 9489dac2966SJianbo Liu struct mlx5dr_action_vport { 94914c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 95014c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *caps; 9519dac2966SJianbo Liu }; 9529dac2966SJianbo Liu 9539dac2966SJianbo Liu struct mlx5dr_action_push_vlan { 95414c32fd1SAlex Vesker u32 vlan_hdr; /* tpid_pcp_dei_vid */ 9559dac2966SJianbo Liu }; 9569dac2966SJianbo Liu 9579dac2966SJianbo Liu struct mlx5dr_action_flow_tag { 95814c32fd1SAlex Vesker u32 flow_tag; 95914c32fd1SAlex Vesker }; 9609dac2966SJianbo Liu 9619dac2966SJianbo Liu struct mlx5dr_action { 9629dac2966SJianbo Liu enum mlx5dr_action_type action_type; 9639dac2966SJianbo Liu refcount_t refcount; 9649dac2966SJianbo Liu 9659dac2966SJianbo Liu union { 9669dac2966SJianbo Liu void *data; 9679dac2966SJianbo Liu struct mlx5dr_action_rewrite *rewrite; 9689dac2966SJianbo Liu struct mlx5dr_action_reformat *reformat; 9691ab6dc35SYevgeny Kliteynik struct mlx5dr_action_sampler *sampler; 9709dac2966SJianbo Liu struct mlx5dr_action_dest_tbl *dest_tbl; 9719dac2966SJianbo Liu struct mlx5dr_action_ctr *ctr; 9729dac2966SJianbo Liu struct mlx5dr_action_vport *vport; 9739dac2966SJianbo Liu struct mlx5dr_action_push_vlan *push_vlan; 9749dac2966SJianbo Liu struct mlx5dr_action_flow_tag *flow_tag; 9759dac2966SJianbo Liu }; 97614c32fd1SAlex Vesker }; 97714c32fd1SAlex Vesker 97814c32fd1SAlex Vesker enum mlx5dr_connect_type { 97914c32fd1SAlex Vesker CONNECT_HIT = 1, 98014c32fd1SAlex Vesker CONNECT_MISS = 2, 98114c32fd1SAlex Vesker }; 98214c32fd1SAlex Vesker 98314c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info { 98414c32fd1SAlex Vesker enum mlx5dr_connect_type type; 98514c32fd1SAlex Vesker union { 98614c32fd1SAlex Vesker struct mlx5dr_ste_htbl *hit_next_htbl; 98714c32fd1SAlex Vesker u64 miss_icm_addr; 98814c32fd1SAlex Vesker }; 98914c32fd1SAlex Vesker }; 99014c32fd1SAlex Vesker 99114c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx { 99214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher; 9938a015baeSYevgeny Kliteynik struct mlx5dr_ste *last_rule_ste; 99414c32fd1SAlex Vesker }; 99514c32fd1SAlex Vesker 99614c32fd1SAlex Vesker struct mlx5dr_rule { 99714c32fd1SAlex Vesker struct mlx5dr_matcher *matcher; 99814c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx rx; 99914c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx tx; 100014c32fd1SAlex Vesker struct list_head rule_actions_list; 100101723919SHamdan Igbaria u32 flow_source; 100214c32fd1SAlex Vesker }; 100314c32fd1SAlex Vesker 10048a015baeSYevgeny Kliteynik void mlx5dr_rule_set_last_member(struct mlx5dr_rule_rx_tx *nic_rule, 10058a015baeSYevgeny Kliteynik struct mlx5dr_ste *ste, 10068a015baeSYevgeny Kliteynik bool force); 10078a015baeSYevgeny Kliteynik int mlx5dr_rule_get_reverse_rule_members(struct mlx5dr_ste **ste_arr, 10088a015baeSYevgeny Kliteynik struct mlx5dr_ste *curr_ste, 10098a015baeSYevgeny Kliteynik int *num_of_stes); 101014c32fd1SAlex Vesker 101114c32fd1SAlex Vesker struct mlx5dr_icm_chunk { 1012a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem *buddy_mem; 101314c32fd1SAlex Vesker struct list_head chunk_list; 101414c32fd1SAlex Vesker u32 rkey; 101514c32fd1SAlex Vesker u32 num_of_entries; 101614c32fd1SAlex Vesker u32 byte_size; 101714c32fd1SAlex Vesker u64 icm_addr; 101814c32fd1SAlex Vesker u64 mr_addr; 101914c32fd1SAlex Vesker 1020a00cd878SYevgeny Kliteynik /* indicates the index of this chunk in the whole memory, 1021a00cd878SYevgeny Kliteynik * used for deleting the chunk from the buddy 1022a00cd878SYevgeny Kliteynik */ 1023a00cd878SYevgeny Kliteynik unsigned int seg; 1024a00cd878SYevgeny Kliteynik 102514c32fd1SAlex Vesker /* Memory optimisation */ 102614c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 102714c32fd1SAlex Vesker u8 *hw_ste_arr; 102814c32fd1SAlex Vesker struct list_head *miss_list; 102914c32fd1SAlex Vesker }; 103014c32fd1SAlex Vesker 1031ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn) 1032ed03a418SAlex Vesker { 1033ed03a418SAlex Vesker mutex_lock(&nic_dmn->mutex); 1034ed03a418SAlex Vesker } 1035ed03a418SAlex Vesker 1036ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn) 1037ed03a418SAlex Vesker { 1038ed03a418SAlex Vesker mutex_unlock(&nic_dmn->mutex); 1039ed03a418SAlex Vesker } 1040ed03a418SAlex Vesker 1041ed03a418SAlex Vesker static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn) 1042ed03a418SAlex Vesker { 1043ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.rx); 1044ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.tx); 1045ed03a418SAlex Vesker } 1046ed03a418SAlex Vesker 1047ed03a418SAlex Vesker static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn) 1048ed03a418SAlex Vesker { 1049ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.tx); 1050ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.rx); 1051ed03a418SAlex Vesker } 1052ed03a418SAlex Vesker 105314c32fd1SAlex Vesker int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 105414c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 1055667f2646SAlex Vesker enum mlx5dr_ipv outer_ipv, 1056667f2646SAlex Vesker enum mlx5dr_ipv inner_ipv); 105714c32fd1SAlex Vesker 1058a00cd878SYevgeny Kliteynik static inline int 1059a00cd878SYevgeny Kliteynik mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type) 1060a00cd878SYevgeny Kliteynik { 1061a00cd878SYevgeny Kliteynik if (icm_type == DR_ICM_TYPE_STE) 1062a00cd878SYevgeny Kliteynik return DR_STE_SIZE; 1063a00cd878SYevgeny Kliteynik 1064a00cd878SYevgeny Kliteynik return DR_MODIFY_ACTION_SIZE; 1065a00cd878SYevgeny Kliteynik } 1066a00cd878SYevgeny Kliteynik 106714c32fd1SAlex Vesker static inline u32 106814c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 106914c32fd1SAlex Vesker { 107014c32fd1SAlex Vesker return 1 << chunk_size; 107114c32fd1SAlex Vesker } 107214c32fd1SAlex Vesker 107314c32fd1SAlex Vesker static inline int 107414c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 107514c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type) 107614c32fd1SAlex Vesker { 107714c32fd1SAlex Vesker int num_of_entries; 107814c32fd1SAlex Vesker int entry_size; 107914c32fd1SAlex Vesker 1080a00cd878SYevgeny Kliteynik entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type); 108114c32fd1SAlex Vesker num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 108214c32fd1SAlex Vesker 108314c32fd1SAlex Vesker return entry_size * num_of_entries; 108414c32fd1SAlex Vesker } 108514c32fd1SAlex Vesker 108632c8e3b2SYevgeny Kliteynik static inline int 108732c8e3b2SYevgeny Kliteynik mlx5dr_ste_htbl_increase_threshold(struct mlx5dr_ste_htbl *htbl) 108832c8e3b2SYevgeny Kliteynik { 108932c8e3b2SYevgeny Kliteynik int num_of_entries = 109032c8e3b2SYevgeny Kliteynik mlx5dr_icm_pool_chunk_size_to_entries(htbl->chunk_size); 109132c8e3b2SYevgeny Kliteynik 109232c8e3b2SYevgeny Kliteynik /* Threshold is 50%, one is added to table of size 1 */ 109332c8e3b2SYevgeny Kliteynik return (num_of_entries + 1) / 2; 109432c8e3b2SYevgeny Kliteynik } 109532c8e3b2SYevgeny Kliteynik 109632c8e3b2SYevgeny Kliteynik static inline bool 109732c8e3b2SYevgeny Kliteynik mlx5dr_ste_htbl_may_grow(struct mlx5dr_ste_htbl *htbl) 109832c8e3b2SYevgeny Kliteynik { 109932c8e3b2SYevgeny Kliteynik if (htbl->chunk_size == DR_CHUNK_SIZE_MAX - 1 || !htbl->byte_mask) 110032c8e3b2SYevgeny Kliteynik return false; 110132c8e3b2SYevgeny Kliteynik 110232c8e3b2SYevgeny Kliteynik return true; 110332c8e3b2SYevgeny Kliteynik } 110432c8e3b2SYevgeny Kliteynik 110514c32fd1SAlex Vesker static inline struct mlx5dr_cmd_vport_cap * 1106*f9f93bd5SYevgeny Kliteynik mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u16 vport) 110714c32fd1SAlex Vesker { 110814c32fd1SAlex Vesker if (!caps->vports_caps || 110914c32fd1SAlex Vesker (vport >= caps->num_vports && vport != WIRE_PORT)) 111014c32fd1SAlex Vesker return NULL; 111114c32fd1SAlex Vesker 111214c32fd1SAlex Vesker if (vport == WIRE_PORT) 111314c32fd1SAlex Vesker vport = caps->num_vports; 111414c32fd1SAlex Vesker 111514c32fd1SAlex Vesker return &caps->vports_caps[vport]; 111614c32fd1SAlex Vesker } 111714c32fd1SAlex Vesker 111814c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details { 111914c32fd1SAlex Vesker u8 status; 112014c32fd1SAlex Vesker u8 level; 112114c32fd1SAlex Vesker u64 sw_owner_icm_root_1; 112214c32fd1SAlex Vesker u64 sw_owner_icm_root_0; 112314c32fd1SAlex Vesker }; 112414c32fd1SAlex Vesker 1125cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr { 1126cc78dbd7SAlex Vesker u32 table_type; 1127cc78dbd7SAlex Vesker u64 icm_addr_rx; 1128cc78dbd7SAlex Vesker u64 icm_addr_tx; 1129cc78dbd7SAlex Vesker u8 level; 1130cc78dbd7SAlex Vesker bool sw_owner; 1131cc78dbd7SAlex Vesker bool term_tbl; 1132cc78dbd7SAlex Vesker bool decap_en; 1133cc78dbd7SAlex Vesker bool reformat_en; 1134cc78dbd7SAlex Vesker }; 1135cc78dbd7SAlex Vesker 113614c32fd1SAlex Vesker /* internal API functions */ 113714c32fd1SAlex Vesker int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 113814c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps); 113914c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 114014c32fd1SAlex Vesker bool other_vport, u16 vport_number, 114114c32fd1SAlex Vesker u64 *icm_address_rx, 114214c32fd1SAlex Vesker u64 *icm_address_tx); 114314c32fd1SAlex Vesker int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 114414c32fd1SAlex Vesker bool other_vport, u16 vport_number, u16 *gvmi); 114514c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 114614c32fd1SAlex Vesker struct mlx5dr_esw_caps *caps); 11471ab6dc35SYevgeny Kliteynik int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev, 11481ab6dc35SYevgeny Kliteynik u32 sampler_id, 11491ab6dc35SYevgeny Kliteynik u64 *rx_icm_addr, 11501ab6dc35SYevgeny Kliteynik u64 *tx_icm_addr); 115114c32fd1SAlex Vesker int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 115214c32fd1SAlex Vesker int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 115314c32fd1SAlex Vesker u32 table_type, 115414c32fd1SAlex Vesker u32 table_id, 115514c32fd1SAlex Vesker u32 group_id, 115614c32fd1SAlex Vesker u32 modify_header_id, 1157*f9f93bd5SYevgeny Kliteynik u16 vport_id); 115814c32fd1SAlex Vesker int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 115914c32fd1SAlex Vesker u32 table_type, 116014c32fd1SAlex Vesker u32 table_id); 116114c32fd1SAlex Vesker int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 116214c32fd1SAlex Vesker u32 table_type, 116314c32fd1SAlex Vesker u8 num_of_actions, 116414c32fd1SAlex Vesker u64 *actions, 116514c32fd1SAlex Vesker u32 *modify_header_id); 116614c32fd1SAlex Vesker int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 116714c32fd1SAlex Vesker u32 modify_header_id); 116814c32fd1SAlex Vesker int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 116914c32fd1SAlex Vesker u32 table_type, 117014c32fd1SAlex Vesker u32 table_id, 117114c32fd1SAlex Vesker u32 *group_id); 117214c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 117314c32fd1SAlex Vesker u32 table_type, 117414c32fd1SAlex Vesker u32 table_id, 117514c32fd1SAlex Vesker u32 group_id); 117614c32fd1SAlex Vesker int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 1177cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr *attr, 117814c32fd1SAlex Vesker u64 *fdb_rx_icm_addr, 117914c32fd1SAlex Vesker u32 *table_id); 118014c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 118114c32fd1SAlex Vesker u32 table_id, 118214c32fd1SAlex Vesker u32 table_type); 118314c32fd1SAlex Vesker int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 118414c32fd1SAlex Vesker enum fs_flow_table_type type, 118514c32fd1SAlex Vesker u32 table_id, 118614c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details *output); 118714c32fd1SAlex Vesker int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 118814c32fd1SAlex Vesker enum mlx5_reformat_ctx_type rt, 11897ea9b398SYevgeny Kliteynik u8 reformat_param_0, 11907ea9b398SYevgeny Kliteynik u8 reformat_param_1, 119114c32fd1SAlex Vesker size_t reformat_size, 119214c32fd1SAlex Vesker void *reformat_data, 119314c32fd1SAlex Vesker u32 *reformat_id); 119414c32fd1SAlex Vesker void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 119514c32fd1SAlex Vesker u32 reformat_id); 119614c32fd1SAlex Vesker 119714c32fd1SAlex Vesker struct mlx5dr_cmd_gid_attr { 119814c32fd1SAlex Vesker u8 gid[16]; 119914c32fd1SAlex Vesker u8 mac[6]; 120014c32fd1SAlex Vesker u32 roce_ver; 120114c32fd1SAlex Vesker }; 120214c32fd1SAlex Vesker 120314c32fd1SAlex Vesker struct mlx5dr_cmd_qp_create_attr { 120414c32fd1SAlex Vesker u32 page_id; 120514c32fd1SAlex Vesker u32 pdn; 120614c32fd1SAlex Vesker u32 cqn; 120714c32fd1SAlex Vesker u32 pm_state; 120814c32fd1SAlex Vesker u32 service_type; 120914c32fd1SAlex Vesker u32 buff_umem_id; 121014c32fd1SAlex Vesker u32 db_umem_id; 121114c32fd1SAlex Vesker u32 sq_wqe_cnt; 121214c32fd1SAlex Vesker u32 rq_wqe_cnt; 121314c32fd1SAlex Vesker u32 rq_wqe_shift; 1214aeacb52aSYevgeny Kliteynik u8 isolate_vl_tc:1; 121514c32fd1SAlex Vesker }; 121614c32fd1SAlex Vesker 121714c32fd1SAlex Vesker int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 121814c32fd1SAlex Vesker u16 index, struct mlx5dr_cmd_gid_attr *attr); 121914c32fd1SAlex Vesker 122014c32fd1SAlex Vesker struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 122114c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type); 122214c32fd1SAlex Vesker void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 122314c32fd1SAlex Vesker 122414c32fd1SAlex Vesker struct mlx5dr_icm_chunk * 122514c32fd1SAlex Vesker mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 122614c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size); 122714c32fd1SAlex Vesker void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 12284fe45e1dSYevgeny Kliteynik 12294fe45e1dSYevgeny Kliteynik void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, 12304fe45e1dSYevgeny Kliteynik u8 *hw_ste_p, u32 ste_size); 123114c32fd1SAlex Vesker int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 123214c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 123314c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 123414c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info, 123514c32fd1SAlex Vesker bool update_hw_ste); 12366b93b400SYevgeny Kliteynik void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, 12376b93b400SYevgeny Kliteynik u16 gvmi, 123846f2a8aeSYevgeny Kliteynik enum mlx5dr_domain_nic_type nic_type, 123914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 124014c32fd1SAlex Vesker u8 *formatted_ste, 124114c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info); 124214c32fd1SAlex Vesker void mlx5dr_ste_copy_param(u8 match_criteria, 124314c32fd1SAlex Vesker struct mlx5dr_match_param *set_param, 124414c32fd1SAlex Vesker struct mlx5dr_match_parameters *mask); 124514c32fd1SAlex Vesker 124614c32fd1SAlex Vesker struct mlx5dr_qp { 124714c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 124814c32fd1SAlex Vesker struct mlx5_wq_qp wq; 124914c32fd1SAlex Vesker struct mlx5_uars_page *uar; 125014c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 1251f93f4f4fSLeon Romanovsky u32 qpn; 125214c32fd1SAlex Vesker struct { 125314c32fd1SAlex Vesker unsigned int pc; 125414c32fd1SAlex Vesker unsigned int cc; 125514c32fd1SAlex Vesker unsigned int size; 125614c32fd1SAlex Vesker unsigned int *wqe_head; 125714c32fd1SAlex Vesker unsigned int wqe_cnt; 125814c32fd1SAlex Vesker } sq; 125914c32fd1SAlex Vesker struct { 126014c32fd1SAlex Vesker unsigned int pc; 126114c32fd1SAlex Vesker unsigned int cc; 126214c32fd1SAlex Vesker unsigned int size; 126314c32fd1SAlex Vesker unsigned int wqe_cnt; 126414c32fd1SAlex Vesker } rq; 126514c32fd1SAlex Vesker int max_inline_data; 126614c32fd1SAlex Vesker }; 126714c32fd1SAlex Vesker 126814c32fd1SAlex Vesker struct mlx5dr_cq { 126914c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 127014c32fd1SAlex Vesker struct mlx5_cqwq wq; 127114c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 127214c32fd1SAlex Vesker struct mlx5_core_cq mcq; 127314c32fd1SAlex Vesker struct mlx5dr_qp *qp; 127414c32fd1SAlex Vesker }; 127514c32fd1SAlex Vesker 127614c32fd1SAlex Vesker struct mlx5dr_mr { 127714c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 127814c32fd1SAlex Vesker struct mlx5_core_mkey mkey; 127914c32fd1SAlex Vesker dma_addr_t dma_addr; 128014c32fd1SAlex Vesker void *addr; 128114c32fd1SAlex Vesker size_t size; 128214c32fd1SAlex Vesker }; 128314c32fd1SAlex Vesker 128414c32fd1SAlex Vesker #define MAX_SEND_CQE 64 128514c32fd1SAlex Vesker #define MIN_READ_SYNC 64 128614c32fd1SAlex Vesker 128714c32fd1SAlex Vesker struct mlx5dr_send_ring { 128814c32fd1SAlex Vesker struct mlx5dr_cq *cq; 128914c32fd1SAlex Vesker struct mlx5dr_qp *qp; 129014c32fd1SAlex Vesker struct mlx5dr_mr *mr; 129114c32fd1SAlex Vesker /* How much wqes are waiting for completion */ 129214c32fd1SAlex Vesker u32 pending_wqe; 129314c32fd1SAlex Vesker /* Signal request per this trash hold value */ 129414c32fd1SAlex Vesker u16 signal_th; 129514c32fd1SAlex Vesker /* Each post_send_size less than max_post_send_size */ 129614c32fd1SAlex Vesker u32 max_post_send_size; 129714c32fd1SAlex Vesker /* manage the send queue */ 129814c32fd1SAlex Vesker u32 tx_head; 129914c32fd1SAlex Vesker void *buf; 130014c32fd1SAlex Vesker u32 buf_size; 130114c32fd1SAlex Vesker u8 sync_buff[MIN_READ_SYNC]; 130214c32fd1SAlex Vesker struct mlx5dr_mr *sync_mr; 1303cedb2819SAlex Vesker spinlock_t lock; /* Protect the data path of the send ring */ 1304d5a84e96SYevgeny Kliteynik bool err_state; /* send_ring is not usable in err state */ 130514c32fd1SAlex Vesker }; 130614c32fd1SAlex Vesker 130714c32fd1SAlex Vesker int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 130814c32fd1SAlex Vesker void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 130914c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring); 131014c32fd1SAlex Vesker int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 131114c32fd1SAlex Vesker int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 131214c32fd1SAlex Vesker struct mlx5dr_ste *ste, 131314c32fd1SAlex Vesker u8 *data, 131414c32fd1SAlex Vesker u16 size, 131514c32fd1SAlex Vesker u16 offset); 131614c32fd1SAlex Vesker int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 131714c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 131814c32fd1SAlex Vesker u8 *formatted_ste, u8 *mask); 131914c32fd1SAlex Vesker int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 132014c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 132114c32fd1SAlex Vesker u8 *ste_init_data, 132214c32fd1SAlex Vesker bool update_hw_ste); 132314c32fd1SAlex Vesker int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 132414c32fd1SAlex Vesker struct mlx5dr_action *action); 132514c32fd1SAlex Vesker 13266de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info { 13276de03d2dSErez Shitrit u32 id; 13286de03d2dSErez Shitrit u16 vport; 13296de03d2dSErez Shitrit enum fs_flow_table_type type; 13306de03d2dSErez Shitrit }; 13316de03d2dSErez Shitrit 13326de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info { 13336de03d2dSErez Shitrit enum mlx5_flow_destination_type type; 13346de03d2dSErez Shitrit union { 13356de03d2dSErez Shitrit u32 tir_num; 13366de03d2dSErez Shitrit u32 ft_num; 13376de03d2dSErez Shitrit u32 ft_id; 13386de03d2dSErez Shitrit u32 counter_id; 13391ab6dc35SYevgeny Kliteynik u32 sampler_id; 13406de03d2dSErez Shitrit struct { 13416de03d2dSErez Shitrit u16 num; 13426de03d2dSErez Shitrit u16 vhca_id; 13436de03d2dSErez Shitrit u32 reformat_id; 13446de03d2dSErez Shitrit u8 flags; 13456de03d2dSErez Shitrit } vport; 13466de03d2dSErez Shitrit }; 13476de03d2dSErez Shitrit }; 13486de03d2dSErez Shitrit 13496de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info { 13506de03d2dSErez Shitrit u32 dests_size; 13516de03d2dSErez Shitrit u32 index; 13526de03d2dSErez Shitrit struct mlx5_flow_context flow_context; 13536de03d2dSErez Shitrit u32 *val; 13546de03d2dSErez Shitrit struct mlx5_flow_act action; 13556de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 135663b85f49SYevgeny Kliteynik bool ignore_flow_level; 13576de03d2dSErez Shitrit }; 13586de03d2dSErez Shitrit 13596de03d2dSErez Shitrit int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 13606de03d2dSErez Shitrit int opmod, int modify_mask, 13616de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info *ft, 13626de03d2dSErez Shitrit u32 group_id, 13636de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info *fte); 13646de03d2dSErez Shitrit 1365a283ea1bSYevgeny Kliteynik bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps); 1366a283ea1bSYevgeny Kliteynik 136714c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft { 136814c32fd1SAlex Vesker u64 rx_icm_addr; 136914c32fd1SAlex Vesker u32 table_id; 137014c32fd1SAlex Vesker u32 group_id; 137114c32fd1SAlex Vesker u32 modify_hdr_id; 137214c32fd1SAlex Vesker }; 137314c32fd1SAlex Vesker 137414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft * 1375*f9f93bd5SYevgeny Kliteynik mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u16 vport_num); 137614c32fd1SAlex Vesker void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 137714c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 137814c32fd1SAlex Vesker int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 1379*f9f93bd5SYevgeny Kliteynik u16 vport_num, 138014c32fd1SAlex Vesker u64 *rx_icm_addr); 138134583beeSErez Shitrit int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 138234583beeSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest, 138334583beeSErez Shitrit int num_dest, 138434583beeSErez Shitrit bool reformat_req, 138534583beeSErez Shitrit u32 *tbl_id, 138663b85f49SYevgeny Kliteynik u32 *group_id, 138763b85f49SYevgeny Kliteynik bool ignore_flow_level); 138834583beeSErez Shitrit void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 138934583beeSErez Shitrit u32 group_id); 139014c32fd1SAlex Vesker #endif /* _DR_TYPES_H_ */ 1391