114c32fd1SAlex Vesker /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 214c32fd1SAlex Vesker /* Copyright (c) 2019, Mellanox Technologies */ 314c32fd1SAlex Vesker 414c32fd1SAlex Vesker #ifndef _DR_TYPES_ 514c32fd1SAlex Vesker #define _DR_TYPES_ 614c32fd1SAlex Vesker 77ae8ac9aSYevgeny Kliteynik #include <linux/mlx5/vport.h> 814c32fd1SAlex Vesker #include <linux/refcount.h> 914c32fd1SAlex Vesker #include "fs_core.h" 1014c32fd1SAlex Vesker #include "wq.h" 1114c32fd1SAlex Vesker #include "lib/mlx5.h" 1214c32fd1SAlex Vesker #include "mlx5_ifc_dr.h" 1314c32fd1SAlex Vesker #include "mlx5dr.h" 149222f0b2SMuhammad Sammar #include "dr_dbg.h" 1514c32fd1SAlex Vesker 163442e033SYevgeny Kliteynik #define DR_RULE_MAX_STES 18 1714c32fd1SAlex Vesker #define DR_ACTION_MAX_STES 5 1814c32fd1SAlex Vesker #define DR_STE_SVLAN 0x1 1914c32fd1SAlex Vesker #define DR_STE_CVLAN 0x2 20699d531fSMuhammad Sammar #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) 21160e9cb3SYevgeny Kliteynik #define DR_NUM_OF_FLEX_PARSERS 8 22160e9cb3SYevgeny Kliteynik #define DR_STE_MAX_FLEX_0_ID 3 23160e9cb3SYevgeny Kliteynik #define DR_STE_MAX_FLEX_1_ID 7 24b47dddc6SYevgeny Kliteynik #define DR_ACTION_CACHE_LINE_SIZE 64 2514c32fd1SAlex Vesker 2614c32fd1SAlex Vesker #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 2714c32fd1SAlex Vesker #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 2814c32fd1SAlex Vesker #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 2914c32fd1SAlex Vesker 30108ff821SYevgeny Kliteynik struct mlx5dr_ptrn_mgr; 31108ff821SYevgeny Kliteynik 32df9dd15aSYevgeny Kliteynik static inline bool dr_is_flex_parser_0_id(u8 parser_id) 33df9dd15aSYevgeny Kliteynik { 34df9dd15aSYevgeny Kliteynik return parser_id <= DR_STE_MAX_FLEX_0_ID; 35df9dd15aSYevgeny Kliteynik } 36df9dd15aSYevgeny Kliteynik 37df9dd15aSYevgeny Kliteynik static inline bool dr_is_flex_parser_1_id(u8 parser_id) 38df9dd15aSYevgeny Kliteynik { 39df9dd15aSYevgeny Kliteynik return parser_id > DR_STE_MAX_FLEX_0_ID; 40df9dd15aSYevgeny Kliteynik } 41df9dd15aSYevgeny Kliteynik 4214c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size { 4314c32fd1SAlex Vesker DR_CHUNK_SIZE_1, 4414c32fd1SAlex Vesker DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 4514c32fd1SAlex Vesker DR_CHUNK_SIZE_2, 4614c32fd1SAlex Vesker DR_CHUNK_SIZE_4, 4714c32fd1SAlex Vesker DR_CHUNK_SIZE_8, 4814c32fd1SAlex Vesker DR_CHUNK_SIZE_16, 4914c32fd1SAlex Vesker DR_CHUNK_SIZE_32, 5014c32fd1SAlex Vesker DR_CHUNK_SIZE_64, 5114c32fd1SAlex Vesker DR_CHUNK_SIZE_128, 5214c32fd1SAlex Vesker DR_CHUNK_SIZE_256, 5314c32fd1SAlex Vesker DR_CHUNK_SIZE_512, 5414c32fd1SAlex Vesker DR_CHUNK_SIZE_1K, 5514c32fd1SAlex Vesker DR_CHUNK_SIZE_2K, 5614c32fd1SAlex Vesker DR_CHUNK_SIZE_4K, 5714c32fd1SAlex Vesker DR_CHUNK_SIZE_8K, 5814c32fd1SAlex Vesker DR_CHUNK_SIZE_16K, 5914c32fd1SAlex Vesker DR_CHUNK_SIZE_32K, 6014c32fd1SAlex Vesker DR_CHUNK_SIZE_64K, 6114c32fd1SAlex Vesker DR_CHUNK_SIZE_128K, 6214c32fd1SAlex Vesker DR_CHUNK_SIZE_256K, 6314c32fd1SAlex Vesker DR_CHUNK_SIZE_512K, 6414c32fd1SAlex Vesker DR_CHUNK_SIZE_1024K, 6514c32fd1SAlex Vesker DR_CHUNK_SIZE_2048K, 6614c32fd1SAlex Vesker DR_CHUNK_SIZE_MAX, 6714c32fd1SAlex Vesker }; 6814c32fd1SAlex Vesker 6914c32fd1SAlex Vesker enum mlx5dr_icm_type { 7014c32fd1SAlex Vesker DR_ICM_TYPE_STE, 7114c32fd1SAlex Vesker DR_ICM_TYPE_MODIFY_ACTION, 72108ff821SYevgeny Kliteynik DR_ICM_TYPE_MODIFY_HDR_PTRN, 7314c32fd1SAlex Vesker }; 7414c32fd1SAlex Vesker 7514c32fd1SAlex Vesker static inline enum mlx5dr_icm_chunk_size 7614c32fd1SAlex Vesker mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 7714c32fd1SAlex Vesker { 7814c32fd1SAlex Vesker chunk += 2; 7914c32fd1SAlex Vesker if (chunk < DR_CHUNK_SIZE_MAX) 8014c32fd1SAlex Vesker return chunk; 8114c32fd1SAlex Vesker 8214c32fd1SAlex Vesker return DR_CHUNK_SIZE_MAX; 8314c32fd1SAlex Vesker } 8414c32fd1SAlex Vesker 8514c32fd1SAlex Vesker enum { 8614c32fd1SAlex Vesker DR_STE_SIZE = 64, 8714c32fd1SAlex Vesker DR_STE_SIZE_CTRL = 32, 88e046b86eSYevgeny Kliteynik DR_STE_SIZE_MATCH_TAG = 32, 8914c32fd1SAlex Vesker DR_STE_SIZE_TAG = 16, 9014c32fd1SAlex Vesker DR_STE_SIZE_MASK = 16, 9114c32fd1SAlex Vesker DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 9214c32fd1SAlex Vesker }; 9314c32fd1SAlex Vesker 94d7418b4eSYevgeny Kliteynik enum mlx5dr_ste_ctx_action_cap { 95d7418b4eSYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_NONE = 0, 962de40f68SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_TX_POP = 1 << 0, 972de40f68SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_RX_PUSH = 1 << 1, 982de40f68SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_RX_ENCAP = 1 << 2, 99638a07f1SYevgeny Kliteynik DR_STE_CTX_ACTION_CAP_POP_MDFY = 1 << 3, 100d7418b4eSYevgeny Kliteynik }; 101d7418b4eSYevgeny Kliteynik 10214c32fd1SAlex Vesker enum { 10314c32fd1SAlex Vesker DR_MODIFY_ACTION_SIZE = 8, 10414c32fd1SAlex Vesker }; 10514c32fd1SAlex Vesker 10614c32fd1SAlex Vesker enum mlx5dr_matcher_criteria { 10714c32fd1SAlex Vesker DR_MATCHER_CRITERIA_EMPTY = 0, 10814c32fd1SAlex Vesker DR_MATCHER_CRITERIA_OUTER = 1 << 0, 10914c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC = 1 << 1, 11014c32fd1SAlex Vesker DR_MATCHER_CRITERIA_INNER = 1 << 2, 11114c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 11214c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 113160e9cb3SYevgeny Kliteynik DR_MATCHER_CRITERIA_MISC4 = 1 << 5, 1148c2b4feeSMuhammad Sammar DR_MATCHER_CRITERIA_MISC5 = 1 << 6, 1158c2b4feeSMuhammad Sammar DR_MATCHER_CRITERIA_MAX = 1 << 7, 11614c32fd1SAlex Vesker }; 11714c32fd1SAlex Vesker 11814c32fd1SAlex Vesker enum mlx5dr_action_type { 11914c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L2_TO_L2, 12014c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L2, 12114c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L3_TO_L2, 12214c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L3, 12314c32fd1SAlex Vesker DR_ACTION_TYP_DROP, 12414c32fd1SAlex Vesker DR_ACTION_TYP_QP, 12514c32fd1SAlex Vesker DR_ACTION_TYP_FT, 12614c32fd1SAlex Vesker DR_ACTION_TYP_CTR, 12714c32fd1SAlex Vesker DR_ACTION_TYP_TAG, 12814c32fd1SAlex Vesker DR_ACTION_TYP_MODIFY_HDR, 12914c32fd1SAlex Vesker DR_ACTION_TYP_VPORT, 13014c32fd1SAlex Vesker DR_ACTION_TYP_POP_VLAN, 13114c32fd1SAlex Vesker DR_ACTION_TYP_PUSH_VLAN, 1327ea9b398SYevgeny Kliteynik DR_ACTION_TYP_INSERT_HDR, 1330139145fSYevgeny Kliteynik DR_ACTION_TYP_REMOVE_HDR, 1341ab6dc35SYevgeny Kliteynik DR_ACTION_TYP_SAMPLER, 1358920d92bSYevgeny Kliteynik DR_ACTION_TYP_ASO_FLOW_METER, 136be6d5daeSYevgeny Kliteynik DR_ACTION_TYP_RANGE, 13714c32fd1SAlex Vesker DR_ACTION_TYP_MAX, 13814c32fd1SAlex Vesker }; 13914c32fd1SAlex Vesker 140667f2646SAlex Vesker enum mlx5dr_ipv { 141667f2646SAlex Vesker DR_RULE_IPV4, 142667f2646SAlex Vesker DR_RULE_IPV6, 143667f2646SAlex Vesker DR_RULE_IPV_MAX, 144667f2646SAlex Vesker }; 145667f2646SAlex Vesker 14614c32fd1SAlex Vesker struct mlx5dr_icm_pool; 14714c32fd1SAlex Vesker struct mlx5dr_icm_chunk; 148a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem; 14914c32fd1SAlex Vesker struct mlx5dr_ste_htbl; 15014c32fd1SAlex Vesker struct mlx5dr_match_param; 15114c32fd1SAlex Vesker struct mlx5dr_cmd_caps; 1528a015baeSYevgeny Kliteynik struct mlx5dr_rule_rx_tx; 15314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx; 1545212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx; 15517b56073SYevgeny Kliteynik struct mlx5dr_send_info_pool; 1564519fc45SYevgeny Kliteynik struct mlx5dr_icm_hot_chunk; 15714c32fd1SAlex Vesker 15814c32fd1SAlex Vesker struct mlx5dr_ste { 15914c32fd1SAlex Vesker /* refcount: indicates the num of rules that using this ste */ 1604ce380caSYevgeny Kliteynik u32 refcount; 16114c32fd1SAlex Vesker 1628f853365SRongwei Liu /* this ste is part of a rule, located in ste's chain */ 1638f853365SRongwei Liu u8 ste_chain_location; 1648f853365SRongwei Liu 16514c32fd1SAlex Vesker /* attached to the miss_list head at each htbl entry */ 16614c32fd1SAlex Vesker struct list_head miss_list_node; 16714c32fd1SAlex Vesker 16814c32fd1SAlex Vesker /* this ste is member of htbl */ 16914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl; 17014c32fd1SAlex Vesker 17114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl; 17214c32fd1SAlex Vesker 1738a015baeSYevgeny Kliteynik /* The rule this STE belongs to */ 1748a015baeSYevgeny Kliteynik struct mlx5dr_rule_rx_tx *rule_rx_tx; 17514c32fd1SAlex Vesker }; 17614c32fd1SAlex Vesker 17714c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl { 17814c32fd1SAlex Vesker /* total number of valid entries belonging to this hash table. This 17914c32fd1SAlex Vesker * includes the non collision and collision entries 18014c32fd1SAlex Vesker */ 18114c32fd1SAlex Vesker unsigned int num_of_valid_entries; 18214c32fd1SAlex Vesker 18314c32fd1SAlex Vesker /* total number of collisions entries attached to this table */ 18414c32fd1SAlex Vesker unsigned int num_of_collisions; 18514c32fd1SAlex Vesker }; 18614c32fd1SAlex Vesker 18714c32fd1SAlex Vesker struct mlx5dr_ste_htbl { 188dd2d3c8dSYevgeny Kliteynik u16 lu_type; 18914c32fd1SAlex Vesker u16 byte_mask; 1904ce380caSYevgeny Kliteynik u32 refcount; 19114c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 19214c32fd1SAlex Vesker struct mlx5dr_ste *pointing_ste; 19314c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl ctrl; 19414c32fd1SAlex Vesker }; 19514c32fd1SAlex Vesker 19614c32fd1SAlex Vesker struct mlx5dr_ste_send_info { 19714c32fd1SAlex Vesker struct mlx5dr_ste *ste; 19814c32fd1SAlex Vesker struct list_head send_list; 19914c32fd1SAlex Vesker u16 size; 20014c32fd1SAlex Vesker u16 offset; 20114c32fd1SAlex Vesker u8 data_cont[DR_STE_SIZE]; 20214c32fd1SAlex Vesker u8 *data; 20314c32fd1SAlex Vesker }; 20414c32fd1SAlex Vesker 20514c32fd1SAlex Vesker void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 20614c32fd1SAlex Vesker u16 offset, u8 *data, 20714c32fd1SAlex Vesker struct mlx5dr_ste_send_info *ste_info, 20814c32fd1SAlex Vesker struct list_head *send_list, 20914c32fd1SAlex Vesker bool copy_data); 21014c32fd1SAlex Vesker 21114c32fd1SAlex Vesker struct mlx5dr_ste_build { 21214c32fd1SAlex Vesker u8 inner:1; 21314c32fd1SAlex Vesker u8 rx:1; 214640bdb1fSAlaa Hleihel u8 vhca_id_valid:1; 215640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn; 21614c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps; 217dd2d3c8dSYevgeny Kliteynik u16 lu_type; 21814c32fd1SAlex Vesker u16 byte_mask; 21914c32fd1SAlex Vesker u8 bit_mask[DR_STE_SIZE_MASK]; 22014c32fd1SAlex Vesker int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 22114c32fd1SAlex Vesker struct mlx5dr_ste_build *sb, 222e6b69bf3SYevgeny Kliteynik u8 *tag); 22314c32fd1SAlex Vesker }; 22414c32fd1SAlex Vesker 22514c32fd1SAlex Vesker struct mlx5dr_ste_htbl * 22614c32fd1SAlex Vesker mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 22714c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size, 228dd2d3c8dSYevgeny Kliteynik u16 lu_type, u16 byte_mask); 22914c32fd1SAlex Vesker 23014c32fd1SAlex Vesker int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 23114c32fd1SAlex Vesker 23214c32fd1SAlex Vesker static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 23314c32fd1SAlex Vesker { 2344ce380caSYevgeny Kliteynik htbl->refcount--; 2354ce380caSYevgeny Kliteynik if (!htbl->refcount) 23614c32fd1SAlex Vesker mlx5dr_ste_htbl_free(htbl); 23714c32fd1SAlex Vesker } 23814c32fd1SAlex Vesker 23914c32fd1SAlex Vesker static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 24014c32fd1SAlex Vesker { 2414ce380caSYevgeny Kliteynik htbl->refcount++; 24214c32fd1SAlex Vesker } 24314c32fd1SAlex Vesker 24414c32fd1SAlex Vesker /* STE utils */ 24514c32fd1SAlex Vesker u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 2461207a772SYevgeny Kliteynik bool mlx5dr_ste_is_miss_addr_set(struct mlx5dr_ste_ctx *ste_ctx, u8 *hw_ste_p); 2476b93b400SYevgeny Kliteynik void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, 2486b93b400SYevgeny Kliteynik u8 *hw_ste, u64 miss_addr); 2496b93b400SYevgeny Kliteynik void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, 2506b93b400SYevgeny Kliteynik u8 *hw_ste, u64 icm_addr, u32 ht_size); 2516b93b400SYevgeny Kliteynik void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, 2526b93b400SYevgeny Kliteynik u8 *hw_ste, 2536b93b400SYevgeny Kliteynik struct mlx5dr_ste_htbl *next_htbl); 25414c32fd1SAlex Vesker void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 25514c32fd1SAlex Vesker bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 25614c32fd1SAlex Vesker u8 ste_location); 25714c32fd1SAlex Vesker u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 25814c32fd1SAlex Vesker u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 25914c32fd1SAlex Vesker struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 26014c32fd1SAlex Vesker 26164c78942SYevgeny Kliteynik #define MLX5DR_MAX_VLANS 2 26264c78942SYevgeny Kliteynik 26364c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr { 26464c78942SYevgeny Kliteynik u32 modify_index; 26564c78942SYevgeny Kliteynik u16 modify_actions; 26664c78942SYevgeny Kliteynik u32 decap_index; 26764c78942SYevgeny Kliteynik u16 decap_actions; 26864c78942SYevgeny Kliteynik u8 decap_with_vlan:1; 26964c78942SYevgeny Kliteynik u64 final_icm_addr; 27064c78942SYevgeny Kliteynik u32 flow_tag; 27164c78942SYevgeny Kliteynik u32 ctr_id; 27264c78942SYevgeny Kliteynik u16 gvmi; 27364c78942SYevgeny Kliteynik u16 hit_gvmi; 2747ea9b398SYevgeny Kliteynik struct { 2757ea9b398SYevgeny Kliteynik u32 id; 2767ea9b398SYevgeny Kliteynik u32 size; 2777ea9b398SYevgeny Kliteynik u8 param_0; 2787ea9b398SYevgeny Kliteynik u8 param_1; 2797ea9b398SYevgeny Kliteynik } reformat; 28064c78942SYevgeny Kliteynik struct { 28164c78942SYevgeny Kliteynik int count; 28264c78942SYevgeny Kliteynik u32 headers[MLX5DR_MAX_VLANS]; 28364c78942SYevgeny Kliteynik } vlans; 2848920d92bSYevgeny Kliteynik 2858920d92bSYevgeny Kliteynik struct { 2868920d92bSYevgeny Kliteynik u32 obj_id; 2878920d92bSYevgeny Kliteynik u32 offset; 2888920d92bSYevgeny Kliteynik u8 dest_reg_id; 2898920d92bSYevgeny Kliteynik u8 init_color; 2908920d92bSYevgeny Kliteynik } aso_flow_meter; 291be6d5daeSYevgeny Kliteynik 292be6d5daeSYevgeny Kliteynik struct { 293be6d5daeSYevgeny Kliteynik u64 miss_icm_addr; 294be6d5daeSYevgeny Kliteynik u32 definer_id; 295be6d5daeSYevgeny Kliteynik u32 min; 296be6d5daeSYevgeny Kliteynik u32 max; 297be6d5daeSYevgeny Kliteynik } range; 29864c78942SYevgeny Kliteynik }; 29964c78942SYevgeny Kliteynik 3006b93b400SYevgeny Kliteynik void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, 3016b93b400SYevgeny Kliteynik struct mlx5dr_domain *dmn, 30264c78942SYevgeny Kliteynik u8 *action_type_set, 30364c78942SYevgeny Kliteynik u8 *last_ste, 30464c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 30564c78942SYevgeny Kliteynik u32 *added_stes); 3066b93b400SYevgeny Kliteynik void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, 3076b93b400SYevgeny Kliteynik struct mlx5dr_domain *dmn, 30864c78942SYevgeny Kliteynik u8 *action_type_set, 30964c78942SYevgeny Kliteynik u8 *last_ste, 31064c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 31164c78942SYevgeny Kliteynik u32 *added_stes); 31264c78942SYevgeny Kliteynik 3134781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, 3144781df92SYevgeny Kliteynik __be64 *hw_action, 3154781df92SYevgeny Kliteynik u8 hw_field, 3164781df92SYevgeny Kliteynik u8 shifter, 3174781df92SYevgeny Kliteynik u8 length, 3184781df92SYevgeny Kliteynik u32 data); 3194781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, 3204781df92SYevgeny Kliteynik __be64 *hw_action, 3214781df92SYevgeny Kliteynik u8 hw_field, 3224781df92SYevgeny Kliteynik u8 shifter, 3234781df92SYevgeny Kliteynik u8 length, 3244781df92SYevgeny Kliteynik u32 data); 3254781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, 3264781df92SYevgeny Kliteynik __be64 *hw_action, 3274781df92SYevgeny Kliteynik u8 dst_hw_field, 3284781df92SYevgeny Kliteynik u8 dst_shifter, 3294781df92SYevgeny Kliteynik u8 dst_len, 3304781df92SYevgeny Kliteynik u8 src_hw_field, 3314781df92SYevgeny Kliteynik u8 src_shifter); 3324781df92SYevgeny Kliteynik int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, 3334781df92SYevgeny Kliteynik void *data, 3344781df92SYevgeny Kliteynik u32 data_sz, 3354781df92SYevgeny Kliteynik u8 *hw_action, 3364781df92SYevgeny Kliteynik u32 hw_action_sz, 3374781df92SYevgeny Kliteynik u16 *used_hw_action_num); 3382533e726SYevgeny Kliteynik int mlx5dr_ste_alloc_modify_hdr(struct mlx5dr_action *action); 3392533e726SYevgeny Kliteynik void mlx5dr_ste_free_modify_hdr(struct mlx5dr_action *action); 3404781df92SYevgeny Kliteynik 3414781df92SYevgeny Kliteynik const struct mlx5dr_ste_action_modify_field * 3424781df92SYevgeny Kliteynik mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field); 3434781df92SYevgeny Kliteynik 3445212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); 34514c32fd1SAlex Vesker void mlx5dr_ste_free(struct mlx5dr_ste *ste, 34614c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 34714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher); 34814c32fd1SAlex Vesker static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 34914c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 35014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher) 35114c32fd1SAlex Vesker { 3524ce380caSYevgeny Kliteynik ste->refcount--; 3534ce380caSYevgeny Kliteynik if (!ste->refcount) 35414c32fd1SAlex Vesker mlx5dr_ste_free(ste, matcher, nic_matcher); 35514c32fd1SAlex Vesker } 35614c32fd1SAlex Vesker 35714c32fd1SAlex Vesker /* initial as 0, increased only when ste appears in a new rule */ 35814c32fd1SAlex Vesker static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 35914c32fd1SAlex Vesker { 3604ce380caSYevgeny Kliteynik ste->refcount++; 36114c32fd1SAlex Vesker } 36214c32fd1SAlex Vesker 36397ffd895SYevgeny Kliteynik static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste) 36497ffd895SYevgeny Kliteynik { 36597ffd895SYevgeny Kliteynik return !ste->refcount; 36697ffd895SYevgeny Kliteynik } 36797ffd895SYevgeny Kliteynik 36814c32fd1SAlex Vesker bool mlx5dr_ste_equal_tag(void *src, void *dst); 36914c32fd1SAlex Vesker int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 37014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 37114c32fd1SAlex Vesker struct mlx5dr_ste *ste, 37214c32fd1SAlex Vesker u8 *cur_hw_ste, 37314c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size log_table_size); 37414c32fd1SAlex Vesker 37514c32fd1SAlex Vesker /* STE build functions */ 37614c32fd1SAlex Vesker int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 37714c32fd1SAlex Vesker u8 match_criteria, 37814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37914c32fd1SAlex Vesker struct mlx5dr_match_param *value); 38014c32fd1SAlex Vesker int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 38114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 38214c32fd1SAlex Vesker struct mlx5dr_match_param *value, 38314c32fd1SAlex Vesker u8 *ste_arr); 3845212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, 3855212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *builder, 38614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 38714c32fd1SAlex Vesker bool inner, bool rx); 3885212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, 3895212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39114c32fd1SAlex Vesker bool inner, bool rx); 3925212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, 3935212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39514c32fd1SAlex Vesker bool inner, bool rx); 3965212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, 3975212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39914c32fd1SAlex Vesker bool inner, bool rx); 4005212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, 4015212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 40214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 40314c32fd1SAlex Vesker bool inner, bool rx); 4045212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, 4055212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 40614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 40714c32fd1SAlex Vesker bool inner, bool rx); 4085212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, 4095212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 41114c32fd1SAlex Vesker bool inner, bool rx); 4125212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, 4135212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 41514c32fd1SAlex Vesker bool inner, bool rx); 4165212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, 4175212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 41914c32fd1SAlex Vesker bool inner, bool rx); 4205212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, 4215212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 42214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 42314c32fd1SAlex Vesker bool inner, bool rx); 4245212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, 4255212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 42614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 42714c32fd1SAlex Vesker bool inner, bool rx); 4285212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, 4295212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 43114c32fd1SAlex Vesker bool inner, bool rx); 4325212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, 4335212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 43514c32fd1SAlex Vesker bool inner, bool rx); 43635ba005dSYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx, 43735ba005dSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43835ba005dSYevgeny Kliteynik struct mlx5dr_match_param *mask, 43935ba005dSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 44035ba005dSYevgeny Kliteynik bool inner, bool rx); 44135ba005dSYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx, 44235ba005dSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 44335ba005dSYevgeny Kliteynik struct mlx5dr_match_param *mask, 44435ba005dSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 44535ba005dSYevgeny Kliteynik bool inner, bool rx); 4464923938dSYevgeny Kliteynik void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, 4475212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 44814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 44914c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps, 45014c32fd1SAlex Vesker bool inner, bool rx); 4515212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, 4525212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 45314c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 45414c32fd1SAlex Vesker bool inner, bool rx); 4555212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, 4565212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 457b6d12238SYevgeny Kliteynik struct mlx5dr_match_param *mask, 458b6d12238SYevgeny Kliteynik bool inner, bool rx); 4593442e033SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, 4603442e033SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 4613442e033SYevgeny Kliteynik struct mlx5dr_match_param *mask, 4623442e033SYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 4633442e033SYevgeny Kliteynik bool inner, bool rx); 464f59464e2SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve_tlv_opt_exist(struct mlx5dr_ste_ctx *ste_ctx, 465f59464e2SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 466f59464e2SYevgeny Kliteynik struct mlx5dr_match_param *mask, 467f59464e2SYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 468f59464e2SYevgeny Kliteynik bool inner, bool rx); 469df9dd15aSYevgeny Kliteynik void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx, 470df9dd15aSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 471df9dd15aSYevgeny Kliteynik struct mlx5dr_match_param *mask, 472df9dd15aSYevgeny Kliteynik bool inner, bool rx); 473df9dd15aSYevgeny Kliteynik void mlx5dr_ste_build_tnl_gtpu_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 474df9dd15aSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 475df9dd15aSYevgeny Kliteynik struct mlx5dr_match_param *mask, 476df9dd15aSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 477df9dd15aSYevgeny Kliteynik bool inner, bool rx); 478df9dd15aSYevgeny Kliteynik void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 479df9dd15aSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 480df9dd15aSYevgeny Kliteynik struct mlx5dr_match_param *mask, 481df9dd15aSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 482df9dd15aSYevgeny Kliteynik bool inner, bool rx); 48309753babSMuhammad Sammar void mlx5dr_ste_build_tnl_header_0_1(struct mlx5dr_ste_ctx *ste_ctx, 48409753babSMuhammad Sammar struct mlx5dr_ste_build *sb, 48509753babSMuhammad Sammar struct mlx5dr_match_param *mask, 48609753babSMuhammad Sammar bool inner, bool rx); 4875212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, 4885212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 48914c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 49014c32fd1SAlex Vesker bool inner, bool rx); 4915212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, 4925212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 49314c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 49414c32fd1SAlex Vesker bool inner, bool rx); 4955212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, 4965212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 49714c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 49814c32fd1SAlex Vesker bool inner, bool rx); 4995212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, 5005212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 50114c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 502640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn, 50314c32fd1SAlex Vesker bool inner, bool rx); 504160e9cb3SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 505160e9cb3SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 506160e9cb3SYevgeny Kliteynik struct mlx5dr_match_param *mask, 507160e9cb3SYevgeny Kliteynik bool inner, bool rx); 508160e9cb3SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 509160e9cb3SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 510160e9cb3SYevgeny Kliteynik struct mlx5dr_match_param *mask, 511160e9cb3SYevgeny Kliteynik bool inner, bool rx); 51214c32fd1SAlex Vesker void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 51314c32fd1SAlex Vesker 51414c32fd1SAlex Vesker /* Actions utils */ 51514c32fd1SAlex Vesker int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 51614c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 51714c32fd1SAlex Vesker struct mlx5dr_action *actions[], 51814c32fd1SAlex Vesker u32 num_actions, 51914c32fd1SAlex Vesker u8 *ste_arr, 52014c32fd1SAlex Vesker u32 *new_hw_ste_arr_sz); 52114c32fd1SAlex Vesker 52214c32fd1SAlex Vesker struct mlx5dr_match_spec { 52314c32fd1SAlex Vesker u32 smac_47_16; /* Source MAC address of incoming packet */ 52414c32fd1SAlex Vesker /* Incoming packet Ethertype - this is the Ethertype 52514c32fd1SAlex Vesker * following the last VLAN tag of the packet 52614c32fd1SAlex Vesker */ 52714c32fd1SAlex Vesker u32 smac_15_0:16; /* Source MAC address of incoming packet */ 5287766c9b9SMuhammad Sammar u32 ethertype:16; 5297766c9b9SMuhammad Sammar 53014c32fd1SAlex Vesker u32 dmac_47_16; /* Destination MAC address of incoming packet */ 5317766c9b9SMuhammad Sammar 5327766c9b9SMuhammad Sammar u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 53314c32fd1SAlex Vesker /* Priority of first VLAN tag in the incoming packet. 53414c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 53514c32fd1SAlex Vesker */ 53614c32fd1SAlex Vesker u32 first_prio:3; 5377766c9b9SMuhammad Sammar /* CFI bit of first VLAN tag in the incoming packet. 5387766c9b9SMuhammad Sammar * Valid only when cvlan_tag==1 or svlan_tag==1 53914c32fd1SAlex Vesker */ 5407766c9b9SMuhammad Sammar u32 first_cfi:1; 5417766c9b9SMuhammad Sammar /* VLAN ID of first VLAN tag in the incoming packet. 5427766c9b9SMuhammad Sammar * Valid only when cvlan_tag==1 or svlan_tag==1 54314c32fd1SAlex Vesker */ 5447766c9b9SMuhammad Sammar u32 first_vid:12; 5457766c9b9SMuhammad Sammar 5467766c9b9SMuhammad Sammar u32 ip_protocol:8; /* IP protocol */ 54714c32fd1SAlex Vesker /* Differentiated Services Code Point derived from 54814c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 54914c32fd1SAlex Vesker */ 55014c32fd1SAlex Vesker u32 ip_dscp:6; 5517766c9b9SMuhammad Sammar /* Explicit Congestion Notification derived from 5527766c9b9SMuhammad Sammar * Traffic Class/TOS field of IPv6/v4 5537766c9b9SMuhammad Sammar */ 5547766c9b9SMuhammad Sammar u32 ip_ecn:2; 5557766c9b9SMuhammad Sammar /* The first vlan in the packet is c-vlan (0x8100). 5567766c9b9SMuhammad Sammar * cvlan_tag and svlan_tag cannot be set together 5577766c9b9SMuhammad Sammar */ 5587766c9b9SMuhammad Sammar u32 cvlan_tag:1; 5597766c9b9SMuhammad Sammar /* The first vlan in the packet is s-vlan (0x8a88). 5607766c9b9SMuhammad Sammar * cvlan_tag and svlan_tag cannot be set together 5617766c9b9SMuhammad Sammar */ 5627766c9b9SMuhammad Sammar u32 svlan_tag:1; 5637766c9b9SMuhammad Sammar u32 frag:1; /* Packet is an IP fragment */ 5647766c9b9SMuhammad Sammar u32 ip_version:4; /* IP version */ 5657766c9b9SMuhammad Sammar /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 5667766c9b9SMuhammad Sammar * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 5677766c9b9SMuhammad Sammar */ 5687766c9b9SMuhammad Sammar u32 tcp_flags:9; 5697766c9b9SMuhammad Sammar 5707766c9b9SMuhammad Sammar /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 5717766c9b9SMuhammad Sammar u32 tcp_sport:16; 57214c32fd1SAlex Vesker /* TCP destination port. 57314c32fd1SAlex Vesker * tcp and udp sport/dport are mutually exclusive 57414c32fd1SAlex Vesker */ 57514c32fd1SAlex Vesker u32 tcp_dport:16; 5767766c9b9SMuhammad Sammar 5775c422bfaSYevgeny Kliteynik u32 reserved_auto1:16; 5785c422bfaSYevgeny Kliteynik u32 ipv4_ihl:4; 5795c422bfaSYevgeny Kliteynik u32 reserved_auto2:4; 58014c32fd1SAlex Vesker u32 ttl_hoplimit:8; 5817766c9b9SMuhammad Sammar 58214c32fd1SAlex Vesker /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 58314c32fd1SAlex Vesker u32 udp_sport:16; 5847766c9b9SMuhammad Sammar /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 5857766c9b9SMuhammad Sammar u32 udp_dport:16; 5867766c9b9SMuhammad Sammar 58714c32fd1SAlex Vesker /* IPv6 source address of incoming packets 58814c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 58914c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 59014c32fd1SAlex Vesker */ 59114c32fd1SAlex Vesker u32 src_ip_127_96; 59214c32fd1SAlex Vesker /* IPv6 source address of incoming packets 59314c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 59414c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 59514c32fd1SAlex Vesker */ 59614c32fd1SAlex Vesker u32 src_ip_95_64; 59714c32fd1SAlex Vesker /* IPv6 source address of incoming packets 59814c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 59914c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 60014c32fd1SAlex Vesker */ 60114c32fd1SAlex Vesker u32 src_ip_63_32; 60214c32fd1SAlex Vesker /* IPv6 source address of incoming packets 60314c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 60414c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 60514c32fd1SAlex Vesker */ 60614c32fd1SAlex Vesker u32 src_ip_31_0; 60714c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 60814c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 60914c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 61014c32fd1SAlex Vesker */ 61114c32fd1SAlex Vesker u32 dst_ip_127_96; 61214c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 61314c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 61414c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 61514c32fd1SAlex Vesker */ 61614c32fd1SAlex Vesker u32 dst_ip_95_64; 61714c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 61814c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 61914c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 62014c32fd1SAlex Vesker */ 62114c32fd1SAlex Vesker u32 dst_ip_63_32; 62214c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 62314c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 62414c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 62514c32fd1SAlex Vesker */ 62614c32fd1SAlex Vesker u32 dst_ip_31_0; 62714c32fd1SAlex Vesker }; 62814c32fd1SAlex Vesker 62914c32fd1SAlex Vesker struct mlx5dr_match_misc { 63014c32fd1SAlex Vesker /* used with GRE, checksum exist when gre_c_present == 1 */ 63114c32fd1SAlex Vesker u32 gre_c_present:1; 6327766c9b9SMuhammad Sammar u32 reserved_auto1:1; 6337766c9b9SMuhammad Sammar /* used with GRE, key exist when gre_k_present == 1 */ 6347766c9b9SMuhammad Sammar u32 gre_k_present:1; 6357766c9b9SMuhammad Sammar /* used with GRE, sequence number exist when gre_s_present == 1 */ 6367766c9b9SMuhammad Sammar u32 gre_s_present:1; 6377766c9b9SMuhammad Sammar u32 source_vhca_port:4; 6387766c9b9SMuhammad Sammar u32 source_sqn:24; /* Source SQN */ 6397766c9b9SMuhammad Sammar 6407766c9b9SMuhammad Sammar u32 source_eswitch_owner_vhca_id:16; 64114c32fd1SAlex Vesker /* Source port.;0xffff determines wire port */ 64214c32fd1SAlex Vesker u32 source_port:16; 6437766c9b9SMuhammad Sammar 64414c32fd1SAlex Vesker /* Priority of second VLAN tag in the outer header of the incoming packet. 64514c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 64614c32fd1SAlex Vesker */ 64714c32fd1SAlex Vesker u32 outer_second_prio:3; 6487766c9b9SMuhammad Sammar /* CFI bit of first VLAN tag in the outer header of the incoming packet. 6497766c9b9SMuhammad Sammar * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 65014c32fd1SAlex Vesker */ 6517766c9b9SMuhammad Sammar u32 outer_second_cfi:1; 6527766c9b9SMuhammad Sammar /* VLAN ID of first VLAN tag the outer header of the incoming packet. 6537766c9b9SMuhammad Sammar * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 6547766c9b9SMuhammad Sammar */ 6557766c9b9SMuhammad Sammar u32 outer_second_vid:12; 6567766c9b9SMuhammad Sammar /* Priority of second VLAN tag in the inner header of the incoming packet. 6577766c9b9SMuhammad Sammar * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 6587766c9b9SMuhammad Sammar */ 6597766c9b9SMuhammad Sammar u32 inner_second_prio:3; 6607766c9b9SMuhammad Sammar /* CFI bit of first VLAN tag in the inner header of the incoming packet. 6617766c9b9SMuhammad Sammar * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 6627766c9b9SMuhammad Sammar */ 6637766c9b9SMuhammad Sammar u32 inner_second_cfi:1; 6647766c9b9SMuhammad Sammar /* VLAN ID of first VLAN tag the inner header of the incoming packet. 6657766c9b9SMuhammad Sammar * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 6667766c9b9SMuhammad Sammar */ 6677766c9b9SMuhammad Sammar u32 inner_second_vid:12; 6687766c9b9SMuhammad Sammar 6697766c9b9SMuhammad Sammar u32 outer_second_cvlan_tag:1; 6707766c9b9SMuhammad Sammar u32 inner_second_cvlan_tag:1; 6717766c9b9SMuhammad Sammar /* The second vlan in the outer header of the packet is c-vlan (0x8100). 67214c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 67314c32fd1SAlex Vesker */ 67414c32fd1SAlex Vesker u32 outer_second_svlan_tag:1; 67514c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is c-vlan (0x8100). 67614c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 67714c32fd1SAlex Vesker */ 6787766c9b9SMuhammad Sammar u32 inner_second_svlan_tag:1; 6797766c9b9SMuhammad Sammar /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 68014c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 68114c32fd1SAlex Vesker */ 6827766c9b9SMuhammad Sammar u32 reserved_auto2:12; 6837766c9b9SMuhammad Sammar /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 6847766c9b9SMuhammad Sammar * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 6857766c9b9SMuhammad Sammar */ 6867766c9b9SMuhammad Sammar u32 gre_protocol:16; /* GRE Protocol (outer) */ 6877766c9b9SMuhammad Sammar 68814c32fd1SAlex Vesker u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 6897766c9b9SMuhammad Sammar u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 6907766c9b9SMuhammad Sammar 69114c32fd1SAlex Vesker u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 6927766c9b9SMuhammad Sammar u32 reserved_auto3:8; 6937766c9b9SMuhammad Sammar 69414c32fd1SAlex Vesker u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 695f59464e2SYevgeny Kliteynik u32 reserved_auto4:6; 696f59464e2SYevgeny Kliteynik u32 geneve_tlv_option_0_exist:1; 6977766c9b9SMuhammad Sammar u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 6987766c9b9SMuhammad Sammar 6997766c9b9SMuhammad Sammar u32 reserved_auto5:12; 70014c32fd1SAlex Vesker u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 7017766c9b9SMuhammad Sammar 70214c32fd1SAlex Vesker u32 reserved_auto6:12; 70314c32fd1SAlex Vesker u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 7047766c9b9SMuhammad Sammar 7057766c9b9SMuhammad Sammar u32 reserved_auto7:10; 70614c32fd1SAlex Vesker u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 7077766c9b9SMuhammad Sammar u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 7087766c9b9SMuhammad Sammar 7097766c9b9SMuhammad Sammar u32 reserved_auto8:8; 71014c32fd1SAlex Vesker u32 bth_dst_qp:24; /* Destination QP in BTH header */ 7117766c9b9SMuhammad Sammar 7127766c9b9SMuhammad Sammar u32 reserved_auto9; 7137766c9b9SMuhammad Sammar u32 outer_esp_spi; 7147766c9b9SMuhammad Sammar u32 reserved_auto10[3]; 71514c32fd1SAlex Vesker }; 71614c32fd1SAlex Vesker 71714c32fd1SAlex Vesker struct mlx5dr_match_misc2 { 71814c32fd1SAlex Vesker u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 7197766c9b9SMuhammad Sammar u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 7207766c9b9SMuhammad Sammar u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 7217766c9b9SMuhammad Sammar u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 7227766c9b9SMuhammad Sammar 72314c32fd1SAlex Vesker u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 7247766c9b9SMuhammad Sammar u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 7257766c9b9SMuhammad Sammar u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 7267766c9b9SMuhammad Sammar u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 7277766c9b9SMuhammad Sammar 72814c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 7297766c9b9SMuhammad Sammar u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 7307766c9b9SMuhammad Sammar u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 7317766c9b9SMuhammad Sammar u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 7327766c9b9SMuhammad Sammar 73314c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 7347766c9b9SMuhammad Sammar u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 7357766c9b9SMuhammad Sammar u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 7367766c9b9SMuhammad Sammar u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 7377766c9b9SMuhammad Sammar 73814c32fd1SAlex Vesker u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 73914c32fd1SAlex Vesker u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 74014c32fd1SAlex Vesker u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 74114c32fd1SAlex Vesker u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 74214c32fd1SAlex Vesker u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 74314c32fd1SAlex Vesker u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 74414c32fd1SAlex Vesker u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 74514c32fd1SAlex Vesker u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 74614c32fd1SAlex Vesker u32 metadata_reg_a; /* metadata_reg_a */ 7477766c9b9SMuhammad Sammar u32 reserved_auto1[3]; 74814c32fd1SAlex Vesker }; 74914c32fd1SAlex Vesker 75014c32fd1SAlex Vesker struct mlx5dr_match_misc3 { 75114c32fd1SAlex Vesker u32 inner_tcp_seq_num; 75214c32fd1SAlex Vesker u32 outer_tcp_seq_num; 75314c32fd1SAlex Vesker u32 inner_tcp_ack_num; 75414c32fd1SAlex Vesker u32 outer_tcp_ack_num; 7557766c9b9SMuhammad Sammar 75614c32fd1SAlex Vesker u32 reserved_auto1:8; 7577766c9b9SMuhammad Sammar u32 outer_vxlan_gpe_vni:24; 7587766c9b9SMuhammad Sammar 75914c32fd1SAlex Vesker u32 outer_vxlan_gpe_next_protocol:8; 7607766c9b9SMuhammad Sammar u32 outer_vxlan_gpe_flags:8; 7617766c9b9SMuhammad Sammar u32 reserved_auto2:16; 7627766c9b9SMuhammad Sammar 76314c32fd1SAlex Vesker u32 icmpv4_header_data; 76414c32fd1SAlex Vesker u32 icmpv6_header_data; 7657766c9b9SMuhammad Sammar 76640ca842cSYevgeny Kliteynik u8 icmpv4_type; 7677766c9b9SMuhammad Sammar u8 icmpv4_code; 7687766c9b9SMuhammad Sammar u8 icmpv6_type; 7697766c9b9SMuhammad Sammar u8 icmpv6_code; 7707766c9b9SMuhammad Sammar 7713442e033SYevgeny Kliteynik u32 geneve_tlv_option_0_data; 7727766c9b9SMuhammad Sammar 773df9dd15aSYevgeny Kliteynik u32 gtpu_teid; 7747766c9b9SMuhammad Sammar 7757766c9b9SMuhammad Sammar u8 gtpu_msg_type; 7767766c9b9SMuhammad Sammar u8 gtpu_msg_flags; 7777766c9b9SMuhammad Sammar u32 reserved_auto3:16; 7787766c9b9SMuhammad Sammar 779df9dd15aSYevgeny Kliteynik u32 gtpu_dw_2; 780df9dd15aSYevgeny Kliteynik u32 gtpu_first_ext_dw_0; 781df9dd15aSYevgeny Kliteynik u32 gtpu_dw_0; 7827766c9b9SMuhammad Sammar u32 reserved_auto4; 78314c32fd1SAlex Vesker }; 78414c32fd1SAlex Vesker 785160e9cb3SYevgeny Kliteynik struct mlx5dr_match_misc4 { 786160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_0; 787160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_0; 788160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_1; 789160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_1; 790160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_2; 791160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_2; 792160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_3; 793160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_3; 7947766c9b9SMuhammad Sammar u32 reserved_auto1[8]; 795160e9cb3SYevgeny Kliteynik }; 796160e9cb3SYevgeny Kliteynik 7978c2b4feeSMuhammad Sammar struct mlx5dr_match_misc5 { 7988c2b4feeSMuhammad Sammar u32 macsec_tag_0; 7998c2b4feeSMuhammad Sammar u32 macsec_tag_1; 8008c2b4feeSMuhammad Sammar u32 macsec_tag_2; 8018c2b4feeSMuhammad Sammar u32 macsec_tag_3; 8028c2b4feeSMuhammad Sammar u32 tunnel_header_0; 8038c2b4feeSMuhammad Sammar u32 tunnel_header_1; 8048c2b4feeSMuhammad Sammar u32 tunnel_header_2; 8058c2b4feeSMuhammad Sammar u32 tunnel_header_3; 8068c2b4feeSMuhammad Sammar }; 8078c2b4feeSMuhammad Sammar 80814c32fd1SAlex Vesker struct mlx5dr_match_param { 80914c32fd1SAlex Vesker struct mlx5dr_match_spec outer; 81014c32fd1SAlex Vesker struct mlx5dr_match_misc misc; 81114c32fd1SAlex Vesker struct mlx5dr_match_spec inner; 81214c32fd1SAlex Vesker struct mlx5dr_match_misc2 misc2; 81314c32fd1SAlex Vesker struct mlx5dr_match_misc3 misc3; 814160e9cb3SYevgeny Kliteynik struct mlx5dr_match_misc4 misc4; 8158c2b4feeSMuhammad Sammar struct mlx5dr_match_misc5 misc5; 81614c32fd1SAlex Vesker }; 81714c32fd1SAlex Vesker 818de1facafSYevgeny Kliteynik #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 81914c32fd1SAlex Vesker (_misc3)->icmpv4_code || \ 82014c32fd1SAlex Vesker (_misc3)->icmpv4_header_data) 82114c32fd1SAlex Vesker 822ffb0753bSYevgeny Kliteynik #define DR_MASK_IS_SRC_IP_SET(_spec) ((_spec)->src_ip_127_96 || \ 823ffb0753bSYevgeny Kliteynik (_spec)->src_ip_95_64 || \ 824ffb0753bSYevgeny Kliteynik (_spec)->src_ip_63_32 || \ 825ffb0753bSYevgeny Kliteynik (_spec)->src_ip_31_0) 826ffb0753bSYevgeny Kliteynik 827ffb0753bSYevgeny Kliteynik #define DR_MASK_IS_DST_IP_SET(_spec) ((_spec)->dst_ip_127_96 || \ 828ffb0753bSYevgeny Kliteynik (_spec)->dst_ip_95_64 || \ 829ffb0753bSYevgeny Kliteynik (_spec)->dst_ip_63_32 || \ 830ffb0753bSYevgeny Kliteynik (_spec)->dst_ip_31_0) 831ffb0753bSYevgeny Kliteynik 83214c32fd1SAlex Vesker struct mlx5dr_esw_caps { 83314c32fd1SAlex Vesker u64 drop_icm_address_rx; 83414c32fd1SAlex Vesker u64 drop_icm_address_tx; 83514c32fd1SAlex Vesker u64 uplink_icm_address_rx; 83614c32fd1SAlex Vesker u64 uplink_icm_address_tx; 83764f45c0fSYevgeny Kliteynik u8 sw_owner:1; 83864f45c0fSYevgeny Kliteynik u8 sw_owner_v2:1; 83914c32fd1SAlex Vesker }; 84014c32fd1SAlex Vesker 84114c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap { 84214c32fd1SAlex Vesker u16 vport_gvmi; 84314c32fd1SAlex Vesker u16 vhca_gvmi; 844f9f93bd5SYevgeny Kliteynik u16 num; 84514c32fd1SAlex Vesker u64 icm_address_rx; 84614c32fd1SAlex Vesker u64 icm_address_tx; 84714c32fd1SAlex Vesker }; 84814c32fd1SAlex Vesker 8497304d603SYevgeny Kliteynik struct mlx5dr_roce_cap { 8507304d603SYevgeny Kliteynik u8 roce_en:1; 8517304d603SYevgeny Kliteynik u8 fl_rc_qp_when_roce_disabled:1; 8527304d603SYevgeny Kliteynik u8 fl_rc_qp_when_roce_enabled:1; 8537304d603SYevgeny Kliteynik }; 8547304d603SYevgeny Kliteynik 85511a45defSYevgeny Kliteynik struct mlx5dr_vports { 85611a45defSYevgeny Kliteynik struct mlx5dr_cmd_vport_cap esw_manager_caps; 8579091b821SYevgeny Kliteynik struct mlx5dr_cmd_vport_cap uplink_caps; 85811a45defSYevgeny Kliteynik struct xarray vports_caps_xa; 85911a45defSYevgeny Kliteynik }; 86011a45defSYevgeny Kliteynik 86114c32fd1SAlex Vesker struct mlx5dr_cmd_caps { 86214c32fd1SAlex Vesker u16 gvmi; 86314c32fd1SAlex Vesker u64 nic_rx_drop_address; 86414c32fd1SAlex Vesker u64 nic_tx_drop_address; 86514c32fd1SAlex Vesker u64 nic_tx_allow_address; 86614c32fd1SAlex Vesker u64 esw_rx_drop_address; 86714c32fd1SAlex Vesker u64 esw_tx_drop_address; 86814c32fd1SAlex Vesker u32 log_icm_size; 86914c32fd1SAlex Vesker u64 hdr_modify_icm_addr; 870108ff821SYevgeny Kliteynik u32 log_modify_pattern_icm_size; 871108ff821SYevgeny Kliteynik u64 hdr_modify_pattern_icm_addr; 87214c32fd1SAlex Vesker u32 flex_protocols; 87314c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw0; 87414c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw1; 87514c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw0; 87614c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw1; 8773442e033SYevgeny Kliteynik u8 flex_parser_id_geneve_tlv_option_0; 87835ba005dSYevgeny Kliteynik u8 flex_parser_id_mpls_over_gre; 87935ba005dSYevgeny Kliteynik u8 flex_parser_id_mpls_over_udp; 880df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_dw_0; 881df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_teid; 882df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_dw_2; 883df9dd15aSYevgeny Kliteynik u8 flex_parser_id_gtpu_first_ext_dw_0; 884f59464e2SYevgeny Kliteynik u8 flex_parser_ok_bits_supp; 88514c32fd1SAlex Vesker u8 max_ft_level; 88614c32fd1SAlex Vesker u16 roce_min_src_udp; 887d421e466SYevgeny Kliteynik u8 sw_format_ver; 88814c32fd1SAlex Vesker bool eswitch_manager; 88914c32fd1SAlex Vesker bool rx_sw_owner; 89014c32fd1SAlex Vesker bool tx_sw_owner; 89114c32fd1SAlex Vesker bool fdb_sw_owner; 89264f45c0fSYevgeny Kliteynik u8 rx_sw_owner_v2:1; 89364f45c0fSYevgeny Kliteynik u8 tx_sw_owner_v2:1; 89464f45c0fSYevgeny Kliteynik u8 fdb_sw_owner_v2:1; 89514c32fd1SAlex Vesker struct mlx5dr_esw_caps esw_caps; 89611a45defSYevgeny Kliteynik struct mlx5dr_vports vports; 89714c32fd1SAlex Vesker bool prio_tag_required; 8987304d603SYevgeny Kliteynik struct mlx5dr_roce_cap roce_caps; 899b7ba743aSYevgeny Kliteynik u16 log_header_modify_argument_granularity; 900b7ba743aSYevgeny Kliteynik u16 log_header_modify_argument_max_alloc; 901b7ba743aSYevgeny Kliteynik bool support_modify_argument; 902dd4acb2aSYevgeny Kliteynik u8 is_ecpf:1; 903aeacb52aSYevgeny Kliteynik u8 isolate_vl_tc:1; 90414c32fd1SAlex Vesker }; 90514c32fd1SAlex Vesker 90646f2a8aeSYevgeny Kliteynik enum mlx5dr_domain_nic_type { 90746f2a8aeSYevgeny Kliteynik DR_DOMAIN_NIC_TYPE_RX, 90846f2a8aeSYevgeny Kliteynik DR_DOMAIN_NIC_TYPE_TX, 90946f2a8aeSYevgeny Kliteynik }; 91046f2a8aeSYevgeny Kliteynik 91114c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx { 91214c32fd1SAlex Vesker u64 drop_icm_addr; 91314c32fd1SAlex Vesker u64 default_icm_addr; 91446f2a8aeSYevgeny Kliteynik enum mlx5dr_domain_nic_type type; 915ed03a418SAlex Vesker struct mutex mutex; /* protect rx/tx domain */ 91614c32fd1SAlex Vesker }; 91714c32fd1SAlex Vesker 91814c32fd1SAlex Vesker struct mlx5dr_domain_info { 91914c32fd1SAlex Vesker bool supp_sw_steering; 92014c32fd1SAlex Vesker u32 max_inline_size; 92114c32fd1SAlex Vesker u32 max_send_wr; 92214c32fd1SAlex Vesker u32 max_log_sw_icm_sz; 92314c32fd1SAlex Vesker u32 max_log_action_icm_sz; 924108ff821SYevgeny Kliteynik u32 max_log_modify_hdr_pattern_icm_sz; 92514c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx rx; 92614c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx tx; 92714c32fd1SAlex Vesker struct mlx5dr_cmd_caps caps; 92814c32fd1SAlex Vesker }; 92914c32fd1SAlex Vesker 93014c32fd1SAlex Vesker struct mlx5dr_domain { 93114c32fd1SAlex Vesker struct mlx5dr_domain *peer_dmn; 93214c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 93314c32fd1SAlex Vesker u32 pdn; 93414c32fd1SAlex Vesker struct mlx5_uars_page *uar; 93514c32fd1SAlex Vesker enum mlx5dr_domain_type type; 93614c32fd1SAlex Vesker refcount_t refcount; 93714c32fd1SAlex Vesker struct mlx5dr_icm_pool *ste_icm_pool; 93814c32fd1SAlex Vesker struct mlx5dr_icm_pool *action_icm_pool; 93917b56073SYevgeny Kliteynik struct mlx5dr_send_info_pool *send_info_pool_rx; 94017b56073SYevgeny Kliteynik struct mlx5dr_send_info_pool *send_info_pool_tx; 941fd785e52SYevgeny Kliteynik struct kmem_cache *chunks_kmem_cache; 942fb628b71SYevgeny Kliteynik struct kmem_cache *htbls_kmem_cache; 943108ff821SYevgeny Kliteynik struct mlx5dr_ptrn_mgr *ptrn_mgr; 94414c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring; 94514c32fd1SAlex Vesker struct mlx5dr_domain_info info; 946c0e90fc2SYevgeny Kliteynik struct xarray csum_fts_xa; 9475212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *ste_ctx; 9489222f0b2SMuhammad Sammar struct list_head dbg_tbl_list; 9499222f0b2SMuhammad Sammar struct mlx5dr_dbg_dump_info dump_info; 9501339678fSYevgeny Kliteynik struct xarray definers_xa; 95114c32fd1SAlex Vesker }; 95214c32fd1SAlex Vesker 95314c32fd1SAlex Vesker struct mlx5dr_table_rx_tx { 95414c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_anchor; 95514c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn; 95614c32fd1SAlex Vesker u64 default_icm_addr; 957cc2295cdSYevgeny Kliteynik struct list_head nic_matcher_list; 95814c32fd1SAlex Vesker }; 95914c32fd1SAlex Vesker 96014c32fd1SAlex Vesker struct mlx5dr_table { 96114c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 96214c32fd1SAlex Vesker struct mlx5dr_table_rx_tx rx; 96314c32fd1SAlex Vesker struct mlx5dr_table_rx_tx tx; 96414c32fd1SAlex Vesker u32 level; 96514c32fd1SAlex Vesker u32 table_type; 96614c32fd1SAlex Vesker u32 table_id; 967988fd6b3SErez Shitrit u32 flags; 96814c32fd1SAlex Vesker struct list_head matcher_list; 96914c32fd1SAlex Vesker struct mlx5dr_action *miss_action; 97014c32fd1SAlex Vesker refcount_t refcount; 9719222f0b2SMuhammad Sammar struct list_head dbg_node; 97214c32fd1SAlex Vesker }; 97314c32fd1SAlex Vesker 97414c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx { 97514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_htbl; 97614c32fd1SAlex Vesker struct mlx5dr_ste_htbl *e_anchor; 97714c32fd1SAlex Vesker struct mlx5dr_ste_build *ste_builder; 978667f2646SAlex Vesker struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 979667f2646SAlex Vesker [DR_RULE_IPV_MAX] 980667f2646SAlex Vesker [DR_RULE_MAX_STES]; 98114c32fd1SAlex Vesker u8 num_of_builders; 982667f2646SAlex Vesker u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 98314c32fd1SAlex Vesker u64 default_icm_addr; 98414c32fd1SAlex Vesker struct mlx5dr_table_rx_tx *nic_tbl; 985cc2295cdSYevgeny Kliteynik u32 prio; 986cc2295cdSYevgeny Kliteynik struct list_head list_node; 987cc2295cdSYevgeny Kliteynik u32 rules; 98814c32fd1SAlex Vesker }; 98914c32fd1SAlex Vesker 99014c32fd1SAlex Vesker struct mlx5dr_matcher { 99114c32fd1SAlex Vesker struct mlx5dr_table *tbl; 99214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx rx; 99314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx tx; 9949222f0b2SMuhammad Sammar struct list_head list_node; /* Used for both matchers and dbg managing */ 995f6409299SHamdan Igbaria u32 prio; 99614c32fd1SAlex Vesker struct mlx5dr_match_param mask; 99714c32fd1SAlex Vesker u8 match_criteria; 99814c32fd1SAlex Vesker refcount_t refcount; 9999222f0b2SMuhammad Sammar struct list_head dbg_rule_list; 100014c32fd1SAlex Vesker }; 100114c32fd1SAlex Vesker 10024781df92SYevgeny Kliteynik struct mlx5dr_ste_action_modify_field { 10034781df92SYevgeny Kliteynik u16 hw_field; 10044781df92SYevgeny Kliteynik u8 start; 10054781df92SYevgeny Kliteynik u8 end; 10064781df92SYevgeny Kliteynik u8 l3_type; 10074781df92SYevgeny Kliteynik u8 l4_type; 10084781df92SYevgeny Kliteynik }; 10094781df92SYevgeny Kliteynik 1010da5d0027SYevgeny Kliteynik struct mlx5dr_ptrn_obj { 1011da5d0027SYevgeny Kliteynik struct mlx5dr_icm_chunk *chunk; 1012da5d0027SYevgeny Kliteynik u8 *data; 1013da5d0027SYevgeny Kliteynik u16 num_of_actions; 1014da5d0027SYevgeny Kliteynik u32 index; 1015da5d0027SYevgeny Kliteynik refcount_t refcount; 1016da5d0027SYevgeny Kliteynik struct list_head list; 1017da5d0027SYevgeny Kliteynik }; 1018da5d0027SYevgeny Kliteynik 10199dac2966SJianbo Liu struct mlx5dr_action_rewrite { 102014c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 102114c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 102214c32fd1SAlex Vesker u8 *data; 102314c32fd1SAlex Vesker u16 num_of_actions; 102414c32fd1SAlex Vesker u32 index; 102514c32fd1SAlex Vesker u8 allow_rx:1; 102614c32fd1SAlex Vesker u8 allow_tx:1; 102714c32fd1SAlex Vesker u8 modify_ttl:1; 1028da5d0027SYevgeny Kliteynik struct mlx5dr_ptrn_obj *ptrn; 10299dac2966SJianbo Liu }; 10309dac2966SJianbo Liu 10319dac2966SJianbo Liu struct mlx5dr_action_reformat { 103214c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 10337ea9b398SYevgeny Kliteynik u32 id; 10347ea9b398SYevgeny Kliteynik u32 size; 10357ea9b398SYevgeny Kliteynik u8 param_0; 10367ea9b398SYevgeny Kliteynik u8 param_1; 10379dac2966SJianbo Liu }; 10389dac2966SJianbo Liu 10391ab6dc35SYevgeny Kliteynik struct mlx5dr_action_sampler { 10401ab6dc35SYevgeny Kliteynik struct mlx5dr_domain *dmn; 10411ab6dc35SYevgeny Kliteynik u64 rx_icm_addr; 10421ab6dc35SYevgeny Kliteynik u64 tx_icm_addr; 10431ab6dc35SYevgeny Kliteynik u32 sampler_id; 10441ab6dc35SYevgeny Kliteynik }; 10451ab6dc35SYevgeny Kliteynik 10469dac2966SJianbo Liu struct mlx5dr_action_dest_tbl { 104714c32fd1SAlex Vesker u8 is_fw_tbl:1; 104814c32fd1SAlex Vesker union { 104914c32fd1SAlex Vesker struct mlx5dr_table *tbl; 105014c32fd1SAlex Vesker struct { 1051aec292eeSAlex Vesker struct mlx5dr_domain *dmn; 1052aec292eeSAlex Vesker u32 id; 1053b8853c96SAlex Vesker u32 group_id; 1054aec292eeSAlex Vesker enum fs_flow_table_type type; 105514c32fd1SAlex Vesker u64 rx_icm_addr; 105614c32fd1SAlex Vesker u64 tx_icm_addr; 1057b8853c96SAlex Vesker struct mlx5dr_action **ref_actions; 1058b8853c96SAlex Vesker u32 num_of_ref_actions; 105914c32fd1SAlex Vesker } fw_tbl; 106014c32fd1SAlex Vesker }; 10619dac2966SJianbo Liu }; 10629dac2966SJianbo Liu 1063be6d5daeSYevgeny Kliteynik struct mlx5dr_action_range { 1064be6d5daeSYevgeny Kliteynik struct mlx5dr_domain *dmn; 1065be6d5daeSYevgeny Kliteynik struct mlx5dr_action *hit_tbl_action; 1066be6d5daeSYevgeny Kliteynik struct mlx5dr_action *miss_tbl_action; 1067be6d5daeSYevgeny Kliteynik u32 definer_id; 1068be6d5daeSYevgeny Kliteynik u32 min; 1069be6d5daeSYevgeny Kliteynik u32 max; 1070be6d5daeSYevgeny Kliteynik }; 1071be6d5daeSYevgeny Kliteynik 10729dac2966SJianbo Liu struct mlx5dr_action_ctr { 107314c32fd1SAlex Vesker u32 ctr_id; 10745dde00a7SYevgeny Kliteynik u32 offset; 10759dac2966SJianbo Liu }; 10769dac2966SJianbo Liu 10779dac2966SJianbo Liu struct mlx5dr_action_vport { 107814c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 107914c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *caps; 10809dac2966SJianbo Liu }; 10819dac2966SJianbo Liu 10829dac2966SJianbo Liu struct mlx5dr_action_push_vlan { 108314c32fd1SAlex Vesker u32 vlan_hdr; /* tpid_pcp_dei_vid */ 10849dac2966SJianbo Liu }; 10859dac2966SJianbo Liu 10869dac2966SJianbo Liu struct mlx5dr_action_flow_tag { 108714c32fd1SAlex Vesker u32 flow_tag; 108814c32fd1SAlex Vesker }; 10899dac2966SJianbo Liu 10909222f0b2SMuhammad Sammar struct mlx5dr_rule_action_member { 10919222f0b2SMuhammad Sammar struct mlx5dr_action *action; 10929222f0b2SMuhammad Sammar struct list_head list; 10939222f0b2SMuhammad Sammar }; 10949222f0b2SMuhammad Sammar 10958920d92bSYevgeny Kliteynik struct mlx5dr_action_aso_flow_meter { 10968920d92bSYevgeny Kliteynik struct mlx5dr_domain *dmn; 10978920d92bSYevgeny Kliteynik u32 obj_id; 10988920d92bSYevgeny Kliteynik u32 offset; 10998920d92bSYevgeny Kliteynik u8 dest_reg_id; 11008920d92bSYevgeny Kliteynik u8 init_color; 11018920d92bSYevgeny Kliteynik }; 11028920d92bSYevgeny Kliteynik 11039dac2966SJianbo Liu struct mlx5dr_action { 11049dac2966SJianbo Liu enum mlx5dr_action_type action_type; 11059dac2966SJianbo Liu refcount_t refcount; 11069dac2966SJianbo Liu 11079dac2966SJianbo Liu union { 11089dac2966SJianbo Liu void *data; 11099dac2966SJianbo Liu struct mlx5dr_action_rewrite *rewrite; 11109dac2966SJianbo Liu struct mlx5dr_action_reformat *reformat; 11111ab6dc35SYevgeny Kliteynik struct mlx5dr_action_sampler *sampler; 11129dac2966SJianbo Liu struct mlx5dr_action_dest_tbl *dest_tbl; 11139dac2966SJianbo Liu struct mlx5dr_action_ctr *ctr; 11149dac2966SJianbo Liu struct mlx5dr_action_vport *vport; 11159dac2966SJianbo Liu struct mlx5dr_action_push_vlan *push_vlan; 11169dac2966SJianbo Liu struct mlx5dr_action_flow_tag *flow_tag; 11178920d92bSYevgeny Kliteynik struct mlx5dr_action_aso_flow_meter *aso; 1118be6d5daeSYevgeny Kliteynik struct mlx5dr_action_range *range; 11199dac2966SJianbo Liu }; 112014c32fd1SAlex Vesker }; 112114c32fd1SAlex Vesker 112214c32fd1SAlex Vesker enum mlx5dr_connect_type { 112314c32fd1SAlex Vesker CONNECT_HIT = 1, 112414c32fd1SAlex Vesker CONNECT_MISS = 2, 112514c32fd1SAlex Vesker }; 112614c32fd1SAlex Vesker 112714c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info { 112814c32fd1SAlex Vesker enum mlx5dr_connect_type type; 112914c32fd1SAlex Vesker union { 113014c32fd1SAlex Vesker struct mlx5dr_ste_htbl *hit_next_htbl; 113114c32fd1SAlex Vesker u64 miss_icm_addr; 113214c32fd1SAlex Vesker }; 113314c32fd1SAlex Vesker }; 113414c32fd1SAlex Vesker 113514c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx { 113614c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher; 11378a015baeSYevgeny Kliteynik struct mlx5dr_ste *last_rule_ste; 113814c32fd1SAlex Vesker }; 113914c32fd1SAlex Vesker 114014c32fd1SAlex Vesker struct mlx5dr_rule { 114114c32fd1SAlex Vesker struct mlx5dr_matcher *matcher; 114214c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx rx; 114314c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx tx; 114414c32fd1SAlex Vesker struct list_head rule_actions_list; 11459222f0b2SMuhammad Sammar struct list_head dbg_node; 114601723919SHamdan Igbaria u32 flow_source; 114714c32fd1SAlex Vesker }; 114814c32fd1SAlex Vesker 11498a015baeSYevgeny Kliteynik void mlx5dr_rule_set_last_member(struct mlx5dr_rule_rx_tx *nic_rule, 11508a015baeSYevgeny Kliteynik struct mlx5dr_ste *ste, 11518a015baeSYevgeny Kliteynik bool force); 11528a015baeSYevgeny Kliteynik int mlx5dr_rule_get_reverse_rule_members(struct mlx5dr_ste **ste_arr, 11538a015baeSYevgeny Kliteynik struct mlx5dr_ste *curr_ste, 11548a015baeSYevgeny Kliteynik int *num_of_stes); 115514c32fd1SAlex Vesker 115614c32fd1SAlex Vesker struct mlx5dr_icm_chunk { 1157a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem *buddy_mem; 115814c32fd1SAlex Vesker 1159a00cd878SYevgeny Kliteynik /* indicates the index of this chunk in the whole memory, 1160a00cd878SYevgeny Kliteynik * used for deleting the chunk from the buddy 1161a00cd878SYevgeny Kliteynik */ 1162a00cd878SYevgeny Kliteynik unsigned int seg; 1163f51bb517SRongwei Liu enum mlx5dr_icm_chunk_size size; 1164a00cd878SYevgeny Kliteynik 116514c32fd1SAlex Vesker /* Memory optimisation */ 116614c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 116714c32fd1SAlex Vesker u8 *hw_ste_arr; 116814c32fd1SAlex Vesker struct list_head *miss_list; 116914c32fd1SAlex Vesker }; 117014c32fd1SAlex Vesker 1171ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn) 1172ed03a418SAlex Vesker { 1173ed03a418SAlex Vesker mutex_lock(&nic_dmn->mutex); 1174ed03a418SAlex Vesker } 1175ed03a418SAlex Vesker 1176ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn) 1177ed03a418SAlex Vesker { 1178ed03a418SAlex Vesker mutex_unlock(&nic_dmn->mutex); 1179ed03a418SAlex Vesker } 1180ed03a418SAlex Vesker 1181ed03a418SAlex Vesker static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn) 1182ed03a418SAlex Vesker { 1183ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.rx); 1184ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.tx); 1185ed03a418SAlex Vesker } 1186ed03a418SAlex Vesker 1187ed03a418SAlex Vesker static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn) 1188ed03a418SAlex Vesker { 1189ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.tx); 1190ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.rx); 1191ed03a418SAlex Vesker } 1192ed03a418SAlex Vesker 1193cc2295cdSYevgeny Kliteynik int mlx5dr_matcher_add_to_tbl_nic(struct mlx5dr_domain *dmn, 1194cc2295cdSYevgeny Kliteynik struct mlx5dr_matcher_rx_tx *nic_matcher); 1195cc2295cdSYevgeny Kliteynik int mlx5dr_matcher_remove_from_tbl_nic(struct mlx5dr_domain *dmn, 1196cc2295cdSYevgeny Kliteynik struct mlx5dr_matcher_rx_tx *nic_matcher); 1197cc2295cdSYevgeny Kliteynik 119814c32fd1SAlex Vesker int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 119914c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 1200667f2646SAlex Vesker enum mlx5dr_ipv outer_ipv, 1201667f2646SAlex Vesker enum mlx5dr_ipv inner_ipv); 120214c32fd1SAlex Vesker 1203003f4f9aSRongwei Liu u64 mlx5dr_icm_pool_get_chunk_mr_addr(struct mlx5dr_icm_chunk *chunk); 1204003f4f9aSRongwei Liu u32 mlx5dr_icm_pool_get_chunk_rkey(struct mlx5dr_icm_chunk *chunk); 12055c4f9b6eSRongwei Liu u64 mlx5dr_icm_pool_get_chunk_icm_addr(struct mlx5dr_icm_chunk *chunk); 1206f51bb517SRongwei Liu u32 mlx5dr_icm_pool_get_chunk_num_of_entries(struct mlx5dr_icm_chunk *chunk); 1207f51bb517SRongwei Liu u32 mlx5dr_icm_pool_get_chunk_byte_size(struct mlx5dr_icm_chunk *chunk); 12080d7f1595SRongwei Liu u8 *mlx5dr_ste_get_hw_ste(struct mlx5dr_ste *ste); 1209003f4f9aSRongwei Liu 1210fb628b71SYevgeny Kliteynik struct mlx5dr_ste_htbl *mlx5dr_icm_pool_alloc_htbl(struct mlx5dr_icm_pool *pool); 1211fb628b71SYevgeny Kliteynik void mlx5dr_icm_pool_free_htbl(struct mlx5dr_icm_pool *pool, struct mlx5dr_ste_htbl *htbl); 1212fb628b71SYevgeny Kliteynik 1213a00cd878SYevgeny Kliteynik static inline int 1214a00cd878SYevgeny Kliteynik mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type) 1215a00cd878SYevgeny Kliteynik { 1216a00cd878SYevgeny Kliteynik if (icm_type == DR_ICM_TYPE_STE) 1217a00cd878SYevgeny Kliteynik return DR_STE_SIZE; 1218a00cd878SYevgeny Kliteynik 1219a00cd878SYevgeny Kliteynik return DR_MODIFY_ACTION_SIZE; 1220a00cd878SYevgeny Kliteynik } 1221a00cd878SYevgeny Kliteynik 122214c32fd1SAlex Vesker static inline u32 122314c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 122414c32fd1SAlex Vesker { 122514c32fd1SAlex Vesker return 1 << chunk_size; 122614c32fd1SAlex Vesker } 122714c32fd1SAlex Vesker 122814c32fd1SAlex Vesker static inline int 122914c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 123014c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type) 123114c32fd1SAlex Vesker { 123214c32fd1SAlex Vesker int num_of_entries; 123314c32fd1SAlex Vesker int entry_size; 123414c32fd1SAlex Vesker 1235a00cd878SYevgeny Kliteynik entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type); 123614c32fd1SAlex Vesker num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 123714c32fd1SAlex Vesker 123814c32fd1SAlex Vesker return entry_size * num_of_entries; 123914c32fd1SAlex Vesker } 124014c32fd1SAlex Vesker 124132c8e3b2SYevgeny Kliteynik static inline int 124232c8e3b2SYevgeny Kliteynik mlx5dr_ste_htbl_increase_threshold(struct mlx5dr_ste_htbl *htbl) 124332c8e3b2SYevgeny Kliteynik { 124432c8e3b2SYevgeny Kliteynik int num_of_entries = 1245597534bdSRongwei Liu mlx5dr_icm_pool_chunk_size_to_entries(htbl->chunk->size); 124632c8e3b2SYevgeny Kliteynik 124732c8e3b2SYevgeny Kliteynik /* Threshold is 50%, one is added to table of size 1 */ 124832c8e3b2SYevgeny Kliteynik return (num_of_entries + 1) / 2; 124932c8e3b2SYevgeny Kliteynik } 125032c8e3b2SYevgeny Kliteynik 125132c8e3b2SYevgeny Kliteynik static inline bool 125232c8e3b2SYevgeny Kliteynik mlx5dr_ste_htbl_may_grow(struct mlx5dr_ste_htbl *htbl) 125332c8e3b2SYevgeny Kliteynik { 1254597534bdSRongwei Liu if (htbl->chunk->size == DR_CHUNK_SIZE_MAX - 1 || !htbl->byte_mask) 125532c8e3b2SYevgeny Kliteynik return false; 125632c8e3b2SYevgeny Kliteynik 125732c8e3b2SYevgeny Kliteynik return true; 125832c8e3b2SYevgeny Kliteynik } 125932c8e3b2SYevgeny Kliteynik 126011a45defSYevgeny Kliteynik struct mlx5dr_cmd_vport_cap * 126111a45defSYevgeny Kliteynik mlx5dr_domain_get_vport_cap(struct mlx5dr_domain *dmn, u16 vport); 126214c32fd1SAlex Vesker 126314c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details { 126414c32fd1SAlex Vesker u8 status; 126514c32fd1SAlex Vesker u8 level; 126614c32fd1SAlex Vesker u64 sw_owner_icm_root_1; 126714c32fd1SAlex Vesker u64 sw_owner_icm_root_0; 126814c32fd1SAlex Vesker }; 126914c32fd1SAlex Vesker 1270cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr { 1271cc78dbd7SAlex Vesker u32 table_type; 1272b0bb369eSMark Bloch u16 uid; 1273cc78dbd7SAlex Vesker u64 icm_addr_rx; 1274cc78dbd7SAlex Vesker u64 icm_addr_tx; 1275cc78dbd7SAlex Vesker u8 level; 1276cc78dbd7SAlex Vesker bool sw_owner; 1277cc78dbd7SAlex Vesker bool term_tbl; 1278cc78dbd7SAlex Vesker bool decap_en; 1279cc78dbd7SAlex Vesker bool reformat_en; 1280cc78dbd7SAlex Vesker }; 1281cc78dbd7SAlex Vesker 128214c32fd1SAlex Vesker /* internal API functions */ 128314c32fd1SAlex Vesker int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 128414c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps); 128514c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 128614c32fd1SAlex Vesker bool other_vport, u16 vport_number, 128714c32fd1SAlex Vesker u64 *icm_address_rx, 128814c32fd1SAlex Vesker u64 *icm_address_tx); 128914c32fd1SAlex Vesker int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 129014c32fd1SAlex Vesker bool other_vport, u16 vport_number, u16 *gvmi); 129114c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 129214c32fd1SAlex Vesker struct mlx5dr_esw_caps *caps); 12931ab6dc35SYevgeny Kliteynik int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev, 12941ab6dc35SYevgeny Kliteynik u32 sampler_id, 12951ab6dc35SYevgeny Kliteynik u64 *rx_icm_addr, 12961ab6dc35SYevgeny Kliteynik u64 *tx_icm_addr); 129714c32fd1SAlex Vesker int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 129814c32fd1SAlex Vesker int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 129914c32fd1SAlex Vesker u32 table_type, 130014c32fd1SAlex Vesker u32 table_id, 130114c32fd1SAlex Vesker u32 group_id, 130214c32fd1SAlex Vesker u32 modify_header_id, 1303f9f93bd5SYevgeny Kliteynik u16 vport_id); 130414c32fd1SAlex Vesker int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 130514c32fd1SAlex Vesker u32 table_type, 130614c32fd1SAlex Vesker u32 table_id); 130714c32fd1SAlex Vesker int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 130814c32fd1SAlex Vesker u32 table_type, 130914c32fd1SAlex Vesker u8 num_of_actions, 131014c32fd1SAlex Vesker u64 *actions, 131114c32fd1SAlex Vesker u32 *modify_header_id); 131214c32fd1SAlex Vesker int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 131314c32fd1SAlex Vesker u32 modify_header_id); 131414c32fd1SAlex Vesker int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 131514c32fd1SAlex Vesker u32 table_type, 131614c32fd1SAlex Vesker u32 table_id, 131714c32fd1SAlex Vesker u32 *group_id); 131814c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 131914c32fd1SAlex Vesker u32 table_type, 132014c32fd1SAlex Vesker u32 table_id, 132114c32fd1SAlex Vesker u32 group_id); 132214c32fd1SAlex Vesker int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 1323cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr *attr, 132414c32fd1SAlex Vesker u64 *fdb_rx_icm_addr, 132514c32fd1SAlex Vesker u32 *table_id); 132614c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 132714c32fd1SAlex Vesker u32 table_id, 132814c32fd1SAlex Vesker u32 table_type); 132914c32fd1SAlex Vesker int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 133014c32fd1SAlex Vesker enum fs_flow_table_type type, 133114c32fd1SAlex Vesker u32 table_id, 133214c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details *output); 133314c32fd1SAlex Vesker int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 133414c32fd1SAlex Vesker enum mlx5_reformat_ctx_type rt, 13357ea9b398SYevgeny Kliteynik u8 reformat_param_0, 13367ea9b398SYevgeny Kliteynik u8 reformat_param_1, 133714c32fd1SAlex Vesker size_t reformat_size, 133814c32fd1SAlex Vesker void *reformat_data, 133914c32fd1SAlex Vesker u32 *reformat_id); 134014c32fd1SAlex Vesker void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 134114c32fd1SAlex Vesker u32 reformat_id); 1342e046b86eSYevgeny Kliteynik int mlx5dr_cmd_create_definer(struct mlx5_core_dev *mdev, 1343e046b86eSYevgeny Kliteynik u16 format_id, 1344e046b86eSYevgeny Kliteynik u8 *dw_selectors, 1345e046b86eSYevgeny Kliteynik u8 *byte_selectors, 1346e046b86eSYevgeny Kliteynik u8 *match_mask, 1347e046b86eSYevgeny Kliteynik u32 *definer_id); 1348e046b86eSYevgeny Kliteynik void mlx5dr_cmd_destroy_definer(struct mlx5_core_dev *mdev, 1349e046b86eSYevgeny Kliteynik u32 definer_id); 135014c32fd1SAlex Vesker 135114c32fd1SAlex Vesker struct mlx5dr_cmd_gid_attr { 135214c32fd1SAlex Vesker u8 gid[16]; 135314c32fd1SAlex Vesker u8 mac[6]; 135414c32fd1SAlex Vesker u32 roce_ver; 135514c32fd1SAlex Vesker }; 135614c32fd1SAlex Vesker 135714c32fd1SAlex Vesker int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 135814c32fd1SAlex Vesker u16 index, struct mlx5dr_cmd_gid_attr *attr); 135914c32fd1SAlex Vesker 1360de69696bSYevgeny Kliteynik int mlx5dr_cmd_create_modify_header_arg(struct mlx5_core_dev *dev, 1361de69696bSYevgeny Kliteynik u16 log_obj_range, u32 pd, 1362de69696bSYevgeny Kliteynik u32 *obj_id); 1363de69696bSYevgeny Kliteynik void mlx5dr_cmd_destroy_modify_header_arg(struct mlx5_core_dev *dev, 1364de69696bSYevgeny Kliteynik u32 obj_id); 1365de69696bSYevgeny Kliteynik 136614c32fd1SAlex Vesker struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 136714c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type); 136814c32fd1SAlex Vesker void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 136914c32fd1SAlex Vesker 137014c32fd1SAlex Vesker struct mlx5dr_icm_chunk * 137114c32fd1SAlex Vesker mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 137214c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size); 137314c32fd1SAlex Vesker void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 13744fe45e1dSYevgeny Kliteynik 13754fe45e1dSYevgeny Kliteynik void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, 13764fe45e1dSYevgeny Kliteynik u8 *hw_ste_p, u32 ste_size); 137714c32fd1SAlex Vesker int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 137814c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 137914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 138014c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info, 138114c32fd1SAlex Vesker bool update_hw_ste); 13826b93b400SYevgeny Kliteynik void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, 13836b93b400SYevgeny Kliteynik u16 gvmi, 138446f2a8aeSYevgeny Kliteynik enum mlx5dr_domain_nic_type nic_type, 138514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 138614c32fd1SAlex Vesker u8 *formatted_ste, 138714c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info); 138814c32fd1SAlex Vesker void mlx5dr_ste_copy_param(u8 match_criteria, 138914c32fd1SAlex Vesker struct mlx5dr_match_param *set_param, 1390941f1979SMuhammad Sammar struct mlx5dr_match_parameters *mask, 1391941f1979SMuhammad Sammar bool clear); 139214c32fd1SAlex Vesker 139314c32fd1SAlex Vesker struct mlx5dr_qp { 139414c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 139514c32fd1SAlex Vesker struct mlx5_wq_qp wq; 139614c32fd1SAlex Vesker struct mlx5_uars_page *uar; 139714c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 1398f93f4f4fSLeon Romanovsky u32 qpn; 139914c32fd1SAlex Vesker struct { 14004605fc0aSYevgeny Kliteynik unsigned int head; 140114c32fd1SAlex Vesker unsigned int pc; 140214c32fd1SAlex Vesker unsigned int cc; 140314c32fd1SAlex Vesker unsigned int size; 140414c32fd1SAlex Vesker unsigned int *wqe_head; 140514c32fd1SAlex Vesker unsigned int wqe_cnt; 140614c32fd1SAlex Vesker } sq; 140714c32fd1SAlex Vesker struct { 140814c32fd1SAlex Vesker unsigned int pc; 140914c32fd1SAlex Vesker unsigned int cc; 141014c32fd1SAlex Vesker unsigned int size; 141114c32fd1SAlex Vesker unsigned int wqe_cnt; 141214c32fd1SAlex Vesker } rq; 141314c32fd1SAlex Vesker int max_inline_data; 141414c32fd1SAlex Vesker }; 141514c32fd1SAlex Vesker 141614c32fd1SAlex Vesker struct mlx5dr_cq { 141714c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 141814c32fd1SAlex Vesker struct mlx5_cqwq wq; 141914c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 142014c32fd1SAlex Vesker struct mlx5_core_cq mcq; 142114c32fd1SAlex Vesker struct mlx5dr_qp *qp; 142214c32fd1SAlex Vesker }; 142314c32fd1SAlex Vesker 142414c32fd1SAlex Vesker struct mlx5dr_mr { 142514c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 142683fec3f1SAharon Landau u32 mkey; 142714c32fd1SAlex Vesker dma_addr_t dma_addr; 142814c32fd1SAlex Vesker void *addr; 142914c32fd1SAlex Vesker size_t size; 143014c32fd1SAlex Vesker }; 143114c32fd1SAlex Vesker 143214c32fd1SAlex Vesker struct mlx5dr_send_ring { 143314c32fd1SAlex Vesker struct mlx5dr_cq *cq; 143414c32fd1SAlex Vesker struct mlx5dr_qp *qp; 143514c32fd1SAlex Vesker struct mlx5dr_mr *mr; 143614c32fd1SAlex Vesker /* How much wqes are waiting for completion */ 143714c32fd1SAlex Vesker u32 pending_wqe; 143814c32fd1SAlex Vesker /* Signal request per this trash hold value */ 143914c32fd1SAlex Vesker u16 signal_th; 144014c32fd1SAlex Vesker /* Each post_send_size less than max_post_send_size */ 144114c32fd1SAlex Vesker u32 max_post_send_size; 144214c32fd1SAlex Vesker /* manage the send queue */ 144314c32fd1SAlex Vesker u32 tx_head; 144414c32fd1SAlex Vesker void *buf; 144514c32fd1SAlex Vesker u32 buf_size; 1446*7d7c9453SYevgeny Kliteynik u8 *sync_buff; 144714c32fd1SAlex Vesker struct mlx5dr_mr *sync_mr; 1448cedb2819SAlex Vesker spinlock_t lock; /* Protect the data path of the send ring */ 1449d5a84e96SYevgeny Kliteynik bool err_state; /* send_ring is not usable in err state */ 145014c32fd1SAlex Vesker }; 145114c32fd1SAlex Vesker 145214c32fd1SAlex Vesker int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 145314c32fd1SAlex Vesker void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 145414c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring); 145514c32fd1SAlex Vesker int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 145614c32fd1SAlex Vesker int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 145714c32fd1SAlex Vesker struct mlx5dr_ste *ste, 145814c32fd1SAlex Vesker u8 *data, 145914c32fd1SAlex Vesker u16 size, 146014c32fd1SAlex Vesker u16 offset); 146114c32fd1SAlex Vesker int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 146214c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 146314c32fd1SAlex Vesker u8 *formatted_ste, u8 *mask); 146414c32fd1SAlex Vesker int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 146514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 146614c32fd1SAlex Vesker u8 *ste_init_data, 146714c32fd1SAlex Vesker bool update_hw_ste); 146814c32fd1SAlex Vesker int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 146914c32fd1SAlex Vesker struct mlx5dr_action *action); 1470da5d0027SYevgeny Kliteynik int mlx5dr_send_postsend_pattern(struct mlx5dr_domain *dmn, 1471da5d0027SYevgeny Kliteynik struct mlx5dr_icm_chunk *chunk, 1472da5d0027SYevgeny Kliteynik u16 num_of_actions, 1473da5d0027SYevgeny Kliteynik u8 *data); 14744605fc0aSYevgeny Kliteynik int mlx5dr_send_postsend_args(struct mlx5dr_domain *dmn, u64 arg_id, 14754605fc0aSYevgeny Kliteynik u16 num_of_actions, u8 *actions_data); 147614c32fd1SAlex Vesker 147717b56073SYevgeny Kliteynik int mlx5dr_send_info_pool_create(struct mlx5dr_domain *dmn); 147817b56073SYevgeny Kliteynik void mlx5dr_send_info_pool_destroy(struct mlx5dr_domain *dmn); 147917b56073SYevgeny Kliteynik struct mlx5dr_ste_send_info *mlx5dr_send_info_alloc(struct mlx5dr_domain *dmn, 148017b56073SYevgeny Kliteynik enum mlx5dr_domain_nic_type nic_type); 148117b56073SYevgeny Kliteynik void mlx5dr_send_info_free(struct mlx5dr_ste_send_info *ste_send_info); 148217b56073SYevgeny Kliteynik 14836de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info { 14846de03d2dSErez Shitrit u32 id; 14856de03d2dSErez Shitrit u16 vport; 14866de03d2dSErez Shitrit enum fs_flow_table_type type; 14876de03d2dSErez Shitrit }; 14886de03d2dSErez Shitrit 14896de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info { 14906de03d2dSErez Shitrit enum mlx5_flow_destination_type type; 14916de03d2dSErez Shitrit union { 14926de03d2dSErez Shitrit u32 tir_num; 14936de03d2dSErez Shitrit u32 ft_num; 14946de03d2dSErez Shitrit u32 ft_id; 14956de03d2dSErez Shitrit u32 counter_id; 14961ab6dc35SYevgeny Kliteynik u32 sampler_id; 14976de03d2dSErez Shitrit struct { 14986de03d2dSErez Shitrit u16 num; 14996de03d2dSErez Shitrit u16 vhca_id; 15006de03d2dSErez Shitrit u32 reformat_id; 15016de03d2dSErez Shitrit u8 flags; 15026de03d2dSErez Shitrit } vport; 15036de03d2dSErez Shitrit }; 15046de03d2dSErez Shitrit }; 15056de03d2dSErez Shitrit 15066de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info { 15076de03d2dSErez Shitrit u32 dests_size; 15086de03d2dSErez Shitrit u32 index; 15096de03d2dSErez Shitrit struct mlx5_flow_context flow_context; 15106de03d2dSErez Shitrit u32 *val; 15116de03d2dSErez Shitrit struct mlx5_flow_act action; 15126de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 151363b85f49SYevgeny Kliteynik bool ignore_flow_level; 15146de03d2dSErez Shitrit }; 15156de03d2dSErez Shitrit 15166de03d2dSErez Shitrit int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 15176de03d2dSErez Shitrit int opmod, int modify_mask, 15186de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info *ft, 15196de03d2dSErez Shitrit u32 group_id, 15206de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info *fte); 15216de03d2dSErez Shitrit 1522a283ea1bSYevgeny Kliteynik bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps); 1523a283ea1bSYevgeny Kliteynik 152414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft { 152514c32fd1SAlex Vesker u64 rx_icm_addr; 152614c32fd1SAlex Vesker u32 table_id; 152714c32fd1SAlex Vesker u32 group_id; 152814c32fd1SAlex Vesker u32 modify_hdr_id; 152914c32fd1SAlex Vesker }; 153014c32fd1SAlex Vesker 153114c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft * 1532f9f93bd5SYevgeny Kliteynik mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u16 vport_num); 153314c32fd1SAlex Vesker void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 153414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 1535c0e90fc2SYevgeny Kliteynik int mlx5dr_domain_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 1536f9f93bd5SYevgeny Kliteynik u16 vport_num, 153714c32fd1SAlex Vesker u64 *rx_icm_addr); 153834583beeSErez Shitrit int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 153934583beeSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest, 154034583beeSErez Shitrit int num_dest, 154134583beeSErez Shitrit bool reformat_req, 154234583beeSErez Shitrit u32 *tbl_id, 154363b85f49SYevgeny Kliteynik u32 *group_id, 15442c5fc6cdSMaor Dickman bool ignore_flow_level, 15452c5fc6cdSMaor Dickman u32 flow_source); 154634583beeSErez Shitrit void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 154734583beeSErez Shitrit u32 group_id); 15480a8c20e2SYevgeny Kliteynik 15490a8c20e2SYevgeny Kliteynik static inline bool mlx5dr_is_fw_table(struct mlx5_flow_table *ft) 15500a8c20e2SYevgeny Kliteynik { 15510a8c20e2SYevgeny Kliteynik return !ft->fs_dr_table.dr_table; 15520a8c20e2SYevgeny Kliteynik } 15530a8c20e2SYevgeny Kliteynik 1554be6d5daeSYevgeny Kliteynik static inline bool mlx5dr_supp_match_ranges(struct mlx5_core_dev *dev) 1555be6d5daeSYevgeny Kliteynik { 1556be6d5daeSYevgeny Kliteynik return (MLX5_CAP_GEN(dev, steering_format_version) >= 1557be6d5daeSYevgeny Kliteynik MLX5_STEERING_FORMAT_CONNECTX_6DX) && 1558be6d5daeSYevgeny Kliteynik (MLX5_CAP_GEN_64(dev, match_definer_format_supported) & 1559be6d5daeSYevgeny Kliteynik (1ULL << MLX5_IFC_DEFINER_FORMAT_ID_SELECT)); 1560be6d5daeSYevgeny Kliteynik } 1561be6d5daeSYevgeny Kliteynik 1562108ff821SYevgeny Kliteynik bool mlx5dr_domain_is_support_ptrn_arg(struct mlx5dr_domain *dmn); 1563108ff821SYevgeny Kliteynik struct mlx5dr_ptrn_mgr *mlx5dr_ptrn_mgr_create(struct mlx5dr_domain *dmn); 1564108ff821SYevgeny Kliteynik void mlx5dr_ptrn_mgr_destroy(struct mlx5dr_ptrn_mgr *mgr); 1565da5d0027SYevgeny Kliteynik struct mlx5dr_ptrn_obj *mlx5dr_ptrn_cache_get_pattern(struct mlx5dr_ptrn_mgr *mgr, 1566da5d0027SYevgeny Kliteynik u16 num_of_actions, u8 *data); 1567da5d0027SYevgeny Kliteynik void mlx5dr_ptrn_cache_put_pattern(struct mlx5dr_ptrn_mgr *mgr, 1568da5d0027SYevgeny Kliteynik struct mlx5dr_ptrn_obj *pattern); 1569108ff821SYevgeny Kliteynik 157014c32fd1SAlex Vesker #endif /* _DR_TYPES_H_ */ 1571