114c32fd1SAlex Vesker /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 214c32fd1SAlex Vesker /* Copyright (c) 2019, Mellanox Technologies */ 314c32fd1SAlex Vesker 414c32fd1SAlex Vesker #ifndef _DR_TYPES_ 514c32fd1SAlex Vesker #define _DR_TYPES_ 614c32fd1SAlex Vesker 714c32fd1SAlex Vesker #include <linux/mlx5/driver.h> 814c32fd1SAlex Vesker #include <linux/refcount.h> 914c32fd1SAlex Vesker #include "fs_core.h" 1014c32fd1SAlex Vesker #include "wq.h" 1114c32fd1SAlex Vesker #include "lib/mlx5.h" 1214c32fd1SAlex Vesker #include "mlx5_ifc_dr.h" 1314c32fd1SAlex Vesker #include "mlx5dr.h" 1414c32fd1SAlex Vesker 1514c32fd1SAlex Vesker #define DR_RULE_MAX_STES 17 1614c32fd1SAlex Vesker #define DR_ACTION_MAX_STES 5 1714c32fd1SAlex Vesker #define WIRE_PORT 0xFFFF 1814c32fd1SAlex Vesker #define DR_STE_SVLAN 0x1 1914c32fd1SAlex Vesker #define DR_STE_CVLAN 0x2 20699d531fSMuhammad Sammar #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) 2114c32fd1SAlex Vesker 2214c32fd1SAlex Vesker #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 2314c32fd1SAlex Vesker #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 2414c32fd1SAlex Vesker #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 2514c32fd1SAlex Vesker 2614c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size { 2714c32fd1SAlex Vesker DR_CHUNK_SIZE_1, 2814c32fd1SAlex Vesker DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 2914c32fd1SAlex Vesker DR_CHUNK_SIZE_2, 3014c32fd1SAlex Vesker DR_CHUNK_SIZE_4, 3114c32fd1SAlex Vesker DR_CHUNK_SIZE_8, 3214c32fd1SAlex Vesker DR_CHUNK_SIZE_16, 3314c32fd1SAlex Vesker DR_CHUNK_SIZE_32, 3414c32fd1SAlex Vesker DR_CHUNK_SIZE_64, 3514c32fd1SAlex Vesker DR_CHUNK_SIZE_128, 3614c32fd1SAlex Vesker DR_CHUNK_SIZE_256, 3714c32fd1SAlex Vesker DR_CHUNK_SIZE_512, 3814c32fd1SAlex Vesker DR_CHUNK_SIZE_1K, 3914c32fd1SAlex Vesker DR_CHUNK_SIZE_2K, 4014c32fd1SAlex Vesker DR_CHUNK_SIZE_4K, 4114c32fd1SAlex Vesker DR_CHUNK_SIZE_8K, 4214c32fd1SAlex Vesker DR_CHUNK_SIZE_16K, 4314c32fd1SAlex Vesker DR_CHUNK_SIZE_32K, 4414c32fd1SAlex Vesker DR_CHUNK_SIZE_64K, 4514c32fd1SAlex Vesker DR_CHUNK_SIZE_128K, 4614c32fd1SAlex Vesker DR_CHUNK_SIZE_256K, 4714c32fd1SAlex Vesker DR_CHUNK_SIZE_512K, 4814c32fd1SAlex Vesker DR_CHUNK_SIZE_1024K, 4914c32fd1SAlex Vesker DR_CHUNK_SIZE_2048K, 5014c32fd1SAlex Vesker DR_CHUNK_SIZE_MAX, 5114c32fd1SAlex Vesker }; 5214c32fd1SAlex Vesker 5314c32fd1SAlex Vesker enum mlx5dr_icm_type { 5414c32fd1SAlex Vesker DR_ICM_TYPE_STE, 5514c32fd1SAlex Vesker DR_ICM_TYPE_MODIFY_ACTION, 5614c32fd1SAlex Vesker }; 5714c32fd1SAlex Vesker 5814c32fd1SAlex Vesker static inline enum mlx5dr_icm_chunk_size 5914c32fd1SAlex Vesker mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 6014c32fd1SAlex Vesker { 6114c32fd1SAlex Vesker chunk += 2; 6214c32fd1SAlex Vesker if (chunk < DR_CHUNK_SIZE_MAX) 6314c32fd1SAlex Vesker return chunk; 6414c32fd1SAlex Vesker 6514c32fd1SAlex Vesker return DR_CHUNK_SIZE_MAX; 6614c32fd1SAlex Vesker } 6714c32fd1SAlex Vesker 6814c32fd1SAlex Vesker enum { 6914c32fd1SAlex Vesker DR_STE_SIZE = 64, 7014c32fd1SAlex Vesker DR_STE_SIZE_CTRL = 32, 7114c32fd1SAlex Vesker DR_STE_SIZE_TAG = 16, 7214c32fd1SAlex Vesker DR_STE_SIZE_MASK = 16, 7314c32fd1SAlex Vesker }; 7414c32fd1SAlex Vesker 7514c32fd1SAlex Vesker enum { 7614c32fd1SAlex Vesker DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 7714c32fd1SAlex Vesker }; 7814c32fd1SAlex Vesker 7914c32fd1SAlex Vesker enum { 8014c32fd1SAlex Vesker DR_MODIFY_ACTION_SIZE = 8, 8114c32fd1SAlex Vesker }; 8214c32fd1SAlex Vesker 8314c32fd1SAlex Vesker enum mlx5dr_matcher_criteria { 8414c32fd1SAlex Vesker DR_MATCHER_CRITERIA_EMPTY = 0, 8514c32fd1SAlex Vesker DR_MATCHER_CRITERIA_OUTER = 1 << 0, 8614c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC = 1 << 1, 8714c32fd1SAlex Vesker DR_MATCHER_CRITERIA_INNER = 1 << 2, 8814c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 8914c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 9014c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MAX = 1 << 5, 9114c32fd1SAlex Vesker }; 9214c32fd1SAlex Vesker 9314c32fd1SAlex Vesker enum mlx5dr_action_type { 9414c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L2_TO_L2, 9514c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L2, 9614c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L3_TO_L2, 9714c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L3, 9814c32fd1SAlex Vesker DR_ACTION_TYP_DROP, 9914c32fd1SAlex Vesker DR_ACTION_TYP_QP, 10014c32fd1SAlex Vesker DR_ACTION_TYP_FT, 10114c32fd1SAlex Vesker DR_ACTION_TYP_CTR, 10214c32fd1SAlex Vesker DR_ACTION_TYP_TAG, 10314c32fd1SAlex Vesker DR_ACTION_TYP_MODIFY_HDR, 10414c32fd1SAlex Vesker DR_ACTION_TYP_VPORT, 10514c32fd1SAlex Vesker DR_ACTION_TYP_POP_VLAN, 10614c32fd1SAlex Vesker DR_ACTION_TYP_PUSH_VLAN, 10714c32fd1SAlex Vesker DR_ACTION_TYP_MAX, 10814c32fd1SAlex Vesker }; 10914c32fd1SAlex Vesker 110667f2646SAlex Vesker enum mlx5dr_ipv { 111667f2646SAlex Vesker DR_RULE_IPV4, 112667f2646SAlex Vesker DR_RULE_IPV6, 113667f2646SAlex Vesker DR_RULE_IPV_MAX, 114667f2646SAlex Vesker }; 115667f2646SAlex Vesker 11614c32fd1SAlex Vesker struct mlx5dr_icm_pool; 11714c32fd1SAlex Vesker struct mlx5dr_icm_chunk; 118a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem; 11914c32fd1SAlex Vesker struct mlx5dr_ste_htbl; 12014c32fd1SAlex Vesker struct mlx5dr_match_param; 12114c32fd1SAlex Vesker struct mlx5dr_cmd_caps; 12214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx; 1235212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx; 12414c32fd1SAlex Vesker 12514c32fd1SAlex Vesker struct mlx5dr_ste { 12614c32fd1SAlex Vesker u8 *hw_ste; 12714c32fd1SAlex Vesker /* refcount: indicates the num of rules that using this ste */ 1284ce380caSYevgeny Kliteynik u32 refcount; 12914c32fd1SAlex Vesker 13014c32fd1SAlex Vesker /* attached to the miss_list head at each htbl entry */ 13114c32fd1SAlex Vesker struct list_head miss_list_node; 13214c32fd1SAlex Vesker 13314c32fd1SAlex Vesker /* each rule member that uses this ste attached here */ 13414c32fd1SAlex Vesker struct list_head rule_list; 13514c32fd1SAlex Vesker 13614c32fd1SAlex Vesker /* this ste is member of htbl */ 13714c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl; 13814c32fd1SAlex Vesker 13914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl; 14014c32fd1SAlex Vesker 14114c32fd1SAlex Vesker /* this ste is part of a rule, located in ste's chain */ 14214c32fd1SAlex Vesker u8 ste_chain_location; 14314c32fd1SAlex Vesker }; 14414c32fd1SAlex Vesker 14514c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl { 14614c32fd1SAlex Vesker /* total number of valid entries belonging to this hash table. This 14714c32fd1SAlex Vesker * includes the non collision and collision entries 14814c32fd1SAlex Vesker */ 14914c32fd1SAlex Vesker unsigned int num_of_valid_entries; 15014c32fd1SAlex Vesker 15114c32fd1SAlex Vesker /* total number of collisions entries attached to this table */ 15214c32fd1SAlex Vesker unsigned int num_of_collisions; 15314c32fd1SAlex Vesker unsigned int increase_threshold; 15414c32fd1SAlex Vesker u8 may_grow:1; 15514c32fd1SAlex Vesker }; 15614c32fd1SAlex Vesker 15714c32fd1SAlex Vesker struct mlx5dr_ste_htbl { 158dd2d3c8dSYevgeny Kliteynik u16 lu_type; 15914c32fd1SAlex Vesker u16 byte_mask; 1604ce380caSYevgeny Kliteynik u32 refcount; 16114c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 16214c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 16314c32fd1SAlex Vesker u8 *hw_ste_arr; 16414c32fd1SAlex Vesker 16514c32fd1SAlex Vesker struct list_head *miss_list; 16614c32fd1SAlex Vesker 16714c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size; 16814c32fd1SAlex Vesker struct mlx5dr_ste *pointing_ste; 16914c32fd1SAlex Vesker 17014c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl ctrl; 17114c32fd1SAlex Vesker }; 17214c32fd1SAlex Vesker 17314c32fd1SAlex Vesker struct mlx5dr_ste_send_info { 17414c32fd1SAlex Vesker struct mlx5dr_ste *ste; 17514c32fd1SAlex Vesker struct list_head send_list; 17614c32fd1SAlex Vesker u16 size; 17714c32fd1SAlex Vesker u16 offset; 17814c32fd1SAlex Vesker u8 data_cont[DR_STE_SIZE]; 17914c32fd1SAlex Vesker u8 *data; 18014c32fd1SAlex Vesker }; 18114c32fd1SAlex Vesker 18214c32fd1SAlex Vesker void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 18314c32fd1SAlex Vesker u16 offset, u8 *data, 18414c32fd1SAlex Vesker struct mlx5dr_ste_send_info *ste_info, 18514c32fd1SAlex Vesker struct list_head *send_list, 18614c32fd1SAlex Vesker bool copy_data); 18714c32fd1SAlex Vesker 18814c32fd1SAlex Vesker struct mlx5dr_ste_build { 18914c32fd1SAlex Vesker u8 inner:1; 19014c32fd1SAlex Vesker u8 rx:1; 191640bdb1fSAlaa Hleihel u8 vhca_id_valid:1; 192640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn; 19314c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps; 194dd2d3c8dSYevgeny Kliteynik u16 lu_type; 19514c32fd1SAlex Vesker u16 byte_mask; 19614c32fd1SAlex Vesker u8 bit_mask[DR_STE_SIZE_MASK]; 19714c32fd1SAlex Vesker int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 19814c32fd1SAlex Vesker struct mlx5dr_ste_build *sb, 199e6b69bf3SYevgeny Kliteynik u8 *tag); 20014c32fd1SAlex Vesker }; 20114c32fd1SAlex Vesker 20214c32fd1SAlex Vesker struct mlx5dr_ste_htbl * 20314c32fd1SAlex Vesker mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 20414c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size, 205dd2d3c8dSYevgeny Kliteynik u16 lu_type, u16 byte_mask); 20614c32fd1SAlex Vesker 20714c32fd1SAlex Vesker int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 20814c32fd1SAlex Vesker 20914c32fd1SAlex Vesker static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 21014c32fd1SAlex Vesker { 2114ce380caSYevgeny Kliteynik htbl->refcount--; 2124ce380caSYevgeny Kliteynik if (!htbl->refcount) 21314c32fd1SAlex Vesker mlx5dr_ste_htbl_free(htbl); 21414c32fd1SAlex Vesker } 21514c32fd1SAlex Vesker 21614c32fd1SAlex Vesker static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 21714c32fd1SAlex Vesker { 2184ce380caSYevgeny Kliteynik htbl->refcount++; 21914c32fd1SAlex Vesker } 22014c32fd1SAlex Vesker 22114c32fd1SAlex Vesker /* STE utils */ 22214c32fd1SAlex Vesker u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 22314c32fd1SAlex Vesker void mlx5dr_ste_set_miss_addr(u8 *hw_ste, u64 miss_addr); 22414c32fd1SAlex Vesker void mlx5dr_ste_set_hit_addr(u8 *hw_ste, u64 icm_addr, u32 ht_size); 22514c32fd1SAlex Vesker void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 22614c32fd1SAlex Vesker bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 22714c32fd1SAlex Vesker u8 ste_location); 22814c32fd1SAlex Vesker u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 22914c32fd1SAlex Vesker u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 23014c32fd1SAlex Vesker struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 23114c32fd1SAlex Vesker 232*64c78942SYevgeny Kliteynik #define MLX5DR_MAX_VLANS 2 233*64c78942SYevgeny Kliteynik 234*64c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr { 235*64c78942SYevgeny Kliteynik u32 modify_index; 236*64c78942SYevgeny Kliteynik u16 modify_actions; 237*64c78942SYevgeny Kliteynik u32 decap_index; 238*64c78942SYevgeny Kliteynik u16 decap_actions; 239*64c78942SYevgeny Kliteynik u8 decap_with_vlan:1; 240*64c78942SYevgeny Kliteynik u64 final_icm_addr; 241*64c78942SYevgeny Kliteynik u32 flow_tag; 242*64c78942SYevgeny Kliteynik u32 ctr_id; 243*64c78942SYevgeny Kliteynik u16 gvmi; 244*64c78942SYevgeny Kliteynik u16 hit_gvmi; 245*64c78942SYevgeny Kliteynik u32 reformat_id; 246*64c78942SYevgeny Kliteynik u32 reformat_size; 247*64c78942SYevgeny Kliteynik struct { 248*64c78942SYevgeny Kliteynik int count; 249*64c78942SYevgeny Kliteynik u32 headers[MLX5DR_MAX_VLANS]; 250*64c78942SYevgeny Kliteynik } vlans; 251*64c78942SYevgeny Kliteynik }; 252*64c78942SYevgeny Kliteynik 253*64c78942SYevgeny Kliteynik void mlx5dr_ste_set_actions_rx(struct mlx5dr_domain *dmn, 254*64c78942SYevgeny Kliteynik u8 *action_type_set, 255*64c78942SYevgeny Kliteynik u8 *last_ste, 256*64c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 257*64c78942SYevgeny Kliteynik u32 *added_stes); 258*64c78942SYevgeny Kliteynik void mlx5dr_ste_set_actions_tx(struct mlx5dr_domain *dmn, 259*64c78942SYevgeny Kliteynik u8 *action_type_set, 260*64c78942SYevgeny Kliteynik u8 *last_ste, 261*64c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 262*64c78942SYevgeny Kliteynik u32 *added_stes); 263*64c78942SYevgeny Kliteynik 2645212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); 26514c32fd1SAlex Vesker void mlx5dr_ste_free(struct mlx5dr_ste *ste, 26614c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 26714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher); 26814c32fd1SAlex Vesker static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 26914c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 27014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher) 27114c32fd1SAlex Vesker { 2724ce380caSYevgeny Kliteynik ste->refcount--; 2734ce380caSYevgeny Kliteynik if (!ste->refcount) 27414c32fd1SAlex Vesker mlx5dr_ste_free(ste, matcher, nic_matcher); 27514c32fd1SAlex Vesker } 27614c32fd1SAlex Vesker 27714c32fd1SAlex Vesker /* initial as 0, increased only when ste appears in a new rule */ 27814c32fd1SAlex Vesker static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 27914c32fd1SAlex Vesker { 2804ce380caSYevgeny Kliteynik ste->refcount++; 28114c32fd1SAlex Vesker } 28214c32fd1SAlex Vesker 28397ffd895SYevgeny Kliteynik static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste) 28497ffd895SYevgeny Kliteynik { 28597ffd895SYevgeny Kliteynik return !ste->refcount; 28697ffd895SYevgeny Kliteynik } 28797ffd895SYevgeny Kliteynik 28814c32fd1SAlex Vesker void mlx5dr_ste_set_hit_addr_by_next_htbl(u8 *hw_ste, 28914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl); 29014c32fd1SAlex Vesker bool mlx5dr_ste_equal_tag(void *src, void *dst); 29114c32fd1SAlex Vesker int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 29214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 29314c32fd1SAlex Vesker struct mlx5dr_ste *ste, 29414c32fd1SAlex Vesker u8 *cur_hw_ste, 29514c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size log_table_size); 29614c32fd1SAlex Vesker 29714c32fd1SAlex Vesker /* STE build functions */ 29814c32fd1SAlex Vesker int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 29914c32fd1SAlex Vesker u8 match_criteria, 30014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 30114c32fd1SAlex Vesker struct mlx5dr_match_param *value); 30214c32fd1SAlex Vesker int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 30314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 30414c32fd1SAlex Vesker struct mlx5dr_match_param *value, 30514c32fd1SAlex Vesker u8 *ste_arr); 3065212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, 3075212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *builder, 30814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 30914c32fd1SAlex Vesker bool inner, bool rx); 3105212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, 3115212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 31214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 31314c32fd1SAlex Vesker bool inner, bool rx); 3145212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, 3155212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 31614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 31714c32fd1SAlex Vesker bool inner, bool rx); 3185212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, 3195212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 32014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 32114c32fd1SAlex Vesker bool inner, bool rx); 3225212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, 3235212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 32414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 32514c32fd1SAlex Vesker bool inner, bool rx); 3265212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, 3275212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 32814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 32914c32fd1SAlex Vesker bool inner, bool rx); 3305212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, 3315212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 33214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 33314c32fd1SAlex Vesker bool inner, bool rx); 3345212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, 3355212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 33614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 33714c32fd1SAlex Vesker bool inner, bool rx); 3385212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, 3395212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 34014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 34114c32fd1SAlex Vesker bool inner, bool rx); 3425212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, 3435212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 34414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 34514c32fd1SAlex Vesker bool inner, bool rx); 3465212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, 3475212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 34814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 34914c32fd1SAlex Vesker bool inner, bool rx); 3505212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, 3515212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 35214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 35314c32fd1SAlex Vesker bool inner, bool rx); 3545212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, 3555212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 35614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 35714c32fd1SAlex Vesker bool inner, bool rx); 3585212f9c6SYevgeny Kliteynik int mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, 3595212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 36014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 36114c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps, 36214c32fd1SAlex Vesker bool inner, bool rx); 3635212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, 3645212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 36514c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 36614c32fd1SAlex Vesker bool inner, bool rx); 3675212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, 3685212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 369b6d12238SYevgeny Kliteynik struct mlx5dr_match_param *mask, 370b6d12238SYevgeny Kliteynik bool inner, bool rx); 3715212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, 3725212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37314c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37414c32fd1SAlex Vesker bool inner, bool rx); 3755212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, 3765212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37714c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37814c32fd1SAlex Vesker bool inner, bool rx); 3795212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, 3805212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 38114c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 38214c32fd1SAlex Vesker bool inner, bool rx); 3835212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, 3845212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 38514c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 386640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn, 38714c32fd1SAlex Vesker bool inner, bool rx); 38814c32fd1SAlex Vesker void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 38914c32fd1SAlex Vesker 39014c32fd1SAlex Vesker /* Actions utils */ 39114c32fd1SAlex Vesker int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 39214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 39314c32fd1SAlex Vesker struct mlx5dr_action *actions[], 39414c32fd1SAlex Vesker u32 num_actions, 39514c32fd1SAlex Vesker u8 *ste_arr, 39614c32fd1SAlex Vesker u32 *new_hw_ste_arr_sz); 39714c32fd1SAlex Vesker 39814c32fd1SAlex Vesker struct mlx5dr_match_spec { 39914c32fd1SAlex Vesker u32 smac_47_16; /* Source MAC address of incoming packet */ 40014c32fd1SAlex Vesker /* Incoming packet Ethertype - this is the Ethertype 40114c32fd1SAlex Vesker * following the last VLAN tag of the packet 40214c32fd1SAlex Vesker */ 40314c32fd1SAlex Vesker u32 ethertype:16; 40414c32fd1SAlex Vesker u32 smac_15_0:16; /* Source MAC address of incoming packet */ 40514c32fd1SAlex Vesker u32 dmac_47_16; /* Destination MAC address of incoming packet */ 40614c32fd1SAlex Vesker /* VLAN ID of first VLAN tag in the incoming packet. 40714c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 40814c32fd1SAlex Vesker */ 40914c32fd1SAlex Vesker u32 first_vid:12; 41014c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the incoming packet. 41114c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 41214c32fd1SAlex Vesker */ 41314c32fd1SAlex Vesker u32 first_cfi:1; 41414c32fd1SAlex Vesker /* Priority of first VLAN tag in the incoming packet. 41514c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 41614c32fd1SAlex Vesker */ 41714c32fd1SAlex Vesker u32 first_prio:3; 41814c32fd1SAlex Vesker u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 41914c32fd1SAlex Vesker /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 42014c32fd1SAlex Vesker * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 42114c32fd1SAlex Vesker */ 42214c32fd1SAlex Vesker u32 tcp_flags:9; 42314c32fd1SAlex Vesker u32 ip_version:4; /* IP version */ 42414c32fd1SAlex Vesker u32 frag:1; /* Packet is an IP fragment */ 42514c32fd1SAlex Vesker /* The first vlan in the packet is s-vlan (0x8a88). 42614c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 42714c32fd1SAlex Vesker */ 42814c32fd1SAlex Vesker u32 svlan_tag:1; 42914c32fd1SAlex Vesker /* The first vlan in the packet is c-vlan (0x8100). 43014c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 43114c32fd1SAlex Vesker */ 43214c32fd1SAlex Vesker u32 cvlan_tag:1; 43314c32fd1SAlex Vesker /* Explicit Congestion Notification derived from 43414c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 43514c32fd1SAlex Vesker */ 43614c32fd1SAlex Vesker u32 ip_ecn:2; 43714c32fd1SAlex Vesker /* Differentiated Services Code Point derived from 43814c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 43914c32fd1SAlex Vesker */ 44014c32fd1SAlex Vesker u32 ip_dscp:6; 44114c32fd1SAlex Vesker u32 ip_protocol:8; /* IP protocol */ 44214c32fd1SAlex Vesker /* TCP destination port. 44314c32fd1SAlex Vesker * tcp and udp sport/dport are mutually exclusive 44414c32fd1SAlex Vesker */ 44514c32fd1SAlex Vesker u32 tcp_dport:16; 44614c32fd1SAlex Vesker /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 44714c32fd1SAlex Vesker u32 tcp_sport:16; 44814c32fd1SAlex Vesker u32 ttl_hoplimit:8; 44914c32fd1SAlex Vesker u32 reserved:24; 45014c32fd1SAlex Vesker /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 45114c32fd1SAlex Vesker u32 udp_dport:16; 45214c32fd1SAlex Vesker /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 45314c32fd1SAlex Vesker u32 udp_sport:16; 45414c32fd1SAlex Vesker /* IPv6 source address of incoming packets 45514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 45614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 45714c32fd1SAlex Vesker */ 45814c32fd1SAlex Vesker u32 src_ip_127_96; 45914c32fd1SAlex Vesker /* IPv6 source address of incoming packets 46014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 46114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 46214c32fd1SAlex Vesker */ 46314c32fd1SAlex Vesker u32 src_ip_95_64; 46414c32fd1SAlex Vesker /* IPv6 source address of incoming packets 46514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 46614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 46714c32fd1SAlex Vesker */ 46814c32fd1SAlex Vesker u32 src_ip_63_32; 46914c32fd1SAlex Vesker /* IPv6 source address of incoming packets 47014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 47114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 47214c32fd1SAlex Vesker */ 47314c32fd1SAlex Vesker u32 src_ip_31_0; 47414c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 47514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 47614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 47714c32fd1SAlex Vesker */ 47814c32fd1SAlex Vesker u32 dst_ip_127_96; 47914c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 48014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 48114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 48214c32fd1SAlex Vesker */ 48314c32fd1SAlex Vesker u32 dst_ip_95_64; 48414c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 48514c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 48614c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 48714c32fd1SAlex Vesker */ 48814c32fd1SAlex Vesker u32 dst_ip_63_32; 48914c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 49014c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 49114c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 49214c32fd1SAlex Vesker */ 49314c32fd1SAlex Vesker u32 dst_ip_31_0; 49414c32fd1SAlex Vesker }; 49514c32fd1SAlex Vesker 49614c32fd1SAlex Vesker struct mlx5dr_match_misc { 49714c32fd1SAlex Vesker u32 source_sqn:24; /* Source SQN */ 49814c32fd1SAlex Vesker u32 source_vhca_port:4; 49914c32fd1SAlex Vesker /* used with GRE, sequence number exist when gre_s_present == 1 */ 50014c32fd1SAlex Vesker u32 gre_s_present:1; 50114c32fd1SAlex Vesker /* used with GRE, key exist when gre_k_present == 1 */ 50214c32fd1SAlex Vesker u32 gre_k_present:1; 50314c32fd1SAlex Vesker u32 reserved_auto1:1; 50414c32fd1SAlex Vesker /* used with GRE, checksum exist when gre_c_present == 1 */ 50514c32fd1SAlex Vesker u32 gre_c_present:1; 50614c32fd1SAlex Vesker /* Source port.;0xffff determines wire port */ 50714c32fd1SAlex Vesker u32 source_port:16; 508640bdb1fSAlaa Hleihel u32 source_eswitch_owner_vhca_id:16; 50914c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the inner header of the incoming packet. 51014c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 51114c32fd1SAlex Vesker */ 51214c32fd1SAlex Vesker u32 inner_second_vid:12; 51314c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the inner header of the incoming packet. 51414c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 51514c32fd1SAlex Vesker */ 51614c32fd1SAlex Vesker u32 inner_second_cfi:1; 51714c32fd1SAlex Vesker /* Priority of second VLAN tag in the inner header of the incoming packet. 51814c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 51914c32fd1SAlex Vesker */ 52014c32fd1SAlex Vesker u32 inner_second_prio:3; 52114c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the outer header of the incoming packet. 52214c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 52314c32fd1SAlex Vesker */ 52414c32fd1SAlex Vesker u32 outer_second_vid:12; 52514c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the outer header of the incoming packet. 52614c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 52714c32fd1SAlex Vesker */ 52814c32fd1SAlex Vesker u32 outer_second_cfi:1; 52914c32fd1SAlex Vesker /* Priority of second VLAN tag in the outer header of the incoming packet. 53014c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 53114c32fd1SAlex Vesker */ 53214c32fd1SAlex Vesker u32 outer_second_prio:3; 53314c32fd1SAlex Vesker u32 gre_protocol:16; /* GRE Protocol (outer) */ 53414c32fd1SAlex Vesker u32 reserved_auto3:12; 53514c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 53614c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 53714c32fd1SAlex Vesker */ 53814c32fd1SAlex Vesker u32 inner_second_svlan_tag:1; 53914c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 54014c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 54114c32fd1SAlex Vesker */ 54214c32fd1SAlex Vesker u32 outer_second_svlan_tag:1; 54314c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is c-vlan (0x8100). 54414c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 54514c32fd1SAlex Vesker */ 54614c32fd1SAlex Vesker u32 inner_second_cvlan_tag:1; 54714c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is c-vlan (0x8100). 54814c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 54914c32fd1SAlex Vesker */ 55014c32fd1SAlex Vesker u32 outer_second_cvlan_tag:1; 55114c32fd1SAlex Vesker u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 55214c32fd1SAlex Vesker u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 55314c32fd1SAlex Vesker u32 reserved_auto4:8; 55414c32fd1SAlex Vesker u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 55514c32fd1SAlex Vesker u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 55614c32fd1SAlex Vesker u32 reserved_auto5:7; 55714c32fd1SAlex Vesker u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 55814c32fd1SAlex Vesker u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 55914c32fd1SAlex Vesker u32 reserved_auto6:12; 56014c32fd1SAlex Vesker u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 56114c32fd1SAlex Vesker u32 reserved_auto7:12; 56214c32fd1SAlex Vesker u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 56314c32fd1SAlex Vesker u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 56414c32fd1SAlex Vesker u32 reserved_auto8:10; 56514c32fd1SAlex Vesker u32 bth_dst_qp:24; /* Destination QP in BTH header */ 56614c32fd1SAlex Vesker u32 reserved_auto9:8; 56714c32fd1SAlex Vesker u8 reserved_auto10[20]; 56814c32fd1SAlex Vesker }; 56914c32fd1SAlex Vesker 57014c32fd1SAlex Vesker struct mlx5dr_match_misc2 { 57114c32fd1SAlex Vesker u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 57214c32fd1SAlex Vesker u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 57314c32fd1SAlex Vesker u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 57414c32fd1SAlex Vesker u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 57514c32fd1SAlex Vesker u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 57614c32fd1SAlex Vesker u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 57714c32fd1SAlex Vesker u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 57814c32fd1SAlex Vesker u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 57914c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 58014c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 58114c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 58214c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 58314c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 58414c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 58514c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 58614c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 58714c32fd1SAlex Vesker u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 58814c32fd1SAlex Vesker u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 58914c32fd1SAlex Vesker u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 59014c32fd1SAlex Vesker u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 59114c32fd1SAlex Vesker u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 59214c32fd1SAlex Vesker u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 59314c32fd1SAlex Vesker u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 59414c32fd1SAlex Vesker u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 59514c32fd1SAlex Vesker u32 metadata_reg_a; /* metadata_reg_a */ 596356d411cSRaed Salem u8 reserved_auto2[12]; 59714c32fd1SAlex Vesker }; 59814c32fd1SAlex Vesker 59914c32fd1SAlex Vesker struct mlx5dr_match_misc3 { 60014c32fd1SAlex Vesker u32 inner_tcp_seq_num; 60114c32fd1SAlex Vesker u32 outer_tcp_seq_num; 60214c32fd1SAlex Vesker u32 inner_tcp_ack_num; 60314c32fd1SAlex Vesker u32 outer_tcp_ack_num; 60414c32fd1SAlex Vesker u32 outer_vxlan_gpe_vni:24; 60514c32fd1SAlex Vesker u32 reserved_auto1:8; 60614c32fd1SAlex Vesker u32 reserved_auto2:16; 60714c32fd1SAlex Vesker u32 outer_vxlan_gpe_flags:8; 60814c32fd1SAlex Vesker u32 outer_vxlan_gpe_next_protocol:8; 60914c32fd1SAlex Vesker u32 icmpv4_header_data; 61014c32fd1SAlex Vesker u32 icmpv6_header_data; 61140ca842cSYevgeny Kliteynik u8 icmpv6_code; 61240ca842cSYevgeny Kliteynik u8 icmpv6_type; 61340ca842cSYevgeny Kliteynik u8 icmpv4_code; 61440ca842cSYevgeny Kliteynik u8 icmpv4_type; 61514c32fd1SAlex Vesker u8 reserved_auto3[0x1c]; 61614c32fd1SAlex Vesker }; 61714c32fd1SAlex Vesker 61814c32fd1SAlex Vesker struct mlx5dr_match_param { 61914c32fd1SAlex Vesker struct mlx5dr_match_spec outer; 62014c32fd1SAlex Vesker struct mlx5dr_match_misc misc; 62114c32fd1SAlex Vesker struct mlx5dr_match_spec inner; 62214c32fd1SAlex Vesker struct mlx5dr_match_misc2 misc2; 62314c32fd1SAlex Vesker struct mlx5dr_match_misc3 misc3; 62414c32fd1SAlex Vesker }; 62514c32fd1SAlex Vesker 626de1facafSYevgeny Kliteynik #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 62714c32fd1SAlex Vesker (_misc3)->icmpv4_code || \ 62814c32fd1SAlex Vesker (_misc3)->icmpv4_header_data) 62914c32fd1SAlex Vesker 63014c32fd1SAlex Vesker struct mlx5dr_esw_caps { 63114c32fd1SAlex Vesker u64 drop_icm_address_rx; 63214c32fd1SAlex Vesker u64 drop_icm_address_tx; 63314c32fd1SAlex Vesker u64 uplink_icm_address_rx; 63414c32fd1SAlex Vesker u64 uplink_icm_address_tx; 63514c32fd1SAlex Vesker bool sw_owner; 63614c32fd1SAlex Vesker }; 63714c32fd1SAlex Vesker 63814c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap { 63914c32fd1SAlex Vesker u16 vport_gvmi; 64014c32fd1SAlex Vesker u16 vhca_gvmi; 64114c32fd1SAlex Vesker u64 icm_address_rx; 64214c32fd1SAlex Vesker u64 icm_address_tx; 64314c32fd1SAlex Vesker u32 num; 64414c32fd1SAlex Vesker }; 64514c32fd1SAlex Vesker 64614c32fd1SAlex Vesker struct mlx5dr_cmd_caps { 64714c32fd1SAlex Vesker u16 gvmi; 64814c32fd1SAlex Vesker u64 nic_rx_drop_address; 64914c32fd1SAlex Vesker u64 nic_tx_drop_address; 65014c32fd1SAlex Vesker u64 nic_tx_allow_address; 65114c32fd1SAlex Vesker u64 esw_rx_drop_address; 65214c32fd1SAlex Vesker u64 esw_tx_drop_address; 65314c32fd1SAlex Vesker u32 log_icm_size; 65414c32fd1SAlex Vesker u64 hdr_modify_icm_addr; 65514c32fd1SAlex Vesker u32 flex_protocols; 65614c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw0; 65714c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw1; 65814c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw0; 65914c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw1; 66014c32fd1SAlex Vesker u8 max_ft_level; 66114c32fd1SAlex Vesker u16 roce_min_src_udp; 66214c32fd1SAlex Vesker u8 num_esw_ports; 663d421e466SYevgeny Kliteynik u8 sw_format_ver; 66414c32fd1SAlex Vesker bool eswitch_manager; 66514c32fd1SAlex Vesker bool rx_sw_owner; 66614c32fd1SAlex Vesker bool tx_sw_owner; 66714c32fd1SAlex Vesker bool fdb_sw_owner; 66814c32fd1SAlex Vesker u32 num_vports; 66914c32fd1SAlex Vesker struct mlx5dr_esw_caps esw_caps; 67014c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *vports_caps; 67114c32fd1SAlex Vesker bool prio_tag_required; 67214c32fd1SAlex Vesker }; 67314c32fd1SAlex Vesker 67414c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx { 67514c32fd1SAlex Vesker u64 drop_icm_addr; 67614c32fd1SAlex Vesker u64 default_icm_addr; 67714c32fd1SAlex Vesker enum mlx5dr_ste_entry_type ste_type; 678ed03a418SAlex Vesker struct mutex mutex; /* protect rx/tx domain */ 67914c32fd1SAlex Vesker }; 68014c32fd1SAlex Vesker 68114c32fd1SAlex Vesker struct mlx5dr_domain_info { 68214c32fd1SAlex Vesker bool supp_sw_steering; 68314c32fd1SAlex Vesker u32 max_inline_size; 68414c32fd1SAlex Vesker u32 max_send_wr; 68514c32fd1SAlex Vesker u32 max_log_sw_icm_sz; 68614c32fd1SAlex Vesker u32 max_log_action_icm_sz; 68714c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx rx; 68814c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx tx; 68914c32fd1SAlex Vesker struct mlx5dr_cmd_caps caps; 69014c32fd1SAlex Vesker }; 69114c32fd1SAlex Vesker 69214c32fd1SAlex Vesker struct mlx5dr_domain_cache { 69314c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft; 69414c32fd1SAlex Vesker }; 69514c32fd1SAlex Vesker 69614c32fd1SAlex Vesker struct mlx5dr_domain { 69714c32fd1SAlex Vesker struct mlx5dr_domain *peer_dmn; 69814c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 69914c32fd1SAlex Vesker u32 pdn; 70014c32fd1SAlex Vesker struct mlx5_uars_page *uar; 70114c32fd1SAlex Vesker enum mlx5dr_domain_type type; 70214c32fd1SAlex Vesker refcount_t refcount; 70314c32fd1SAlex Vesker struct mlx5dr_icm_pool *ste_icm_pool; 70414c32fd1SAlex Vesker struct mlx5dr_icm_pool *action_icm_pool; 70514c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring; 70614c32fd1SAlex Vesker struct mlx5dr_domain_info info; 70714c32fd1SAlex Vesker struct mlx5dr_domain_cache cache; 7085212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *ste_ctx; 70914c32fd1SAlex Vesker }; 71014c32fd1SAlex Vesker 71114c32fd1SAlex Vesker struct mlx5dr_table_rx_tx { 71214c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_anchor; 71314c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn; 71414c32fd1SAlex Vesker u64 default_icm_addr; 71514c32fd1SAlex Vesker }; 71614c32fd1SAlex Vesker 71714c32fd1SAlex Vesker struct mlx5dr_table { 71814c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 71914c32fd1SAlex Vesker struct mlx5dr_table_rx_tx rx; 72014c32fd1SAlex Vesker struct mlx5dr_table_rx_tx tx; 72114c32fd1SAlex Vesker u32 level; 72214c32fd1SAlex Vesker u32 table_type; 72314c32fd1SAlex Vesker u32 table_id; 724988fd6b3SErez Shitrit u32 flags; 72514c32fd1SAlex Vesker struct list_head matcher_list; 72614c32fd1SAlex Vesker struct mlx5dr_action *miss_action; 72714c32fd1SAlex Vesker refcount_t refcount; 72814c32fd1SAlex Vesker }; 72914c32fd1SAlex Vesker 73014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx { 73114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_htbl; 73214c32fd1SAlex Vesker struct mlx5dr_ste_htbl *e_anchor; 73314c32fd1SAlex Vesker struct mlx5dr_ste_build *ste_builder; 734667f2646SAlex Vesker struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 735667f2646SAlex Vesker [DR_RULE_IPV_MAX] 736667f2646SAlex Vesker [DR_RULE_MAX_STES]; 73714c32fd1SAlex Vesker u8 num_of_builders; 738667f2646SAlex Vesker u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 73914c32fd1SAlex Vesker u64 default_icm_addr; 74014c32fd1SAlex Vesker struct mlx5dr_table_rx_tx *nic_tbl; 74114c32fd1SAlex Vesker }; 74214c32fd1SAlex Vesker 74314c32fd1SAlex Vesker struct mlx5dr_matcher { 74414c32fd1SAlex Vesker struct mlx5dr_table *tbl; 74514c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx rx; 74614c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx tx; 74714c32fd1SAlex Vesker struct list_head matcher_list; 748f6409299SHamdan Igbaria u32 prio; 74914c32fd1SAlex Vesker struct mlx5dr_match_param mask; 75014c32fd1SAlex Vesker u8 match_criteria; 75114c32fd1SAlex Vesker refcount_t refcount; 75214c32fd1SAlex Vesker struct mlx5dv_flow_matcher *dv_matcher; 75314c32fd1SAlex Vesker }; 75414c32fd1SAlex Vesker 75514c32fd1SAlex Vesker struct mlx5dr_rule_member { 75614c32fd1SAlex Vesker struct mlx5dr_ste *ste; 75714c32fd1SAlex Vesker /* attached to mlx5dr_rule via this */ 75814c32fd1SAlex Vesker struct list_head list; 75914c32fd1SAlex Vesker /* attached to mlx5dr_ste via this */ 76014c32fd1SAlex Vesker struct list_head use_ste_list; 76114c32fd1SAlex Vesker }; 76214c32fd1SAlex Vesker 76314c32fd1SAlex Vesker struct mlx5dr_action { 76414c32fd1SAlex Vesker enum mlx5dr_action_type action_type; 76514c32fd1SAlex Vesker refcount_t refcount; 76614c32fd1SAlex Vesker union { 76714c32fd1SAlex Vesker struct { 76814c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 76914c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 77014c32fd1SAlex Vesker u8 *data; 77114c32fd1SAlex Vesker u16 num_of_actions; 77214c32fd1SAlex Vesker u32 index; 77314c32fd1SAlex Vesker u8 allow_rx:1; 77414c32fd1SAlex Vesker u8 allow_tx:1; 77514c32fd1SAlex Vesker u8 modify_ttl:1; 77614c32fd1SAlex Vesker } rewrite; 77714c32fd1SAlex Vesker struct { 77814c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 77914c32fd1SAlex Vesker u32 reformat_id; 78014c32fd1SAlex Vesker u32 reformat_size; 78114c32fd1SAlex Vesker } reformat; 78214c32fd1SAlex Vesker struct { 78314c32fd1SAlex Vesker u8 is_fw_tbl:1; 78414c32fd1SAlex Vesker union { 78514c32fd1SAlex Vesker struct mlx5dr_table *tbl; 78614c32fd1SAlex Vesker struct { 787aec292eeSAlex Vesker struct mlx5dr_domain *dmn; 788aec292eeSAlex Vesker u32 id; 789b8853c96SAlex Vesker u32 group_id; 790aec292eeSAlex Vesker enum fs_flow_table_type type; 79114c32fd1SAlex Vesker u64 rx_icm_addr; 79214c32fd1SAlex Vesker u64 tx_icm_addr; 793b8853c96SAlex Vesker struct mlx5dr_action **ref_actions; 794b8853c96SAlex Vesker u32 num_of_ref_actions; 79514c32fd1SAlex Vesker } fw_tbl; 79614c32fd1SAlex Vesker }; 79714c32fd1SAlex Vesker } dest_tbl; 79814c32fd1SAlex Vesker struct { 79914c32fd1SAlex Vesker u32 ctr_id; 80014c32fd1SAlex Vesker u32 offeset; 80114c32fd1SAlex Vesker } ctr; 80214c32fd1SAlex Vesker struct { 80314c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 80414c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *caps; 80514c32fd1SAlex Vesker } vport; 80614c32fd1SAlex Vesker struct { 80714c32fd1SAlex Vesker u32 vlan_hdr; /* tpid_pcp_dei_vid */ 80814c32fd1SAlex Vesker } push_vlan; 80914c32fd1SAlex Vesker u32 flow_tag; 81014c32fd1SAlex Vesker }; 81114c32fd1SAlex Vesker }; 81214c32fd1SAlex Vesker 81314c32fd1SAlex Vesker enum mlx5dr_connect_type { 81414c32fd1SAlex Vesker CONNECT_HIT = 1, 81514c32fd1SAlex Vesker CONNECT_MISS = 2, 81614c32fd1SAlex Vesker }; 81714c32fd1SAlex Vesker 81814c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info { 81914c32fd1SAlex Vesker enum mlx5dr_connect_type type; 82014c32fd1SAlex Vesker union { 82114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *hit_next_htbl; 82214c32fd1SAlex Vesker u64 miss_icm_addr; 82314c32fd1SAlex Vesker }; 82414c32fd1SAlex Vesker }; 82514c32fd1SAlex Vesker 82614c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx { 82714c32fd1SAlex Vesker struct list_head rule_members_list; 82814c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher; 82914c32fd1SAlex Vesker }; 83014c32fd1SAlex Vesker 83114c32fd1SAlex Vesker struct mlx5dr_rule { 83214c32fd1SAlex Vesker struct mlx5dr_matcher *matcher; 83314c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx rx; 83414c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx tx; 83514c32fd1SAlex Vesker struct list_head rule_actions_list; 83601723919SHamdan Igbaria u32 flow_source; 83714c32fd1SAlex Vesker }; 83814c32fd1SAlex Vesker 83914c32fd1SAlex Vesker void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste, 84014c32fd1SAlex Vesker struct mlx5dr_ste *ste); 84114c32fd1SAlex Vesker 84214c32fd1SAlex Vesker struct mlx5dr_icm_chunk { 843a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem *buddy_mem; 84414c32fd1SAlex Vesker struct list_head chunk_list; 84514c32fd1SAlex Vesker u32 rkey; 84614c32fd1SAlex Vesker u32 num_of_entries; 84714c32fd1SAlex Vesker u32 byte_size; 84814c32fd1SAlex Vesker u64 icm_addr; 84914c32fd1SAlex Vesker u64 mr_addr; 85014c32fd1SAlex Vesker 851a00cd878SYevgeny Kliteynik /* indicates the index of this chunk in the whole memory, 852a00cd878SYevgeny Kliteynik * used for deleting the chunk from the buddy 853a00cd878SYevgeny Kliteynik */ 854a00cd878SYevgeny Kliteynik unsigned int seg; 855a00cd878SYevgeny Kliteynik 85614c32fd1SAlex Vesker /* Memory optimisation */ 85714c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 85814c32fd1SAlex Vesker u8 *hw_ste_arr; 85914c32fd1SAlex Vesker struct list_head *miss_list; 86014c32fd1SAlex Vesker }; 86114c32fd1SAlex Vesker 862ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn) 863ed03a418SAlex Vesker { 864ed03a418SAlex Vesker mutex_lock(&nic_dmn->mutex); 865ed03a418SAlex Vesker } 866ed03a418SAlex Vesker 867ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn) 868ed03a418SAlex Vesker { 869ed03a418SAlex Vesker mutex_unlock(&nic_dmn->mutex); 870ed03a418SAlex Vesker } 871ed03a418SAlex Vesker 872ed03a418SAlex Vesker static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn) 873ed03a418SAlex Vesker { 874ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.rx); 875ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.tx); 876ed03a418SAlex Vesker } 877ed03a418SAlex Vesker 878ed03a418SAlex Vesker static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn) 879ed03a418SAlex Vesker { 880ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.tx); 881ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.rx); 882ed03a418SAlex Vesker } 883ed03a418SAlex Vesker 88414c32fd1SAlex Vesker int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 88514c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 886667f2646SAlex Vesker enum mlx5dr_ipv outer_ipv, 887667f2646SAlex Vesker enum mlx5dr_ipv inner_ipv); 88814c32fd1SAlex Vesker 889a00cd878SYevgeny Kliteynik static inline int 890a00cd878SYevgeny Kliteynik mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type) 891a00cd878SYevgeny Kliteynik { 892a00cd878SYevgeny Kliteynik if (icm_type == DR_ICM_TYPE_STE) 893a00cd878SYevgeny Kliteynik return DR_STE_SIZE; 894a00cd878SYevgeny Kliteynik 895a00cd878SYevgeny Kliteynik return DR_MODIFY_ACTION_SIZE; 896a00cd878SYevgeny Kliteynik } 897a00cd878SYevgeny Kliteynik 89814c32fd1SAlex Vesker static inline u32 89914c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 90014c32fd1SAlex Vesker { 90114c32fd1SAlex Vesker return 1 << chunk_size; 90214c32fd1SAlex Vesker } 90314c32fd1SAlex Vesker 90414c32fd1SAlex Vesker static inline int 90514c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 90614c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type) 90714c32fd1SAlex Vesker { 90814c32fd1SAlex Vesker int num_of_entries; 90914c32fd1SAlex Vesker int entry_size; 91014c32fd1SAlex Vesker 911a00cd878SYevgeny Kliteynik entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type); 91214c32fd1SAlex Vesker num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 91314c32fd1SAlex Vesker 91414c32fd1SAlex Vesker return entry_size * num_of_entries; 91514c32fd1SAlex Vesker } 91614c32fd1SAlex Vesker 91714c32fd1SAlex Vesker static inline struct mlx5dr_cmd_vport_cap * 91814c32fd1SAlex Vesker mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport) 91914c32fd1SAlex Vesker { 92014c32fd1SAlex Vesker if (!caps->vports_caps || 92114c32fd1SAlex Vesker (vport >= caps->num_vports && vport != WIRE_PORT)) 92214c32fd1SAlex Vesker return NULL; 92314c32fd1SAlex Vesker 92414c32fd1SAlex Vesker if (vport == WIRE_PORT) 92514c32fd1SAlex Vesker vport = caps->num_vports; 92614c32fd1SAlex Vesker 92714c32fd1SAlex Vesker return &caps->vports_caps[vport]; 92814c32fd1SAlex Vesker } 92914c32fd1SAlex Vesker 93014c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details { 93114c32fd1SAlex Vesker u8 status; 93214c32fd1SAlex Vesker u8 level; 93314c32fd1SAlex Vesker u64 sw_owner_icm_root_1; 93414c32fd1SAlex Vesker u64 sw_owner_icm_root_0; 93514c32fd1SAlex Vesker }; 93614c32fd1SAlex Vesker 937cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr { 938cc78dbd7SAlex Vesker u32 table_type; 939cc78dbd7SAlex Vesker u64 icm_addr_rx; 940cc78dbd7SAlex Vesker u64 icm_addr_tx; 941cc78dbd7SAlex Vesker u8 level; 942cc78dbd7SAlex Vesker bool sw_owner; 943cc78dbd7SAlex Vesker bool term_tbl; 944cc78dbd7SAlex Vesker bool decap_en; 945cc78dbd7SAlex Vesker bool reformat_en; 946cc78dbd7SAlex Vesker }; 947cc78dbd7SAlex Vesker 94814c32fd1SAlex Vesker /* internal API functions */ 94914c32fd1SAlex Vesker int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 95014c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps); 95114c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 95214c32fd1SAlex Vesker bool other_vport, u16 vport_number, 95314c32fd1SAlex Vesker u64 *icm_address_rx, 95414c32fd1SAlex Vesker u64 *icm_address_tx); 95514c32fd1SAlex Vesker int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 95614c32fd1SAlex Vesker bool other_vport, u16 vport_number, u16 *gvmi); 95714c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 95814c32fd1SAlex Vesker struct mlx5dr_esw_caps *caps); 95914c32fd1SAlex Vesker int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 96014c32fd1SAlex Vesker int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 96114c32fd1SAlex Vesker u32 table_type, 96214c32fd1SAlex Vesker u32 table_id, 96314c32fd1SAlex Vesker u32 group_id, 96414c32fd1SAlex Vesker u32 modify_header_id, 96514c32fd1SAlex Vesker u32 vport_id); 96614c32fd1SAlex Vesker int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 96714c32fd1SAlex Vesker u32 table_type, 96814c32fd1SAlex Vesker u32 table_id); 96914c32fd1SAlex Vesker int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 97014c32fd1SAlex Vesker u32 table_type, 97114c32fd1SAlex Vesker u8 num_of_actions, 97214c32fd1SAlex Vesker u64 *actions, 97314c32fd1SAlex Vesker u32 *modify_header_id); 97414c32fd1SAlex Vesker int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 97514c32fd1SAlex Vesker u32 modify_header_id); 97614c32fd1SAlex Vesker int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 97714c32fd1SAlex Vesker u32 table_type, 97814c32fd1SAlex Vesker u32 table_id, 97914c32fd1SAlex Vesker u32 *group_id); 98014c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 98114c32fd1SAlex Vesker u32 table_type, 98214c32fd1SAlex Vesker u32 table_id, 98314c32fd1SAlex Vesker u32 group_id); 98414c32fd1SAlex Vesker int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 985cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr *attr, 98614c32fd1SAlex Vesker u64 *fdb_rx_icm_addr, 98714c32fd1SAlex Vesker u32 *table_id); 98814c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 98914c32fd1SAlex Vesker u32 table_id, 99014c32fd1SAlex Vesker u32 table_type); 99114c32fd1SAlex Vesker int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 99214c32fd1SAlex Vesker enum fs_flow_table_type type, 99314c32fd1SAlex Vesker u32 table_id, 99414c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details *output); 99514c32fd1SAlex Vesker int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 99614c32fd1SAlex Vesker enum mlx5_reformat_ctx_type rt, 99714c32fd1SAlex Vesker size_t reformat_size, 99814c32fd1SAlex Vesker void *reformat_data, 99914c32fd1SAlex Vesker u32 *reformat_id); 100014c32fd1SAlex Vesker void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 100114c32fd1SAlex Vesker u32 reformat_id); 100214c32fd1SAlex Vesker 100314c32fd1SAlex Vesker struct mlx5dr_cmd_gid_attr { 100414c32fd1SAlex Vesker u8 gid[16]; 100514c32fd1SAlex Vesker u8 mac[6]; 100614c32fd1SAlex Vesker u32 roce_ver; 100714c32fd1SAlex Vesker }; 100814c32fd1SAlex Vesker 100914c32fd1SAlex Vesker struct mlx5dr_cmd_qp_create_attr { 101014c32fd1SAlex Vesker u32 page_id; 101114c32fd1SAlex Vesker u32 pdn; 101214c32fd1SAlex Vesker u32 cqn; 101314c32fd1SAlex Vesker u32 pm_state; 101414c32fd1SAlex Vesker u32 service_type; 101514c32fd1SAlex Vesker u32 buff_umem_id; 101614c32fd1SAlex Vesker u32 db_umem_id; 101714c32fd1SAlex Vesker u32 sq_wqe_cnt; 101814c32fd1SAlex Vesker u32 rq_wqe_cnt; 101914c32fd1SAlex Vesker u32 rq_wqe_shift; 102014c32fd1SAlex Vesker }; 102114c32fd1SAlex Vesker 102214c32fd1SAlex Vesker int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 102314c32fd1SAlex Vesker u16 index, struct mlx5dr_cmd_gid_attr *attr); 102414c32fd1SAlex Vesker 102514c32fd1SAlex Vesker struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 102614c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type); 102714c32fd1SAlex Vesker void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 102814c32fd1SAlex Vesker 102914c32fd1SAlex Vesker struct mlx5dr_icm_chunk * 103014c32fd1SAlex Vesker mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 103114c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size); 103214c32fd1SAlex Vesker void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 103314c32fd1SAlex Vesker int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 103414c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 103514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 103614c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info, 103714c32fd1SAlex Vesker bool update_hw_ste); 103814c32fd1SAlex Vesker void mlx5dr_ste_set_formatted_ste(u16 gvmi, 103914c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 104014c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 104114c32fd1SAlex Vesker u8 *formatted_ste, 104214c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info); 104314c32fd1SAlex Vesker void mlx5dr_ste_copy_param(u8 match_criteria, 104414c32fd1SAlex Vesker struct mlx5dr_match_param *set_param, 104514c32fd1SAlex Vesker struct mlx5dr_match_parameters *mask); 104614c32fd1SAlex Vesker 104714c32fd1SAlex Vesker struct mlx5dr_qp { 104814c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 104914c32fd1SAlex Vesker struct mlx5_wq_qp wq; 105014c32fd1SAlex Vesker struct mlx5_uars_page *uar; 105114c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 1052f93f4f4fSLeon Romanovsky u32 qpn; 105314c32fd1SAlex Vesker struct { 105414c32fd1SAlex Vesker unsigned int pc; 105514c32fd1SAlex Vesker unsigned int cc; 105614c32fd1SAlex Vesker unsigned int size; 105714c32fd1SAlex Vesker unsigned int *wqe_head; 105814c32fd1SAlex Vesker unsigned int wqe_cnt; 105914c32fd1SAlex Vesker } sq; 106014c32fd1SAlex Vesker struct { 106114c32fd1SAlex Vesker unsigned int pc; 106214c32fd1SAlex Vesker unsigned int cc; 106314c32fd1SAlex Vesker unsigned int size; 106414c32fd1SAlex Vesker unsigned int wqe_cnt; 106514c32fd1SAlex Vesker } rq; 106614c32fd1SAlex Vesker int max_inline_data; 106714c32fd1SAlex Vesker }; 106814c32fd1SAlex Vesker 106914c32fd1SAlex Vesker struct mlx5dr_cq { 107014c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 107114c32fd1SAlex Vesker struct mlx5_cqwq wq; 107214c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 107314c32fd1SAlex Vesker struct mlx5_core_cq mcq; 107414c32fd1SAlex Vesker struct mlx5dr_qp *qp; 107514c32fd1SAlex Vesker }; 107614c32fd1SAlex Vesker 107714c32fd1SAlex Vesker struct mlx5dr_mr { 107814c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 107914c32fd1SAlex Vesker struct mlx5_core_mkey mkey; 108014c32fd1SAlex Vesker dma_addr_t dma_addr; 108114c32fd1SAlex Vesker void *addr; 108214c32fd1SAlex Vesker size_t size; 108314c32fd1SAlex Vesker }; 108414c32fd1SAlex Vesker 108514c32fd1SAlex Vesker #define MAX_SEND_CQE 64 108614c32fd1SAlex Vesker #define MIN_READ_SYNC 64 108714c32fd1SAlex Vesker 108814c32fd1SAlex Vesker struct mlx5dr_send_ring { 108914c32fd1SAlex Vesker struct mlx5dr_cq *cq; 109014c32fd1SAlex Vesker struct mlx5dr_qp *qp; 109114c32fd1SAlex Vesker struct mlx5dr_mr *mr; 109214c32fd1SAlex Vesker /* How much wqes are waiting for completion */ 109314c32fd1SAlex Vesker u32 pending_wqe; 109414c32fd1SAlex Vesker /* Signal request per this trash hold value */ 109514c32fd1SAlex Vesker u16 signal_th; 109614c32fd1SAlex Vesker /* Each post_send_size less than max_post_send_size */ 109714c32fd1SAlex Vesker u32 max_post_send_size; 109814c32fd1SAlex Vesker /* manage the send queue */ 109914c32fd1SAlex Vesker u32 tx_head; 110014c32fd1SAlex Vesker void *buf; 110114c32fd1SAlex Vesker u32 buf_size; 110214c32fd1SAlex Vesker struct ib_wc wc[MAX_SEND_CQE]; 110314c32fd1SAlex Vesker u8 sync_buff[MIN_READ_SYNC]; 110414c32fd1SAlex Vesker struct mlx5dr_mr *sync_mr; 1105cedb2819SAlex Vesker spinlock_t lock; /* Protect the data path of the send ring */ 110614c32fd1SAlex Vesker }; 110714c32fd1SAlex Vesker 110814c32fd1SAlex Vesker int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 110914c32fd1SAlex Vesker void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 111014c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring); 111114c32fd1SAlex Vesker int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 111214c32fd1SAlex Vesker int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 111314c32fd1SAlex Vesker struct mlx5dr_ste *ste, 111414c32fd1SAlex Vesker u8 *data, 111514c32fd1SAlex Vesker u16 size, 111614c32fd1SAlex Vesker u16 offset); 111714c32fd1SAlex Vesker int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 111814c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 111914c32fd1SAlex Vesker u8 *formatted_ste, u8 *mask); 112014c32fd1SAlex Vesker int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 112114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 112214c32fd1SAlex Vesker u8 *ste_init_data, 112314c32fd1SAlex Vesker bool update_hw_ste); 112414c32fd1SAlex Vesker int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 112514c32fd1SAlex Vesker struct mlx5dr_action *action); 112614c32fd1SAlex Vesker 11276de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info { 11286de03d2dSErez Shitrit u32 id; 11296de03d2dSErez Shitrit u16 vport; 11306de03d2dSErez Shitrit enum fs_flow_table_type type; 11316de03d2dSErez Shitrit }; 11326de03d2dSErez Shitrit 11336de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info { 11346de03d2dSErez Shitrit enum mlx5_flow_destination_type type; 11356de03d2dSErez Shitrit union { 11366de03d2dSErez Shitrit u32 tir_num; 11376de03d2dSErez Shitrit u32 ft_num; 11386de03d2dSErez Shitrit u32 ft_id; 11396de03d2dSErez Shitrit u32 counter_id; 11406de03d2dSErez Shitrit struct { 11416de03d2dSErez Shitrit u16 num; 11426de03d2dSErez Shitrit u16 vhca_id; 11436de03d2dSErez Shitrit u32 reformat_id; 11446de03d2dSErez Shitrit u8 flags; 11456de03d2dSErez Shitrit } vport; 11466de03d2dSErez Shitrit }; 11476de03d2dSErez Shitrit }; 11486de03d2dSErez Shitrit 11496de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info { 11506de03d2dSErez Shitrit u32 dests_size; 11516de03d2dSErez Shitrit u32 index; 11526de03d2dSErez Shitrit struct mlx5_flow_context flow_context; 11536de03d2dSErez Shitrit u32 *val; 11546de03d2dSErez Shitrit struct mlx5_flow_act action; 11556de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 11566de03d2dSErez Shitrit }; 11576de03d2dSErez Shitrit 11586de03d2dSErez Shitrit int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 11596de03d2dSErez Shitrit int opmod, int modify_mask, 11606de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info *ft, 11616de03d2dSErez Shitrit u32 group_id, 11626de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info *fte); 11636de03d2dSErez Shitrit 116414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft { 116514c32fd1SAlex Vesker u64 rx_icm_addr; 116614c32fd1SAlex Vesker u32 table_id; 116714c32fd1SAlex Vesker u32 group_id; 116814c32fd1SAlex Vesker u32 modify_hdr_id; 116914c32fd1SAlex Vesker }; 117014c32fd1SAlex Vesker 117114c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft * 117214c32fd1SAlex Vesker mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num); 117314c32fd1SAlex Vesker void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 117414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 117514c32fd1SAlex Vesker int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 117614c32fd1SAlex Vesker u32 vport_num, 117714c32fd1SAlex Vesker u64 *rx_icm_addr); 117834583beeSErez Shitrit int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 117934583beeSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest, 118034583beeSErez Shitrit int num_dest, 118134583beeSErez Shitrit bool reformat_req, 118234583beeSErez Shitrit u32 *tbl_id, 118334583beeSErez Shitrit u32 *group_id); 118434583beeSErez Shitrit void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 118534583beeSErez Shitrit u32 group_id); 118614c32fd1SAlex Vesker #endif /* _DR_TYPES_H_ */ 1187