114c32fd1SAlex Vesker /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 214c32fd1SAlex Vesker /* Copyright (c) 2019, Mellanox Technologies */ 314c32fd1SAlex Vesker 414c32fd1SAlex Vesker #ifndef _DR_TYPES_ 514c32fd1SAlex Vesker #define _DR_TYPES_ 614c32fd1SAlex Vesker 714c32fd1SAlex Vesker #include <linux/mlx5/driver.h> 814c32fd1SAlex Vesker #include <linux/refcount.h> 914c32fd1SAlex Vesker #include "fs_core.h" 1014c32fd1SAlex Vesker #include "wq.h" 1114c32fd1SAlex Vesker #include "lib/mlx5.h" 1214c32fd1SAlex Vesker #include "mlx5_ifc_dr.h" 1314c32fd1SAlex Vesker #include "mlx5dr.h" 1414c32fd1SAlex Vesker 153442e033SYevgeny Kliteynik #define DR_RULE_MAX_STES 18 1614c32fd1SAlex Vesker #define DR_ACTION_MAX_STES 5 1714c32fd1SAlex Vesker #define WIRE_PORT 0xFFFF 1814c32fd1SAlex Vesker #define DR_STE_SVLAN 0x1 1914c32fd1SAlex Vesker #define DR_STE_CVLAN 0x2 20699d531fSMuhammad Sammar #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) 21160e9cb3SYevgeny Kliteynik #define DR_NUM_OF_FLEX_PARSERS 8 22160e9cb3SYevgeny Kliteynik #define DR_STE_MAX_FLEX_0_ID 3 23160e9cb3SYevgeny Kliteynik #define DR_STE_MAX_FLEX_1_ID 7 2414c32fd1SAlex Vesker 2514c32fd1SAlex Vesker #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 2614c32fd1SAlex Vesker #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 2714c32fd1SAlex Vesker #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 2814c32fd1SAlex Vesker 2914c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size { 3014c32fd1SAlex Vesker DR_CHUNK_SIZE_1, 3114c32fd1SAlex Vesker DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 3214c32fd1SAlex Vesker DR_CHUNK_SIZE_2, 3314c32fd1SAlex Vesker DR_CHUNK_SIZE_4, 3414c32fd1SAlex Vesker DR_CHUNK_SIZE_8, 3514c32fd1SAlex Vesker DR_CHUNK_SIZE_16, 3614c32fd1SAlex Vesker DR_CHUNK_SIZE_32, 3714c32fd1SAlex Vesker DR_CHUNK_SIZE_64, 3814c32fd1SAlex Vesker DR_CHUNK_SIZE_128, 3914c32fd1SAlex Vesker DR_CHUNK_SIZE_256, 4014c32fd1SAlex Vesker DR_CHUNK_SIZE_512, 4114c32fd1SAlex Vesker DR_CHUNK_SIZE_1K, 4214c32fd1SAlex Vesker DR_CHUNK_SIZE_2K, 4314c32fd1SAlex Vesker DR_CHUNK_SIZE_4K, 4414c32fd1SAlex Vesker DR_CHUNK_SIZE_8K, 4514c32fd1SAlex Vesker DR_CHUNK_SIZE_16K, 4614c32fd1SAlex Vesker DR_CHUNK_SIZE_32K, 4714c32fd1SAlex Vesker DR_CHUNK_SIZE_64K, 4814c32fd1SAlex Vesker DR_CHUNK_SIZE_128K, 4914c32fd1SAlex Vesker DR_CHUNK_SIZE_256K, 5014c32fd1SAlex Vesker DR_CHUNK_SIZE_512K, 5114c32fd1SAlex Vesker DR_CHUNK_SIZE_1024K, 5214c32fd1SAlex Vesker DR_CHUNK_SIZE_2048K, 5314c32fd1SAlex Vesker DR_CHUNK_SIZE_MAX, 5414c32fd1SAlex Vesker }; 5514c32fd1SAlex Vesker 5614c32fd1SAlex Vesker enum mlx5dr_icm_type { 5714c32fd1SAlex Vesker DR_ICM_TYPE_STE, 5814c32fd1SAlex Vesker DR_ICM_TYPE_MODIFY_ACTION, 5914c32fd1SAlex Vesker }; 6014c32fd1SAlex Vesker 6114c32fd1SAlex Vesker static inline enum mlx5dr_icm_chunk_size 6214c32fd1SAlex Vesker mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 6314c32fd1SAlex Vesker { 6414c32fd1SAlex Vesker chunk += 2; 6514c32fd1SAlex Vesker if (chunk < DR_CHUNK_SIZE_MAX) 6614c32fd1SAlex Vesker return chunk; 6714c32fd1SAlex Vesker 6814c32fd1SAlex Vesker return DR_CHUNK_SIZE_MAX; 6914c32fd1SAlex Vesker } 7014c32fd1SAlex Vesker 7114c32fd1SAlex Vesker enum { 7214c32fd1SAlex Vesker DR_STE_SIZE = 64, 7314c32fd1SAlex Vesker DR_STE_SIZE_CTRL = 32, 7414c32fd1SAlex Vesker DR_STE_SIZE_TAG = 16, 7514c32fd1SAlex Vesker DR_STE_SIZE_MASK = 16, 7614c32fd1SAlex Vesker }; 7714c32fd1SAlex Vesker 7814c32fd1SAlex Vesker enum { 7914c32fd1SAlex Vesker DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 8014c32fd1SAlex Vesker }; 8114c32fd1SAlex Vesker 8214c32fd1SAlex Vesker enum { 8314c32fd1SAlex Vesker DR_MODIFY_ACTION_SIZE = 8, 8414c32fd1SAlex Vesker }; 8514c32fd1SAlex Vesker 8614c32fd1SAlex Vesker enum mlx5dr_matcher_criteria { 8714c32fd1SAlex Vesker DR_MATCHER_CRITERIA_EMPTY = 0, 8814c32fd1SAlex Vesker DR_MATCHER_CRITERIA_OUTER = 1 << 0, 8914c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC = 1 << 1, 9014c32fd1SAlex Vesker DR_MATCHER_CRITERIA_INNER = 1 << 2, 9114c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 9214c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 93160e9cb3SYevgeny Kliteynik DR_MATCHER_CRITERIA_MISC4 = 1 << 5, 94160e9cb3SYevgeny Kliteynik DR_MATCHER_CRITERIA_MAX = 1 << 6, 9514c32fd1SAlex Vesker }; 9614c32fd1SAlex Vesker 9714c32fd1SAlex Vesker enum mlx5dr_action_type { 9814c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L2_TO_L2, 9914c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L2, 10014c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L3_TO_L2, 10114c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L3, 10214c32fd1SAlex Vesker DR_ACTION_TYP_DROP, 10314c32fd1SAlex Vesker DR_ACTION_TYP_QP, 10414c32fd1SAlex Vesker DR_ACTION_TYP_FT, 10514c32fd1SAlex Vesker DR_ACTION_TYP_CTR, 10614c32fd1SAlex Vesker DR_ACTION_TYP_TAG, 10714c32fd1SAlex Vesker DR_ACTION_TYP_MODIFY_HDR, 10814c32fd1SAlex Vesker DR_ACTION_TYP_VPORT, 10914c32fd1SAlex Vesker DR_ACTION_TYP_POP_VLAN, 11014c32fd1SAlex Vesker DR_ACTION_TYP_PUSH_VLAN, 11114c32fd1SAlex Vesker DR_ACTION_TYP_MAX, 11214c32fd1SAlex Vesker }; 11314c32fd1SAlex Vesker 114667f2646SAlex Vesker enum mlx5dr_ipv { 115667f2646SAlex Vesker DR_RULE_IPV4, 116667f2646SAlex Vesker DR_RULE_IPV6, 117667f2646SAlex Vesker DR_RULE_IPV_MAX, 118667f2646SAlex Vesker }; 119667f2646SAlex Vesker 12014c32fd1SAlex Vesker struct mlx5dr_icm_pool; 12114c32fd1SAlex Vesker struct mlx5dr_icm_chunk; 122a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem; 12314c32fd1SAlex Vesker struct mlx5dr_ste_htbl; 12414c32fd1SAlex Vesker struct mlx5dr_match_param; 12514c32fd1SAlex Vesker struct mlx5dr_cmd_caps; 12614c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx; 1275212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx; 12814c32fd1SAlex Vesker 12914c32fd1SAlex Vesker struct mlx5dr_ste { 13014c32fd1SAlex Vesker u8 *hw_ste; 13114c32fd1SAlex Vesker /* refcount: indicates the num of rules that using this ste */ 1324ce380caSYevgeny Kliteynik u32 refcount; 13314c32fd1SAlex Vesker 13414c32fd1SAlex Vesker /* attached to the miss_list head at each htbl entry */ 13514c32fd1SAlex Vesker struct list_head miss_list_node; 13614c32fd1SAlex Vesker 13714c32fd1SAlex Vesker /* each rule member that uses this ste attached here */ 13814c32fd1SAlex Vesker struct list_head rule_list; 13914c32fd1SAlex Vesker 14014c32fd1SAlex Vesker /* this ste is member of htbl */ 14114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl; 14214c32fd1SAlex Vesker 14314c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl; 14414c32fd1SAlex Vesker 14514c32fd1SAlex Vesker /* this ste is part of a rule, located in ste's chain */ 14614c32fd1SAlex Vesker u8 ste_chain_location; 14714c32fd1SAlex Vesker }; 14814c32fd1SAlex Vesker 14914c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl { 15014c32fd1SAlex Vesker /* total number of valid entries belonging to this hash table. This 15114c32fd1SAlex Vesker * includes the non collision and collision entries 15214c32fd1SAlex Vesker */ 15314c32fd1SAlex Vesker unsigned int num_of_valid_entries; 15414c32fd1SAlex Vesker 15514c32fd1SAlex Vesker /* total number of collisions entries attached to this table */ 15614c32fd1SAlex Vesker unsigned int num_of_collisions; 15714c32fd1SAlex Vesker unsigned int increase_threshold; 15814c32fd1SAlex Vesker u8 may_grow:1; 15914c32fd1SAlex Vesker }; 16014c32fd1SAlex Vesker 16114c32fd1SAlex Vesker struct mlx5dr_ste_htbl { 162dd2d3c8dSYevgeny Kliteynik u16 lu_type; 16314c32fd1SAlex Vesker u16 byte_mask; 1644ce380caSYevgeny Kliteynik u32 refcount; 16514c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 16614c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 16714c32fd1SAlex Vesker u8 *hw_ste_arr; 16814c32fd1SAlex Vesker 16914c32fd1SAlex Vesker struct list_head *miss_list; 17014c32fd1SAlex Vesker 17114c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size; 17214c32fd1SAlex Vesker struct mlx5dr_ste *pointing_ste; 17314c32fd1SAlex Vesker 17414c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl ctrl; 17514c32fd1SAlex Vesker }; 17614c32fd1SAlex Vesker 17714c32fd1SAlex Vesker struct mlx5dr_ste_send_info { 17814c32fd1SAlex Vesker struct mlx5dr_ste *ste; 17914c32fd1SAlex Vesker struct list_head send_list; 18014c32fd1SAlex Vesker u16 size; 18114c32fd1SAlex Vesker u16 offset; 18214c32fd1SAlex Vesker u8 data_cont[DR_STE_SIZE]; 18314c32fd1SAlex Vesker u8 *data; 18414c32fd1SAlex Vesker }; 18514c32fd1SAlex Vesker 18614c32fd1SAlex Vesker void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 18714c32fd1SAlex Vesker u16 offset, u8 *data, 18814c32fd1SAlex Vesker struct mlx5dr_ste_send_info *ste_info, 18914c32fd1SAlex Vesker struct list_head *send_list, 19014c32fd1SAlex Vesker bool copy_data); 19114c32fd1SAlex Vesker 19214c32fd1SAlex Vesker struct mlx5dr_ste_build { 19314c32fd1SAlex Vesker u8 inner:1; 19414c32fd1SAlex Vesker u8 rx:1; 195640bdb1fSAlaa Hleihel u8 vhca_id_valid:1; 196640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn; 19714c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps; 198dd2d3c8dSYevgeny Kliteynik u16 lu_type; 19914c32fd1SAlex Vesker u16 byte_mask; 20014c32fd1SAlex Vesker u8 bit_mask[DR_STE_SIZE_MASK]; 20114c32fd1SAlex Vesker int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 20214c32fd1SAlex Vesker struct mlx5dr_ste_build *sb, 203e6b69bf3SYevgeny Kliteynik u8 *tag); 20414c32fd1SAlex Vesker }; 20514c32fd1SAlex Vesker 20614c32fd1SAlex Vesker struct mlx5dr_ste_htbl * 20714c32fd1SAlex Vesker mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 20814c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size, 209dd2d3c8dSYevgeny Kliteynik u16 lu_type, u16 byte_mask); 21014c32fd1SAlex Vesker 21114c32fd1SAlex Vesker int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 21214c32fd1SAlex Vesker 21314c32fd1SAlex Vesker static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 21414c32fd1SAlex Vesker { 2154ce380caSYevgeny Kliteynik htbl->refcount--; 2164ce380caSYevgeny Kliteynik if (!htbl->refcount) 21714c32fd1SAlex Vesker mlx5dr_ste_htbl_free(htbl); 21814c32fd1SAlex Vesker } 21914c32fd1SAlex Vesker 22014c32fd1SAlex Vesker static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 22114c32fd1SAlex Vesker { 2224ce380caSYevgeny Kliteynik htbl->refcount++; 22314c32fd1SAlex Vesker } 22414c32fd1SAlex Vesker 22514c32fd1SAlex Vesker /* STE utils */ 22614c32fd1SAlex Vesker u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 2276b93b400SYevgeny Kliteynik void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, 2286b93b400SYevgeny Kliteynik u8 *hw_ste, u64 miss_addr); 2296b93b400SYevgeny Kliteynik void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, 2306b93b400SYevgeny Kliteynik u8 *hw_ste, u64 icm_addr, u32 ht_size); 2316b93b400SYevgeny Kliteynik void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, 2326b93b400SYevgeny Kliteynik u8 *hw_ste, 2336b93b400SYevgeny Kliteynik struct mlx5dr_ste_htbl *next_htbl); 23414c32fd1SAlex Vesker void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 23514c32fd1SAlex Vesker bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 23614c32fd1SAlex Vesker u8 ste_location); 23714c32fd1SAlex Vesker u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 23814c32fd1SAlex Vesker u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 23914c32fd1SAlex Vesker struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 24014c32fd1SAlex Vesker 24164c78942SYevgeny Kliteynik #define MLX5DR_MAX_VLANS 2 24264c78942SYevgeny Kliteynik 24364c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr { 24464c78942SYevgeny Kliteynik u32 modify_index; 24564c78942SYevgeny Kliteynik u16 modify_actions; 24664c78942SYevgeny Kliteynik u32 decap_index; 24764c78942SYevgeny Kliteynik u16 decap_actions; 24864c78942SYevgeny Kliteynik u8 decap_with_vlan:1; 24964c78942SYevgeny Kliteynik u64 final_icm_addr; 25064c78942SYevgeny Kliteynik u32 flow_tag; 25164c78942SYevgeny Kliteynik u32 ctr_id; 25264c78942SYevgeny Kliteynik u16 gvmi; 25364c78942SYevgeny Kliteynik u16 hit_gvmi; 25464c78942SYevgeny Kliteynik u32 reformat_id; 25564c78942SYevgeny Kliteynik u32 reformat_size; 25664c78942SYevgeny Kliteynik struct { 25764c78942SYevgeny Kliteynik int count; 25864c78942SYevgeny Kliteynik u32 headers[MLX5DR_MAX_VLANS]; 25964c78942SYevgeny Kliteynik } vlans; 26064c78942SYevgeny Kliteynik }; 26164c78942SYevgeny Kliteynik 2626b93b400SYevgeny Kliteynik void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, 2636b93b400SYevgeny Kliteynik struct mlx5dr_domain *dmn, 26464c78942SYevgeny Kliteynik u8 *action_type_set, 26564c78942SYevgeny Kliteynik u8 *last_ste, 26664c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 26764c78942SYevgeny Kliteynik u32 *added_stes); 2686b93b400SYevgeny Kliteynik void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, 2696b93b400SYevgeny Kliteynik struct mlx5dr_domain *dmn, 27064c78942SYevgeny Kliteynik u8 *action_type_set, 27164c78942SYevgeny Kliteynik u8 *last_ste, 27264c78942SYevgeny Kliteynik struct mlx5dr_ste_actions_attr *attr, 27364c78942SYevgeny Kliteynik u32 *added_stes); 27464c78942SYevgeny Kliteynik 2754781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, 2764781df92SYevgeny Kliteynik __be64 *hw_action, 2774781df92SYevgeny Kliteynik u8 hw_field, 2784781df92SYevgeny Kliteynik u8 shifter, 2794781df92SYevgeny Kliteynik u8 length, 2804781df92SYevgeny Kliteynik u32 data); 2814781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, 2824781df92SYevgeny Kliteynik __be64 *hw_action, 2834781df92SYevgeny Kliteynik u8 hw_field, 2844781df92SYevgeny Kliteynik u8 shifter, 2854781df92SYevgeny Kliteynik u8 length, 2864781df92SYevgeny Kliteynik u32 data); 2874781df92SYevgeny Kliteynik void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, 2884781df92SYevgeny Kliteynik __be64 *hw_action, 2894781df92SYevgeny Kliteynik u8 dst_hw_field, 2904781df92SYevgeny Kliteynik u8 dst_shifter, 2914781df92SYevgeny Kliteynik u8 dst_len, 2924781df92SYevgeny Kliteynik u8 src_hw_field, 2934781df92SYevgeny Kliteynik u8 src_shifter); 2944781df92SYevgeny Kliteynik int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, 2954781df92SYevgeny Kliteynik void *data, 2964781df92SYevgeny Kliteynik u32 data_sz, 2974781df92SYevgeny Kliteynik u8 *hw_action, 2984781df92SYevgeny Kliteynik u32 hw_action_sz, 2994781df92SYevgeny Kliteynik u16 *used_hw_action_num); 3004781df92SYevgeny Kliteynik 3014781df92SYevgeny Kliteynik const struct mlx5dr_ste_action_modify_field * 3024781df92SYevgeny Kliteynik mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field); 3034781df92SYevgeny Kliteynik 3045212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); 30514c32fd1SAlex Vesker void mlx5dr_ste_free(struct mlx5dr_ste *ste, 30614c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 30714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher); 30814c32fd1SAlex Vesker static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 30914c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 31014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher) 31114c32fd1SAlex Vesker { 3124ce380caSYevgeny Kliteynik ste->refcount--; 3134ce380caSYevgeny Kliteynik if (!ste->refcount) 31414c32fd1SAlex Vesker mlx5dr_ste_free(ste, matcher, nic_matcher); 31514c32fd1SAlex Vesker } 31614c32fd1SAlex Vesker 31714c32fd1SAlex Vesker /* initial as 0, increased only when ste appears in a new rule */ 31814c32fd1SAlex Vesker static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 31914c32fd1SAlex Vesker { 3204ce380caSYevgeny Kliteynik ste->refcount++; 32114c32fd1SAlex Vesker } 32214c32fd1SAlex Vesker 32397ffd895SYevgeny Kliteynik static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste) 32497ffd895SYevgeny Kliteynik { 32597ffd895SYevgeny Kliteynik return !ste->refcount; 32697ffd895SYevgeny Kliteynik } 32797ffd895SYevgeny Kliteynik 32814c32fd1SAlex Vesker bool mlx5dr_ste_equal_tag(void *src, void *dst); 32914c32fd1SAlex Vesker int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 33014c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 33114c32fd1SAlex Vesker struct mlx5dr_ste *ste, 33214c32fd1SAlex Vesker u8 *cur_hw_ste, 33314c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size log_table_size); 33414c32fd1SAlex Vesker 33514c32fd1SAlex Vesker /* STE build functions */ 33614c32fd1SAlex Vesker int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 33714c32fd1SAlex Vesker u8 match_criteria, 33814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 33914c32fd1SAlex Vesker struct mlx5dr_match_param *value); 34014c32fd1SAlex Vesker int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 34114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 34214c32fd1SAlex Vesker struct mlx5dr_match_param *value, 34314c32fd1SAlex Vesker u8 *ste_arr); 3445212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, 3455212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *builder, 34614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 34714c32fd1SAlex Vesker bool inner, bool rx); 3485212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, 3495212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 35014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 35114c32fd1SAlex Vesker bool inner, bool rx); 3525212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, 3535212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 35414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 35514c32fd1SAlex Vesker bool inner, bool rx); 3565212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, 3575212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 35814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 35914c32fd1SAlex Vesker bool inner, bool rx); 3605212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, 3615212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 36214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 36314c32fd1SAlex Vesker bool inner, bool rx); 3645212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, 3655212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 36614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 36714c32fd1SAlex Vesker bool inner, bool rx); 3685212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, 3695212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37114c32fd1SAlex Vesker bool inner, bool rx); 3725212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, 3735212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37514c32fd1SAlex Vesker bool inner, bool rx); 3765212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, 3775212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 37814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 37914c32fd1SAlex Vesker bool inner, bool rx); 3805212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, 3815212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 38214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 38314c32fd1SAlex Vesker bool inner, bool rx); 3845212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, 3855212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 38614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 38714c32fd1SAlex Vesker bool inner, bool rx); 3885212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, 3895212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39114c32fd1SAlex Vesker bool inner, bool rx); 3925212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, 3935212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 39414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 39514c32fd1SAlex Vesker bool inner, bool rx); 396*35ba005dSYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx, 397*35ba005dSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 398*35ba005dSYevgeny Kliteynik struct mlx5dr_match_param *mask, 399*35ba005dSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 400*35ba005dSYevgeny Kliteynik bool inner, bool rx); 401*35ba005dSYevgeny Kliteynik void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx, 402*35ba005dSYevgeny Kliteynik struct mlx5dr_ste_build *sb, 403*35ba005dSYevgeny Kliteynik struct mlx5dr_match_param *mask, 404*35ba005dSYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 405*35ba005dSYevgeny Kliteynik bool inner, bool rx); 4064923938dSYevgeny Kliteynik void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, 4075212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 40814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 40914c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps, 41014c32fd1SAlex Vesker bool inner, bool rx); 4115212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, 4125212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 41314c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 41414c32fd1SAlex Vesker bool inner, bool rx); 4155212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, 4165212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 417b6d12238SYevgeny Kliteynik struct mlx5dr_match_param *mask, 418b6d12238SYevgeny Kliteynik bool inner, bool rx); 4193442e033SYevgeny Kliteynik void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, 4203442e033SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 4213442e033SYevgeny Kliteynik struct mlx5dr_match_param *mask, 4223442e033SYevgeny Kliteynik struct mlx5dr_cmd_caps *caps, 4233442e033SYevgeny Kliteynik bool inner, bool rx); 4245212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, 4255212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 42614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 42714c32fd1SAlex Vesker bool inner, bool rx); 4285212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, 4295212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 43114c32fd1SAlex Vesker bool inner, bool rx); 4325212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, 4335212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 43514c32fd1SAlex Vesker bool inner, bool rx); 4365212f9c6SYevgeny Kliteynik void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, 4375212f9c6SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 43814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 439640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn, 44014c32fd1SAlex Vesker bool inner, bool rx); 441160e9cb3SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx, 442160e9cb3SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 443160e9cb3SYevgeny Kliteynik struct mlx5dr_match_param *mask, 444160e9cb3SYevgeny Kliteynik bool inner, bool rx); 445160e9cb3SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx, 446160e9cb3SYevgeny Kliteynik struct mlx5dr_ste_build *sb, 447160e9cb3SYevgeny Kliteynik struct mlx5dr_match_param *mask, 448160e9cb3SYevgeny Kliteynik bool inner, bool rx); 44914c32fd1SAlex Vesker void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 45014c32fd1SAlex Vesker 45114c32fd1SAlex Vesker /* Actions utils */ 45214c32fd1SAlex Vesker int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 45314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 45414c32fd1SAlex Vesker struct mlx5dr_action *actions[], 45514c32fd1SAlex Vesker u32 num_actions, 45614c32fd1SAlex Vesker u8 *ste_arr, 45714c32fd1SAlex Vesker u32 *new_hw_ste_arr_sz); 45814c32fd1SAlex Vesker 45914c32fd1SAlex Vesker struct mlx5dr_match_spec { 46014c32fd1SAlex Vesker u32 smac_47_16; /* Source MAC address of incoming packet */ 46114c32fd1SAlex Vesker /* Incoming packet Ethertype - this is the Ethertype 46214c32fd1SAlex Vesker * following the last VLAN tag of the packet 46314c32fd1SAlex Vesker */ 46414c32fd1SAlex Vesker u32 ethertype:16; 46514c32fd1SAlex Vesker u32 smac_15_0:16; /* Source MAC address of incoming packet */ 46614c32fd1SAlex Vesker u32 dmac_47_16; /* Destination MAC address of incoming packet */ 46714c32fd1SAlex Vesker /* VLAN ID of first VLAN tag in the incoming packet. 46814c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 46914c32fd1SAlex Vesker */ 47014c32fd1SAlex Vesker u32 first_vid:12; 47114c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the incoming packet. 47214c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 47314c32fd1SAlex Vesker */ 47414c32fd1SAlex Vesker u32 first_cfi:1; 47514c32fd1SAlex Vesker /* Priority of first VLAN tag in the incoming packet. 47614c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 47714c32fd1SAlex Vesker */ 47814c32fd1SAlex Vesker u32 first_prio:3; 47914c32fd1SAlex Vesker u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 48014c32fd1SAlex Vesker /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 48114c32fd1SAlex Vesker * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 48214c32fd1SAlex Vesker */ 48314c32fd1SAlex Vesker u32 tcp_flags:9; 48414c32fd1SAlex Vesker u32 ip_version:4; /* IP version */ 48514c32fd1SAlex Vesker u32 frag:1; /* Packet is an IP fragment */ 48614c32fd1SAlex Vesker /* The first vlan in the packet is s-vlan (0x8a88). 48714c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 48814c32fd1SAlex Vesker */ 48914c32fd1SAlex Vesker u32 svlan_tag:1; 49014c32fd1SAlex Vesker /* The first vlan in the packet is c-vlan (0x8100). 49114c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 49214c32fd1SAlex Vesker */ 49314c32fd1SAlex Vesker u32 cvlan_tag:1; 49414c32fd1SAlex Vesker /* Explicit Congestion Notification derived from 49514c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 49614c32fd1SAlex Vesker */ 49714c32fd1SAlex Vesker u32 ip_ecn:2; 49814c32fd1SAlex Vesker /* Differentiated Services Code Point derived from 49914c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 50014c32fd1SAlex Vesker */ 50114c32fd1SAlex Vesker u32 ip_dscp:6; 50214c32fd1SAlex Vesker u32 ip_protocol:8; /* IP protocol */ 50314c32fd1SAlex Vesker /* TCP destination port. 50414c32fd1SAlex Vesker * tcp and udp sport/dport are mutually exclusive 50514c32fd1SAlex Vesker */ 50614c32fd1SAlex Vesker u32 tcp_dport:16; 50714c32fd1SAlex Vesker /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 50814c32fd1SAlex Vesker u32 tcp_sport:16; 50914c32fd1SAlex Vesker u32 ttl_hoplimit:8; 51014c32fd1SAlex Vesker u32 reserved:24; 51114c32fd1SAlex Vesker /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 51214c32fd1SAlex Vesker u32 udp_dport:16; 51314c32fd1SAlex Vesker /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 51414c32fd1SAlex Vesker u32 udp_sport:16; 51514c32fd1SAlex Vesker /* IPv6 source address of incoming packets 51614c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 51714c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 51814c32fd1SAlex Vesker */ 51914c32fd1SAlex Vesker u32 src_ip_127_96; 52014c32fd1SAlex Vesker /* IPv6 source address of incoming packets 52114c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 52214c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 52314c32fd1SAlex Vesker */ 52414c32fd1SAlex Vesker u32 src_ip_95_64; 52514c32fd1SAlex Vesker /* IPv6 source address of incoming packets 52614c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 52714c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 52814c32fd1SAlex Vesker */ 52914c32fd1SAlex Vesker u32 src_ip_63_32; 53014c32fd1SAlex Vesker /* IPv6 source address of incoming packets 53114c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 53214c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 53314c32fd1SAlex Vesker */ 53414c32fd1SAlex Vesker u32 src_ip_31_0; 53514c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 53614c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 53714c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 53814c32fd1SAlex Vesker */ 53914c32fd1SAlex Vesker u32 dst_ip_127_96; 54014c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 54114c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 54214c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 54314c32fd1SAlex Vesker */ 54414c32fd1SAlex Vesker u32 dst_ip_95_64; 54514c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 54614c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 54714c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 54814c32fd1SAlex Vesker */ 54914c32fd1SAlex Vesker u32 dst_ip_63_32; 55014c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 55114c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 55214c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 55314c32fd1SAlex Vesker */ 55414c32fd1SAlex Vesker u32 dst_ip_31_0; 55514c32fd1SAlex Vesker }; 55614c32fd1SAlex Vesker 55714c32fd1SAlex Vesker struct mlx5dr_match_misc { 55814c32fd1SAlex Vesker u32 source_sqn:24; /* Source SQN */ 55914c32fd1SAlex Vesker u32 source_vhca_port:4; 56014c32fd1SAlex Vesker /* used with GRE, sequence number exist when gre_s_present == 1 */ 56114c32fd1SAlex Vesker u32 gre_s_present:1; 56214c32fd1SAlex Vesker /* used with GRE, key exist when gre_k_present == 1 */ 56314c32fd1SAlex Vesker u32 gre_k_present:1; 56414c32fd1SAlex Vesker u32 reserved_auto1:1; 56514c32fd1SAlex Vesker /* used with GRE, checksum exist when gre_c_present == 1 */ 56614c32fd1SAlex Vesker u32 gre_c_present:1; 56714c32fd1SAlex Vesker /* Source port.;0xffff determines wire port */ 56814c32fd1SAlex Vesker u32 source_port:16; 569640bdb1fSAlaa Hleihel u32 source_eswitch_owner_vhca_id:16; 57014c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the inner header of the incoming packet. 57114c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 57214c32fd1SAlex Vesker */ 57314c32fd1SAlex Vesker u32 inner_second_vid:12; 57414c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the inner header of the incoming packet. 57514c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 57614c32fd1SAlex Vesker */ 57714c32fd1SAlex Vesker u32 inner_second_cfi:1; 57814c32fd1SAlex Vesker /* Priority of second VLAN tag in the inner header of the incoming packet. 57914c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 58014c32fd1SAlex Vesker */ 58114c32fd1SAlex Vesker u32 inner_second_prio:3; 58214c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the outer header of the incoming packet. 58314c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 58414c32fd1SAlex Vesker */ 58514c32fd1SAlex Vesker u32 outer_second_vid:12; 58614c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the outer header of the incoming packet. 58714c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 58814c32fd1SAlex Vesker */ 58914c32fd1SAlex Vesker u32 outer_second_cfi:1; 59014c32fd1SAlex Vesker /* Priority of second VLAN tag in the outer header of the incoming packet. 59114c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 59214c32fd1SAlex Vesker */ 59314c32fd1SAlex Vesker u32 outer_second_prio:3; 59414c32fd1SAlex Vesker u32 gre_protocol:16; /* GRE Protocol (outer) */ 59514c32fd1SAlex Vesker u32 reserved_auto3:12; 59614c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 59714c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 59814c32fd1SAlex Vesker */ 59914c32fd1SAlex Vesker u32 inner_second_svlan_tag:1; 60014c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 60114c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 60214c32fd1SAlex Vesker */ 60314c32fd1SAlex Vesker u32 outer_second_svlan_tag:1; 60414c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is c-vlan (0x8100). 60514c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 60614c32fd1SAlex Vesker */ 60714c32fd1SAlex Vesker u32 inner_second_cvlan_tag:1; 60814c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is c-vlan (0x8100). 60914c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 61014c32fd1SAlex Vesker */ 61114c32fd1SAlex Vesker u32 outer_second_cvlan_tag:1; 61214c32fd1SAlex Vesker u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 61314c32fd1SAlex Vesker u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 61414c32fd1SAlex Vesker u32 reserved_auto4:8; 61514c32fd1SAlex Vesker u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 61614c32fd1SAlex Vesker u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 61714c32fd1SAlex Vesker u32 reserved_auto5:7; 61814c32fd1SAlex Vesker u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 61914c32fd1SAlex Vesker u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 62014c32fd1SAlex Vesker u32 reserved_auto6:12; 62114c32fd1SAlex Vesker u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 62214c32fd1SAlex Vesker u32 reserved_auto7:12; 62314c32fd1SAlex Vesker u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 62414c32fd1SAlex Vesker u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 62514c32fd1SAlex Vesker u32 reserved_auto8:10; 62614c32fd1SAlex Vesker u32 bth_dst_qp:24; /* Destination QP in BTH header */ 62714c32fd1SAlex Vesker u32 reserved_auto9:8; 62814c32fd1SAlex Vesker u8 reserved_auto10[20]; 62914c32fd1SAlex Vesker }; 63014c32fd1SAlex Vesker 63114c32fd1SAlex Vesker struct mlx5dr_match_misc2 { 63214c32fd1SAlex Vesker u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 63314c32fd1SAlex Vesker u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 63414c32fd1SAlex Vesker u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 63514c32fd1SAlex Vesker u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 63614c32fd1SAlex Vesker u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 63714c32fd1SAlex Vesker u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 63814c32fd1SAlex Vesker u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 63914c32fd1SAlex Vesker u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 64014c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 64114c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 64214c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 64314c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 64414c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 64514c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 64614c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 64714c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 64814c32fd1SAlex Vesker u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 64914c32fd1SAlex Vesker u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 65014c32fd1SAlex Vesker u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 65114c32fd1SAlex Vesker u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 65214c32fd1SAlex Vesker u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 65314c32fd1SAlex Vesker u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 65414c32fd1SAlex Vesker u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 65514c32fd1SAlex Vesker u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 65614c32fd1SAlex Vesker u32 metadata_reg_a; /* metadata_reg_a */ 657356d411cSRaed Salem u8 reserved_auto2[12]; 65814c32fd1SAlex Vesker }; 65914c32fd1SAlex Vesker 66014c32fd1SAlex Vesker struct mlx5dr_match_misc3 { 66114c32fd1SAlex Vesker u32 inner_tcp_seq_num; 66214c32fd1SAlex Vesker u32 outer_tcp_seq_num; 66314c32fd1SAlex Vesker u32 inner_tcp_ack_num; 66414c32fd1SAlex Vesker u32 outer_tcp_ack_num; 66514c32fd1SAlex Vesker u32 outer_vxlan_gpe_vni:24; 66614c32fd1SAlex Vesker u32 reserved_auto1:8; 66714c32fd1SAlex Vesker u32 reserved_auto2:16; 66814c32fd1SAlex Vesker u32 outer_vxlan_gpe_flags:8; 66914c32fd1SAlex Vesker u32 outer_vxlan_gpe_next_protocol:8; 67014c32fd1SAlex Vesker u32 icmpv4_header_data; 67114c32fd1SAlex Vesker u32 icmpv6_header_data; 67240ca842cSYevgeny Kliteynik u8 icmpv6_code; 67340ca842cSYevgeny Kliteynik u8 icmpv6_type; 67440ca842cSYevgeny Kliteynik u8 icmpv4_code; 67540ca842cSYevgeny Kliteynik u8 icmpv4_type; 6763442e033SYevgeny Kliteynik u32 geneve_tlv_option_0_data; 6773442e033SYevgeny Kliteynik u8 reserved_auto3[0x18]; 67814c32fd1SAlex Vesker }; 67914c32fd1SAlex Vesker 680160e9cb3SYevgeny Kliteynik struct mlx5dr_match_misc4 { 681160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_0; 682160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_0; 683160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_1; 684160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_1; 685160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_2; 686160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_2; 687160e9cb3SYevgeny Kliteynik u32 prog_sample_field_value_3; 688160e9cb3SYevgeny Kliteynik u32 prog_sample_field_id_3; 689160e9cb3SYevgeny Kliteynik }; 690160e9cb3SYevgeny Kliteynik 69114c32fd1SAlex Vesker struct mlx5dr_match_param { 69214c32fd1SAlex Vesker struct mlx5dr_match_spec outer; 69314c32fd1SAlex Vesker struct mlx5dr_match_misc misc; 69414c32fd1SAlex Vesker struct mlx5dr_match_spec inner; 69514c32fd1SAlex Vesker struct mlx5dr_match_misc2 misc2; 69614c32fd1SAlex Vesker struct mlx5dr_match_misc3 misc3; 697160e9cb3SYevgeny Kliteynik struct mlx5dr_match_misc4 misc4; 69814c32fd1SAlex Vesker }; 69914c32fd1SAlex Vesker 700de1facafSYevgeny Kliteynik #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 70114c32fd1SAlex Vesker (_misc3)->icmpv4_code || \ 70214c32fd1SAlex Vesker (_misc3)->icmpv4_header_data) 70314c32fd1SAlex Vesker 70414c32fd1SAlex Vesker struct mlx5dr_esw_caps { 70514c32fd1SAlex Vesker u64 drop_icm_address_rx; 70614c32fd1SAlex Vesker u64 drop_icm_address_tx; 70714c32fd1SAlex Vesker u64 uplink_icm_address_rx; 70814c32fd1SAlex Vesker u64 uplink_icm_address_tx; 70964f45c0fSYevgeny Kliteynik u8 sw_owner:1; 71064f45c0fSYevgeny Kliteynik u8 sw_owner_v2:1; 71114c32fd1SAlex Vesker }; 71214c32fd1SAlex Vesker 71314c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap { 71414c32fd1SAlex Vesker u16 vport_gvmi; 71514c32fd1SAlex Vesker u16 vhca_gvmi; 71614c32fd1SAlex Vesker u64 icm_address_rx; 71714c32fd1SAlex Vesker u64 icm_address_tx; 71814c32fd1SAlex Vesker u32 num; 71914c32fd1SAlex Vesker }; 72014c32fd1SAlex Vesker 72114c32fd1SAlex Vesker struct mlx5dr_cmd_caps { 72214c32fd1SAlex Vesker u16 gvmi; 72314c32fd1SAlex Vesker u64 nic_rx_drop_address; 72414c32fd1SAlex Vesker u64 nic_tx_drop_address; 72514c32fd1SAlex Vesker u64 nic_tx_allow_address; 72614c32fd1SAlex Vesker u64 esw_rx_drop_address; 72714c32fd1SAlex Vesker u64 esw_tx_drop_address; 72814c32fd1SAlex Vesker u32 log_icm_size; 72914c32fd1SAlex Vesker u64 hdr_modify_icm_addr; 73014c32fd1SAlex Vesker u32 flex_protocols; 73114c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw0; 73214c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw1; 73314c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw0; 73414c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw1; 7353442e033SYevgeny Kliteynik u8 flex_parser_id_geneve_tlv_option_0; 736*35ba005dSYevgeny Kliteynik u8 flex_parser_id_mpls_over_gre; 737*35ba005dSYevgeny Kliteynik u8 flex_parser_id_mpls_over_udp; 73814c32fd1SAlex Vesker u8 max_ft_level; 73914c32fd1SAlex Vesker u16 roce_min_src_udp; 74014c32fd1SAlex Vesker u8 num_esw_ports; 741d421e466SYevgeny Kliteynik u8 sw_format_ver; 74214c32fd1SAlex Vesker bool eswitch_manager; 74314c32fd1SAlex Vesker bool rx_sw_owner; 74414c32fd1SAlex Vesker bool tx_sw_owner; 74514c32fd1SAlex Vesker bool fdb_sw_owner; 74664f45c0fSYevgeny Kliteynik u8 rx_sw_owner_v2:1; 74764f45c0fSYevgeny Kliteynik u8 tx_sw_owner_v2:1; 74864f45c0fSYevgeny Kliteynik u8 fdb_sw_owner_v2:1; 74914c32fd1SAlex Vesker u32 num_vports; 75014c32fd1SAlex Vesker struct mlx5dr_esw_caps esw_caps; 75114c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *vports_caps; 75214c32fd1SAlex Vesker bool prio_tag_required; 75314c32fd1SAlex Vesker }; 75414c32fd1SAlex Vesker 75514c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx { 75614c32fd1SAlex Vesker u64 drop_icm_addr; 75714c32fd1SAlex Vesker u64 default_icm_addr; 75814c32fd1SAlex Vesker enum mlx5dr_ste_entry_type ste_type; 759ed03a418SAlex Vesker struct mutex mutex; /* protect rx/tx domain */ 76014c32fd1SAlex Vesker }; 76114c32fd1SAlex Vesker 76214c32fd1SAlex Vesker struct mlx5dr_domain_info { 76314c32fd1SAlex Vesker bool supp_sw_steering; 76414c32fd1SAlex Vesker u32 max_inline_size; 76514c32fd1SAlex Vesker u32 max_send_wr; 76614c32fd1SAlex Vesker u32 max_log_sw_icm_sz; 76714c32fd1SAlex Vesker u32 max_log_action_icm_sz; 76814c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx rx; 76914c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx tx; 77014c32fd1SAlex Vesker struct mlx5dr_cmd_caps caps; 77114c32fd1SAlex Vesker }; 77214c32fd1SAlex Vesker 77314c32fd1SAlex Vesker struct mlx5dr_domain_cache { 77414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft; 77514c32fd1SAlex Vesker }; 77614c32fd1SAlex Vesker 77714c32fd1SAlex Vesker struct mlx5dr_domain { 77814c32fd1SAlex Vesker struct mlx5dr_domain *peer_dmn; 77914c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 78014c32fd1SAlex Vesker u32 pdn; 78114c32fd1SAlex Vesker struct mlx5_uars_page *uar; 78214c32fd1SAlex Vesker enum mlx5dr_domain_type type; 78314c32fd1SAlex Vesker refcount_t refcount; 78414c32fd1SAlex Vesker struct mlx5dr_icm_pool *ste_icm_pool; 78514c32fd1SAlex Vesker struct mlx5dr_icm_pool *action_icm_pool; 78614c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring; 78714c32fd1SAlex Vesker struct mlx5dr_domain_info info; 78814c32fd1SAlex Vesker struct mlx5dr_domain_cache cache; 7895212f9c6SYevgeny Kliteynik struct mlx5dr_ste_ctx *ste_ctx; 79014c32fd1SAlex Vesker }; 79114c32fd1SAlex Vesker 79214c32fd1SAlex Vesker struct mlx5dr_table_rx_tx { 79314c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_anchor; 79414c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn; 79514c32fd1SAlex Vesker u64 default_icm_addr; 79614c32fd1SAlex Vesker }; 79714c32fd1SAlex Vesker 79814c32fd1SAlex Vesker struct mlx5dr_table { 79914c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 80014c32fd1SAlex Vesker struct mlx5dr_table_rx_tx rx; 80114c32fd1SAlex Vesker struct mlx5dr_table_rx_tx tx; 80214c32fd1SAlex Vesker u32 level; 80314c32fd1SAlex Vesker u32 table_type; 80414c32fd1SAlex Vesker u32 table_id; 805988fd6b3SErez Shitrit u32 flags; 80614c32fd1SAlex Vesker struct list_head matcher_list; 80714c32fd1SAlex Vesker struct mlx5dr_action *miss_action; 80814c32fd1SAlex Vesker refcount_t refcount; 80914c32fd1SAlex Vesker }; 81014c32fd1SAlex Vesker 81114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx { 81214c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_htbl; 81314c32fd1SAlex Vesker struct mlx5dr_ste_htbl *e_anchor; 81414c32fd1SAlex Vesker struct mlx5dr_ste_build *ste_builder; 815667f2646SAlex Vesker struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 816667f2646SAlex Vesker [DR_RULE_IPV_MAX] 817667f2646SAlex Vesker [DR_RULE_MAX_STES]; 81814c32fd1SAlex Vesker u8 num_of_builders; 819667f2646SAlex Vesker u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 82014c32fd1SAlex Vesker u64 default_icm_addr; 82114c32fd1SAlex Vesker struct mlx5dr_table_rx_tx *nic_tbl; 82214c32fd1SAlex Vesker }; 82314c32fd1SAlex Vesker 82414c32fd1SAlex Vesker struct mlx5dr_matcher { 82514c32fd1SAlex Vesker struct mlx5dr_table *tbl; 82614c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx rx; 82714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx tx; 82814c32fd1SAlex Vesker struct list_head matcher_list; 829f6409299SHamdan Igbaria u32 prio; 83014c32fd1SAlex Vesker struct mlx5dr_match_param mask; 83114c32fd1SAlex Vesker u8 match_criteria; 83214c32fd1SAlex Vesker refcount_t refcount; 83314c32fd1SAlex Vesker struct mlx5dv_flow_matcher *dv_matcher; 83414c32fd1SAlex Vesker }; 83514c32fd1SAlex Vesker 83614c32fd1SAlex Vesker struct mlx5dr_rule_member { 83714c32fd1SAlex Vesker struct mlx5dr_ste *ste; 83814c32fd1SAlex Vesker /* attached to mlx5dr_rule via this */ 83914c32fd1SAlex Vesker struct list_head list; 84014c32fd1SAlex Vesker /* attached to mlx5dr_ste via this */ 84114c32fd1SAlex Vesker struct list_head use_ste_list; 84214c32fd1SAlex Vesker }; 84314c32fd1SAlex Vesker 8444781df92SYevgeny Kliteynik struct mlx5dr_ste_action_modify_field { 8454781df92SYevgeny Kliteynik u16 hw_field; 8464781df92SYevgeny Kliteynik u8 start; 8474781df92SYevgeny Kliteynik u8 end; 8484781df92SYevgeny Kliteynik u8 l3_type; 8494781df92SYevgeny Kliteynik u8 l4_type; 8504781df92SYevgeny Kliteynik }; 8514781df92SYevgeny Kliteynik 8529dac2966SJianbo Liu struct mlx5dr_action_rewrite { 85314c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 85414c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 85514c32fd1SAlex Vesker u8 *data; 85614c32fd1SAlex Vesker u16 num_of_actions; 85714c32fd1SAlex Vesker u32 index; 85814c32fd1SAlex Vesker u8 allow_rx:1; 85914c32fd1SAlex Vesker u8 allow_tx:1; 86014c32fd1SAlex Vesker u8 modify_ttl:1; 8619dac2966SJianbo Liu }; 8629dac2966SJianbo Liu 8639dac2966SJianbo Liu struct mlx5dr_action_reformat { 86414c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 86514c32fd1SAlex Vesker u32 reformat_id; 86614c32fd1SAlex Vesker u32 reformat_size; 8679dac2966SJianbo Liu }; 8689dac2966SJianbo Liu 8699dac2966SJianbo Liu struct mlx5dr_action_dest_tbl { 87014c32fd1SAlex Vesker u8 is_fw_tbl:1; 87114c32fd1SAlex Vesker union { 87214c32fd1SAlex Vesker struct mlx5dr_table *tbl; 87314c32fd1SAlex Vesker struct { 874aec292eeSAlex Vesker struct mlx5dr_domain *dmn; 875aec292eeSAlex Vesker u32 id; 876b8853c96SAlex Vesker u32 group_id; 877aec292eeSAlex Vesker enum fs_flow_table_type type; 87814c32fd1SAlex Vesker u64 rx_icm_addr; 87914c32fd1SAlex Vesker u64 tx_icm_addr; 880b8853c96SAlex Vesker struct mlx5dr_action **ref_actions; 881b8853c96SAlex Vesker u32 num_of_ref_actions; 88214c32fd1SAlex Vesker } fw_tbl; 88314c32fd1SAlex Vesker }; 8849dac2966SJianbo Liu }; 8859dac2966SJianbo Liu 8869dac2966SJianbo Liu struct mlx5dr_action_ctr { 88714c32fd1SAlex Vesker u32 ctr_id; 88814c32fd1SAlex Vesker u32 offeset; 8899dac2966SJianbo Liu }; 8909dac2966SJianbo Liu 8919dac2966SJianbo Liu struct mlx5dr_action_vport { 89214c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 89314c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *caps; 8949dac2966SJianbo Liu }; 8959dac2966SJianbo Liu 8969dac2966SJianbo Liu struct mlx5dr_action_push_vlan { 89714c32fd1SAlex Vesker u32 vlan_hdr; /* tpid_pcp_dei_vid */ 8989dac2966SJianbo Liu }; 8999dac2966SJianbo Liu 9009dac2966SJianbo Liu struct mlx5dr_action_flow_tag { 90114c32fd1SAlex Vesker u32 flow_tag; 90214c32fd1SAlex Vesker }; 9039dac2966SJianbo Liu 9049dac2966SJianbo Liu struct mlx5dr_action { 9059dac2966SJianbo Liu enum mlx5dr_action_type action_type; 9069dac2966SJianbo Liu refcount_t refcount; 9079dac2966SJianbo Liu 9089dac2966SJianbo Liu union { 9099dac2966SJianbo Liu void *data; 9109dac2966SJianbo Liu struct mlx5dr_action_rewrite *rewrite; 9119dac2966SJianbo Liu struct mlx5dr_action_reformat *reformat; 9129dac2966SJianbo Liu struct mlx5dr_action_dest_tbl *dest_tbl; 9139dac2966SJianbo Liu struct mlx5dr_action_ctr *ctr; 9149dac2966SJianbo Liu struct mlx5dr_action_vport *vport; 9159dac2966SJianbo Liu struct mlx5dr_action_push_vlan *push_vlan; 9169dac2966SJianbo Liu struct mlx5dr_action_flow_tag *flow_tag; 9179dac2966SJianbo Liu }; 91814c32fd1SAlex Vesker }; 91914c32fd1SAlex Vesker 92014c32fd1SAlex Vesker enum mlx5dr_connect_type { 92114c32fd1SAlex Vesker CONNECT_HIT = 1, 92214c32fd1SAlex Vesker CONNECT_MISS = 2, 92314c32fd1SAlex Vesker }; 92414c32fd1SAlex Vesker 92514c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info { 92614c32fd1SAlex Vesker enum mlx5dr_connect_type type; 92714c32fd1SAlex Vesker union { 92814c32fd1SAlex Vesker struct mlx5dr_ste_htbl *hit_next_htbl; 92914c32fd1SAlex Vesker u64 miss_icm_addr; 93014c32fd1SAlex Vesker }; 93114c32fd1SAlex Vesker }; 93214c32fd1SAlex Vesker 93314c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx { 93414c32fd1SAlex Vesker struct list_head rule_members_list; 93514c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher; 93614c32fd1SAlex Vesker }; 93714c32fd1SAlex Vesker 93814c32fd1SAlex Vesker struct mlx5dr_rule { 93914c32fd1SAlex Vesker struct mlx5dr_matcher *matcher; 94014c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx rx; 94114c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx tx; 94214c32fd1SAlex Vesker struct list_head rule_actions_list; 94301723919SHamdan Igbaria u32 flow_source; 94414c32fd1SAlex Vesker }; 94514c32fd1SAlex Vesker 94614c32fd1SAlex Vesker void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste, 94714c32fd1SAlex Vesker struct mlx5dr_ste *ste); 94814c32fd1SAlex Vesker 94914c32fd1SAlex Vesker struct mlx5dr_icm_chunk { 950a00cd878SYevgeny Kliteynik struct mlx5dr_icm_buddy_mem *buddy_mem; 95114c32fd1SAlex Vesker struct list_head chunk_list; 95214c32fd1SAlex Vesker u32 rkey; 95314c32fd1SAlex Vesker u32 num_of_entries; 95414c32fd1SAlex Vesker u32 byte_size; 95514c32fd1SAlex Vesker u64 icm_addr; 95614c32fd1SAlex Vesker u64 mr_addr; 95714c32fd1SAlex Vesker 958a00cd878SYevgeny Kliteynik /* indicates the index of this chunk in the whole memory, 959a00cd878SYevgeny Kliteynik * used for deleting the chunk from the buddy 960a00cd878SYevgeny Kliteynik */ 961a00cd878SYevgeny Kliteynik unsigned int seg; 962a00cd878SYevgeny Kliteynik 96314c32fd1SAlex Vesker /* Memory optimisation */ 96414c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 96514c32fd1SAlex Vesker u8 *hw_ste_arr; 96614c32fd1SAlex Vesker struct list_head *miss_list; 96714c32fd1SAlex Vesker }; 96814c32fd1SAlex Vesker 969ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn) 970ed03a418SAlex Vesker { 971ed03a418SAlex Vesker mutex_lock(&nic_dmn->mutex); 972ed03a418SAlex Vesker } 973ed03a418SAlex Vesker 974ed03a418SAlex Vesker static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn) 975ed03a418SAlex Vesker { 976ed03a418SAlex Vesker mutex_unlock(&nic_dmn->mutex); 977ed03a418SAlex Vesker } 978ed03a418SAlex Vesker 979ed03a418SAlex Vesker static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn) 980ed03a418SAlex Vesker { 981ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.rx); 982ed03a418SAlex Vesker mlx5dr_domain_nic_lock(&dmn->info.tx); 983ed03a418SAlex Vesker } 984ed03a418SAlex Vesker 985ed03a418SAlex Vesker static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn) 986ed03a418SAlex Vesker { 987ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.tx); 988ed03a418SAlex Vesker mlx5dr_domain_nic_unlock(&dmn->info.rx); 989ed03a418SAlex Vesker } 990ed03a418SAlex Vesker 99114c32fd1SAlex Vesker int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 99214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 993667f2646SAlex Vesker enum mlx5dr_ipv outer_ipv, 994667f2646SAlex Vesker enum mlx5dr_ipv inner_ipv); 99514c32fd1SAlex Vesker 996a00cd878SYevgeny Kliteynik static inline int 997a00cd878SYevgeny Kliteynik mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type) 998a00cd878SYevgeny Kliteynik { 999a00cd878SYevgeny Kliteynik if (icm_type == DR_ICM_TYPE_STE) 1000a00cd878SYevgeny Kliteynik return DR_STE_SIZE; 1001a00cd878SYevgeny Kliteynik 1002a00cd878SYevgeny Kliteynik return DR_MODIFY_ACTION_SIZE; 1003a00cd878SYevgeny Kliteynik } 1004a00cd878SYevgeny Kliteynik 100514c32fd1SAlex Vesker static inline u32 100614c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 100714c32fd1SAlex Vesker { 100814c32fd1SAlex Vesker return 1 << chunk_size; 100914c32fd1SAlex Vesker } 101014c32fd1SAlex Vesker 101114c32fd1SAlex Vesker static inline int 101214c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 101314c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type) 101414c32fd1SAlex Vesker { 101514c32fd1SAlex Vesker int num_of_entries; 101614c32fd1SAlex Vesker int entry_size; 101714c32fd1SAlex Vesker 1018a00cd878SYevgeny Kliteynik entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type); 101914c32fd1SAlex Vesker num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 102014c32fd1SAlex Vesker 102114c32fd1SAlex Vesker return entry_size * num_of_entries; 102214c32fd1SAlex Vesker } 102314c32fd1SAlex Vesker 102414c32fd1SAlex Vesker static inline struct mlx5dr_cmd_vport_cap * 102514c32fd1SAlex Vesker mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport) 102614c32fd1SAlex Vesker { 102714c32fd1SAlex Vesker if (!caps->vports_caps || 102814c32fd1SAlex Vesker (vport >= caps->num_vports && vport != WIRE_PORT)) 102914c32fd1SAlex Vesker return NULL; 103014c32fd1SAlex Vesker 103114c32fd1SAlex Vesker if (vport == WIRE_PORT) 103214c32fd1SAlex Vesker vport = caps->num_vports; 103314c32fd1SAlex Vesker 103414c32fd1SAlex Vesker return &caps->vports_caps[vport]; 103514c32fd1SAlex Vesker } 103614c32fd1SAlex Vesker 103714c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details { 103814c32fd1SAlex Vesker u8 status; 103914c32fd1SAlex Vesker u8 level; 104014c32fd1SAlex Vesker u64 sw_owner_icm_root_1; 104114c32fd1SAlex Vesker u64 sw_owner_icm_root_0; 104214c32fd1SAlex Vesker }; 104314c32fd1SAlex Vesker 1044cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr { 1045cc78dbd7SAlex Vesker u32 table_type; 1046cc78dbd7SAlex Vesker u64 icm_addr_rx; 1047cc78dbd7SAlex Vesker u64 icm_addr_tx; 1048cc78dbd7SAlex Vesker u8 level; 1049cc78dbd7SAlex Vesker bool sw_owner; 1050cc78dbd7SAlex Vesker bool term_tbl; 1051cc78dbd7SAlex Vesker bool decap_en; 1052cc78dbd7SAlex Vesker bool reformat_en; 1053cc78dbd7SAlex Vesker }; 1054cc78dbd7SAlex Vesker 105514c32fd1SAlex Vesker /* internal API functions */ 105614c32fd1SAlex Vesker int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 105714c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps); 105814c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 105914c32fd1SAlex Vesker bool other_vport, u16 vport_number, 106014c32fd1SAlex Vesker u64 *icm_address_rx, 106114c32fd1SAlex Vesker u64 *icm_address_tx); 106214c32fd1SAlex Vesker int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 106314c32fd1SAlex Vesker bool other_vport, u16 vport_number, u16 *gvmi); 106414c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 106514c32fd1SAlex Vesker struct mlx5dr_esw_caps *caps); 106614c32fd1SAlex Vesker int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 106714c32fd1SAlex Vesker int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 106814c32fd1SAlex Vesker u32 table_type, 106914c32fd1SAlex Vesker u32 table_id, 107014c32fd1SAlex Vesker u32 group_id, 107114c32fd1SAlex Vesker u32 modify_header_id, 107214c32fd1SAlex Vesker u32 vport_id); 107314c32fd1SAlex Vesker int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 107414c32fd1SAlex Vesker u32 table_type, 107514c32fd1SAlex Vesker u32 table_id); 107614c32fd1SAlex Vesker int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 107714c32fd1SAlex Vesker u32 table_type, 107814c32fd1SAlex Vesker u8 num_of_actions, 107914c32fd1SAlex Vesker u64 *actions, 108014c32fd1SAlex Vesker u32 *modify_header_id); 108114c32fd1SAlex Vesker int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 108214c32fd1SAlex Vesker u32 modify_header_id); 108314c32fd1SAlex Vesker int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 108414c32fd1SAlex Vesker u32 table_type, 108514c32fd1SAlex Vesker u32 table_id, 108614c32fd1SAlex Vesker u32 *group_id); 108714c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 108814c32fd1SAlex Vesker u32 table_type, 108914c32fd1SAlex Vesker u32 table_id, 109014c32fd1SAlex Vesker u32 group_id); 109114c32fd1SAlex Vesker int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 1092cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr *attr, 109314c32fd1SAlex Vesker u64 *fdb_rx_icm_addr, 109414c32fd1SAlex Vesker u32 *table_id); 109514c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 109614c32fd1SAlex Vesker u32 table_id, 109714c32fd1SAlex Vesker u32 table_type); 109814c32fd1SAlex Vesker int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 109914c32fd1SAlex Vesker enum fs_flow_table_type type, 110014c32fd1SAlex Vesker u32 table_id, 110114c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details *output); 110214c32fd1SAlex Vesker int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 110314c32fd1SAlex Vesker enum mlx5_reformat_ctx_type rt, 110414c32fd1SAlex Vesker size_t reformat_size, 110514c32fd1SAlex Vesker void *reformat_data, 110614c32fd1SAlex Vesker u32 *reformat_id); 110714c32fd1SAlex Vesker void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 110814c32fd1SAlex Vesker u32 reformat_id); 110914c32fd1SAlex Vesker 111014c32fd1SAlex Vesker struct mlx5dr_cmd_gid_attr { 111114c32fd1SAlex Vesker u8 gid[16]; 111214c32fd1SAlex Vesker u8 mac[6]; 111314c32fd1SAlex Vesker u32 roce_ver; 111414c32fd1SAlex Vesker }; 111514c32fd1SAlex Vesker 111614c32fd1SAlex Vesker struct mlx5dr_cmd_qp_create_attr { 111714c32fd1SAlex Vesker u32 page_id; 111814c32fd1SAlex Vesker u32 pdn; 111914c32fd1SAlex Vesker u32 cqn; 112014c32fd1SAlex Vesker u32 pm_state; 112114c32fd1SAlex Vesker u32 service_type; 112214c32fd1SAlex Vesker u32 buff_umem_id; 112314c32fd1SAlex Vesker u32 db_umem_id; 112414c32fd1SAlex Vesker u32 sq_wqe_cnt; 112514c32fd1SAlex Vesker u32 rq_wqe_cnt; 112614c32fd1SAlex Vesker u32 rq_wqe_shift; 112714c32fd1SAlex Vesker }; 112814c32fd1SAlex Vesker 112914c32fd1SAlex Vesker int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 113014c32fd1SAlex Vesker u16 index, struct mlx5dr_cmd_gid_attr *attr); 113114c32fd1SAlex Vesker 113214c32fd1SAlex Vesker struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 113314c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type); 113414c32fd1SAlex Vesker void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 113514c32fd1SAlex Vesker 113614c32fd1SAlex Vesker struct mlx5dr_icm_chunk * 113714c32fd1SAlex Vesker mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 113814c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size); 113914c32fd1SAlex Vesker void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 11404fe45e1dSYevgeny Kliteynik 11414fe45e1dSYevgeny Kliteynik void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, 11424fe45e1dSYevgeny Kliteynik u8 *hw_ste_p, u32 ste_size); 114314c32fd1SAlex Vesker int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 114414c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 114514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 114614c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info, 114714c32fd1SAlex Vesker bool update_hw_ste); 11486b93b400SYevgeny Kliteynik void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, 11496b93b400SYevgeny Kliteynik u16 gvmi, 115014c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 115114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 115214c32fd1SAlex Vesker u8 *formatted_ste, 115314c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info); 115414c32fd1SAlex Vesker void mlx5dr_ste_copy_param(u8 match_criteria, 115514c32fd1SAlex Vesker struct mlx5dr_match_param *set_param, 115614c32fd1SAlex Vesker struct mlx5dr_match_parameters *mask); 115714c32fd1SAlex Vesker 115814c32fd1SAlex Vesker struct mlx5dr_qp { 115914c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 116014c32fd1SAlex Vesker struct mlx5_wq_qp wq; 116114c32fd1SAlex Vesker struct mlx5_uars_page *uar; 116214c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 1163f93f4f4fSLeon Romanovsky u32 qpn; 116414c32fd1SAlex Vesker struct { 116514c32fd1SAlex Vesker unsigned int pc; 116614c32fd1SAlex Vesker unsigned int cc; 116714c32fd1SAlex Vesker unsigned int size; 116814c32fd1SAlex Vesker unsigned int *wqe_head; 116914c32fd1SAlex Vesker unsigned int wqe_cnt; 117014c32fd1SAlex Vesker } sq; 117114c32fd1SAlex Vesker struct { 117214c32fd1SAlex Vesker unsigned int pc; 117314c32fd1SAlex Vesker unsigned int cc; 117414c32fd1SAlex Vesker unsigned int size; 117514c32fd1SAlex Vesker unsigned int wqe_cnt; 117614c32fd1SAlex Vesker } rq; 117714c32fd1SAlex Vesker int max_inline_data; 117814c32fd1SAlex Vesker }; 117914c32fd1SAlex Vesker 118014c32fd1SAlex Vesker struct mlx5dr_cq { 118114c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 118214c32fd1SAlex Vesker struct mlx5_cqwq wq; 118314c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 118414c32fd1SAlex Vesker struct mlx5_core_cq mcq; 118514c32fd1SAlex Vesker struct mlx5dr_qp *qp; 118614c32fd1SAlex Vesker }; 118714c32fd1SAlex Vesker 118814c32fd1SAlex Vesker struct mlx5dr_mr { 118914c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 119014c32fd1SAlex Vesker struct mlx5_core_mkey mkey; 119114c32fd1SAlex Vesker dma_addr_t dma_addr; 119214c32fd1SAlex Vesker void *addr; 119314c32fd1SAlex Vesker size_t size; 119414c32fd1SAlex Vesker }; 119514c32fd1SAlex Vesker 119614c32fd1SAlex Vesker #define MAX_SEND_CQE 64 119714c32fd1SAlex Vesker #define MIN_READ_SYNC 64 119814c32fd1SAlex Vesker 119914c32fd1SAlex Vesker struct mlx5dr_send_ring { 120014c32fd1SAlex Vesker struct mlx5dr_cq *cq; 120114c32fd1SAlex Vesker struct mlx5dr_qp *qp; 120214c32fd1SAlex Vesker struct mlx5dr_mr *mr; 120314c32fd1SAlex Vesker /* How much wqes are waiting for completion */ 120414c32fd1SAlex Vesker u32 pending_wqe; 120514c32fd1SAlex Vesker /* Signal request per this trash hold value */ 120614c32fd1SAlex Vesker u16 signal_th; 120714c32fd1SAlex Vesker /* Each post_send_size less than max_post_send_size */ 120814c32fd1SAlex Vesker u32 max_post_send_size; 120914c32fd1SAlex Vesker /* manage the send queue */ 121014c32fd1SAlex Vesker u32 tx_head; 121114c32fd1SAlex Vesker void *buf; 121214c32fd1SAlex Vesker u32 buf_size; 121314c32fd1SAlex Vesker struct ib_wc wc[MAX_SEND_CQE]; 121414c32fd1SAlex Vesker u8 sync_buff[MIN_READ_SYNC]; 121514c32fd1SAlex Vesker struct mlx5dr_mr *sync_mr; 1216cedb2819SAlex Vesker spinlock_t lock; /* Protect the data path of the send ring */ 121714c32fd1SAlex Vesker }; 121814c32fd1SAlex Vesker 121914c32fd1SAlex Vesker int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 122014c32fd1SAlex Vesker void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 122114c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring); 122214c32fd1SAlex Vesker int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 122314c32fd1SAlex Vesker int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 122414c32fd1SAlex Vesker struct mlx5dr_ste *ste, 122514c32fd1SAlex Vesker u8 *data, 122614c32fd1SAlex Vesker u16 size, 122714c32fd1SAlex Vesker u16 offset); 122814c32fd1SAlex Vesker int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 122914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 123014c32fd1SAlex Vesker u8 *formatted_ste, u8 *mask); 123114c32fd1SAlex Vesker int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 123214c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 123314c32fd1SAlex Vesker u8 *ste_init_data, 123414c32fd1SAlex Vesker bool update_hw_ste); 123514c32fd1SAlex Vesker int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 123614c32fd1SAlex Vesker struct mlx5dr_action *action); 123714c32fd1SAlex Vesker 12386de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info { 12396de03d2dSErez Shitrit u32 id; 12406de03d2dSErez Shitrit u16 vport; 12416de03d2dSErez Shitrit enum fs_flow_table_type type; 12426de03d2dSErez Shitrit }; 12436de03d2dSErez Shitrit 12446de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info { 12456de03d2dSErez Shitrit enum mlx5_flow_destination_type type; 12466de03d2dSErez Shitrit union { 12476de03d2dSErez Shitrit u32 tir_num; 12486de03d2dSErez Shitrit u32 ft_num; 12496de03d2dSErez Shitrit u32 ft_id; 12506de03d2dSErez Shitrit u32 counter_id; 12516de03d2dSErez Shitrit struct { 12526de03d2dSErez Shitrit u16 num; 12536de03d2dSErez Shitrit u16 vhca_id; 12546de03d2dSErez Shitrit u32 reformat_id; 12556de03d2dSErez Shitrit u8 flags; 12566de03d2dSErez Shitrit } vport; 12576de03d2dSErez Shitrit }; 12586de03d2dSErez Shitrit }; 12596de03d2dSErez Shitrit 12606de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info { 12616de03d2dSErez Shitrit u32 dests_size; 12626de03d2dSErez Shitrit u32 index; 12636de03d2dSErez Shitrit struct mlx5_flow_context flow_context; 12646de03d2dSErez Shitrit u32 *val; 12656de03d2dSErez Shitrit struct mlx5_flow_act action; 12666de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 12676de03d2dSErez Shitrit }; 12686de03d2dSErez Shitrit 12696de03d2dSErez Shitrit int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 12706de03d2dSErez Shitrit int opmod, int modify_mask, 12716de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info *ft, 12726de03d2dSErez Shitrit u32 group_id, 12736de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info *fte); 12746de03d2dSErez Shitrit 1275a283ea1bSYevgeny Kliteynik bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps); 1276a283ea1bSYevgeny Kliteynik 127714c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft { 127814c32fd1SAlex Vesker u64 rx_icm_addr; 127914c32fd1SAlex Vesker u32 table_id; 128014c32fd1SAlex Vesker u32 group_id; 128114c32fd1SAlex Vesker u32 modify_hdr_id; 128214c32fd1SAlex Vesker }; 128314c32fd1SAlex Vesker 128414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft * 128514c32fd1SAlex Vesker mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num); 128614c32fd1SAlex Vesker void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 128714c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 128814c32fd1SAlex Vesker int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 128914c32fd1SAlex Vesker u32 vport_num, 129014c32fd1SAlex Vesker u64 *rx_icm_addr); 129134583beeSErez Shitrit int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 129234583beeSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest, 129334583beeSErez Shitrit int num_dest, 129434583beeSErez Shitrit bool reformat_req, 129534583beeSErez Shitrit u32 *tbl_id, 129634583beeSErez Shitrit u32 *group_id); 129734583beeSErez Shitrit void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 129834583beeSErez Shitrit u32 group_id); 129914c32fd1SAlex Vesker #endif /* _DR_TYPES_H_ */ 1300