114c32fd1SAlex Vesker /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 214c32fd1SAlex Vesker /* Copyright (c) 2019, Mellanox Technologies */ 314c32fd1SAlex Vesker 414c32fd1SAlex Vesker #ifndef _DR_TYPES_ 514c32fd1SAlex Vesker #define _DR_TYPES_ 614c32fd1SAlex Vesker 714c32fd1SAlex Vesker #include <linux/mlx5/driver.h> 814c32fd1SAlex Vesker #include <linux/refcount.h> 914c32fd1SAlex Vesker #include "fs_core.h" 1014c32fd1SAlex Vesker #include "wq.h" 1114c32fd1SAlex Vesker #include "lib/mlx5.h" 1214c32fd1SAlex Vesker #include "mlx5_ifc_dr.h" 1314c32fd1SAlex Vesker #include "mlx5dr.h" 1414c32fd1SAlex Vesker 1514c32fd1SAlex Vesker #define DR_RULE_MAX_STES 17 1614c32fd1SAlex Vesker #define DR_ACTION_MAX_STES 5 1714c32fd1SAlex Vesker #define WIRE_PORT 0xFFFF 1814c32fd1SAlex Vesker #define DR_STE_SVLAN 0x1 1914c32fd1SAlex Vesker #define DR_STE_CVLAN 0x2 2014c32fd1SAlex Vesker 2114c32fd1SAlex Vesker #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) 2214c32fd1SAlex Vesker #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) 2314c32fd1SAlex Vesker #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) 2414c32fd1SAlex Vesker 2514c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size { 2614c32fd1SAlex Vesker DR_CHUNK_SIZE_1, 2714c32fd1SAlex Vesker DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */ 2814c32fd1SAlex Vesker DR_CHUNK_SIZE_2, 2914c32fd1SAlex Vesker DR_CHUNK_SIZE_4, 3014c32fd1SAlex Vesker DR_CHUNK_SIZE_8, 3114c32fd1SAlex Vesker DR_CHUNK_SIZE_16, 3214c32fd1SAlex Vesker DR_CHUNK_SIZE_32, 3314c32fd1SAlex Vesker DR_CHUNK_SIZE_64, 3414c32fd1SAlex Vesker DR_CHUNK_SIZE_128, 3514c32fd1SAlex Vesker DR_CHUNK_SIZE_256, 3614c32fd1SAlex Vesker DR_CHUNK_SIZE_512, 3714c32fd1SAlex Vesker DR_CHUNK_SIZE_1K, 3814c32fd1SAlex Vesker DR_CHUNK_SIZE_2K, 3914c32fd1SAlex Vesker DR_CHUNK_SIZE_4K, 4014c32fd1SAlex Vesker DR_CHUNK_SIZE_8K, 4114c32fd1SAlex Vesker DR_CHUNK_SIZE_16K, 4214c32fd1SAlex Vesker DR_CHUNK_SIZE_32K, 4314c32fd1SAlex Vesker DR_CHUNK_SIZE_64K, 4414c32fd1SAlex Vesker DR_CHUNK_SIZE_128K, 4514c32fd1SAlex Vesker DR_CHUNK_SIZE_256K, 4614c32fd1SAlex Vesker DR_CHUNK_SIZE_512K, 4714c32fd1SAlex Vesker DR_CHUNK_SIZE_1024K, 4814c32fd1SAlex Vesker DR_CHUNK_SIZE_2048K, 4914c32fd1SAlex Vesker DR_CHUNK_SIZE_MAX, 5014c32fd1SAlex Vesker }; 5114c32fd1SAlex Vesker 5214c32fd1SAlex Vesker enum mlx5dr_icm_type { 5314c32fd1SAlex Vesker DR_ICM_TYPE_STE, 5414c32fd1SAlex Vesker DR_ICM_TYPE_MODIFY_ACTION, 5514c32fd1SAlex Vesker }; 5614c32fd1SAlex Vesker 5714c32fd1SAlex Vesker static inline enum mlx5dr_icm_chunk_size 5814c32fd1SAlex Vesker mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk) 5914c32fd1SAlex Vesker { 6014c32fd1SAlex Vesker chunk += 2; 6114c32fd1SAlex Vesker if (chunk < DR_CHUNK_SIZE_MAX) 6214c32fd1SAlex Vesker return chunk; 6314c32fd1SAlex Vesker 6414c32fd1SAlex Vesker return DR_CHUNK_SIZE_MAX; 6514c32fd1SAlex Vesker } 6614c32fd1SAlex Vesker 6714c32fd1SAlex Vesker enum { 6814c32fd1SAlex Vesker DR_STE_SIZE = 64, 6914c32fd1SAlex Vesker DR_STE_SIZE_CTRL = 32, 7014c32fd1SAlex Vesker DR_STE_SIZE_TAG = 16, 7114c32fd1SAlex Vesker DR_STE_SIZE_MASK = 16, 7214c32fd1SAlex Vesker }; 7314c32fd1SAlex Vesker 7414c32fd1SAlex Vesker enum { 7514c32fd1SAlex Vesker DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK, 7614c32fd1SAlex Vesker }; 7714c32fd1SAlex Vesker 7814c32fd1SAlex Vesker enum { 7914c32fd1SAlex Vesker DR_MODIFY_ACTION_SIZE = 8, 8014c32fd1SAlex Vesker }; 8114c32fd1SAlex Vesker 8214c32fd1SAlex Vesker enum mlx5dr_matcher_criteria { 8314c32fd1SAlex Vesker DR_MATCHER_CRITERIA_EMPTY = 0, 8414c32fd1SAlex Vesker DR_MATCHER_CRITERIA_OUTER = 1 << 0, 8514c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC = 1 << 1, 8614c32fd1SAlex Vesker DR_MATCHER_CRITERIA_INNER = 1 << 2, 8714c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC2 = 1 << 3, 8814c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MISC3 = 1 << 4, 8914c32fd1SAlex Vesker DR_MATCHER_CRITERIA_MAX = 1 << 5, 9014c32fd1SAlex Vesker }; 9114c32fd1SAlex Vesker 9214c32fd1SAlex Vesker enum mlx5dr_action_type { 9314c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L2_TO_L2, 9414c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L2, 9514c32fd1SAlex Vesker DR_ACTION_TYP_TNL_L3_TO_L2, 9614c32fd1SAlex Vesker DR_ACTION_TYP_L2_TO_TNL_L3, 9714c32fd1SAlex Vesker DR_ACTION_TYP_DROP, 9814c32fd1SAlex Vesker DR_ACTION_TYP_QP, 9914c32fd1SAlex Vesker DR_ACTION_TYP_FT, 10014c32fd1SAlex Vesker DR_ACTION_TYP_CTR, 10114c32fd1SAlex Vesker DR_ACTION_TYP_TAG, 10214c32fd1SAlex Vesker DR_ACTION_TYP_MODIFY_HDR, 10314c32fd1SAlex Vesker DR_ACTION_TYP_VPORT, 10414c32fd1SAlex Vesker DR_ACTION_TYP_POP_VLAN, 10514c32fd1SAlex Vesker DR_ACTION_TYP_PUSH_VLAN, 10614c32fd1SAlex Vesker DR_ACTION_TYP_MAX, 10714c32fd1SAlex Vesker }; 10814c32fd1SAlex Vesker 109667f2646SAlex Vesker enum mlx5dr_ipv { 110667f2646SAlex Vesker DR_RULE_IPV4, 111667f2646SAlex Vesker DR_RULE_IPV6, 112667f2646SAlex Vesker DR_RULE_IPV_MAX, 113667f2646SAlex Vesker }; 114667f2646SAlex Vesker 11514c32fd1SAlex Vesker struct mlx5dr_icm_pool; 11614c32fd1SAlex Vesker struct mlx5dr_icm_chunk; 11714c32fd1SAlex Vesker struct mlx5dr_icm_bucket; 11814c32fd1SAlex Vesker struct mlx5dr_ste_htbl; 11914c32fd1SAlex Vesker struct mlx5dr_match_param; 12014c32fd1SAlex Vesker struct mlx5dr_cmd_caps; 12114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx; 12214c32fd1SAlex Vesker 12314c32fd1SAlex Vesker struct mlx5dr_ste { 12414c32fd1SAlex Vesker u8 *hw_ste; 12514c32fd1SAlex Vesker /* refcount: indicates the num of rules that using this ste */ 12614c32fd1SAlex Vesker refcount_t refcount; 12714c32fd1SAlex Vesker 12814c32fd1SAlex Vesker /* attached to the miss_list head at each htbl entry */ 12914c32fd1SAlex Vesker struct list_head miss_list_node; 13014c32fd1SAlex Vesker 13114c32fd1SAlex Vesker /* each rule member that uses this ste attached here */ 13214c32fd1SAlex Vesker struct list_head rule_list; 13314c32fd1SAlex Vesker 13414c32fd1SAlex Vesker /* this ste is member of htbl */ 13514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl; 13614c32fd1SAlex Vesker 13714c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl; 13814c32fd1SAlex Vesker 13914c32fd1SAlex Vesker /* this ste is part of a rule, located in ste's chain */ 14014c32fd1SAlex Vesker u8 ste_chain_location; 14114c32fd1SAlex Vesker }; 14214c32fd1SAlex Vesker 14314c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl { 14414c32fd1SAlex Vesker /* total number of valid entries belonging to this hash table. This 14514c32fd1SAlex Vesker * includes the non collision and collision entries 14614c32fd1SAlex Vesker */ 14714c32fd1SAlex Vesker unsigned int num_of_valid_entries; 14814c32fd1SAlex Vesker 14914c32fd1SAlex Vesker /* total number of collisions entries attached to this table */ 15014c32fd1SAlex Vesker unsigned int num_of_collisions; 15114c32fd1SAlex Vesker unsigned int increase_threshold; 15214c32fd1SAlex Vesker u8 may_grow:1; 15314c32fd1SAlex Vesker }; 15414c32fd1SAlex Vesker 15514c32fd1SAlex Vesker struct mlx5dr_ste_htbl { 15614c32fd1SAlex Vesker u8 lu_type; 15714c32fd1SAlex Vesker u16 byte_mask; 15814c32fd1SAlex Vesker refcount_t refcount; 15914c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 16014c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 16114c32fd1SAlex Vesker u8 *hw_ste_arr; 16214c32fd1SAlex Vesker 16314c32fd1SAlex Vesker struct list_head *miss_list; 16414c32fd1SAlex Vesker 16514c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size; 16614c32fd1SAlex Vesker struct mlx5dr_ste *pointing_ste; 16714c32fd1SAlex Vesker 16814c32fd1SAlex Vesker struct mlx5dr_ste_htbl_ctrl ctrl; 16914c32fd1SAlex Vesker }; 17014c32fd1SAlex Vesker 17114c32fd1SAlex Vesker struct mlx5dr_ste_send_info { 17214c32fd1SAlex Vesker struct mlx5dr_ste *ste; 17314c32fd1SAlex Vesker struct list_head send_list; 17414c32fd1SAlex Vesker u16 size; 17514c32fd1SAlex Vesker u16 offset; 17614c32fd1SAlex Vesker u8 data_cont[DR_STE_SIZE]; 17714c32fd1SAlex Vesker u8 *data; 17814c32fd1SAlex Vesker }; 17914c32fd1SAlex Vesker 18014c32fd1SAlex Vesker void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size, 18114c32fd1SAlex Vesker u16 offset, u8 *data, 18214c32fd1SAlex Vesker struct mlx5dr_ste_send_info *ste_info, 18314c32fd1SAlex Vesker struct list_head *send_list, 18414c32fd1SAlex Vesker bool copy_data); 18514c32fd1SAlex Vesker 18614c32fd1SAlex Vesker struct mlx5dr_ste_build { 18714c32fd1SAlex Vesker u8 inner:1; 18814c32fd1SAlex Vesker u8 rx:1; 189640bdb1fSAlaa Hleihel u8 vhca_id_valid:1; 190640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn; 19114c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps; 19214c32fd1SAlex Vesker u8 lu_type; 19314c32fd1SAlex Vesker u16 byte_mask; 19414c32fd1SAlex Vesker u8 bit_mask[DR_STE_SIZE_MASK]; 19514c32fd1SAlex Vesker int (*ste_build_tag_func)(struct mlx5dr_match_param *spec, 19614c32fd1SAlex Vesker struct mlx5dr_ste_build *sb, 19714c32fd1SAlex Vesker u8 *hw_ste_p); 19814c32fd1SAlex Vesker }; 19914c32fd1SAlex Vesker 20014c32fd1SAlex Vesker struct mlx5dr_ste_htbl * 20114c32fd1SAlex Vesker mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool, 20214c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size, 20314c32fd1SAlex Vesker u8 lu_type, u16 byte_mask); 20414c32fd1SAlex Vesker 20514c32fd1SAlex Vesker int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl); 20614c32fd1SAlex Vesker 20714c32fd1SAlex Vesker static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl) 20814c32fd1SAlex Vesker { 20914c32fd1SAlex Vesker if (refcount_dec_and_test(&htbl->refcount)) 21014c32fd1SAlex Vesker mlx5dr_ste_htbl_free(htbl); 21114c32fd1SAlex Vesker } 21214c32fd1SAlex Vesker 21314c32fd1SAlex Vesker static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl) 21414c32fd1SAlex Vesker { 21514c32fd1SAlex Vesker refcount_inc(&htbl->refcount); 21614c32fd1SAlex Vesker } 21714c32fd1SAlex Vesker 21814c32fd1SAlex Vesker /* STE utils */ 21914c32fd1SAlex Vesker u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl); 22014c32fd1SAlex Vesker void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type, u16 gvmi); 22114c32fd1SAlex Vesker void mlx5dr_ste_always_hit_htbl(struct mlx5dr_ste *ste, 22214c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl); 22314c32fd1SAlex Vesker void mlx5dr_ste_set_miss_addr(u8 *hw_ste, u64 miss_addr); 22414c32fd1SAlex Vesker u64 mlx5dr_ste_get_miss_addr(u8 *hw_ste); 22514c32fd1SAlex Vesker void mlx5dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi); 22614c32fd1SAlex Vesker void mlx5dr_ste_set_hit_addr(u8 *hw_ste, u64 icm_addr, u32 ht_size); 22714c32fd1SAlex Vesker void mlx5dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr); 22814c32fd1SAlex Vesker void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask); 22914c32fd1SAlex Vesker bool mlx5dr_ste_not_used_ste(struct mlx5dr_ste *ste); 23014c32fd1SAlex Vesker bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher, 23114c32fd1SAlex Vesker u8 ste_location); 23214c32fd1SAlex Vesker void mlx5dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag); 23314c32fd1SAlex Vesker void mlx5dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id); 23414c32fd1SAlex Vesker void mlx5dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id, 23514c32fd1SAlex Vesker int size, bool encap_l3); 23614c32fd1SAlex Vesker void mlx5dr_ste_set_rx_decap(u8 *hw_ste_p); 23714c32fd1SAlex Vesker void mlx5dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan); 23814c32fd1SAlex Vesker void mlx5dr_ste_set_rx_pop_vlan(u8 *hw_ste_p); 23914c32fd1SAlex Vesker void mlx5dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_tpid_pcp_dei_vid, 24014c32fd1SAlex Vesker bool go_back); 24114c32fd1SAlex Vesker void mlx5dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type); 24214c32fd1SAlex Vesker u8 mlx5dr_ste_get_entry_type(u8 *hw_ste_p); 24314c32fd1SAlex Vesker void mlx5dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, 24414c32fd1SAlex Vesker u32 re_write_index); 24514c32fd1SAlex Vesker void mlx5dr_ste_set_go_back_bit(u8 *hw_ste_p); 24614c32fd1SAlex Vesker u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste); 24714c32fd1SAlex Vesker u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste); 24814c32fd1SAlex Vesker struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste); 24914c32fd1SAlex Vesker 25014c32fd1SAlex Vesker void mlx5dr_ste_free(struct mlx5dr_ste *ste, 25114c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 25214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher); 25314c32fd1SAlex Vesker static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste, 25414c32fd1SAlex Vesker struct mlx5dr_matcher *matcher, 25514c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher) 25614c32fd1SAlex Vesker { 25714c32fd1SAlex Vesker if (refcount_dec_and_test(&ste->refcount)) 25814c32fd1SAlex Vesker mlx5dr_ste_free(ste, matcher, nic_matcher); 25914c32fd1SAlex Vesker } 26014c32fd1SAlex Vesker 26114c32fd1SAlex Vesker /* initial as 0, increased only when ste appears in a new rule */ 26214c32fd1SAlex Vesker static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste) 26314c32fd1SAlex Vesker { 26414c32fd1SAlex Vesker refcount_inc(&ste->refcount); 26514c32fd1SAlex Vesker } 26614c32fd1SAlex Vesker 26714c32fd1SAlex Vesker void mlx5dr_ste_set_hit_addr_by_next_htbl(u8 *hw_ste, 26814c32fd1SAlex Vesker struct mlx5dr_ste_htbl *next_htbl); 26914c32fd1SAlex Vesker bool mlx5dr_ste_equal_tag(void *src, void *dst); 27014c32fd1SAlex Vesker int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher, 27114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 27214c32fd1SAlex Vesker struct mlx5dr_ste *ste, 27314c32fd1SAlex Vesker u8 *cur_hw_ste, 27414c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size log_table_size); 27514c32fd1SAlex Vesker 27614c32fd1SAlex Vesker /* STE build functions */ 27714c32fd1SAlex Vesker int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn, 27814c32fd1SAlex Vesker u8 match_criteria, 27914c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 28014c32fd1SAlex Vesker struct mlx5dr_match_param *value); 28114c32fd1SAlex Vesker int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher, 28214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 28314c32fd1SAlex Vesker struct mlx5dr_match_param *value, 28414c32fd1SAlex Vesker u8 *ste_arr); 28514c32fd1SAlex Vesker int mlx5dr_ste_build_eth_l2_src_des(struct mlx5dr_ste_build *builder, 28614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 28714c32fd1SAlex Vesker bool inner, bool rx); 28814c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_build *sb, 28914c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 29014c32fd1SAlex Vesker bool inner, bool rx); 29114c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_build *sb, 29214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 29314c32fd1SAlex Vesker bool inner, bool rx); 29414c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_build *sb, 29514c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 29614c32fd1SAlex Vesker bool inner, bool rx); 29714c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_build *sb, 29814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 29914c32fd1SAlex Vesker bool inner, bool rx); 30014c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_build *sb, 30114c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 30214c32fd1SAlex Vesker bool inner, bool rx); 30314c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_build *sb, 30414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 30514c32fd1SAlex Vesker bool inner, bool rx); 30614c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_build *sb, 30714c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 30814c32fd1SAlex Vesker bool inner, bool rx); 30914c32fd1SAlex Vesker void mlx5dr_ste_build_ipv6_l3_l4(struct mlx5dr_ste_build *sb, 31014c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 31114c32fd1SAlex Vesker bool inner, bool rx); 31214c32fd1SAlex Vesker void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_build *sb, 31314c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 31414c32fd1SAlex Vesker bool inner, bool rx); 31514c32fd1SAlex Vesker void mlx5dr_ste_build_gre(struct mlx5dr_ste_build *sb, 31614c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 31714c32fd1SAlex Vesker bool inner, bool rx); 31814c32fd1SAlex Vesker void mlx5dr_ste_build_mpls(struct mlx5dr_ste_build *sb, 31914c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 32014c32fd1SAlex Vesker bool inner, bool rx); 32114c32fd1SAlex Vesker void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_build *sb, 32214c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 32314c32fd1SAlex Vesker bool inner, bool rx); 32414c32fd1SAlex Vesker int mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_build *sb, 32514c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 32614c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps, 32714c32fd1SAlex Vesker bool inner, bool rx); 3286e9e286eSYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_tnl_vxlan_gpe(struct mlx5dr_ste_build *sb, 32914c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 33014c32fd1SAlex Vesker bool inner, bool rx); 331b6d12238SYevgeny Kliteynik void mlx5dr_ste_build_flex_parser_tnl_geneve(struct mlx5dr_ste_build *sb, 332b6d12238SYevgeny Kliteynik struct mlx5dr_match_param *mask, 333b6d12238SYevgeny Kliteynik bool inner, bool rx); 33414c32fd1SAlex Vesker void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_build *sb, 33514c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 33614c32fd1SAlex Vesker bool inner, bool rx); 33714c32fd1SAlex Vesker void mlx5dr_ste_build_register_0(struct mlx5dr_ste_build *sb, 33814c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 33914c32fd1SAlex Vesker bool inner, bool rx); 34014c32fd1SAlex Vesker void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb, 34114c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 34214c32fd1SAlex Vesker bool inner, bool rx); 34314c32fd1SAlex Vesker int mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb, 34414c32fd1SAlex Vesker struct mlx5dr_match_param *mask, 345640bdb1fSAlaa Hleihel struct mlx5dr_domain *dmn, 34614c32fd1SAlex Vesker bool inner, bool rx); 34714c32fd1SAlex Vesker void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx); 34814c32fd1SAlex Vesker 34914c32fd1SAlex Vesker /* Actions utils */ 35014c32fd1SAlex Vesker int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 35114c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 35214c32fd1SAlex Vesker struct mlx5dr_action *actions[], 35314c32fd1SAlex Vesker u32 num_actions, 35414c32fd1SAlex Vesker u8 *ste_arr, 35514c32fd1SAlex Vesker u32 *new_hw_ste_arr_sz); 35614c32fd1SAlex Vesker 35714c32fd1SAlex Vesker struct mlx5dr_match_spec { 35814c32fd1SAlex Vesker u32 smac_47_16; /* Source MAC address of incoming packet */ 35914c32fd1SAlex Vesker /* Incoming packet Ethertype - this is the Ethertype 36014c32fd1SAlex Vesker * following the last VLAN tag of the packet 36114c32fd1SAlex Vesker */ 36214c32fd1SAlex Vesker u32 ethertype:16; 36314c32fd1SAlex Vesker u32 smac_15_0:16; /* Source MAC address of incoming packet */ 36414c32fd1SAlex Vesker u32 dmac_47_16; /* Destination MAC address of incoming packet */ 36514c32fd1SAlex Vesker /* VLAN ID of first VLAN tag in the incoming packet. 36614c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 36714c32fd1SAlex Vesker */ 36814c32fd1SAlex Vesker u32 first_vid:12; 36914c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the incoming packet. 37014c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 37114c32fd1SAlex Vesker */ 37214c32fd1SAlex Vesker u32 first_cfi:1; 37314c32fd1SAlex Vesker /* Priority of first VLAN tag in the incoming packet. 37414c32fd1SAlex Vesker * Valid only when cvlan_tag==1 or svlan_tag==1 37514c32fd1SAlex Vesker */ 37614c32fd1SAlex Vesker u32 first_prio:3; 37714c32fd1SAlex Vesker u32 dmac_15_0:16; /* Destination MAC address of incoming packet */ 37814c32fd1SAlex Vesker /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK; 37914c32fd1SAlex Vesker * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS 38014c32fd1SAlex Vesker */ 38114c32fd1SAlex Vesker u32 tcp_flags:9; 38214c32fd1SAlex Vesker u32 ip_version:4; /* IP version */ 38314c32fd1SAlex Vesker u32 frag:1; /* Packet is an IP fragment */ 38414c32fd1SAlex Vesker /* The first vlan in the packet is s-vlan (0x8a88). 38514c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 38614c32fd1SAlex Vesker */ 38714c32fd1SAlex Vesker u32 svlan_tag:1; 38814c32fd1SAlex Vesker /* The first vlan in the packet is c-vlan (0x8100). 38914c32fd1SAlex Vesker * cvlan_tag and svlan_tag cannot be set together 39014c32fd1SAlex Vesker */ 39114c32fd1SAlex Vesker u32 cvlan_tag:1; 39214c32fd1SAlex Vesker /* Explicit Congestion Notification derived from 39314c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 39414c32fd1SAlex Vesker */ 39514c32fd1SAlex Vesker u32 ip_ecn:2; 39614c32fd1SAlex Vesker /* Differentiated Services Code Point derived from 39714c32fd1SAlex Vesker * Traffic Class/TOS field of IPv6/v4 39814c32fd1SAlex Vesker */ 39914c32fd1SAlex Vesker u32 ip_dscp:6; 40014c32fd1SAlex Vesker u32 ip_protocol:8; /* IP protocol */ 40114c32fd1SAlex Vesker /* TCP destination port. 40214c32fd1SAlex Vesker * tcp and udp sport/dport are mutually exclusive 40314c32fd1SAlex Vesker */ 40414c32fd1SAlex Vesker u32 tcp_dport:16; 40514c32fd1SAlex Vesker /* TCP source port.;tcp and udp sport/dport are mutually exclusive */ 40614c32fd1SAlex Vesker u32 tcp_sport:16; 40714c32fd1SAlex Vesker u32 ttl_hoplimit:8; 40814c32fd1SAlex Vesker u32 reserved:24; 40914c32fd1SAlex Vesker /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */ 41014c32fd1SAlex Vesker u32 udp_dport:16; 41114c32fd1SAlex Vesker /* UDP source port.;tcp and udp sport/dport are mutually exclusive */ 41214c32fd1SAlex Vesker u32 udp_sport:16; 41314c32fd1SAlex Vesker /* IPv6 source address of incoming packets 41414c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 41514c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 41614c32fd1SAlex Vesker */ 41714c32fd1SAlex Vesker u32 src_ip_127_96; 41814c32fd1SAlex Vesker /* IPv6 source address of incoming packets 41914c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 42014c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 42114c32fd1SAlex Vesker */ 42214c32fd1SAlex Vesker u32 src_ip_95_64; 42314c32fd1SAlex Vesker /* IPv6 source address of incoming packets 42414c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 42514c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 42614c32fd1SAlex Vesker */ 42714c32fd1SAlex Vesker u32 src_ip_63_32; 42814c32fd1SAlex Vesker /* IPv6 source address of incoming packets 42914c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 43014c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 43114c32fd1SAlex Vesker */ 43214c32fd1SAlex Vesker u32 src_ip_31_0; 43314c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 43414c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 43514c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 43614c32fd1SAlex Vesker */ 43714c32fd1SAlex Vesker u32 dst_ip_127_96; 43814c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 43914c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 44014c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 44114c32fd1SAlex Vesker */ 44214c32fd1SAlex Vesker u32 dst_ip_95_64; 44314c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 44414c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 44514c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 44614c32fd1SAlex Vesker */ 44714c32fd1SAlex Vesker u32 dst_ip_63_32; 44814c32fd1SAlex Vesker /* IPv6 destination address of incoming packets 44914c32fd1SAlex Vesker * For IPv4 address use bits 31:0 (rest of the bits are reserved) 45014c32fd1SAlex Vesker * This field should be qualified by an appropriate ethertype 45114c32fd1SAlex Vesker */ 45214c32fd1SAlex Vesker u32 dst_ip_31_0; 45314c32fd1SAlex Vesker }; 45414c32fd1SAlex Vesker 45514c32fd1SAlex Vesker struct mlx5dr_match_misc { 45614c32fd1SAlex Vesker u32 source_sqn:24; /* Source SQN */ 45714c32fd1SAlex Vesker u32 source_vhca_port:4; 45814c32fd1SAlex Vesker /* used with GRE, sequence number exist when gre_s_present == 1 */ 45914c32fd1SAlex Vesker u32 gre_s_present:1; 46014c32fd1SAlex Vesker /* used with GRE, key exist when gre_k_present == 1 */ 46114c32fd1SAlex Vesker u32 gre_k_present:1; 46214c32fd1SAlex Vesker u32 reserved_auto1:1; 46314c32fd1SAlex Vesker /* used with GRE, checksum exist when gre_c_present == 1 */ 46414c32fd1SAlex Vesker u32 gre_c_present:1; 46514c32fd1SAlex Vesker /* Source port.;0xffff determines wire port */ 46614c32fd1SAlex Vesker u32 source_port:16; 467640bdb1fSAlaa Hleihel u32 source_eswitch_owner_vhca_id:16; 46814c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the inner header of the incoming packet. 46914c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 47014c32fd1SAlex Vesker */ 47114c32fd1SAlex Vesker u32 inner_second_vid:12; 47214c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the inner header of the incoming packet. 47314c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 47414c32fd1SAlex Vesker */ 47514c32fd1SAlex Vesker u32 inner_second_cfi:1; 47614c32fd1SAlex Vesker /* Priority of second VLAN tag in the inner header of the incoming packet. 47714c32fd1SAlex Vesker * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1 47814c32fd1SAlex Vesker */ 47914c32fd1SAlex Vesker u32 inner_second_prio:3; 48014c32fd1SAlex Vesker /* VLAN ID of first VLAN tag the outer header of the incoming packet. 48114c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 48214c32fd1SAlex Vesker */ 48314c32fd1SAlex Vesker u32 outer_second_vid:12; 48414c32fd1SAlex Vesker /* CFI bit of first VLAN tag in the outer header of the incoming packet. 48514c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 48614c32fd1SAlex Vesker */ 48714c32fd1SAlex Vesker u32 outer_second_cfi:1; 48814c32fd1SAlex Vesker /* Priority of second VLAN tag in the outer header of the incoming packet. 48914c32fd1SAlex Vesker * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1 49014c32fd1SAlex Vesker */ 49114c32fd1SAlex Vesker u32 outer_second_prio:3; 49214c32fd1SAlex Vesker u32 gre_protocol:16; /* GRE Protocol (outer) */ 49314c32fd1SAlex Vesker u32 reserved_auto3:12; 49414c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is s-vlan (0x8a88). 49514c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 49614c32fd1SAlex Vesker */ 49714c32fd1SAlex Vesker u32 inner_second_svlan_tag:1; 49814c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is s-vlan (0x8a88). 49914c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 50014c32fd1SAlex Vesker */ 50114c32fd1SAlex Vesker u32 outer_second_svlan_tag:1; 50214c32fd1SAlex Vesker /* The second vlan in the inner header of the packet is c-vlan (0x8100). 50314c32fd1SAlex Vesker * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together 50414c32fd1SAlex Vesker */ 50514c32fd1SAlex Vesker u32 inner_second_cvlan_tag:1; 50614c32fd1SAlex Vesker /* The second vlan in the outer header of the packet is c-vlan (0x8100). 50714c32fd1SAlex Vesker * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together 50814c32fd1SAlex Vesker */ 50914c32fd1SAlex Vesker u32 outer_second_cvlan_tag:1; 51014c32fd1SAlex Vesker u32 gre_key_l:8; /* GRE Key [7:0] (outer) */ 51114c32fd1SAlex Vesker u32 gre_key_h:24; /* GRE Key[31:8] (outer) */ 51214c32fd1SAlex Vesker u32 reserved_auto4:8; 51314c32fd1SAlex Vesker u32 vxlan_vni:24; /* VXLAN VNI (outer) */ 51414c32fd1SAlex Vesker u32 geneve_oam:1; /* GENEVE OAM field (outer) */ 51514c32fd1SAlex Vesker u32 reserved_auto5:7; 51614c32fd1SAlex Vesker u32 geneve_vni:24; /* GENEVE VNI field (outer) */ 51714c32fd1SAlex Vesker u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */ 51814c32fd1SAlex Vesker u32 reserved_auto6:12; 51914c32fd1SAlex Vesker u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */ 52014c32fd1SAlex Vesker u32 reserved_auto7:12; 52114c32fd1SAlex Vesker u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */ 52214c32fd1SAlex Vesker u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */ 52314c32fd1SAlex Vesker u32 reserved_auto8:10; 52414c32fd1SAlex Vesker u32 bth_dst_qp:24; /* Destination QP in BTH header */ 52514c32fd1SAlex Vesker u32 reserved_auto9:8; 52614c32fd1SAlex Vesker u8 reserved_auto10[20]; 52714c32fd1SAlex Vesker }; 52814c32fd1SAlex Vesker 52914c32fd1SAlex Vesker struct mlx5dr_match_misc2 { 53014c32fd1SAlex Vesker u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */ 53114c32fd1SAlex Vesker u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */ 53214c32fd1SAlex Vesker u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */ 53314c32fd1SAlex Vesker u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */ 53414c32fd1SAlex Vesker u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */ 53514c32fd1SAlex Vesker u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */ 53614c32fd1SAlex Vesker u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */ 53714c32fd1SAlex Vesker u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */ 53814c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */ 53914c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */ 54014c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */ 54114c32fd1SAlex Vesker u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */ 54214c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */ 54314c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */ 54414c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */ 54514c32fd1SAlex Vesker u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */ 54614c32fd1SAlex Vesker u32 metadata_reg_c_7; /* metadata_reg_c_7 */ 54714c32fd1SAlex Vesker u32 metadata_reg_c_6; /* metadata_reg_c_6 */ 54814c32fd1SAlex Vesker u32 metadata_reg_c_5; /* metadata_reg_c_5 */ 54914c32fd1SAlex Vesker u32 metadata_reg_c_4; /* metadata_reg_c_4 */ 55014c32fd1SAlex Vesker u32 metadata_reg_c_3; /* metadata_reg_c_3 */ 55114c32fd1SAlex Vesker u32 metadata_reg_c_2; /* metadata_reg_c_2 */ 55214c32fd1SAlex Vesker u32 metadata_reg_c_1; /* metadata_reg_c_1 */ 55314c32fd1SAlex Vesker u32 metadata_reg_c_0; /* metadata_reg_c_0 */ 55414c32fd1SAlex Vesker u32 metadata_reg_a; /* metadata_reg_a */ 55514c32fd1SAlex Vesker u32 metadata_reg_b; /* metadata_reg_b */ 55614c32fd1SAlex Vesker u8 reserved_auto2[8]; 55714c32fd1SAlex Vesker }; 55814c32fd1SAlex Vesker 55914c32fd1SAlex Vesker struct mlx5dr_match_misc3 { 56014c32fd1SAlex Vesker u32 inner_tcp_seq_num; 56114c32fd1SAlex Vesker u32 outer_tcp_seq_num; 56214c32fd1SAlex Vesker u32 inner_tcp_ack_num; 56314c32fd1SAlex Vesker u32 outer_tcp_ack_num; 56414c32fd1SAlex Vesker u32 outer_vxlan_gpe_vni:24; 56514c32fd1SAlex Vesker u32 reserved_auto1:8; 56614c32fd1SAlex Vesker u32 reserved_auto2:16; 56714c32fd1SAlex Vesker u32 outer_vxlan_gpe_flags:8; 56814c32fd1SAlex Vesker u32 outer_vxlan_gpe_next_protocol:8; 56914c32fd1SAlex Vesker u32 icmpv4_header_data; 57014c32fd1SAlex Vesker u32 icmpv6_header_data; 57114c32fd1SAlex Vesker u32 icmpv6_code:8; 57214c32fd1SAlex Vesker u32 icmpv6_type:8; 57314c32fd1SAlex Vesker u32 icmpv4_code:8; 57414c32fd1SAlex Vesker u32 icmpv4_type:8; 57514c32fd1SAlex Vesker u8 reserved_auto3[0x1c]; 57614c32fd1SAlex Vesker }; 57714c32fd1SAlex Vesker 57814c32fd1SAlex Vesker struct mlx5dr_match_param { 57914c32fd1SAlex Vesker struct mlx5dr_match_spec outer; 58014c32fd1SAlex Vesker struct mlx5dr_match_misc misc; 58114c32fd1SAlex Vesker struct mlx5dr_match_spec inner; 58214c32fd1SAlex Vesker struct mlx5dr_match_misc2 misc2; 58314c32fd1SAlex Vesker struct mlx5dr_match_misc3 misc3; 58414c32fd1SAlex Vesker }; 58514c32fd1SAlex Vesker 58614c32fd1SAlex Vesker #define DR_MASK_IS_FLEX_PARSER_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \ 58714c32fd1SAlex Vesker (_misc3)->icmpv4_code || \ 58814c32fd1SAlex Vesker (_misc3)->icmpv4_header_data) 58914c32fd1SAlex Vesker 59014c32fd1SAlex Vesker struct mlx5dr_esw_caps { 59114c32fd1SAlex Vesker u64 drop_icm_address_rx; 59214c32fd1SAlex Vesker u64 drop_icm_address_tx; 59314c32fd1SAlex Vesker u64 uplink_icm_address_rx; 59414c32fd1SAlex Vesker u64 uplink_icm_address_tx; 59514c32fd1SAlex Vesker bool sw_owner; 59614c32fd1SAlex Vesker }; 59714c32fd1SAlex Vesker 59814c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap { 59914c32fd1SAlex Vesker u16 vport_gvmi; 60014c32fd1SAlex Vesker u16 vhca_gvmi; 60114c32fd1SAlex Vesker u64 icm_address_rx; 60214c32fd1SAlex Vesker u64 icm_address_tx; 60314c32fd1SAlex Vesker u32 num; 60414c32fd1SAlex Vesker }; 60514c32fd1SAlex Vesker 60614c32fd1SAlex Vesker struct mlx5dr_cmd_caps { 60714c32fd1SAlex Vesker u16 gvmi; 60814c32fd1SAlex Vesker u64 nic_rx_drop_address; 60914c32fd1SAlex Vesker u64 nic_tx_drop_address; 61014c32fd1SAlex Vesker u64 nic_tx_allow_address; 61114c32fd1SAlex Vesker u64 esw_rx_drop_address; 61214c32fd1SAlex Vesker u64 esw_tx_drop_address; 61314c32fd1SAlex Vesker u32 log_icm_size; 61414c32fd1SAlex Vesker u64 hdr_modify_icm_addr; 61514c32fd1SAlex Vesker u32 flex_protocols; 61614c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw0; 61714c32fd1SAlex Vesker u8 flex_parser_id_icmp_dw1; 61814c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw0; 61914c32fd1SAlex Vesker u8 flex_parser_id_icmpv6_dw1; 62014c32fd1SAlex Vesker u8 max_ft_level; 62114c32fd1SAlex Vesker u16 roce_min_src_udp; 62214c32fd1SAlex Vesker u8 num_esw_ports; 62314c32fd1SAlex Vesker bool eswitch_manager; 62414c32fd1SAlex Vesker bool rx_sw_owner; 62514c32fd1SAlex Vesker bool tx_sw_owner; 62614c32fd1SAlex Vesker bool fdb_sw_owner; 62714c32fd1SAlex Vesker u32 num_vports; 62814c32fd1SAlex Vesker struct mlx5dr_esw_caps esw_caps; 62914c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *vports_caps; 63014c32fd1SAlex Vesker bool prio_tag_required; 63114c32fd1SAlex Vesker }; 63214c32fd1SAlex Vesker 63314c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx { 63414c32fd1SAlex Vesker u64 drop_icm_addr; 63514c32fd1SAlex Vesker u64 default_icm_addr; 63614c32fd1SAlex Vesker enum mlx5dr_ste_entry_type ste_type; 63714c32fd1SAlex Vesker }; 63814c32fd1SAlex Vesker 63914c32fd1SAlex Vesker struct mlx5dr_domain_info { 64014c32fd1SAlex Vesker bool supp_sw_steering; 64114c32fd1SAlex Vesker u32 max_inline_size; 64214c32fd1SAlex Vesker u32 max_send_wr; 64314c32fd1SAlex Vesker u32 max_log_sw_icm_sz; 64414c32fd1SAlex Vesker u32 max_log_action_icm_sz; 64514c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx rx; 64614c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx tx; 64714c32fd1SAlex Vesker struct mlx5dr_cmd_caps caps; 64814c32fd1SAlex Vesker }; 64914c32fd1SAlex Vesker 65014c32fd1SAlex Vesker struct mlx5dr_domain_cache { 65114c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft; 65214c32fd1SAlex Vesker }; 65314c32fd1SAlex Vesker 65414c32fd1SAlex Vesker struct mlx5dr_domain { 65514c32fd1SAlex Vesker struct mlx5dr_domain *peer_dmn; 65614c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 65714c32fd1SAlex Vesker u32 pdn; 65814c32fd1SAlex Vesker struct mlx5_uars_page *uar; 65914c32fd1SAlex Vesker enum mlx5dr_domain_type type; 66014c32fd1SAlex Vesker refcount_t refcount; 66114c32fd1SAlex Vesker struct mutex mutex; /* protect domain */ 66214c32fd1SAlex Vesker struct mlx5dr_icm_pool *ste_icm_pool; 66314c32fd1SAlex Vesker struct mlx5dr_icm_pool *action_icm_pool; 66414c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring; 66514c32fd1SAlex Vesker struct mlx5dr_domain_info info; 66614c32fd1SAlex Vesker struct mlx5dr_domain_cache cache; 66714c32fd1SAlex Vesker }; 66814c32fd1SAlex Vesker 66914c32fd1SAlex Vesker struct mlx5dr_table_rx_tx { 67014c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_anchor; 67114c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn; 67214c32fd1SAlex Vesker u64 default_icm_addr; 67314c32fd1SAlex Vesker }; 67414c32fd1SAlex Vesker 67514c32fd1SAlex Vesker struct mlx5dr_table { 67614c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 67714c32fd1SAlex Vesker struct mlx5dr_table_rx_tx rx; 67814c32fd1SAlex Vesker struct mlx5dr_table_rx_tx tx; 67914c32fd1SAlex Vesker u32 level; 68014c32fd1SAlex Vesker u32 table_type; 68114c32fd1SAlex Vesker u32 table_id; 68214c32fd1SAlex Vesker struct list_head matcher_list; 68314c32fd1SAlex Vesker struct mlx5dr_action *miss_action; 68414c32fd1SAlex Vesker refcount_t refcount; 68514c32fd1SAlex Vesker }; 68614c32fd1SAlex Vesker 68714c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx { 68814c32fd1SAlex Vesker struct mlx5dr_ste_htbl *s_htbl; 68914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *e_anchor; 69014c32fd1SAlex Vesker struct mlx5dr_ste_build *ste_builder; 691667f2646SAlex Vesker struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX] 692667f2646SAlex Vesker [DR_RULE_IPV_MAX] 693667f2646SAlex Vesker [DR_RULE_MAX_STES]; 69414c32fd1SAlex Vesker u8 num_of_builders; 695667f2646SAlex Vesker u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX]; 69614c32fd1SAlex Vesker u64 default_icm_addr; 69714c32fd1SAlex Vesker struct mlx5dr_table_rx_tx *nic_tbl; 69814c32fd1SAlex Vesker }; 69914c32fd1SAlex Vesker 70014c32fd1SAlex Vesker struct mlx5dr_matcher { 70114c32fd1SAlex Vesker struct mlx5dr_table *tbl; 70214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx rx; 70314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx tx; 70414c32fd1SAlex Vesker struct list_head matcher_list; 70514c32fd1SAlex Vesker u16 prio; 70614c32fd1SAlex Vesker struct mlx5dr_match_param mask; 70714c32fd1SAlex Vesker u8 match_criteria; 70814c32fd1SAlex Vesker refcount_t refcount; 70914c32fd1SAlex Vesker struct mlx5dv_flow_matcher *dv_matcher; 71014c32fd1SAlex Vesker }; 71114c32fd1SAlex Vesker 71214c32fd1SAlex Vesker struct mlx5dr_rule_member { 71314c32fd1SAlex Vesker struct mlx5dr_ste *ste; 71414c32fd1SAlex Vesker /* attached to mlx5dr_rule via this */ 71514c32fd1SAlex Vesker struct list_head list; 71614c32fd1SAlex Vesker /* attached to mlx5dr_ste via this */ 71714c32fd1SAlex Vesker struct list_head use_ste_list; 71814c32fd1SAlex Vesker }; 71914c32fd1SAlex Vesker 72014c32fd1SAlex Vesker struct mlx5dr_action { 72114c32fd1SAlex Vesker enum mlx5dr_action_type action_type; 72214c32fd1SAlex Vesker refcount_t refcount; 72314c32fd1SAlex Vesker union { 72414c32fd1SAlex Vesker struct { 72514c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 72614c32fd1SAlex Vesker struct mlx5dr_icm_chunk *chunk; 72714c32fd1SAlex Vesker u8 *data; 72814c32fd1SAlex Vesker u32 data_size; 72914c32fd1SAlex Vesker u16 num_of_actions; 73014c32fd1SAlex Vesker u32 index; 73114c32fd1SAlex Vesker u8 allow_rx:1; 73214c32fd1SAlex Vesker u8 allow_tx:1; 73314c32fd1SAlex Vesker u8 modify_ttl:1; 73414c32fd1SAlex Vesker } rewrite; 73514c32fd1SAlex Vesker struct { 73614c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 73714c32fd1SAlex Vesker u32 reformat_id; 73814c32fd1SAlex Vesker u32 reformat_size; 73914c32fd1SAlex Vesker } reformat; 74014c32fd1SAlex Vesker struct { 74114c32fd1SAlex Vesker u8 is_fw_tbl:1; 74214c32fd1SAlex Vesker union { 74314c32fd1SAlex Vesker struct mlx5dr_table *tbl; 74414c32fd1SAlex Vesker struct { 74514c32fd1SAlex Vesker struct mlx5_flow_table *ft; 74614c32fd1SAlex Vesker u64 rx_icm_addr; 74714c32fd1SAlex Vesker u64 tx_icm_addr; 74814c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 74914c32fd1SAlex Vesker } fw_tbl; 75014c32fd1SAlex Vesker }; 75114c32fd1SAlex Vesker } dest_tbl; 75214c32fd1SAlex Vesker struct { 75314c32fd1SAlex Vesker u32 ctr_id; 75414c32fd1SAlex Vesker u32 offeset; 75514c32fd1SAlex Vesker } ctr; 75614c32fd1SAlex Vesker struct { 75714c32fd1SAlex Vesker struct mlx5dr_domain *dmn; 75814c32fd1SAlex Vesker struct mlx5dr_cmd_vport_cap *caps; 75914c32fd1SAlex Vesker } vport; 76014c32fd1SAlex Vesker struct { 76114c32fd1SAlex Vesker u32 vlan_hdr; /* tpid_pcp_dei_vid */ 76214c32fd1SAlex Vesker } push_vlan; 76314c32fd1SAlex Vesker u32 flow_tag; 76414c32fd1SAlex Vesker }; 76514c32fd1SAlex Vesker }; 76614c32fd1SAlex Vesker 76714c32fd1SAlex Vesker enum mlx5dr_connect_type { 76814c32fd1SAlex Vesker CONNECT_HIT = 1, 76914c32fd1SAlex Vesker CONNECT_MISS = 2, 77014c32fd1SAlex Vesker }; 77114c32fd1SAlex Vesker 77214c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info { 77314c32fd1SAlex Vesker enum mlx5dr_connect_type type; 77414c32fd1SAlex Vesker union { 77514c32fd1SAlex Vesker struct mlx5dr_ste_htbl *hit_next_htbl; 77614c32fd1SAlex Vesker u64 miss_icm_addr; 77714c32fd1SAlex Vesker }; 77814c32fd1SAlex Vesker }; 77914c32fd1SAlex Vesker 78014c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx { 78114c32fd1SAlex Vesker struct list_head rule_members_list; 78214c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher; 78314c32fd1SAlex Vesker }; 78414c32fd1SAlex Vesker 78514c32fd1SAlex Vesker struct mlx5dr_rule { 78614c32fd1SAlex Vesker struct mlx5dr_matcher *matcher; 78714c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx rx; 78814c32fd1SAlex Vesker struct mlx5dr_rule_rx_tx tx; 78914c32fd1SAlex Vesker struct list_head rule_actions_list; 79014c32fd1SAlex Vesker }; 79114c32fd1SAlex Vesker 79214c32fd1SAlex Vesker void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste, 79314c32fd1SAlex Vesker struct mlx5dr_ste *ste); 79414c32fd1SAlex Vesker 79514c32fd1SAlex Vesker struct mlx5dr_icm_chunk { 79614c32fd1SAlex Vesker struct mlx5dr_icm_bucket *bucket; 79714c32fd1SAlex Vesker struct list_head chunk_list; 79814c32fd1SAlex Vesker u32 rkey; 79914c32fd1SAlex Vesker u32 num_of_entries; 80014c32fd1SAlex Vesker u32 byte_size; 80114c32fd1SAlex Vesker u64 icm_addr; 80214c32fd1SAlex Vesker u64 mr_addr; 80314c32fd1SAlex Vesker 80414c32fd1SAlex Vesker /* Memory optimisation */ 80514c32fd1SAlex Vesker struct mlx5dr_ste *ste_arr; 80614c32fd1SAlex Vesker u8 *hw_ste_arr; 80714c32fd1SAlex Vesker struct list_head *miss_list; 80814c32fd1SAlex Vesker }; 80914c32fd1SAlex Vesker 81014c32fd1SAlex Vesker static inline int 81114c32fd1SAlex Vesker mlx5dr_matcher_supp_flex_parser_icmp_v4(struct mlx5dr_cmd_caps *caps) 81214c32fd1SAlex Vesker { 81314c32fd1SAlex Vesker return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED; 81414c32fd1SAlex Vesker } 81514c32fd1SAlex Vesker 81614c32fd1SAlex Vesker static inline int 81714c32fd1SAlex Vesker mlx5dr_matcher_supp_flex_parser_icmp_v6(struct mlx5dr_cmd_caps *caps) 81814c32fd1SAlex Vesker { 81914c32fd1SAlex Vesker return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED; 82014c32fd1SAlex Vesker } 82114c32fd1SAlex Vesker 82214c32fd1SAlex Vesker int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher, 82314c32fd1SAlex Vesker struct mlx5dr_matcher_rx_tx *nic_matcher, 824667f2646SAlex Vesker enum mlx5dr_ipv outer_ipv, 825667f2646SAlex Vesker enum mlx5dr_ipv inner_ipv); 82614c32fd1SAlex Vesker 82714c32fd1SAlex Vesker static inline u32 82814c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size) 82914c32fd1SAlex Vesker { 83014c32fd1SAlex Vesker return 1 << chunk_size; 83114c32fd1SAlex Vesker } 83214c32fd1SAlex Vesker 83314c32fd1SAlex Vesker static inline int 83414c32fd1SAlex Vesker mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size, 83514c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type) 83614c32fd1SAlex Vesker { 83714c32fd1SAlex Vesker int num_of_entries; 83814c32fd1SAlex Vesker int entry_size; 83914c32fd1SAlex Vesker 84014c32fd1SAlex Vesker if (icm_type == DR_ICM_TYPE_STE) 84114c32fd1SAlex Vesker entry_size = DR_STE_SIZE; 84214c32fd1SAlex Vesker else 84314c32fd1SAlex Vesker entry_size = DR_MODIFY_ACTION_SIZE; 84414c32fd1SAlex Vesker 84514c32fd1SAlex Vesker num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size); 84614c32fd1SAlex Vesker 84714c32fd1SAlex Vesker return entry_size * num_of_entries; 84814c32fd1SAlex Vesker } 84914c32fd1SAlex Vesker 85014c32fd1SAlex Vesker static inline struct mlx5dr_cmd_vport_cap * 85114c32fd1SAlex Vesker mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport) 85214c32fd1SAlex Vesker { 85314c32fd1SAlex Vesker if (!caps->vports_caps || 85414c32fd1SAlex Vesker (vport >= caps->num_vports && vport != WIRE_PORT)) 85514c32fd1SAlex Vesker return NULL; 85614c32fd1SAlex Vesker 85714c32fd1SAlex Vesker if (vport == WIRE_PORT) 85814c32fd1SAlex Vesker vport = caps->num_vports; 85914c32fd1SAlex Vesker 86014c32fd1SAlex Vesker return &caps->vports_caps[vport]; 86114c32fd1SAlex Vesker } 86214c32fd1SAlex Vesker 86314c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details { 86414c32fd1SAlex Vesker u8 status; 86514c32fd1SAlex Vesker u8 level; 86614c32fd1SAlex Vesker u64 sw_owner_icm_root_1; 86714c32fd1SAlex Vesker u64 sw_owner_icm_root_0; 86814c32fd1SAlex Vesker }; 86914c32fd1SAlex Vesker 870cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr { 871cc78dbd7SAlex Vesker u32 table_type; 872cc78dbd7SAlex Vesker u64 icm_addr_rx; 873cc78dbd7SAlex Vesker u64 icm_addr_tx; 874cc78dbd7SAlex Vesker u8 level; 875cc78dbd7SAlex Vesker bool sw_owner; 876cc78dbd7SAlex Vesker bool term_tbl; 877cc78dbd7SAlex Vesker bool decap_en; 878cc78dbd7SAlex Vesker bool reformat_en; 879cc78dbd7SAlex Vesker }; 880cc78dbd7SAlex Vesker 88114c32fd1SAlex Vesker /* internal API functions */ 88214c32fd1SAlex Vesker int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev, 88314c32fd1SAlex Vesker struct mlx5dr_cmd_caps *caps); 88414c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev, 88514c32fd1SAlex Vesker bool other_vport, u16 vport_number, 88614c32fd1SAlex Vesker u64 *icm_address_rx, 88714c32fd1SAlex Vesker u64 *icm_address_tx); 88814c32fd1SAlex Vesker int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev, 88914c32fd1SAlex Vesker bool other_vport, u16 vport_number, u16 *gvmi); 89014c32fd1SAlex Vesker int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev, 89114c32fd1SAlex Vesker struct mlx5dr_esw_caps *caps); 89214c32fd1SAlex Vesker int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev); 89314c32fd1SAlex Vesker int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, 89414c32fd1SAlex Vesker u32 table_type, 89514c32fd1SAlex Vesker u32 table_id, 89614c32fd1SAlex Vesker u32 group_id, 89714c32fd1SAlex Vesker u32 modify_header_id, 89814c32fd1SAlex Vesker u32 vport_id); 89914c32fd1SAlex Vesker int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev, 90014c32fd1SAlex Vesker u32 table_type, 90114c32fd1SAlex Vesker u32 table_id); 90214c32fd1SAlex Vesker int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev, 90314c32fd1SAlex Vesker u32 table_type, 90414c32fd1SAlex Vesker u8 num_of_actions, 90514c32fd1SAlex Vesker u64 *actions, 90614c32fd1SAlex Vesker u32 *modify_header_id); 90714c32fd1SAlex Vesker int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev, 90814c32fd1SAlex Vesker u32 modify_header_id); 90914c32fd1SAlex Vesker int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev, 91014c32fd1SAlex Vesker u32 table_type, 91114c32fd1SAlex Vesker u32 table_id, 91214c32fd1SAlex Vesker u32 *group_id); 91314c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev, 91414c32fd1SAlex Vesker u32 table_type, 91514c32fd1SAlex Vesker u32 table_id, 91614c32fd1SAlex Vesker u32 group_id); 91714c32fd1SAlex Vesker int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev, 918cc78dbd7SAlex Vesker struct mlx5dr_cmd_create_flow_table_attr *attr, 91914c32fd1SAlex Vesker u64 *fdb_rx_icm_addr, 92014c32fd1SAlex Vesker u32 *table_id); 92114c32fd1SAlex Vesker int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev, 92214c32fd1SAlex Vesker u32 table_id, 92314c32fd1SAlex Vesker u32 table_type); 92414c32fd1SAlex Vesker int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev, 92514c32fd1SAlex Vesker enum fs_flow_table_type type, 92614c32fd1SAlex Vesker u32 table_id, 92714c32fd1SAlex Vesker struct mlx5dr_cmd_query_flow_table_details *output); 92814c32fd1SAlex Vesker int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev, 92914c32fd1SAlex Vesker enum mlx5_reformat_ctx_type rt, 93014c32fd1SAlex Vesker size_t reformat_size, 93114c32fd1SAlex Vesker void *reformat_data, 93214c32fd1SAlex Vesker u32 *reformat_id); 93314c32fd1SAlex Vesker void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev, 93414c32fd1SAlex Vesker u32 reformat_id); 93514c32fd1SAlex Vesker 93614c32fd1SAlex Vesker struct mlx5dr_cmd_gid_attr { 93714c32fd1SAlex Vesker u8 gid[16]; 93814c32fd1SAlex Vesker u8 mac[6]; 93914c32fd1SAlex Vesker u32 roce_ver; 94014c32fd1SAlex Vesker }; 94114c32fd1SAlex Vesker 94214c32fd1SAlex Vesker struct mlx5dr_cmd_qp_create_attr { 94314c32fd1SAlex Vesker u32 page_id; 94414c32fd1SAlex Vesker u32 pdn; 94514c32fd1SAlex Vesker u32 cqn; 94614c32fd1SAlex Vesker u32 pm_state; 94714c32fd1SAlex Vesker u32 service_type; 94814c32fd1SAlex Vesker u32 buff_umem_id; 94914c32fd1SAlex Vesker u32 db_umem_id; 95014c32fd1SAlex Vesker u32 sq_wqe_cnt; 95114c32fd1SAlex Vesker u32 rq_wqe_cnt; 95214c32fd1SAlex Vesker u32 rq_wqe_shift; 95314c32fd1SAlex Vesker }; 95414c32fd1SAlex Vesker 95514c32fd1SAlex Vesker int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num, 95614c32fd1SAlex Vesker u16 index, struct mlx5dr_cmd_gid_attr *attr); 95714c32fd1SAlex Vesker 95814c32fd1SAlex Vesker struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, 95914c32fd1SAlex Vesker enum mlx5dr_icm_type icm_type); 96014c32fd1SAlex Vesker void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool); 96114c32fd1SAlex Vesker 96214c32fd1SAlex Vesker struct mlx5dr_icm_chunk * 96314c32fd1SAlex Vesker mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool, 96414c32fd1SAlex Vesker enum mlx5dr_icm_chunk_size chunk_size); 96514c32fd1SAlex Vesker void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk); 96614c32fd1SAlex Vesker bool mlx5dr_ste_is_not_valid_entry(u8 *p_hw_ste); 96714c32fd1SAlex Vesker int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, 96814c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 96914c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 97014c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info, 97114c32fd1SAlex Vesker bool update_hw_ste); 97214c32fd1SAlex Vesker void mlx5dr_ste_set_formatted_ste(u16 gvmi, 97314c32fd1SAlex Vesker struct mlx5dr_domain_rx_tx *nic_dmn, 97414c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 97514c32fd1SAlex Vesker u8 *formatted_ste, 97614c32fd1SAlex Vesker struct mlx5dr_htbl_connect_info *connect_info); 97714c32fd1SAlex Vesker void mlx5dr_ste_copy_param(u8 match_criteria, 97814c32fd1SAlex Vesker struct mlx5dr_match_param *set_param, 97914c32fd1SAlex Vesker struct mlx5dr_match_parameters *mask); 98014c32fd1SAlex Vesker 98114c32fd1SAlex Vesker struct mlx5dr_qp { 98214c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 98314c32fd1SAlex Vesker struct mlx5_wq_qp wq; 98414c32fd1SAlex Vesker struct mlx5_uars_page *uar; 98514c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 98614c32fd1SAlex Vesker struct mlx5_core_qp mqp; 98714c32fd1SAlex Vesker struct { 98814c32fd1SAlex Vesker unsigned int pc; 98914c32fd1SAlex Vesker unsigned int cc; 99014c32fd1SAlex Vesker unsigned int size; 99114c32fd1SAlex Vesker unsigned int *wqe_head; 99214c32fd1SAlex Vesker unsigned int wqe_cnt; 99314c32fd1SAlex Vesker } sq; 99414c32fd1SAlex Vesker struct { 99514c32fd1SAlex Vesker unsigned int pc; 99614c32fd1SAlex Vesker unsigned int cc; 99714c32fd1SAlex Vesker unsigned int size; 99814c32fd1SAlex Vesker unsigned int wqe_cnt; 99914c32fd1SAlex Vesker } rq; 100014c32fd1SAlex Vesker int max_inline_data; 100114c32fd1SAlex Vesker }; 100214c32fd1SAlex Vesker 100314c32fd1SAlex Vesker struct mlx5dr_cq { 100414c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 100514c32fd1SAlex Vesker struct mlx5_cqwq wq; 100614c32fd1SAlex Vesker struct mlx5_wq_ctrl wq_ctrl; 100714c32fd1SAlex Vesker struct mlx5_core_cq mcq; 100814c32fd1SAlex Vesker struct mlx5dr_qp *qp; 100914c32fd1SAlex Vesker }; 101014c32fd1SAlex Vesker 101114c32fd1SAlex Vesker struct mlx5dr_mr { 101214c32fd1SAlex Vesker struct mlx5_core_dev *mdev; 101314c32fd1SAlex Vesker struct mlx5_core_mkey mkey; 101414c32fd1SAlex Vesker dma_addr_t dma_addr; 101514c32fd1SAlex Vesker void *addr; 101614c32fd1SAlex Vesker size_t size; 101714c32fd1SAlex Vesker }; 101814c32fd1SAlex Vesker 101914c32fd1SAlex Vesker #define MAX_SEND_CQE 64 102014c32fd1SAlex Vesker #define MIN_READ_SYNC 64 102114c32fd1SAlex Vesker 102214c32fd1SAlex Vesker struct mlx5dr_send_ring { 102314c32fd1SAlex Vesker struct mlx5dr_cq *cq; 102414c32fd1SAlex Vesker struct mlx5dr_qp *qp; 102514c32fd1SAlex Vesker struct mlx5dr_mr *mr; 102614c32fd1SAlex Vesker /* How much wqes are waiting for completion */ 102714c32fd1SAlex Vesker u32 pending_wqe; 102814c32fd1SAlex Vesker /* Signal request per this trash hold value */ 102914c32fd1SAlex Vesker u16 signal_th; 103014c32fd1SAlex Vesker /* Each post_send_size less than max_post_send_size */ 103114c32fd1SAlex Vesker u32 max_post_send_size; 103214c32fd1SAlex Vesker /* manage the send queue */ 103314c32fd1SAlex Vesker u32 tx_head; 103414c32fd1SAlex Vesker void *buf; 103514c32fd1SAlex Vesker u32 buf_size; 103614c32fd1SAlex Vesker struct ib_wc wc[MAX_SEND_CQE]; 103714c32fd1SAlex Vesker u8 sync_buff[MIN_READ_SYNC]; 103814c32fd1SAlex Vesker struct mlx5dr_mr *sync_mr; 103914c32fd1SAlex Vesker }; 104014c32fd1SAlex Vesker 104114c32fd1SAlex Vesker int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn); 104214c32fd1SAlex Vesker void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn, 104314c32fd1SAlex Vesker struct mlx5dr_send_ring *send_ring); 104414c32fd1SAlex Vesker int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn); 104514c32fd1SAlex Vesker int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn, 104614c32fd1SAlex Vesker struct mlx5dr_ste *ste, 104714c32fd1SAlex Vesker u8 *data, 104814c32fd1SAlex Vesker u16 size, 104914c32fd1SAlex Vesker u16 offset); 105014c32fd1SAlex Vesker int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn, 105114c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 105214c32fd1SAlex Vesker u8 *formatted_ste, u8 *mask); 105314c32fd1SAlex Vesker int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn, 105414c32fd1SAlex Vesker struct mlx5dr_ste_htbl *htbl, 105514c32fd1SAlex Vesker u8 *ste_init_data, 105614c32fd1SAlex Vesker bool update_hw_ste); 105714c32fd1SAlex Vesker int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn, 105814c32fd1SAlex Vesker struct mlx5dr_action *action); 105914c32fd1SAlex Vesker 10606de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info { 10616de03d2dSErez Shitrit u32 id; 10626de03d2dSErez Shitrit u16 vport; 10636de03d2dSErez Shitrit enum fs_flow_table_type type; 10646de03d2dSErez Shitrit }; 10656de03d2dSErez Shitrit 10666de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info { 10676de03d2dSErez Shitrit enum mlx5_flow_destination_type type; 10686de03d2dSErez Shitrit union { 10696de03d2dSErez Shitrit u32 tir_num; 10706de03d2dSErez Shitrit u32 ft_num; 10716de03d2dSErez Shitrit u32 ft_id; 10726de03d2dSErez Shitrit u32 counter_id; 10736de03d2dSErez Shitrit struct { 10746de03d2dSErez Shitrit u16 num; 10756de03d2dSErez Shitrit u16 vhca_id; 10766de03d2dSErez Shitrit u32 reformat_id; 10776de03d2dSErez Shitrit u8 flags; 10786de03d2dSErez Shitrit } vport; 10796de03d2dSErez Shitrit }; 10806de03d2dSErez Shitrit }; 10816de03d2dSErez Shitrit 10826de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info { 10836de03d2dSErez Shitrit u32 dests_size; 10846de03d2dSErez Shitrit u32 index; 10856de03d2dSErez Shitrit struct mlx5_flow_context flow_context; 10866de03d2dSErez Shitrit u32 *val; 10876de03d2dSErez Shitrit struct mlx5_flow_act action; 10886de03d2dSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest_arr; 10896de03d2dSErez Shitrit }; 10906de03d2dSErez Shitrit 10916de03d2dSErez Shitrit int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, 10926de03d2dSErez Shitrit int opmod, int modify_mask, 10936de03d2dSErez Shitrit struct mlx5dr_cmd_ft_info *ft, 10946de03d2dSErez Shitrit u32 group_id, 10956de03d2dSErez Shitrit struct mlx5dr_cmd_fte_info *fte); 10966de03d2dSErez Shitrit 109714c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft { 109814c32fd1SAlex Vesker u64 rx_icm_addr; 109914c32fd1SAlex Vesker u32 table_id; 110014c32fd1SAlex Vesker u32 group_id; 110114c32fd1SAlex Vesker u32 modify_hdr_id; 110214c32fd1SAlex Vesker }; 110314c32fd1SAlex Vesker 110414c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft * 110514c32fd1SAlex Vesker mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num); 110614c32fd1SAlex Vesker void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn, 110714c32fd1SAlex Vesker struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft); 110814c32fd1SAlex Vesker int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn, 110914c32fd1SAlex Vesker u32 vport_num, 111014c32fd1SAlex Vesker u64 *rx_icm_addr); 111134583beeSErez Shitrit int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn, 111234583beeSErez Shitrit struct mlx5dr_cmd_flow_destination_hw_info *dest, 111334583beeSErez Shitrit int num_dest, 111434583beeSErez Shitrit bool reformat_req, 111534583beeSErez Shitrit u32 *tbl_id, 111634583beeSErez Shitrit u32 *group_id); 111734583beeSErez Shitrit void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id, 111834583beeSErez Shitrit u32 group_id); 111914c32fd1SAlex Vesker #endif /* _DR_TYPES_H_ */ 1120