1*9222f0b2SMuhammad Sammar /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2*9222f0b2SMuhammad Sammar /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ 3*9222f0b2SMuhammad Sammar 4*9222f0b2SMuhammad Sammar struct mlx5dr_dbg_dump_info { 5*9222f0b2SMuhammad Sammar struct mutex dbg_mutex; /* protect dbg lists */ 6*9222f0b2SMuhammad Sammar struct dentry *steering_debugfs; 7*9222f0b2SMuhammad Sammar struct dentry *fdb_debugfs; 8*9222f0b2SMuhammad Sammar }; 9*9222f0b2SMuhammad Sammar 10*9222f0b2SMuhammad Sammar void mlx5dr_dbg_init_dump(struct mlx5dr_domain *dmn); 11*9222f0b2SMuhammad Sammar void mlx5dr_dbg_uninit_dump(struct mlx5dr_domain *dmn); 12*9222f0b2SMuhammad Sammar void mlx5dr_dbg_tbl_add(struct mlx5dr_table *tbl); 13*9222f0b2SMuhammad Sammar void mlx5dr_dbg_tbl_del(struct mlx5dr_table *tbl); 14*9222f0b2SMuhammad Sammar void mlx5dr_dbg_rule_add(struct mlx5dr_rule *rule); 15*9222f0b2SMuhammad Sammar void mlx5dr_dbg_rule_del(struct mlx5dr_rule *rule); 16