1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "dr_types.h" 5 #include "dr_ste.h" 6 7 enum dr_action_domain { 8 DR_ACTION_DOMAIN_NIC_INGRESS, 9 DR_ACTION_DOMAIN_NIC_EGRESS, 10 DR_ACTION_DOMAIN_FDB_INGRESS, 11 DR_ACTION_DOMAIN_FDB_EGRESS, 12 DR_ACTION_DOMAIN_MAX, 13 }; 14 15 enum dr_action_valid_state { 16 DR_ACTION_STATE_ERR, 17 DR_ACTION_STATE_NO_ACTION, 18 DR_ACTION_STATE_ENCAP, 19 DR_ACTION_STATE_DECAP, 20 DR_ACTION_STATE_MODIFY_HDR, 21 DR_ACTION_STATE_POP_VLAN, 22 DR_ACTION_STATE_PUSH_VLAN, 23 DR_ACTION_STATE_NON_TERM, 24 DR_ACTION_STATE_TERM, 25 DR_ACTION_STATE_MAX, 26 }; 27 28 static const char * const action_type_to_str[] = { 29 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2", 30 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2", 31 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2", 32 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3", 33 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP", 34 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP", 35 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT", 36 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR", 37 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG", 38 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR", 39 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT", 40 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN", 41 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN", 42 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER", 43 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR", 44 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR", 45 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN", 46 }; 47 48 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id) 49 { 50 if (action_id > DR_ACTION_TYP_MAX) 51 action_id = DR_ACTION_TYP_MAX; 52 return action_type_to_str[action_id]; 53 } 54 55 static const enum dr_action_valid_state 56 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = { 57 [DR_ACTION_DOMAIN_NIC_INGRESS] = { 58 [DR_ACTION_STATE_NO_ACTION] = { 59 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 60 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 61 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 62 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 63 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 64 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 65 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 66 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 67 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 68 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 69 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 70 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 71 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 72 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 73 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 74 }, 75 [DR_ACTION_STATE_DECAP] = { 76 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 77 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 78 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 79 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 80 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP, 81 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 82 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 83 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 84 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 85 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 86 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 87 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 88 }, 89 [DR_ACTION_STATE_ENCAP] = { 90 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 91 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 92 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 93 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 94 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP, 95 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 96 }, 97 [DR_ACTION_STATE_MODIFY_HDR] = { 98 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 99 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 100 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 101 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 102 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR, 103 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 104 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 105 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 106 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 107 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 108 }, 109 [DR_ACTION_STATE_POP_VLAN] = { 110 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 111 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 112 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 113 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 114 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN, 115 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 116 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 117 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 118 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 119 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 120 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 121 }, 122 [DR_ACTION_STATE_PUSH_VLAN] = { 123 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 124 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 125 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 126 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN, 127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 128 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 129 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 130 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 131 }, 132 [DR_ACTION_STATE_NON_TERM] = { 133 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 134 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 135 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 136 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 137 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 138 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 139 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 140 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 141 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 142 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 143 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 144 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 145 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 146 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 147 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 148 }, 149 [DR_ACTION_STATE_TERM] = { 150 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 151 }, 152 }, 153 [DR_ACTION_DOMAIN_NIC_EGRESS] = { 154 [DR_ACTION_STATE_NO_ACTION] = { 155 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 156 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 157 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 158 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 159 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 160 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 161 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 162 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 163 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 164 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 165 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 166 }, 167 [DR_ACTION_STATE_DECAP] = { 168 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 169 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 170 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 171 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 172 }, 173 [DR_ACTION_STATE_ENCAP] = { 174 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 175 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 176 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 177 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 178 }, 179 [DR_ACTION_STATE_MODIFY_HDR] = { 180 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 181 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 182 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 183 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 184 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 185 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 186 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 187 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 188 }, 189 [DR_ACTION_STATE_POP_VLAN] = { 190 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 191 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 192 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 193 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 194 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 195 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 196 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 197 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 198 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 199 }, 200 [DR_ACTION_STATE_PUSH_VLAN] = { 201 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 202 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 203 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 204 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 205 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 206 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 207 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 208 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 209 }, 210 [DR_ACTION_STATE_NON_TERM] = { 211 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 212 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 213 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 214 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 215 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 216 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 217 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 218 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 219 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 220 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 221 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 222 }, 223 [DR_ACTION_STATE_TERM] = { 224 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 225 }, 226 }, 227 [DR_ACTION_DOMAIN_FDB_INGRESS] = { 228 [DR_ACTION_STATE_NO_ACTION] = { 229 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 230 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 231 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 232 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 233 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 234 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 235 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 236 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 237 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 238 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 239 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 240 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 241 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 242 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 243 }, 244 [DR_ACTION_STATE_DECAP] = { 245 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 246 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 247 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 248 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 249 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 250 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 251 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 252 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 253 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 254 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 255 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 256 }, 257 [DR_ACTION_STATE_ENCAP] = { 258 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 259 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 260 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 261 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 262 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 263 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 264 }, 265 [DR_ACTION_STATE_MODIFY_HDR] = { 266 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 267 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 268 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 269 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 270 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 271 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 272 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 273 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 274 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 275 }, 276 [DR_ACTION_STATE_POP_VLAN] = { 277 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 278 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 279 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 280 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 281 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 282 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 283 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 284 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 285 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 286 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 287 }, 288 [DR_ACTION_STATE_PUSH_VLAN] = { 289 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 290 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 291 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 292 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 293 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 294 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 295 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 296 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 297 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 298 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 299 }, 300 [DR_ACTION_STATE_NON_TERM] = { 301 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 302 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 303 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 304 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 305 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 306 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 307 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 308 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 309 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 310 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 311 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 312 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 313 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 314 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 315 }, 316 [DR_ACTION_STATE_TERM] = { 317 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 318 }, 319 }, 320 [DR_ACTION_DOMAIN_FDB_EGRESS] = { 321 [DR_ACTION_STATE_NO_ACTION] = { 322 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 323 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 324 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 325 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 326 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 327 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 328 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 329 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 330 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 331 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 332 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 333 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 334 }, 335 [DR_ACTION_STATE_DECAP] = { 336 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 337 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 338 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 339 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 340 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 341 }, 342 [DR_ACTION_STATE_ENCAP] = { 343 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 344 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 345 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 346 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 347 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 348 }, 349 [DR_ACTION_STATE_MODIFY_HDR] = { 350 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 351 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 352 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 353 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 354 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 355 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 356 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 357 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 358 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 359 }, 360 [DR_ACTION_STATE_POP_VLAN] = { 361 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 362 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 363 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 364 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 365 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 366 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 367 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 368 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 369 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 370 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 371 }, 372 [DR_ACTION_STATE_PUSH_VLAN] = { 373 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 374 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 375 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 376 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 377 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 378 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 379 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 380 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 381 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 382 }, 383 [DR_ACTION_STATE_NON_TERM] = { 384 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 385 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 386 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 387 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 388 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 389 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 390 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 391 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 392 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 393 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 394 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 395 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 396 }, 397 [DR_ACTION_STATE_TERM] = { 398 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 399 }, 400 }, 401 }; 402 403 static int 404 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type, 405 enum mlx5dr_action_type *action_type) 406 { 407 switch (reformat_type) { 408 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2: 409 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2; 410 break; 411 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2: 412 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2; 413 break; 414 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2: 415 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2; 416 break; 417 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3: 418 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3; 419 break; 420 case DR_ACTION_REFORMAT_TYP_INSERT_HDR: 421 *action_type = DR_ACTION_TYP_INSERT_HDR; 422 break; 423 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR: 424 *action_type = DR_ACTION_TYP_REMOVE_HDR; 425 break; 426 default: 427 return -EINVAL; 428 } 429 430 return 0; 431 } 432 433 /* Apply the actions on the rule STE array starting from the last_ste. 434 * Actions might require more than one STE, new_num_stes will return 435 * the new size of the STEs array, rule with actions. 436 */ 437 static void dr_actions_apply(struct mlx5dr_domain *dmn, 438 enum mlx5dr_domain_nic_type nic_type, 439 u8 *action_type_set, 440 u8 *last_ste, 441 struct mlx5dr_ste_actions_attr *attr, 442 u32 *new_num_stes) 443 { 444 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; 445 u32 added_stes = 0; 446 447 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 448 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set, 449 last_ste, attr, &added_stes); 450 else 451 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set, 452 last_ste, attr, &added_stes); 453 454 *new_num_stes += added_stes; 455 } 456 457 static enum dr_action_domain 458 dr_action_get_action_domain(enum mlx5dr_domain_type domain, 459 enum mlx5dr_domain_nic_type nic_type) 460 { 461 switch (domain) { 462 case MLX5DR_DOMAIN_TYPE_NIC_RX: 463 return DR_ACTION_DOMAIN_NIC_INGRESS; 464 case MLX5DR_DOMAIN_TYPE_NIC_TX: 465 return DR_ACTION_DOMAIN_NIC_EGRESS; 466 case MLX5DR_DOMAIN_TYPE_FDB: 467 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 468 return DR_ACTION_DOMAIN_FDB_INGRESS; 469 return DR_ACTION_DOMAIN_FDB_EGRESS; 470 default: 471 WARN_ON(true); 472 return DR_ACTION_DOMAIN_MAX; 473 } 474 } 475 476 static 477 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain, 478 u32 action_type, 479 u32 *state) 480 { 481 u32 cur_state = *state; 482 483 /* Check action state machine is valid */ 484 *state = next_action_state[action_domain][cur_state][action_type]; 485 486 if (*state == DR_ACTION_STATE_ERR) 487 return -EOPNOTSUPP; 488 489 return 0; 490 } 491 492 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, 493 struct mlx5dr_action *dest_action, 494 u64 *final_icm_addr) 495 { 496 int ret; 497 498 switch (dest_action->action_type) { 499 case DR_ACTION_TYP_FT: 500 /* Allow destination flow table only if table is a terminating 501 * table, since there is an *assumption* that in such case FW 502 * will recalculate the CS. 503 */ 504 if (dest_action->dest_tbl->is_fw_tbl) { 505 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr; 506 } else { 507 mlx5dr_dbg(dmn, 508 "Destination FT should be terminating when modify TTL is used\n"); 509 return -EINVAL; 510 } 511 break; 512 513 case DR_ACTION_TYP_VPORT: 514 /* If destination is vport we will get the FW flow table 515 * that recalculates the CS and forwards to the vport. 516 */ 517 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn, 518 dest_action->vport->caps->num, 519 final_icm_addr); 520 if (ret) { 521 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); 522 return ret; 523 } 524 break; 525 526 default: 527 break; 528 } 529 530 return 0; 531 } 532 533 static void dr_action_print_sequence(struct mlx5dr_domain *dmn, 534 struct mlx5dr_action *actions[], 535 int last_idx) 536 { 537 int i; 538 539 for (i = 0; i <= last_idx; i++) 540 mlx5dr_err(dmn, "< %s (%d) > ", 541 dr_action_id_to_str(actions[i]->action_type), 542 actions[i]->action_type); 543 } 544 545 #define WITH_VLAN_NUM_HW_ACTIONS 6 546 547 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 548 struct mlx5dr_matcher_rx_tx *nic_matcher, 549 struct mlx5dr_action *actions[], 550 u32 num_actions, 551 u8 *ste_arr, 552 u32 *new_hw_ste_arr_sz) 553 { 554 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn; 555 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX; 556 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 557 u8 action_type_set[DR_ACTION_TYP_MAX] = {}; 558 struct mlx5dr_ste_actions_attr attr = {}; 559 struct mlx5dr_action *dest_action = NULL; 560 u32 state = DR_ACTION_STATE_NO_ACTION; 561 enum dr_action_domain action_domain; 562 bool recalc_cs_required = false; 563 u8 *last_ste; 564 int i, ret; 565 566 attr.gvmi = dmn->info.caps.gvmi; 567 attr.hit_gvmi = dmn->info.caps.gvmi; 568 attr.final_icm_addr = nic_dmn->default_icm_addr; 569 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type); 570 571 for (i = 0; i < num_actions; i++) { 572 struct mlx5dr_action_dest_tbl *dest_tbl; 573 struct mlx5dr_action *action; 574 int max_actions_type = 1; 575 u32 action_type; 576 577 action = actions[i]; 578 action_type = action->action_type; 579 580 switch (action_type) { 581 case DR_ACTION_TYP_DROP: 582 attr.final_icm_addr = nic_dmn->drop_icm_addr; 583 break; 584 case DR_ACTION_TYP_FT: 585 dest_action = action; 586 dest_tbl = action->dest_tbl; 587 if (!dest_tbl->is_fw_tbl) { 588 if (dest_tbl->tbl->dmn != dmn) { 589 mlx5dr_err(dmn, 590 "Destination table belongs to a different domain\n"); 591 return -EINVAL; 592 } 593 if (dest_tbl->tbl->level <= matcher->tbl->level) { 594 mlx5_core_dbg_once(dmn->mdev, 595 "Connecting table to a lower/same level destination table\n"); 596 mlx5dr_dbg(dmn, 597 "Connecting table at level %d to a destination table at level %d\n", 598 matcher->tbl->level, 599 dest_tbl->tbl->level); 600 } 601 attr.final_icm_addr = rx_rule ? 602 dest_tbl->tbl->rx.s_anchor->chunk->icm_addr : 603 dest_tbl->tbl->tx.s_anchor->chunk->icm_addr; 604 } else { 605 struct mlx5dr_cmd_query_flow_table_details output; 606 int ret; 607 608 /* get the relevant addresses */ 609 if (!action->dest_tbl->fw_tbl.rx_icm_addr) { 610 ret = mlx5dr_cmd_query_flow_table(dmn->mdev, 611 dest_tbl->fw_tbl.type, 612 dest_tbl->fw_tbl.id, 613 &output); 614 if (!ret) { 615 dest_tbl->fw_tbl.tx_icm_addr = 616 output.sw_owner_icm_root_1; 617 dest_tbl->fw_tbl.rx_icm_addr = 618 output.sw_owner_icm_root_0; 619 } else { 620 mlx5dr_err(dmn, 621 "Failed mlx5_cmd_query_flow_table ret: %d\n", 622 ret); 623 return ret; 624 } 625 } 626 attr.final_icm_addr = rx_rule ? 627 dest_tbl->fw_tbl.rx_icm_addr : 628 dest_tbl->fw_tbl.tx_icm_addr; 629 } 630 break; 631 case DR_ACTION_TYP_QP: 632 mlx5dr_info(dmn, "Domain doesn't support QP\n"); 633 return -EOPNOTSUPP; 634 case DR_ACTION_TYP_CTR: 635 attr.ctr_id = action->ctr->ctr_id + 636 action->ctr->offset; 637 break; 638 case DR_ACTION_TYP_TAG: 639 attr.flow_tag = action->flow_tag->flow_tag; 640 break; 641 case DR_ACTION_TYP_TNL_L2_TO_L2: 642 break; 643 case DR_ACTION_TYP_TNL_L3_TO_L2: 644 attr.decap_index = action->rewrite->index; 645 attr.decap_actions = action->rewrite->num_of_actions; 646 attr.decap_with_vlan = 647 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS; 648 break; 649 case DR_ACTION_TYP_MODIFY_HDR: 650 attr.modify_index = action->rewrite->index; 651 attr.modify_actions = action->rewrite->num_of_actions; 652 recalc_cs_required = action->rewrite->modify_ttl && 653 !mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps); 654 break; 655 case DR_ACTION_TYP_L2_TO_TNL_L2: 656 case DR_ACTION_TYP_L2_TO_TNL_L3: 657 if (rx_rule && 658 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) { 659 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n"); 660 return -EOPNOTSUPP; 661 } 662 attr.reformat.size = action->reformat->size; 663 attr.reformat.id = action->reformat->id; 664 break; 665 case DR_ACTION_TYP_SAMPLER: 666 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr : 667 action->sampler->tx_icm_addr; 668 break; 669 case DR_ACTION_TYP_VPORT: 670 attr.hit_gvmi = action->vport->caps->vhca_gvmi; 671 dest_action = action; 672 attr.final_icm_addr = rx_rule ? 673 action->vport->caps->icm_address_rx : 674 action->vport->caps->icm_address_tx; 675 break; 676 case DR_ACTION_TYP_POP_VLAN: 677 if (!rx_rule && !(dmn->ste_ctx->actions_caps & 678 DR_STE_CTX_ACTION_CAP_TX_POP)) { 679 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n"); 680 return -EOPNOTSUPP; 681 } 682 683 max_actions_type = MLX5DR_MAX_VLANS; 684 attr.vlans.count++; 685 break; 686 case DR_ACTION_TYP_PUSH_VLAN: 687 if (rx_rule && !(dmn->ste_ctx->actions_caps & 688 DR_STE_CTX_ACTION_CAP_RX_PUSH)) { 689 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n"); 690 return -EOPNOTSUPP; 691 } 692 693 max_actions_type = MLX5DR_MAX_VLANS; 694 if (attr.vlans.count == MLX5DR_MAX_VLANS) { 695 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n"); 696 return -EINVAL; 697 } 698 699 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr; 700 break; 701 case DR_ACTION_TYP_INSERT_HDR: 702 case DR_ACTION_TYP_REMOVE_HDR: 703 attr.reformat.size = action->reformat->size; 704 attr.reformat.id = action->reformat->id; 705 attr.reformat.param_0 = action->reformat->param_0; 706 attr.reformat.param_1 = action->reformat->param_1; 707 break; 708 default: 709 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type); 710 return -EINVAL; 711 } 712 713 /* Check action duplication */ 714 if (++action_type_set[action_type] > max_actions_type) { 715 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n", 716 action_type, max_actions_type); 717 return -EINVAL; 718 } 719 720 /* Check action state machine is valid */ 721 if (dr_action_validate_and_get_next_state(action_domain, 722 action_type, 723 &state)) { 724 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:", 725 attr.gvmi, rx_rule); 726 dr_action_print_sequence(dmn, actions, i); 727 return -EOPNOTSUPP; 728 } 729 } 730 731 *new_hw_ste_arr_sz = nic_matcher->num_of_builders; 732 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1); 733 734 /* Due to a HW bug in some devices, modifying TTL on RX flows will 735 * cause an incorrect checksum calculation. In this case we will 736 * use a FW table to recalculate. 737 */ 738 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB && 739 rx_rule && recalc_cs_required && dest_action) { 740 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr); 741 if (ret) { 742 mlx5dr_err(dmn, 743 "Failed to handle checksum recalculation err %d\n", 744 ret); 745 return ret; 746 } 747 } 748 749 dr_actions_apply(dmn, 750 nic_dmn->type, 751 action_type_set, 752 last_ste, 753 &attr, 754 new_hw_ste_arr_sz); 755 756 return 0; 757 } 758 759 static unsigned int action_size[DR_ACTION_TYP_MAX] = { 760 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat), 761 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat), 762 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite), 763 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat), 764 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl), 765 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr), 766 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag), 767 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite), 768 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport), 769 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan), 770 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat), 771 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat), 772 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler), 773 }; 774 775 static struct mlx5dr_action * 776 dr_action_create_generic(enum mlx5dr_action_type action_type) 777 { 778 struct mlx5dr_action *action; 779 int extra_size; 780 781 if (action_type < DR_ACTION_TYP_MAX) 782 extra_size = action_size[action_type]; 783 else 784 return NULL; 785 786 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL); 787 if (!action) 788 return NULL; 789 790 action->action_type = action_type; 791 refcount_set(&action->refcount, 1); 792 action->data = action + 1; 793 794 return action; 795 } 796 797 struct mlx5dr_action *mlx5dr_action_create_drop(void) 798 { 799 return dr_action_create_generic(DR_ACTION_TYP_DROP); 800 } 801 802 struct mlx5dr_action * 803 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num) 804 { 805 struct mlx5dr_action *action; 806 807 action = dr_action_create_generic(DR_ACTION_TYP_FT); 808 if (!action) 809 return NULL; 810 811 action->dest_tbl->is_fw_tbl = true; 812 action->dest_tbl->fw_tbl.dmn = dmn; 813 action->dest_tbl->fw_tbl.id = table_num; 814 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 815 refcount_inc(&dmn->refcount); 816 817 return action; 818 } 819 820 struct mlx5dr_action * 821 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl) 822 { 823 struct mlx5dr_action *action; 824 825 refcount_inc(&tbl->refcount); 826 827 action = dr_action_create_generic(DR_ACTION_TYP_FT); 828 if (!action) 829 goto dec_ref; 830 831 action->dest_tbl->tbl = tbl; 832 833 return action; 834 835 dec_ref: 836 refcount_dec(&tbl->refcount); 837 return NULL; 838 } 839 840 struct mlx5dr_action * 841 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn, 842 struct mlx5dr_action_dest *dests, 843 u32 num_of_dests, 844 bool ignore_flow_level) 845 { 846 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests; 847 struct mlx5dr_action **ref_actions; 848 struct mlx5dr_action *action; 849 bool reformat_req = false; 850 u32 num_of_ref = 0; 851 u32 ref_act_cnt; 852 int ret; 853 int i; 854 855 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 856 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n"); 857 return NULL; 858 } 859 860 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL); 861 if (!hw_dests) 862 return NULL; 863 864 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt))) 865 goto free_hw_dests; 866 867 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL); 868 if (!ref_actions) 869 goto free_hw_dests; 870 871 for (i = 0; i < num_of_dests; i++) { 872 struct mlx5dr_action *reformat_action = dests[i].reformat; 873 struct mlx5dr_action *dest_action = dests[i].dest; 874 875 ref_actions[num_of_ref++] = dest_action; 876 877 switch (dest_action->action_type) { 878 case DR_ACTION_TYP_VPORT: 879 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID; 880 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; 881 hw_dests[i].vport.num = dest_action->vport->caps->num; 882 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi; 883 if (reformat_action) { 884 reformat_req = true; 885 hw_dests[i].vport.reformat_id = 886 reformat_action->reformat->id; 887 ref_actions[num_of_ref++] = reformat_action; 888 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; 889 } 890 break; 891 892 case DR_ACTION_TYP_FT: 893 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 894 if (dest_action->dest_tbl->is_fw_tbl) 895 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id; 896 else 897 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id; 898 break; 899 900 default: 901 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n"); 902 goto free_ref_actions; 903 } 904 } 905 906 action = dr_action_create_generic(DR_ACTION_TYP_FT); 907 if (!action) 908 goto free_ref_actions; 909 910 ret = mlx5dr_fw_create_md_tbl(dmn, 911 hw_dests, 912 num_of_dests, 913 reformat_req, 914 &action->dest_tbl->fw_tbl.id, 915 &action->dest_tbl->fw_tbl.group_id, 916 ignore_flow_level); 917 if (ret) 918 goto free_action; 919 920 refcount_inc(&dmn->refcount); 921 922 for (i = 0; i < num_of_ref; i++) 923 refcount_inc(&ref_actions[i]->refcount); 924 925 action->dest_tbl->is_fw_tbl = true; 926 action->dest_tbl->fw_tbl.dmn = dmn; 927 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 928 action->dest_tbl->fw_tbl.ref_actions = ref_actions; 929 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref; 930 931 kfree(hw_dests); 932 933 return action; 934 935 free_action: 936 kfree(action); 937 free_ref_actions: 938 kfree(ref_actions); 939 free_hw_dests: 940 kfree(hw_dests); 941 return NULL; 942 } 943 944 struct mlx5dr_action * 945 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn, 946 struct mlx5_flow_table *ft) 947 { 948 struct mlx5dr_action *action; 949 950 action = dr_action_create_generic(DR_ACTION_TYP_FT); 951 if (!action) 952 return NULL; 953 954 action->dest_tbl->is_fw_tbl = 1; 955 action->dest_tbl->fw_tbl.type = ft->type; 956 action->dest_tbl->fw_tbl.id = ft->id; 957 action->dest_tbl->fw_tbl.dmn = dmn; 958 959 refcount_inc(&dmn->refcount); 960 961 return action; 962 } 963 964 struct mlx5dr_action * 965 mlx5dr_action_create_flow_counter(u32 counter_id) 966 { 967 struct mlx5dr_action *action; 968 969 action = dr_action_create_generic(DR_ACTION_TYP_CTR); 970 if (!action) 971 return NULL; 972 973 action->ctr->ctr_id = counter_id; 974 975 return action; 976 } 977 978 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value) 979 { 980 struct mlx5dr_action *action; 981 982 action = dr_action_create_generic(DR_ACTION_TYP_TAG); 983 if (!action) 984 return NULL; 985 986 action->flow_tag->flow_tag = tag_value & 0xffffff; 987 988 return action; 989 } 990 991 struct mlx5dr_action * 992 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id) 993 { 994 struct mlx5dr_action *action; 995 u64 icm_rx, icm_tx; 996 int ret; 997 998 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id, 999 &icm_rx, &icm_tx); 1000 if (ret) 1001 return NULL; 1002 1003 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER); 1004 if (!action) 1005 return NULL; 1006 1007 action->sampler->dmn = dmn; 1008 action->sampler->sampler_id = sampler_id; 1009 action->sampler->rx_icm_addr = icm_rx; 1010 action->sampler->tx_icm_addr = icm_tx; 1011 1012 refcount_inc(&dmn->refcount); 1013 return action; 1014 } 1015 1016 static int 1017 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type, 1018 struct mlx5dr_domain *dmn, 1019 u8 reformat_param_0, 1020 u8 reformat_param_1, 1021 size_t data_sz, 1022 void *data) 1023 { 1024 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) { 1025 if ((!data && data_sz) || (data && !data_sz) || 1026 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz || 1027 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) { 1028 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n"); 1029 goto out_err; 1030 } 1031 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) { 1032 if (data || 1033 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz || 1034 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) { 1035 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n"); 1036 goto out_err; 1037 } 1038 } else if (reformat_param_0 || reformat_param_1 || 1039 reformat_type > DR_ACTION_TYP_REMOVE_HDR) { 1040 mlx5dr_dbg(dmn, "Invalid reformat parameters\n"); 1041 goto out_err; 1042 } 1043 1044 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 1045 return 0; 1046 1047 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) { 1048 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 && 1049 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) { 1050 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n"); 1051 goto out_err; 1052 } 1053 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) { 1054 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 && 1055 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) { 1056 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n"); 1057 goto out_err; 1058 } 1059 } 1060 1061 return 0; 1062 1063 out_err: 1064 return -EINVAL; 1065 } 1066 1067 #define ACTION_CACHE_LINE_SIZE 64 1068 1069 static int 1070 dr_action_create_reformat_action(struct mlx5dr_domain *dmn, 1071 u8 reformat_param_0, u8 reformat_param_1, 1072 size_t data_sz, void *data, 1073 struct mlx5dr_action *action) 1074 { 1075 u32 reformat_id; 1076 int ret; 1077 1078 switch (action->action_type) { 1079 case DR_ACTION_TYP_L2_TO_TNL_L2: 1080 case DR_ACTION_TYP_L2_TO_TNL_L3: 1081 { 1082 enum mlx5_reformat_ctx_type rt; 1083 1084 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2) 1085 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL; 1086 else 1087 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL; 1088 1089 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0, 1090 data_sz, data, 1091 &reformat_id); 1092 if (ret) 1093 return ret; 1094 1095 action->reformat->id = reformat_id; 1096 action->reformat->size = data_sz; 1097 return 0; 1098 } 1099 case DR_ACTION_TYP_TNL_L2_TO_L2: 1100 { 1101 return 0; 1102 } 1103 case DR_ACTION_TYP_TNL_L3_TO_L2: 1104 { 1105 u8 hw_actions[ACTION_CACHE_LINE_SIZE] = {}; 1106 int ret; 1107 1108 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx, 1109 data, data_sz, 1110 hw_actions, 1111 ACTION_CACHE_LINE_SIZE, 1112 &action->rewrite->num_of_actions); 1113 if (ret) { 1114 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n"); 1115 return ret; 1116 } 1117 1118 action->rewrite->chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, 1119 DR_CHUNK_SIZE_8); 1120 if (!action->rewrite->chunk) { 1121 mlx5dr_dbg(dmn, "Failed allocating modify header chunk\n"); 1122 return -ENOMEM; 1123 } 1124 1125 action->rewrite->data = (void *)hw_actions; 1126 action->rewrite->index = (action->rewrite->chunk->icm_addr - 1127 dmn->info.caps.hdr_modify_icm_addr) / 1128 ACTION_CACHE_LINE_SIZE; 1129 1130 ret = mlx5dr_send_postsend_action(dmn, action); 1131 if (ret) { 1132 mlx5dr_dbg(dmn, "Writing decap l3 actions to ICM failed\n"); 1133 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1134 return ret; 1135 } 1136 return 0; 1137 } 1138 case DR_ACTION_TYP_INSERT_HDR: 1139 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, 1140 MLX5_REFORMAT_TYPE_INSERT_HDR, 1141 reformat_param_0, 1142 reformat_param_1, 1143 data_sz, data, 1144 &reformat_id); 1145 if (ret) 1146 return ret; 1147 1148 action->reformat->id = reformat_id; 1149 action->reformat->size = data_sz; 1150 action->reformat->param_0 = reformat_param_0; 1151 action->reformat->param_1 = reformat_param_1; 1152 return 0; 1153 case DR_ACTION_TYP_REMOVE_HDR: 1154 action->reformat->id = 0; 1155 action->reformat->size = data_sz; 1156 action->reformat->param_0 = reformat_param_0; 1157 action->reformat->param_1 = reformat_param_1; 1158 return 0; 1159 default: 1160 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type); 1161 return -EINVAL; 1162 } 1163 } 1164 1165 #define CVLAN_ETHERTYPE 0x8100 1166 #define SVLAN_ETHERTYPE 0x88a8 1167 1168 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void) 1169 { 1170 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN); 1171 } 1172 1173 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn, 1174 __be32 vlan_hdr) 1175 { 1176 u32 vlan_hdr_h = ntohl(vlan_hdr); 1177 u16 ethertype = vlan_hdr_h >> 16; 1178 struct mlx5dr_action *action; 1179 1180 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) { 1181 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n"); 1182 return NULL; 1183 } 1184 1185 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN); 1186 if (!action) 1187 return NULL; 1188 1189 action->push_vlan->vlan_hdr = vlan_hdr_h; 1190 return action; 1191 } 1192 1193 struct mlx5dr_action * 1194 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn, 1195 enum mlx5dr_action_reformat_type reformat_type, 1196 u8 reformat_param_0, 1197 u8 reformat_param_1, 1198 size_t data_sz, 1199 void *data) 1200 { 1201 enum mlx5dr_action_type action_type; 1202 struct mlx5dr_action *action; 1203 int ret; 1204 1205 refcount_inc(&dmn->refcount); 1206 1207 /* General checks */ 1208 ret = dr_action_reformat_to_action_type(reformat_type, &action_type); 1209 if (ret) { 1210 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n"); 1211 goto dec_ref; 1212 } 1213 1214 ret = dr_action_verify_reformat_params(action_type, dmn, 1215 reformat_param_0, reformat_param_1, 1216 data_sz, data); 1217 if (ret) 1218 goto dec_ref; 1219 1220 action = dr_action_create_generic(action_type); 1221 if (!action) 1222 goto dec_ref; 1223 1224 action->reformat->dmn = dmn; 1225 1226 ret = dr_action_create_reformat_action(dmn, 1227 reformat_param_0, 1228 reformat_param_1, 1229 data_sz, 1230 data, 1231 action); 1232 if (ret) { 1233 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret); 1234 goto free_action; 1235 } 1236 1237 return action; 1238 1239 free_action: 1240 kfree(action); 1241 dec_ref: 1242 refcount_dec(&dmn->refcount); 1243 return NULL; 1244 } 1245 1246 static int 1247 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn, 1248 __be64 *sw_action, 1249 __be64 *hw_action, 1250 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1251 { 1252 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1253 u8 max_length; 1254 u16 sw_field; 1255 u32 data; 1256 1257 /* Get SW modify action data */ 1258 sw_field = MLX5_GET(set_action_in, sw_action, field); 1259 data = MLX5_GET(set_action_in, sw_action, data); 1260 1261 /* Convert SW data to HW modify action format */ 1262 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1263 if (!hw_action_info) { 1264 mlx5dr_dbg(dmn, "Modify add action invalid field given\n"); 1265 return -EINVAL; 1266 } 1267 1268 max_length = hw_action_info->end - hw_action_info->start + 1; 1269 1270 mlx5dr_ste_set_action_add(dmn->ste_ctx, 1271 hw_action, 1272 hw_action_info->hw_field, 1273 hw_action_info->start, 1274 max_length, 1275 data); 1276 1277 *ret_hw_info = hw_action_info; 1278 1279 return 0; 1280 } 1281 1282 static int 1283 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn, 1284 __be64 *sw_action, 1285 __be64 *hw_action, 1286 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1287 { 1288 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1289 u8 offset, length, max_length; 1290 u16 sw_field; 1291 u32 data; 1292 1293 /* Get SW modify action data */ 1294 length = MLX5_GET(set_action_in, sw_action, length); 1295 offset = MLX5_GET(set_action_in, sw_action, offset); 1296 sw_field = MLX5_GET(set_action_in, sw_action, field); 1297 data = MLX5_GET(set_action_in, sw_action, data); 1298 1299 /* Convert SW data to HW modify action format */ 1300 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1301 if (!hw_action_info) { 1302 mlx5dr_dbg(dmn, "Modify set action invalid field given\n"); 1303 return -EINVAL; 1304 } 1305 1306 /* PRM defines that length zero specific length of 32bits */ 1307 length = length ? length : 32; 1308 1309 max_length = hw_action_info->end - hw_action_info->start + 1; 1310 1311 if (length + offset > max_length) { 1312 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1313 return -EINVAL; 1314 } 1315 1316 mlx5dr_ste_set_action_set(dmn->ste_ctx, 1317 hw_action, 1318 hw_action_info->hw_field, 1319 hw_action_info->start + offset, 1320 length, 1321 data); 1322 1323 *ret_hw_info = hw_action_info; 1324 1325 return 0; 1326 } 1327 1328 static int 1329 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn, 1330 __be64 *sw_action, 1331 __be64 *hw_action, 1332 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1333 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1334 { 1335 u8 src_offset, dst_offset, src_max_length, dst_max_length, length; 1336 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1337 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1338 u16 src_field, dst_field; 1339 1340 /* Get SW modify action data */ 1341 src_field = MLX5_GET(copy_action_in, sw_action, src_field); 1342 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field); 1343 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset); 1344 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset); 1345 length = MLX5_GET(copy_action_in, sw_action, length); 1346 1347 /* Convert SW data to HW modify action format */ 1348 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field); 1349 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field); 1350 if (!hw_src_action_info || !hw_dst_action_info) { 1351 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n"); 1352 return -EINVAL; 1353 } 1354 1355 /* PRM defines that length zero specific length of 32bits */ 1356 length = length ? length : 32; 1357 1358 src_max_length = hw_src_action_info->end - 1359 hw_src_action_info->start + 1; 1360 dst_max_length = hw_dst_action_info->end - 1361 hw_dst_action_info->start + 1; 1362 1363 if (length + src_offset > src_max_length || 1364 length + dst_offset > dst_max_length) { 1365 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1366 return -EINVAL; 1367 } 1368 1369 mlx5dr_ste_set_action_copy(dmn->ste_ctx, 1370 hw_action, 1371 hw_dst_action_info->hw_field, 1372 hw_dst_action_info->start + dst_offset, 1373 length, 1374 hw_src_action_info->hw_field, 1375 hw_src_action_info->start + src_offset); 1376 1377 *ret_dst_hw_info = hw_dst_action_info; 1378 *ret_src_hw_info = hw_src_action_info; 1379 1380 return 0; 1381 } 1382 1383 static int 1384 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn, 1385 __be64 *sw_action, 1386 __be64 *hw_action, 1387 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1388 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1389 { 1390 u8 action; 1391 int ret; 1392 1393 *hw_action = 0; 1394 *ret_src_hw_info = NULL; 1395 1396 /* Get SW modify action type */ 1397 action = MLX5_GET(set_action_in, sw_action, action_type); 1398 1399 switch (action) { 1400 case MLX5_ACTION_TYPE_SET: 1401 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action, 1402 hw_action, 1403 ret_dst_hw_info); 1404 break; 1405 1406 case MLX5_ACTION_TYPE_ADD: 1407 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action, 1408 hw_action, 1409 ret_dst_hw_info); 1410 break; 1411 1412 case MLX5_ACTION_TYPE_COPY: 1413 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action, 1414 hw_action, 1415 ret_dst_hw_info, 1416 ret_src_hw_info); 1417 break; 1418 1419 default: 1420 mlx5dr_info(dmn, "Unsupported action_type for modify action\n"); 1421 ret = -EOPNOTSUPP; 1422 } 1423 1424 return ret; 1425 } 1426 1427 static int 1428 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action, 1429 const __be64 *sw_action) 1430 { 1431 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1432 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1433 1434 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1435 action->rewrite->allow_rx = 0; 1436 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1437 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1438 sw_field); 1439 return -EINVAL; 1440 } 1441 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1442 action->rewrite->allow_tx = 0; 1443 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1444 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1445 sw_field); 1446 return -EINVAL; 1447 } 1448 } 1449 1450 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1451 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n"); 1452 return -EINVAL; 1453 } 1454 1455 return 0; 1456 } 1457 1458 static int 1459 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action, 1460 const __be64 *sw_action) 1461 { 1462 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1463 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1464 1465 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL && 1466 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT && 1467 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM && 1468 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) { 1469 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", 1470 sw_field); 1471 return -EINVAL; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int 1478 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action, 1479 const __be64 *sw_action) 1480 { 1481 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1482 u16 sw_fields[2]; 1483 int i; 1484 1485 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field); 1486 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field); 1487 1488 for (i = 0; i < 2; i++) { 1489 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1490 action->rewrite->allow_rx = 0; 1491 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1492 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1493 sw_fields[i]); 1494 return -EINVAL; 1495 } 1496 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1497 action->rewrite->allow_tx = 0; 1498 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1499 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1500 sw_fields[i]); 1501 return -EINVAL; 1502 } 1503 } 1504 } 1505 1506 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1507 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n"); 1508 return -EINVAL; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int 1515 dr_action_modify_check_field_limitation(struct mlx5dr_action *action, 1516 const __be64 *sw_action) 1517 { 1518 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1519 u8 action_type; 1520 int ret; 1521 1522 action_type = MLX5_GET(set_action_in, sw_action, action_type); 1523 1524 switch (action_type) { 1525 case MLX5_ACTION_TYPE_SET: 1526 ret = dr_action_modify_check_set_field_limitation(action, 1527 sw_action); 1528 break; 1529 1530 case MLX5_ACTION_TYPE_ADD: 1531 ret = dr_action_modify_check_add_field_limitation(action, 1532 sw_action); 1533 break; 1534 1535 case MLX5_ACTION_TYPE_COPY: 1536 ret = dr_action_modify_check_copy_field_limitation(action, 1537 sw_action); 1538 break; 1539 1540 default: 1541 mlx5dr_info(dmn, "Unsupported action %d modify action\n", 1542 action_type); 1543 ret = -EOPNOTSUPP; 1544 } 1545 1546 return ret; 1547 } 1548 1549 static bool 1550 dr_action_modify_check_is_ttl_modify(const void *sw_action) 1551 { 1552 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1553 1554 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL; 1555 } 1556 1557 static bool dr_action_modify_ttl_ignore(struct mlx5dr_domain *dmn) 1558 { 1559 return !mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps) && 1560 !MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify); 1561 } 1562 1563 static int dr_actions_convert_modify_header(struct mlx5dr_action *action, 1564 u32 max_hw_actions, 1565 u32 num_sw_actions, 1566 __be64 sw_actions[], 1567 __be64 hw_actions[], 1568 u32 *num_hw_actions, 1569 bool *modify_ttl) 1570 { 1571 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1572 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1573 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1574 int ret, i, hw_idx = 0; 1575 __be64 *sw_action; 1576 __be64 hw_action; 1577 u16 hw_field = 0; 1578 u32 l3_type = 0; 1579 u32 l4_type = 0; 1580 1581 *modify_ttl = false; 1582 1583 action->rewrite->allow_rx = 1; 1584 action->rewrite->allow_tx = 1; 1585 1586 for (i = 0; i < num_sw_actions; i++) { 1587 sw_action = &sw_actions[i]; 1588 1589 ret = dr_action_modify_check_field_limitation(action, 1590 sw_action); 1591 if (ret) 1592 return ret; 1593 1594 if (!(*modify_ttl) && 1595 dr_action_modify_check_is_ttl_modify(sw_action)) { 1596 if (dr_action_modify_ttl_ignore(dmn)) 1597 continue; 1598 1599 *modify_ttl = true; 1600 } 1601 1602 /* Convert SW action to HW action */ 1603 ret = dr_action_modify_sw_to_hw(dmn, 1604 sw_action, 1605 &hw_action, 1606 &hw_dst_action_info, 1607 &hw_src_action_info); 1608 if (ret) 1609 return ret; 1610 1611 /* Due to a HW limitation we cannot modify 2 different L3 types */ 1612 if (l3_type && hw_dst_action_info->l3_type && 1613 hw_dst_action_info->l3_type != l3_type) { 1614 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n"); 1615 return -EINVAL; 1616 } 1617 if (hw_dst_action_info->l3_type) 1618 l3_type = hw_dst_action_info->l3_type; 1619 1620 /* Due to a HW limitation we cannot modify two different L4 types */ 1621 if (l4_type && hw_dst_action_info->l4_type && 1622 hw_dst_action_info->l4_type != l4_type) { 1623 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n"); 1624 return -EINVAL; 1625 } 1626 if (hw_dst_action_info->l4_type) 1627 l4_type = hw_dst_action_info->l4_type; 1628 1629 /* HW reads and executes two actions at once this means we 1630 * need to create a gap if two actions access the same field 1631 */ 1632 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field || 1633 (hw_src_action_info && 1634 hw_field == hw_src_action_info->hw_field))) { 1635 /* Check if after gap insertion the total number of HW 1636 * modify actions doesn't exceeds the limit 1637 */ 1638 hw_idx++; 1639 if (hw_idx >= max_hw_actions) { 1640 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n"); 1641 return -EINVAL; 1642 } 1643 } 1644 hw_field = hw_dst_action_info->hw_field; 1645 1646 hw_actions[hw_idx] = hw_action; 1647 hw_idx++; 1648 } 1649 1650 /* if the resulting HW actions list is empty, add NOP action */ 1651 if (!hw_idx) 1652 hw_idx++; 1653 1654 *num_hw_actions = hw_idx; 1655 1656 return 0; 1657 } 1658 1659 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn, 1660 size_t actions_sz, 1661 __be64 actions[], 1662 struct mlx5dr_action *action) 1663 { 1664 struct mlx5dr_icm_chunk *chunk; 1665 u32 max_hw_actions; 1666 u32 num_hw_actions; 1667 u32 num_sw_actions; 1668 __be64 *hw_actions; 1669 bool modify_ttl; 1670 int ret; 1671 1672 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE; 1673 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16); 1674 1675 if (num_sw_actions > max_hw_actions) { 1676 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n", 1677 num_sw_actions, max_hw_actions); 1678 return -EINVAL; 1679 } 1680 1681 chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16); 1682 if (!chunk) 1683 return -ENOMEM; 1684 1685 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL); 1686 if (!hw_actions) { 1687 ret = -ENOMEM; 1688 goto free_chunk; 1689 } 1690 1691 ret = dr_actions_convert_modify_header(action, 1692 max_hw_actions, 1693 num_sw_actions, 1694 actions, 1695 hw_actions, 1696 &num_hw_actions, 1697 &modify_ttl); 1698 if (ret) 1699 goto free_hw_actions; 1700 1701 action->rewrite->chunk = chunk; 1702 action->rewrite->modify_ttl = modify_ttl; 1703 action->rewrite->data = (u8 *)hw_actions; 1704 action->rewrite->num_of_actions = num_hw_actions; 1705 action->rewrite->index = (chunk->icm_addr - 1706 dmn->info.caps.hdr_modify_icm_addr) / 1707 ACTION_CACHE_LINE_SIZE; 1708 1709 ret = mlx5dr_send_postsend_action(dmn, action); 1710 if (ret) 1711 goto free_hw_actions; 1712 1713 return 0; 1714 1715 free_hw_actions: 1716 kfree(hw_actions); 1717 free_chunk: 1718 mlx5dr_icm_free_chunk(chunk); 1719 return ret; 1720 } 1721 1722 struct mlx5dr_action * 1723 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn, 1724 u32 flags, 1725 size_t actions_sz, 1726 __be64 actions[]) 1727 { 1728 struct mlx5dr_action *action; 1729 int ret = 0; 1730 1731 refcount_inc(&dmn->refcount); 1732 1733 if (actions_sz % DR_MODIFY_ACTION_SIZE) { 1734 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n"); 1735 goto dec_ref; 1736 } 1737 1738 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR); 1739 if (!action) 1740 goto dec_ref; 1741 1742 action->rewrite->dmn = dmn; 1743 1744 ret = dr_action_create_modify_action(dmn, 1745 actions_sz, 1746 actions, 1747 action); 1748 if (ret) { 1749 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret); 1750 goto free_action; 1751 } 1752 1753 return action; 1754 1755 free_action: 1756 kfree(action); 1757 dec_ref: 1758 refcount_dec(&dmn->refcount); 1759 return NULL; 1760 } 1761 1762 struct mlx5dr_action * 1763 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn, 1764 u16 vport, u8 vhca_id_valid, 1765 u16 vhca_id) 1766 { 1767 struct mlx5dr_cmd_vport_cap *vport_cap; 1768 struct mlx5dr_domain *vport_dmn; 1769 struct mlx5dr_action *action; 1770 u8 peer_vport; 1771 1772 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi); 1773 vport_dmn = peer_vport ? dmn->peer_dmn : dmn; 1774 if (!vport_dmn) { 1775 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n"); 1776 return NULL; 1777 } 1778 1779 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1780 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n"); 1781 return NULL; 1782 } 1783 1784 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport); 1785 if (!vport_cap) { 1786 mlx5dr_err(dmn, 1787 "Failed to get vport 0x%x caps - vport is disabled or invalid\n", 1788 vport); 1789 return NULL; 1790 } 1791 1792 action = dr_action_create_generic(DR_ACTION_TYP_VPORT); 1793 if (!action) 1794 return NULL; 1795 1796 action->vport->dmn = vport_dmn; 1797 action->vport->caps = vport_cap; 1798 1799 return action; 1800 } 1801 1802 int mlx5dr_action_destroy(struct mlx5dr_action *action) 1803 { 1804 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1)) 1805 return -EBUSY; 1806 1807 switch (action->action_type) { 1808 case DR_ACTION_TYP_FT: 1809 if (action->dest_tbl->is_fw_tbl) 1810 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount); 1811 else 1812 refcount_dec(&action->dest_tbl->tbl->refcount); 1813 1814 if (action->dest_tbl->is_fw_tbl && 1815 action->dest_tbl->fw_tbl.num_of_ref_actions) { 1816 struct mlx5dr_action **ref_actions; 1817 int i; 1818 1819 ref_actions = action->dest_tbl->fw_tbl.ref_actions; 1820 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++) 1821 refcount_dec(&ref_actions[i]->refcount); 1822 1823 kfree(ref_actions); 1824 1825 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn, 1826 action->dest_tbl->fw_tbl.id, 1827 action->dest_tbl->fw_tbl.group_id); 1828 } 1829 break; 1830 case DR_ACTION_TYP_TNL_L2_TO_L2: 1831 case DR_ACTION_TYP_REMOVE_HDR: 1832 refcount_dec(&action->reformat->dmn->refcount); 1833 break; 1834 case DR_ACTION_TYP_TNL_L3_TO_L2: 1835 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1836 refcount_dec(&action->rewrite->dmn->refcount); 1837 break; 1838 case DR_ACTION_TYP_L2_TO_TNL_L2: 1839 case DR_ACTION_TYP_L2_TO_TNL_L3: 1840 case DR_ACTION_TYP_INSERT_HDR: 1841 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev, 1842 action->reformat->id); 1843 refcount_dec(&action->reformat->dmn->refcount); 1844 break; 1845 case DR_ACTION_TYP_MODIFY_HDR: 1846 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1847 kfree(action->rewrite->data); 1848 refcount_dec(&action->rewrite->dmn->refcount); 1849 break; 1850 case DR_ACTION_TYP_SAMPLER: 1851 refcount_dec(&action->sampler->dmn->refcount); 1852 break; 1853 default: 1854 break; 1855 } 1856 1857 kfree(action); 1858 return 0; 1859 } 1860