1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "dr_types.h" 5 #include "dr_ste.h" 6 7 enum dr_action_domain { 8 DR_ACTION_DOMAIN_NIC_INGRESS, 9 DR_ACTION_DOMAIN_NIC_EGRESS, 10 DR_ACTION_DOMAIN_FDB_INGRESS, 11 DR_ACTION_DOMAIN_FDB_EGRESS, 12 DR_ACTION_DOMAIN_MAX, 13 }; 14 15 enum dr_action_valid_state { 16 DR_ACTION_STATE_ERR, 17 DR_ACTION_STATE_NO_ACTION, 18 DR_ACTION_STATE_ENCAP, 19 DR_ACTION_STATE_DECAP, 20 DR_ACTION_STATE_MODIFY_HDR, 21 DR_ACTION_STATE_POP_VLAN, 22 DR_ACTION_STATE_PUSH_VLAN, 23 DR_ACTION_STATE_NON_TERM, 24 DR_ACTION_STATE_TERM, 25 DR_ACTION_STATE_ASO, 26 DR_ACTION_STATE_MAX, 27 }; 28 29 static const char * const action_type_to_str[] = { 30 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2", 31 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2", 32 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2", 33 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3", 34 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP", 35 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP", 36 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT", 37 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR", 38 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG", 39 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR", 40 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT", 41 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN", 42 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN", 43 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER", 44 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR", 45 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR", 46 [DR_ACTION_TYP_ASO_FLOW_METER] = "DR_ACTION_TYP_ASO_FLOW_METER", 47 [DR_ACTION_TYP_RANGE] = "DR_ACTION_TYP_RANGE", 48 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN", 49 }; 50 51 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id) 52 { 53 if (action_id > DR_ACTION_TYP_MAX) 54 action_id = DR_ACTION_TYP_MAX; 55 return action_type_to_str[action_id]; 56 } 57 58 static const enum dr_action_valid_state 59 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = { 60 [DR_ACTION_DOMAIN_NIC_INGRESS] = { 61 [DR_ACTION_STATE_NO_ACTION] = { 62 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 63 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 64 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 65 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 66 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 67 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 68 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 69 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 70 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 71 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 72 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 73 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 74 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 75 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 76 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 77 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 78 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 79 }, 80 [DR_ACTION_STATE_DECAP] = { 81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 82 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 83 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 84 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 85 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 86 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP, 87 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 88 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 89 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 90 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 91 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 92 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 93 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 94 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 95 }, 96 [DR_ACTION_STATE_ENCAP] = { 97 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 98 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 99 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 100 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 101 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 102 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP, 103 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 104 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 105 }, 106 [DR_ACTION_STATE_MODIFY_HDR] = { 107 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 108 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 109 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 110 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 111 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 112 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR, 113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 116 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 118 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 119 }, 120 [DR_ACTION_STATE_POP_VLAN] = { 121 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 122 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 123 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 124 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 125 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 126 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN, 127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 128 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 129 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 130 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 131 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 132 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 133 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 134 }, 135 [DR_ACTION_STATE_PUSH_VLAN] = { 136 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 137 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 138 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 139 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 140 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN, 141 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 142 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 143 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 144 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 145 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 146 }, 147 [DR_ACTION_STATE_NON_TERM] = { 148 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 149 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 151 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 152 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 153 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 154 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 155 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 156 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 157 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 158 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 159 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 160 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 161 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 162 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 163 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 164 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 165 }, 166 [DR_ACTION_STATE_ASO] = { 167 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 168 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 169 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 170 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 171 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 172 }, 173 [DR_ACTION_STATE_TERM] = { 174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 175 }, 176 }, 177 [DR_ACTION_DOMAIN_NIC_EGRESS] = { 178 [DR_ACTION_STATE_NO_ACTION] = { 179 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 180 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 181 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 182 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 183 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 184 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 185 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 186 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 187 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 188 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 189 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 190 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 191 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 192 }, 193 [DR_ACTION_STATE_DECAP] = { 194 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 195 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 196 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 197 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 198 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 199 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 200 }, 201 [DR_ACTION_STATE_ENCAP] = { 202 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 203 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 204 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 205 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 206 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 207 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 208 }, 209 [DR_ACTION_STATE_MODIFY_HDR] = { 210 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 211 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 212 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 213 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 214 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 215 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 216 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 217 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 218 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 219 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 220 }, 221 [DR_ACTION_STATE_POP_VLAN] = { 222 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 223 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 224 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 225 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 226 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 227 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 228 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 229 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 230 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 231 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 232 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 233 }, 234 [DR_ACTION_STATE_PUSH_VLAN] = { 235 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 236 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 237 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 238 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 239 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 240 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 241 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 242 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 243 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 244 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 245 }, 246 [DR_ACTION_STATE_NON_TERM] = { 247 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 248 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 249 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 250 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 251 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 252 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 253 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 254 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 255 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 256 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 257 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 258 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 259 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 260 }, 261 [DR_ACTION_STATE_ASO] = { 262 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 263 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 264 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 265 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 266 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 267 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 268 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 269 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 270 }, 271 [DR_ACTION_STATE_TERM] = { 272 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 273 }, 274 }, 275 [DR_ACTION_DOMAIN_FDB_INGRESS] = { 276 [DR_ACTION_STATE_NO_ACTION] = { 277 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 278 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 279 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 280 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 281 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 282 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 283 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 284 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 285 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 286 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 287 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 288 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 289 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 290 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 291 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 292 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 293 }, 294 [DR_ACTION_STATE_DECAP] = { 295 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 296 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 297 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 298 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 299 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 300 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 301 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 302 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 303 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 304 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 305 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 306 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 307 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 308 }, 309 [DR_ACTION_STATE_ENCAP] = { 310 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 311 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 312 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 313 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 314 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 315 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 316 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 317 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 318 }, 319 [DR_ACTION_STATE_MODIFY_HDR] = { 320 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 321 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 322 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 323 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 324 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 325 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 326 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 327 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 328 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 329 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 330 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 331 }, 332 [DR_ACTION_STATE_POP_VLAN] = { 333 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 334 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 335 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 336 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 337 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 338 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 339 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 340 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 341 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 342 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 343 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 344 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 345 }, 346 [DR_ACTION_STATE_PUSH_VLAN] = { 347 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 348 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 349 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 350 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 351 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 352 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 353 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 354 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 355 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 356 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 357 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 358 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 359 }, 360 [DR_ACTION_STATE_NON_TERM] = { 361 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 362 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 363 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 364 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 365 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 366 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 367 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 368 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 369 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 370 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 371 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 372 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 373 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 374 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 375 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 376 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 377 }, 378 [DR_ACTION_STATE_ASO] = { 379 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 380 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 381 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 382 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 383 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 384 }, 385 [DR_ACTION_STATE_TERM] = { 386 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 387 }, 388 }, 389 [DR_ACTION_DOMAIN_FDB_EGRESS] = { 390 [DR_ACTION_STATE_NO_ACTION] = { 391 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 392 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 393 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 394 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 395 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 396 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 397 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 398 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 399 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 400 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 401 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 402 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 403 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 404 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 405 }, 406 [DR_ACTION_STATE_DECAP] = { 407 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 408 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 409 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 410 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 411 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 412 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 413 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 414 }, 415 [DR_ACTION_STATE_ENCAP] = { 416 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 417 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 418 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 419 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 420 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 421 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 422 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 423 }, 424 [DR_ACTION_STATE_MODIFY_HDR] = { 425 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 426 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 427 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 428 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 429 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 430 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 431 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 432 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 433 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 434 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 435 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 436 }, 437 [DR_ACTION_STATE_POP_VLAN] = { 438 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 439 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 440 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 441 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 442 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 443 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 444 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 445 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 446 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 447 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 448 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 449 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 450 }, 451 [DR_ACTION_STATE_PUSH_VLAN] = { 452 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 453 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 454 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 455 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 456 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 457 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 458 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 459 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 460 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 461 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 462 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 463 }, 464 [DR_ACTION_STATE_NON_TERM] = { 465 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 466 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 467 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 468 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 469 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 470 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 471 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 472 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 473 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 474 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 475 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 476 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 477 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 478 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 479 }, 480 [DR_ACTION_STATE_ASO] = { 481 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 482 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 483 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 484 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 485 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 486 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 487 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 488 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 489 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 490 }, 491 [DR_ACTION_STATE_TERM] = { 492 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 493 }, 494 }, 495 }; 496 497 static int 498 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type, 499 enum mlx5dr_action_type *action_type) 500 { 501 switch (reformat_type) { 502 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2: 503 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2; 504 break; 505 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2: 506 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2; 507 break; 508 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2: 509 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2; 510 break; 511 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3: 512 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3; 513 break; 514 case DR_ACTION_REFORMAT_TYP_INSERT_HDR: 515 *action_type = DR_ACTION_TYP_INSERT_HDR; 516 break; 517 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR: 518 *action_type = DR_ACTION_TYP_REMOVE_HDR; 519 break; 520 default: 521 return -EINVAL; 522 } 523 524 return 0; 525 } 526 527 /* Apply the actions on the rule STE array starting from the last_ste. 528 * Actions might require more than one STE, new_num_stes will return 529 * the new size of the STEs array, rule with actions. 530 */ 531 static void dr_actions_apply(struct mlx5dr_domain *dmn, 532 enum mlx5dr_domain_nic_type nic_type, 533 u8 *action_type_set, 534 u8 *last_ste, 535 struct mlx5dr_ste_actions_attr *attr, 536 u32 *new_num_stes) 537 { 538 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; 539 u32 added_stes = 0; 540 541 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 542 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set, 543 last_ste, attr, &added_stes); 544 else 545 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set, 546 last_ste, attr, &added_stes); 547 548 *new_num_stes += added_stes; 549 } 550 551 static enum dr_action_domain 552 dr_action_get_action_domain(enum mlx5dr_domain_type domain, 553 enum mlx5dr_domain_nic_type nic_type) 554 { 555 switch (domain) { 556 case MLX5DR_DOMAIN_TYPE_NIC_RX: 557 return DR_ACTION_DOMAIN_NIC_INGRESS; 558 case MLX5DR_DOMAIN_TYPE_NIC_TX: 559 return DR_ACTION_DOMAIN_NIC_EGRESS; 560 case MLX5DR_DOMAIN_TYPE_FDB: 561 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 562 return DR_ACTION_DOMAIN_FDB_INGRESS; 563 return DR_ACTION_DOMAIN_FDB_EGRESS; 564 default: 565 WARN_ON(true); 566 return DR_ACTION_DOMAIN_MAX; 567 } 568 } 569 570 static 571 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain, 572 u32 action_type, 573 u32 *state) 574 { 575 u32 cur_state = *state; 576 577 /* Check action state machine is valid */ 578 *state = next_action_state[action_domain][cur_state][action_type]; 579 580 if (*state == DR_ACTION_STATE_ERR) 581 return -EOPNOTSUPP; 582 583 return 0; 584 } 585 586 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, 587 struct mlx5dr_action *dest_action, 588 u64 *final_icm_addr) 589 { 590 int ret; 591 592 switch (dest_action->action_type) { 593 case DR_ACTION_TYP_FT: 594 /* Allow destination flow table only if table is a terminating 595 * table, since there is an *assumption* that in such case FW 596 * will recalculate the CS. 597 */ 598 if (dest_action->dest_tbl->is_fw_tbl) { 599 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr; 600 } else { 601 mlx5dr_dbg(dmn, 602 "Destination FT should be terminating when modify TTL is used\n"); 603 return -EINVAL; 604 } 605 break; 606 607 case DR_ACTION_TYP_VPORT: 608 /* If destination is vport we will get the FW flow table 609 * that recalculates the CS and forwards to the vport. 610 */ 611 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn, 612 dest_action->vport->caps->num, 613 final_icm_addr); 614 if (ret) { 615 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); 616 return ret; 617 } 618 break; 619 620 default: 621 break; 622 } 623 624 return 0; 625 } 626 627 static void dr_action_modify_ttl_adjust(struct mlx5dr_domain *dmn, 628 struct mlx5dr_ste_actions_attr *attr, 629 bool rx_rule, 630 bool *recalc_cs_required) 631 { 632 *recalc_cs_required = false; 633 634 /* if device supports csum recalculation - no adjustment needed */ 635 if (mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps)) 636 return; 637 638 /* no adjustment needed on TX rules */ 639 if (!rx_rule) 640 return; 641 642 if (!MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify)) { 643 /* Ignore the modify TTL action. 644 * It is always kept as last HW action. 645 */ 646 attr->modify_actions--; 647 return; 648 } 649 650 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 651 /* Due to a HW bug on some devices, modifying TTL on RX flows 652 * will cause an incorrect checksum calculation. In such cases 653 * we will use a FW table to recalculate the checksum. 654 */ 655 *recalc_cs_required = true; 656 } 657 658 static void dr_action_print_sequence(struct mlx5dr_domain *dmn, 659 struct mlx5dr_action *actions[], 660 int last_idx) 661 { 662 int i; 663 664 for (i = 0; i <= last_idx; i++) 665 mlx5dr_err(dmn, "< %s (%d) > ", 666 dr_action_id_to_str(actions[i]->action_type), 667 actions[i]->action_type); 668 } 669 670 static int dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher *matcher, 671 struct mlx5dr_action_dest_tbl *dest_tbl, 672 bool is_rx_rule, 673 u64 *final_icm_addr) 674 { 675 struct mlx5dr_cmd_query_flow_table_details output; 676 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 677 int ret; 678 679 if (!dest_tbl->fw_tbl.rx_icm_addr) { 680 ret = mlx5dr_cmd_query_flow_table(dmn->mdev, 681 dest_tbl->fw_tbl.type, 682 dest_tbl->fw_tbl.id, 683 &output); 684 if (ret) { 685 mlx5dr_err(dmn, 686 "Failed mlx5_cmd_query_flow_table ret: %d\n", 687 ret); 688 return ret; 689 } 690 691 dest_tbl->fw_tbl.tx_icm_addr = output.sw_owner_icm_root_1; 692 dest_tbl->fw_tbl.rx_icm_addr = output.sw_owner_icm_root_0; 693 } 694 695 *final_icm_addr = is_rx_rule ? dest_tbl->fw_tbl.rx_icm_addr : 696 dest_tbl->fw_tbl.tx_icm_addr; 697 return 0; 698 } 699 700 static int dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher *matcher, 701 struct mlx5dr_action_dest_tbl *dest_tbl, 702 bool is_rx_rule, 703 u64 *final_icm_addr) 704 { 705 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 706 struct mlx5dr_icm_chunk *chunk; 707 708 if (dest_tbl->tbl->dmn != dmn) { 709 mlx5dr_err(dmn, 710 "Destination table belongs to a different domain\n"); 711 return -EINVAL; 712 } 713 714 if (dest_tbl->tbl->level <= matcher->tbl->level) { 715 mlx5_core_dbg_once(dmn->mdev, 716 "Connecting table to a lower/same level destination table\n"); 717 mlx5dr_dbg(dmn, 718 "Connecting table at level %d to a destination table at level %d\n", 719 matcher->tbl->level, 720 dest_tbl->tbl->level); 721 } 722 723 chunk = is_rx_rule ? dest_tbl->tbl->rx.s_anchor->chunk : 724 dest_tbl->tbl->tx.s_anchor->chunk; 725 726 *final_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(chunk); 727 return 0; 728 } 729 730 static int dr_action_get_dest_tbl_addr(struct mlx5dr_matcher *matcher, 731 struct mlx5dr_action_dest_tbl *dest_tbl, 732 bool is_rx_rule, 733 u64 *final_icm_addr) 734 { 735 if (dest_tbl->is_fw_tbl) 736 return dr_action_get_dest_fw_tbl_addr(matcher, 737 dest_tbl, 738 is_rx_rule, 739 final_icm_addr); 740 741 return dr_action_get_dest_sw_tbl_addr(matcher, 742 dest_tbl, 743 is_rx_rule, 744 final_icm_addr); 745 } 746 747 #define WITH_VLAN_NUM_HW_ACTIONS 6 748 749 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 750 struct mlx5dr_matcher_rx_tx *nic_matcher, 751 struct mlx5dr_action *actions[], 752 u32 num_actions, 753 u8 *ste_arr, 754 u32 *new_hw_ste_arr_sz) 755 { 756 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn; 757 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX; 758 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 759 u8 action_type_set[DR_ACTION_TYP_MAX] = {}; 760 struct mlx5dr_ste_actions_attr attr = {}; 761 struct mlx5dr_action *dest_action = NULL; 762 u32 state = DR_ACTION_STATE_NO_ACTION; 763 enum dr_action_domain action_domain; 764 bool recalc_cs_required = false; 765 u8 *last_ste; 766 int i, ret; 767 768 attr.gvmi = dmn->info.caps.gvmi; 769 attr.hit_gvmi = dmn->info.caps.gvmi; 770 attr.final_icm_addr = nic_dmn->default_icm_addr; 771 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type); 772 773 for (i = 0; i < num_actions; i++) { 774 struct mlx5dr_action *action; 775 int max_actions_type = 1; 776 u32 action_type; 777 778 action = actions[i]; 779 action_type = action->action_type; 780 781 switch (action_type) { 782 case DR_ACTION_TYP_DROP: 783 attr.final_icm_addr = nic_dmn->drop_icm_addr; 784 break; 785 case DR_ACTION_TYP_FT: 786 dest_action = action; 787 ret = dr_action_get_dest_tbl_addr(matcher, action->dest_tbl, 788 rx_rule, &attr.final_icm_addr); 789 if (ret) 790 return ret; 791 break; 792 case DR_ACTION_TYP_RANGE: 793 ret = dr_action_get_dest_tbl_addr(matcher, 794 action->range->hit_tbl_action->dest_tbl, 795 rx_rule, &attr.final_icm_addr); 796 if (ret) 797 return ret; 798 799 ret = dr_action_get_dest_tbl_addr(matcher, 800 action->range->miss_tbl_action->dest_tbl, 801 rx_rule, &attr.range.miss_icm_addr); 802 if (ret) 803 return ret; 804 805 attr.range.definer_id = action->range->definer_id; 806 attr.range.min = action->range->min; 807 attr.range.max = action->range->max; 808 break; 809 case DR_ACTION_TYP_QP: 810 mlx5dr_info(dmn, "Domain doesn't support QP\n"); 811 return -EOPNOTSUPP; 812 case DR_ACTION_TYP_CTR: 813 attr.ctr_id = action->ctr->ctr_id + 814 action->ctr->offset; 815 break; 816 case DR_ACTION_TYP_TAG: 817 attr.flow_tag = action->flow_tag->flow_tag; 818 break; 819 case DR_ACTION_TYP_TNL_L2_TO_L2: 820 break; 821 case DR_ACTION_TYP_TNL_L3_TO_L2: 822 if (action->rewrite->ptrn && action->rewrite->arg) { 823 attr.decap_index = mlx5dr_arg_get_obj_id(action->rewrite->arg); 824 attr.decap_actions = action->rewrite->ptrn->num_of_actions; 825 attr.decap_pat_idx = action->rewrite->ptrn->index; 826 } else { 827 attr.decap_index = action->rewrite->index; 828 attr.decap_actions = action->rewrite->num_of_actions; 829 attr.decap_with_vlan = 830 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS; 831 attr.decap_pat_idx = MLX5DR_INVALID_PATTERN_INDEX; 832 } 833 break; 834 case DR_ACTION_TYP_MODIFY_HDR: 835 if (action->rewrite->single_action_opt) { 836 attr.modify_actions = action->rewrite->num_of_actions; 837 attr.single_modify_action = action->rewrite->data; 838 } else { 839 if (action->rewrite->ptrn && action->rewrite->arg) { 840 attr.modify_index = 841 mlx5dr_arg_get_obj_id(action->rewrite->arg); 842 attr.modify_actions = action->rewrite->ptrn->num_of_actions; 843 attr.modify_pat_idx = action->rewrite->ptrn->index; 844 } else { 845 attr.modify_index = action->rewrite->index; 846 attr.modify_actions = action->rewrite->num_of_actions; 847 attr.modify_pat_idx = MLX5DR_INVALID_PATTERN_INDEX; 848 } 849 } 850 if (action->rewrite->modify_ttl) 851 dr_action_modify_ttl_adjust(dmn, &attr, rx_rule, 852 &recalc_cs_required); 853 break; 854 case DR_ACTION_TYP_L2_TO_TNL_L2: 855 case DR_ACTION_TYP_L2_TO_TNL_L3: 856 if (rx_rule && 857 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) { 858 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n"); 859 return -EOPNOTSUPP; 860 } 861 attr.reformat.size = action->reformat->size; 862 attr.reformat.id = action->reformat->id; 863 break; 864 case DR_ACTION_TYP_SAMPLER: 865 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr : 866 action->sampler->tx_icm_addr; 867 break; 868 case DR_ACTION_TYP_VPORT: 869 attr.hit_gvmi = action->vport->caps->vhca_gvmi; 870 dest_action = action; 871 attr.final_icm_addr = rx_rule ? 872 action->vport->caps->icm_address_rx : 873 action->vport->caps->icm_address_tx; 874 break; 875 case DR_ACTION_TYP_POP_VLAN: 876 if (!rx_rule && !(dmn->ste_ctx->actions_caps & 877 DR_STE_CTX_ACTION_CAP_TX_POP)) { 878 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n"); 879 return -EOPNOTSUPP; 880 } 881 882 max_actions_type = MLX5DR_MAX_VLANS; 883 attr.vlans.count++; 884 break; 885 case DR_ACTION_TYP_PUSH_VLAN: 886 if (rx_rule && !(dmn->ste_ctx->actions_caps & 887 DR_STE_CTX_ACTION_CAP_RX_PUSH)) { 888 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n"); 889 return -EOPNOTSUPP; 890 } 891 892 max_actions_type = MLX5DR_MAX_VLANS; 893 if (attr.vlans.count == MLX5DR_MAX_VLANS) { 894 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n"); 895 return -EINVAL; 896 } 897 898 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr; 899 break; 900 case DR_ACTION_TYP_INSERT_HDR: 901 case DR_ACTION_TYP_REMOVE_HDR: 902 attr.reformat.size = action->reformat->size; 903 attr.reformat.id = action->reformat->id; 904 attr.reformat.param_0 = action->reformat->param_0; 905 attr.reformat.param_1 = action->reformat->param_1; 906 break; 907 case DR_ACTION_TYP_ASO_FLOW_METER: 908 attr.aso_flow_meter.obj_id = action->aso->obj_id; 909 attr.aso_flow_meter.offset = action->aso->offset; 910 attr.aso_flow_meter.dest_reg_id = action->aso->dest_reg_id; 911 attr.aso_flow_meter.init_color = action->aso->init_color; 912 break; 913 default: 914 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type); 915 return -EINVAL; 916 } 917 918 /* Check action duplication */ 919 if (++action_type_set[action_type] > max_actions_type) { 920 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n", 921 action_type, max_actions_type); 922 return -EINVAL; 923 } 924 925 /* Check action state machine is valid */ 926 if (dr_action_validate_and_get_next_state(action_domain, 927 action_type, 928 &state)) { 929 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:", 930 attr.gvmi, rx_rule); 931 dr_action_print_sequence(dmn, actions, i); 932 return -EOPNOTSUPP; 933 } 934 } 935 936 *new_hw_ste_arr_sz = nic_matcher->num_of_builders; 937 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1); 938 939 if (recalc_cs_required && dest_action) { 940 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr); 941 if (ret) { 942 mlx5dr_err(dmn, 943 "Failed to handle checksum recalculation err %d\n", 944 ret); 945 return ret; 946 } 947 } 948 949 dr_actions_apply(dmn, 950 nic_dmn->type, 951 action_type_set, 952 last_ste, 953 &attr, 954 new_hw_ste_arr_sz); 955 956 return 0; 957 } 958 959 static unsigned int action_size[DR_ACTION_TYP_MAX] = { 960 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat), 961 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat), 962 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite), 963 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat), 964 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl), 965 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr), 966 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag), 967 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite), 968 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport), 969 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan), 970 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat), 971 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat), 972 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler), 973 [DR_ACTION_TYP_ASO_FLOW_METER] = sizeof(struct mlx5dr_action_aso_flow_meter), 974 [DR_ACTION_TYP_RANGE] = sizeof(struct mlx5dr_action_range), 975 }; 976 977 static struct mlx5dr_action * 978 dr_action_create_generic(enum mlx5dr_action_type action_type) 979 { 980 struct mlx5dr_action *action; 981 int extra_size; 982 983 if (action_type < DR_ACTION_TYP_MAX) 984 extra_size = action_size[action_type]; 985 else 986 return NULL; 987 988 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL); 989 if (!action) 990 return NULL; 991 992 action->action_type = action_type; 993 refcount_set(&action->refcount, 1); 994 action->data = action + 1; 995 996 return action; 997 } 998 999 struct mlx5dr_action *mlx5dr_action_create_drop(void) 1000 { 1001 return dr_action_create_generic(DR_ACTION_TYP_DROP); 1002 } 1003 1004 struct mlx5dr_action * 1005 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num) 1006 { 1007 struct mlx5dr_action *action; 1008 1009 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1010 if (!action) 1011 return NULL; 1012 1013 action->dest_tbl->is_fw_tbl = true; 1014 action->dest_tbl->fw_tbl.dmn = dmn; 1015 action->dest_tbl->fw_tbl.id = table_num; 1016 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 1017 refcount_inc(&dmn->refcount); 1018 1019 return action; 1020 } 1021 1022 struct mlx5dr_action * 1023 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl) 1024 { 1025 struct mlx5dr_action *action; 1026 1027 refcount_inc(&tbl->refcount); 1028 1029 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1030 if (!action) 1031 goto dec_ref; 1032 1033 action->dest_tbl->tbl = tbl; 1034 1035 return action; 1036 1037 dec_ref: 1038 refcount_dec(&tbl->refcount); 1039 return NULL; 1040 } 1041 1042 static void dr_action_range_definer_fill(u16 *format_id, 1043 u8 *dw_selectors, 1044 u8 *byte_selectors, 1045 u8 *match_mask) 1046 { 1047 int i; 1048 1049 *format_id = MLX5_IFC_DEFINER_FORMAT_ID_SELECT; 1050 1051 dw_selectors[0] = MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN / 4; 1052 1053 for (i = 1; i < MLX5_IFC_DEFINER_DW_SELECTORS_NUM; i++) 1054 dw_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED; 1055 1056 for (i = 0; i < MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM; i++) 1057 byte_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED; 1058 1059 MLX5_SET(match_definer_match_mask, match_mask, 1060 match_dw_0, 0xffffUL << 16); 1061 } 1062 1063 static int dr_action_create_range_definer(struct mlx5dr_action *action) 1064 { 1065 u8 match_mask[MLX5_FLD_SZ_BYTES(match_definer, match_mask)] = {}; 1066 u8 byte_selectors[MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM] = {}; 1067 u8 dw_selectors[MLX5_IFC_DEFINER_DW_SELECTORS_NUM] = {}; 1068 struct mlx5dr_domain *dmn = action->range->dmn; 1069 u32 definer_id; 1070 u16 format_id; 1071 int ret; 1072 1073 dr_action_range_definer_fill(&format_id, 1074 dw_selectors, 1075 byte_selectors, 1076 match_mask); 1077 1078 ret = mlx5dr_definer_get(dmn, format_id, 1079 dw_selectors, byte_selectors, 1080 match_mask, &definer_id); 1081 if (ret) 1082 return ret; 1083 1084 action->range->definer_id = definer_id; 1085 return 0; 1086 } 1087 1088 static void dr_action_destroy_range_definer(struct mlx5dr_action *action) 1089 { 1090 mlx5dr_definer_put(action->range->dmn, action->range->definer_id); 1091 } 1092 1093 struct mlx5dr_action * 1094 mlx5dr_action_create_dest_match_range(struct mlx5dr_domain *dmn, 1095 u32 field, 1096 struct mlx5_flow_table *hit_ft, 1097 struct mlx5_flow_table *miss_ft, 1098 u32 min, 1099 u32 max) 1100 { 1101 struct mlx5dr_action *action; 1102 int ret; 1103 1104 if (!mlx5dr_supp_match_ranges(dmn->mdev)) { 1105 mlx5dr_dbg(dmn, "SELECT definer support is needed for match range\n"); 1106 return NULL; 1107 } 1108 1109 if (field != MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN || 1110 min > 0xffff || max > 0xffff) { 1111 mlx5dr_err(dmn, "Invalid match range parameters\n"); 1112 return NULL; 1113 } 1114 1115 action = dr_action_create_generic(DR_ACTION_TYP_RANGE); 1116 if (!action) 1117 return NULL; 1118 1119 action->range->hit_tbl_action = 1120 mlx5dr_is_fw_table(hit_ft) ? 1121 mlx5dr_action_create_dest_flow_fw_table(dmn, hit_ft) : 1122 mlx5dr_action_create_dest_table(hit_ft->fs_dr_table.dr_table); 1123 1124 if (!action->range->hit_tbl_action) 1125 goto free_action; 1126 1127 action->range->miss_tbl_action = 1128 mlx5dr_is_fw_table(miss_ft) ? 1129 mlx5dr_action_create_dest_flow_fw_table(dmn, miss_ft) : 1130 mlx5dr_action_create_dest_table(miss_ft->fs_dr_table.dr_table); 1131 1132 if (!action->range->miss_tbl_action) 1133 goto free_hit_tbl_action; 1134 1135 action->range->min = min; 1136 action->range->max = max; 1137 action->range->dmn = dmn; 1138 1139 ret = dr_action_create_range_definer(action); 1140 if (ret) 1141 goto free_miss_tbl_action; 1142 1143 /* No need to increase refcount on domain for this action, 1144 * the hit/miss table actions will do it internally. 1145 */ 1146 1147 return action; 1148 1149 free_miss_tbl_action: 1150 mlx5dr_action_destroy(action->range->miss_tbl_action); 1151 free_hit_tbl_action: 1152 mlx5dr_action_destroy(action->range->hit_tbl_action); 1153 free_action: 1154 kfree(action); 1155 1156 return NULL; 1157 } 1158 1159 struct mlx5dr_action * 1160 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn, 1161 struct mlx5dr_action_dest *dests, 1162 u32 num_of_dests, 1163 bool ignore_flow_level, 1164 u32 flow_source) 1165 { 1166 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests; 1167 struct mlx5dr_action **ref_actions; 1168 struct mlx5dr_action *action; 1169 bool reformat_req = false; 1170 u32 num_of_ref = 0; 1171 u32 ref_act_cnt; 1172 int ret; 1173 int i; 1174 1175 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1176 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n"); 1177 return NULL; 1178 } 1179 1180 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL); 1181 if (!hw_dests) 1182 return NULL; 1183 1184 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt))) 1185 goto free_hw_dests; 1186 1187 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL); 1188 if (!ref_actions) 1189 goto free_hw_dests; 1190 1191 for (i = 0; i < num_of_dests; i++) { 1192 struct mlx5dr_action *reformat_action = dests[i].reformat; 1193 struct mlx5dr_action *dest_action = dests[i].dest; 1194 1195 ref_actions[num_of_ref++] = dest_action; 1196 1197 switch (dest_action->action_type) { 1198 case DR_ACTION_TYP_VPORT: 1199 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID; 1200 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; 1201 hw_dests[i].vport.num = dest_action->vport->caps->num; 1202 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi; 1203 if (reformat_action) { 1204 reformat_req = true; 1205 hw_dests[i].vport.reformat_id = 1206 reformat_action->reformat->id; 1207 ref_actions[num_of_ref++] = reformat_action; 1208 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; 1209 } 1210 break; 1211 1212 case DR_ACTION_TYP_FT: 1213 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 1214 if (dest_action->dest_tbl->is_fw_tbl) 1215 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id; 1216 else 1217 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id; 1218 break; 1219 1220 default: 1221 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n"); 1222 goto free_ref_actions; 1223 } 1224 } 1225 1226 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1227 if (!action) 1228 goto free_ref_actions; 1229 1230 ret = mlx5dr_fw_create_md_tbl(dmn, 1231 hw_dests, 1232 num_of_dests, 1233 reformat_req, 1234 &action->dest_tbl->fw_tbl.id, 1235 &action->dest_tbl->fw_tbl.group_id, 1236 ignore_flow_level, 1237 flow_source); 1238 if (ret) 1239 goto free_action; 1240 1241 refcount_inc(&dmn->refcount); 1242 1243 for (i = 0; i < num_of_ref; i++) 1244 refcount_inc(&ref_actions[i]->refcount); 1245 1246 action->dest_tbl->is_fw_tbl = true; 1247 action->dest_tbl->fw_tbl.dmn = dmn; 1248 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 1249 action->dest_tbl->fw_tbl.ref_actions = ref_actions; 1250 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref; 1251 1252 kfree(hw_dests); 1253 1254 return action; 1255 1256 free_action: 1257 kfree(action); 1258 free_ref_actions: 1259 kfree(ref_actions); 1260 free_hw_dests: 1261 kfree(hw_dests); 1262 return NULL; 1263 } 1264 1265 struct mlx5dr_action * 1266 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn, 1267 struct mlx5_flow_table *ft) 1268 { 1269 struct mlx5dr_action *action; 1270 1271 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1272 if (!action) 1273 return NULL; 1274 1275 action->dest_tbl->is_fw_tbl = 1; 1276 action->dest_tbl->fw_tbl.type = ft->type; 1277 action->dest_tbl->fw_tbl.id = ft->id; 1278 action->dest_tbl->fw_tbl.dmn = dmn; 1279 1280 refcount_inc(&dmn->refcount); 1281 1282 return action; 1283 } 1284 1285 struct mlx5dr_action * 1286 mlx5dr_action_create_flow_counter(u32 counter_id) 1287 { 1288 struct mlx5dr_action *action; 1289 1290 action = dr_action_create_generic(DR_ACTION_TYP_CTR); 1291 if (!action) 1292 return NULL; 1293 1294 action->ctr->ctr_id = counter_id; 1295 1296 return action; 1297 } 1298 1299 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value) 1300 { 1301 struct mlx5dr_action *action; 1302 1303 action = dr_action_create_generic(DR_ACTION_TYP_TAG); 1304 if (!action) 1305 return NULL; 1306 1307 action->flow_tag->flow_tag = tag_value & 0xffffff; 1308 1309 return action; 1310 } 1311 1312 struct mlx5dr_action * 1313 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id) 1314 { 1315 struct mlx5dr_action *action; 1316 u64 icm_rx, icm_tx; 1317 int ret; 1318 1319 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id, 1320 &icm_rx, &icm_tx); 1321 if (ret) 1322 return NULL; 1323 1324 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER); 1325 if (!action) 1326 return NULL; 1327 1328 action->sampler->dmn = dmn; 1329 action->sampler->sampler_id = sampler_id; 1330 action->sampler->rx_icm_addr = icm_rx; 1331 action->sampler->tx_icm_addr = icm_tx; 1332 1333 refcount_inc(&dmn->refcount); 1334 return action; 1335 } 1336 1337 static int 1338 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type, 1339 struct mlx5dr_domain *dmn, 1340 u8 reformat_param_0, 1341 u8 reformat_param_1, 1342 size_t data_sz, 1343 void *data) 1344 { 1345 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) { 1346 if ((!data && data_sz) || (data && !data_sz) || 1347 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz || 1348 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) { 1349 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n"); 1350 goto out_err; 1351 } 1352 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) { 1353 if (data || 1354 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz || 1355 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) { 1356 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n"); 1357 goto out_err; 1358 } 1359 } else if (reformat_param_0 || reformat_param_1 || 1360 reformat_type > DR_ACTION_TYP_REMOVE_HDR) { 1361 mlx5dr_dbg(dmn, "Invalid reformat parameters\n"); 1362 goto out_err; 1363 } 1364 1365 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 1366 return 0; 1367 1368 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) { 1369 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 && 1370 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) { 1371 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n"); 1372 goto out_err; 1373 } 1374 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) { 1375 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 && 1376 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) { 1377 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n"); 1378 goto out_err; 1379 } 1380 } 1381 1382 return 0; 1383 1384 out_err: 1385 return -EINVAL; 1386 } 1387 1388 static int 1389 dr_action_create_reformat_action(struct mlx5dr_domain *dmn, 1390 u8 reformat_param_0, u8 reformat_param_1, 1391 size_t data_sz, void *data, 1392 struct mlx5dr_action *action) 1393 { 1394 u32 reformat_id; 1395 int ret; 1396 1397 switch (action->action_type) { 1398 case DR_ACTION_TYP_L2_TO_TNL_L2: 1399 case DR_ACTION_TYP_L2_TO_TNL_L3: 1400 { 1401 enum mlx5_reformat_ctx_type rt; 1402 1403 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2) 1404 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL; 1405 else 1406 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL; 1407 1408 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0, 1409 data_sz, data, 1410 &reformat_id); 1411 if (ret) 1412 return ret; 1413 1414 action->reformat->id = reformat_id; 1415 action->reformat->size = data_sz; 1416 return 0; 1417 } 1418 case DR_ACTION_TYP_TNL_L2_TO_L2: 1419 { 1420 return 0; 1421 } 1422 case DR_ACTION_TYP_TNL_L3_TO_L2: 1423 { 1424 u8 hw_actions[DR_ACTION_CACHE_LINE_SIZE] = {}; 1425 int ret; 1426 1427 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx, 1428 data, data_sz, 1429 hw_actions, 1430 DR_ACTION_CACHE_LINE_SIZE, 1431 &action->rewrite->num_of_actions); 1432 if (ret) { 1433 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n"); 1434 return ret; 1435 } 1436 1437 action->rewrite->data = hw_actions; 1438 action->rewrite->dmn = dmn; 1439 1440 ret = mlx5dr_ste_alloc_modify_hdr(action); 1441 if (ret) { 1442 mlx5dr_dbg(dmn, "Failed preparing reformat data\n"); 1443 return ret; 1444 } 1445 return 0; 1446 } 1447 case DR_ACTION_TYP_INSERT_HDR: 1448 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, 1449 MLX5_REFORMAT_TYPE_INSERT_HDR, 1450 reformat_param_0, 1451 reformat_param_1, 1452 data_sz, data, 1453 &reformat_id); 1454 if (ret) 1455 return ret; 1456 1457 action->reformat->id = reformat_id; 1458 action->reformat->size = data_sz; 1459 action->reformat->param_0 = reformat_param_0; 1460 action->reformat->param_1 = reformat_param_1; 1461 return 0; 1462 case DR_ACTION_TYP_REMOVE_HDR: 1463 action->reformat->id = 0; 1464 action->reformat->size = data_sz; 1465 action->reformat->param_0 = reformat_param_0; 1466 action->reformat->param_1 = reformat_param_1; 1467 return 0; 1468 default: 1469 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type); 1470 return -EINVAL; 1471 } 1472 } 1473 1474 #define CVLAN_ETHERTYPE 0x8100 1475 #define SVLAN_ETHERTYPE 0x88a8 1476 1477 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void) 1478 { 1479 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN); 1480 } 1481 1482 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn, 1483 __be32 vlan_hdr) 1484 { 1485 u32 vlan_hdr_h = ntohl(vlan_hdr); 1486 u16 ethertype = vlan_hdr_h >> 16; 1487 struct mlx5dr_action *action; 1488 1489 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) { 1490 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n"); 1491 return NULL; 1492 } 1493 1494 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN); 1495 if (!action) 1496 return NULL; 1497 1498 action->push_vlan->vlan_hdr = vlan_hdr_h; 1499 return action; 1500 } 1501 1502 struct mlx5dr_action * 1503 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn, 1504 enum mlx5dr_action_reformat_type reformat_type, 1505 u8 reformat_param_0, 1506 u8 reformat_param_1, 1507 size_t data_sz, 1508 void *data) 1509 { 1510 enum mlx5dr_action_type action_type; 1511 struct mlx5dr_action *action; 1512 int ret; 1513 1514 refcount_inc(&dmn->refcount); 1515 1516 /* General checks */ 1517 ret = dr_action_reformat_to_action_type(reformat_type, &action_type); 1518 if (ret) { 1519 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n"); 1520 goto dec_ref; 1521 } 1522 1523 ret = dr_action_verify_reformat_params(action_type, dmn, 1524 reformat_param_0, reformat_param_1, 1525 data_sz, data); 1526 if (ret) 1527 goto dec_ref; 1528 1529 action = dr_action_create_generic(action_type); 1530 if (!action) 1531 goto dec_ref; 1532 1533 action->reformat->dmn = dmn; 1534 1535 ret = dr_action_create_reformat_action(dmn, 1536 reformat_param_0, 1537 reformat_param_1, 1538 data_sz, 1539 data, 1540 action); 1541 if (ret) { 1542 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret); 1543 goto free_action; 1544 } 1545 1546 return action; 1547 1548 free_action: 1549 kfree(action); 1550 dec_ref: 1551 refcount_dec(&dmn->refcount); 1552 return NULL; 1553 } 1554 1555 static int 1556 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn, 1557 __be64 *sw_action, 1558 __be64 *hw_action, 1559 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1560 { 1561 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1562 u8 max_length; 1563 u16 sw_field; 1564 u32 data; 1565 1566 /* Get SW modify action data */ 1567 sw_field = MLX5_GET(set_action_in, sw_action, field); 1568 data = MLX5_GET(set_action_in, sw_action, data); 1569 1570 /* Convert SW data to HW modify action format */ 1571 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1572 if (!hw_action_info) { 1573 mlx5dr_dbg(dmn, "Modify add action invalid field given\n"); 1574 return -EINVAL; 1575 } 1576 1577 max_length = hw_action_info->end - hw_action_info->start + 1; 1578 1579 mlx5dr_ste_set_action_add(dmn->ste_ctx, 1580 hw_action, 1581 hw_action_info->hw_field, 1582 hw_action_info->start, 1583 max_length, 1584 data); 1585 1586 *ret_hw_info = hw_action_info; 1587 1588 return 0; 1589 } 1590 1591 static int 1592 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn, 1593 __be64 *sw_action, 1594 __be64 *hw_action, 1595 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1596 { 1597 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1598 u8 offset, length, max_length; 1599 u16 sw_field; 1600 u32 data; 1601 1602 /* Get SW modify action data */ 1603 length = MLX5_GET(set_action_in, sw_action, length); 1604 offset = MLX5_GET(set_action_in, sw_action, offset); 1605 sw_field = MLX5_GET(set_action_in, sw_action, field); 1606 data = MLX5_GET(set_action_in, sw_action, data); 1607 1608 /* Convert SW data to HW modify action format */ 1609 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1610 if (!hw_action_info) { 1611 mlx5dr_dbg(dmn, "Modify set action invalid field given\n"); 1612 return -EINVAL; 1613 } 1614 1615 /* PRM defines that length zero specific length of 32bits */ 1616 length = length ? length : 32; 1617 1618 max_length = hw_action_info->end - hw_action_info->start + 1; 1619 1620 if (length + offset > max_length) { 1621 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1622 return -EINVAL; 1623 } 1624 1625 mlx5dr_ste_set_action_set(dmn->ste_ctx, 1626 hw_action, 1627 hw_action_info->hw_field, 1628 hw_action_info->start + offset, 1629 length, 1630 data); 1631 1632 *ret_hw_info = hw_action_info; 1633 1634 return 0; 1635 } 1636 1637 static int 1638 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn, 1639 __be64 *sw_action, 1640 __be64 *hw_action, 1641 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1642 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1643 { 1644 u8 src_offset, dst_offset, src_max_length, dst_max_length, length; 1645 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1646 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1647 u16 src_field, dst_field; 1648 1649 /* Get SW modify action data */ 1650 src_field = MLX5_GET(copy_action_in, sw_action, src_field); 1651 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field); 1652 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset); 1653 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset); 1654 length = MLX5_GET(copy_action_in, sw_action, length); 1655 1656 /* Convert SW data to HW modify action format */ 1657 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field); 1658 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field); 1659 if (!hw_src_action_info || !hw_dst_action_info) { 1660 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n"); 1661 return -EINVAL; 1662 } 1663 1664 /* PRM defines that length zero specific length of 32bits */ 1665 length = length ? length : 32; 1666 1667 src_max_length = hw_src_action_info->end - 1668 hw_src_action_info->start + 1; 1669 dst_max_length = hw_dst_action_info->end - 1670 hw_dst_action_info->start + 1; 1671 1672 if (length + src_offset > src_max_length || 1673 length + dst_offset > dst_max_length) { 1674 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1675 return -EINVAL; 1676 } 1677 1678 mlx5dr_ste_set_action_copy(dmn->ste_ctx, 1679 hw_action, 1680 hw_dst_action_info->hw_field, 1681 hw_dst_action_info->start + dst_offset, 1682 length, 1683 hw_src_action_info->hw_field, 1684 hw_src_action_info->start + src_offset); 1685 1686 *ret_dst_hw_info = hw_dst_action_info; 1687 *ret_src_hw_info = hw_src_action_info; 1688 1689 return 0; 1690 } 1691 1692 static int 1693 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn, 1694 __be64 *sw_action, 1695 __be64 *hw_action, 1696 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1697 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1698 { 1699 u8 action; 1700 int ret; 1701 1702 *hw_action = 0; 1703 *ret_src_hw_info = NULL; 1704 1705 /* Get SW modify action type */ 1706 action = MLX5_GET(set_action_in, sw_action, action_type); 1707 1708 switch (action) { 1709 case MLX5_ACTION_TYPE_SET: 1710 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action, 1711 hw_action, 1712 ret_dst_hw_info); 1713 break; 1714 1715 case MLX5_ACTION_TYPE_ADD: 1716 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action, 1717 hw_action, 1718 ret_dst_hw_info); 1719 break; 1720 1721 case MLX5_ACTION_TYPE_COPY: 1722 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action, 1723 hw_action, 1724 ret_dst_hw_info, 1725 ret_src_hw_info); 1726 break; 1727 1728 default: 1729 mlx5dr_info(dmn, "Unsupported action_type for modify action\n"); 1730 ret = -EOPNOTSUPP; 1731 } 1732 1733 return ret; 1734 } 1735 1736 static int 1737 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action, 1738 const __be64 *sw_action) 1739 { 1740 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1741 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1742 1743 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1744 action->rewrite->allow_rx = 0; 1745 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1746 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1747 sw_field); 1748 return -EINVAL; 1749 } 1750 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1751 action->rewrite->allow_tx = 0; 1752 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1753 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1754 sw_field); 1755 return -EINVAL; 1756 } 1757 } 1758 1759 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1760 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n"); 1761 return -EINVAL; 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int 1768 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action, 1769 const __be64 *sw_action) 1770 { 1771 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1772 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1773 1774 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL && 1775 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT && 1776 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM && 1777 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) { 1778 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", 1779 sw_field); 1780 return -EINVAL; 1781 } 1782 1783 return 0; 1784 } 1785 1786 static int 1787 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action, 1788 const __be64 *sw_action) 1789 { 1790 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1791 u16 sw_fields[2]; 1792 int i; 1793 1794 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field); 1795 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field); 1796 1797 for (i = 0; i < 2; i++) { 1798 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1799 action->rewrite->allow_rx = 0; 1800 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1801 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1802 sw_fields[i]); 1803 return -EINVAL; 1804 } 1805 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1806 action->rewrite->allow_tx = 0; 1807 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1808 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1809 sw_fields[i]); 1810 return -EINVAL; 1811 } 1812 } 1813 } 1814 1815 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1816 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n"); 1817 return -EINVAL; 1818 } 1819 1820 return 0; 1821 } 1822 1823 static int 1824 dr_action_modify_check_field_limitation(struct mlx5dr_action *action, 1825 const __be64 *sw_action) 1826 { 1827 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1828 u8 action_type; 1829 int ret; 1830 1831 action_type = MLX5_GET(set_action_in, sw_action, action_type); 1832 1833 switch (action_type) { 1834 case MLX5_ACTION_TYPE_SET: 1835 ret = dr_action_modify_check_set_field_limitation(action, 1836 sw_action); 1837 break; 1838 1839 case MLX5_ACTION_TYPE_ADD: 1840 ret = dr_action_modify_check_add_field_limitation(action, 1841 sw_action); 1842 break; 1843 1844 case MLX5_ACTION_TYPE_COPY: 1845 ret = dr_action_modify_check_copy_field_limitation(action, 1846 sw_action); 1847 break; 1848 1849 default: 1850 mlx5dr_info(dmn, "Unsupported action %d modify action\n", 1851 action_type); 1852 ret = -EOPNOTSUPP; 1853 } 1854 1855 return ret; 1856 } 1857 1858 static bool 1859 dr_action_modify_check_is_ttl_modify(const void *sw_action) 1860 { 1861 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1862 1863 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL; 1864 } 1865 1866 static int dr_actions_convert_modify_header(struct mlx5dr_action *action, 1867 u32 max_hw_actions, 1868 u32 num_sw_actions, 1869 __be64 sw_actions[], 1870 __be64 hw_actions[], 1871 u32 *num_hw_actions, 1872 bool *modify_ttl) 1873 { 1874 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1875 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1876 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1877 __be64 *modify_ttl_sw_action = NULL; 1878 int ret, i, hw_idx = 0; 1879 __be64 *sw_action; 1880 __be64 hw_action; 1881 u16 hw_field = 0; 1882 u32 l3_type = 0; 1883 u32 l4_type = 0; 1884 1885 *modify_ttl = false; 1886 1887 action->rewrite->allow_rx = 1; 1888 action->rewrite->allow_tx = 1; 1889 1890 for (i = 0; i < num_sw_actions || modify_ttl_sw_action; i++) { 1891 /* modify TTL is handled separately, as a last action */ 1892 if (i == num_sw_actions) { 1893 sw_action = modify_ttl_sw_action; 1894 modify_ttl_sw_action = NULL; 1895 } else { 1896 sw_action = &sw_actions[i]; 1897 } 1898 1899 ret = dr_action_modify_check_field_limitation(action, 1900 sw_action); 1901 if (ret) 1902 return ret; 1903 1904 if (!(*modify_ttl) && 1905 dr_action_modify_check_is_ttl_modify(sw_action)) { 1906 modify_ttl_sw_action = sw_action; 1907 *modify_ttl = true; 1908 continue; 1909 } 1910 1911 /* Convert SW action to HW action */ 1912 ret = dr_action_modify_sw_to_hw(dmn, 1913 sw_action, 1914 &hw_action, 1915 &hw_dst_action_info, 1916 &hw_src_action_info); 1917 if (ret) 1918 return ret; 1919 1920 /* Due to a HW limitation we cannot modify 2 different L3 types */ 1921 if (l3_type && hw_dst_action_info->l3_type && 1922 hw_dst_action_info->l3_type != l3_type) { 1923 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n"); 1924 return -EINVAL; 1925 } 1926 if (hw_dst_action_info->l3_type) 1927 l3_type = hw_dst_action_info->l3_type; 1928 1929 /* Due to a HW limitation we cannot modify two different L4 types */ 1930 if (l4_type && hw_dst_action_info->l4_type && 1931 hw_dst_action_info->l4_type != l4_type) { 1932 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n"); 1933 return -EINVAL; 1934 } 1935 if (hw_dst_action_info->l4_type) 1936 l4_type = hw_dst_action_info->l4_type; 1937 1938 /* HW reads and executes two actions at once this means we 1939 * need to create a gap if two actions access the same field 1940 */ 1941 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field || 1942 (hw_src_action_info && 1943 hw_field == hw_src_action_info->hw_field))) { 1944 /* Check if after gap insertion the total number of HW 1945 * modify actions doesn't exceeds the limit 1946 */ 1947 hw_idx++; 1948 if (hw_idx >= max_hw_actions) { 1949 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n"); 1950 return -EINVAL; 1951 } 1952 } 1953 hw_field = hw_dst_action_info->hw_field; 1954 1955 hw_actions[hw_idx] = hw_action; 1956 hw_idx++; 1957 } 1958 1959 /* if the resulting HW actions list is empty, add NOP action */ 1960 if (!hw_idx) 1961 hw_idx++; 1962 1963 *num_hw_actions = hw_idx; 1964 1965 return 0; 1966 } 1967 1968 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn, 1969 size_t actions_sz, 1970 __be64 actions[], 1971 struct mlx5dr_action *action) 1972 { 1973 u32 max_hw_actions; 1974 u32 num_hw_actions; 1975 u32 num_sw_actions; 1976 __be64 *hw_actions; 1977 bool modify_ttl; 1978 int ret; 1979 1980 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE; 1981 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16); 1982 1983 if (num_sw_actions > max_hw_actions) { 1984 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n", 1985 num_sw_actions, max_hw_actions); 1986 return -EINVAL; 1987 } 1988 1989 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL); 1990 if (!hw_actions) 1991 return -ENOMEM; 1992 1993 ret = dr_actions_convert_modify_header(action, 1994 max_hw_actions, 1995 num_sw_actions, 1996 actions, 1997 hw_actions, 1998 &num_hw_actions, 1999 &modify_ttl); 2000 if (ret) 2001 goto free_hw_actions; 2002 2003 action->rewrite->modify_ttl = modify_ttl; 2004 action->rewrite->data = (u8 *)hw_actions; 2005 action->rewrite->num_of_actions = num_hw_actions; 2006 2007 if (num_hw_actions == 1 && 2008 dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) { 2009 action->rewrite->single_action_opt = true; 2010 } else { 2011 action->rewrite->single_action_opt = false; 2012 ret = mlx5dr_ste_alloc_modify_hdr(action); 2013 if (ret) 2014 goto free_hw_actions; 2015 } 2016 2017 return 0; 2018 2019 free_hw_actions: 2020 kfree(hw_actions); 2021 return ret; 2022 } 2023 2024 struct mlx5dr_action * 2025 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn, 2026 u32 flags, 2027 size_t actions_sz, 2028 __be64 actions[]) 2029 { 2030 struct mlx5dr_action *action; 2031 int ret = 0; 2032 2033 refcount_inc(&dmn->refcount); 2034 2035 if (actions_sz % DR_MODIFY_ACTION_SIZE) { 2036 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n"); 2037 goto dec_ref; 2038 } 2039 2040 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR); 2041 if (!action) 2042 goto dec_ref; 2043 2044 action->rewrite->dmn = dmn; 2045 2046 ret = dr_action_create_modify_action(dmn, 2047 actions_sz, 2048 actions, 2049 action); 2050 if (ret) { 2051 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret); 2052 goto free_action; 2053 } 2054 2055 return action; 2056 2057 free_action: 2058 kfree(action); 2059 dec_ref: 2060 refcount_dec(&dmn->refcount); 2061 return NULL; 2062 } 2063 2064 struct mlx5dr_action * 2065 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn, 2066 u16 vport, u8 vhca_id_valid, 2067 u16 vhca_id) 2068 { 2069 struct mlx5dr_cmd_vport_cap *vport_cap; 2070 struct mlx5dr_domain *vport_dmn; 2071 struct mlx5dr_action *action; 2072 u8 peer_vport; 2073 2074 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi); 2075 vport_dmn = peer_vport ? dmn->peer_dmn : dmn; 2076 if (!vport_dmn) { 2077 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n"); 2078 return NULL; 2079 } 2080 2081 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 2082 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n"); 2083 return NULL; 2084 } 2085 2086 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport); 2087 if (!vport_cap) { 2088 mlx5dr_err(dmn, 2089 "Failed to get vport 0x%x caps - vport is disabled or invalid\n", 2090 vport); 2091 return NULL; 2092 } 2093 2094 action = dr_action_create_generic(DR_ACTION_TYP_VPORT); 2095 if (!action) 2096 return NULL; 2097 2098 action->vport->dmn = vport_dmn; 2099 action->vport->caps = vport_cap; 2100 2101 return action; 2102 } 2103 2104 struct mlx5dr_action * 2105 mlx5dr_action_create_aso(struct mlx5dr_domain *dmn, u32 obj_id, 2106 u8 dest_reg_id, u8 aso_type, 2107 u8 init_color, u8 meter_id) 2108 { 2109 struct mlx5dr_action *action; 2110 2111 if (aso_type != MLX5_EXE_ASO_FLOW_METER) 2112 return NULL; 2113 2114 if (init_color > MLX5_FLOW_METER_COLOR_UNDEFINED) 2115 return NULL; 2116 2117 action = dr_action_create_generic(DR_ACTION_TYP_ASO_FLOW_METER); 2118 if (!action) 2119 return NULL; 2120 2121 action->aso->obj_id = obj_id; 2122 action->aso->offset = meter_id; 2123 action->aso->dest_reg_id = dest_reg_id; 2124 action->aso->init_color = init_color; 2125 action->aso->dmn = dmn; 2126 2127 refcount_inc(&dmn->refcount); 2128 2129 return action; 2130 } 2131 2132 int mlx5dr_action_destroy(struct mlx5dr_action *action) 2133 { 2134 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1)) 2135 return -EBUSY; 2136 2137 switch (action->action_type) { 2138 case DR_ACTION_TYP_FT: 2139 if (action->dest_tbl->is_fw_tbl) 2140 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount); 2141 else 2142 refcount_dec(&action->dest_tbl->tbl->refcount); 2143 2144 if (action->dest_tbl->is_fw_tbl && 2145 action->dest_tbl->fw_tbl.num_of_ref_actions) { 2146 struct mlx5dr_action **ref_actions; 2147 int i; 2148 2149 ref_actions = action->dest_tbl->fw_tbl.ref_actions; 2150 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++) 2151 refcount_dec(&ref_actions[i]->refcount); 2152 2153 kfree(ref_actions); 2154 2155 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn, 2156 action->dest_tbl->fw_tbl.id, 2157 action->dest_tbl->fw_tbl.group_id); 2158 } 2159 break; 2160 case DR_ACTION_TYP_TNL_L2_TO_L2: 2161 case DR_ACTION_TYP_REMOVE_HDR: 2162 refcount_dec(&action->reformat->dmn->refcount); 2163 break; 2164 case DR_ACTION_TYP_TNL_L3_TO_L2: 2165 mlx5dr_ste_free_modify_hdr(action); 2166 kfree(action->rewrite->data); 2167 refcount_dec(&action->rewrite->dmn->refcount); 2168 break; 2169 case DR_ACTION_TYP_L2_TO_TNL_L2: 2170 case DR_ACTION_TYP_L2_TO_TNL_L3: 2171 case DR_ACTION_TYP_INSERT_HDR: 2172 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev, 2173 action->reformat->id); 2174 refcount_dec(&action->reformat->dmn->refcount); 2175 break; 2176 case DR_ACTION_TYP_MODIFY_HDR: 2177 if (!action->rewrite->single_action_opt) 2178 mlx5dr_ste_free_modify_hdr(action); 2179 kfree(action->rewrite->data); 2180 refcount_dec(&action->rewrite->dmn->refcount); 2181 break; 2182 case DR_ACTION_TYP_SAMPLER: 2183 refcount_dec(&action->sampler->dmn->refcount); 2184 break; 2185 case DR_ACTION_TYP_ASO_FLOW_METER: 2186 refcount_dec(&action->aso->dmn->refcount); 2187 break; 2188 case DR_ACTION_TYP_RANGE: 2189 dr_action_destroy_range_definer(action); 2190 mlx5dr_action_destroy(action->range->miss_tbl_action); 2191 mlx5dr_action_destroy(action->range->hit_tbl_action); 2192 break; 2193 default: 2194 break; 2195 } 2196 2197 kfree(action); 2198 return 0; 2199 } 2200