1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "dr_types.h" 5 #include "dr_ste.h" 6 7 enum dr_action_domain { 8 DR_ACTION_DOMAIN_NIC_INGRESS, 9 DR_ACTION_DOMAIN_NIC_EGRESS, 10 DR_ACTION_DOMAIN_FDB_INGRESS, 11 DR_ACTION_DOMAIN_FDB_EGRESS, 12 DR_ACTION_DOMAIN_MAX, 13 }; 14 15 enum dr_action_valid_state { 16 DR_ACTION_STATE_ERR, 17 DR_ACTION_STATE_NO_ACTION, 18 DR_ACTION_STATE_ENCAP, 19 DR_ACTION_STATE_DECAP, 20 DR_ACTION_STATE_MODIFY_HDR, 21 DR_ACTION_STATE_POP_VLAN, 22 DR_ACTION_STATE_PUSH_VLAN, 23 DR_ACTION_STATE_NON_TERM, 24 DR_ACTION_STATE_TERM, 25 DR_ACTION_STATE_ASO, 26 DR_ACTION_STATE_MAX, 27 }; 28 29 static const char * const action_type_to_str[] = { 30 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2", 31 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2", 32 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2", 33 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3", 34 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP", 35 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP", 36 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT", 37 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR", 38 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG", 39 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR", 40 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT", 41 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN", 42 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN", 43 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER", 44 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR", 45 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR", 46 [DR_ACTION_TYP_ASO_FLOW_METER] = "DR_ACTION_TYP_ASO_FLOW_METER", 47 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN", 48 }; 49 50 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id) 51 { 52 if (action_id > DR_ACTION_TYP_MAX) 53 action_id = DR_ACTION_TYP_MAX; 54 return action_type_to_str[action_id]; 55 } 56 57 static const enum dr_action_valid_state 58 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = { 59 [DR_ACTION_DOMAIN_NIC_INGRESS] = { 60 [DR_ACTION_STATE_NO_ACTION] = { 61 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 62 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 63 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 64 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 65 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 66 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 67 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 68 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 69 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 70 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 71 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 72 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 73 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 74 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 75 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 76 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 77 }, 78 [DR_ACTION_STATE_DECAP] = { 79 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 80 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 81 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 82 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 83 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP, 84 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 85 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 86 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 87 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 88 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 89 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 90 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 91 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 92 }, 93 [DR_ACTION_STATE_ENCAP] = { 94 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 95 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 96 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 97 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 98 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP, 99 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 100 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 101 }, 102 [DR_ACTION_STATE_MODIFY_HDR] = { 103 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 104 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 105 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 106 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 107 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR, 108 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 109 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 110 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 111 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 112 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 113 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 114 }, 115 [DR_ACTION_STATE_POP_VLAN] = { 116 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 117 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 118 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 119 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 120 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN, 121 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 122 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 123 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 124 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 125 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 126 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 127 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 128 }, 129 [DR_ACTION_STATE_PUSH_VLAN] = { 130 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 131 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 132 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 133 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN, 134 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 135 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 136 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 137 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 138 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 139 }, 140 [DR_ACTION_STATE_NON_TERM] = { 141 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 142 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 143 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 144 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 145 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 146 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 147 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 148 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 149 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 150 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 151 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 152 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 153 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 154 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 155 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 156 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 157 }, 158 [DR_ACTION_STATE_ASO] = { 159 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 160 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 161 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 162 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 163 }, 164 [DR_ACTION_STATE_TERM] = { 165 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 166 }, 167 }, 168 [DR_ACTION_DOMAIN_NIC_EGRESS] = { 169 [DR_ACTION_STATE_NO_ACTION] = { 170 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 171 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 172 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 173 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 174 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 175 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 176 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 177 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 178 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 179 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 180 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 181 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 182 }, 183 [DR_ACTION_STATE_DECAP] = { 184 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 185 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 186 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 187 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 188 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 189 }, 190 [DR_ACTION_STATE_ENCAP] = { 191 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 192 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 193 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 194 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 195 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 196 }, 197 [DR_ACTION_STATE_MODIFY_HDR] = { 198 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 199 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 200 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 201 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 202 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 203 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 204 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 205 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 206 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 207 }, 208 [DR_ACTION_STATE_POP_VLAN] = { 209 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 210 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 211 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 212 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 213 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 214 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 215 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 216 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 217 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 218 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 219 }, 220 [DR_ACTION_STATE_PUSH_VLAN] = { 221 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 222 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 223 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 224 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 225 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 226 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 227 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 228 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 229 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 230 }, 231 [DR_ACTION_STATE_NON_TERM] = { 232 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 233 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 234 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 235 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 236 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 237 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 238 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 239 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 240 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 241 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 242 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 243 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 244 }, 245 [DR_ACTION_STATE_ASO] = { 246 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 247 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 248 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 249 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 250 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 251 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 252 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 253 }, 254 [DR_ACTION_STATE_TERM] = { 255 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 256 }, 257 }, 258 [DR_ACTION_DOMAIN_FDB_INGRESS] = { 259 [DR_ACTION_STATE_NO_ACTION] = { 260 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 261 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 262 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 263 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 264 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 265 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 266 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 267 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 268 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 269 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 270 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 271 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 272 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 273 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 274 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 275 }, 276 [DR_ACTION_STATE_DECAP] = { 277 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 278 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 279 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 280 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 281 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 282 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 283 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 284 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 285 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 286 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 287 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 288 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 289 }, 290 [DR_ACTION_STATE_ENCAP] = { 291 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 292 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 293 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 294 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 295 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 296 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 297 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 298 }, 299 [DR_ACTION_STATE_MODIFY_HDR] = { 300 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 301 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 302 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 303 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 304 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 305 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 306 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 307 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 308 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 309 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 310 }, 311 [DR_ACTION_STATE_POP_VLAN] = { 312 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 313 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 314 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 315 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 316 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 317 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 318 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 319 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 320 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 321 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 322 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 323 }, 324 [DR_ACTION_STATE_PUSH_VLAN] = { 325 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 326 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 327 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 328 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 329 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 330 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 331 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 332 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 333 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 334 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 335 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 336 }, 337 [DR_ACTION_STATE_NON_TERM] = { 338 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 339 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 340 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 341 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 342 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 343 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 344 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 345 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 346 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 347 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 348 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 349 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 350 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 351 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 352 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 353 }, 354 [DR_ACTION_STATE_ASO] = { 355 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 356 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 357 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 358 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 359 }, 360 [DR_ACTION_STATE_TERM] = { 361 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 362 }, 363 }, 364 [DR_ACTION_DOMAIN_FDB_EGRESS] = { 365 [DR_ACTION_STATE_NO_ACTION] = { 366 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 367 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 368 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 369 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 370 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 371 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 372 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 373 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 374 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 375 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 376 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 377 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 378 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 379 }, 380 [DR_ACTION_STATE_DECAP] = { 381 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 382 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 383 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 384 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 385 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 386 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 387 }, 388 [DR_ACTION_STATE_ENCAP] = { 389 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 390 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 391 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 392 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 393 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 394 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 395 }, 396 [DR_ACTION_STATE_MODIFY_HDR] = { 397 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 398 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 399 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 400 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 401 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 402 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 403 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 404 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 405 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 406 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 407 }, 408 [DR_ACTION_STATE_POP_VLAN] = { 409 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 410 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 411 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 412 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 413 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 414 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 415 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 416 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 417 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 418 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 419 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 420 }, 421 [DR_ACTION_STATE_PUSH_VLAN] = { 422 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 423 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 424 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 425 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 426 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 427 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 428 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 429 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 430 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 431 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 432 }, 433 [DR_ACTION_STATE_NON_TERM] = { 434 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 435 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 436 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 437 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 438 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 439 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 440 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 441 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 442 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 443 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 444 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 445 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 446 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 447 }, 448 [DR_ACTION_STATE_ASO] = { 449 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 450 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 451 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 452 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 453 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 454 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 455 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 456 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 457 }, 458 [DR_ACTION_STATE_TERM] = { 459 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 460 }, 461 }, 462 }; 463 464 static int 465 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type, 466 enum mlx5dr_action_type *action_type) 467 { 468 switch (reformat_type) { 469 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2: 470 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2; 471 break; 472 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2: 473 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2; 474 break; 475 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2: 476 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2; 477 break; 478 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3: 479 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3; 480 break; 481 case DR_ACTION_REFORMAT_TYP_INSERT_HDR: 482 *action_type = DR_ACTION_TYP_INSERT_HDR; 483 break; 484 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR: 485 *action_type = DR_ACTION_TYP_REMOVE_HDR; 486 break; 487 default: 488 return -EINVAL; 489 } 490 491 return 0; 492 } 493 494 /* Apply the actions on the rule STE array starting from the last_ste. 495 * Actions might require more than one STE, new_num_stes will return 496 * the new size of the STEs array, rule with actions. 497 */ 498 static void dr_actions_apply(struct mlx5dr_domain *dmn, 499 enum mlx5dr_domain_nic_type nic_type, 500 u8 *action_type_set, 501 u8 *last_ste, 502 struct mlx5dr_ste_actions_attr *attr, 503 u32 *new_num_stes) 504 { 505 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; 506 u32 added_stes = 0; 507 508 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 509 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set, 510 last_ste, attr, &added_stes); 511 else 512 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set, 513 last_ste, attr, &added_stes); 514 515 *new_num_stes += added_stes; 516 } 517 518 static enum dr_action_domain 519 dr_action_get_action_domain(enum mlx5dr_domain_type domain, 520 enum mlx5dr_domain_nic_type nic_type) 521 { 522 switch (domain) { 523 case MLX5DR_DOMAIN_TYPE_NIC_RX: 524 return DR_ACTION_DOMAIN_NIC_INGRESS; 525 case MLX5DR_DOMAIN_TYPE_NIC_TX: 526 return DR_ACTION_DOMAIN_NIC_EGRESS; 527 case MLX5DR_DOMAIN_TYPE_FDB: 528 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 529 return DR_ACTION_DOMAIN_FDB_INGRESS; 530 return DR_ACTION_DOMAIN_FDB_EGRESS; 531 default: 532 WARN_ON(true); 533 return DR_ACTION_DOMAIN_MAX; 534 } 535 } 536 537 static 538 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain, 539 u32 action_type, 540 u32 *state) 541 { 542 u32 cur_state = *state; 543 544 /* Check action state machine is valid */ 545 *state = next_action_state[action_domain][cur_state][action_type]; 546 547 if (*state == DR_ACTION_STATE_ERR) 548 return -EOPNOTSUPP; 549 550 return 0; 551 } 552 553 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, 554 struct mlx5dr_action *dest_action, 555 u64 *final_icm_addr) 556 { 557 int ret; 558 559 switch (dest_action->action_type) { 560 case DR_ACTION_TYP_FT: 561 /* Allow destination flow table only if table is a terminating 562 * table, since there is an *assumption* that in such case FW 563 * will recalculate the CS. 564 */ 565 if (dest_action->dest_tbl->is_fw_tbl) { 566 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr; 567 } else { 568 mlx5dr_dbg(dmn, 569 "Destination FT should be terminating when modify TTL is used\n"); 570 return -EINVAL; 571 } 572 break; 573 574 case DR_ACTION_TYP_VPORT: 575 /* If destination is vport we will get the FW flow table 576 * that recalculates the CS and forwards to the vport. 577 */ 578 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn, 579 dest_action->vport->caps->num, 580 final_icm_addr); 581 if (ret) { 582 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); 583 return ret; 584 } 585 break; 586 587 default: 588 break; 589 } 590 591 return 0; 592 } 593 594 static void dr_action_modify_ttl_adjust(struct mlx5dr_domain *dmn, 595 struct mlx5dr_ste_actions_attr *attr, 596 bool rx_rule, 597 bool *recalc_cs_required) 598 { 599 *recalc_cs_required = false; 600 601 /* if device supports csum recalculation - no adjustment needed */ 602 if (mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps)) 603 return; 604 605 /* no adjustment needed on TX rules */ 606 if (!rx_rule) 607 return; 608 609 if (!MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify)) { 610 /* Ignore the modify TTL action. 611 * It is always kept as last HW action. 612 */ 613 attr->modify_actions--; 614 return; 615 } 616 617 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 618 /* Due to a HW bug on some devices, modifying TTL on RX flows 619 * will cause an incorrect checksum calculation. In such cases 620 * we will use a FW table to recalculate the checksum. 621 */ 622 *recalc_cs_required = true; 623 } 624 625 static void dr_action_print_sequence(struct mlx5dr_domain *dmn, 626 struct mlx5dr_action *actions[], 627 int last_idx) 628 { 629 int i; 630 631 for (i = 0; i <= last_idx; i++) 632 mlx5dr_err(dmn, "< %s (%d) > ", 633 dr_action_id_to_str(actions[i]->action_type), 634 actions[i]->action_type); 635 } 636 637 #define WITH_VLAN_NUM_HW_ACTIONS 6 638 639 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 640 struct mlx5dr_matcher_rx_tx *nic_matcher, 641 struct mlx5dr_action *actions[], 642 u32 num_actions, 643 u8 *ste_arr, 644 u32 *new_hw_ste_arr_sz) 645 { 646 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn; 647 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX; 648 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 649 u8 action_type_set[DR_ACTION_TYP_MAX] = {}; 650 struct mlx5dr_ste_actions_attr attr = {}; 651 struct mlx5dr_action *dest_action = NULL; 652 u32 state = DR_ACTION_STATE_NO_ACTION; 653 enum dr_action_domain action_domain; 654 bool recalc_cs_required = false; 655 u8 *last_ste; 656 int i, ret; 657 658 attr.gvmi = dmn->info.caps.gvmi; 659 attr.hit_gvmi = dmn->info.caps.gvmi; 660 attr.final_icm_addr = nic_dmn->default_icm_addr; 661 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type); 662 663 for (i = 0; i < num_actions; i++) { 664 struct mlx5dr_action_dest_tbl *dest_tbl; 665 struct mlx5dr_icm_chunk *chunk; 666 struct mlx5dr_action *action; 667 int max_actions_type = 1; 668 u32 action_type; 669 670 action = actions[i]; 671 action_type = action->action_type; 672 673 switch (action_type) { 674 case DR_ACTION_TYP_DROP: 675 attr.final_icm_addr = nic_dmn->drop_icm_addr; 676 break; 677 case DR_ACTION_TYP_FT: 678 dest_action = action; 679 dest_tbl = action->dest_tbl; 680 if (!dest_tbl->is_fw_tbl) { 681 if (dest_tbl->tbl->dmn != dmn) { 682 mlx5dr_err(dmn, 683 "Destination table belongs to a different domain\n"); 684 return -EINVAL; 685 } 686 if (dest_tbl->tbl->level <= matcher->tbl->level) { 687 mlx5_core_dbg_once(dmn->mdev, 688 "Connecting table to a lower/same level destination table\n"); 689 mlx5dr_dbg(dmn, 690 "Connecting table at level %d to a destination table at level %d\n", 691 matcher->tbl->level, 692 dest_tbl->tbl->level); 693 } 694 chunk = rx_rule ? dest_tbl->tbl->rx.s_anchor->chunk : 695 dest_tbl->tbl->tx.s_anchor->chunk; 696 attr.final_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(chunk); 697 } else { 698 struct mlx5dr_cmd_query_flow_table_details output; 699 int ret; 700 701 /* get the relevant addresses */ 702 if (!action->dest_tbl->fw_tbl.rx_icm_addr) { 703 ret = mlx5dr_cmd_query_flow_table(dmn->mdev, 704 dest_tbl->fw_tbl.type, 705 dest_tbl->fw_tbl.id, 706 &output); 707 if (!ret) { 708 dest_tbl->fw_tbl.tx_icm_addr = 709 output.sw_owner_icm_root_1; 710 dest_tbl->fw_tbl.rx_icm_addr = 711 output.sw_owner_icm_root_0; 712 } else { 713 mlx5dr_err(dmn, 714 "Failed mlx5_cmd_query_flow_table ret: %d\n", 715 ret); 716 return ret; 717 } 718 } 719 attr.final_icm_addr = rx_rule ? 720 dest_tbl->fw_tbl.rx_icm_addr : 721 dest_tbl->fw_tbl.tx_icm_addr; 722 } 723 break; 724 case DR_ACTION_TYP_QP: 725 mlx5dr_info(dmn, "Domain doesn't support QP\n"); 726 return -EOPNOTSUPP; 727 case DR_ACTION_TYP_CTR: 728 attr.ctr_id = action->ctr->ctr_id + 729 action->ctr->offset; 730 break; 731 case DR_ACTION_TYP_TAG: 732 attr.flow_tag = action->flow_tag->flow_tag; 733 break; 734 case DR_ACTION_TYP_TNL_L2_TO_L2: 735 break; 736 case DR_ACTION_TYP_TNL_L3_TO_L2: 737 attr.decap_index = action->rewrite->index; 738 attr.decap_actions = action->rewrite->num_of_actions; 739 attr.decap_with_vlan = 740 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS; 741 break; 742 case DR_ACTION_TYP_MODIFY_HDR: 743 attr.modify_index = action->rewrite->index; 744 attr.modify_actions = action->rewrite->num_of_actions; 745 if (action->rewrite->modify_ttl) 746 dr_action_modify_ttl_adjust(dmn, &attr, rx_rule, 747 &recalc_cs_required); 748 break; 749 case DR_ACTION_TYP_L2_TO_TNL_L2: 750 case DR_ACTION_TYP_L2_TO_TNL_L3: 751 if (rx_rule && 752 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) { 753 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n"); 754 return -EOPNOTSUPP; 755 } 756 attr.reformat.size = action->reformat->size; 757 attr.reformat.id = action->reformat->id; 758 break; 759 case DR_ACTION_TYP_SAMPLER: 760 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr : 761 action->sampler->tx_icm_addr; 762 break; 763 case DR_ACTION_TYP_VPORT: 764 attr.hit_gvmi = action->vport->caps->vhca_gvmi; 765 dest_action = action; 766 attr.final_icm_addr = rx_rule ? 767 action->vport->caps->icm_address_rx : 768 action->vport->caps->icm_address_tx; 769 break; 770 case DR_ACTION_TYP_POP_VLAN: 771 if (!rx_rule && !(dmn->ste_ctx->actions_caps & 772 DR_STE_CTX_ACTION_CAP_TX_POP)) { 773 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n"); 774 return -EOPNOTSUPP; 775 } 776 777 max_actions_type = MLX5DR_MAX_VLANS; 778 attr.vlans.count++; 779 break; 780 case DR_ACTION_TYP_PUSH_VLAN: 781 if (rx_rule && !(dmn->ste_ctx->actions_caps & 782 DR_STE_CTX_ACTION_CAP_RX_PUSH)) { 783 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n"); 784 return -EOPNOTSUPP; 785 } 786 787 max_actions_type = MLX5DR_MAX_VLANS; 788 if (attr.vlans.count == MLX5DR_MAX_VLANS) { 789 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n"); 790 return -EINVAL; 791 } 792 793 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr; 794 break; 795 case DR_ACTION_TYP_INSERT_HDR: 796 case DR_ACTION_TYP_REMOVE_HDR: 797 attr.reformat.size = action->reformat->size; 798 attr.reformat.id = action->reformat->id; 799 attr.reformat.param_0 = action->reformat->param_0; 800 attr.reformat.param_1 = action->reformat->param_1; 801 break; 802 case DR_ACTION_TYP_ASO_FLOW_METER: 803 attr.aso_flow_meter.obj_id = action->aso->obj_id; 804 attr.aso_flow_meter.offset = action->aso->offset; 805 attr.aso_flow_meter.dest_reg_id = action->aso->dest_reg_id; 806 attr.aso_flow_meter.init_color = action->aso->init_color; 807 break; 808 default: 809 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type); 810 return -EINVAL; 811 } 812 813 /* Check action duplication */ 814 if (++action_type_set[action_type] > max_actions_type) { 815 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n", 816 action_type, max_actions_type); 817 return -EINVAL; 818 } 819 820 /* Check action state machine is valid */ 821 if (dr_action_validate_and_get_next_state(action_domain, 822 action_type, 823 &state)) { 824 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:", 825 attr.gvmi, rx_rule); 826 dr_action_print_sequence(dmn, actions, i); 827 return -EOPNOTSUPP; 828 } 829 } 830 831 *new_hw_ste_arr_sz = nic_matcher->num_of_builders; 832 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1); 833 834 if (recalc_cs_required && dest_action) { 835 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr); 836 if (ret) { 837 mlx5dr_err(dmn, 838 "Failed to handle checksum recalculation err %d\n", 839 ret); 840 return ret; 841 } 842 } 843 844 dr_actions_apply(dmn, 845 nic_dmn->type, 846 action_type_set, 847 last_ste, 848 &attr, 849 new_hw_ste_arr_sz); 850 851 return 0; 852 } 853 854 static unsigned int action_size[DR_ACTION_TYP_MAX] = { 855 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat), 856 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat), 857 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite), 858 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat), 859 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl), 860 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr), 861 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag), 862 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite), 863 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport), 864 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan), 865 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat), 866 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat), 867 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler), 868 [DR_ACTION_TYP_ASO_FLOW_METER] = sizeof(struct mlx5dr_action_aso_flow_meter), 869 }; 870 871 static struct mlx5dr_action * 872 dr_action_create_generic(enum mlx5dr_action_type action_type) 873 { 874 struct mlx5dr_action *action; 875 int extra_size; 876 877 if (action_type < DR_ACTION_TYP_MAX) 878 extra_size = action_size[action_type]; 879 else 880 return NULL; 881 882 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL); 883 if (!action) 884 return NULL; 885 886 action->action_type = action_type; 887 refcount_set(&action->refcount, 1); 888 action->data = action + 1; 889 890 return action; 891 } 892 893 struct mlx5dr_action *mlx5dr_action_create_drop(void) 894 { 895 return dr_action_create_generic(DR_ACTION_TYP_DROP); 896 } 897 898 struct mlx5dr_action * 899 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num) 900 { 901 struct mlx5dr_action *action; 902 903 action = dr_action_create_generic(DR_ACTION_TYP_FT); 904 if (!action) 905 return NULL; 906 907 action->dest_tbl->is_fw_tbl = true; 908 action->dest_tbl->fw_tbl.dmn = dmn; 909 action->dest_tbl->fw_tbl.id = table_num; 910 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 911 refcount_inc(&dmn->refcount); 912 913 return action; 914 } 915 916 struct mlx5dr_action * 917 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl) 918 { 919 struct mlx5dr_action *action; 920 921 refcount_inc(&tbl->refcount); 922 923 action = dr_action_create_generic(DR_ACTION_TYP_FT); 924 if (!action) 925 goto dec_ref; 926 927 action->dest_tbl->tbl = tbl; 928 929 return action; 930 931 dec_ref: 932 refcount_dec(&tbl->refcount); 933 return NULL; 934 } 935 936 struct mlx5dr_action * 937 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn, 938 struct mlx5dr_action_dest *dests, 939 u32 num_of_dests, 940 bool ignore_flow_level, 941 u32 flow_source) 942 { 943 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests; 944 struct mlx5dr_action **ref_actions; 945 struct mlx5dr_action *action; 946 bool reformat_req = false; 947 u32 num_of_ref = 0; 948 u32 ref_act_cnt; 949 int ret; 950 int i; 951 952 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 953 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n"); 954 return NULL; 955 } 956 957 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL); 958 if (!hw_dests) 959 return NULL; 960 961 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt))) 962 goto free_hw_dests; 963 964 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL); 965 if (!ref_actions) 966 goto free_hw_dests; 967 968 for (i = 0; i < num_of_dests; i++) { 969 struct mlx5dr_action *reformat_action = dests[i].reformat; 970 struct mlx5dr_action *dest_action = dests[i].dest; 971 972 ref_actions[num_of_ref++] = dest_action; 973 974 switch (dest_action->action_type) { 975 case DR_ACTION_TYP_VPORT: 976 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID; 977 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; 978 hw_dests[i].vport.num = dest_action->vport->caps->num; 979 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi; 980 if (reformat_action) { 981 reformat_req = true; 982 hw_dests[i].vport.reformat_id = 983 reformat_action->reformat->id; 984 ref_actions[num_of_ref++] = reformat_action; 985 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; 986 } 987 break; 988 989 case DR_ACTION_TYP_FT: 990 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 991 if (dest_action->dest_tbl->is_fw_tbl) 992 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id; 993 else 994 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id; 995 break; 996 997 default: 998 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n"); 999 goto free_ref_actions; 1000 } 1001 } 1002 1003 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1004 if (!action) 1005 goto free_ref_actions; 1006 1007 ret = mlx5dr_fw_create_md_tbl(dmn, 1008 hw_dests, 1009 num_of_dests, 1010 reformat_req, 1011 &action->dest_tbl->fw_tbl.id, 1012 &action->dest_tbl->fw_tbl.group_id, 1013 ignore_flow_level, 1014 flow_source); 1015 if (ret) 1016 goto free_action; 1017 1018 refcount_inc(&dmn->refcount); 1019 1020 for (i = 0; i < num_of_ref; i++) 1021 refcount_inc(&ref_actions[i]->refcount); 1022 1023 action->dest_tbl->is_fw_tbl = true; 1024 action->dest_tbl->fw_tbl.dmn = dmn; 1025 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 1026 action->dest_tbl->fw_tbl.ref_actions = ref_actions; 1027 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref; 1028 1029 kfree(hw_dests); 1030 1031 return action; 1032 1033 free_action: 1034 kfree(action); 1035 free_ref_actions: 1036 kfree(ref_actions); 1037 free_hw_dests: 1038 kfree(hw_dests); 1039 return NULL; 1040 } 1041 1042 struct mlx5dr_action * 1043 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn, 1044 struct mlx5_flow_table *ft) 1045 { 1046 struct mlx5dr_action *action; 1047 1048 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1049 if (!action) 1050 return NULL; 1051 1052 action->dest_tbl->is_fw_tbl = 1; 1053 action->dest_tbl->fw_tbl.type = ft->type; 1054 action->dest_tbl->fw_tbl.id = ft->id; 1055 action->dest_tbl->fw_tbl.dmn = dmn; 1056 1057 refcount_inc(&dmn->refcount); 1058 1059 return action; 1060 } 1061 1062 struct mlx5dr_action * 1063 mlx5dr_action_create_flow_counter(u32 counter_id) 1064 { 1065 struct mlx5dr_action *action; 1066 1067 action = dr_action_create_generic(DR_ACTION_TYP_CTR); 1068 if (!action) 1069 return NULL; 1070 1071 action->ctr->ctr_id = counter_id; 1072 1073 return action; 1074 } 1075 1076 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value) 1077 { 1078 struct mlx5dr_action *action; 1079 1080 action = dr_action_create_generic(DR_ACTION_TYP_TAG); 1081 if (!action) 1082 return NULL; 1083 1084 action->flow_tag->flow_tag = tag_value & 0xffffff; 1085 1086 return action; 1087 } 1088 1089 struct mlx5dr_action * 1090 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id) 1091 { 1092 struct mlx5dr_action *action; 1093 u64 icm_rx, icm_tx; 1094 int ret; 1095 1096 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id, 1097 &icm_rx, &icm_tx); 1098 if (ret) 1099 return NULL; 1100 1101 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER); 1102 if (!action) 1103 return NULL; 1104 1105 action->sampler->dmn = dmn; 1106 action->sampler->sampler_id = sampler_id; 1107 action->sampler->rx_icm_addr = icm_rx; 1108 action->sampler->tx_icm_addr = icm_tx; 1109 1110 refcount_inc(&dmn->refcount); 1111 return action; 1112 } 1113 1114 static int 1115 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type, 1116 struct mlx5dr_domain *dmn, 1117 u8 reformat_param_0, 1118 u8 reformat_param_1, 1119 size_t data_sz, 1120 void *data) 1121 { 1122 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) { 1123 if ((!data && data_sz) || (data && !data_sz) || 1124 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz || 1125 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) { 1126 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n"); 1127 goto out_err; 1128 } 1129 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) { 1130 if (data || 1131 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz || 1132 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) { 1133 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n"); 1134 goto out_err; 1135 } 1136 } else if (reformat_param_0 || reformat_param_1 || 1137 reformat_type > DR_ACTION_TYP_REMOVE_HDR) { 1138 mlx5dr_dbg(dmn, "Invalid reformat parameters\n"); 1139 goto out_err; 1140 } 1141 1142 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 1143 return 0; 1144 1145 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) { 1146 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 && 1147 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) { 1148 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n"); 1149 goto out_err; 1150 } 1151 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) { 1152 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 && 1153 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) { 1154 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n"); 1155 goto out_err; 1156 } 1157 } 1158 1159 return 0; 1160 1161 out_err: 1162 return -EINVAL; 1163 } 1164 1165 #define ACTION_CACHE_LINE_SIZE 64 1166 1167 static int 1168 dr_action_create_reformat_action(struct mlx5dr_domain *dmn, 1169 u8 reformat_param_0, u8 reformat_param_1, 1170 size_t data_sz, void *data, 1171 struct mlx5dr_action *action) 1172 { 1173 u32 reformat_id; 1174 int ret; 1175 1176 switch (action->action_type) { 1177 case DR_ACTION_TYP_L2_TO_TNL_L2: 1178 case DR_ACTION_TYP_L2_TO_TNL_L3: 1179 { 1180 enum mlx5_reformat_ctx_type rt; 1181 1182 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2) 1183 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL; 1184 else 1185 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL; 1186 1187 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0, 1188 data_sz, data, 1189 &reformat_id); 1190 if (ret) 1191 return ret; 1192 1193 action->reformat->id = reformat_id; 1194 action->reformat->size = data_sz; 1195 return 0; 1196 } 1197 case DR_ACTION_TYP_TNL_L2_TO_L2: 1198 { 1199 return 0; 1200 } 1201 case DR_ACTION_TYP_TNL_L3_TO_L2: 1202 { 1203 u8 hw_actions[ACTION_CACHE_LINE_SIZE] = {}; 1204 int ret; 1205 1206 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx, 1207 data, data_sz, 1208 hw_actions, 1209 ACTION_CACHE_LINE_SIZE, 1210 &action->rewrite->num_of_actions); 1211 if (ret) { 1212 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n"); 1213 return ret; 1214 } 1215 1216 action->rewrite->chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, 1217 DR_CHUNK_SIZE_8); 1218 if (!action->rewrite->chunk) { 1219 mlx5dr_dbg(dmn, "Failed allocating modify header chunk\n"); 1220 return -ENOMEM; 1221 } 1222 1223 action->rewrite->data = (void *)hw_actions; 1224 action->rewrite->index = (mlx5dr_icm_pool_get_chunk_icm_addr 1225 (action->rewrite->chunk) - 1226 dmn->info.caps.hdr_modify_icm_addr) / 1227 ACTION_CACHE_LINE_SIZE; 1228 1229 ret = mlx5dr_send_postsend_action(dmn, action); 1230 if (ret) { 1231 mlx5dr_dbg(dmn, "Writing decap l3 actions to ICM failed\n"); 1232 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1233 return ret; 1234 } 1235 return 0; 1236 } 1237 case DR_ACTION_TYP_INSERT_HDR: 1238 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, 1239 MLX5_REFORMAT_TYPE_INSERT_HDR, 1240 reformat_param_0, 1241 reformat_param_1, 1242 data_sz, data, 1243 &reformat_id); 1244 if (ret) 1245 return ret; 1246 1247 action->reformat->id = reformat_id; 1248 action->reformat->size = data_sz; 1249 action->reformat->param_0 = reformat_param_0; 1250 action->reformat->param_1 = reformat_param_1; 1251 return 0; 1252 case DR_ACTION_TYP_REMOVE_HDR: 1253 action->reformat->id = 0; 1254 action->reformat->size = data_sz; 1255 action->reformat->param_0 = reformat_param_0; 1256 action->reformat->param_1 = reformat_param_1; 1257 return 0; 1258 default: 1259 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type); 1260 return -EINVAL; 1261 } 1262 } 1263 1264 #define CVLAN_ETHERTYPE 0x8100 1265 #define SVLAN_ETHERTYPE 0x88a8 1266 1267 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void) 1268 { 1269 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN); 1270 } 1271 1272 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn, 1273 __be32 vlan_hdr) 1274 { 1275 u32 vlan_hdr_h = ntohl(vlan_hdr); 1276 u16 ethertype = vlan_hdr_h >> 16; 1277 struct mlx5dr_action *action; 1278 1279 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) { 1280 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n"); 1281 return NULL; 1282 } 1283 1284 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN); 1285 if (!action) 1286 return NULL; 1287 1288 action->push_vlan->vlan_hdr = vlan_hdr_h; 1289 return action; 1290 } 1291 1292 struct mlx5dr_action * 1293 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn, 1294 enum mlx5dr_action_reformat_type reformat_type, 1295 u8 reformat_param_0, 1296 u8 reformat_param_1, 1297 size_t data_sz, 1298 void *data) 1299 { 1300 enum mlx5dr_action_type action_type; 1301 struct mlx5dr_action *action; 1302 int ret; 1303 1304 refcount_inc(&dmn->refcount); 1305 1306 /* General checks */ 1307 ret = dr_action_reformat_to_action_type(reformat_type, &action_type); 1308 if (ret) { 1309 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n"); 1310 goto dec_ref; 1311 } 1312 1313 ret = dr_action_verify_reformat_params(action_type, dmn, 1314 reformat_param_0, reformat_param_1, 1315 data_sz, data); 1316 if (ret) 1317 goto dec_ref; 1318 1319 action = dr_action_create_generic(action_type); 1320 if (!action) 1321 goto dec_ref; 1322 1323 action->reformat->dmn = dmn; 1324 1325 ret = dr_action_create_reformat_action(dmn, 1326 reformat_param_0, 1327 reformat_param_1, 1328 data_sz, 1329 data, 1330 action); 1331 if (ret) { 1332 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret); 1333 goto free_action; 1334 } 1335 1336 return action; 1337 1338 free_action: 1339 kfree(action); 1340 dec_ref: 1341 refcount_dec(&dmn->refcount); 1342 return NULL; 1343 } 1344 1345 static int 1346 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn, 1347 __be64 *sw_action, 1348 __be64 *hw_action, 1349 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1350 { 1351 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1352 u8 max_length; 1353 u16 sw_field; 1354 u32 data; 1355 1356 /* Get SW modify action data */ 1357 sw_field = MLX5_GET(set_action_in, sw_action, field); 1358 data = MLX5_GET(set_action_in, sw_action, data); 1359 1360 /* Convert SW data to HW modify action format */ 1361 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1362 if (!hw_action_info) { 1363 mlx5dr_dbg(dmn, "Modify add action invalid field given\n"); 1364 return -EINVAL; 1365 } 1366 1367 max_length = hw_action_info->end - hw_action_info->start + 1; 1368 1369 mlx5dr_ste_set_action_add(dmn->ste_ctx, 1370 hw_action, 1371 hw_action_info->hw_field, 1372 hw_action_info->start, 1373 max_length, 1374 data); 1375 1376 *ret_hw_info = hw_action_info; 1377 1378 return 0; 1379 } 1380 1381 static int 1382 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn, 1383 __be64 *sw_action, 1384 __be64 *hw_action, 1385 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1386 { 1387 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1388 u8 offset, length, max_length; 1389 u16 sw_field; 1390 u32 data; 1391 1392 /* Get SW modify action data */ 1393 length = MLX5_GET(set_action_in, sw_action, length); 1394 offset = MLX5_GET(set_action_in, sw_action, offset); 1395 sw_field = MLX5_GET(set_action_in, sw_action, field); 1396 data = MLX5_GET(set_action_in, sw_action, data); 1397 1398 /* Convert SW data to HW modify action format */ 1399 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1400 if (!hw_action_info) { 1401 mlx5dr_dbg(dmn, "Modify set action invalid field given\n"); 1402 return -EINVAL; 1403 } 1404 1405 /* PRM defines that length zero specific length of 32bits */ 1406 length = length ? length : 32; 1407 1408 max_length = hw_action_info->end - hw_action_info->start + 1; 1409 1410 if (length + offset > max_length) { 1411 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1412 return -EINVAL; 1413 } 1414 1415 mlx5dr_ste_set_action_set(dmn->ste_ctx, 1416 hw_action, 1417 hw_action_info->hw_field, 1418 hw_action_info->start + offset, 1419 length, 1420 data); 1421 1422 *ret_hw_info = hw_action_info; 1423 1424 return 0; 1425 } 1426 1427 static int 1428 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn, 1429 __be64 *sw_action, 1430 __be64 *hw_action, 1431 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1432 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1433 { 1434 u8 src_offset, dst_offset, src_max_length, dst_max_length, length; 1435 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1436 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1437 u16 src_field, dst_field; 1438 1439 /* Get SW modify action data */ 1440 src_field = MLX5_GET(copy_action_in, sw_action, src_field); 1441 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field); 1442 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset); 1443 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset); 1444 length = MLX5_GET(copy_action_in, sw_action, length); 1445 1446 /* Convert SW data to HW modify action format */ 1447 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field); 1448 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field); 1449 if (!hw_src_action_info || !hw_dst_action_info) { 1450 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n"); 1451 return -EINVAL; 1452 } 1453 1454 /* PRM defines that length zero specific length of 32bits */ 1455 length = length ? length : 32; 1456 1457 src_max_length = hw_src_action_info->end - 1458 hw_src_action_info->start + 1; 1459 dst_max_length = hw_dst_action_info->end - 1460 hw_dst_action_info->start + 1; 1461 1462 if (length + src_offset > src_max_length || 1463 length + dst_offset > dst_max_length) { 1464 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1465 return -EINVAL; 1466 } 1467 1468 mlx5dr_ste_set_action_copy(dmn->ste_ctx, 1469 hw_action, 1470 hw_dst_action_info->hw_field, 1471 hw_dst_action_info->start + dst_offset, 1472 length, 1473 hw_src_action_info->hw_field, 1474 hw_src_action_info->start + src_offset); 1475 1476 *ret_dst_hw_info = hw_dst_action_info; 1477 *ret_src_hw_info = hw_src_action_info; 1478 1479 return 0; 1480 } 1481 1482 static int 1483 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn, 1484 __be64 *sw_action, 1485 __be64 *hw_action, 1486 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1487 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1488 { 1489 u8 action; 1490 int ret; 1491 1492 *hw_action = 0; 1493 *ret_src_hw_info = NULL; 1494 1495 /* Get SW modify action type */ 1496 action = MLX5_GET(set_action_in, sw_action, action_type); 1497 1498 switch (action) { 1499 case MLX5_ACTION_TYPE_SET: 1500 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action, 1501 hw_action, 1502 ret_dst_hw_info); 1503 break; 1504 1505 case MLX5_ACTION_TYPE_ADD: 1506 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action, 1507 hw_action, 1508 ret_dst_hw_info); 1509 break; 1510 1511 case MLX5_ACTION_TYPE_COPY: 1512 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action, 1513 hw_action, 1514 ret_dst_hw_info, 1515 ret_src_hw_info); 1516 break; 1517 1518 default: 1519 mlx5dr_info(dmn, "Unsupported action_type for modify action\n"); 1520 ret = -EOPNOTSUPP; 1521 } 1522 1523 return ret; 1524 } 1525 1526 static int 1527 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action, 1528 const __be64 *sw_action) 1529 { 1530 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1531 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1532 1533 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1534 action->rewrite->allow_rx = 0; 1535 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1536 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1537 sw_field); 1538 return -EINVAL; 1539 } 1540 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1541 action->rewrite->allow_tx = 0; 1542 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1543 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1544 sw_field); 1545 return -EINVAL; 1546 } 1547 } 1548 1549 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1550 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n"); 1551 return -EINVAL; 1552 } 1553 1554 return 0; 1555 } 1556 1557 static int 1558 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action, 1559 const __be64 *sw_action) 1560 { 1561 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1562 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1563 1564 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL && 1565 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT && 1566 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM && 1567 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) { 1568 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", 1569 sw_field); 1570 return -EINVAL; 1571 } 1572 1573 return 0; 1574 } 1575 1576 static int 1577 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action, 1578 const __be64 *sw_action) 1579 { 1580 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1581 u16 sw_fields[2]; 1582 int i; 1583 1584 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field); 1585 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field); 1586 1587 for (i = 0; i < 2; i++) { 1588 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1589 action->rewrite->allow_rx = 0; 1590 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1591 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1592 sw_fields[i]); 1593 return -EINVAL; 1594 } 1595 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1596 action->rewrite->allow_tx = 0; 1597 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1598 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1599 sw_fields[i]); 1600 return -EINVAL; 1601 } 1602 } 1603 } 1604 1605 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1606 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n"); 1607 return -EINVAL; 1608 } 1609 1610 return 0; 1611 } 1612 1613 static int 1614 dr_action_modify_check_field_limitation(struct mlx5dr_action *action, 1615 const __be64 *sw_action) 1616 { 1617 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1618 u8 action_type; 1619 int ret; 1620 1621 action_type = MLX5_GET(set_action_in, sw_action, action_type); 1622 1623 switch (action_type) { 1624 case MLX5_ACTION_TYPE_SET: 1625 ret = dr_action_modify_check_set_field_limitation(action, 1626 sw_action); 1627 break; 1628 1629 case MLX5_ACTION_TYPE_ADD: 1630 ret = dr_action_modify_check_add_field_limitation(action, 1631 sw_action); 1632 break; 1633 1634 case MLX5_ACTION_TYPE_COPY: 1635 ret = dr_action_modify_check_copy_field_limitation(action, 1636 sw_action); 1637 break; 1638 1639 default: 1640 mlx5dr_info(dmn, "Unsupported action %d modify action\n", 1641 action_type); 1642 ret = -EOPNOTSUPP; 1643 } 1644 1645 return ret; 1646 } 1647 1648 static bool 1649 dr_action_modify_check_is_ttl_modify(const void *sw_action) 1650 { 1651 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1652 1653 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL; 1654 } 1655 1656 static int dr_actions_convert_modify_header(struct mlx5dr_action *action, 1657 u32 max_hw_actions, 1658 u32 num_sw_actions, 1659 __be64 sw_actions[], 1660 __be64 hw_actions[], 1661 u32 *num_hw_actions, 1662 bool *modify_ttl) 1663 { 1664 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1665 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1666 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1667 __be64 *modify_ttl_sw_action = NULL; 1668 int ret, i, hw_idx = 0; 1669 __be64 *sw_action; 1670 __be64 hw_action; 1671 u16 hw_field = 0; 1672 u32 l3_type = 0; 1673 u32 l4_type = 0; 1674 1675 *modify_ttl = false; 1676 1677 action->rewrite->allow_rx = 1; 1678 action->rewrite->allow_tx = 1; 1679 1680 for (i = 0; i < num_sw_actions || modify_ttl_sw_action; i++) { 1681 /* modify TTL is handled separately, as a last action */ 1682 if (i == num_sw_actions) { 1683 sw_action = modify_ttl_sw_action; 1684 modify_ttl_sw_action = NULL; 1685 } else { 1686 sw_action = &sw_actions[i]; 1687 } 1688 1689 ret = dr_action_modify_check_field_limitation(action, 1690 sw_action); 1691 if (ret) 1692 return ret; 1693 1694 if (!(*modify_ttl) && 1695 dr_action_modify_check_is_ttl_modify(sw_action)) { 1696 modify_ttl_sw_action = sw_action; 1697 *modify_ttl = true; 1698 continue; 1699 } 1700 1701 /* Convert SW action to HW action */ 1702 ret = dr_action_modify_sw_to_hw(dmn, 1703 sw_action, 1704 &hw_action, 1705 &hw_dst_action_info, 1706 &hw_src_action_info); 1707 if (ret) 1708 return ret; 1709 1710 /* Due to a HW limitation we cannot modify 2 different L3 types */ 1711 if (l3_type && hw_dst_action_info->l3_type && 1712 hw_dst_action_info->l3_type != l3_type) { 1713 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n"); 1714 return -EINVAL; 1715 } 1716 if (hw_dst_action_info->l3_type) 1717 l3_type = hw_dst_action_info->l3_type; 1718 1719 /* Due to a HW limitation we cannot modify two different L4 types */ 1720 if (l4_type && hw_dst_action_info->l4_type && 1721 hw_dst_action_info->l4_type != l4_type) { 1722 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n"); 1723 return -EINVAL; 1724 } 1725 if (hw_dst_action_info->l4_type) 1726 l4_type = hw_dst_action_info->l4_type; 1727 1728 /* HW reads and executes two actions at once this means we 1729 * need to create a gap if two actions access the same field 1730 */ 1731 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field || 1732 (hw_src_action_info && 1733 hw_field == hw_src_action_info->hw_field))) { 1734 /* Check if after gap insertion the total number of HW 1735 * modify actions doesn't exceeds the limit 1736 */ 1737 hw_idx++; 1738 if (hw_idx >= max_hw_actions) { 1739 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n"); 1740 return -EINVAL; 1741 } 1742 } 1743 hw_field = hw_dst_action_info->hw_field; 1744 1745 hw_actions[hw_idx] = hw_action; 1746 hw_idx++; 1747 } 1748 1749 /* if the resulting HW actions list is empty, add NOP action */ 1750 if (!hw_idx) 1751 hw_idx++; 1752 1753 *num_hw_actions = hw_idx; 1754 1755 return 0; 1756 } 1757 1758 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn, 1759 size_t actions_sz, 1760 __be64 actions[], 1761 struct mlx5dr_action *action) 1762 { 1763 struct mlx5dr_icm_chunk *chunk; 1764 u32 max_hw_actions; 1765 u32 num_hw_actions; 1766 u32 num_sw_actions; 1767 __be64 *hw_actions; 1768 bool modify_ttl; 1769 int ret; 1770 1771 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE; 1772 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16); 1773 1774 if (num_sw_actions > max_hw_actions) { 1775 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n", 1776 num_sw_actions, max_hw_actions); 1777 return -EINVAL; 1778 } 1779 1780 chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16); 1781 if (!chunk) 1782 return -ENOMEM; 1783 1784 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL); 1785 if (!hw_actions) { 1786 ret = -ENOMEM; 1787 goto free_chunk; 1788 } 1789 1790 ret = dr_actions_convert_modify_header(action, 1791 max_hw_actions, 1792 num_sw_actions, 1793 actions, 1794 hw_actions, 1795 &num_hw_actions, 1796 &modify_ttl); 1797 if (ret) 1798 goto free_hw_actions; 1799 1800 action->rewrite->chunk = chunk; 1801 action->rewrite->modify_ttl = modify_ttl; 1802 action->rewrite->data = (u8 *)hw_actions; 1803 action->rewrite->num_of_actions = num_hw_actions; 1804 action->rewrite->index = (mlx5dr_icm_pool_get_chunk_icm_addr(chunk) - 1805 dmn->info.caps.hdr_modify_icm_addr) / 1806 ACTION_CACHE_LINE_SIZE; 1807 1808 ret = mlx5dr_send_postsend_action(dmn, action); 1809 if (ret) 1810 goto free_hw_actions; 1811 1812 return 0; 1813 1814 free_hw_actions: 1815 kfree(hw_actions); 1816 free_chunk: 1817 mlx5dr_icm_free_chunk(chunk); 1818 return ret; 1819 } 1820 1821 struct mlx5dr_action * 1822 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn, 1823 u32 flags, 1824 size_t actions_sz, 1825 __be64 actions[]) 1826 { 1827 struct mlx5dr_action *action; 1828 int ret = 0; 1829 1830 refcount_inc(&dmn->refcount); 1831 1832 if (actions_sz % DR_MODIFY_ACTION_SIZE) { 1833 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n"); 1834 goto dec_ref; 1835 } 1836 1837 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR); 1838 if (!action) 1839 goto dec_ref; 1840 1841 action->rewrite->dmn = dmn; 1842 1843 ret = dr_action_create_modify_action(dmn, 1844 actions_sz, 1845 actions, 1846 action); 1847 if (ret) { 1848 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret); 1849 goto free_action; 1850 } 1851 1852 return action; 1853 1854 free_action: 1855 kfree(action); 1856 dec_ref: 1857 refcount_dec(&dmn->refcount); 1858 return NULL; 1859 } 1860 1861 struct mlx5dr_action * 1862 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn, 1863 u16 vport, u8 vhca_id_valid, 1864 u16 vhca_id) 1865 { 1866 struct mlx5dr_cmd_vport_cap *vport_cap; 1867 struct mlx5dr_domain *vport_dmn; 1868 struct mlx5dr_action *action; 1869 u8 peer_vport; 1870 1871 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi); 1872 vport_dmn = peer_vport ? dmn->peer_dmn : dmn; 1873 if (!vport_dmn) { 1874 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n"); 1875 return NULL; 1876 } 1877 1878 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1879 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n"); 1880 return NULL; 1881 } 1882 1883 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport); 1884 if (!vport_cap) { 1885 mlx5dr_err(dmn, 1886 "Failed to get vport 0x%x caps - vport is disabled or invalid\n", 1887 vport); 1888 return NULL; 1889 } 1890 1891 action = dr_action_create_generic(DR_ACTION_TYP_VPORT); 1892 if (!action) 1893 return NULL; 1894 1895 action->vport->dmn = vport_dmn; 1896 action->vport->caps = vport_cap; 1897 1898 return action; 1899 } 1900 1901 struct mlx5dr_action * 1902 mlx5dr_action_create_aso(struct mlx5dr_domain *dmn, u32 obj_id, 1903 u8 dest_reg_id, u8 aso_type, 1904 u8 init_color, u8 meter_id) 1905 { 1906 struct mlx5dr_action *action; 1907 1908 if (aso_type != MLX5_EXE_ASO_FLOW_METER) 1909 return NULL; 1910 1911 if (init_color > MLX5_FLOW_METER_COLOR_UNDEFINED) 1912 return NULL; 1913 1914 action = dr_action_create_generic(DR_ACTION_TYP_ASO_FLOW_METER); 1915 if (!action) 1916 return NULL; 1917 1918 action->aso->obj_id = obj_id; 1919 action->aso->offset = meter_id; 1920 action->aso->dest_reg_id = dest_reg_id; 1921 action->aso->init_color = init_color; 1922 action->aso->dmn = dmn; 1923 1924 refcount_inc(&dmn->refcount); 1925 1926 return action; 1927 } 1928 1929 int mlx5dr_action_destroy(struct mlx5dr_action *action) 1930 { 1931 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1)) 1932 return -EBUSY; 1933 1934 switch (action->action_type) { 1935 case DR_ACTION_TYP_FT: 1936 if (action->dest_tbl->is_fw_tbl) 1937 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount); 1938 else 1939 refcount_dec(&action->dest_tbl->tbl->refcount); 1940 1941 if (action->dest_tbl->is_fw_tbl && 1942 action->dest_tbl->fw_tbl.num_of_ref_actions) { 1943 struct mlx5dr_action **ref_actions; 1944 int i; 1945 1946 ref_actions = action->dest_tbl->fw_tbl.ref_actions; 1947 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++) 1948 refcount_dec(&ref_actions[i]->refcount); 1949 1950 kfree(ref_actions); 1951 1952 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn, 1953 action->dest_tbl->fw_tbl.id, 1954 action->dest_tbl->fw_tbl.group_id); 1955 } 1956 break; 1957 case DR_ACTION_TYP_TNL_L2_TO_L2: 1958 case DR_ACTION_TYP_REMOVE_HDR: 1959 refcount_dec(&action->reformat->dmn->refcount); 1960 break; 1961 case DR_ACTION_TYP_TNL_L3_TO_L2: 1962 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1963 refcount_dec(&action->rewrite->dmn->refcount); 1964 break; 1965 case DR_ACTION_TYP_L2_TO_TNL_L2: 1966 case DR_ACTION_TYP_L2_TO_TNL_L3: 1967 case DR_ACTION_TYP_INSERT_HDR: 1968 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev, 1969 action->reformat->id); 1970 refcount_dec(&action->reformat->dmn->refcount); 1971 break; 1972 case DR_ACTION_TYP_MODIFY_HDR: 1973 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1974 kfree(action->rewrite->data); 1975 refcount_dec(&action->rewrite->dmn->refcount); 1976 break; 1977 case DR_ACTION_TYP_SAMPLER: 1978 refcount_dec(&action->sampler->dmn->refcount); 1979 break; 1980 case DR_ACTION_TYP_ASO_FLOW_METER: 1981 refcount_dec(&action->aso->dmn->refcount); 1982 break; 1983 default: 1984 break; 1985 } 1986 1987 kfree(action); 1988 return 0; 1989 } 1990