1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "dr_types.h" 5 #include "dr_ste.h" 6 7 enum dr_action_domain { 8 DR_ACTION_DOMAIN_NIC_INGRESS, 9 DR_ACTION_DOMAIN_NIC_EGRESS, 10 DR_ACTION_DOMAIN_FDB_INGRESS, 11 DR_ACTION_DOMAIN_FDB_EGRESS, 12 DR_ACTION_DOMAIN_MAX, 13 }; 14 15 enum dr_action_valid_state { 16 DR_ACTION_STATE_ERR, 17 DR_ACTION_STATE_NO_ACTION, 18 DR_ACTION_STATE_ENCAP, 19 DR_ACTION_STATE_DECAP, 20 DR_ACTION_STATE_MODIFY_HDR, 21 DR_ACTION_STATE_POP_VLAN, 22 DR_ACTION_STATE_PUSH_VLAN, 23 DR_ACTION_STATE_NON_TERM, 24 DR_ACTION_STATE_TERM, 25 DR_ACTION_STATE_ASO, 26 DR_ACTION_STATE_MAX, 27 }; 28 29 static const char * const action_type_to_str[] = { 30 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2", 31 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2", 32 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2", 33 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3", 34 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP", 35 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP", 36 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT", 37 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR", 38 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG", 39 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR", 40 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT", 41 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN", 42 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN", 43 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER", 44 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR", 45 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR", 46 [DR_ACTION_TYP_ASO_FLOW_METER] = "DR_ACTION_TYP_ASO_FLOW_METER", 47 [DR_ACTION_TYP_RANGE] = "DR_ACTION_TYP_RANGE", 48 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN", 49 }; 50 51 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id) 52 { 53 if (action_id > DR_ACTION_TYP_MAX) 54 action_id = DR_ACTION_TYP_MAX; 55 return action_type_to_str[action_id]; 56 } 57 58 static const enum dr_action_valid_state 59 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = { 60 [DR_ACTION_DOMAIN_NIC_INGRESS] = { 61 [DR_ACTION_STATE_NO_ACTION] = { 62 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 63 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 64 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 65 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 66 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 67 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 68 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 69 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 70 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 71 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 72 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 73 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 74 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 75 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 76 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 77 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 78 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 79 }, 80 [DR_ACTION_STATE_DECAP] = { 81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 82 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 83 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 84 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 85 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 86 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP, 87 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 88 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 89 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 90 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 91 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 92 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 93 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 94 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 95 }, 96 [DR_ACTION_STATE_ENCAP] = { 97 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 98 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 99 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 100 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 101 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 102 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP, 103 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 104 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 105 }, 106 [DR_ACTION_STATE_MODIFY_HDR] = { 107 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 108 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 109 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 110 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 111 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 112 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR, 113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 116 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 118 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 119 }, 120 [DR_ACTION_STATE_POP_VLAN] = { 121 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 122 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 123 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 124 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 125 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 126 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN, 127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 128 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 129 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 130 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 131 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 132 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 133 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 134 }, 135 [DR_ACTION_STATE_PUSH_VLAN] = { 136 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 137 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 138 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 139 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 140 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN, 141 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 142 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 143 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 144 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 145 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 146 }, 147 [DR_ACTION_STATE_NON_TERM] = { 148 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 149 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 151 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 152 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 153 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 154 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 155 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 156 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 157 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 158 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 159 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 160 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 161 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 162 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 163 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 164 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 165 }, 166 [DR_ACTION_STATE_ASO] = { 167 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 168 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 169 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 170 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 171 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 172 }, 173 [DR_ACTION_STATE_TERM] = { 174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 175 }, 176 }, 177 [DR_ACTION_DOMAIN_NIC_EGRESS] = { 178 [DR_ACTION_STATE_NO_ACTION] = { 179 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 180 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 181 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 182 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 183 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 184 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 185 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 186 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 187 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 188 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 189 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 190 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 191 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 192 }, 193 [DR_ACTION_STATE_DECAP] = { 194 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 195 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 196 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 197 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 198 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 199 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 200 }, 201 [DR_ACTION_STATE_ENCAP] = { 202 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 203 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 204 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 205 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 206 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 207 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 208 }, 209 [DR_ACTION_STATE_MODIFY_HDR] = { 210 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 211 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 212 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 213 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 214 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 215 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 216 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 217 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 218 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 219 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 220 }, 221 [DR_ACTION_STATE_POP_VLAN] = { 222 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 223 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 224 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 225 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 226 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 227 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 228 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 229 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 230 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 231 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 232 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 233 }, 234 [DR_ACTION_STATE_PUSH_VLAN] = { 235 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 236 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 237 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 238 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 239 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 240 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 241 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 242 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 243 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 244 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 245 }, 246 [DR_ACTION_STATE_NON_TERM] = { 247 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 248 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 249 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 250 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 251 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 252 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 253 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 254 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 255 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 256 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 257 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 258 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 259 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 260 }, 261 [DR_ACTION_STATE_ASO] = { 262 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 263 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 264 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 265 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 266 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 267 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 268 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 269 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 270 }, 271 [DR_ACTION_STATE_TERM] = { 272 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 273 }, 274 }, 275 [DR_ACTION_DOMAIN_FDB_INGRESS] = { 276 [DR_ACTION_STATE_NO_ACTION] = { 277 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 278 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 279 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 280 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 281 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 282 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 283 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 284 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 285 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 286 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 287 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 288 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 289 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 290 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 291 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 292 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 293 }, 294 [DR_ACTION_STATE_DECAP] = { 295 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 296 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 297 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 298 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 299 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 300 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 301 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 302 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 303 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 304 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 305 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 306 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 307 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 308 }, 309 [DR_ACTION_STATE_ENCAP] = { 310 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 311 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 312 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 313 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 314 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 315 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 316 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 317 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 318 }, 319 [DR_ACTION_STATE_MODIFY_HDR] = { 320 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 321 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 322 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 323 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 324 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 325 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 326 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 327 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 328 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 329 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 330 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 331 }, 332 [DR_ACTION_STATE_POP_VLAN] = { 333 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 334 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 335 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 336 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 337 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 338 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 339 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 340 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 341 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 342 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 343 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 344 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 345 }, 346 [DR_ACTION_STATE_PUSH_VLAN] = { 347 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 348 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 349 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 350 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 351 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 352 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 353 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 354 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 355 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 356 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 357 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 358 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 359 }, 360 [DR_ACTION_STATE_NON_TERM] = { 361 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 362 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 363 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 364 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 365 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 366 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 367 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 368 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 369 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 370 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 371 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 372 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 373 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 374 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 375 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 376 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 377 }, 378 [DR_ACTION_STATE_ASO] = { 379 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 380 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 381 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 382 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 383 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 384 }, 385 [DR_ACTION_STATE_TERM] = { 386 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 387 }, 388 }, 389 [DR_ACTION_DOMAIN_FDB_EGRESS] = { 390 [DR_ACTION_STATE_NO_ACTION] = { 391 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 392 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 393 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 394 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 395 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 396 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 397 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 398 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 399 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 400 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 401 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 402 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 403 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 404 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 405 }, 406 [DR_ACTION_STATE_DECAP] = { 407 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 408 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 409 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 410 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 411 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 412 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 413 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 414 }, 415 [DR_ACTION_STATE_ENCAP] = { 416 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 417 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 418 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 419 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 420 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 421 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 422 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 423 }, 424 [DR_ACTION_STATE_MODIFY_HDR] = { 425 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 426 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 427 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 428 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 429 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 430 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 431 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 432 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 433 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 434 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 435 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 436 }, 437 [DR_ACTION_STATE_POP_VLAN] = { 438 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 439 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 440 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 441 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 442 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 443 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 444 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 445 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 446 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 447 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 448 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 449 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 450 }, 451 [DR_ACTION_STATE_PUSH_VLAN] = { 452 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 453 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 454 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 455 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 456 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 457 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 458 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 459 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 460 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 461 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 462 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 463 }, 464 [DR_ACTION_STATE_NON_TERM] = { 465 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 466 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 467 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 468 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 469 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 470 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 471 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 472 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 473 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 474 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 475 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 476 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 477 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 478 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 479 }, 480 [DR_ACTION_STATE_ASO] = { 481 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 482 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 483 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 484 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 485 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 486 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 487 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 488 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 489 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 490 }, 491 [DR_ACTION_STATE_TERM] = { 492 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 493 }, 494 }, 495 }; 496 497 static int 498 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type, 499 enum mlx5dr_action_type *action_type) 500 { 501 switch (reformat_type) { 502 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2: 503 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2; 504 break; 505 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2: 506 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2; 507 break; 508 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2: 509 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2; 510 break; 511 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3: 512 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3; 513 break; 514 case DR_ACTION_REFORMAT_TYP_INSERT_HDR: 515 *action_type = DR_ACTION_TYP_INSERT_HDR; 516 break; 517 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR: 518 *action_type = DR_ACTION_TYP_REMOVE_HDR; 519 break; 520 default: 521 return -EINVAL; 522 } 523 524 return 0; 525 } 526 527 /* Apply the actions on the rule STE array starting from the last_ste. 528 * Actions might require more than one STE, new_num_stes will return 529 * the new size of the STEs array, rule with actions. 530 */ 531 static void dr_actions_apply(struct mlx5dr_domain *dmn, 532 enum mlx5dr_domain_nic_type nic_type, 533 u8 *action_type_set, 534 u8 *last_ste, 535 struct mlx5dr_ste_actions_attr *attr, 536 u32 *new_num_stes) 537 { 538 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; 539 u32 added_stes = 0; 540 541 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 542 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set, 543 last_ste, attr, &added_stes); 544 else 545 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set, 546 last_ste, attr, &added_stes); 547 548 *new_num_stes += added_stes; 549 } 550 551 static enum dr_action_domain 552 dr_action_get_action_domain(enum mlx5dr_domain_type domain, 553 enum mlx5dr_domain_nic_type nic_type) 554 { 555 switch (domain) { 556 case MLX5DR_DOMAIN_TYPE_NIC_RX: 557 return DR_ACTION_DOMAIN_NIC_INGRESS; 558 case MLX5DR_DOMAIN_TYPE_NIC_TX: 559 return DR_ACTION_DOMAIN_NIC_EGRESS; 560 case MLX5DR_DOMAIN_TYPE_FDB: 561 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 562 return DR_ACTION_DOMAIN_FDB_INGRESS; 563 return DR_ACTION_DOMAIN_FDB_EGRESS; 564 default: 565 WARN_ON(true); 566 return DR_ACTION_DOMAIN_MAX; 567 } 568 } 569 570 static 571 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain, 572 u32 action_type, 573 u32 *state) 574 { 575 u32 cur_state = *state; 576 577 /* Check action state machine is valid */ 578 *state = next_action_state[action_domain][cur_state][action_type]; 579 580 if (*state == DR_ACTION_STATE_ERR) 581 return -EOPNOTSUPP; 582 583 return 0; 584 } 585 586 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, 587 struct mlx5dr_action *dest_action, 588 u64 *final_icm_addr) 589 { 590 int ret; 591 592 switch (dest_action->action_type) { 593 case DR_ACTION_TYP_FT: 594 /* Allow destination flow table only if table is a terminating 595 * table, since there is an *assumption* that in such case FW 596 * will recalculate the CS. 597 */ 598 if (dest_action->dest_tbl->is_fw_tbl) { 599 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr; 600 } else { 601 mlx5dr_dbg(dmn, 602 "Destination FT should be terminating when modify TTL is used\n"); 603 return -EINVAL; 604 } 605 break; 606 607 case DR_ACTION_TYP_VPORT: 608 /* If destination is vport we will get the FW flow table 609 * that recalculates the CS and forwards to the vport. 610 */ 611 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn, 612 dest_action->vport->caps->num, 613 final_icm_addr); 614 if (ret) { 615 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); 616 return ret; 617 } 618 break; 619 620 default: 621 break; 622 } 623 624 return 0; 625 } 626 627 static void dr_action_modify_ttl_adjust(struct mlx5dr_domain *dmn, 628 struct mlx5dr_ste_actions_attr *attr, 629 bool rx_rule, 630 bool *recalc_cs_required) 631 { 632 *recalc_cs_required = false; 633 634 /* if device supports csum recalculation - no adjustment needed */ 635 if (mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps)) 636 return; 637 638 /* no adjustment needed on TX rules */ 639 if (!rx_rule) 640 return; 641 642 if (!MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify)) { 643 /* Ignore the modify TTL action. 644 * It is always kept as last HW action. 645 */ 646 attr->modify_actions--; 647 return; 648 } 649 650 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 651 /* Due to a HW bug on some devices, modifying TTL on RX flows 652 * will cause an incorrect checksum calculation. In such cases 653 * we will use a FW table to recalculate the checksum. 654 */ 655 *recalc_cs_required = true; 656 } 657 658 static void dr_action_print_sequence(struct mlx5dr_domain *dmn, 659 struct mlx5dr_action *actions[], 660 int last_idx) 661 { 662 int i; 663 664 for (i = 0; i <= last_idx; i++) 665 mlx5dr_err(dmn, "< %s (%d) > ", 666 dr_action_id_to_str(actions[i]->action_type), 667 actions[i]->action_type); 668 } 669 670 static int dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher *matcher, 671 struct mlx5dr_action_dest_tbl *dest_tbl, 672 bool is_rx_rule, 673 u64 *final_icm_addr) 674 { 675 struct mlx5dr_cmd_query_flow_table_details output; 676 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 677 int ret; 678 679 if (!dest_tbl->fw_tbl.rx_icm_addr) { 680 ret = mlx5dr_cmd_query_flow_table(dmn->mdev, 681 dest_tbl->fw_tbl.type, 682 dest_tbl->fw_tbl.id, 683 &output); 684 if (ret) { 685 mlx5dr_err(dmn, 686 "Failed mlx5_cmd_query_flow_table ret: %d\n", 687 ret); 688 return ret; 689 } 690 691 dest_tbl->fw_tbl.tx_icm_addr = output.sw_owner_icm_root_1; 692 dest_tbl->fw_tbl.rx_icm_addr = output.sw_owner_icm_root_0; 693 } 694 695 *final_icm_addr = is_rx_rule ? dest_tbl->fw_tbl.rx_icm_addr : 696 dest_tbl->fw_tbl.tx_icm_addr; 697 return 0; 698 } 699 700 static int dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher *matcher, 701 struct mlx5dr_action_dest_tbl *dest_tbl, 702 bool is_rx_rule, 703 u64 *final_icm_addr) 704 { 705 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 706 struct mlx5dr_icm_chunk *chunk; 707 708 if (dest_tbl->tbl->dmn != dmn) { 709 mlx5dr_err(dmn, 710 "Destination table belongs to a different domain\n"); 711 return -EINVAL; 712 } 713 714 if (dest_tbl->tbl->level <= matcher->tbl->level) { 715 mlx5_core_dbg_once(dmn->mdev, 716 "Connecting table to a lower/same level destination table\n"); 717 mlx5dr_dbg(dmn, 718 "Connecting table at level %d to a destination table at level %d\n", 719 matcher->tbl->level, 720 dest_tbl->tbl->level); 721 } 722 723 chunk = is_rx_rule ? dest_tbl->tbl->rx.s_anchor->chunk : 724 dest_tbl->tbl->tx.s_anchor->chunk; 725 726 *final_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(chunk); 727 return 0; 728 } 729 730 static int dr_action_get_dest_tbl_addr(struct mlx5dr_matcher *matcher, 731 struct mlx5dr_action_dest_tbl *dest_tbl, 732 bool is_rx_rule, 733 u64 *final_icm_addr) 734 { 735 if (dest_tbl->is_fw_tbl) 736 return dr_action_get_dest_fw_tbl_addr(matcher, 737 dest_tbl, 738 is_rx_rule, 739 final_icm_addr); 740 741 return dr_action_get_dest_sw_tbl_addr(matcher, 742 dest_tbl, 743 is_rx_rule, 744 final_icm_addr); 745 } 746 747 #define WITH_VLAN_NUM_HW_ACTIONS 6 748 749 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 750 struct mlx5dr_matcher_rx_tx *nic_matcher, 751 struct mlx5dr_action *actions[], 752 u32 num_actions, 753 u8 *ste_arr, 754 u32 *new_hw_ste_arr_sz) 755 { 756 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn; 757 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX; 758 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 759 u8 action_type_set[DR_ACTION_TYP_MAX] = {}; 760 struct mlx5dr_ste_actions_attr attr = {}; 761 struct mlx5dr_action *dest_action = NULL; 762 u32 state = DR_ACTION_STATE_NO_ACTION; 763 enum dr_action_domain action_domain; 764 bool recalc_cs_required = false; 765 u8 *last_ste; 766 int i, ret; 767 768 attr.gvmi = dmn->info.caps.gvmi; 769 attr.hit_gvmi = dmn->info.caps.gvmi; 770 attr.final_icm_addr = nic_dmn->default_icm_addr; 771 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type); 772 773 for (i = 0; i < num_actions; i++) { 774 struct mlx5dr_action *action; 775 int max_actions_type = 1; 776 u32 action_type; 777 778 action = actions[i]; 779 action_type = action->action_type; 780 781 switch (action_type) { 782 case DR_ACTION_TYP_DROP: 783 attr.final_icm_addr = nic_dmn->drop_icm_addr; 784 break; 785 case DR_ACTION_TYP_FT: 786 dest_action = action; 787 ret = dr_action_get_dest_tbl_addr(matcher, action->dest_tbl, 788 rx_rule, &attr.final_icm_addr); 789 if (ret) 790 return ret; 791 break; 792 case DR_ACTION_TYP_RANGE: 793 ret = dr_action_get_dest_tbl_addr(matcher, 794 action->range->hit_tbl_action->dest_tbl, 795 rx_rule, &attr.final_icm_addr); 796 if (ret) 797 return ret; 798 799 ret = dr_action_get_dest_tbl_addr(matcher, 800 action->range->miss_tbl_action->dest_tbl, 801 rx_rule, &attr.range.miss_icm_addr); 802 if (ret) 803 return ret; 804 805 attr.range.definer_id = action->range->definer_id; 806 attr.range.min = action->range->min; 807 attr.range.max = action->range->max; 808 break; 809 case DR_ACTION_TYP_QP: 810 mlx5dr_info(dmn, "Domain doesn't support QP\n"); 811 return -EOPNOTSUPP; 812 case DR_ACTION_TYP_CTR: 813 attr.ctr_id = action->ctr->ctr_id + 814 action->ctr->offset; 815 break; 816 case DR_ACTION_TYP_TAG: 817 attr.flow_tag = action->flow_tag->flow_tag; 818 break; 819 case DR_ACTION_TYP_TNL_L2_TO_L2: 820 break; 821 case DR_ACTION_TYP_TNL_L3_TO_L2: 822 attr.decap_index = action->rewrite->index; 823 attr.decap_actions = action->rewrite->num_of_actions; 824 attr.decap_with_vlan = 825 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS; 826 break; 827 case DR_ACTION_TYP_MODIFY_HDR: 828 attr.modify_index = action->rewrite->index; 829 attr.modify_actions = action->rewrite->num_of_actions; 830 if (action->rewrite->modify_ttl) 831 dr_action_modify_ttl_adjust(dmn, &attr, rx_rule, 832 &recalc_cs_required); 833 break; 834 case DR_ACTION_TYP_L2_TO_TNL_L2: 835 case DR_ACTION_TYP_L2_TO_TNL_L3: 836 if (rx_rule && 837 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) { 838 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n"); 839 return -EOPNOTSUPP; 840 } 841 attr.reformat.size = action->reformat->size; 842 attr.reformat.id = action->reformat->id; 843 break; 844 case DR_ACTION_TYP_SAMPLER: 845 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr : 846 action->sampler->tx_icm_addr; 847 break; 848 case DR_ACTION_TYP_VPORT: 849 attr.hit_gvmi = action->vport->caps->vhca_gvmi; 850 dest_action = action; 851 attr.final_icm_addr = rx_rule ? 852 action->vport->caps->icm_address_rx : 853 action->vport->caps->icm_address_tx; 854 break; 855 case DR_ACTION_TYP_POP_VLAN: 856 if (!rx_rule && !(dmn->ste_ctx->actions_caps & 857 DR_STE_CTX_ACTION_CAP_TX_POP)) { 858 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n"); 859 return -EOPNOTSUPP; 860 } 861 862 max_actions_type = MLX5DR_MAX_VLANS; 863 attr.vlans.count++; 864 break; 865 case DR_ACTION_TYP_PUSH_VLAN: 866 if (rx_rule && !(dmn->ste_ctx->actions_caps & 867 DR_STE_CTX_ACTION_CAP_RX_PUSH)) { 868 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n"); 869 return -EOPNOTSUPP; 870 } 871 872 max_actions_type = MLX5DR_MAX_VLANS; 873 if (attr.vlans.count == MLX5DR_MAX_VLANS) { 874 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n"); 875 return -EINVAL; 876 } 877 878 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr; 879 break; 880 case DR_ACTION_TYP_INSERT_HDR: 881 case DR_ACTION_TYP_REMOVE_HDR: 882 attr.reformat.size = action->reformat->size; 883 attr.reformat.id = action->reformat->id; 884 attr.reformat.param_0 = action->reformat->param_0; 885 attr.reformat.param_1 = action->reformat->param_1; 886 break; 887 case DR_ACTION_TYP_ASO_FLOW_METER: 888 attr.aso_flow_meter.obj_id = action->aso->obj_id; 889 attr.aso_flow_meter.offset = action->aso->offset; 890 attr.aso_flow_meter.dest_reg_id = action->aso->dest_reg_id; 891 attr.aso_flow_meter.init_color = action->aso->init_color; 892 break; 893 default: 894 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type); 895 return -EINVAL; 896 } 897 898 /* Check action duplication */ 899 if (++action_type_set[action_type] > max_actions_type) { 900 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n", 901 action_type, max_actions_type); 902 return -EINVAL; 903 } 904 905 /* Check action state machine is valid */ 906 if (dr_action_validate_and_get_next_state(action_domain, 907 action_type, 908 &state)) { 909 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:", 910 attr.gvmi, rx_rule); 911 dr_action_print_sequence(dmn, actions, i); 912 return -EOPNOTSUPP; 913 } 914 } 915 916 *new_hw_ste_arr_sz = nic_matcher->num_of_builders; 917 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1); 918 919 if (recalc_cs_required && dest_action) { 920 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr); 921 if (ret) { 922 mlx5dr_err(dmn, 923 "Failed to handle checksum recalculation err %d\n", 924 ret); 925 return ret; 926 } 927 } 928 929 dr_actions_apply(dmn, 930 nic_dmn->type, 931 action_type_set, 932 last_ste, 933 &attr, 934 new_hw_ste_arr_sz); 935 936 return 0; 937 } 938 939 static unsigned int action_size[DR_ACTION_TYP_MAX] = { 940 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat), 941 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat), 942 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite), 943 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat), 944 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl), 945 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr), 946 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag), 947 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite), 948 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport), 949 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan), 950 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat), 951 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat), 952 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler), 953 [DR_ACTION_TYP_ASO_FLOW_METER] = sizeof(struct mlx5dr_action_aso_flow_meter), 954 [DR_ACTION_TYP_RANGE] = sizeof(struct mlx5dr_action_range), 955 }; 956 957 static struct mlx5dr_action * 958 dr_action_create_generic(enum mlx5dr_action_type action_type) 959 { 960 struct mlx5dr_action *action; 961 int extra_size; 962 963 if (action_type < DR_ACTION_TYP_MAX) 964 extra_size = action_size[action_type]; 965 else 966 return NULL; 967 968 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL); 969 if (!action) 970 return NULL; 971 972 action->action_type = action_type; 973 refcount_set(&action->refcount, 1); 974 action->data = action + 1; 975 976 return action; 977 } 978 979 struct mlx5dr_action *mlx5dr_action_create_drop(void) 980 { 981 return dr_action_create_generic(DR_ACTION_TYP_DROP); 982 } 983 984 struct mlx5dr_action * 985 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num) 986 { 987 struct mlx5dr_action *action; 988 989 action = dr_action_create_generic(DR_ACTION_TYP_FT); 990 if (!action) 991 return NULL; 992 993 action->dest_tbl->is_fw_tbl = true; 994 action->dest_tbl->fw_tbl.dmn = dmn; 995 action->dest_tbl->fw_tbl.id = table_num; 996 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 997 refcount_inc(&dmn->refcount); 998 999 return action; 1000 } 1001 1002 struct mlx5dr_action * 1003 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl) 1004 { 1005 struct mlx5dr_action *action; 1006 1007 refcount_inc(&tbl->refcount); 1008 1009 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1010 if (!action) 1011 goto dec_ref; 1012 1013 action->dest_tbl->tbl = tbl; 1014 1015 return action; 1016 1017 dec_ref: 1018 refcount_dec(&tbl->refcount); 1019 return NULL; 1020 } 1021 1022 static void dr_action_range_definer_fill(u16 *format_id, 1023 u8 *dw_selectors, 1024 u8 *byte_selectors, 1025 u8 *match_mask) 1026 { 1027 int i; 1028 1029 *format_id = MLX5_IFC_DEFINER_FORMAT_ID_SELECT; 1030 1031 dw_selectors[0] = MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN / 4; 1032 1033 for (i = 1; i < MLX5_IFC_DEFINER_DW_SELECTORS_NUM; i++) 1034 dw_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED; 1035 1036 for (i = 0; i < MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM; i++) 1037 byte_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED; 1038 1039 MLX5_SET(match_definer_match_mask, match_mask, 1040 match_dw_0, 0xffffUL << 16); 1041 } 1042 1043 static int dr_action_create_range_definer(struct mlx5dr_action *action) 1044 { 1045 u8 match_mask[MLX5_FLD_SZ_BYTES(match_definer, match_mask)] = {}; 1046 u8 byte_selectors[MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM] = {}; 1047 u8 dw_selectors[MLX5_IFC_DEFINER_DW_SELECTORS_NUM] = {}; 1048 struct mlx5dr_domain *dmn = action->range->dmn; 1049 u32 definer_id; 1050 u16 format_id; 1051 int ret; 1052 1053 dr_action_range_definer_fill(&format_id, 1054 dw_selectors, 1055 byte_selectors, 1056 match_mask); 1057 1058 ret = mlx5dr_definer_get(dmn, format_id, 1059 dw_selectors, byte_selectors, 1060 match_mask, &definer_id); 1061 if (ret) 1062 return ret; 1063 1064 action->range->definer_id = definer_id; 1065 return 0; 1066 } 1067 1068 static void dr_action_destroy_range_definer(struct mlx5dr_action *action) 1069 { 1070 mlx5dr_definer_put(action->range->dmn, action->range->definer_id); 1071 } 1072 1073 struct mlx5dr_action * 1074 mlx5dr_action_create_dest_match_range(struct mlx5dr_domain *dmn, 1075 u32 field, 1076 struct mlx5_flow_table *hit_ft, 1077 struct mlx5_flow_table *miss_ft, 1078 u32 min, 1079 u32 max) 1080 { 1081 struct mlx5dr_action *action; 1082 int ret; 1083 1084 if (!mlx5dr_supp_match_ranges(dmn->mdev)) { 1085 mlx5dr_dbg(dmn, "SELECT definer support is needed for match range\n"); 1086 return NULL; 1087 } 1088 1089 if (field != MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN || 1090 min > 0xffff || max > 0xffff) { 1091 mlx5dr_err(dmn, "Invalid match range parameters\n"); 1092 return NULL; 1093 } 1094 1095 action = dr_action_create_generic(DR_ACTION_TYP_RANGE); 1096 if (!action) 1097 return NULL; 1098 1099 action->range->hit_tbl_action = 1100 mlx5dr_is_fw_table(hit_ft) ? 1101 mlx5dr_action_create_dest_flow_fw_table(dmn, hit_ft) : 1102 mlx5dr_action_create_dest_table(hit_ft->fs_dr_table.dr_table); 1103 1104 if (!action->range->hit_tbl_action) 1105 goto free_action; 1106 1107 action->range->miss_tbl_action = 1108 mlx5dr_is_fw_table(miss_ft) ? 1109 mlx5dr_action_create_dest_flow_fw_table(dmn, miss_ft) : 1110 mlx5dr_action_create_dest_table(miss_ft->fs_dr_table.dr_table); 1111 1112 if (!action->range->miss_tbl_action) 1113 goto free_hit_tbl_action; 1114 1115 action->range->min = min; 1116 action->range->max = max; 1117 action->range->dmn = dmn; 1118 1119 ret = dr_action_create_range_definer(action); 1120 if (ret) 1121 goto free_miss_tbl_action; 1122 1123 /* No need to increase refcount on domain for this action, 1124 * the hit/miss table actions will do it internally. 1125 */ 1126 1127 return action; 1128 1129 free_miss_tbl_action: 1130 mlx5dr_action_destroy(action->range->miss_tbl_action); 1131 free_hit_tbl_action: 1132 mlx5dr_action_destroy(action->range->hit_tbl_action); 1133 free_action: 1134 kfree(action); 1135 1136 return NULL; 1137 } 1138 1139 struct mlx5dr_action * 1140 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn, 1141 struct mlx5dr_action_dest *dests, 1142 u32 num_of_dests, 1143 bool ignore_flow_level, 1144 u32 flow_source) 1145 { 1146 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests; 1147 struct mlx5dr_action **ref_actions; 1148 struct mlx5dr_action *action; 1149 bool reformat_req = false; 1150 u32 num_of_ref = 0; 1151 u32 ref_act_cnt; 1152 int ret; 1153 int i; 1154 1155 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1156 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n"); 1157 return NULL; 1158 } 1159 1160 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL); 1161 if (!hw_dests) 1162 return NULL; 1163 1164 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt))) 1165 goto free_hw_dests; 1166 1167 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL); 1168 if (!ref_actions) 1169 goto free_hw_dests; 1170 1171 for (i = 0; i < num_of_dests; i++) { 1172 struct mlx5dr_action *reformat_action = dests[i].reformat; 1173 struct mlx5dr_action *dest_action = dests[i].dest; 1174 1175 ref_actions[num_of_ref++] = dest_action; 1176 1177 switch (dest_action->action_type) { 1178 case DR_ACTION_TYP_VPORT: 1179 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID; 1180 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; 1181 hw_dests[i].vport.num = dest_action->vport->caps->num; 1182 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi; 1183 if (reformat_action) { 1184 reformat_req = true; 1185 hw_dests[i].vport.reformat_id = 1186 reformat_action->reformat->id; 1187 ref_actions[num_of_ref++] = reformat_action; 1188 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; 1189 } 1190 break; 1191 1192 case DR_ACTION_TYP_FT: 1193 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 1194 if (dest_action->dest_tbl->is_fw_tbl) 1195 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id; 1196 else 1197 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id; 1198 break; 1199 1200 default: 1201 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n"); 1202 goto free_ref_actions; 1203 } 1204 } 1205 1206 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1207 if (!action) 1208 goto free_ref_actions; 1209 1210 ret = mlx5dr_fw_create_md_tbl(dmn, 1211 hw_dests, 1212 num_of_dests, 1213 reformat_req, 1214 &action->dest_tbl->fw_tbl.id, 1215 &action->dest_tbl->fw_tbl.group_id, 1216 ignore_flow_level, 1217 flow_source); 1218 if (ret) 1219 goto free_action; 1220 1221 refcount_inc(&dmn->refcount); 1222 1223 for (i = 0; i < num_of_ref; i++) 1224 refcount_inc(&ref_actions[i]->refcount); 1225 1226 action->dest_tbl->is_fw_tbl = true; 1227 action->dest_tbl->fw_tbl.dmn = dmn; 1228 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 1229 action->dest_tbl->fw_tbl.ref_actions = ref_actions; 1230 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref; 1231 1232 kfree(hw_dests); 1233 1234 return action; 1235 1236 free_action: 1237 kfree(action); 1238 free_ref_actions: 1239 kfree(ref_actions); 1240 free_hw_dests: 1241 kfree(hw_dests); 1242 return NULL; 1243 } 1244 1245 struct mlx5dr_action * 1246 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn, 1247 struct mlx5_flow_table *ft) 1248 { 1249 struct mlx5dr_action *action; 1250 1251 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1252 if (!action) 1253 return NULL; 1254 1255 action->dest_tbl->is_fw_tbl = 1; 1256 action->dest_tbl->fw_tbl.type = ft->type; 1257 action->dest_tbl->fw_tbl.id = ft->id; 1258 action->dest_tbl->fw_tbl.dmn = dmn; 1259 1260 refcount_inc(&dmn->refcount); 1261 1262 return action; 1263 } 1264 1265 struct mlx5dr_action * 1266 mlx5dr_action_create_flow_counter(u32 counter_id) 1267 { 1268 struct mlx5dr_action *action; 1269 1270 action = dr_action_create_generic(DR_ACTION_TYP_CTR); 1271 if (!action) 1272 return NULL; 1273 1274 action->ctr->ctr_id = counter_id; 1275 1276 return action; 1277 } 1278 1279 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value) 1280 { 1281 struct mlx5dr_action *action; 1282 1283 action = dr_action_create_generic(DR_ACTION_TYP_TAG); 1284 if (!action) 1285 return NULL; 1286 1287 action->flow_tag->flow_tag = tag_value & 0xffffff; 1288 1289 return action; 1290 } 1291 1292 struct mlx5dr_action * 1293 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id) 1294 { 1295 struct mlx5dr_action *action; 1296 u64 icm_rx, icm_tx; 1297 int ret; 1298 1299 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id, 1300 &icm_rx, &icm_tx); 1301 if (ret) 1302 return NULL; 1303 1304 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER); 1305 if (!action) 1306 return NULL; 1307 1308 action->sampler->dmn = dmn; 1309 action->sampler->sampler_id = sampler_id; 1310 action->sampler->rx_icm_addr = icm_rx; 1311 action->sampler->tx_icm_addr = icm_tx; 1312 1313 refcount_inc(&dmn->refcount); 1314 return action; 1315 } 1316 1317 static int 1318 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type, 1319 struct mlx5dr_domain *dmn, 1320 u8 reformat_param_0, 1321 u8 reformat_param_1, 1322 size_t data_sz, 1323 void *data) 1324 { 1325 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) { 1326 if ((!data && data_sz) || (data && !data_sz) || 1327 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz || 1328 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) { 1329 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n"); 1330 goto out_err; 1331 } 1332 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) { 1333 if (data || 1334 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz || 1335 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) { 1336 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n"); 1337 goto out_err; 1338 } 1339 } else if (reformat_param_0 || reformat_param_1 || 1340 reformat_type > DR_ACTION_TYP_REMOVE_HDR) { 1341 mlx5dr_dbg(dmn, "Invalid reformat parameters\n"); 1342 goto out_err; 1343 } 1344 1345 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 1346 return 0; 1347 1348 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) { 1349 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 && 1350 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) { 1351 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n"); 1352 goto out_err; 1353 } 1354 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) { 1355 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 && 1356 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) { 1357 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n"); 1358 goto out_err; 1359 } 1360 } 1361 1362 return 0; 1363 1364 out_err: 1365 return -EINVAL; 1366 } 1367 1368 #define ACTION_CACHE_LINE_SIZE 64 1369 1370 static int 1371 dr_action_create_reformat_action(struct mlx5dr_domain *dmn, 1372 u8 reformat_param_0, u8 reformat_param_1, 1373 size_t data_sz, void *data, 1374 struct mlx5dr_action *action) 1375 { 1376 u32 reformat_id; 1377 int ret; 1378 1379 switch (action->action_type) { 1380 case DR_ACTION_TYP_L2_TO_TNL_L2: 1381 case DR_ACTION_TYP_L2_TO_TNL_L3: 1382 { 1383 enum mlx5_reformat_ctx_type rt; 1384 1385 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2) 1386 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL; 1387 else 1388 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL; 1389 1390 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0, 1391 data_sz, data, 1392 &reformat_id); 1393 if (ret) 1394 return ret; 1395 1396 action->reformat->id = reformat_id; 1397 action->reformat->size = data_sz; 1398 return 0; 1399 } 1400 case DR_ACTION_TYP_TNL_L2_TO_L2: 1401 { 1402 return 0; 1403 } 1404 case DR_ACTION_TYP_TNL_L3_TO_L2: 1405 { 1406 u8 hw_actions[ACTION_CACHE_LINE_SIZE] = {}; 1407 int ret; 1408 1409 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx, 1410 data, data_sz, 1411 hw_actions, 1412 ACTION_CACHE_LINE_SIZE, 1413 &action->rewrite->num_of_actions); 1414 if (ret) { 1415 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n"); 1416 return ret; 1417 } 1418 1419 action->rewrite->chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, 1420 DR_CHUNK_SIZE_8); 1421 if (!action->rewrite->chunk) { 1422 mlx5dr_dbg(dmn, "Failed allocating modify header chunk\n"); 1423 return -ENOMEM; 1424 } 1425 1426 action->rewrite->data = (void *)hw_actions; 1427 action->rewrite->index = (mlx5dr_icm_pool_get_chunk_icm_addr 1428 (action->rewrite->chunk) - 1429 dmn->info.caps.hdr_modify_icm_addr) / 1430 ACTION_CACHE_LINE_SIZE; 1431 1432 ret = mlx5dr_send_postsend_action(dmn, action); 1433 if (ret) { 1434 mlx5dr_dbg(dmn, "Writing decap l3 actions to ICM failed\n"); 1435 mlx5dr_icm_free_chunk(action->rewrite->chunk); 1436 return ret; 1437 } 1438 return 0; 1439 } 1440 case DR_ACTION_TYP_INSERT_HDR: 1441 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, 1442 MLX5_REFORMAT_TYPE_INSERT_HDR, 1443 reformat_param_0, 1444 reformat_param_1, 1445 data_sz, data, 1446 &reformat_id); 1447 if (ret) 1448 return ret; 1449 1450 action->reformat->id = reformat_id; 1451 action->reformat->size = data_sz; 1452 action->reformat->param_0 = reformat_param_0; 1453 action->reformat->param_1 = reformat_param_1; 1454 return 0; 1455 case DR_ACTION_TYP_REMOVE_HDR: 1456 action->reformat->id = 0; 1457 action->reformat->size = data_sz; 1458 action->reformat->param_0 = reformat_param_0; 1459 action->reformat->param_1 = reformat_param_1; 1460 return 0; 1461 default: 1462 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type); 1463 return -EINVAL; 1464 } 1465 } 1466 1467 #define CVLAN_ETHERTYPE 0x8100 1468 #define SVLAN_ETHERTYPE 0x88a8 1469 1470 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void) 1471 { 1472 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN); 1473 } 1474 1475 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn, 1476 __be32 vlan_hdr) 1477 { 1478 u32 vlan_hdr_h = ntohl(vlan_hdr); 1479 u16 ethertype = vlan_hdr_h >> 16; 1480 struct mlx5dr_action *action; 1481 1482 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) { 1483 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n"); 1484 return NULL; 1485 } 1486 1487 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN); 1488 if (!action) 1489 return NULL; 1490 1491 action->push_vlan->vlan_hdr = vlan_hdr_h; 1492 return action; 1493 } 1494 1495 struct mlx5dr_action * 1496 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn, 1497 enum mlx5dr_action_reformat_type reformat_type, 1498 u8 reformat_param_0, 1499 u8 reformat_param_1, 1500 size_t data_sz, 1501 void *data) 1502 { 1503 enum mlx5dr_action_type action_type; 1504 struct mlx5dr_action *action; 1505 int ret; 1506 1507 refcount_inc(&dmn->refcount); 1508 1509 /* General checks */ 1510 ret = dr_action_reformat_to_action_type(reformat_type, &action_type); 1511 if (ret) { 1512 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n"); 1513 goto dec_ref; 1514 } 1515 1516 ret = dr_action_verify_reformat_params(action_type, dmn, 1517 reformat_param_0, reformat_param_1, 1518 data_sz, data); 1519 if (ret) 1520 goto dec_ref; 1521 1522 action = dr_action_create_generic(action_type); 1523 if (!action) 1524 goto dec_ref; 1525 1526 action->reformat->dmn = dmn; 1527 1528 ret = dr_action_create_reformat_action(dmn, 1529 reformat_param_0, 1530 reformat_param_1, 1531 data_sz, 1532 data, 1533 action); 1534 if (ret) { 1535 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret); 1536 goto free_action; 1537 } 1538 1539 return action; 1540 1541 free_action: 1542 kfree(action); 1543 dec_ref: 1544 refcount_dec(&dmn->refcount); 1545 return NULL; 1546 } 1547 1548 static int 1549 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn, 1550 __be64 *sw_action, 1551 __be64 *hw_action, 1552 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1553 { 1554 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1555 u8 max_length; 1556 u16 sw_field; 1557 u32 data; 1558 1559 /* Get SW modify action data */ 1560 sw_field = MLX5_GET(set_action_in, sw_action, field); 1561 data = MLX5_GET(set_action_in, sw_action, data); 1562 1563 /* Convert SW data to HW modify action format */ 1564 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1565 if (!hw_action_info) { 1566 mlx5dr_dbg(dmn, "Modify add action invalid field given\n"); 1567 return -EINVAL; 1568 } 1569 1570 max_length = hw_action_info->end - hw_action_info->start + 1; 1571 1572 mlx5dr_ste_set_action_add(dmn->ste_ctx, 1573 hw_action, 1574 hw_action_info->hw_field, 1575 hw_action_info->start, 1576 max_length, 1577 data); 1578 1579 *ret_hw_info = hw_action_info; 1580 1581 return 0; 1582 } 1583 1584 static int 1585 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn, 1586 __be64 *sw_action, 1587 __be64 *hw_action, 1588 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1589 { 1590 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1591 u8 offset, length, max_length; 1592 u16 sw_field; 1593 u32 data; 1594 1595 /* Get SW modify action data */ 1596 length = MLX5_GET(set_action_in, sw_action, length); 1597 offset = MLX5_GET(set_action_in, sw_action, offset); 1598 sw_field = MLX5_GET(set_action_in, sw_action, field); 1599 data = MLX5_GET(set_action_in, sw_action, data); 1600 1601 /* Convert SW data to HW modify action format */ 1602 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1603 if (!hw_action_info) { 1604 mlx5dr_dbg(dmn, "Modify set action invalid field given\n"); 1605 return -EINVAL; 1606 } 1607 1608 /* PRM defines that length zero specific length of 32bits */ 1609 length = length ? length : 32; 1610 1611 max_length = hw_action_info->end - hw_action_info->start + 1; 1612 1613 if (length + offset > max_length) { 1614 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1615 return -EINVAL; 1616 } 1617 1618 mlx5dr_ste_set_action_set(dmn->ste_ctx, 1619 hw_action, 1620 hw_action_info->hw_field, 1621 hw_action_info->start + offset, 1622 length, 1623 data); 1624 1625 *ret_hw_info = hw_action_info; 1626 1627 return 0; 1628 } 1629 1630 static int 1631 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn, 1632 __be64 *sw_action, 1633 __be64 *hw_action, 1634 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1635 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1636 { 1637 u8 src_offset, dst_offset, src_max_length, dst_max_length, length; 1638 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1639 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1640 u16 src_field, dst_field; 1641 1642 /* Get SW modify action data */ 1643 src_field = MLX5_GET(copy_action_in, sw_action, src_field); 1644 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field); 1645 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset); 1646 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset); 1647 length = MLX5_GET(copy_action_in, sw_action, length); 1648 1649 /* Convert SW data to HW modify action format */ 1650 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field); 1651 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field); 1652 if (!hw_src_action_info || !hw_dst_action_info) { 1653 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n"); 1654 return -EINVAL; 1655 } 1656 1657 /* PRM defines that length zero specific length of 32bits */ 1658 length = length ? length : 32; 1659 1660 src_max_length = hw_src_action_info->end - 1661 hw_src_action_info->start + 1; 1662 dst_max_length = hw_dst_action_info->end - 1663 hw_dst_action_info->start + 1; 1664 1665 if (length + src_offset > src_max_length || 1666 length + dst_offset > dst_max_length) { 1667 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1668 return -EINVAL; 1669 } 1670 1671 mlx5dr_ste_set_action_copy(dmn->ste_ctx, 1672 hw_action, 1673 hw_dst_action_info->hw_field, 1674 hw_dst_action_info->start + dst_offset, 1675 length, 1676 hw_src_action_info->hw_field, 1677 hw_src_action_info->start + src_offset); 1678 1679 *ret_dst_hw_info = hw_dst_action_info; 1680 *ret_src_hw_info = hw_src_action_info; 1681 1682 return 0; 1683 } 1684 1685 static int 1686 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn, 1687 __be64 *sw_action, 1688 __be64 *hw_action, 1689 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1690 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1691 { 1692 u8 action; 1693 int ret; 1694 1695 *hw_action = 0; 1696 *ret_src_hw_info = NULL; 1697 1698 /* Get SW modify action type */ 1699 action = MLX5_GET(set_action_in, sw_action, action_type); 1700 1701 switch (action) { 1702 case MLX5_ACTION_TYPE_SET: 1703 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action, 1704 hw_action, 1705 ret_dst_hw_info); 1706 break; 1707 1708 case MLX5_ACTION_TYPE_ADD: 1709 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action, 1710 hw_action, 1711 ret_dst_hw_info); 1712 break; 1713 1714 case MLX5_ACTION_TYPE_COPY: 1715 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action, 1716 hw_action, 1717 ret_dst_hw_info, 1718 ret_src_hw_info); 1719 break; 1720 1721 default: 1722 mlx5dr_info(dmn, "Unsupported action_type for modify action\n"); 1723 ret = -EOPNOTSUPP; 1724 } 1725 1726 return ret; 1727 } 1728 1729 static int 1730 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action, 1731 const __be64 *sw_action) 1732 { 1733 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1734 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1735 1736 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1737 action->rewrite->allow_rx = 0; 1738 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1739 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1740 sw_field); 1741 return -EINVAL; 1742 } 1743 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1744 action->rewrite->allow_tx = 0; 1745 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1746 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1747 sw_field); 1748 return -EINVAL; 1749 } 1750 } 1751 1752 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1753 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n"); 1754 return -EINVAL; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int 1761 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action, 1762 const __be64 *sw_action) 1763 { 1764 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1765 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1766 1767 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL && 1768 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT && 1769 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM && 1770 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) { 1771 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", 1772 sw_field); 1773 return -EINVAL; 1774 } 1775 1776 return 0; 1777 } 1778 1779 static int 1780 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action, 1781 const __be64 *sw_action) 1782 { 1783 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1784 u16 sw_fields[2]; 1785 int i; 1786 1787 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field); 1788 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field); 1789 1790 for (i = 0; i < 2; i++) { 1791 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1792 action->rewrite->allow_rx = 0; 1793 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1794 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1795 sw_fields[i]); 1796 return -EINVAL; 1797 } 1798 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1799 action->rewrite->allow_tx = 0; 1800 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1801 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1802 sw_fields[i]); 1803 return -EINVAL; 1804 } 1805 } 1806 } 1807 1808 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1809 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n"); 1810 return -EINVAL; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int 1817 dr_action_modify_check_field_limitation(struct mlx5dr_action *action, 1818 const __be64 *sw_action) 1819 { 1820 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1821 u8 action_type; 1822 int ret; 1823 1824 action_type = MLX5_GET(set_action_in, sw_action, action_type); 1825 1826 switch (action_type) { 1827 case MLX5_ACTION_TYPE_SET: 1828 ret = dr_action_modify_check_set_field_limitation(action, 1829 sw_action); 1830 break; 1831 1832 case MLX5_ACTION_TYPE_ADD: 1833 ret = dr_action_modify_check_add_field_limitation(action, 1834 sw_action); 1835 break; 1836 1837 case MLX5_ACTION_TYPE_COPY: 1838 ret = dr_action_modify_check_copy_field_limitation(action, 1839 sw_action); 1840 break; 1841 1842 default: 1843 mlx5dr_info(dmn, "Unsupported action %d modify action\n", 1844 action_type); 1845 ret = -EOPNOTSUPP; 1846 } 1847 1848 return ret; 1849 } 1850 1851 static bool 1852 dr_action_modify_check_is_ttl_modify(const void *sw_action) 1853 { 1854 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1855 1856 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL; 1857 } 1858 1859 static int dr_actions_convert_modify_header(struct mlx5dr_action *action, 1860 u32 max_hw_actions, 1861 u32 num_sw_actions, 1862 __be64 sw_actions[], 1863 __be64 hw_actions[], 1864 u32 *num_hw_actions, 1865 bool *modify_ttl) 1866 { 1867 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1868 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1869 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1870 __be64 *modify_ttl_sw_action = NULL; 1871 int ret, i, hw_idx = 0; 1872 __be64 *sw_action; 1873 __be64 hw_action; 1874 u16 hw_field = 0; 1875 u32 l3_type = 0; 1876 u32 l4_type = 0; 1877 1878 *modify_ttl = false; 1879 1880 action->rewrite->allow_rx = 1; 1881 action->rewrite->allow_tx = 1; 1882 1883 for (i = 0; i < num_sw_actions || modify_ttl_sw_action; i++) { 1884 /* modify TTL is handled separately, as a last action */ 1885 if (i == num_sw_actions) { 1886 sw_action = modify_ttl_sw_action; 1887 modify_ttl_sw_action = NULL; 1888 } else { 1889 sw_action = &sw_actions[i]; 1890 } 1891 1892 ret = dr_action_modify_check_field_limitation(action, 1893 sw_action); 1894 if (ret) 1895 return ret; 1896 1897 if (!(*modify_ttl) && 1898 dr_action_modify_check_is_ttl_modify(sw_action)) { 1899 modify_ttl_sw_action = sw_action; 1900 *modify_ttl = true; 1901 continue; 1902 } 1903 1904 /* Convert SW action to HW action */ 1905 ret = dr_action_modify_sw_to_hw(dmn, 1906 sw_action, 1907 &hw_action, 1908 &hw_dst_action_info, 1909 &hw_src_action_info); 1910 if (ret) 1911 return ret; 1912 1913 /* Due to a HW limitation we cannot modify 2 different L3 types */ 1914 if (l3_type && hw_dst_action_info->l3_type && 1915 hw_dst_action_info->l3_type != l3_type) { 1916 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n"); 1917 return -EINVAL; 1918 } 1919 if (hw_dst_action_info->l3_type) 1920 l3_type = hw_dst_action_info->l3_type; 1921 1922 /* Due to a HW limitation we cannot modify two different L4 types */ 1923 if (l4_type && hw_dst_action_info->l4_type && 1924 hw_dst_action_info->l4_type != l4_type) { 1925 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n"); 1926 return -EINVAL; 1927 } 1928 if (hw_dst_action_info->l4_type) 1929 l4_type = hw_dst_action_info->l4_type; 1930 1931 /* HW reads and executes two actions at once this means we 1932 * need to create a gap if two actions access the same field 1933 */ 1934 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field || 1935 (hw_src_action_info && 1936 hw_field == hw_src_action_info->hw_field))) { 1937 /* Check if after gap insertion the total number of HW 1938 * modify actions doesn't exceeds the limit 1939 */ 1940 hw_idx++; 1941 if (hw_idx >= max_hw_actions) { 1942 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n"); 1943 return -EINVAL; 1944 } 1945 } 1946 hw_field = hw_dst_action_info->hw_field; 1947 1948 hw_actions[hw_idx] = hw_action; 1949 hw_idx++; 1950 } 1951 1952 /* if the resulting HW actions list is empty, add NOP action */ 1953 if (!hw_idx) 1954 hw_idx++; 1955 1956 *num_hw_actions = hw_idx; 1957 1958 return 0; 1959 } 1960 1961 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn, 1962 size_t actions_sz, 1963 __be64 actions[], 1964 struct mlx5dr_action *action) 1965 { 1966 struct mlx5dr_icm_chunk *chunk; 1967 u32 max_hw_actions; 1968 u32 num_hw_actions; 1969 u32 num_sw_actions; 1970 __be64 *hw_actions; 1971 bool modify_ttl; 1972 int ret; 1973 1974 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE; 1975 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16); 1976 1977 if (num_sw_actions > max_hw_actions) { 1978 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n", 1979 num_sw_actions, max_hw_actions); 1980 return -EINVAL; 1981 } 1982 1983 chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16); 1984 if (!chunk) 1985 return -ENOMEM; 1986 1987 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL); 1988 if (!hw_actions) { 1989 ret = -ENOMEM; 1990 goto free_chunk; 1991 } 1992 1993 ret = dr_actions_convert_modify_header(action, 1994 max_hw_actions, 1995 num_sw_actions, 1996 actions, 1997 hw_actions, 1998 &num_hw_actions, 1999 &modify_ttl); 2000 if (ret) 2001 goto free_hw_actions; 2002 2003 action->rewrite->chunk = chunk; 2004 action->rewrite->modify_ttl = modify_ttl; 2005 action->rewrite->data = (u8 *)hw_actions; 2006 action->rewrite->num_of_actions = num_hw_actions; 2007 action->rewrite->index = (mlx5dr_icm_pool_get_chunk_icm_addr(chunk) - 2008 dmn->info.caps.hdr_modify_icm_addr) / 2009 ACTION_CACHE_LINE_SIZE; 2010 2011 ret = mlx5dr_send_postsend_action(dmn, action); 2012 if (ret) 2013 goto free_hw_actions; 2014 2015 return 0; 2016 2017 free_hw_actions: 2018 kfree(hw_actions); 2019 free_chunk: 2020 mlx5dr_icm_free_chunk(chunk); 2021 return ret; 2022 } 2023 2024 struct mlx5dr_action * 2025 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn, 2026 u32 flags, 2027 size_t actions_sz, 2028 __be64 actions[]) 2029 { 2030 struct mlx5dr_action *action; 2031 int ret = 0; 2032 2033 refcount_inc(&dmn->refcount); 2034 2035 if (actions_sz % DR_MODIFY_ACTION_SIZE) { 2036 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n"); 2037 goto dec_ref; 2038 } 2039 2040 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR); 2041 if (!action) 2042 goto dec_ref; 2043 2044 action->rewrite->dmn = dmn; 2045 2046 ret = dr_action_create_modify_action(dmn, 2047 actions_sz, 2048 actions, 2049 action); 2050 if (ret) { 2051 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret); 2052 goto free_action; 2053 } 2054 2055 return action; 2056 2057 free_action: 2058 kfree(action); 2059 dec_ref: 2060 refcount_dec(&dmn->refcount); 2061 return NULL; 2062 } 2063 2064 struct mlx5dr_action * 2065 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn, 2066 u16 vport, u8 vhca_id_valid, 2067 u16 vhca_id) 2068 { 2069 struct mlx5dr_cmd_vport_cap *vport_cap; 2070 struct mlx5dr_domain *vport_dmn; 2071 struct mlx5dr_action *action; 2072 u8 peer_vport; 2073 2074 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi); 2075 vport_dmn = peer_vport ? dmn->peer_dmn : dmn; 2076 if (!vport_dmn) { 2077 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n"); 2078 return NULL; 2079 } 2080 2081 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 2082 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n"); 2083 return NULL; 2084 } 2085 2086 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport); 2087 if (!vport_cap) { 2088 mlx5dr_err(dmn, 2089 "Failed to get vport 0x%x caps - vport is disabled or invalid\n", 2090 vport); 2091 return NULL; 2092 } 2093 2094 action = dr_action_create_generic(DR_ACTION_TYP_VPORT); 2095 if (!action) 2096 return NULL; 2097 2098 action->vport->dmn = vport_dmn; 2099 action->vport->caps = vport_cap; 2100 2101 return action; 2102 } 2103 2104 struct mlx5dr_action * 2105 mlx5dr_action_create_aso(struct mlx5dr_domain *dmn, u32 obj_id, 2106 u8 dest_reg_id, u8 aso_type, 2107 u8 init_color, u8 meter_id) 2108 { 2109 struct mlx5dr_action *action; 2110 2111 if (aso_type != MLX5_EXE_ASO_FLOW_METER) 2112 return NULL; 2113 2114 if (init_color > MLX5_FLOW_METER_COLOR_UNDEFINED) 2115 return NULL; 2116 2117 action = dr_action_create_generic(DR_ACTION_TYP_ASO_FLOW_METER); 2118 if (!action) 2119 return NULL; 2120 2121 action->aso->obj_id = obj_id; 2122 action->aso->offset = meter_id; 2123 action->aso->dest_reg_id = dest_reg_id; 2124 action->aso->init_color = init_color; 2125 action->aso->dmn = dmn; 2126 2127 refcount_inc(&dmn->refcount); 2128 2129 return action; 2130 } 2131 2132 int mlx5dr_action_destroy(struct mlx5dr_action *action) 2133 { 2134 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1)) 2135 return -EBUSY; 2136 2137 switch (action->action_type) { 2138 case DR_ACTION_TYP_FT: 2139 if (action->dest_tbl->is_fw_tbl) 2140 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount); 2141 else 2142 refcount_dec(&action->dest_tbl->tbl->refcount); 2143 2144 if (action->dest_tbl->is_fw_tbl && 2145 action->dest_tbl->fw_tbl.num_of_ref_actions) { 2146 struct mlx5dr_action **ref_actions; 2147 int i; 2148 2149 ref_actions = action->dest_tbl->fw_tbl.ref_actions; 2150 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++) 2151 refcount_dec(&ref_actions[i]->refcount); 2152 2153 kfree(ref_actions); 2154 2155 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn, 2156 action->dest_tbl->fw_tbl.id, 2157 action->dest_tbl->fw_tbl.group_id); 2158 } 2159 break; 2160 case DR_ACTION_TYP_TNL_L2_TO_L2: 2161 case DR_ACTION_TYP_REMOVE_HDR: 2162 refcount_dec(&action->reformat->dmn->refcount); 2163 break; 2164 case DR_ACTION_TYP_TNL_L3_TO_L2: 2165 mlx5dr_icm_free_chunk(action->rewrite->chunk); 2166 refcount_dec(&action->rewrite->dmn->refcount); 2167 break; 2168 case DR_ACTION_TYP_L2_TO_TNL_L2: 2169 case DR_ACTION_TYP_L2_TO_TNL_L3: 2170 case DR_ACTION_TYP_INSERT_HDR: 2171 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev, 2172 action->reformat->id); 2173 refcount_dec(&action->reformat->dmn->refcount); 2174 break; 2175 case DR_ACTION_TYP_MODIFY_HDR: 2176 mlx5dr_icm_free_chunk(action->rewrite->chunk); 2177 kfree(action->rewrite->data); 2178 refcount_dec(&action->rewrite->dmn->refcount); 2179 break; 2180 case DR_ACTION_TYP_SAMPLER: 2181 refcount_dec(&action->sampler->dmn->refcount); 2182 break; 2183 case DR_ACTION_TYP_ASO_FLOW_METER: 2184 refcount_dec(&action->aso->dmn->refcount); 2185 break; 2186 case DR_ACTION_TYP_RANGE: 2187 dr_action_destroy_range_definer(action); 2188 mlx5dr_action_destroy(action->range->miss_tbl_action); 2189 mlx5dr_action_destroy(action->range->hit_tbl_action); 2190 break; 2191 default: 2192 break; 2193 } 2194 2195 kfree(action); 2196 return 0; 2197 } 2198