1 /* 2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/mlx5/driver.h> 36 #include "mlx5_core.h" 37 38 /* Scheduling element fw management */ 39 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 40 void *ctx, u32 *element_id) 41 { 42 u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {}; 43 u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {}; 44 void *schedc; 45 int err; 46 47 schedc = MLX5_ADDR_OF(create_scheduling_element_in, in, 48 scheduling_context); 49 MLX5_SET(create_scheduling_element_in, in, opcode, 50 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT); 51 MLX5_SET(create_scheduling_element_in, in, scheduling_hierarchy, 52 hierarchy); 53 memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context)); 54 55 err = mlx5_cmd_exec_inout(dev, create_scheduling_element, in, out); 56 if (err) 57 return err; 58 59 *element_id = MLX5_GET(create_scheduling_element_out, out, 60 scheduling_element_id); 61 return 0; 62 } 63 64 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 65 void *ctx, u32 element_id, 66 u32 modify_bitmask) 67 { 68 u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {}; 69 void *schedc; 70 71 schedc = MLX5_ADDR_OF(modify_scheduling_element_in, in, 72 scheduling_context); 73 MLX5_SET(modify_scheduling_element_in, in, opcode, 74 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT); 75 MLX5_SET(modify_scheduling_element_in, in, scheduling_element_id, 76 element_id); 77 MLX5_SET(modify_scheduling_element_in, in, modify_bitmask, 78 modify_bitmask); 79 MLX5_SET(modify_scheduling_element_in, in, scheduling_hierarchy, 80 hierarchy); 81 memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context)); 82 83 return mlx5_cmd_exec_in(dev, modify_scheduling_element, in); 84 } 85 86 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 87 u32 element_id) 88 { 89 u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {}; 90 91 MLX5_SET(destroy_scheduling_element_in, in, opcode, 92 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT); 93 MLX5_SET(destroy_scheduling_element_in, in, scheduling_element_id, 94 element_id); 95 MLX5_SET(destroy_scheduling_element_in, in, scheduling_hierarchy, 96 hierarchy); 97 98 return mlx5_cmd_exec_in(dev, destroy_scheduling_element, in); 99 } 100 101 static bool mlx5_rl_are_equal_raw(struct mlx5_rl_entry *entry, void *rl_in, 102 u16 uid) 103 { 104 return (!memcmp(entry->rl_raw, rl_in, sizeof(entry->rl_raw)) && 105 entry->uid == uid); 106 } 107 108 /* Finds an entry where we can register the given rate 109 * If the rate already exists, return the entry where it is registered, 110 * otherwise return the first available entry. 111 * If the table is full, return NULL 112 */ 113 static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table, 114 void *rl_in, u16 uid, bool dedicated) 115 { 116 struct mlx5_rl_entry *ret_entry = NULL; 117 bool empty_found = false; 118 int i; 119 120 for (i = 0; i < table->max_size; i++) { 121 if (dedicated) { 122 if (!table->rl_entry[i].refcount) 123 return &table->rl_entry[i]; 124 continue; 125 } 126 127 if (table->rl_entry[i].refcount) { 128 if (table->rl_entry[i].dedicated) 129 continue; 130 if (mlx5_rl_are_equal_raw(&table->rl_entry[i], rl_in, 131 uid)) 132 return &table->rl_entry[i]; 133 } else if (!empty_found) { 134 empty_found = true; 135 ret_entry = &table->rl_entry[i]; 136 } 137 } 138 139 return ret_entry; 140 } 141 142 static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev, 143 struct mlx5_rl_entry *entry, bool set) 144 { 145 u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {}; 146 void *pp_context; 147 148 pp_context = MLX5_ADDR_OF(set_pp_rate_limit_in, in, ctx); 149 MLX5_SET(set_pp_rate_limit_in, in, opcode, 150 MLX5_CMD_OP_SET_PP_RATE_LIMIT); 151 MLX5_SET(set_pp_rate_limit_in, in, uid, entry->uid); 152 MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, entry->index); 153 if (set) 154 memcpy(pp_context, entry->rl_raw, sizeof(entry->rl_raw)); 155 return mlx5_cmd_exec_in(dev, set_pp_rate_limit, in); 156 } 157 158 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate) 159 { 160 struct mlx5_rl_table *table = &dev->priv.rl_table; 161 162 return (rate <= table->max_rate && rate >= table->min_rate); 163 } 164 EXPORT_SYMBOL(mlx5_rl_is_in_range); 165 166 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 167 struct mlx5_rate_limit *rl_1) 168 { 169 return ((rl_0->rate == rl_1->rate) && 170 (rl_0->max_burst_sz == rl_1->max_burst_sz) && 171 (rl_0->typical_pkt_sz == rl_1->typical_pkt_sz)); 172 } 173 EXPORT_SYMBOL(mlx5_rl_are_equal); 174 175 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, 176 bool dedicated_entry, u16 *index) 177 { 178 struct mlx5_rl_table *table = &dev->priv.rl_table; 179 struct mlx5_rl_entry *entry; 180 int err = 0; 181 u32 rate; 182 183 rate = MLX5_GET(set_pp_rate_limit_context, rl_in, rate_limit); 184 mutex_lock(&table->rl_lock); 185 186 if (!rate || !mlx5_rl_is_in_range(dev, rate)) { 187 mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n", 188 rate, table->min_rate, table->max_rate); 189 err = -EINVAL; 190 goto out; 191 } 192 193 entry = find_rl_entry(table, rl_in, uid, dedicated_entry); 194 if (!entry) { 195 mlx5_core_err(dev, "Max number of %u rates reached\n", 196 table->max_size); 197 err = -ENOSPC; 198 goto out; 199 } 200 if (entry->refcount) { 201 /* rate already configured */ 202 entry->refcount++; 203 } else { 204 memcpy(entry->rl_raw, rl_in, sizeof(entry->rl_raw)); 205 entry->uid = uid; 206 /* new rate limit */ 207 err = mlx5_set_pp_rate_limit_cmd(dev, entry, true); 208 if (err) { 209 mlx5_core_err( 210 dev, 211 "Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 212 err, rate, 213 MLX5_GET(set_pp_rate_limit_context, rl_in, 214 burst_upper_bound), 215 MLX5_GET(set_pp_rate_limit_context, rl_in, 216 typical_packet_size)); 217 goto out; 218 } 219 220 entry->refcount = 1; 221 entry->dedicated = dedicated_entry; 222 } 223 *index = entry->index; 224 225 out: 226 mutex_unlock(&table->rl_lock); 227 return err; 228 } 229 EXPORT_SYMBOL(mlx5_rl_add_rate_raw); 230 231 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index) 232 { 233 struct mlx5_rl_table *table = &dev->priv.rl_table; 234 struct mlx5_rl_entry *entry; 235 236 mutex_lock(&table->rl_lock); 237 entry = &table->rl_entry[index - 1]; 238 entry->refcount--; 239 if (!entry->refcount) 240 /* need to remove rate */ 241 mlx5_set_pp_rate_limit_cmd(dev, entry, false); 242 mutex_unlock(&table->rl_lock); 243 } 244 EXPORT_SYMBOL(mlx5_rl_remove_rate_raw); 245 246 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 247 struct mlx5_rate_limit *rl) 248 { 249 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {}; 250 251 MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate); 252 MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound, 253 rl->max_burst_sz); 254 MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size, 255 rl->typical_pkt_sz); 256 257 return mlx5_rl_add_rate_raw(dev, rl_raw, 258 MLX5_CAP_QOS(dev, packet_pacing_uid) ? 259 MLX5_SHARED_RESOURCE_UID : 0, 260 false, index); 261 } 262 EXPORT_SYMBOL(mlx5_rl_add_rate); 263 264 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl) 265 { 266 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {}; 267 struct mlx5_rl_table *table = &dev->priv.rl_table; 268 struct mlx5_rl_entry *entry = NULL; 269 270 /* 0 is a reserved value for unlimited rate */ 271 if (rl->rate == 0) 272 return; 273 274 MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate); 275 MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound, 276 rl->max_burst_sz); 277 MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size, 278 rl->typical_pkt_sz); 279 280 mutex_lock(&table->rl_lock); 281 entry = find_rl_entry(table, rl_raw, 282 MLX5_CAP_QOS(dev, packet_pacing_uid) ? 283 MLX5_SHARED_RESOURCE_UID : 0, false); 284 if (!entry || !entry->refcount) { 285 mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u are not configured\n", 286 rl->rate, rl->max_burst_sz, rl->typical_pkt_sz); 287 goto out; 288 } 289 290 entry->refcount--; 291 if (!entry->refcount) 292 /* need to remove rate */ 293 mlx5_set_pp_rate_limit_cmd(dev, entry, false); 294 295 out: 296 mutex_unlock(&table->rl_lock); 297 } 298 EXPORT_SYMBOL(mlx5_rl_remove_rate); 299 300 int mlx5_init_rl_table(struct mlx5_core_dev *dev) 301 { 302 struct mlx5_rl_table *table = &dev->priv.rl_table; 303 int i; 304 305 mutex_init(&table->rl_lock); 306 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) { 307 table->max_size = 0; 308 return 0; 309 } 310 311 /* First entry is reserved for unlimited rate */ 312 table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1; 313 table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate); 314 table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate); 315 316 table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry), 317 GFP_KERNEL); 318 if (!table->rl_entry) 319 return -ENOMEM; 320 321 /* The index represents the index in HW rate limit table 322 * Index 0 is reserved for unlimited rate 323 */ 324 for (i = 0; i < table->max_size; i++) 325 table->rl_entry[i].index = i + 1; 326 327 /* Index 0 is reserved */ 328 mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n", 329 table->max_size, 330 table->min_rate >> 10, 331 table->max_rate >> 10); 332 333 return 0; 334 } 335 336 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev) 337 { 338 struct mlx5_rl_table *table = &dev->priv.rl_table; 339 int i; 340 341 /* Clear all configured rates */ 342 for (i = 0; i < table->max_size; i++) 343 if (table->rl_entry[i].refcount) 344 mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i], 345 false); 346 347 kfree(dev->priv.rl_table.rl_entry); 348 } 349